1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include <linux/iopoll.h> 6 #include <net/rtnetlink.h> 7 #include "hclgevf_cmd.h" 8 #include "hclgevf_main.h" 9 #include "hclge_mbx.h" 10 #include "hnae3.h" 11 12 #define HCLGEVF_NAME "hclgevf" 13 14 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 15 static struct hnae3_ae_algo ae_algovf; 16 17 static const struct pci_device_id ae_algovf_pci_tbl[] = { 18 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 19 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 20 /* required last entry */ 21 {0, } 22 }; 23 24 static const u8 hclgevf_hash_key[] = { 25 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 26 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 27 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 28 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 29 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 30 }; 31 32 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 33 34 static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 35 HCLGEVF_CMDQ_TX_ADDR_H_REG, 36 HCLGEVF_CMDQ_TX_DEPTH_REG, 37 HCLGEVF_CMDQ_TX_TAIL_REG, 38 HCLGEVF_CMDQ_TX_HEAD_REG, 39 HCLGEVF_CMDQ_RX_ADDR_L_REG, 40 HCLGEVF_CMDQ_RX_ADDR_H_REG, 41 HCLGEVF_CMDQ_RX_DEPTH_REG, 42 HCLGEVF_CMDQ_RX_TAIL_REG, 43 HCLGEVF_CMDQ_RX_HEAD_REG, 44 HCLGEVF_VECTOR0_CMDQ_SRC_REG, 45 HCLGEVF_CMDQ_INTR_STS_REG, 46 HCLGEVF_CMDQ_INTR_EN_REG, 47 HCLGEVF_CMDQ_INTR_GEN_REG}; 48 49 static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 50 HCLGEVF_RST_ING, 51 HCLGEVF_GRO_EN_REG}; 52 53 static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 54 HCLGEVF_RING_RX_ADDR_H_REG, 55 HCLGEVF_RING_RX_BD_NUM_REG, 56 HCLGEVF_RING_RX_BD_LENGTH_REG, 57 HCLGEVF_RING_RX_MERGE_EN_REG, 58 HCLGEVF_RING_RX_TAIL_REG, 59 HCLGEVF_RING_RX_HEAD_REG, 60 HCLGEVF_RING_RX_FBD_NUM_REG, 61 HCLGEVF_RING_RX_OFFSET_REG, 62 HCLGEVF_RING_RX_FBD_OFFSET_REG, 63 HCLGEVF_RING_RX_STASH_REG, 64 HCLGEVF_RING_RX_BD_ERR_REG, 65 HCLGEVF_RING_TX_ADDR_L_REG, 66 HCLGEVF_RING_TX_ADDR_H_REG, 67 HCLGEVF_RING_TX_BD_NUM_REG, 68 HCLGEVF_RING_TX_PRIORITY_REG, 69 HCLGEVF_RING_TX_TC_REG, 70 HCLGEVF_RING_TX_MERGE_EN_REG, 71 HCLGEVF_RING_TX_TAIL_REG, 72 HCLGEVF_RING_TX_HEAD_REG, 73 HCLGEVF_RING_TX_FBD_NUM_REG, 74 HCLGEVF_RING_TX_OFFSET_REG, 75 HCLGEVF_RING_TX_EBD_NUM_REG, 76 HCLGEVF_RING_TX_EBD_OFFSET_REG, 77 HCLGEVF_RING_TX_BD_ERR_REG, 78 HCLGEVF_RING_EN_REG}; 79 80 static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 81 HCLGEVF_TQP_INTR_GL0_REG, 82 HCLGEVF_TQP_INTR_GL1_REG, 83 HCLGEVF_TQP_INTR_GL2_REG, 84 HCLGEVF_TQP_INTR_RL_REG}; 85 86 static inline struct hclgevf_dev *hclgevf_ae_get_hdev( 87 struct hnae3_handle *handle) 88 { 89 if (!handle->client) 90 return container_of(handle, struct hclgevf_dev, nic); 91 else if (handle->client->type == HNAE3_CLIENT_ROCE) 92 return container_of(handle, struct hclgevf_dev, roce); 93 else 94 return container_of(handle, struct hclgevf_dev, nic); 95 } 96 97 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 98 { 99 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 100 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 101 struct hclgevf_desc desc; 102 struct hclgevf_tqp *tqp; 103 int status; 104 int i; 105 106 for (i = 0; i < kinfo->num_tqps; i++) { 107 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 108 hclgevf_cmd_setup_basic_desc(&desc, 109 HCLGEVF_OPC_QUERY_RX_STATUS, 110 true); 111 112 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 113 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 114 if (status) { 115 dev_err(&hdev->pdev->dev, 116 "Query tqp stat fail, status = %d,queue = %d\n", 117 status, i); 118 return status; 119 } 120 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 121 le32_to_cpu(desc.data[1]); 122 123 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 124 true); 125 126 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 127 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 128 if (status) { 129 dev_err(&hdev->pdev->dev, 130 "Query tqp stat fail, status = %d,queue = %d\n", 131 status, i); 132 return status; 133 } 134 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 135 le32_to_cpu(desc.data[1]); 136 } 137 138 return 0; 139 } 140 141 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 142 { 143 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 144 struct hclgevf_tqp *tqp; 145 u64 *buff = data; 146 int i; 147 148 for (i = 0; i < kinfo->num_tqps; i++) { 149 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 150 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 151 } 152 for (i = 0; i < kinfo->num_tqps; i++) { 153 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 154 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 155 } 156 157 return buff; 158 } 159 160 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 161 { 162 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 163 164 return kinfo->num_tqps * 2; 165 } 166 167 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 168 { 169 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 170 u8 *buff = data; 171 int i = 0; 172 173 for (i = 0; i < kinfo->num_tqps; i++) { 174 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 175 struct hclgevf_tqp, q); 176 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 177 tqp->index); 178 buff += ETH_GSTRING_LEN; 179 } 180 181 for (i = 0; i < kinfo->num_tqps; i++) { 182 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 183 struct hclgevf_tqp, q); 184 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 185 tqp->index); 186 buff += ETH_GSTRING_LEN; 187 } 188 189 return buff; 190 } 191 192 static void hclgevf_update_stats(struct hnae3_handle *handle, 193 struct net_device_stats *net_stats) 194 { 195 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 196 int status; 197 198 status = hclgevf_tqps_update_stats(handle); 199 if (status) 200 dev_err(&hdev->pdev->dev, 201 "VF update of TQPS stats fail, status = %d.\n", 202 status); 203 } 204 205 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 206 { 207 if (strset == ETH_SS_TEST) 208 return -EOPNOTSUPP; 209 else if (strset == ETH_SS_STATS) 210 return hclgevf_tqps_get_sset_count(handle, strset); 211 212 return 0; 213 } 214 215 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 216 u8 *data) 217 { 218 u8 *p = (char *)data; 219 220 if (strset == ETH_SS_STATS) 221 p = hclgevf_tqps_get_strings(handle, p); 222 } 223 224 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 225 { 226 hclgevf_tqps_get_stats(handle, data); 227 } 228 229 static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 230 { 231 u8 resp_msg; 232 int status; 233 234 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 235 true, &resp_msg, sizeof(u8)); 236 if (status) { 237 dev_err(&hdev->pdev->dev, 238 "VF request to get TC info from PF failed %d", 239 status); 240 return status; 241 } 242 243 hdev->hw_tc_map = resp_msg; 244 245 return 0; 246 } 247 248 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 249 { 250 struct hnae3_handle *nic = &hdev->nic; 251 u8 resp_msg; 252 int ret; 253 254 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 255 HCLGE_MBX_GET_PORT_BASE_VLAN_STATE, 256 NULL, 0, true, &resp_msg, sizeof(u8)); 257 if (ret) { 258 dev_err(&hdev->pdev->dev, 259 "VF request to get port based vlan state failed %d", 260 ret); 261 return ret; 262 } 263 264 nic->port_base_vlan_state = resp_msg; 265 266 return 0; 267 } 268 269 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 270 { 271 #define HCLGEVF_TQPS_RSS_INFO_LEN 6 272 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 273 int status; 274 275 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 276 true, resp_msg, 277 HCLGEVF_TQPS_RSS_INFO_LEN); 278 if (status) { 279 dev_err(&hdev->pdev->dev, 280 "VF request to get tqp info from PF failed %d", 281 status); 282 return status; 283 } 284 285 memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 286 memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 287 memcpy(&hdev->rx_buf_len, &resp_msg[4], sizeof(u16)); 288 289 return 0; 290 } 291 292 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 293 { 294 #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 295 u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 296 int ret; 297 298 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QDEPTH, 0, NULL, 0, 299 true, resp_msg, 300 HCLGEVF_TQPS_DEPTH_INFO_LEN); 301 if (ret) { 302 dev_err(&hdev->pdev->dev, 303 "VF request to get tqp depth info from PF failed %d", 304 ret); 305 return ret; 306 } 307 308 memcpy(&hdev->num_tx_desc, &resp_msg[0], sizeof(u16)); 309 memcpy(&hdev->num_rx_desc, &resp_msg[2], sizeof(u16)); 310 311 return 0; 312 } 313 314 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 315 { 316 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 317 u8 msg_data[2], resp_data[2]; 318 u16 qid_in_pf = 0; 319 int ret; 320 321 memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 322 323 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data, 324 2, true, resp_data, 2); 325 if (!ret) 326 qid_in_pf = *(u16 *)resp_data; 327 328 return qid_in_pf; 329 } 330 331 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 332 { 333 u8 resp_msg[2]; 334 int ret; 335 336 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_MEDIA_TYPE, 0, NULL, 0, 337 true, resp_msg, sizeof(resp_msg)); 338 if (ret) { 339 dev_err(&hdev->pdev->dev, 340 "VF request to get the pf port media type failed %d", 341 ret); 342 return ret; 343 } 344 345 hdev->hw.mac.media_type = resp_msg[0]; 346 hdev->hw.mac.module_type = resp_msg[1]; 347 348 return 0; 349 } 350 351 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 352 { 353 struct hclgevf_tqp *tqp; 354 int i; 355 356 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 357 sizeof(struct hclgevf_tqp), GFP_KERNEL); 358 if (!hdev->htqp) 359 return -ENOMEM; 360 361 tqp = hdev->htqp; 362 363 for (i = 0; i < hdev->num_tqps; i++) { 364 tqp->dev = &hdev->pdev->dev; 365 tqp->index = i; 366 367 tqp->q.ae_algo = &ae_algovf; 368 tqp->q.buf_size = hdev->rx_buf_len; 369 tqp->q.tx_desc_num = hdev->num_tx_desc; 370 tqp->q.rx_desc_num = hdev->num_rx_desc; 371 tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 372 i * HCLGEVF_TQP_REG_SIZE; 373 374 tqp++; 375 } 376 377 return 0; 378 } 379 380 static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 381 { 382 struct hnae3_handle *nic = &hdev->nic; 383 struct hnae3_knic_private_info *kinfo; 384 u16 new_tqps = hdev->num_tqps; 385 int i; 386 387 kinfo = &nic->kinfo; 388 kinfo->num_tc = 0; 389 kinfo->num_tx_desc = hdev->num_tx_desc; 390 kinfo->num_rx_desc = hdev->num_rx_desc; 391 kinfo->rx_buf_len = hdev->rx_buf_len; 392 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 393 if (hdev->hw_tc_map & BIT(i)) 394 kinfo->num_tc++; 395 396 kinfo->rss_size 397 = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 398 new_tqps = kinfo->rss_size * kinfo->num_tc; 399 kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 400 401 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 402 sizeof(struct hnae3_queue *), GFP_KERNEL); 403 if (!kinfo->tqp) 404 return -ENOMEM; 405 406 for (i = 0; i < kinfo->num_tqps; i++) { 407 hdev->htqp[i].q.handle = &hdev->nic; 408 hdev->htqp[i].q.tqp_index = i; 409 kinfo->tqp[i] = &hdev->htqp[i].q; 410 } 411 412 return 0; 413 } 414 415 static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 416 { 417 int status; 418 u8 resp_msg; 419 420 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 421 0, false, &resp_msg, sizeof(u8)); 422 if (status) 423 dev_err(&hdev->pdev->dev, 424 "VF failed to fetch link status(%d) from PF", status); 425 } 426 427 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 428 { 429 struct hnae3_handle *rhandle = &hdev->roce; 430 struct hnae3_handle *handle = &hdev->nic; 431 struct hnae3_client *rclient; 432 struct hnae3_client *client; 433 434 client = handle->client; 435 rclient = hdev->roce_client; 436 437 link_state = 438 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 439 440 if (link_state != hdev->hw.mac.link) { 441 client->ops->link_status_change(handle, !!link_state); 442 if (rclient && rclient->ops->link_status_change) 443 rclient->ops->link_status_change(rhandle, !!link_state); 444 hdev->hw.mac.link = link_state; 445 } 446 } 447 448 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 449 { 450 #define HCLGEVF_ADVERTISING 0 451 #define HCLGEVF_SUPPORTED 1 452 u8 send_msg; 453 u8 resp_msg; 454 455 send_msg = HCLGEVF_ADVERTISING; 456 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, &send_msg, 457 sizeof(u8), false, &resp_msg, sizeof(u8)); 458 send_msg = HCLGEVF_SUPPORTED; 459 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, &send_msg, 460 sizeof(u8), false, &resp_msg, sizeof(u8)); 461 } 462 463 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 464 { 465 struct hnae3_handle *nic = &hdev->nic; 466 int ret; 467 468 nic->ae_algo = &ae_algovf; 469 nic->pdev = hdev->pdev; 470 nic->numa_node_mask = hdev->numa_node_mask; 471 nic->flags |= HNAE3_SUPPORT_VF; 472 473 ret = hclgevf_knic_setup(hdev); 474 if (ret) 475 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 476 ret); 477 return ret; 478 } 479 480 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 481 { 482 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 483 dev_warn(&hdev->pdev->dev, 484 "vector(vector_id %d) has been freed.\n", vector_id); 485 return; 486 } 487 488 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 489 hdev->num_msi_left += 1; 490 hdev->num_msi_used -= 1; 491 } 492 493 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 494 struct hnae3_vector_info *vector_info) 495 { 496 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 497 struct hnae3_vector_info *vector = vector_info; 498 int alloc = 0; 499 int i, j; 500 501 vector_num = min(hdev->num_msi_left, vector_num); 502 503 for (j = 0; j < vector_num; j++) { 504 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 505 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 506 vector->vector = pci_irq_vector(hdev->pdev, i); 507 vector->io_addr = hdev->hw.io_base + 508 HCLGEVF_VECTOR_REG_BASE + 509 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 510 hdev->vector_status[i] = 0; 511 hdev->vector_irq[i] = vector->vector; 512 513 vector++; 514 alloc++; 515 516 break; 517 } 518 } 519 } 520 hdev->num_msi_left -= alloc; 521 hdev->num_msi_used += alloc; 522 523 return alloc; 524 } 525 526 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 527 { 528 int i; 529 530 for (i = 0; i < hdev->num_msi; i++) 531 if (vector == hdev->vector_irq[i]) 532 return i; 533 534 return -EINVAL; 535 } 536 537 static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 538 const u8 hfunc, const u8 *key) 539 { 540 struct hclgevf_rss_config_cmd *req; 541 struct hclgevf_desc desc; 542 int key_offset = 0; 543 int key_counts; 544 int key_size; 545 int ret; 546 547 key_counts = HCLGEVF_RSS_KEY_SIZE; 548 req = (struct hclgevf_rss_config_cmd *)desc.data; 549 550 while (key_counts) { 551 hclgevf_cmd_setup_basic_desc(&desc, 552 HCLGEVF_OPC_RSS_GENERIC_CONFIG, 553 false); 554 555 req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 556 req->hash_config |= 557 (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 558 559 key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts); 560 memcpy(req->hash_key, 561 key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 562 563 key_counts -= key_size; 564 key_offset++; 565 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 566 if (ret) { 567 dev_err(&hdev->pdev->dev, 568 "Configure RSS config fail, status = %d\n", 569 ret); 570 return ret; 571 } 572 } 573 574 return 0; 575 } 576 577 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 578 { 579 return HCLGEVF_RSS_KEY_SIZE; 580 } 581 582 static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 583 { 584 return HCLGEVF_RSS_IND_TBL_SIZE; 585 } 586 587 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 588 { 589 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 590 struct hclgevf_rss_indirection_table_cmd *req; 591 struct hclgevf_desc desc; 592 int status; 593 int i, j; 594 595 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 596 597 for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 598 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 599 false); 600 req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 601 req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 602 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 603 req->rss_result[j] = 604 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 605 606 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 607 if (status) { 608 dev_err(&hdev->pdev->dev, 609 "VF failed(=%d) to set RSS indirection table\n", 610 status); 611 return status; 612 } 613 } 614 615 return 0; 616 } 617 618 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 619 { 620 struct hclgevf_rss_tc_mode_cmd *req; 621 u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 622 u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 623 u16 tc_size[HCLGEVF_MAX_TC_NUM]; 624 struct hclgevf_desc desc; 625 u16 roundup_size; 626 int status; 627 int i; 628 629 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 630 631 roundup_size = roundup_pow_of_two(rss_size); 632 roundup_size = ilog2(roundup_size); 633 634 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 635 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 636 tc_size[i] = roundup_size; 637 tc_offset[i] = rss_size * i; 638 } 639 640 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 641 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 642 hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 643 (tc_valid[i] & 0x1)); 644 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 645 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 646 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 647 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 648 } 649 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 650 if (status) 651 dev_err(&hdev->pdev->dev, 652 "VF failed(=%d) to set rss tc mode\n", status); 653 654 return status; 655 } 656 657 /* for revision 0x20, vf shared the same rss config with pf */ 658 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 659 { 660 #define HCLGEVF_RSS_MBX_RESP_LEN 8 661 662 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 663 u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 664 u16 msg_num, hash_key_index; 665 u8 index; 666 int ret; 667 668 msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 669 HCLGEVF_RSS_MBX_RESP_LEN; 670 for (index = 0; index < msg_num; index++) { 671 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_RSS_KEY, 0, 672 &index, sizeof(index), 673 true, resp_msg, 674 HCLGEVF_RSS_MBX_RESP_LEN); 675 if (ret) { 676 dev_err(&hdev->pdev->dev, 677 "VF get rss hash key from PF failed, ret=%d", 678 ret); 679 return ret; 680 } 681 682 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 683 if (index == msg_num - 1) 684 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 685 &resp_msg[0], 686 HCLGEVF_RSS_KEY_SIZE - hash_key_index); 687 else 688 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 689 &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 690 } 691 692 return 0; 693 } 694 695 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 696 u8 *hfunc) 697 { 698 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 699 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 700 int i, ret; 701 702 if (handle->pdev->revision >= 0x21) { 703 /* Get hash algorithm */ 704 if (hfunc) { 705 switch (rss_cfg->hash_algo) { 706 case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 707 *hfunc = ETH_RSS_HASH_TOP; 708 break; 709 case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 710 *hfunc = ETH_RSS_HASH_XOR; 711 break; 712 default: 713 *hfunc = ETH_RSS_HASH_UNKNOWN; 714 break; 715 } 716 } 717 718 /* Get the RSS Key required by the user */ 719 if (key) 720 memcpy(key, rss_cfg->rss_hash_key, 721 HCLGEVF_RSS_KEY_SIZE); 722 } else { 723 if (hfunc) 724 *hfunc = ETH_RSS_HASH_TOP; 725 if (key) { 726 ret = hclgevf_get_rss_hash_key(hdev); 727 if (ret) 728 return ret; 729 memcpy(key, rss_cfg->rss_hash_key, 730 HCLGEVF_RSS_KEY_SIZE); 731 } 732 } 733 734 if (indir) 735 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 736 indir[i] = rss_cfg->rss_indirection_tbl[i]; 737 738 return 0; 739 } 740 741 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 742 const u8 *key, const u8 hfunc) 743 { 744 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 745 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 746 int ret, i; 747 748 if (handle->pdev->revision >= 0x21) { 749 /* Set the RSS Hash Key if specififed by the user */ 750 if (key) { 751 switch (hfunc) { 752 case ETH_RSS_HASH_TOP: 753 rss_cfg->hash_algo = 754 HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 755 break; 756 case ETH_RSS_HASH_XOR: 757 rss_cfg->hash_algo = 758 HCLGEVF_RSS_HASH_ALGO_SIMPLE; 759 break; 760 case ETH_RSS_HASH_NO_CHANGE: 761 break; 762 default: 763 return -EINVAL; 764 } 765 766 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 767 key); 768 if (ret) 769 return ret; 770 771 /* Update the shadow RSS key with user specified qids */ 772 memcpy(rss_cfg->rss_hash_key, key, 773 HCLGEVF_RSS_KEY_SIZE); 774 } 775 } 776 777 /* update the shadow RSS table with user specified qids */ 778 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 779 rss_cfg->rss_indirection_tbl[i] = indir[i]; 780 781 /* update the hardware */ 782 return hclgevf_set_rss_indir_table(hdev); 783 } 784 785 static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 786 { 787 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 788 789 if (nfc->data & RXH_L4_B_2_3) 790 hash_sets |= HCLGEVF_D_PORT_BIT; 791 else 792 hash_sets &= ~HCLGEVF_D_PORT_BIT; 793 794 if (nfc->data & RXH_IP_SRC) 795 hash_sets |= HCLGEVF_S_IP_BIT; 796 else 797 hash_sets &= ~HCLGEVF_S_IP_BIT; 798 799 if (nfc->data & RXH_IP_DST) 800 hash_sets |= HCLGEVF_D_IP_BIT; 801 else 802 hash_sets &= ~HCLGEVF_D_IP_BIT; 803 804 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 805 hash_sets |= HCLGEVF_V_TAG_BIT; 806 807 return hash_sets; 808 } 809 810 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 811 struct ethtool_rxnfc *nfc) 812 { 813 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 814 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 815 struct hclgevf_rss_input_tuple_cmd *req; 816 struct hclgevf_desc desc; 817 u8 tuple_sets; 818 int ret; 819 820 if (handle->pdev->revision == 0x20) 821 return -EOPNOTSUPP; 822 823 if (nfc->data & 824 ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 825 return -EINVAL; 826 827 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 828 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 829 830 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 831 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 832 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 833 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 834 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 835 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 836 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 837 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 838 839 tuple_sets = hclgevf_get_rss_hash_bits(nfc); 840 switch (nfc->flow_type) { 841 case TCP_V4_FLOW: 842 req->ipv4_tcp_en = tuple_sets; 843 break; 844 case TCP_V6_FLOW: 845 req->ipv6_tcp_en = tuple_sets; 846 break; 847 case UDP_V4_FLOW: 848 req->ipv4_udp_en = tuple_sets; 849 break; 850 case UDP_V6_FLOW: 851 req->ipv6_udp_en = tuple_sets; 852 break; 853 case SCTP_V4_FLOW: 854 req->ipv4_sctp_en = tuple_sets; 855 break; 856 case SCTP_V6_FLOW: 857 if ((nfc->data & RXH_L4_B_0_1) || 858 (nfc->data & RXH_L4_B_2_3)) 859 return -EINVAL; 860 861 req->ipv6_sctp_en = tuple_sets; 862 break; 863 case IPV4_FLOW: 864 req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 865 break; 866 case IPV6_FLOW: 867 req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 868 break; 869 default: 870 return -EINVAL; 871 } 872 873 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 874 if (ret) { 875 dev_err(&hdev->pdev->dev, 876 "Set rss tuple fail, status = %d\n", ret); 877 return ret; 878 } 879 880 rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 881 rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 882 rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 883 rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 884 rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 885 rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 886 rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 887 rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 888 return 0; 889 } 890 891 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 892 struct ethtool_rxnfc *nfc) 893 { 894 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 895 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 896 u8 tuple_sets; 897 898 if (handle->pdev->revision == 0x20) 899 return -EOPNOTSUPP; 900 901 nfc->data = 0; 902 903 switch (nfc->flow_type) { 904 case TCP_V4_FLOW: 905 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 906 break; 907 case UDP_V4_FLOW: 908 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 909 break; 910 case TCP_V6_FLOW: 911 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 912 break; 913 case UDP_V6_FLOW: 914 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 915 break; 916 case SCTP_V4_FLOW: 917 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 918 break; 919 case SCTP_V6_FLOW: 920 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 921 break; 922 case IPV4_FLOW: 923 case IPV6_FLOW: 924 tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 925 break; 926 default: 927 return -EINVAL; 928 } 929 930 if (!tuple_sets) 931 return 0; 932 933 if (tuple_sets & HCLGEVF_D_PORT_BIT) 934 nfc->data |= RXH_L4_B_2_3; 935 if (tuple_sets & HCLGEVF_S_PORT_BIT) 936 nfc->data |= RXH_L4_B_0_1; 937 if (tuple_sets & HCLGEVF_D_IP_BIT) 938 nfc->data |= RXH_IP_DST; 939 if (tuple_sets & HCLGEVF_S_IP_BIT) 940 nfc->data |= RXH_IP_SRC; 941 942 return 0; 943 } 944 945 static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 946 struct hclgevf_rss_cfg *rss_cfg) 947 { 948 struct hclgevf_rss_input_tuple_cmd *req; 949 struct hclgevf_desc desc; 950 int ret; 951 952 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 953 954 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 955 956 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 957 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 958 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 959 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 960 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 961 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 962 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 963 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 964 965 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 966 if (ret) 967 dev_err(&hdev->pdev->dev, 968 "Configure rss input fail, status = %d\n", ret); 969 return ret; 970 } 971 972 static int hclgevf_get_tc_size(struct hnae3_handle *handle) 973 { 974 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 975 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 976 977 return rss_cfg->rss_size; 978 } 979 980 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 981 int vector_id, 982 struct hnae3_ring_chain_node *ring_chain) 983 { 984 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 985 struct hnae3_ring_chain_node *node; 986 struct hclge_mbx_vf_to_pf_cmd *req; 987 struct hclgevf_desc desc; 988 int i = 0; 989 int status; 990 u8 type; 991 992 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 993 994 for (node = ring_chain; node; node = node->next) { 995 int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 996 HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 997 998 if (i == 0) { 999 hclgevf_cmd_setup_basic_desc(&desc, 1000 HCLGEVF_OPC_MBX_VF_TO_PF, 1001 false); 1002 type = en ? 1003 HCLGE_MBX_MAP_RING_TO_VECTOR : 1004 HCLGE_MBX_UNMAP_RING_TO_VECTOR; 1005 req->msg[0] = type; 1006 req->msg[1] = vector_id; 1007 } 1008 1009 req->msg[idx_offset] = 1010 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 1011 req->msg[idx_offset + 1] = node->tqp_index; 1012 req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 1013 HNAE3_RING_GL_IDX_M, 1014 HNAE3_RING_GL_IDX_S); 1015 1016 i++; 1017 if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 1018 HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 1019 HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 1020 !node->next) { 1021 req->msg[2] = i; 1022 1023 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1024 if (status) { 1025 dev_err(&hdev->pdev->dev, 1026 "Map TQP fail, status is %d.\n", 1027 status); 1028 return status; 1029 } 1030 i = 0; 1031 hclgevf_cmd_setup_basic_desc(&desc, 1032 HCLGEVF_OPC_MBX_VF_TO_PF, 1033 false); 1034 req->msg[0] = type; 1035 req->msg[1] = vector_id; 1036 } 1037 } 1038 1039 return 0; 1040 } 1041 1042 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1043 struct hnae3_ring_chain_node *ring_chain) 1044 { 1045 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1046 int vector_id; 1047 1048 vector_id = hclgevf_get_vector_index(hdev, vector); 1049 if (vector_id < 0) { 1050 dev_err(&handle->pdev->dev, 1051 "Get vector index fail. ret =%d\n", vector_id); 1052 return vector_id; 1053 } 1054 1055 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1056 } 1057 1058 static int hclgevf_unmap_ring_from_vector( 1059 struct hnae3_handle *handle, 1060 int vector, 1061 struct hnae3_ring_chain_node *ring_chain) 1062 { 1063 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1064 int ret, vector_id; 1065 1066 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1067 return 0; 1068 1069 vector_id = hclgevf_get_vector_index(hdev, vector); 1070 if (vector_id < 0) { 1071 dev_err(&handle->pdev->dev, 1072 "Get vector index fail. ret =%d\n", vector_id); 1073 return vector_id; 1074 } 1075 1076 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 1077 if (ret) 1078 dev_err(&handle->pdev->dev, 1079 "Unmap ring from vector fail. vector=%d, ret =%d\n", 1080 vector_id, 1081 ret); 1082 1083 return ret; 1084 } 1085 1086 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 1087 { 1088 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1089 int vector_id; 1090 1091 vector_id = hclgevf_get_vector_index(hdev, vector); 1092 if (vector_id < 0) { 1093 dev_err(&handle->pdev->dev, 1094 "hclgevf_put_vector get vector index fail. ret =%d\n", 1095 vector_id); 1096 return vector_id; 1097 } 1098 1099 hclgevf_free_vector(hdev, vector_id); 1100 1101 return 0; 1102 } 1103 1104 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1105 bool en_bc_pmc) 1106 { 1107 struct hclge_mbx_vf_to_pf_cmd *req; 1108 struct hclgevf_desc desc; 1109 int ret; 1110 1111 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1112 1113 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 1114 req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 1115 req->msg[1] = en_bc_pmc ? 1 : 0; 1116 1117 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1118 if (ret) 1119 dev_err(&hdev->pdev->dev, 1120 "Set promisc mode fail, status is %d.\n", ret); 1121 1122 return ret; 1123 } 1124 1125 static int hclgevf_set_promisc_mode(struct hclgevf_dev *hdev, bool en_bc_pmc) 1126 { 1127 return hclgevf_cmd_set_promisc_mode(hdev, en_bc_pmc); 1128 } 1129 1130 static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, int tqp_id, 1131 int stream_id, bool enable) 1132 { 1133 struct hclgevf_cfg_com_tqp_queue_cmd *req; 1134 struct hclgevf_desc desc; 1135 int status; 1136 1137 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1138 1139 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1140 false); 1141 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1142 req->stream_id = cpu_to_le16(stream_id); 1143 req->enable |= enable << HCLGEVF_TQP_ENABLE_B; 1144 1145 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1146 if (status) 1147 dev_err(&hdev->pdev->dev, 1148 "TQP enable fail, status =%d.\n", status); 1149 1150 return status; 1151 } 1152 1153 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1154 { 1155 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1156 struct hclgevf_tqp *tqp; 1157 int i; 1158 1159 for (i = 0; i < kinfo->num_tqps; i++) { 1160 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1161 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1162 } 1163 } 1164 1165 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1166 { 1167 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1168 1169 ether_addr_copy(p, hdev->hw.mac.mac_addr); 1170 } 1171 1172 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 1173 bool is_first) 1174 { 1175 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1176 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1177 u8 *new_mac_addr = (u8 *)p; 1178 u8 msg_data[ETH_ALEN * 2]; 1179 u16 subcode; 1180 int status; 1181 1182 ether_addr_copy(msg_data, new_mac_addr); 1183 ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 1184 1185 subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 1186 HCLGE_MBX_MAC_VLAN_UC_MODIFY; 1187 1188 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1189 subcode, msg_data, ETH_ALEN * 2, 1190 true, NULL, 0); 1191 if (!status) 1192 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1193 1194 return status; 1195 } 1196 1197 static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1198 const unsigned char *addr) 1199 { 1200 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1201 1202 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1203 HCLGE_MBX_MAC_VLAN_UC_ADD, 1204 addr, ETH_ALEN, false, NULL, 0); 1205 } 1206 1207 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1208 const unsigned char *addr) 1209 { 1210 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1211 1212 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1213 HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1214 addr, ETH_ALEN, false, NULL, 0); 1215 } 1216 1217 static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1218 const unsigned char *addr) 1219 { 1220 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1221 1222 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1223 HCLGE_MBX_MAC_VLAN_MC_ADD, 1224 addr, ETH_ALEN, false, NULL, 0); 1225 } 1226 1227 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1228 const unsigned char *addr) 1229 { 1230 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1231 1232 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1233 HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1234 addr, ETH_ALEN, false, NULL, 0); 1235 } 1236 1237 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1238 __be16 proto, u16 vlan_id, 1239 bool is_kill) 1240 { 1241 #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1242 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1243 u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1244 1245 if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1246 return -EINVAL; 1247 1248 if (proto != htons(ETH_P_8021Q)) 1249 return -EPROTONOSUPPORT; 1250 1251 msg_data[0] = is_kill; 1252 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1253 memcpy(&msg_data[3], &proto, sizeof(proto)); 1254 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1255 HCLGE_MBX_VLAN_FILTER, msg_data, 1256 HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 1257 } 1258 1259 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1260 { 1261 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1262 u8 msg_data; 1263 1264 msg_data = enable ? 1 : 0; 1265 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1266 HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1267 1, false, NULL, 0); 1268 } 1269 1270 static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1271 { 1272 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1273 u8 msg_data[2]; 1274 int ret; 1275 1276 memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 1277 1278 /* disable vf queue before send queue reset msg to PF */ 1279 ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 1280 if (ret) 1281 return ret; 1282 1283 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 1284 2, true, NULL, 0); 1285 } 1286 1287 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1288 { 1289 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1290 1291 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu, 1292 sizeof(new_mtu), true, NULL, 0); 1293 } 1294 1295 static int hclgevf_notify_client(struct hclgevf_dev *hdev, 1296 enum hnae3_reset_notify_type type) 1297 { 1298 struct hnae3_client *client = hdev->nic_client; 1299 struct hnae3_handle *handle = &hdev->nic; 1300 int ret; 1301 1302 if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 1303 !client) 1304 return 0; 1305 1306 if (!client->ops->reset_notify) 1307 return -EOPNOTSUPP; 1308 1309 ret = client->ops->reset_notify(handle, type); 1310 if (ret) 1311 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 1312 type, ret); 1313 1314 return ret; 1315 } 1316 1317 static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 1318 { 1319 struct hclgevf_dev *hdev = ae_dev->priv; 1320 1321 set_bit(HNAE3_FLR_DONE, &hdev->flr_state); 1322 } 1323 1324 static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev, 1325 unsigned long delay_us, 1326 unsigned long wait_cnt) 1327 { 1328 unsigned long cnt = 0; 1329 1330 while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) && 1331 cnt++ < wait_cnt) 1332 usleep_range(delay_us, delay_us * 2); 1333 1334 if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) { 1335 dev_err(&hdev->pdev->dev, 1336 "flr wait timeout\n"); 1337 return -ETIMEDOUT; 1338 } 1339 1340 return 0; 1341 } 1342 1343 static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 1344 { 1345 #define HCLGEVF_RESET_WAIT_US 20000 1346 #define HCLGEVF_RESET_WAIT_CNT 2000 1347 #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1348 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1349 1350 u32 val; 1351 int ret; 1352 1353 /* wait to check the hardware reset completion status */ 1354 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1355 dev_info(&hdev->pdev->dev, "checking vf resetting status: %x\n", val); 1356 1357 if (hdev->reset_type == HNAE3_FLR_RESET) 1358 return hclgevf_flr_poll_timeout(hdev, 1359 HCLGEVF_RESET_WAIT_US, 1360 HCLGEVF_RESET_WAIT_CNT); 1361 1362 ret = readl_poll_timeout(hdev->hw.io_base + HCLGEVF_RST_ING, val, 1363 !(val & HCLGEVF_RST_ING_BITS), 1364 HCLGEVF_RESET_WAIT_US, 1365 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1366 1367 /* hardware completion status should be available by this time */ 1368 if (ret) { 1369 dev_err(&hdev->pdev->dev, 1370 "could'nt get reset done status from h/w, timeout!\n"); 1371 return ret; 1372 } 1373 1374 /* we will wait a bit more to let reset of the stack to complete. This 1375 * might happen in case reset assertion was made by PF. Yes, this also 1376 * means we might end up waiting bit more even for VF reset. 1377 */ 1378 msleep(5000); 1379 1380 return 0; 1381 } 1382 1383 static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 1384 { 1385 int ret; 1386 1387 /* uninitialize the nic client */ 1388 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 1389 if (ret) 1390 return ret; 1391 1392 /* re-initialize the hclge device */ 1393 ret = hclgevf_reset_hdev(hdev); 1394 if (ret) { 1395 dev_err(&hdev->pdev->dev, 1396 "hclge device re-init failed, VF is disabled!\n"); 1397 return ret; 1398 } 1399 1400 /* bring up the nic client again */ 1401 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 1402 if (ret) 1403 return ret; 1404 1405 return hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT); 1406 } 1407 1408 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1409 { 1410 #define HCLGEVF_RESET_SYNC_TIME 100 1411 1412 int ret = 0; 1413 1414 switch (hdev->reset_type) { 1415 case HNAE3_VF_FUNC_RESET: 1416 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1417 0, true, NULL, sizeof(u8)); 1418 hdev->rst_stats.vf_func_rst_cnt++; 1419 break; 1420 case HNAE3_FLR_RESET: 1421 set_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1422 hdev->rst_stats.flr_rst_cnt++; 1423 break; 1424 default: 1425 break; 1426 } 1427 1428 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1429 /* inform hardware that preparatory work is done */ 1430 msleep(HCLGEVF_RESET_SYNC_TIME); 1431 hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 1432 HCLGEVF_NIC_CMQ_ENABLE); 1433 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1434 hdev->reset_type, ret); 1435 1436 return ret; 1437 } 1438 1439 static int hclgevf_reset(struct hclgevf_dev *hdev) 1440 { 1441 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1442 int ret; 1443 1444 /* Initialize ae_dev reset status as well, in case enet layer wants to 1445 * know if device is undergoing reset 1446 */ 1447 ae_dev->reset_type = hdev->reset_type; 1448 hdev->rst_stats.rst_cnt++; 1449 rtnl_lock(); 1450 1451 /* bring down the nic to stop any ongoing TX/RX */ 1452 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 1453 if (ret) 1454 goto err_reset_lock; 1455 1456 rtnl_unlock(); 1457 1458 ret = hclgevf_reset_prepare_wait(hdev); 1459 if (ret) 1460 goto err_reset; 1461 1462 /* check if VF could successfully fetch the hardware reset completion 1463 * status from the hardware 1464 */ 1465 ret = hclgevf_reset_wait(hdev); 1466 if (ret) { 1467 /* can't do much in this situation, will disable VF */ 1468 dev_err(&hdev->pdev->dev, 1469 "VF failed(=%d) to fetch H/W reset completion status\n", 1470 ret); 1471 goto err_reset; 1472 } 1473 1474 hdev->rst_stats.hw_rst_done_cnt++; 1475 1476 rtnl_lock(); 1477 1478 /* now, re-initialize the nic client and ae device*/ 1479 ret = hclgevf_reset_stack(hdev); 1480 if (ret) { 1481 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 1482 goto err_reset_lock; 1483 } 1484 1485 /* bring up the nic to enable TX/RX again */ 1486 ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 1487 if (ret) 1488 goto err_reset_lock; 1489 1490 rtnl_unlock(); 1491 1492 hdev->last_reset_time = jiffies; 1493 ae_dev->reset_type = HNAE3_NONE_RESET; 1494 hdev->rst_stats.rst_done_cnt++; 1495 1496 return ret; 1497 err_reset_lock: 1498 rtnl_unlock(); 1499 err_reset: 1500 /* When VF reset failed, only the higher level reset asserted by PF 1501 * can restore it, so re-initialize the command queue to receive 1502 * this higher reset event. 1503 */ 1504 hclgevf_cmd_init(hdev); 1505 dev_err(&hdev->pdev->dev, "failed to reset VF\n"); 1506 if (hclgevf_is_reset_pending(hdev)) 1507 hclgevf_reset_task_schedule(hdev); 1508 1509 return ret; 1510 } 1511 1512 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1513 unsigned long *addr) 1514 { 1515 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1516 1517 /* return the highest priority reset level amongst all */ 1518 if (test_bit(HNAE3_VF_RESET, addr)) { 1519 rst_level = HNAE3_VF_RESET; 1520 clear_bit(HNAE3_VF_RESET, addr); 1521 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1522 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1523 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1524 rst_level = HNAE3_VF_FULL_RESET; 1525 clear_bit(HNAE3_VF_FULL_RESET, addr); 1526 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1527 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1528 rst_level = HNAE3_VF_PF_FUNC_RESET; 1529 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1530 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1531 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1532 rst_level = HNAE3_VF_FUNC_RESET; 1533 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1534 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 1535 rst_level = HNAE3_FLR_RESET; 1536 clear_bit(HNAE3_FLR_RESET, addr); 1537 } 1538 1539 return rst_level; 1540 } 1541 1542 static void hclgevf_reset_event(struct pci_dev *pdev, 1543 struct hnae3_handle *handle) 1544 { 1545 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1546 struct hclgevf_dev *hdev = ae_dev->priv; 1547 1548 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 1549 1550 if (hdev->default_reset_request) 1551 hdev->reset_level = 1552 hclgevf_get_reset_level(hdev, 1553 &hdev->default_reset_request); 1554 else 1555 hdev->reset_level = HNAE3_VF_FUNC_RESET; 1556 1557 /* reset of this VF requested */ 1558 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1559 hclgevf_reset_task_schedule(hdev); 1560 1561 hdev->last_reset_time = jiffies; 1562 } 1563 1564 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1565 enum hnae3_reset_type rst_type) 1566 { 1567 struct hclgevf_dev *hdev = ae_dev->priv; 1568 1569 set_bit(rst_type, &hdev->default_reset_request); 1570 } 1571 1572 static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 1573 { 1574 #define HCLGEVF_FLR_WAIT_MS 100 1575 #define HCLGEVF_FLR_WAIT_CNT 50 1576 struct hclgevf_dev *hdev = ae_dev->priv; 1577 int cnt = 0; 1578 1579 clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1580 clear_bit(HNAE3_FLR_DONE, &hdev->flr_state); 1581 set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request); 1582 hclgevf_reset_event(hdev->pdev, NULL); 1583 1584 while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) && 1585 cnt++ < HCLGEVF_FLR_WAIT_CNT) 1586 msleep(HCLGEVF_FLR_WAIT_MS); 1587 1588 if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state)) 1589 dev_err(&hdev->pdev->dev, 1590 "flr wait down timeout: %d\n", cnt); 1591 } 1592 1593 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1594 { 1595 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1596 1597 return hdev->fw_version; 1598 } 1599 1600 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1601 { 1602 struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1603 1604 vector->vector_irq = pci_irq_vector(hdev->pdev, 1605 HCLGEVF_MISC_VECTOR_NUM); 1606 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1607 /* vector status always valid for Vector 0 */ 1608 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1609 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1610 1611 hdev->num_msi_left -= 1; 1612 hdev->num_msi_used += 1; 1613 } 1614 1615 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 1616 { 1617 if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) && 1618 !test_bit(HCLGEVF_STATE_REMOVING, &hdev->state)) { 1619 set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 1620 schedule_work(&hdev->rst_service_task); 1621 } 1622 } 1623 1624 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1625 { 1626 if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) && 1627 !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) { 1628 set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1629 schedule_work(&hdev->mbx_service_task); 1630 } 1631 } 1632 1633 static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 1634 { 1635 if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 1636 !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 1637 schedule_work(&hdev->service_task); 1638 } 1639 1640 static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev) 1641 { 1642 /* if we have any pending mailbox event then schedule the mbx task */ 1643 if (hdev->mbx_event_pending) 1644 hclgevf_mbx_task_schedule(hdev); 1645 1646 if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state)) 1647 hclgevf_reset_task_schedule(hdev); 1648 } 1649 1650 static void hclgevf_service_timer(struct timer_list *t) 1651 { 1652 struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 1653 1654 mod_timer(&hdev->service_timer, jiffies + 1655 HCLGEVF_GENERAL_TASK_INTERVAL * HZ); 1656 1657 hdev->stats_timer++; 1658 hclgevf_task_schedule(hdev); 1659 } 1660 1661 static void hclgevf_reset_service_task(struct work_struct *work) 1662 { 1663 struct hclgevf_dev *hdev = 1664 container_of(work, struct hclgevf_dev, rst_service_task); 1665 int ret; 1666 1667 if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1668 return; 1669 1670 clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 1671 1672 if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1673 &hdev->reset_state)) { 1674 /* PF has initmated that it is about to reset the hardware. 1675 * We now have to poll & check if harware has actually completed 1676 * the reset sequence. On hardware reset completion, VF needs to 1677 * reset the client and ae device. 1678 */ 1679 hdev->reset_attempts = 0; 1680 1681 hdev->last_reset_time = jiffies; 1682 while ((hdev->reset_type = 1683 hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 1684 != HNAE3_NONE_RESET) { 1685 ret = hclgevf_reset(hdev); 1686 if (ret) 1687 dev_err(&hdev->pdev->dev, 1688 "VF stack reset failed %d.\n", ret); 1689 } 1690 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1691 &hdev->reset_state)) { 1692 /* we could be here when either of below happens: 1693 * 1. reset was initiated due to watchdog timeout due to 1694 * a. IMP was earlier reset and our TX got choked down and 1695 * which resulted in watchdog reacting and inducing VF 1696 * reset. This also means our cmdq would be unreliable. 1697 * b. problem in TX due to other lower layer(example link 1698 * layer not functioning properly etc.) 1699 * 2. VF reset might have been initiated due to some config 1700 * change. 1701 * 1702 * NOTE: Theres no clear way to detect above cases than to react 1703 * to the response of PF for this reset request. PF will ack the 1704 * 1b and 2. cases but we will not get any intimation about 1a 1705 * from PF as cmdq would be in unreliable state i.e. mailbox 1706 * communication between PF and VF would be broken. 1707 */ 1708 1709 /* if we are never geting into pending state it means either: 1710 * 1. PF is not receiving our request which could be due to IMP 1711 * reset 1712 * 2. PF is screwed 1713 * We cannot do much for 2. but to check first we can try reset 1714 * our PCIe + stack and see if it alleviates the problem. 1715 */ 1716 if (hdev->reset_attempts > 3) { 1717 /* prepare for full reset of stack + pcie interface */ 1718 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1719 1720 /* "defer" schedule the reset task again */ 1721 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1722 } else { 1723 hdev->reset_attempts++; 1724 1725 set_bit(hdev->reset_level, &hdev->reset_pending); 1726 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1727 } 1728 hclgevf_reset_task_schedule(hdev); 1729 } 1730 1731 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1732 } 1733 1734 static void hclgevf_mailbox_service_task(struct work_struct *work) 1735 { 1736 struct hclgevf_dev *hdev; 1737 1738 hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 1739 1740 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1741 return; 1742 1743 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1744 1745 hclgevf_mbx_async_handler(hdev); 1746 1747 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1748 } 1749 1750 static void hclgevf_keep_alive_timer(struct timer_list *t) 1751 { 1752 struct hclgevf_dev *hdev = from_timer(hdev, t, keep_alive_timer); 1753 1754 schedule_work(&hdev->keep_alive_task); 1755 mod_timer(&hdev->keep_alive_timer, jiffies + 1756 HCLGEVF_KEEP_ALIVE_TASK_INTERVAL * HZ); 1757 } 1758 1759 static void hclgevf_keep_alive_task(struct work_struct *work) 1760 { 1761 struct hclgevf_dev *hdev; 1762 u8 respmsg; 1763 int ret; 1764 1765 hdev = container_of(work, struct hclgevf_dev, keep_alive_task); 1766 1767 if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 1768 return; 1769 1770 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL, 1771 0, false, &respmsg, sizeof(u8)); 1772 if (ret) 1773 dev_err(&hdev->pdev->dev, 1774 "VF sends keep alive cmd failed(=%d)\n", ret); 1775 } 1776 1777 static void hclgevf_service_task(struct work_struct *work) 1778 { 1779 struct hnae3_handle *handle; 1780 struct hclgevf_dev *hdev; 1781 1782 hdev = container_of(work, struct hclgevf_dev, service_task); 1783 handle = &hdev->nic; 1784 1785 if (hdev->stats_timer >= HCLGEVF_STATS_TIMER_INTERVAL) { 1786 hclgevf_tqps_update_stats(handle); 1787 hdev->stats_timer = 0; 1788 } 1789 1790 /* request the link status from the PF. PF would be able to tell VF 1791 * about such updates in future so we might remove this later 1792 */ 1793 hclgevf_request_link_info(hdev); 1794 1795 hclgevf_update_link_mode(hdev); 1796 1797 hclgevf_deferred_task_schedule(hdev); 1798 1799 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1800 } 1801 1802 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1803 { 1804 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1805 } 1806 1807 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1808 u32 *clearval) 1809 { 1810 u32 cmdq_src_reg, rst_ing_reg; 1811 1812 /* fetch the events from their corresponding regs */ 1813 cmdq_src_reg = hclgevf_read_dev(&hdev->hw, 1814 HCLGEVF_VECTOR0_CMDQ_SRC_REG); 1815 1816 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_src_reg) { 1817 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1818 dev_info(&hdev->pdev->dev, 1819 "receive reset interrupt 0x%x!\n", rst_ing_reg); 1820 set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1821 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1822 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1823 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RST_INT_B); 1824 *clearval = cmdq_src_reg; 1825 hdev->rst_stats.vf_rst_cnt++; 1826 return HCLGEVF_VECTOR0_EVENT_RST; 1827 } 1828 1829 /* check for vector0 mailbox(=CMDQ RX) event source */ 1830 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 1831 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1832 *clearval = cmdq_src_reg; 1833 return HCLGEVF_VECTOR0_EVENT_MBX; 1834 } 1835 1836 dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 1837 1838 return HCLGEVF_VECTOR0_EVENT_OTHER; 1839 } 1840 1841 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1842 { 1843 writel(en ? 1 : 0, vector->addr); 1844 } 1845 1846 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1847 { 1848 enum hclgevf_evt_cause event_cause; 1849 struct hclgevf_dev *hdev = data; 1850 u32 clearval; 1851 1852 hclgevf_enable_vector(&hdev->misc_vector, false); 1853 event_cause = hclgevf_check_evt_cause(hdev, &clearval); 1854 1855 switch (event_cause) { 1856 case HCLGEVF_VECTOR0_EVENT_RST: 1857 hclgevf_reset_task_schedule(hdev); 1858 break; 1859 case HCLGEVF_VECTOR0_EVENT_MBX: 1860 hclgevf_mbx_handler(hdev); 1861 break; 1862 default: 1863 break; 1864 } 1865 1866 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 1867 hclgevf_clear_event_cause(hdev, clearval); 1868 hclgevf_enable_vector(&hdev->misc_vector, true); 1869 } 1870 1871 return IRQ_HANDLED; 1872 } 1873 1874 static int hclgevf_configure(struct hclgevf_dev *hdev) 1875 { 1876 int ret; 1877 1878 /* get current port based vlan state from PF */ 1879 ret = hclgevf_get_port_base_vlan_filter_state(hdev); 1880 if (ret) 1881 return ret; 1882 1883 /* get queue configuration from PF */ 1884 ret = hclgevf_get_queue_info(hdev); 1885 if (ret) 1886 return ret; 1887 1888 /* get queue depth info from PF */ 1889 ret = hclgevf_get_queue_depth(hdev); 1890 if (ret) 1891 return ret; 1892 1893 ret = hclgevf_get_pf_media_type(hdev); 1894 if (ret) 1895 return ret; 1896 1897 /* get tc configuration from PF */ 1898 return hclgevf_get_tc_info(hdev); 1899 } 1900 1901 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 1902 { 1903 struct pci_dev *pdev = ae_dev->pdev; 1904 struct hclgevf_dev *hdev; 1905 1906 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 1907 if (!hdev) 1908 return -ENOMEM; 1909 1910 hdev->pdev = pdev; 1911 hdev->ae_dev = ae_dev; 1912 ae_dev->priv = hdev; 1913 1914 return 0; 1915 } 1916 1917 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 1918 { 1919 struct hnae3_handle *roce = &hdev->roce; 1920 struct hnae3_handle *nic = &hdev->nic; 1921 1922 roce->rinfo.num_vectors = hdev->num_roce_msix; 1923 1924 if (hdev->num_msi_left < roce->rinfo.num_vectors || 1925 hdev->num_msi_left == 0) 1926 return -EINVAL; 1927 1928 roce->rinfo.base_vector = hdev->roce_base_vector; 1929 1930 roce->rinfo.netdev = nic->kinfo.netdev; 1931 roce->rinfo.roce_io_base = hdev->hw.io_base; 1932 1933 roce->pdev = nic->pdev; 1934 roce->ae_algo = nic->ae_algo; 1935 roce->numa_node_mask = nic->numa_node_mask; 1936 1937 return 0; 1938 } 1939 1940 static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 1941 { 1942 struct hclgevf_cfg_gro_status_cmd *req; 1943 struct hclgevf_desc desc; 1944 int ret; 1945 1946 if (!hnae3_dev_gro_supported(hdev)) 1947 return 0; 1948 1949 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 1950 false); 1951 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 1952 1953 req->gro_en = cpu_to_le16(en ? 1 : 0); 1954 1955 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1956 if (ret) 1957 dev_err(&hdev->pdev->dev, 1958 "VF GRO hardware config cmd failed, ret = %d.\n", ret); 1959 1960 return ret; 1961 } 1962 1963 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 1964 { 1965 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1966 int i, ret; 1967 1968 rss_cfg->rss_size = hdev->rss_size_max; 1969 1970 if (hdev->pdev->revision >= 0x21) { 1971 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 1972 memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 1973 HCLGEVF_RSS_KEY_SIZE); 1974 1975 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 1976 rss_cfg->rss_hash_key); 1977 if (ret) 1978 return ret; 1979 1980 rss_cfg->rss_tuple_sets.ipv4_tcp_en = 1981 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1982 rss_cfg->rss_tuple_sets.ipv4_udp_en = 1983 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1984 rss_cfg->rss_tuple_sets.ipv4_sctp_en = 1985 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1986 rss_cfg->rss_tuple_sets.ipv4_fragment_en = 1987 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1988 rss_cfg->rss_tuple_sets.ipv6_tcp_en = 1989 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1990 rss_cfg->rss_tuple_sets.ipv6_udp_en = 1991 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1992 rss_cfg->rss_tuple_sets.ipv6_sctp_en = 1993 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1994 rss_cfg->rss_tuple_sets.ipv6_fragment_en = 1995 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1996 1997 ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 1998 if (ret) 1999 return ret; 2000 2001 } 2002 2003 /* Initialize RSS indirect table for each vport */ 2004 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 2005 rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max; 2006 2007 ret = hclgevf_set_rss_indir_table(hdev); 2008 if (ret) 2009 return ret; 2010 2011 return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max); 2012 } 2013 2014 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2015 { 2016 /* other vlan config(like, VLAN TX/RX offload) would also be added 2017 * here later 2018 */ 2019 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2020 false); 2021 } 2022 2023 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 2024 { 2025 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2026 2027 if (enable) { 2028 mod_timer(&hdev->service_timer, jiffies + HZ); 2029 } else { 2030 del_timer_sync(&hdev->service_timer); 2031 cancel_work_sync(&hdev->service_task); 2032 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2033 } 2034 } 2035 2036 static int hclgevf_ae_start(struct hnae3_handle *handle) 2037 { 2038 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2039 2040 /* reset tqp stats */ 2041 hclgevf_reset_tqp_stats(handle); 2042 2043 hclgevf_request_link_info(hdev); 2044 2045 hclgevf_update_link_mode(hdev); 2046 2047 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2048 2049 return 0; 2050 } 2051 2052 static void hclgevf_ae_stop(struct hnae3_handle *handle) 2053 { 2054 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2055 int i; 2056 2057 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2058 2059 if (hdev->reset_type != HNAE3_VF_RESET) 2060 for (i = 0; i < handle->kinfo.num_tqps; i++) 2061 if (hclgevf_reset_tqp(handle, i)) 2062 break; 2063 2064 /* reset tqp stats */ 2065 hclgevf_reset_tqp_stats(handle); 2066 hclgevf_update_link_status(hdev, 0); 2067 } 2068 2069 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2070 { 2071 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2072 u8 msg_data; 2073 2074 msg_data = alive ? 1 : 0; 2075 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE, 2076 0, &msg_data, 1, false, NULL, 0); 2077 } 2078 2079 static int hclgevf_client_start(struct hnae3_handle *handle) 2080 { 2081 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2082 int ret; 2083 2084 ret = hclgevf_set_alive(handle, true); 2085 if (ret) 2086 return ret; 2087 2088 mod_timer(&hdev->keep_alive_timer, jiffies + 2089 HCLGEVF_KEEP_ALIVE_TASK_INTERVAL * HZ); 2090 2091 return 0; 2092 } 2093 2094 static void hclgevf_client_stop(struct hnae3_handle *handle) 2095 { 2096 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2097 int ret; 2098 2099 ret = hclgevf_set_alive(handle, false); 2100 if (ret) 2101 dev_warn(&hdev->pdev->dev, 2102 "%s failed %d\n", __func__, ret); 2103 2104 del_timer_sync(&hdev->keep_alive_timer); 2105 cancel_work_sync(&hdev->keep_alive_task); 2106 } 2107 2108 static void hclgevf_state_init(struct hclgevf_dev *hdev) 2109 { 2110 /* setup tasks for the MBX */ 2111 INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 2112 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2113 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2114 2115 /* setup tasks for service timer */ 2116 timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 2117 2118 INIT_WORK(&hdev->service_task, hclgevf_service_task); 2119 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2120 2121 INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task); 2122 2123 mutex_init(&hdev->mbx_resp.mbx_mutex); 2124 2125 /* bring the device down */ 2126 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2127 } 2128 2129 static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2130 { 2131 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2132 set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2133 2134 if (hdev->keep_alive_timer.function) 2135 del_timer_sync(&hdev->keep_alive_timer); 2136 if (hdev->keep_alive_task.func) 2137 cancel_work_sync(&hdev->keep_alive_task); 2138 if (hdev->service_timer.function) 2139 del_timer_sync(&hdev->service_timer); 2140 if (hdev->service_task.func) 2141 cancel_work_sync(&hdev->service_task); 2142 if (hdev->mbx_service_task.func) 2143 cancel_work_sync(&hdev->mbx_service_task); 2144 if (hdev->rst_service_task.func) 2145 cancel_work_sync(&hdev->rst_service_task); 2146 2147 mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2148 } 2149 2150 static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2151 { 2152 struct pci_dev *pdev = hdev->pdev; 2153 int vectors; 2154 int i; 2155 2156 if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) 2157 vectors = pci_alloc_irq_vectors(pdev, 2158 hdev->roce_base_msix_offset + 1, 2159 hdev->num_msi, 2160 PCI_IRQ_MSIX); 2161 else 2162 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 2163 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2164 2165 if (vectors < 0) { 2166 dev_err(&pdev->dev, 2167 "failed(%d) to allocate MSI/MSI-X vectors\n", 2168 vectors); 2169 return vectors; 2170 } 2171 if (vectors < hdev->num_msi) 2172 dev_warn(&hdev->pdev->dev, 2173 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2174 hdev->num_msi, vectors); 2175 2176 hdev->num_msi = vectors; 2177 hdev->num_msi_left = vectors; 2178 hdev->base_msi_vector = pdev->irq; 2179 hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2180 2181 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2182 sizeof(u16), GFP_KERNEL); 2183 if (!hdev->vector_status) { 2184 pci_free_irq_vectors(pdev); 2185 return -ENOMEM; 2186 } 2187 2188 for (i = 0; i < hdev->num_msi; i++) 2189 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2190 2191 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2192 sizeof(int), GFP_KERNEL); 2193 if (!hdev->vector_irq) { 2194 devm_kfree(&pdev->dev, hdev->vector_status); 2195 pci_free_irq_vectors(pdev); 2196 return -ENOMEM; 2197 } 2198 2199 return 0; 2200 } 2201 2202 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2203 { 2204 struct pci_dev *pdev = hdev->pdev; 2205 2206 devm_kfree(&pdev->dev, hdev->vector_status); 2207 devm_kfree(&pdev->dev, hdev->vector_irq); 2208 pci_free_irq_vectors(pdev); 2209 } 2210 2211 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2212 { 2213 int ret = 0; 2214 2215 hclgevf_get_misc_vector(hdev); 2216 2217 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2218 0, "hclgevf_cmd", hdev); 2219 if (ret) { 2220 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2221 hdev->misc_vector.vector_irq); 2222 return ret; 2223 } 2224 2225 hclgevf_clear_event_cause(hdev, 0); 2226 2227 /* enable misc. vector(vector 0) */ 2228 hclgevf_enable_vector(&hdev->misc_vector, true); 2229 2230 return ret; 2231 } 2232 2233 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2234 { 2235 /* disable misc vector(vector 0) */ 2236 hclgevf_enable_vector(&hdev->misc_vector, false); 2237 synchronize_irq(hdev->misc_vector.vector_irq); 2238 free_irq(hdev->misc_vector.vector_irq, hdev); 2239 hclgevf_free_vector(hdev, 0); 2240 } 2241 2242 static void hclgevf_info_show(struct hclgevf_dev *hdev) 2243 { 2244 struct device *dev = &hdev->pdev->dev; 2245 2246 dev_info(dev, "VF info begin:\n"); 2247 2248 dev_info(dev, "Task queue pairs numbers: %d\n", hdev->num_tqps); 2249 dev_info(dev, "Desc num per TX queue: %d\n", hdev->num_tx_desc); 2250 dev_info(dev, "Desc num per RX queue: %d\n", hdev->num_rx_desc); 2251 dev_info(dev, "Numbers of vports: %d\n", hdev->num_alloc_vport); 2252 dev_info(dev, "HW tc map: %d\n", hdev->hw_tc_map); 2253 dev_info(dev, "PF media type of this VF: %d\n", 2254 hdev->hw.mac.media_type); 2255 2256 dev_info(dev, "VF info end.\n"); 2257 } 2258 2259 static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 2260 struct hnae3_client *client) 2261 { 2262 struct hclgevf_dev *hdev = ae_dev->priv; 2263 int ret; 2264 2265 ret = client->ops->init_instance(&hdev->nic); 2266 if (ret) 2267 return ret; 2268 2269 set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2270 hnae3_set_client_init_flag(client, ae_dev, 1); 2271 2272 if (netif_msg_drv(&hdev->nic)) 2273 hclgevf_info_show(hdev); 2274 2275 return 0; 2276 } 2277 2278 static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 2279 struct hnae3_client *client) 2280 { 2281 struct hclgevf_dev *hdev = ae_dev->priv; 2282 int ret; 2283 2284 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 2285 !hdev->nic_client) 2286 return 0; 2287 2288 ret = hclgevf_init_roce_base_info(hdev); 2289 if (ret) 2290 return ret; 2291 2292 ret = client->ops->init_instance(&hdev->roce); 2293 if (ret) 2294 return ret; 2295 2296 hnae3_set_client_init_flag(client, ae_dev, 1); 2297 2298 return 0; 2299 } 2300 2301 static int hclgevf_init_client_instance(struct hnae3_client *client, 2302 struct hnae3_ae_dev *ae_dev) 2303 { 2304 struct hclgevf_dev *hdev = ae_dev->priv; 2305 int ret; 2306 2307 switch (client->type) { 2308 case HNAE3_CLIENT_KNIC: 2309 hdev->nic_client = client; 2310 hdev->nic.client = client; 2311 2312 ret = hclgevf_init_nic_client_instance(ae_dev, client); 2313 if (ret) 2314 goto clear_nic; 2315 2316 ret = hclgevf_init_roce_client_instance(ae_dev, 2317 hdev->roce_client); 2318 if (ret) 2319 goto clear_roce; 2320 2321 break; 2322 case HNAE3_CLIENT_ROCE: 2323 if (hnae3_dev_roce_supported(hdev)) { 2324 hdev->roce_client = client; 2325 hdev->roce.client = client; 2326 } 2327 2328 ret = hclgevf_init_roce_client_instance(ae_dev, client); 2329 if (ret) 2330 goto clear_roce; 2331 2332 break; 2333 default: 2334 return -EINVAL; 2335 } 2336 2337 return 0; 2338 2339 clear_nic: 2340 hdev->nic_client = NULL; 2341 hdev->nic.client = NULL; 2342 return ret; 2343 clear_roce: 2344 hdev->roce_client = NULL; 2345 hdev->roce.client = NULL; 2346 return ret; 2347 } 2348 2349 static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2350 struct hnae3_ae_dev *ae_dev) 2351 { 2352 struct hclgevf_dev *hdev = ae_dev->priv; 2353 2354 /* un-init roce, if it exists */ 2355 if (hdev->roce_client) { 2356 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 2357 hdev->roce_client = NULL; 2358 hdev->roce.client = NULL; 2359 } 2360 2361 /* un-init nic/unic, if this was not called by roce client */ 2362 if (client->ops->uninit_instance && hdev->nic_client && 2363 client->type != HNAE3_CLIENT_ROCE) { 2364 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2365 2366 client->ops->uninit_instance(&hdev->nic, 0); 2367 hdev->nic_client = NULL; 2368 hdev->nic.client = NULL; 2369 } 2370 } 2371 2372 static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2373 { 2374 struct pci_dev *pdev = hdev->pdev; 2375 struct hclgevf_hw *hw; 2376 int ret; 2377 2378 ret = pci_enable_device(pdev); 2379 if (ret) { 2380 dev_err(&pdev->dev, "failed to enable PCI device\n"); 2381 return ret; 2382 } 2383 2384 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2385 if (ret) { 2386 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2387 goto err_disable_device; 2388 } 2389 2390 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2391 if (ret) { 2392 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2393 goto err_disable_device; 2394 } 2395 2396 pci_set_master(pdev); 2397 hw = &hdev->hw; 2398 hw->hdev = hdev; 2399 hw->io_base = pci_iomap(pdev, 2, 0); 2400 if (!hw->io_base) { 2401 dev_err(&pdev->dev, "can't map configuration register space\n"); 2402 ret = -ENOMEM; 2403 goto err_clr_master; 2404 } 2405 2406 return 0; 2407 2408 err_clr_master: 2409 pci_clear_master(pdev); 2410 pci_release_regions(pdev); 2411 err_disable_device: 2412 pci_disable_device(pdev); 2413 2414 return ret; 2415 } 2416 2417 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2418 { 2419 struct pci_dev *pdev = hdev->pdev; 2420 2421 pci_iounmap(pdev, hdev->hw.io_base); 2422 pci_clear_master(pdev); 2423 pci_release_regions(pdev); 2424 pci_disable_device(pdev); 2425 } 2426 2427 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 2428 { 2429 struct hclgevf_query_res_cmd *req; 2430 struct hclgevf_desc desc; 2431 int ret; 2432 2433 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 2434 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2435 if (ret) { 2436 dev_err(&hdev->pdev->dev, 2437 "query vf resource failed, ret = %d.\n", ret); 2438 return ret; 2439 } 2440 2441 req = (struct hclgevf_query_res_cmd *)desc.data; 2442 2443 if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) { 2444 hdev->roce_base_msix_offset = 2445 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 2446 HCLGEVF_MSIX_OFT_ROCEE_M, 2447 HCLGEVF_MSIX_OFT_ROCEE_S); 2448 hdev->num_roce_msix = 2449 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 2450 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2451 2452 /* VF should have NIC vectors and Roce vectors, NIC vectors 2453 * are queued before Roce vectors. The offset is fixed to 64. 2454 */ 2455 hdev->num_msi = hdev->num_roce_msix + 2456 hdev->roce_base_msix_offset; 2457 } else { 2458 hdev->num_msi = 2459 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 2460 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2461 } 2462 2463 return 0; 2464 } 2465 2466 static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2467 { 2468 struct pci_dev *pdev = hdev->pdev; 2469 int ret = 0; 2470 2471 if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2472 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2473 hclgevf_misc_irq_uninit(hdev); 2474 hclgevf_uninit_msi(hdev); 2475 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2476 } 2477 2478 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2479 pci_set_master(pdev); 2480 ret = hclgevf_init_msi(hdev); 2481 if (ret) { 2482 dev_err(&pdev->dev, 2483 "failed(%d) to init MSI/MSI-X\n", ret); 2484 return ret; 2485 } 2486 2487 ret = hclgevf_misc_irq_init(hdev); 2488 if (ret) { 2489 hclgevf_uninit_msi(hdev); 2490 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2491 ret); 2492 return ret; 2493 } 2494 2495 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2496 } 2497 2498 return ret; 2499 } 2500 2501 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2502 { 2503 struct pci_dev *pdev = hdev->pdev; 2504 int ret; 2505 2506 ret = hclgevf_pci_reset(hdev); 2507 if (ret) { 2508 dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2509 return ret; 2510 } 2511 2512 ret = hclgevf_cmd_init(hdev); 2513 if (ret) { 2514 dev_err(&pdev->dev, "cmd failed %d\n", ret); 2515 return ret; 2516 } 2517 2518 ret = hclgevf_rss_init_hw(hdev); 2519 if (ret) { 2520 dev_err(&hdev->pdev->dev, 2521 "failed(%d) to initialize RSS\n", ret); 2522 return ret; 2523 } 2524 2525 ret = hclgevf_config_gro(hdev, true); 2526 if (ret) 2527 return ret; 2528 2529 ret = hclgevf_init_vlan_config(hdev); 2530 if (ret) { 2531 dev_err(&hdev->pdev->dev, 2532 "failed(%d) to initialize VLAN config\n", ret); 2533 return ret; 2534 } 2535 2536 dev_info(&hdev->pdev->dev, "Reset done\n"); 2537 2538 return 0; 2539 } 2540 2541 static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 2542 { 2543 struct pci_dev *pdev = hdev->pdev; 2544 int ret; 2545 2546 ret = hclgevf_pci_init(hdev); 2547 if (ret) { 2548 dev_err(&pdev->dev, "PCI initialization failed\n"); 2549 return ret; 2550 } 2551 2552 ret = hclgevf_cmd_queue_init(hdev); 2553 if (ret) { 2554 dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret); 2555 goto err_cmd_queue_init; 2556 } 2557 2558 ret = hclgevf_cmd_init(hdev); 2559 if (ret) 2560 goto err_cmd_init; 2561 2562 /* Get vf resource */ 2563 ret = hclgevf_query_vf_resource(hdev); 2564 if (ret) { 2565 dev_err(&hdev->pdev->dev, 2566 "Query vf status error, ret = %d.\n", ret); 2567 goto err_cmd_init; 2568 } 2569 2570 ret = hclgevf_init_msi(hdev); 2571 if (ret) { 2572 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 2573 goto err_cmd_init; 2574 } 2575 2576 hclgevf_state_init(hdev); 2577 hdev->reset_level = HNAE3_VF_FUNC_RESET; 2578 2579 ret = hclgevf_misc_irq_init(hdev); 2580 if (ret) { 2581 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2582 ret); 2583 goto err_misc_irq_init; 2584 } 2585 2586 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2587 2588 ret = hclgevf_configure(hdev); 2589 if (ret) { 2590 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2591 goto err_config; 2592 } 2593 2594 ret = hclgevf_alloc_tqps(hdev); 2595 if (ret) { 2596 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2597 goto err_config; 2598 } 2599 2600 ret = hclgevf_set_handle_info(hdev); 2601 if (ret) { 2602 dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 2603 goto err_config; 2604 } 2605 2606 ret = hclgevf_config_gro(hdev, true); 2607 if (ret) 2608 goto err_config; 2609 2610 /* vf is not allowed to enable unicast/multicast promisc mode. 2611 * For revision 0x20, default to disable broadcast promisc mode, 2612 * firmware makes sure broadcast packets can be accepted. 2613 * For revision 0x21, default to enable broadcast promisc mode. 2614 */ 2615 ret = hclgevf_set_promisc_mode(hdev, true); 2616 if (ret) 2617 goto err_config; 2618 2619 /* Initialize RSS for this VF */ 2620 ret = hclgevf_rss_init_hw(hdev); 2621 if (ret) { 2622 dev_err(&hdev->pdev->dev, 2623 "failed(%d) to initialize RSS\n", ret); 2624 goto err_config; 2625 } 2626 2627 ret = hclgevf_init_vlan_config(hdev); 2628 if (ret) { 2629 dev_err(&hdev->pdev->dev, 2630 "failed(%d) to initialize VLAN config\n", ret); 2631 goto err_config; 2632 } 2633 2634 hdev->last_reset_time = jiffies; 2635 pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME); 2636 2637 return 0; 2638 2639 err_config: 2640 hclgevf_misc_irq_uninit(hdev); 2641 err_misc_irq_init: 2642 hclgevf_state_uninit(hdev); 2643 hclgevf_uninit_msi(hdev); 2644 err_cmd_init: 2645 hclgevf_cmd_uninit(hdev); 2646 err_cmd_queue_init: 2647 hclgevf_pci_uninit(hdev); 2648 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2649 return ret; 2650 } 2651 2652 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2653 { 2654 hclgevf_state_uninit(hdev); 2655 2656 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2657 hclgevf_misc_irq_uninit(hdev); 2658 hclgevf_uninit_msi(hdev); 2659 } 2660 2661 hclgevf_pci_uninit(hdev); 2662 hclgevf_cmd_uninit(hdev); 2663 } 2664 2665 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 2666 { 2667 struct pci_dev *pdev = ae_dev->pdev; 2668 struct hclgevf_dev *hdev; 2669 int ret; 2670 2671 ret = hclgevf_alloc_hdev(ae_dev); 2672 if (ret) { 2673 dev_err(&pdev->dev, "hclge device allocation failed\n"); 2674 return ret; 2675 } 2676 2677 ret = hclgevf_init_hdev(ae_dev->priv); 2678 if (ret) { 2679 dev_err(&pdev->dev, "hclge device initialization failed\n"); 2680 return ret; 2681 } 2682 2683 hdev = ae_dev->priv; 2684 timer_setup(&hdev->keep_alive_timer, hclgevf_keep_alive_timer, 0); 2685 INIT_WORK(&hdev->keep_alive_task, hclgevf_keep_alive_task); 2686 2687 return 0; 2688 } 2689 2690 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 2691 { 2692 struct hclgevf_dev *hdev = ae_dev->priv; 2693 2694 hclgevf_uninit_hdev(hdev); 2695 ae_dev->priv = NULL; 2696 } 2697 2698 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2699 { 2700 struct hnae3_handle *nic = &hdev->nic; 2701 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2702 2703 return min_t(u32, hdev->rss_size_max, 2704 hdev->num_tqps / kinfo->num_tc); 2705 } 2706 2707 /** 2708 * hclgevf_get_channels - Get the current channels enabled and max supported. 2709 * @handle: hardware information for network interface 2710 * @ch: ethtool channels structure 2711 * 2712 * We don't support separate tx and rx queues as channels. The other count 2713 * represents how many queues are being used for control. max_combined counts 2714 * how many queue pairs we can support. They may not be mapped 1 to 1 with 2715 * q_vectors since we support a lot more queue pairs than q_vectors. 2716 **/ 2717 static void hclgevf_get_channels(struct hnae3_handle *handle, 2718 struct ethtool_channels *ch) 2719 { 2720 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2721 2722 ch->max_combined = hclgevf_get_max_channels(hdev); 2723 ch->other_count = 0; 2724 ch->max_other = 0; 2725 ch->combined_count = handle->kinfo.rss_size; 2726 } 2727 2728 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 2729 u16 *alloc_tqps, u16 *max_rss_size) 2730 { 2731 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2732 2733 *alloc_tqps = hdev->num_tqps; 2734 *max_rss_size = hdev->rss_size_max; 2735 } 2736 2737 static int hclgevf_get_status(struct hnae3_handle *handle) 2738 { 2739 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2740 2741 return hdev->hw.mac.link; 2742 } 2743 2744 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 2745 u8 *auto_neg, u32 *speed, 2746 u8 *duplex) 2747 { 2748 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2749 2750 if (speed) 2751 *speed = hdev->hw.mac.speed; 2752 if (duplex) 2753 *duplex = hdev->hw.mac.duplex; 2754 if (auto_neg) 2755 *auto_neg = AUTONEG_DISABLE; 2756 } 2757 2758 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 2759 u8 duplex) 2760 { 2761 hdev->hw.mac.speed = speed; 2762 hdev->hw.mac.duplex = duplex; 2763 } 2764 2765 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 2766 { 2767 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2768 2769 return hclgevf_config_gro(hdev, enable); 2770 } 2771 2772 static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 2773 u8 *module_type) 2774 { 2775 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2776 2777 if (media_type) 2778 *media_type = hdev->hw.mac.media_type; 2779 2780 if (module_type) 2781 *module_type = hdev->hw.mac.module_type; 2782 } 2783 2784 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 2785 { 2786 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2787 2788 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 2789 } 2790 2791 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 2792 { 2793 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2794 2795 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2796 } 2797 2798 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 2799 { 2800 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2801 2802 return hdev->rst_stats.hw_rst_done_cnt; 2803 } 2804 2805 static void hclgevf_get_link_mode(struct hnae3_handle *handle, 2806 unsigned long *supported, 2807 unsigned long *advertising) 2808 { 2809 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2810 2811 *supported = hdev->hw.mac.supported; 2812 *advertising = hdev->hw.mac.advertising; 2813 } 2814 2815 #define MAX_SEPARATE_NUM 4 2816 #define SEPARATOR_VALUE 0xFFFFFFFF 2817 #define REG_NUM_PER_LINE 4 2818 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 2819 2820 static int hclgevf_get_regs_len(struct hnae3_handle *handle) 2821 { 2822 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 2823 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2824 2825 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 2826 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 2827 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 2828 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 2829 2830 return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 2831 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 2832 } 2833 2834 static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 2835 void *data) 2836 { 2837 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2838 int i, j, reg_um, separator_num; 2839 u32 *reg = data; 2840 2841 *version = hdev->fw_version; 2842 2843 /* fetching per-VF registers values from VF PCIe register space */ 2844 reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 2845 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2846 for (i = 0; i < reg_um; i++) 2847 *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 2848 for (i = 0; i < separator_num; i++) 2849 *reg++ = SEPARATOR_VALUE; 2850 2851 reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 2852 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2853 for (i = 0; i < reg_um; i++) 2854 *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 2855 for (i = 0; i < separator_num; i++) 2856 *reg++ = SEPARATOR_VALUE; 2857 2858 reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 2859 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2860 for (j = 0; j < hdev->num_tqps; j++) { 2861 for (i = 0; i < reg_um; i++) 2862 *reg++ = hclgevf_read_dev(&hdev->hw, 2863 ring_reg_addr_list[i] + 2864 0x200 * j); 2865 for (i = 0; i < separator_num; i++) 2866 *reg++ = SEPARATOR_VALUE; 2867 } 2868 2869 reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 2870 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2871 for (j = 0; j < hdev->num_msi_used - 1; j++) { 2872 for (i = 0; i < reg_um; i++) 2873 *reg++ = hclgevf_read_dev(&hdev->hw, 2874 tqp_intr_reg_addr_list[i] + 2875 4 * j); 2876 for (i = 0; i < separator_num; i++) 2877 *reg++ = SEPARATOR_VALUE; 2878 } 2879 } 2880 2881 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 2882 u8 *port_base_vlan_info, u8 data_size) 2883 { 2884 struct hnae3_handle *nic = &hdev->nic; 2885 2886 rtnl_lock(); 2887 hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 2888 rtnl_unlock(); 2889 2890 /* send msg to PF and wait update port based vlan info */ 2891 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 2892 HCLGE_MBX_PORT_BASE_VLAN_CFG, 2893 port_base_vlan_info, data_size, 2894 false, NULL, 0); 2895 2896 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 2897 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 2898 else 2899 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 2900 2901 rtnl_lock(); 2902 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 2903 rtnl_unlock(); 2904 } 2905 2906 static const struct hnae3_ae_ops hclgevf_ops = { 2907 .init_ae_dev = hclgevf_init_ae_dev, 2908 .uninit_ae_dev = hclgevf_uninit_ae_dev, 2909 .flr_prepare = hclgevf_flr_prepare, 2910 .flr_done = hclgevf_flr_done, 2911 .init_client_instance = hclgevf_init_client_instance, 2912 .uninit_client_instance = hclgevf_uninit_client_instance, 2913 .start = hclgevf_ae_start, 2914 .stop = hclgevf_ae_stop, 2915 .client_start = hclgevf_client_start, 2916 .client_stop = hclgevf_client_stop, 2917 .map_ring_to_vector = hclgevf_map_ring_to_vector, 2918 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 2919 .get_vector = hclgevf_get_vector, 2920 .put_vector = hclgevf_put_vector, 2921 .reset_queue = hclgevf_reset_tqp, 2922 .get_mac_addr = hclgevf_get_mac_addr, 2923 .set_mac_addr = hclgevf_set_mac_addr, 2924 .add_uc_addr = hclgevf_add_uc_addr, 2925 .rm_uc_addr = hclgevf_rm_uc_addr, 2926 .add_mc_addr = hclgevf_add_mc_addr, 2927 .rm_mc_addr = hclgevf_rm_mc_addr, 2928 .get_stats = hclgevf_get_stats, 2929 .update_stats = hclgevf_update_stats, 2930 .get_strings = hclgevf_get_strings, 2931 .get_sset_count = hclgevf_get_sset_count, 2932 .get_rss_key_size = hclgevf_get_rss_key_size, 2933 .get_rss_indir_size = hclgevf_get_rss_indir_size, 2934 .get_rss = hclgevf_get_rss, 2935 .set_rss = hclgevf_set_rss, 2936 .get_rss_tuple = hclgevf_get_rss_tuple, 2937 .set_rss_tuple = hclgevf_set_rss_tuple, 2938 .get_tc_size = hclgevf_get_tc_size, 2939 .get_fw_version = hclgevf_get_fw_version, 2940 .set_vlan_filter = hclgevf_set_vlan_filter, 2941 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 2942 .reset_event = hclgevf_reset_event, 2943 .set_default_reset_request = hclgevf_set_def_reset_request, 2944 .get_channels = hclgevf_get_channels, 2945 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 2946 .get_regs_len = hclgevf_get_regs_len, 2947 .get_regs = hclgevf_get_regs, 2948 .get_status = hclgevf_get_status, 2949 .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 2950 .get_media_type = hclgevf_get_media_type, 2951 .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 2952 .ae_dev_resetting = hclgevf_ae_dev_resetting, 2953 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 2954 .set_gro_en = hclgevf_gro_en, 2955 .set_mtu = hclgevf_set_mtu, 2956 .get_global_queue_id = hclgevf_get_qid_global, 2957 .set_timer_task = hclgevf_set_timer_task, 2958 .get_link_mode = hclgevf_get_link_mode, 2959 }; 2960 2961 static struct hnae3_ae_algo ae_algovf = { 2962 .ops = &hclgevf_ops, 2963 .pdev_id_table = ae_algovf_pci_tbl, 2964 }; 2965 2966 static int hclgevf_init(void) 2967 { 2968 pr_info("%s is initializing\n", HCLGEVF_NAME); 2969 2970 hnae3_register_ae_algo(&ae_algovf); 2971 2972 return 0; 2973 } 2974 2975 static void hclgevf_exit(void) 2976 { 2977 hnae3_unregister_ae_algo(&ae_algovf); 2978 } 2979 module_init(hclgevf_init); 2980 module_exit(hclgevf_exit); 2981 2982 MODULE_LICENSE("GPL"); 2983 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 2984 MODULE_DESCRIPTION("HCLGEVF Driver"); 2985 MODULE_VERSION(HCLGEVF_MOD_VERSION); 2986