1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include <net/rtnetlink.h> 6 #include "hclgevf_cmd.h" 7 #include "hclgevf_main.h" 8 #include "hclge_mbx.h" 9 #include "hnae3.h" 10 11 #define HCLGEVF_NAME "hclgevf" 12 13 static int hclgevf_init_hdev(struct hclgevf_dev *hdev); 14 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev); 15 static struct hnae3_ae_algo ae_algovf; 16 17 static const struct pci_device_id ae_algovf_pci_tbl[] = { 18 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 19 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 20 /* required last entry */ 21 {0, } 22 }; 23 24 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 25 26 static inline struct hclgevf_dev *hclgevf_ae_get_hdev( 27 struct hnae3_handle *handle) 28 { 29 return container_of(handle, struct hclgevf_dev, nic); 30 } 31 32 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 33 { 34 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 35 struct hnae3_queue *queue; 36 struct hclgevf_desc desc; 37 struct hclgevf_tqp *tqp; 38 int status; 39 int i; 40 41 for (i = 0; i < hdev->num_tqps; i++) { 42 queue = handle->kinfo.tqp[i]; 43 tqp = container_of(queue, struct hclgevf_tqp, q); 44 hclgevf_cmd_setup_basic_desc(&desc, 45 HCLGEVF_OPC_QUERY_RX_STATUS, 46 true); 47 48 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 49 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 50 if (status) { 51 dev_err(&hdev->pdev->dev, 52 "Query tqp stat fail, status = %d,queue = %d\n", 53 status, i); 54 return status; 55 } 56 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 57 le32_to_cpu(desc.data[1]); 58 59 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 60 true); 61 62 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 63 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 64 if (status) { 65 dev_err(&hdev->pdev->dev, 66 "Query tqp stat fail, status = %d,queue = %d\n", 67 status, i); 68 return status; 69 } 70 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 71 le32_to_cpu(desc.data[1]); 72 } 73 74 return 0; 75 } 76 77 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 78 { 79 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 80 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 81 struct hclgevf_tqp *tqp; 82 u64 *buff = data; 83 int i; 84 85 for (i = 0; i < hdev->num_tqps; i++) { 86 tqp = container_of(handle->kinfo.tqp[i], struct hclgevf_tqp, q); 87 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 88 } 89 for (i = 0; i < kinfo->num_tqps; i++) { 90 tqp = container_of(handle->kinfo.tqp[i], struct hclgevf_tqp, q); 91 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 92 } 93 94 return buff; 95 } 96 97 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 98 { 99 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 100 101 return hdev->num_tqps * 2; 102 } 103 104 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 105 { 106 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 107 u8 *buff = data; 108 int i = 0; 109 110 for (i = 0; i < hdev->num_tqps; i++) { 111 struct hclgevf_tqp *tqp = container_of(handle->kinfo.tqp[i], 112 struct hclgevf_tqp, q); 113 snprintf(buff, ETH_GSTRING_LEN, "txq#%d_pktnum_rcd", 114 tqp->index); 115 buff += ETH_GSTRING_LEN; 116 } 117 118 for (i = 0; i < hdev->num_tqps; i++) { 119 struct hclgevf_tqp *tqp = container_of(handle->kinfo.tqp[i], 120 struct hclgevf_tqp, q); 121 snprintf(buff, ETH_GSTRING_LEN, "rxq#%d_pktnum_rcd", 122 tqp->index); 123 buff += ETH_GSTRING_LEN; 124 } 125 126 return buff; 127 } 128 129 static void hclgevf_update_stats(struct hnae3_handle *handle, 130 struct net_device_stats *net_stats) 131 { 132 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 133 int status; 134 135 status = hclgevf_tqps_update_stats(handle); 136 if (status) 137 dev_err(&hdev->pdev->dev, 138 "VF update of TQPS stats fail, status = %d.\n", 139 status); 140 } 141 142 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 143 { 144 if (strset == ETH_SS_TEST) 145 return -EOPNOTSUPP; 146 else if (strset == ETH_SS_STATS) 147 return hclgevf_tqps_get_sset_count(handle, strset); 148 149 return 0; 150 } 151 152 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 153 u8 *data) 154 { 155 u8 *p = (char *)data; 156 157 if (strset == ETH_SS_STATS) 158 p = hclgevf_tqps_get_strings(handle, p); 159 } 160 161 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 162 { 163 hclgevf_tqps_get_stats(handle, data); 164 } 165 166 static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 167 { 168 u8 resp_msg; 169 int status; 170 171 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 172 true, &resp_msg, sizeof(u8)); 173 if (status) { 174 dev_err(&hdev->pdev->dev, 175 "VF request to get TC info from PF failed %d", 176 status); 177 return status; 178 } 179 180 hdev->hw_tc_map = resp_msg; 181 182 return 0; 183 } 184 185 static int hclge_get_queue_info(struct hclgevf_dev *hdev) 186 { 187 #define HCLGEVF_TQPS_RSS_INFO_LEN 8 188 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 189 int status; 190 191 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 192 true, resp_msg, 193 HCLGEVF_TQPS_RSS_INFO_LEN); 194 if (status) { 195 dev_err(&hdev->pdev->dev, 196 "VF request to get tqp info from PF failed %d", 197 status); 198 return status; 199 } 200 201 memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 202 memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 203 memcpy(&hdev->num_desc, &resp_msg[4], sizeof(u16)); 204 memcpy(&hdev->rx_buf_len, &resp_msg[6], sizeof(u16)); 205 206 return 0; 207 } 208 209 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 210 { 211 struct hclgevf_tqp *tqp; 212 int i; 213 214 /* if this is on going reset then we need to re-allocate the TPQs 215 * since we cannot assume we would get same number of TPQs back from PF 216 */ 217 if (hclgevf_dev_ongoing_reset(hdev)) 218 devm_kfree(&hdev->pdev->dev, hdev->htqp); 219 220 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 221 sizeof(struct hclgevf_tqp), GFP_KERNEL); 222 if (!hdev->htqp) 223 return -ENOMEM; 224 225 tqp = hdev->htqp; 226 227 for (i = 0; i < hdev->num_tqps; i++) { 228 tqp->dev = &hdev->pdev->dev; 229 tqp->index = i; 230 231 tqp->q.ae_algo = &ae_algovf; 232 tqp->q.buf_size = hdev->rx_buf_len; 233 tqp->q.desc_num = hdev->num_desc; 234 tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 235 i * HCLGEVF_TQP_REG_SIZE; 236 237 tqp++; 238 } 239 240 return 0; 241 } 242 243 static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 244 { 245 struct hnae3_handle *nic = &hdev->nic; 246 struct hnae3_knic_private_info *kinfo; 247 u16 new_tqps = hdev->num_tqps; 248 int i; 249 250 kinfo = &nic->kinfo; 251 kinfo->num_tc = 0; 252 kinfo->num_desc = hdev->num_desc; 253 kinfo->rx_buf_len = hdev->rx_buf_len; 254 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 255 if (hdev->hw_tc_map & BIT(i)) 256 kinfo->num_tc++; 257 258 kinfo->rss_size 259 = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 260 new_tqps = kinfo->rss_size * kinfo->num_tc; 261 kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 262 263 /* if this is on going reset then we need to re-allocate the hnae queues 264 * as well since number of TPQs from PF might have changed. 265 */ 266 if (hclgevf_dev_ongoing_reset(hdev)) 267 devm_kfree(&hdev->pdev->dev, kinfo->tqp); 268 269 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 270 sizeof(struct hnae3_queue *), GFP_KERNEL); 271 if (!kinfo->tqp) 272 return -ENOMEM; 273 274 for (i = 0; i < kinfo->num_tqps; i++) { 275 hdev->htqp[i].q.handle = &hdev->nic; 276 hdev->htqp[i].q.tqp_index = i; 277 kinfo->tqp[i] = &hdev->htqp[i].q; 278 } 279 280 return 0; 281 } 282 283 static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 284 { 285 int status; 286 u8 resp_msg; 287 288 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 289 0, false, &resp_msg, sizeof(u8)); 290 if (status) 291 dev_err(&hdev->pdev->dev, 292 "VF failed to fetch link status(%d) from PF", status); 293 } 294 295 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 296 { 297 struct hnae3_handle *handle = &hdev->nic; 298 struct hnae3_client *client; 299 300 client = handle->client; 301 302 if (link_state != hdev->hw.mac.link) { 303 client->ops->link_status_change(handle, !!link_state); 304 hdev->hw.mac.link = link_state; 305 } 306 } 307 308 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 309 { 310 struct hnae3_handle *nic = &hdev->nic; 311 int ret; 312 313 nic->ae_algo = &ae_algovf; 314 nic->pdev = hdev->pdev; 315 nic->numa_node_mask = hdev->numa_node_mask; 316 nic->flags |= HNAE3_SUPPORT_VF; 317 318 if (hdev->ae_dev->dev_type != HNAE3_DEV_KNIC) { 319 dev_err(&hdev->pdev->dev, "unsupported device type %d\n", 320 hdev->ae_dev->dev_type); 321 return -EINVAL; 322 } 323 324 ret = hclgevf_knic_setup(hdev); 325 if (ret) 326 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 327 ret); 328 return ret; 329 } 330 331 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 332 { 333 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 334 hdev->num_msi_left += 1; 335 hdev->num_msi_used -= 1; 336 } 337 338 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 339 struct hnae3_vector_info *vector_info) 340 { 341 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 342 struct hnae3_vector_info *vector = vector_info; 343 int alloc = 0; 344 int i, j; 345 346 vector_num = min(hdev->num_msi_left, vector_num); 347 348 for (j = 0; j < vector_num; j++) { 349 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 350 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 351 vector->vector = pci_irq_vector(hdev->pdev, i); 352 vector->io_addr = hdev->hw.io_base + 353 HCLGEVF_VECTOR_REG_BASE + 354 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 355 hdev->vector_status[i] = 0; 356 hdev->vector_irq[i] = vector->vector; 357 358 vector++; 359 alloc++; 360 361 break; 362 } 363 } 364 } 365 hdev->num_msi_left -= alloc; 366 hdev->num_msi_used += alloc; 367 368 return alloc; 369 } 370 371 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 372 { 373 int i; 374 375 for (i = 0; i < hdev->num_msi; i++) 376 if (vector == hdev->vector_irq[i]) 377 return i; 378 379 return -EINVAL; 380 } 381 382 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 383 { 384 return HCLGEVF_RSS_KEY_SIZE; 385 } 386 387 static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 388 { 389 return HCLGEVF_RSS_IND_TBL_SIZE; 390 } 391 392 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 393 { 394 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 395 struct hclgevf_rss_indirection_table_cmd *req; 396 struct hclgevf_desc desc; 397 int status; 398 int i, j; 399 400 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 401 402 for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 403 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 404 false); 405 req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 406 req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 407 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 408 req->rss_result[j] = 409 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 410 411 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 412 if (status) { 413 dev_err(&hdev->pdev->dev, 414 "VF failed(=%d) to set RSS indirection table\n", 415 status); 416 return status; 417 } 418 } 419 420 return 0; 421 } 422 423 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 424 { 425 struct hclgevf_rss_tc_mode_cmd *req; 426 u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 427 u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 428 u16 tc_size[HCLGEVF_MAX_TC_NUM]; 429 struct hclgevf_desc desc; 430 u16 roundup_size; 431 int status; 432 int i; 433 434 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 435 436 roundup_size = roundup_pow_of_two(rss_size); 437 roundup_size = ilog2(roundup_size); 438 439 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 440 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 441 tc_size[i] = roundup_size; 442 tc_offset[i] = rss_size * i; 443 } 444 445 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 446 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 447 hnae_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 448 (tc_valid[i] & 0x1)); 449 hnae_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 450 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 451 hnae_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 452 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 453 } 454 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 455 if (status) 456 dev_err(&hdev->pdev->dev, 457 "VF failed(=%d) to set rss tc mode\n", status); 458 459 return status; 460 } 461 462 static int hclgevf_get_rss_hw_cfg(struct hnae3_handle *handle, u8 *hash, 463 u8 *key) 464 { 465 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 466 struct hclgevf_rss_config_cmd *req; 467 int lkup_times = key ? 3 : 1; 468 struct hclgevf_desc desc; 469 int key_offset; 470 int key_size; 471 int status; 472 473 req = (struct hclgevf_rss_config_cmd *)desc.data; 474 lkup_times = (lkup_times == 3) ? 3 : ((hash) ? 1 : 0); 475 476 for (key_offset = 0; key_offset < lkup_times; key_offset++) { 477 hclgevf_cmd_setup_basic_desc(&desc, 478 HCLGEVF_OPC_RSS_GENERIC_CONFIG, 479 true); 480 req->hash_config |= (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET); 481 482 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 483 if (status) { 484 dev_err(&hdev->pdev->dev, 485 "failed to get hardware RSS cfg, status = %d\n", 486 status); 487 return status; 488 } 489 490 if (key_offset == 2) 491 key_size = 492 HCLGEVF_RSS_KEY_SIZE - HCLGEVF_RSS_HASH_KEY_NUM * 2; 493 else 494 key_size = HCLGEVF_RSS_HASH_KEY_NUM; 495 496 if (key) 497 memcpy(key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, 498 req->hash_key, 499 key_size); 500 } 501 502 if (hash) { 503 if ((req->hash_config & 0xf) == HCLGEVF_RSS_HASH_ALGO_TOEPLITZ) 504 *hash = ETH_RSS_HASH_TOP; 505 else 506 *hash = ETH_RSS_HASH_UNKNOWN; 507 } 508 509 return 0; 510 } 511 512 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 513 u8 *hfunc) 514 { 515 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 516 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 517 int i; 518 519 if (indir) 520 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 521 indir[i] = rss_cfg->rss_indirection_tbl[i]; 522 523 return hclgevf_get_rss_hw_cfg(handle, hfunc, key); 524 } 525 526 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 527 const u8 *key, const u8 hfunc) 528 { 529 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 530 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 531 int i; 532 533 /* update the shadow RSS table with user specified qids */ 534 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 535 rss_cfg->rss_indirection_tbl[i] = indir[i]; 536 537 /* update the hardware */ 538 return hclgevf_set_rss_indir_table(hdev); 539 } 540 541 static int hclgevf_get_tc_size(struct hnae3_handle *handle) 542 { 543 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 544 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 545 546 return rss_cfg->rss_size; 547 } 548 549 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 550 int vector, 551 struct hnae3_ring_chain_node *ring_chain) 552 { 553 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 554 struct hnae3_ring_chain_node *node; 555 struct hclge_mbx_vf_to_pf_cmd *req; 556 struct hclgevf_desc desc; 557 int i = 0, vector_id; 558 int status; 559 u8 type; 560 561 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 562 vector_id = hclgevf_get_vector_index(hdev, vector); 563 if (vector_id < 0) { 564 dev_err(&handle->pdev->dev, 565 "Get vector index fail. ret =%d\n", vector_id); 566 return vector_id; 567 } 568 569 for (node = ring_chain; node; node = node->next) { 570 int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 571 HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 572 573 if (i == 0) { 574 hclgevf_cmd_setup_basic_desc(&desc, 575 HCLGEVF_OPC_MBX_VF_TO_PF, 576 false); 577 type = en ? 578 HCLGE_MBX_MAP_RING_TO_VECTOR : 579 HCLGE_MBX_UNMAP_RING_TO_VECTOR; 580 req->msg[0] = type; 581 req->msg[1] = vector_id; 582 } 583 584 req->msg[idx_offset] = 585 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B); 586 req->msg[idx_offset + 1] = node->tqp_index; 587 req->msg[idx_offset + 2] = hnae_get_field(node->int_gl_idx, 588 HNAE3_RING_GL_IDX_M, 589 HNAE3_RING_GL_IDX_S); 590 591 i++; 592 if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 593 HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 594 HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 595 !node->next) { 596 req->msg[2] = i; 597 598 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 599 if (status) { 600 dev_err(&hdev->pdev->dev, 601 "Map TQP fail, status is %d.\n", 602 status); 603 return status; 604 } 605 i = 0; 606 hclgevf_cmd_setup_basic_desc(&desc, 607 HCLGEVF_OPC_MBX_VF_TO_PF, 608 false); 609 req->msg[0] = type; 610 req->msg[1] = vector_id; 611 } 612 } 613 614 return 0; 615 } 616 617 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 618 struct hnae3_ring_chain_node *ring_chain) 619 { 620 return hclgevf_bind_ring_to_vector(handle, true, vector, ring_chain); 621 } 622 623 static int hclgevf_unmap_ring_from_vector( 624 struct hnae3_handle *handle, 625 int vector, 626 struct hnae3_ring_chain_node *ring_chain) 627 { 628 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 629 int ret, vector_id; 630 631 vector_id = hclgevf_get_vector_index(hdev, vector); 632 if (vector_id < 0) { 633 dev_err(&handle->pdev->dev, 634 "Get vector index fail. ret =%d\n", vector_id); 635 return vector_id; 636 } 637 638 ret = hclgevf_bind_ring_to_vector(handle, false, vector, ring_chain); 639 if (ret) 640 dev_err(&handle->pdev->dev, 641 "Unmap ring from vector fail. vector=%d, ret =%d\n", 642 vector_id, 643 ret); 644 645 return ret; 646 } 647 648 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 649 { 650 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 651 652 hclgevf_free_vector(hdev, vector); 653 654 return 0; 655 } 656 657 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 658 bool en_uc_pmc, bool en_mc_pmc) 659 { 660 struct hclge_mbx_vf_to_pf_cmd *req; 661 struct hclgevf_desc desc; 662 int status; 663 664 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 665 666 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 667 req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 668 req->msg[1] = en_uc_pmc ? 1 : 0; 669 req->msg[2] = en_mc_pmc ? 1 : 0; 670 671 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 672 if (status) 673 dev_err(&hdev->pdev->dev, 674 "Set promisc mode fail, status is %d.\n", status); 675 676 return status; 677 } 678 679 static void hclgevf_set_promisc_mode(struct hnae3_handle *handle, 680 bool en_uc_pmc, bool en_mc_pmc) 681 { 682 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 683 684 hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc); 685 } 686 687 static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, int tqp_id, 688 int stream_id, bool enable) 689 { 690 struct hclgevf_cfg_com_tqp_queue_cmd *req; 691 struct hclgevf_desc desc; 692 int status; 693 694 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 695 696 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 697 false); 698 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 699 req->stream_id = cpu_to_le16(stream_id); 700 req->enable |= enable << HCLGEVF_TQP_ENABLE_B; 701 702 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 703 if (status) 704 dev_err(&hdev->pdev->dev, 705 "TQP enable fail, status =%d.\n", status); 706 707 return status; 708 } 709 710 static int hclgevf_get_queue_id(struct hnae3_queue *queue) 711 { 712 struct hclgevf_tqp *tqp = container_of(queue, struct hclgevf_tqp, q); 713 714 return tqp->index; 715 } 716 717 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 718 { 719 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 720 struct hnae3_queue *queue; 721 struct hclgevf_tqp *tqp; 722 int i; 723 724 for (i = 0; i < hdev->num_tqps; i++) { 725 queue = handle->kinfo.tqp[i]; 726 tqp = container_of(queue, struct hclgevf_tqp, q); 727 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 728 } 729 } 730 731 static int hclgevf_cfg_func_mta_filter(struct hnae3_handle *handle, bool en) 732 { 733 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 734 u8 msg[2] = {0}; 735 736 msg[0] = en; 737 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 738 HCLGE_MBX_MAC_VLAN_MC_FUNC_MTA_ENABLE, 739 msg, 1, false, NULL, 0); 740 } 741 742 static int hclgevf_cfg_func_mta_type(struct hclgevf_dev *hdev) 743 { 744 u8 resp_msg = HCLGEVF_MTA_TYPE_SEL_MAX; 745 int ret; 746 747 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 748 HCLGE_MBX_MAC_VLAN_MTA_TYPE_READ, 749 NULL, 0, true, &resp_msg, sizeof(u8)); 750 751 if (ret) { 752 dev_err(&hdev->pdev->dev, 753 "Read mta type fail, ret=%d.\n", ret); 754 return ret; 755 } 756 757 if (resp_msg > HCLGEVF_MTA_TYPE_SEL_MAX) { 758 dev_err(&hdev->pdev->dev, 759 "Read mta type invalid, resp=%d.\n", resp_msg); 760 return -EINVAL; 761 } 762 763 hdev->mta_mac_sel_type = resp_msg; 764 765 return 0; 766 } 767 768 static u16 hclgevf_get_mac_addr_to_mta_index(struct hclgevf_dev *hdev, 769 const u8 *addr) 770 { 771 u32 rsh = HCLGEVF_MTA_TYPE_SEL_MAX - hdev->mta_mac_sel_type; 772 u16 high_val = addr[1] | (addr[0] << 8); 773 774 return (high_val >> rsh) & 0xfff; 775 } 776 777 static int hclgevf_do_update_mta_status(struct hclgevf_dev *hdev, 778 unsigned long *status) 779 { 780 #define HCLGEVF_MTA_STATUS_MSG_SIZE 13 781 #define HCLGEVF_MTA_STATUS_MSG_BITS \ 782 (HCLGEVF_MTA_STATUS_MSG_SIZE * BITS_PER_BYTE) 783 #define HCLGEVF_MTA_STATUS_MSG_END_BITS \ 784 (HCLGEVF_MTA_TBL_SIZE % HCLGEVF_MTA_STATUS_MSG_BITS) 785 u16 tbl_cnt; 786 u16 tbl_idx; 787 u8 msg_cnt; 788 u8 msg_idx; 789 int ret; 790 791 msg_cnt = DIV_ROUND_UP(HCLGEVF_MTA_TBL_SIZE, 792 HCLGEVF_MTA_STATUS_MSG_BITS); 793 tbl_idx = 0; 794 msg_idx = 0; 795 while (msg_cnt--) { 796 u8 msg[HCLGEVF_MTA_STATUS_MSG_SIZE + 1]; 797 u8 *p = &msg[1]; 798 u8 msg_ofs; 799 u8 msg_bit; 800 801 memset(msg, 0, sizeof(msg)); 802 803 /* set index field */ 804 msg[0] = 0x7F & msg_idx; 805 806 /* set end flag field */ 807 if (msg_cnt == 0) { 808 msg[0] |= 0x80; 809 tbl_cnt = HCLGEVF_MTA_STATUS_MSG_END_BITS; 810 } else { 811 tbl_cnt = HCLGEVF_MTA_STATUS_MSG_BITS; 812 } 813 814 /* set status field */ 815 msg_ofs = 0; 816 msg_bit = 0; 817 while (tbl_cnt--) { 818 if (test_bit(tbl_idx, status)) 819 p[msg_ofs] |= BIT(msg_bit); 820 821 tbl_idx++; 822 823 msg_bit++; 824 if (msg_bit == BITS_PER_BYTE) { 825 msg_bit = 0; 826 msg_ofs++; 827 } 828 } 829 830 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 831 HCLGE_MBX_MAC_VLAN_MTA_STATUS_UPDATE, 832 msg, sizeof(msg), false, NULL, 0); 833 if (ret) 834 break; 835 836 msg_idx++; 837 } 838 839 return ret; 840 } 841 842 static int hclgevf_update_mta_status(struct hnae3_handle *handle) 843 { 844 unsigned long mta_status[BITS_TO_LONGS(HCLGEVF_MTA_TBL_SIZE)]; 845 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 846 struct net_device *netdev = hdev->nic.kinfo.netdev; 847 struct netdev_hw_addr *ha; 848 u16 tbl_idx; 849 850 /* clear status */ 851 memset(mta_status, 0, sizeof(mta_status)); 852 853 /* update status from mc addr list */ 854 netdev_for_each_mc_addr(ha, netdev) { 855 tbl_idx = hclgevf_get_mac_addr_to_mta_index(hdev, ha->addr); 856 set_bit(tbl_idx, mta_status); 857 } 858 859 return hclgevf_do_update_mta_status(hdev, mta_status); 860 } 861 862 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 863 { 864 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 865 866 ether_addr_copy(p, hdev->hw.mac.mac_addr); 867 } 868 869 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 870 bool is_first) 871 { 872 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 873 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 874 u8 *new_mac_addr = (u8 *)p; 875 u8 msg_data[ETH_ALEN * 2]; 876 u16 subcode; 877 int status; 878 879 ether_addr_copy(msg_data, new_mac_addr); 880 ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 881 882 subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 883 HCLGE_MBX_MAC_VLAN_UC_MODIFY; 884 885 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 886 subcode, msg_data, ETH_ALEN * 2, 887 true, NULL, 0); 888 if (!status) 889 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 890 891 return status; 892 } 893 894 static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 895 const unsigned char *addr) 896 { 897 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 898 899 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 900 HCLGE_MBX_MAC_VLAN_UC_ADD, 901 addr, ETH_ALEN, false, NULL, 0); 902 } 903 904 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 905 const unsigned char *addr) 906 { 907 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 908 909 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 910 HCLGE_MBX_MAC_VLAN_UC_REMOVE, 911 addr, ETH_ALEN, false, NULL, 0); 912 } 913 914 static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 915 const unsigned char *addr) 916 { 917 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 918 919 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 920 HCLGE_MBX_MAC_VLAN_MC_ADD, 921 addr, ETH_ALEN, false, NULL, 0); 922 } 923 924 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 925 const unsigned char *addr) 926 { 927 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 928 929 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 930 HCLGE_MBX_MAC_VLAN_MC_REMOVE, 931 addr, ETH_ALEN, false, NULL, 0); 932 } 933 934 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 935 __be16 proto, u16 vlan_id, 936 bool is_kill) 937 { 938 #define HCLGEVF_VLAN_MBX_MSG_LEN 5 939 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 940 u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 941 942 if (vlan_id > 4095) 943 return -EINVAL; 944 945 if (proto != htons(ETH_P_8021Q)) 946 return -EPROTONOSUPPORT; 947 948 msg_data[0] = is_kill; 949 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 950 memcpy(&msg_data[3], &proto, sizeof(proto)); 951 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 952 HCLGE_MBX_VLAN_FILTER, msg_data, 953 HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 954 } 955 956 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 957 { 958 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 959 u8 msg_data; 960 961 msg_data = enable ? 1 : 0; 962 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 963 HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 964 1, false, NULL, 0); 965 } 966 967 static void hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 968 { 969 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 970 u8 msg_data[2]; 971 int ret; 972 973 memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 974 975 /* disable vf queue before send queue reset msg to PF */ 976 ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 977 if (ret) 978 return; 979 980 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 981 2, true, NULL, 0); 982 } 983 984 static int hclgevf_notify_client(struct hclgevf_dev *hdev, 985 enum hnae3_reset_notify_type type) 986 { 987 struct hnae3_client *client = hdev->nic_client; 988 struct hnae3_handle *handle = &hdev->nic; 989 990 if (!client->ops->reset_notify) 991 return -EOPNOTSUPP; 992 993 return client->ops->reset_notify(handle, type); 994 } 995 996 static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 997 { 998 #define HCLGEVF_RESET_WAIT_MS 500 999 #define HCLGEVF_RESET_WAIT_CNT 20 1000 u32 val, cnt = 0; 1001 1002 /* wait to check the hardware reset completion status */ 1003 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_FUN_RST_ING); 1004 while (hnae_get_bit(val, HCLGEVF_FUN_RST_ING_B) && 1005 (cnt < HCLGEVF_RESET_WAIT_CNT)) { 1006 msleep(HCLGEVF_RESET_WAIT_MS); 1007 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_FUN_RST_ING); 1008 cnt++; 1009 } 1010 1011 /* hardware completion status should be available by this time */ 1012 if (cnt >= HCLGEVF_RESET_WAIT_CNT) { 1013 dev_warn(&hdev->pdev->dev, 1014 "could'nt get reset done status from h/w, timeout!\n"); 1015 return -EBUSY; 1016 } 1017 1018 /* we will wait a bit more to let reset of the stack to complete. This 1019 * might happen in case reset assertion was made by PF. Yes, this also 1020 * means we might end up waiting bit more even for VF reset. 1021 */ 1022 msleep(5000); 1023 1024 return 0; 1025 } 1026 1027 static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 1028 { 1029 int ret; 1030 1031 /* uninitialize the nic client */ 1032 hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 1033 1034 /* re-initialize the hclge device */ 1035 ret = hclgevf_init_hdev(hdev); 1036 if (ret) { 1037 dev_err(&hdev->pdev->dev, 1038 "hclge device re-init failed, VF is disabled!\n"); 1039 return ret; 1040 } 1041 1042 /* bring up the nic client again */ 1043 hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 1044 1045 return 0; 1046 } 1047 1048 static int hclgevf_reset(struct hclgevf_dev *hdev) 1049 { 1050 int ret; 1051 1052 rtnl_lock(); 1053 1054 /* bring down the nic to stop any ongoing TX/RX */ 1055 hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 1056 1057 /* check if VF could successfully fetch the hardware reset completion 1058 * status from the hardware 1059 */ 1060 ret = hclgevf_reset_wait(hdev); 1061 if (ret) { 1062 /* can't do much in this situation, will disable VF */ 1063 dev_err(&hdev->pdev->dev, 1064 "VF failed(=%d) to fetch H/W reset completion status\n", 1065 ret); 1066 1067 dev_warn(&hdev->pdev->dev, "VF reset failed, disabling VF!\n"); 1068 hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 1069 1070 rtnl_unlock(); 1071 return ret; 1072 } 1073 1074 /* now, re-initialize the nic client and ae device*/ 1075 ret = hclgevf_reset_stack(hdev); 1076 if (ret) 1077 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 1078 1079 /* bring up the nic to enable TX/RX again */ 1080 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 1081 1082 rtnl_unlock(); 1083 1084 return ret; 1085 } 1086 1087 static int hclgevf_do_reset(struct hclgevf_dev *hdev) 1088 { 1089 int status; 1090 u8 respmsg; 1091 1092 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1093 0, false, &respmsg, sizeof(u8)); 1094 if (status) 1095 dev_err(&hdev->pdev->dev, 1096 "VF reset request to PF failed(=%d)\n", status); 1097 1098 return status; 1099 } 1100 1101 static void hclgevf_reset_event(struct hnae3_handle *handle) 1102 { 1103 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1104 1105 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 1106 1107 handle->reset_level = HNAE3_VF_RESET; 1108 1109 /* reset of this VF requested */ 1110 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1111 hclgevf_reset_task_schedule(hdev); 1112 1113 handle->last_reset_time = jiffies; 1114 } 1115 1116 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1117 { 1118 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1119 1120 return hdev->fw_version; 1121 } 1122 1123 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1124 { 1125 struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1126 1127 vector->vector_irq = pci_irq_vector(hdev->pdev, 1128 HCLGEVF_MISC_VECTOR_NUM); 1129 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1130 /* vector status always valid for Vector 0 */ 1131 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1132 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1133 1134 hdev->num_msi_left -= 1; 1135 hdev->num_msi_used += 1; 1136 } 1137 1138 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 1139 { 1140 if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) && 1141 !test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) { 1142 set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 1143 schedule_work(&hdev->rst_service_task); 1144 } 1145 } 1146 1147 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1148 { 1149 if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) && 1150 !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) { 1151 set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1152 schedule_work(&hdev->mbx_service_task); 1153 } 1154 } 1155 1156 static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 1157 { 1158 if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 1159 !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 1160 schedule_work(&hdev->service_task); 1161 } 1162 1163 static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev) 1164 { 1165 /* if we have any pending mailbox event then schedule the mbx task */ 1166 if (hdev->mbx_event_pending) 1167 hclgevf_mbx_task_schedule(hdev); 1168 1169 if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state)) 1170 hclgevf_reset_task_schedule(hdev); 1171 } 1172 1173 static void hclgevf_service_timer(struct timer_list *t) 1174 { 1175 struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 1176 1177 mod_timer(&hdev->service_timer, jiffies + 5 * HZ); 1178 1179 hclgevf_task_schedule(hdev); 1180 } 1181 1182 static void hclgevf_reset_service_task(struct work_struct *work) 1183 { 1184 struct hclgevf_dev *hdev = 1185 container_of(work, struct hclgevf_dev, rst_service_task); 1186 int ret; 1187 1188 if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1189 return; 1190 1191 clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 1192 1193 if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1194 &hdev->reset_state)) { 1195 /* PF has initmated that it is about to reset the hardware. 1196 * We now have to poll & check if harware has actually completed 1197 * the reset sequence. On hardware reset completion, VF needs to 1198 * reset the client and ae device. 1199 */ 1200 hdev->reset_attempts = 0; 1201 1202 ret = hclgevf_reset(hdev); 1203 if (ret) 1204 dev_err(&hdev->pdev->dev, "VF stack reset failed.\n"); 1205 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1206 &hdev->reset_state)) { 1207 /* we could be here when either of below happens: 1208 * 1. reset was initiated due to watchdog timeout due to 1209 * a. IMP was earlier reset and our TX got choked down and 1210 * which resulted in watchdog reacting and inducing VF 1211 * reset. This also means our cmdq would be unreliable. 1212 * b. problem in TX due to other lower layer(example link 1213 * layer not functioning properly etc.) 1214 * 2. VF reset might have been initiated due to some config 1215 * change. 1216 * 1217 * NOTE: Theres no clear way to detect above cases than to react 1218 * to the response of PF for this reset request. PF will ack the 1219 * 1b and 2. cases but we will not get any intimation about 1a 1220 * from PF as cmdq would be in unreliable state i.e. mailbox 1221 * communication between PF and VF would be broken. 1222 */ 1223 1224 /* if we are never geting into pending state it means either: 1225 * 1. PF is not receiving our request which could be due to IMP 1226 * reset 1227 * 2. PF is screwed 1228 * We cannot do much for 2. but to check first we can try reset 1229 * our PCIe + stack and see if it alleviates the problem. 1230 */ 1231 if (hdev->reset_attempts > 3) { 1232 /* prepare for full reset of stack + pcie interface */ 1233 hdev->nic.reset_level = HNAE3_VF_FULL_RESET; 1234 1235 /* "defer" schedule the reset task again */ 1236 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1237 } else { 1238 hdev->reset_attempts++; 1239 1240 /* request PF for resetting this VF via mailbox */ 1241 ret = hclgevf_do_reset(hdev); 1242 if (ret) 1243 dev_warn(&hdev->pdev->dev, 1244 "VF rst fail, stack will call\n"); 1245 } 1246 } 1247 1248 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1249 } 1250 1251 static void hclgevf_mailbox_service_task(struct work_struct *work) 1252 { 1253 struct hclgevf_dev *hdev; 1254 1255 hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 1256 1257 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1258 return; 1259 1260 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1261 1262 hclgevf_mbx_async_handler(hdev); 1263 1264 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1265 } 1266 1267 static void hclgevf_service_task(struct work_struct *work) 1268 { 1269 struct hclgevf_dev *hdev; 1270 1271 hdev = container_of(work, struct hclgevf_dev, service_task); 1272 1273 /* request the link status from the PF. PF would be able to tell VF 1274 * about such updates in future so we might remove this later 1275 */ 1276 hclgevf_request_link_info(hdev); 1277 1278 hclgevf_deferred_task_schedule(hdev); 1279 1280 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1281 } 1282 1283 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1284 { 1285 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1286 } 1287 1288 static bool hclgevf_check_event_cause(struct hclgevf_dev *hdev, u32 *clearval) 1289 { 1290 u32 cmdq_src_reg; 1291 1292 /* fetch the events from their corresponding regs */ 1293 cmdq_src_reg = hclgevf_read_dev(&hdev->hw, 1294 HCLGEVF_VECTOR0_CMDQ_SRC_REG); 1295 1296 /* check for vector0 mailbox(=CMDQ RX) event source */ 1297 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 1298 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1299 *clearval = cmdq_src_reg; 1300 return true; 1301 } 1302 1303 dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 1304 1305 return false; 1306 } 1307 1308 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1309 { 1310 writel(en ? 1 : 0, vector->addr); 1311 } 1312 1313 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1314 { 1315 struct hclgevf_dev *hdev = data; 1316 u32 clearval; 1317 1318 hclgevf_enable_vector(&hdev->misc_vector, false); 1319 if (!hclgevf_check_event_cause(hdev, &clearval)) 1320 goto skip_sched; 1321 1322 hclgevf_mbx_handler(hdev); 1323 1324 hclgevf_clear_event_cause(hdev, clearval); 1325 1326 skip_sched: 1327 hclgevf_enable_vector(&hdev->misc_vector, true); 1328 1329 return IRQ_HANDLED; 1330 } 1331 1332 static int hclgevf_configure(struct hclgevf_dev *hdev) 1333 { 1334 int ret; 1335 1336 /* get queue configuration from PF */ 1337 ret = hclge_get_queue_info(hdev); 1338 if (ret) 1339 return ret; 1340 /* get tc configuration from PF */ 1341 return hclgevf_get_tc_info(hdev); 1342 } 1343 1344 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 1345 { 1346 struct pci_dev *pdev = ae_dev->pdev; 1347 struct hclgevf_dev *hdev = ae_dev->priv; 1348 1349 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 1350 if (!hdev) 1351 return -ENOMEM; 1352 1353 hdev->pdev = pdev; 1354 hdev->ae_dev = ae_dev; 1355 ae_dev->priv = hdev; 1356 1357 return 0; 1358 } 1359 1360 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 1361 { 1362 struct hnae3_handle *roce = &hdev->roce; 1363 struct hnae3_handle *nic = &hdev->nic; 1364 1365 roce->rinfo.num_vectors = HCLGEVF_ROCEE_VECTOR_NUM; 1366 1367 if (hdev->num_msi_left < roce->rinfo.num_vectors || 1368 hdev->num_msi_left == 0) 1369 return -EINVAL; 1370 1371 roce->rinfo.base_vector = 1372 hdev->vector_status[hdev->num_msi_used]; 1373 1374 roce->rinfo.netdev = nic->kinfo.netdev; 1375 roce->rinfo.roce_io_base = hdev->hw.io_base; 1376 1377 roce->pdev = nic->pdev; 1378 roce->ae_algo = nic->ae_algo; 1379 roce->numa_node_mask = nic->numa_node_mask; 1380 1381 return 0; 1382 } 1383 1384 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 1385 { 1386 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1387 int i, ret; 1388 1389 rss_cfg->rss_size = hdev->rss_size_max; 1390 1391 /* Initialize RSS indirect table for each vport */ 1392 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 1393 rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max; 1394 1395 ret = hclgevf_set_rss_indir_table(hdev); 1396 if (ret) 1397 return ret; 1398 1399 return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max); 1400 } 1401 1402 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 1403 { 1404 /* other vlan config(like, VLAN TX/RX offload) would also be added 1405 * here later 1406 */ 1407 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 1408 false); 1409 } 1410 1411 static int hclgevf_ae_start(struct hnae3_handle *handle) 1412 { 1413 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1414 int i, queue_id; 1415 1416 for (i = 0; i < handle->kinfo.num_tqps; i++) { 1417 /* ring enable */ 1418 queue_id = hclgevf_get_queue_id(handle->kinfo.tqp[i]); 1419 if (queue_id < 0) { 1420 dev_warn(&hdev->pdev->dev, 1421 "Get invalid queue id, ignore it\n"); 1422 continue; 1423 } 1424 1425 hclgevf_tqp_enable(hdev, queue_id, 0, true); 1426 } 1427 1428 /* reset tqp stats */ 1429 hclgevf_reset_tqp_stats(handle); 1430 1431 hclgevf_request_link_info(hdev); 1432 1433 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1434 mod_timer(&hdev->service_timer, jiffies + HZ); 1435 1436 return 0; 1437 } 1438 1439 static void hclgevf_ae_stop(struct hnae3_handle *handle) 1440 { 1441 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1442 int i, queue_id; 1443 1444 for (i = 0; i < hdev->num_tqps; i++) { 1445 /* Ring disable */ 1446 queue_id = hclgevf_get_queue_id(handle->kinfo.tqp[i]); 1447 if (queue_id < 0) { 1448 dev_warn(&hdev->pdev->dev, 1449 "Get invalid queue id, ignore it\n"); 1450 continue; 1451 } 1452 1453 hclgevf_tqp_enable(hdev, queue_id, 0, false); 1454 } 1455 1456 /* reset tqp stats */ 1457 hclgevf_reset_tqp_stats(handle); 1458 del_timer_sync(&hdev->service_timer); 1459 cancel_work_sync(&hdev->service_task); 1460 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1461 hclgevf_update_link_status(hdev, 0); 1462 } 1463 1464 static void hclgevf_state_init(struct hclgevf_dev *hdev) 1465 { 1466 /* if this is on going reset then skip this initialization */ 1467 if (hclgevf_dev_ongoing_reset(hdev)) 1468 return; 1469 1470 /* setup tasks for the MBX */ 1471 INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 1472 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1473 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1474 1475 /* setup tasks for service timer */ 1476 timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 1477 1478 INIT_WORK(&hdev->service_task, hclgevf_service_task); 1479 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1480 1481 INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task); 1482 1483 mutex_init(&hdev->mbx_resp.mbx_mutex); 1484 1485 /* bring the device down */ 1486 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1487 } 1488 1489 static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 1490 { 1491 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1492 1493 if (hdev->service_timer.function) 1494 del_timer_sync(&hdev->service_timer); 1495 if (hdev->service_task.func) 1496 cancel_work_sync(&hdev->service_task); 1497 if (hdev->mbx_service_task.func) 1498 cancel_work_sync(&hdev->mbx_service_task); 1499 if (hdev->rst_service_task.func) 1500 cancel_work_sync(&hdev->rst_service_task); 1501 1502 mutex_destroy(&hdev->mbx_resp.mbx_mutex); 1503 } 1504 1505 static int hclgevf_init_msi(struct hclgevf_dev *hdev) 1506 { 1507 struct pci_dev *pdev = hdev->pdev; 1508 int vectors; 1509 int i; 1510 1511 /* if this is on going reset then skip this initialization */ 1512 if (hclgevf_dev_ongoing_reset(hdev)) 1513 return 0; 1514 1515 hdev->num_msi = HCLGEVF_MAX_VF_VECTOR_NUM; 1516 1517 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 1518 PCI_IRQ_MSI | PCI_IRQ_MSIX); 1519 if (vectors < 0) { 1520 dev_err(&pdev->dev, 1521 "failed(%d) to allocate MSI/MSI-X vectors\n", 1522 vectors); 1523 return vectors; 1524 } 1525 if (vectors < hdev->num_msi) 1526 dev_warn(&hdev->pdev->dev, 1527 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 1528 hdev->num_msi, vectors); 1529 1530 hdev->num_msi = vectors; 1531 hdev->num_msi_left = vectors; 1532 hdev->base_msi_vector = pdev->irq; 1533 1534 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 1535 sizeof(u16), GFP_KERNEL); 1536 if (!hdev->vector_status) { 1537 pci_free_irq_vectors(pdev); 1538 return -ENOMEM; 1539 } 1540 1541 for (i = 0; i < hdev->num_msi; i++) 1542 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 1543 1544 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 1545 sizeof(int), GFP_KERNEL); 1546 if (!hdev->vector_irq) { 1547 pci_free_irq_vectors(pdev); 1548 return -ENOMEM; 1549 } 1550 1551 return 0; 1552 } 1553 1554 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 1555 { 1556 struct pci_dev *pdev = hdev->pdev; 1557 1558 pci_free_irq_vectors(pdev); 1559 } 1560 1561 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 1562 { 1563 int ret = 0; 1564 1565 /* if this is on going reset then skip this initialization */ 1566 if (hclgevf_dev_ongoing_reset(hdev)) 1567 return 0; 1568 1569 hclgevf_get_misc_vector(hdev); 1570 1571 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 1572 0, "hclgevf_cmd", hdev); 1573 if (ret) { 1574 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 1575 hdev->misc_vector.vector_irq); 1576 return ret; 1577 } 1578 1579 /* enable misc. vector(vector 0) */ 1580 hclgevf_enable_vector(&hdev->misc_vector, true); 1581 1582 return ret; 1583 } 1584 1585 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 1586 { 1587 /* disable misc vector(vector 0) */ 1588 hclgevf_enable_vector(&hdev->misc_vector, false); 1589 free_irq(hdev->misc_vector.vector_irq, hdev); 1590 hclgevf_free_vector(hdev, 0); 1591 } 1592 1593 static int hclgevf_init_instance(struct hclgevf_dev *hdev, 1594 struct hnae3_client *client) 1595 { 1596 int ret; 1597 1598 switch (client->type) { 1599 case HNAE3_CLIENT_KNIC: 1600 hdev->nic_client = client; 1601 hdev->nic.client = client; 1602 1603 ret = client->ops->init_instance(&hdev->nic); 1604 if (ret) 1605 return ret; 1606 1607 if (hdev->roce_client && hnae3_dev_roce_supported(hdev)) { 1608 struct hnae3_client *rc = hdev->roce_client; 1609 1610 ret = hclgevf_init_roce_base_info(hdev); 1611 if (ret) 1612 return ret; 1613 ret = rc->ops->init_instance(&hdev->roce); 1614 if (ret) 1615 return ret; 1616 } 1617 break; 1618 case HNAE3_CLIENT_UNIC: 1619 hdev->nic_client = client; 1620 hdev->nic.client = client; 1621 1622 ret = client->ops->init_instance(&hdev->nic); 1623 if (ret) 1624 return ret; 1625 break; 1626 case HNAE3_CLIENT_ROCE: 1627 if (hnae3_dev_roce_supported(hdev)) { 1628 hdev->roce_client = client; 1629 hdev->roce.client = client; 1630 } 1631 1632 if (hdev->roce_client && hdev->nic_client) { 1633 ret = hclgevf_init_roce_base_info(hdev); 1634 if (ret) 1635 return ret; 1636 1637 ret = client->ops->init_instance(&hdev->roce); 1638 if (ret) 1639 return ret; 1640 } 1641 } 1642 1643 return 0; 1644 } 1645 1646 static void hclgevf_uninit_instance(struct hclgevf_dev *hdev, 1647 struct hnae3_client *client) 1648 { 1649 /* un-init roce, if it exists */ 1650 if (hdev->roce_client) 1651 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 1652 1653 /* un-init nic/unic, if this was not called by roce client */ 1654 if ((client->ops->uninit_instance) && 1655 (client->type != HNAE3_CLIENT_ROCE)) 1656 client->ops->uninit_instance(&hdev->nic, 0); 1657 } 1658 1659 static int hclgevf_register_client(struct hnae3_client *client, 1660 struct hnae3_ae_dev *ae_dev) 1661 { 1662 struct hclgevf_dev *hdev = ae_dev->priv; 1663 1664 return hclgevf_init_instance(hdev, client); 1665 } 1666 1667 static void hclgevf_unregister_client(struct hnae3_client *client, 1668 struct hnae3_ae_dev *ae_dev) 1669 { 1670 struct hclgevf_dev *hdev = ae_dev->priv; 1671 1672 hclgevf_uninit_instance(hdev, client); 1673 } 1674 1675 static int hclgevf_pci_init(struct hclgevf_dev *hdev) 1676 { 1677 struct pci_dev *pdev = hdev->pdev; 1678 struct hclgevf_hw *hw; 1679 int ret; 1680 1681 /* check if we need to skip initialization of pci. This will happen if 1682 * device is undergoing VF reset. Otherwise, we would need to 1683 * re-initialize pci interface again i.e. when device is not going 1684 * through *any* reset or actually undergoing full reset. 1685 */ 1686 if (hclgevf_dev_ongoing_reset(hdev)) 1687 return 0; 1688 1689 ret = pci_enable_device(pdev); 1690 if (ret) { 1691 dev_err(&pdev->dev, "failed to enable PCI device\n"); 1692 return ret; 1693 } 1694 1695 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 1696 if (ret) { 1697 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 1698 goto err_disable_device; 1699 } 1700 1701 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 1702 if (ret) { 1703 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 1704 goto err_disable_device; 1705 } 1706 1707 pci_set_master(pdev); 1708 hw = &hdev->hw; 1709 hw->hdev = hdev; 1710 hw->io_base = pci_iomap(pdev, 2, 0); 1711 if (!hw->io_base) { 1712 dev_err(&pdev->dev, "can't map configuration register space\n"); 1713 ret = -ENOMEM; 1714 goto err_clr_master; 1715 } 1716 1717 return 0; 1718 1719 err_clr_master: 1720 pci_clear_master(pdev); 1721 pci_release_regions(pdev); 1722 err_disable_device: 1723 pci_disable_device(pdev); 1724 1725 return ret; 1726 } 1727 1728 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 1729 { 1730 struct pci_dev *pdev = hdev->pdev; 1731 1732 pci_iounmap(pdev, hdev->hw.io_base); 1733 pci_clear_master(pdev); 1734 pci_release_regions(pdev); 1735 pci_disable_device(pdev); 1736 } 1737 1738 static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 1739 { 1740 struct pci_dev *pdev = hdev->pdev; 1741 int ret; 1742 1743 /* check if device is on-going full reset(i.e. pcie as well) */ 1744 if (hclgevf_dev_ongoing_full_reset(hdev)) { 1745 dev_warn(&pdev->dev, "device is going full reset\n"); 1746 hclgevf_uninit_hdev(hdev); 1747 } 1748 1749 ret = hclgevf_pci_init(hdev); 1750 if (ret) { 1751 dev_err(&pdev->dev, "PCI initialization failed\n"); 1752 return ret; 1753 } 1754 1755 ret = hclgevf_init_msi(hdev); 1756 if (ret) { 1757 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 1758 goto err_irq_init; 1759 } 1760 1761 hclgevf_state_init(hdev); 1762 1763 ret = hclgevf_cmd_init(hdev); 1764 if (ret) 1765 goto err_cmd_init; 1766 1767 ret = hclgevf_misc_irq_init(hdev); 1768 if (ret) { 1769 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 1770 ret); 1771 goto err_misc_irq_init; 1772 } 1773 1774 ret = hclgevf_configure(hdev); 1775 if (ret) { 1776 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 1777 goto err_config; 1778 } 1779 1780 ret = hclgevf_alloc_tqps(hdev); 1781 if (ret) { 1782 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 1783 goto err_config; 1784 } 1785 1786 ret = hclgevf_set_handle_info(hdev); 1787 if (ret) { 1788 dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 1789 goto err_config; 1790 } 1791 1792 /* Initialize mta type for this VF */ 1793 ret = hclgevf_cfg_func_mta_type(hdev); 1794 if (ret) { 1795 dev_err(&hdev->pdev->dev, 1796 "failed(%d) to initialize MTA type\n", ret); 1797 goto err_config; 1798 } 1799 1800 /* Initialize RSS for this VF */ 1801 ret = hclgevf_rss_init_hw(hdev); 1802 if (ret) { 1803 dev_err(&hdev->pdev->dev, 1804 "failed(%d) to initialize RSS\n", ret); 1805 goto err_config; 1806 } 1807 1808 ret = hclgevf_init_vlan_config(hdev); 1809 if (ret) { 1810 dev_err(&hdev->pdev->dev, 1811 "failed(%d) to initialize VLAN config\n", ret); 1812 goto err_config; 1813 } 1814 1815 pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME); 1816 1817 return 0; 1818 1819 err_config: 1820 hclgevf_misc_irq_uninit(hdev); 1821 err_misc_irq_init: 1822 hclgevf_cmd_uninit(hdev); 1823 err_cmd_init: 1824 hclgevf_state_uninit(hdev); 1825 hclgevf_uninit_msi(hdev); 1826 err_irq_init: 1827 hclgevf_pci_uninit(hdev); 1828 return ret; 1829 } 1830 1831 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 1832 { 1833 hclgevf_state_uninit(hdev); 1834 hclgevf_misc_irq_uninit(hdev); 1835 hclgevf_cmd_uninit(hdev); 1836 hclgevf_uninit_msi(hdev); 1837 hclgevf_pci_uninit(hdev); 1838 } 1839 1840 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 1841 { 1842 struct pci_dev *pdev = ae_dev->pdev; 1843 int ret; 1844 1845 ret = hclgevf_alloc_hdev(ae_dev); 1846 if (ret) { 1847 dev_err(&pdev->dev, "hclge device allocation failed\n"); 1848 return ret; 1849 } 1850 1851 ret = hclgevf_init_hdev(ae_dev->priv); 1852 if (ret) 1853 dev_err(&pdev->dev, "hclge device initialization failed\n"); 1854 1855 return ret; 1856 } 1857 1858 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 1859 { 1860 struct hclgevf_dev *hdev = ae_dev->priv; 1861 1862 hclgevf_uninit_hdev(hdev); 1863 ae_dev->priv = NULL; 1864 } 1865 1866 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 1867 { 1868 struct hnae3_handle *nic = &hdev->nic; 1869 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 1870 1871 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps); 1872 } 1873 1874 /** 1875 * hclgevf_get_channels - Get the current channels enabled and max supported. 1876 * @handle: hardware information for network interface 1877 * @ch: ethtool channels structure 1878 * 1879 * We don't support separate tx and rx queues as channels. The other count 1880 * represents how many queues are being used for control. max_combined counts 1881 * how many queue pairs we can support. They may not be mapped 1 to 1 with 1882 * q_vectors since we support a lot more queue pairs than q_vectors. 1883 **/ 1884 static void hclgevf_get_channels(struct hnae3_handle *handle, 1885 struct ethtool_channels *ch) 1886 { 1887 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1888 1889 ch->max_combined = hclgevf_get_max_channels(hdev); 1890 ch->other_count = 0; 1891 ch->max_other = 0; 1892 ch->combined_count = hdev->num_tqps; 1893 } 1894 1895 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 1896 u16 *free_tqps, u16 *max_rss_size) 1897 { 1898 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1899 1900 *free_tqps = 0; 1901 *max_rss_size = hdev->rss_size_max; 1902 } 1903 1904 static int hclgevf_get_status(struct hnae3_handle *handle) 1905 { 1906 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1907 1908 return hdev->hw.mac.link; 1909 } 1910 1911 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 1912 u8 *auto_neg, u32 *speed, 1913 u8 *duplex) 1914 { 1915 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1916 1917 if (speed) 1918 *speed = hdev->hw.mac.speed; 1919 if (duplex) 1920 *duplex = hdev->hw.mac.duplex; 1921 if (auto_neg) 1922 *auto_neg = AUTONEG_DISABLE; 1923 } 1924 1925 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 1926 u8 duplex) 1927 { 1928 hdev->hw.mac.speed = speed; 1929 hdev->hw.mac.duplex = duplex; 1930 } 1931 1932 static const struct hnae3_ae_ops hclgevf_ops = { 1933 .init_ae_dev = hclgevf_init_ae_dev, 1934 .uninit_ae_dev = hclgevf_uninit_ae_dev, 1935 .init_client_instance = hclgevf_register_client, 1936 .uninit_client_instance = hclgevf_unregister_client, 1937 .start = hclgevf_ae_start, 1938 .stop = hclgevf_ae_stop, 1939 .map_ring_to_vector = hclgevf_map_ring_to_vector, 1940 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 1941 .get_vector = hclgevf_get_vector, 1942 .put_vector = hclgevf_put_vector, 1943 .reset_queue = hclgevf_reset_tqp, 1944 .set_promisc_mode = hclgevf_set_promisc_mode, 1945 .get_mac_addr = hclgevf_get_mac_addr, 1946 .set_mac_addr = hclgevf_set_mac_addr, 1947 .add_uc_addr = hclgevf_add_uc_addr, 1948 .rm_uc_addr = hclgevf_rm_uc_addr, 1949 .add_mc_addr = hclgevf_add_mc_addr, 1950 .rm_mc_addr = hclgevf_rm_mc_addr, 1951 .update_mta_status = hclgevf_update_mta_status, 1952 .get_stats = hclgevf_get_stats, 1953 .update_stats = hclgevf_update_stats, 1954 .get_strings = hclgevf_get_strings, 1955 .get_sset_count = hclgevf_get_sset_count, 1956 .get_rss_key_size = hclgevf_get_rss_key_size, 1957 .get_rss_indir_size = hclgevf_get_rss_indir_size, 1958 .get_rss = hclgevf_get_rss, 1959 .set_rss = hclgevf_set_rss, 1960 .get_tc_size = hclgevf_get_tc_size, 1961 .get_fw_version = hclgevf_get_fw_version, 1962 .set_vlan_filter = hclgevf_set_vlan_filter, 1963 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 1964 .reset_event = hclgevf_reset_event, 1965 .get_channels = hclgevf_get_channels, 1966 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 1967 .get_status = hclgevf_get_status, 1968 .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 1969 }; 1970 1971 static struct hnae3_ae_algo ae_algovf = { 1972 .ops = &hclgevf_ops, 1973 .name = HCLGEVF_NAME, 1974 .pdev_id_table = ae_algovf_pci_tbl, 1975 }; 1976 1977 static int hclgevf_init(void) 1978 { 1979 pr_info("%s is initializing\n", HCLGEVF_NAME); 1980 1981 hnae3_register_ae_algo(&ae_algovf); 1982 1983 return 0; 1984 } 1985 1986 static void hclgevf_exit(void) 1987 { 1988 hnae3_unregister_ae_algo(&ae_algovf); 1989 } 1990 module_init(hclgevf_init); 1991 module_exit(hclgevf_exit); 1992 1993 MODULE_LICENSE("GPL"); 1994 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 1995 MODULE_DESCRIPTION("HCLGEVF Driver"); 1996 MODULE_VERSION(HCLGEVF_MOD_VERSION); 1997