1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include <linux/iopoll.h> 6 #include <net/rtnetlink.h> 7 #include "hclgevf_cmd.h" 8 #include "hclgevf_main.h" 9 #include "hclge_mbx.h" 10 #include "hnae3.h" 11 12 #define HCLGEVF_NAME "hclgevf" 13 14 #define HCLGEVF_RESET_MAX_FAIL_CNT 5 15 16 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 17 static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 18 unsigned long delay); 19 20 static struct hnae3_ae_algo ae_algovf; 21 22 static struct workqueue_struct *hclgevf_wq; 23 24 static const struct pci_device_id ae_algovf_pci_tbl[] = { 25 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0}, 26 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 27 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 28 /* required last entry */ 29 {0, } 30 }; 31 32 static const u8 hclgevf_hash_key[] = { 33 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 34 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 35 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 36 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 37 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 38 }; 39 40 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 41 42 static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 43 HCLGEVF_CMDQ_TX_ADDR_H_REG, 44 HCLGEVF_CMDQ_TX_DEPTH_REG, 45 HCLGEVF_CMDQ_TX_TAIL_REG, 46 HCLGEVF_CMDQ_TX_HEAD_REG, 47 HCLGEVF_CMDQ_RX_ADDR_L_REG, 48 HCLGEVF_CMDQ_RX_ADDR_H_REG, 49 HCLGEVF_CMDQ_RX_DEPTH_REG, 50 HCLGEVF_CMDQ_RX_TAIL_REG, 51 HCLGEVF_CMDQ_RX_HEAD_REG, 52 HCLGEVF_VECTOR0_CMDQ_SRC_REG, 53 HCLGEVF_VECTOR0_CMDQ_STATE_REG, 54 HCLGEVF_CMDQ_INTR_EN_REG, 55 HCLGEVF_CMDQ_INTR_GEN_REG}; 56 57 static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 58 HCLGEVF_RST_ING, 59 HCLGEVF_GRO_EN_REG}; 60 61 static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 62 HCLGEVF_RING_RX_ADDR_H_REG, 63 HCLGEVF_RING_RX_BD_NUM_REG, 64 HCLGEVF_RING_RX_BD_LENGTH_REG, 65 HCLGEVF_RING_RX_MERGE_EN_REG, 66 HCLGEVF_RING_RX_TAIL_REG, 67 HCLGEVF_RING_RX_HEAD_REG, 68 HCLGEVF_RING_RX_FBD_NUM_REG, 69 HCLGEVF_RING_RX_OFFSET_REG, 70 HCLGEVF_RING_RX_FBD_OFFSET_REG, 71 HCLGEVF_RING_RX_STASH_REG, 72 HCLGEVF_RING_RX_BD_ERR_REG, 73 HCLGEVF_RING_TX_ADDR_L_REG, 74 HCLGEVF_RING_TX_ADDR_H_REG, 75 HCLGEVF_RING_TX_BD_NUM_REG, 76 HCLGEVF_RING_TX_PRIORITY_REG, 77 HCLGEVF_RING_TX_TC_REG, 78 HCLGEVF_RING_TX_MERGE_EN_REG, 79 HCLGEVF_RING_TX_TAIL_REG, 80 HCLGEVF_RING_TX_HEAD_REG, 81 HCLGEVF_RING_TX_FBD_NUM_REG, 82 HCLGEVF_RING_TX_OFFSET_REG, 83 HCLGEVF_RING_TX_EBD_NUM_REG, 84 HCLGEVF_RING_TX_EBD_OFFSET_REG, 85 HCLGEVF_RING_TX_BD_ERR_REG, 86 HCLGEVF_RING_EN_REG}; 87 88 static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 89 HCLGEVF_TQP_INTR_GL0_REG, 90 HCLGEVF_TQP_INTR_GL1_REG, 91 HCLGEVF_TQP_INTR_GL2_REG, 92 HCLGEVF_TQP_INTR_RL_REG}; 93 94 static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 95 { 96 if (!handle->client) 97 return container_of(handle, struct hclgevf_dev, nic); 98 else if (handle->client->type == HNAE3_CLIENT_ROCE) 99 return container_of(handle, struct hclgevf_dev, roce); 100 else 101 return container_of(handle, struct hclgevf_dev, nic); 102 } 103 104 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 105 { 106 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 107 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 108 struct hclgevf_desc desc; 109 struct hclgevf_tqp *tqp; 110 int status; 111 int i; 112 113 for (i = 0; i < kinfo->num_tqps; i++) { 114 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 115 hclgevf_cmd_setup_basic_desc(&desc, 116 HCLGEVF_OPC_QUERY_RX_STATUS, 117 true); 118 119 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 120 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 121 if (status) { 122 dev_err(&hdev->pdev->dev, 123 "Query tqp stat fail, status = %d,queue = %d\n", 124 status, i); 125 return status; 126 } 127 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 128 le32_to_cpu(desc.data[1]); 129 130 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 131 true); 132 133 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 134 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 135 if (status) { 136 dev_err(&hdev->pdev->dev, 137 "Query tqp stat fail, status = %d,queue = %d\n", 138 status, i); 139 return status; 140 } 141 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 142 le32_to_cpu(desc.data[1]); 143 } 144 145 return 0; 146 } 147 148 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 149 { 150 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 151 struct hclgevf_tqp *tqp; 152 u64 *buff = data; 153 int i; 154 155 for (i = 0; i < kinfo->num_tqps; i++) { 156 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 157 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 158 } 159 for (i = 0; i < kinfo->num_tqps; i++) { 160 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 161 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 162 } 163 164 return buff; 165 } 166 167 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 168 { 169 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 170 171 return kinfo->num_tqps * 2; 172 } 173 174 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 175 { 176 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 177 u8 *buff = data; 178 int i; 179 180 for (i = 0; i < kinfo->num_tqps; i++) { 181 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 182 struct hclgevf_tqp, q); 183 snprintf(buff, ETH_GSTRING_LEN, "txq%u_pktnum_rcd", 184 tqp->index); 185 buff += ETH_GSTRING_LEN; 186 } 187 188 for (i = 0; i < kinfo->num_tqps; i++) { 189 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 190 struct hclgevf_tqp, q); 191 snprintf(buff, ETH_GSTRING_LEN, "rxq%u_pktnum_rcd", 192 tqp->index); 193 buff += ETH_GSTRING_LEN; 194 } 195 196 return buff; 197 } 198 199 static void hclgevf_update_stats(struct hnae3_handle *handle, 200 struct net_device_stats *net_stats) 201 { 202 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 203 int status; 204 205 status = hclgevf_tqps_update_stats(handle); 206 if (status) 207 dev_err(&hdev->pdev->dev, 208 "VF update of TQPS stats fail, status = %d.\n", 209 status); 210 } 211 212 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 213 { 214 if (strset == ETH_SS_TEST) 215 return -EOPNOTSUPP; 216 else if (strset == ETH_SS_STATS) 217 return hclgevf_tqps_get_sset_count(handle, strset); 218 219 return 0; 220 } 221 222 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 223 u8 *data) 224 { 225 u8 *p = (char *)data; 226 227 if (strset == ETH_SS_STATS) 228 p = hclgevf_tqps_get_strings(handle, p); 229 } 230 231 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 232 { 233 hclgevf_tqps_get_stats(handle, data); 234 } 235 236 static void hclgevf_build_send_msg(struct hclge_vf_to_pf_msg *msg, u8 code, 237 u8 subcode) 238 { 239 if (msg) { 240 memset(msg, 0, sizeof(struct hclge_vf_to_pf_msg)); 241 msg->code = code; 242 msg->subcode = subcode; 243 } 244 } 245 246 static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 247 { 248 struct hclge_vf_to_pf_msg send_msg; 249 u8 resp_msg; 250 int status; 251 252 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_TCINFO, 0); 253 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg, 254 sizeof(resp_msg)); 255 if (status) { 256 dev_err(&hdev->pdev->dev, 257 "VF request to get TC info from PF failed %d", 258 status); 259 return status; 260 } 261 262 hdev->hw_tc_map = resp_msg; 263 264 return 0; 265 } 266 267 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 268 { 269 struct hnae3_handle *nic = &hdev->nic; 270 struct hclge_vf_to_pf_msg send_msg; 271 u8 resp_msg; 272 int ret; 273 274 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 275 HCLGE_MBX_GET_PORT_BASE_VLAN_STATE); 276 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg, 277 sizeof(u8)); 278 if (ret) { 279 dev_err(&hdev->pdev->dev, 280 "VF request to get port based vlan state failed %d", 281 ret); 282 return ret; 283 } 284 285 nic->port_base_vlan_state = resp_msg; 286 287 return 0; 288 } 289 290 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 291 { 292 #define HCLGEVF_TQPS_RSS_INFO_LEN 6 293 #define HCLGEVF_TQPS_ALLOC_OFFSET 0 294 #define HCLGEVF_TQPS_RSS_SIZE_OFFSET 2 295 #define HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET 4 296 297 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 298 struct hclge_vf_to_pf_msg send_msg; 299 int status; 300 301 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QINFO, 0); 302 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 303 HCLGEVF_TQPS_RSS_INFO_LEN); 304 if (status) { 305 dev_err(&hdev->pdev->dev, 306 "VF request to get tqp info from PF failed %d", 307 status); 308 return status; 309 } 310 311 memcpy(&hdev->num_tqps, &resp_msg[HCLGEVF_TQPS_ALLOC_OFFSET], 312 sizeof(u16)); 313 memcpy(&hdev->rss_size_max, &resp_msg[HCLGEVF_TQPS_RSS_SIZE_OFFSET], 314 sizeof(u16)); 315 memcpy(&hdev->rx_buf_len, &resp_msg[HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET], 316 sizeof(u16)); 317 318 return 0; 319 } 320 321 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 322 { 323 #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 324 #define HCLGEVF_TQPS_NUM_TX_DESC_OFFSET 0 325 #define HCLGEVF_TQPS_NUM_RX_DESC_OFFSET 2 326 327 u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 328 struct hclge_vf_to_pf_msg send_msg; 329 int ret; 330 331 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QDEPTH, 0); 332 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 333 HCLGEVF_TQPS_DEPTH_INFO_LEN); 334 if (ret) { 335 dev_err(&hdev->pdev->dev, 336 "VF request to get tqp depth info from PF failed %d", 337 ret); 338 return ret; 339 } 340 341 memcpy(&hdev->num_tx_desc, &resp_msg[HCLGEVF_TQPS_NUM_TX_DESC_OFFSET], 342 sizeof(u16)); 343 memcpy(&hdev->num_rx_desc, &resp_msg[HCLGEVF_TQPS_NUM_RX_DESC_OFFSET], 344 sizeof(u16)); 345 346 return 0; 347 } 348 349 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 350 { 351 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 352 struct hclge_vf_to_pf_msg send_msg; 353 u16 qid_in_pf = 0; 354 u8 resp_data[2]; 355 int ret; 356 357 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QID_IN_PF, 0); 358 memcpy(send_msg.data, &queue_id, sizeof(queue_id)); 359 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_data, 360 sizeof(resp_data)); 361 if (!ret) 362 qid_in_pf = *(u16 *)resp_data; 363 364 return qid_in_pf; 365 } 366 367 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 368 { 369 struct hclge_vf_to_pf_msg send_msg; 370 u8 resp_msg[2]; 371 int ret; 372 373 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MEDIA_TYPE, 0); 374 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 375 sizeof(resp_msg)); 376 if (ret) { 377 dev_err(&hdev->pdev->dev, 378 "VF request to get the pf port media type failed %d", 379 ret); 380 return ret; 381 } 382 383 hdev->hw.mac.media_type = resp_msg[0]; 384 hdev->hw.mac.module_type = resp_msg[1]; 385 386 return 0; 387 } 388 389 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 390 { 391 struct hclgevf_tqp *tqp; 392 int i; 393 394 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 395 sizeof(struct hclgevf_tqp), GFP_KERNEL); 396 if (!hdev->htqp) 397 return -ENOMEM; 398 399 tqp = hdev->htqp; 400 401 for (i = 0; i < hdev->num_tqps; i++) { 402 tqp->dev = &hdev->pdev->dev; 403 tqp->index = i; 404 405 tqp->q.ae_algo = &ae_algovf; 406 tqp->q.buf_size = hdev->rx_buf_len; 407 tqp->q.tx_desc_num = hdev->num_tx_desc; 408 tqp->q.rx_desc_num = hdev->num_rx_desc; 409 410 /* need an extended offset to configure queues >= 411 * HCLGEVF_TQP_MAX_SIZE_DEV_V2. 412 */ 413 if (i < HCLGEVF_TQP_MAX_SIZE_DEV_V2) 414 tqp->q.io_base = hdev->hw.io_base + 415 HCLGEVF_TQP_REG_OFFSET + 416 i * HCLGEVF_TQP_REG_SIZE; 417 else 418 tqp->q.io_base = hdev->hw.io_base + 419 HCLGEVF_TQP_REG_OFFSET + 420 HCLGEVF_TQP_EXT_REG_OFFSET + 421 (i - HCLGEVF_TQP_MAX_SIZE_DEV_V2) * 422 HCLGEVF_TQP_REG_SIZE; 423 424 tqp++; 425 } 426 427 return 0; 428 } 429 430 static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 431 { 432 struct hnae3_handle *nic = &hdev->nic; 433 struct hnae3_knic_private_info *kinfo; 434 u16 new_tqps = hdev->num_tqps; 435 unsigned int i; 436 u8 num_tc = 0; 437 438 kinfo = &nic->kinfo; 439 kinfo->num_tx_desc = hdev->num_tx_desc; 440 kinfo->num_rx_desc = hdev->num_rx_desc; 441 kinfo->rx_buf_len = hdev->rx_buf_len; 442 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 443 if (hdev->hw_tc_map & BIT(i)) 444 num_tc++; 445 446 num_tc = num_tc ? num_tc : 1; 447 kinfo->tc_info.num_tc = num_tc; 448 kinfo->rss_size = min_t(u16, hdev->rss_size_max, new_tqps / num_tc); 449 new_tqps = kinfo->rss_size * num_tc; 450 kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 451 452 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 453 sizeof(struct hnae3_queue *), GFP_KERNEL); 454 if (!kinfo->tqp) 455 return -ENOMEM; 456 457 for (i = 0; i < kinfo->num_tqps; i++) { 458 hdev->htqp[i].q.handle = &hdev->nic; 459 hdev->htqp[i].q.tqp_index = i; 460 kinfo->tqp[i] = &hdev->htqp[i].q; 461 } 462 463 /* after init the max rss_size and tqps, adjust the default tqp numbers 464 * and rss size with the actual vector numbers 465 */ 466 kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps); 467 kinfo->rss_size = min_t(u16, kinfo->num_tqps / num_tc, 468 kinfo->rss_size); 469 470 return 0; 471 } 472 473 static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 474 { 475 struct hclge_vf_to_pf_msg send_msg; 476 int status; 477 478 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_STATUS, 0); 479 status = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 480 if (status) 481 dev_err(&hdev->pdev->dev, 482 "VF failed to fetch link status(%d) from PF", status); 483 } 484 485 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 486 { 487 struct hnae3_handle *rhandle = &hdev->roce; 488 struct hnae3_handle *handle = &hdev->nic; 489 struct hnae3_client *rclient; 490 struct hnae3_client *client; 491 492 if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state)) 493 return; 494 495 client = handle->client; 496 rclient = hdev->roce_client; 497 498 link_state = 499 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 500 if (link_state != hdev->hw.mac.link) { 501 client->ops->link_status_change(handle, !!link_state); 502 if (rclient && rclient->ops->link_status_change) 503 rclient->ops->link_status_change(rhandle, !!link_state); 504 hdev->hw.mac.link = link_state; 505 } 506 507 clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state); 508 } 509 510 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 511 { 512 #define HCLGEVF_ADVERTISING 0 513 #define HCLGEVF_SUPPORTED 1 514 515 struct hclge_vf_to_pf_msg send_msg; 516 517 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_MODE, 0); 518 send_msg.data[0] = HCLGEVF_ADVERTISING; 519 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 520 send_msg.data[0] = HCLGEVF_SUPPORTED; 521 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 522 } 523 524 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 525 { 526 struct hnae3_handle *nic = &hdev->nic; 527 int ret; 528 529 nic->ae_algo = &ae_algovf; 530 nic->pdev = hdev->pdev; 531 nic->numa_node_mask = hdev->numa_node_mask; 532 nic->flags |= HNAE3_SUPPORT_VF; 533 534 ret = hclgevf_knic_setup(hdev); 535 if (ret) 536 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 537 ret); 538 return ret; 539 } 540 541 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 542 { 543 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 544 dev_warn(&hdev->pdev->dev, 545 "vector(vector_id %d) has been freed.\n", vector_id); 546 return; 547 } 548 549 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 550 hdev->num_msi_left += 1; 551 hdev->num_msi_used -= 1; 552 } 553 554 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 555 struct hnae3_vector_info *vector_info) 556 { 557 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 558 struct hnae3_vector_info *vector = vector_info; 559 int alloc = 0; 560 int i, j; 561 562 vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num); 563 vector_num = min(hdev->num_msi_left, vector_num); 564 565 for (j = 0; j < vector_num; j++) { 566 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 567 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 568 vector->vector = pci_irq_vector(hdev->pdev, i); 569 vector->io_addr = hdev->hw.io_base + 570 HCLGEVF_VECTOR_REG_BASE + 571 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 572 hdev->vector_status[i] = 0; 573 hdev->vector_irq[i] = vector->vector; 574 575 vector++; 576 alloc++; 577 578 break; 579 } 580 } 581 } 582 hdev->num_msi_left -= alloc; 583 hdev->num_msi_used += alloc; 584 585 return alloc; 586 } 587 588 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 589 { 590 int i; 591 592 for (i = 0; i < hdev->num_msi; i++) 593 if (vector == hdev->vector_irq[i]) 594 return i; 595 596 return -EINVAL; 597 } 598 599 static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 600 const u8 hfunc, const u8 *key) 601 { 602 struct hclgevf_rss_config_cmd *req; 603 unsigned int key_offset = 0; 604 struct hclgevf_desc desc; 605 int key_counts; 606 int key_size; 607 int ret; 608 609 key_counts = HCLGEVF_RSS_KEY_SIZE; 610 req = (struct hclgevf_rss_config_cmd *)desc.data; 611 612 while (key_counts) { 613 hclgevf_cmd_setup_basic_desc(&desc, 614 HCLGEVF_OPC_RSS_GENERIC_CONFIG, 615 false); 616 617 req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 618 req->hash_config |= 619 (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 620 621 key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts); 622 memcpy(req->hash_key, 623 key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 624 625 key_counts -= key_size; 626 key_offset++; 627 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 628 if (ret) { 629 dev_err(&hdev->pdev->dev, 630 "Configure RSS config fail, status = %d\n", 631 ret); 632 return ret; 633 } 634 } 635 636 return 0; 637 } 638 639 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 640 { 641 return HCLGEVF_RSS_KEY_SIZE; 642 } 643 644 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 645 { 646 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 647 struct hclgevf_rss_indirection_table_cmd *req; 648 struct hclgevf_desc desc; 649 int rss_cfg_tbl_num; 650 int status; 651 int i, j; 652 653 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 654 rss_cfg_tbl_num = hdev->ae_dev->dev_specs.rss_ind_tbl_size / 655 HCLGEVF_RSS_CFG_TBL_SIZE; 656 657 for (i = 0; i < rss_cfg_tbl_num; i++) { 658 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 659 false); 660 req->start_table_index = 661 cpu_to_le16(i * HCLGEVF_RSS_CFG_TBL_SIZE); 662 req->rss_set_bitmap = cpu_to_le16(HCLGEVF_RSS_SET_BITMAP_MSK); 663 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 664 req->rss_result[j] = 665 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 666 667 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 668 if (status) { 669 dev_err(&hdev->pdev->dev, 670 "VF failed(=%d) to set RSS indirection table\n", 671 status); 672 return status; 673 } 674 } 675 676 return 0; 677 } 678 679 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 680 { 681 struct hclgevf_rss_tc_mode_cmd *req; 682 u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 683 u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 684 u16 tc_size[HCLGEVF_MAX_TC_NUM]; 685 struct hclgevf_desc desc; 686 u16 roundup_size; 687 unsigned int i; 688 int status; 689 690 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 691 692 roundup_size = roundup_pow_of_two(rss_size); 693 roundup_size = ilog2(roundup_size); 694 695 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 696 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 697 tc_size[i] = roundup_size; 698 tc_offset[i] = rss_size * i; 699 } 700 701 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 702 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 703 u16 mode = 0; 704 705 hnae3_set_bit(mode, HCLGEVF_RSS_TC_VALID_B, 706 (tc_valid[i] & 0x1)); 707 hnae3_set_field(mode, HCLGEVF_RSS_TC_SIZE_M, 708 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 709 hnae3_set_bit(mode, HCLGEVF_RSS_TC_SIZE_MSB_B, 710 tc_size[i] >> HCLGEVF_RSS_TC_SIZE_MSB_OFFSET & 711 0x1); 712 hnae3_set_field(mode, HCLGEVF_RSS_TC_OFFSET_M, 713 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 714 715 req->rss_tc_mode[i] = cpu_to_le16(mode); 716 } 717 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 718 if (status) 719 dev_err(&hdev->pdev->dev, 720 "VF failed(=%d) to set rss tc mode\n", status); 721 722 return status; 723 } 724 725 /* for revision 0x20, vf shared the same rss config with pf */ 726 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 727 { 728 #define HCLGEVF_RSS_MBX_RESP_LEN 8 729 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 730 u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 731 struct hclge_vf_to_pf_msg send_msg; 732 u16 msg_num, hash_key_index; 733 u8 index; 734 int ret; 735 736 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_RSS_KEY, 0); 737 msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 738 HCLGEVF_RSS_MBX_RESP_LEN; 739 for (index = 0; index < msg_num; index++) { 740 send_msg.data[0] = index; 741 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 742 HCLGEVF_RSS_MBX_RESP_LEN); 743 if (ret) { 744 dev_err(&hdev->pdev->dev, 745 "VF get rss hash key from PF failed, ret=%d", 746 ret); 747 return ret; 748 } 749 750 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 751 if (index == msg_num - 1) 752 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 753 &resp_msg[0], 754 HCLGEVF_RSS_KEY_SIZE - hash_key_index); 755 else 756 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 757 &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 758 } 759 760 return 0; 761 } 762 763 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 764 u8 *hfunc) 765 { 766 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 767 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 768 int i, ret; 769 770 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 771 /* Get hash algorithm */ 772 if (hfunc) { 773 switch (rss_cfg->hash_algo) { 774 case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 775 *hfunc = ETH_RSS_HASH_TOP; 776 break; 777 case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 778 *hfunc = ETH_RSS_HASH_XOR; 779 break; 780 default: 781 *hfunc = ETH_RSS_HASH_UNKNOWN; 782 break; 783 } 784 } 785 786 /* Get the RSS Key required by the user */ 787 if (key) 788 memcpy(key, rss_cfg->rss_hash_key, 789 HCLGEVF_RSS_KEY_SIZE); 790 } else { 791 if (hfunc) 792 *hfunc = ETH_RSS_HASH_TOP; 793 if (key) { 794 ret = hclgevf_get_rss_hash_key(hdev); 795 if (ret) 796 return ret; 797 memcpy(key, rss_cfg->rss_hash_key, 798 HCLGEVF_RSS_KEY_SIZE); 799 } 800 } 801 802 if (indir) 803 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 804 indir[i] = rss_cfg->rss_indirection_tbl[i]; 805 806 return 0; 807 } 808 809 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 810 const u8 *key, const u8 hfunc) 811 { 812 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 813 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 814 int ret, i; 815 816 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 817 /* Set the RSS Hash Key if specififed by the user */ 818 if (key) { 819 switch (hfunc) { 820 case ETH_RSS_HASH_TOP: 821 rss_cfg->hash_algo = 822 HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 823 break; 824 case ETH_RSS_HASH_XOR: 825 rss_cfg->hash_algo = 826 HCLGEVF_RSS_HASH_ALGO_SIMPLE; 827 break; 828 case ETH_RSS_HASH_NO_CHANGE: 829 break; 830 default: 831 return -EINVAL; 832 } 833 834 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 835 key); 836 if (ret) 837 return ret; 838 839 /* Update the shadow RSS key with user specified qids */ 840 memcpy(rss_cfg->rss_hash_key, key, 841 HCLGEVF_RSS_KEY_SIZE); 842 } 843 } 844 845 /* update the shadow RSS table with user specified qids */ 846 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 847 rss_cfg->rss_indirection_tbl[i] = indir[i]; 848 849 /* update the hardware */ 850 return hclgevf_set_rss_indir_table(hdev); 851 } 852 853 static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 854 { 855 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 856 857 if (nfc->data & RXH_L4_B_2_3) 858 hash_sets |= HCLGEVF_D_PORT_BIT; 859 else 860 hash_sets &= ~HCLGEVF_D_PORT_BIT; 861 862 if (nfc->data & RXH_IP_SRC) 863 hash_sets |= HCLGEVF_S_IP_BIT; 864 else 865 hash_sets &= ~HCLGEVF_S_IP_BIT; 866 867 if (nfc->data & RXH_IP_DST) 868 hash_sets |= HCLGEVF_D_IP_BIT; 869 else 870 hash_sets &= ~HCLGEVF_D_IP_BIT; 871 872 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 873 hash_sets |= HCLGEVF_V_TAG_BIT; 874 875 return hash_sets; 876 } 877 878 static int hclgevf_init_rss_tuple_cmd(struct hnae3_handle *handle, 879 struct ethtool_rxnfc *nfc, 880 struct hclgevf_rss_input_tuple_cmd *req) 881 { 882 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 883 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 884 u8 tuple_sets; 885 886 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 887 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 888 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 889 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 890 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 891 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 892 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 893 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 894 895 tuple_sets = hclgevf_get_rss_hash_bits(nfc); 896 switch (nfc->flow_type) { 897 case TCP_V4_FLOW: 898 req->ipv4_tcp_en = tuple_sets; 899 break; 900 case TCP_V6_FLOW: 901 req->ipv6_tcp_en = tuple_sets; 902 break; 903 case UDP_V4_FLOW: 904 req->ipv4_udp_en = tuple_sets; 905 break; 906 case UDP_V6_FLOW: 907 req->ipv6_udp_en = tuple_sets; 908 break; 909 case SCTP_V4_FLOW: 910 req->ipv4_sctp_en = tuple_sets; 911 break; 912 case SCTP_V6_FLOW: 913 if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 && 914 (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3))) 915 return -EINVAL; 916 917 req->ipv6_sctp_en = tuple_sets; 918 break; 919 case IPV4_FLOW: 920 req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 921 break; 922 case IPV6_FLOW: 923 req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 924 break; 925 default: 926 return -EINVAL; 927 } 928 929 return 0; 930 } 931 932 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 933 struct ethtool_rxnfc *nfc) 934 { 935 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 936 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 937 struct hclgevf_rss_input_tuple_cmd *req; 938 struct hclgevf_desc desc; 939 int ret; 940 941 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 942 return -EOPNOTSUPP; 943 944 if (nfc->data & 945 ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 946 return -EINVAL; 947 948 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 949 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 950 951 ret = hclgevf_init_rss_tuple_cmd(handle, nfc, req); 952 if (ret) { 953 dev_err(&hdev->pdev->dev, 954 "failed to init rss tuple cmd, ret = %d\n", ret); 955 return ret; 956 } 957 958 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 959 if (ret) { 960 dev_err(&hdev->pdev->dev, 961 "Set rss tuple fail, status = %d\n", ret); 962 return ret; 963 } 964 965 rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 966 rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 967 rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 968 rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 969 rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 970 rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 971 rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 972 rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 973 return 0; 974 } 975 976 static int hclgevf_get_rss_tuple_by_flow_type(struct hclgevf_dev *hdev, 977 int flow_type, u8 *tuple_sets) 978 { 979 switch (flow_type) { 980 case TCP_V4_FLOW: 981 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_tcp_en; 982 break; 983 case UDP_V4_FLOW: 984 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_udp_en; 985 break; 986 case TCP_V6_FLOW: 987 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_tcp_en; 988 break; 989 case UDP_V6_FLOW: 990 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_udp_en; 991 break; 992 case SCTP_V4_FLOW: 993 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_sctp_en; 994 break; 995 case SCTP_V6_FLOW: 996 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_sctp_en; 997 break; 998 case IPV4_FLOW: 999 case IPV6_FLOW: 1000 *tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 1001 break; 1002 default: 1003 return -EINVAL; 1004 } 1005 1006 return 0; 1007 } 1008 1009 static u64 hclgevf_convert_rss_tuple(u8 tuple_sets) 1010 { 1011 u64 tuple_data = 0; 1012 1013 if (tuple_sets & HCLGEVF_D_PORT_BIT) 1014 tuple_data |= RXH_L4_B_2_3; 1015 if (tuple_sets & HCLGEVF_S_PORT_BIT) 1016 tuple_data |= RXH_L4_B_0_1; 1017 if (tuple_sets & HCLGEVF_D_IP_BIT) 1018 tuple_data |= RXH_IP_DST; 1019 if (tuple_sets & HCLGEVF_S_IP_BIT) 1020 tuple_data |= RXH_IP_SRC; 1021 1022 return tuple_data; 1023 } 1024 1025 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 1026 struct ethtool_rxnfc *nfc) 1027 { 1028 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1029 u8 tuple_sets; 1030 int ret; 1031 1032 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 1033 return -EOPNOTSUPP; 1034 1035 nfc->data = 0; 1036 1037 ret = hclgevf_get_rss_tuple_by_flow_type(hdev, nfc->flow_type, 1038 &tuple_sets); 1039 if (ret || !tuple_sets) 1040 return ret; 1041 1042 nfc->data = hclgevf_convert_rss_tuple(tuple_sets); 1043 1044 return 0; 1045 } 1046 1047 static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 1048 struct hclgevf_rss_cfg *rss_cfg) 1049 { 1050 struct hclgevf_rss_input_tuple_cmd *req; 1051 struct hclgevf_desc desc; 1052 int ret; 1053 1054 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 1055 1056 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 1057 1058 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 1059 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 1060 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 1061 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 1062 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 1063 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 1064 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 1065 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 1066 1067 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1068 if (ret) 1069 dev_err(&hdev->pdev->dev, 1070 "Configure rss input fail, status = %d\n", ret); 1071 return ret; 1072 } 1073 1074 static int hclgevf_get_tc_size(struct hnae3_handle *handle) 1075 { 1076 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1077 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1078 1079 return rss_cfg->rss_size; 1080 } 1081 1082 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 1083 int vector_id, 1084 struct hnae3_ring_chain_node *ring_chain) 1085 { 1086 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1087 struct hclge_vf_to_pf_msg send_msg; 1088 struct hnae3_ring_chain_node *node; 1089 int status; 1090 int i = 0; 1091 1092 memset(&send_msg, 0, sizeof(send_msg)); 1093 send_msg.code = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 1094 HCLGE_MBX_UNMAP_RING_TO_VECTOR; 1095 send_msg.vector_id = vector_id; 1096 1097 for (node = ring_chain; node; node = node->next) { 1098 send_msg.param[i].ring_type = 1099 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 1100 1101 send_msg.param[i].tqp_index = node->tqp_index; 1102 send_msg.param[i].int_gl_index = 1103 hnae3_get_field(node->int_gl_idx, 1104 HNAE3_RING_GL_IDX_M, 1105 HNAE3_RING_GL_IDX_S); 1106 1107 i++; 1108 if (i == HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM || !node->next) { 1109 send_msg.ring_num = i; 1110 1111 status = hclgevf_send_mbx_msg(hdev, &send_msg, false, 1112 NULL, 0); 1113 if (status) { 1114 dev_err(&hdev->pdev->dev, 1115 "Map TQP fail, status is %d.\n", 1116 status); 1117 return status; 1118 } 1119 i = 0; 1120 } 1121 } 1122 1123 return 0; 1124 } 1125 1126 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1127 struct hnae3_ring_chain_node *ring_chain) 1128 { 1129 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1130 int vector_id; 1131 1132 vector_id = hclgevf_get_vector_index(hdev, vector); 1133 if (vector_id < 0) { 1134 dev_err(&handle->pdev->dev, 1135 "Get vector index fail. ret =%d\n", vector_id); 1136 return vector_id; 1137 } 1138 1139 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1140 } 1141 1142 static int hclgevf_unmap_ring_from_vector( 1143 struct hnae3_handle *handle, 1144 int vector, 1145 struct hnae3_ring_chain_node *ring_chain) 1146 { 1147 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1148 int ret, vector_id; 1149 1150 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1151 return 0; 1152 1153 vector_id = hclgevf_get_vector_index(hdev, vector); 1154 if (vector_id < 0) { 1155 dev_err(&handle->pdev->dev, 1156 "Get vector index fail. ret =%d\n", vector_id); 1157 return vector_id; 1158 } 1159 1160 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 1161 if (ret) 1162 dev_err(&handle->pdev->dev, 1163 "Unmap ring from vector fail. vector=%d, ret =%d\n", 1164 vector_id, 1165 ret); 1166 1167 return ret; 1168 } 1169 1170 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 1171 { 1172 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1173 int vector_id; 1174 1175 vector_id = hclgevf_get_vector_index(hdev, vector); 1176 if (vector_id < 0) { 1177 dev_err(&handle->pdev->dev, 1178 "hclgevf_put_vector get vector index fail. ret =%d\n", 1179 vector_id); 1180 return vector_id; 1181 } 1182 1183 hclgevf_free_vector(hdev, vector_id); 1184 1185 return 0; 1186 } 1187 1188 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1189 bool en_uc_pmc, bool en_mc_pmc, 1190 bool en_bc_pmc) 1191 { 1192 struct hnae3_handle *handle = &hdev->nic; 1193 struct hclge_vf_to_pf_msg send_msg; 1194 int ret; 1195 1196 memset(&send_msg, 0, sizeof(send_msg)); 1197 send_msg.code = HCLGE_MBX_SET_PROMISC_MODE; 1198 send_msg.en_bc = en_bc_pmc ? 1 : 0; 1199 send_msg.en_uc = en_uc_pmc ? 1 : 0; 1200 send_msg.en_mc = en_mc_pmc ? 1 : 0; 1201 send_msg.en_limit_promisc = test_bit(HNAE3_PFLAG_LIMIT_PROMISC, 1202 &handle->priv_flags) ? 1 : 0; 1203 1204 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1205 if (ret) 1206 dev_err(&hdev->pdev->dev, 1207 "Set promisc mode fail, status is %d.\n", ret); 1208 1209 return ret; 1210 } 1211 1212 static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 1213 bool en_mc_pmc) 1214 { 1215 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1216 bool en_bc_pmc; 1217 1218 en_bc_pmc = hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2; 1219 1220 return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc, 1221 en_bc_pmc); 1222 } 1223 1224 static void hclgevf_request_update_promisc_mode(struct hnae3_handle *handle) 1225 { 1226 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1227 1228 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 1229 hclgevf_task_schedule(hdev, 0); 1230 } 1231 1232 static void hclgevf_sync_promisc_mode(struct hclgevf_dev *hdev) 1233 { 1234 struct hnae3_handle *handle = &hdev->nic; 1235 bool en_uc_pmc = handle->netdev_flags & HNAE3_UPE; 1236 bool en_mc_pmc = handle->netdev_flags & HNAE3_MPE; 1237 int ret; 1238 1239 if (test_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state)) { 1240 ret = hclgevf_set_promisc_mode(handle, en_uc_pmc, en_mc_pmc); 1241 if (!ret) 1242 clear_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 1243 } 1244 } 1245 1246 static int hclgevf_tqp_enable_cmd_send(struct hclgevf_dev *hdev, u16 tqp_id, 1247 u16 stream_id, bool enable) 1248 { 1249 struct hclgevf_cfg_com_tqp_queue_cmd *req; 1250 struct hclgevf_desc desc; 1251 1252 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1253 1254 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1255 false); 1256 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1257 req->stream_id = cpu_to_le16(stream_id); 1258 if (enable) 1259 req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 1260 1261 return hclgevf_cmd_send(&hdev->hw, &desc, 1); 1262 } 1263 1264 static int hclgevf_tqp_enable(struct hnae3_handle *handle, bool enable) 1265 { 1266 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1267 int ret; 1268 u16 i; 1269 1270 for (i = 0; i < handle->kinfo.num_tqps; i++) { 1271 ret = hclgevf_tqp_enable_cmd_send(hdev, i, 0, enable); 1272 if (ret) 1273 return ret; 1274 } 1275 1276 return 0; 1277 } 1278 1279 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1280 { 1281 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1282 struct hclgevf_tqp *tqp; 1283 int i; 1284 1285 for (i = 0; i < kinfo->num_tqps; i++) { 1286 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1287 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1288 } 1289 } 1290 1291 static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p) 1292 { 1293 struct hclge_vf_to_pf_msg send_msg; 1294 u8 host_mac[ETH_ALEN]; 1295 int status; 1296 1297 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MAC_ADDR, 0); 1298 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, host_mac, 1299 ETH_ALEN); 1300 if (status) { 1301 dev_err(&hdev->pdev->dev, 1302 "fail to get VF MAC from host %d", status); 1303 return status; 1304 } 1305 1306 ether_addr_copy(p, host_mac); 1307 1308 return 0; 1309 } 1310 1311 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1312 { 1313 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1314 u8 host_mac_addr[ETH_ALEN]; 1315 1316 if (hclgevf_get_host_mac_addr(hdev, host_mac_addr)) 1317 return; 1318 1319 hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr); 1320 if (hdev->has_pf_mac) 1321 ether_addr_copy(p, host_mac_addr); 1322 else 1323 ether_addr_copy(p, hdev->hw.mac.mac_addr); 1324 } 1325 1326 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 1327 bool is_first) 1328 { 1329 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1330 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1331 struct hclge_vf_to_pf_msg send_msg; 1332 u8 *new_mac_addr = (u8 *)p; 1333 int status; 1334 1335 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 0); 1336 send_msg.subcode = HCLGE_MBX_MAC_VLAN_UC_MODIFY; 1337 ether_addr_copy(send_msg.data, new_mac_addr); 1338 if (is_first && !hdev->has_pf_mac) 1339 eth_zero_addr(&send_msg.data[ETH_ALEN]); 1340 else 1341 ether_addr_copy(&send_msg.data[ETH_ALEN], old_mac_addr); 1342 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1343 if (!status) 1344 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1345 1346 return status; 1347 } 1348 1349 static struct hclgevf_mac_addr_node * 1350 hclgevf_find_mac_node(struct list_head *list, const u8 *mac_addr) 1351 { 1352 struct hclgevf_mac_addr_node *mac_node, *tmp; 1353 1354 list_for_each_entry_safe(mac_node, tmp, list, node) 1355 if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 1356 return mac_node; 1357 1358 return NULL; 1359 } 1360 1361 static void hclgevf_update_mac_node(struct hclgevf_mac_addr_node *mac_node, 1362 enum HCLGEVF_MAC_NODE_STATE state) 1363 { 1364 switch (state) { 1365 /* from set_rx_mode or tmp_add_list */ 1366 case HCLGEVF_MAC_TO_ADD: 1367 if (mac_node->state == HCLGEVF_MAC_TO_DEL) 1368 mac_node->state = HCLGEVF_MAC_ACTIVE; 1369 break; 1370 /* only from set_rx_mode */ 1371 case HCLGEVF_MAC_TO_DEL: 1372 if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1373 list_del(&mac_node->node); 1374 kfree(mac_node); 1375 } else { 1376 mac_node->state = HCLGEVF_MAC_TO_DEL; 1377 } 1378 break; 1379 /* only from tmp_add_list, the mac_node->state won't be 1380 * HCLGEVF_MAC_ACTIVE 1381 */ 1382 case HCLGEVF_MAC_ACTIVE: 1383 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1384 mac_node->state = HCLGEVF_MAC_ACTIVE; 1385 break; 1386 } 1387 } 1388 1389 static int hclgevf_update_mac_list(struct hnae3_handle *handle, 1390 enum HCLGEVF_MAC_NODE_STATE state, 1391 enum HCLGEVF_MAC_ADDR_TYPE mac_type, 1392 const unsigned char *addr) 1393 { 1394 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1395 struct hclgevf_mac_addr_node *mac_node; 1396 struct list_head *list; 1397 1398 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1399 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1400 1401 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1402 1403 /* if the mac addr is already in the mac list, no need to add a new 1404 * one into it, just check the mac addr state, convert it to a new 1405 * new state, or just remove it, or do nothing. 1406 */ 1407 mac_node = hclgevf_find_mac_node(list, addr); 1408 if (mac_node) { 1409 hclgevf_update_mac_node(mac_node, state); 1410 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1411 return 0; 1412 } 1413 /* if this address is never added, unnecessary to delete */ 1414 if (state == HCLGEVF_MAC_TO_DEL) { 1415 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1416 return -ENOENT; 1417 } 1418 1419 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 1420 if (!mac_node) { 1421 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1422 return -ENOMEM; 1423 } 1424 1425 mac_node->state = state; 1426 ether_addr_copy(mac_node->mac_addr, addr); 1427 list_add_tail(&mac_node->node, list); 1428 1429 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1430 return 0; 1431 } 1432 1433 static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1434 const unsigned char *addr) 1435 { 1436 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1437 HCLGEVF_MAC_ADDR_UC, addr); 1438 } 1439 1440 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1441 const unsigned char *addr) 1442 { 1443 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1444 HCLGEVF_MAC_ADDR_UC, addr); 1445 } 1446 1447 static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1448 const unsigned char *addr) 1449 { 1450 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1451 HCLGEVF_MAC_ADDR_MC, addr); 1452 } 1453 1454 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1455 const unsigned char *addr) 1456 { 1457 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1458 HCLGEVF_MAC_ADDR_MC, addr); 1459 } 1460 1461 static int hclgevf_add_del_mac_addr(struct hclgevf_dev *hdev, 1462 struct hclgevf_mac_addr_node *mac_node, 1463 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1464 { 1465 struct hclge_vf_to_pf_msg send_msg; 1466 u8 code, subcode; 1467 1468 if (mac_type == HCLGEVF_MAC_ADDR_UC) { 1469 code = HCLGE_MBX_SET_UNICAST; 1470 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1471 subcode = HCLGE_MBX_MAC_VLAN_UC_ADD; 1472 else 1473 subcode = HCLGE_MBX_MAC_VLAN_UC_REMOVE; 1474 } else { 1475 code = HCLGE_MBX_SET_MULTICAST; 1476 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1477 subcode = HCLGE_MBX_MAC_VLAN_MC_ADD; 1478 else 1479 subcode = HCLGE_MBX_MAC_VLAN_MC_REMOVE; 1480 } 1481 1482 hclgevf_build_send_msg(&send_msg, code, subcode); 1483 ether_addr_copy(send_msg.data, mac_node->mac_addr); 1484 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1485 } 1486 1487 static void hclgevf_config_mac_list(struct hclgevf_dev *hdev, 1488 struct list_head *list, 1489 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1490 { 1491 struct hclgevf_mac_addr_node *mac_node, *tmp; 1492 int ret; 1493 1494 list_for_each_entry_safe(mac_node, tmp, list, node) { 1495 ret = hclgevf_add_del_mac_addr(hdev, mac_node, mac_type); 1496 if (ret) { 1497 dev_err(&hdev->pdev->dev, 1498 "failed to configure mac %pM, state = %d, ret = %d\n", 1499 mac_node->mac_addr, mac_node->state, ret); 1500 return; 1501 } 1502 if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1503 mac_node->state = HCLGEVF_MAC_ACTIVE; 1504 } else { 1505 list_del(&mac_node->node); 1506 kfree(mac_node); 1507 } 1508 } 1509 } 1510 1511 static void hclgevf_sync_from_add_list(struct list_head *add_list, 1512 struct list_head *mac_list) 1513 { 1514 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1515 1516 list_for_each_entry_safe(mac_node, tmp, add_list, node) { 1517 /* if the mac address from tmp_add_list is not in the 1518 * uc/mc_mac_list, it means have received a TO_DEL request 1519 * during the time window of sending mac config request to PF 1520 * If mac_node state is ACTIVE, then change its state to TO_DEL, 1521 * then it will be removed at next time. If is TO_ADD, it means 1522 * send TO_ADD request failed, so just remove the mac node. 1523 */ 1524 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1525 if (new_node) { 1526 hclgevf_update_mac_node(new_node, mac_node->state); 1527 list_del(&mac_node->node); 1528 kfree(mac_node); 1529 } else if (mac_node->state == HCLGEVF_MAC_ACTIVE) { 1530 mac_node->state = HCLGEVF_MAC_TO_DEL; 1531 list_del(&mac_node->node); 1532 list_add_tail(&mac_node->node, mac_list); 1533 } else { 1534 list_del(&mac_node->node); 1535 kfree(mac_node); 1536 } 1537 } 1538 } 1539 1540 static void hclgevf_sync_from_del_list(struct list_head *del_list, 1541 struct list_head *mac_list) 1542 { 1543 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1544 1545 list_for_each_entry_safe(mac_node, tmp, del_list, node) { 1546 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1547 if (new_node) { 1548 /* If the mac addr is exist in the mac list, it means 1549 * received a new request TO_ADD during the time window 1550 * of sending mac addr configurrequest to PF, so just 1551 * change the mac state to ACTIVE. 1552 */ 1553 new_node->state = HCLGEVF_MAC_ACTIVE; 1554 list_del(&mac_node->node); 1555 kfree(mac_node); 1556 } else { 1557 list_del(&mac_node->node); 1558 list_add_tail(&mac_node->node, mac_list); 1559 } 1560 } 1561 } 1562 1563 static void hclgevf_clear_list(struct list_head *list) 1564 { 1565 struct hclgevf_mac_addr_node *mac_node, *tmp; 1566 1567 list_for_each_entry_safe(mac_node, tmp, list, node) { 1568 list_del(&mac_node->node); 1569 kfree(mac_node); 1570 } 1571 } 1572 1573 static void hclgevf_sync_mac_list(struct hclgevf_dev *hdev, 1574 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1575 { 1576 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1577 struct list_head tmp_add_list, tmp_del_list; 1578 struct list_head *list; 1579 1580 INIT_LIST_HEAD(&tmp_add_list); 1581 INIT_LIST_HEAD(&tmp_del_list); 1582 1583 /* move the mac addr to the tmp_add_list and tmp_del_list, then 1584 * we can add/delete these mac addr outside the spin lock 1585 */ 1586 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1587 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1588 1589 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1590 1591 list_for_each_entry_safe(mac_node, tmp, list, node) { 1592 switch (mac_node->state) { 1593 case HCLGEVF_MAC_TO_DEL: 1594 list_del(&mac_node->node); 1595 list_add_tail(&mac_node->node, &tmp_del_list); 1596 break; 1597 case HCLGEVF_MAC_TO_ADD: 1598 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 1599 if (!new_node) 1600 goto stop_traverse; 1601 1602 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 1603 new_node->state = mac_node->state; 1604 list_add_tail(&new_node->node, &tmp_add_list); 1605 break; 1606 default: 1607 break; 1608 } 1609 } 1610 1611 stop_traverse: 1612 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1613 1614 /* delete first, in order to get max mac table space for adding */ 1615 hclgevf_config_mac_list(hdev, &tmp_del_list, mac_type); 1616 hclgevf_config_mac_list(hdev, &tmp_add_list, mac_type); 1617 1618 /* if some mac addresses were added/deleted fail, move back to the 1619 * mac_list, and retry at next time. 1620 */ 1621 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1622 1623 hclgevf_sync_from_del_list(&tmp_del_list, list); 1624 hclgevf_sync_from_add_list(&tmp_add_list, list); 1625 1626 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1627 } 1628 1629 static void hclgevf_sync_mac_table(struct hclgevf_dev *hdev) 1630 { 1631 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_UC); 1632 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_MC); 1633 } 1634 1635 static void hclgevf_uninit_mac_list(struct hclgevf_dev *hdev) 1636 { 1637 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1638 1639 hclgevf_clear_list(&hdev->mac_table.uc_mac_list); 1640 hclgevf_clear_list(&hdev->mac_table.mc_mac_list); 1641 1642 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1643 } 1644 1645 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1646 __be16 proto, u16 vlan_id, 1647 bool is_kill) 1648 { 1649 #define HCLGEVF_VLAN_MBX_IS_KILL_OFFSET 0 1650 #define HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET 1 1651 #define HCLGEVF_VLAN_MBX_PROTO_OFFSET 3 1652 1653 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1654 struct hclge_vf_to_pf_msg send_msg; 1655 int ret; 1656 1657 if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1658 return -EINVAL; 1659 1660 if (proto != htons(ETH_P_8021Q)) 1661 return -EPROTONOSUPPORT; 1662 1663 /* When device is resetting or reset failed, firmware is unable to 1664 * handle mailbox. Just record the vlan id, and remove it after 1665 * reset finished. 1666 */ 1667 if ((test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 1668 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) && is_kill) { 1669 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1670 return -EBUSY; 1671 } 1672 1673 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1674 HCLGE_MBX_VLAN_FILTER); 1675 send_msg.data[HCLGEVF_VLAN_MBX_IS_KILL_OFFSET] = is_kill; 1676 memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET], &vlan_id, 1677 sizeof(vlan_id)); 1678 memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_PROTO_OFFSET], &proto, 1679 sizeof(proto)); 1680 /* when remove hw vlan filter failed, record the vlan id, 1681 * and try to remove it from hw later, to be consistence 1682 * with stack. 1683 */ 1684 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1685 if (is_kill && ret) 1686 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1687 1688 return ret; 1689 } 1690 1691 static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1692 { 1693 #define HCLGEVF_MAX_SYNC_COUNT 60 1694 struct hnae3_handle *handle = &hdev->nic; 1695 int ret, sync_cnt = 0; 1696 u16 vlan_id; 1697 1698 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1699 while (vlan_id != VLAN_N_VID) { 1700 ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1701 vlan_id, true); 1702 if (ret) 1703 return; 1704 1705 clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1706 sync_cnt++; 1707 if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1708 return; 1709 1710 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1711 } 1712 } 1713 1714 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1715 { 1716 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1717 struct hclge_vf_to_pf_msg send_msg; 1718 1719 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1720 HCLGE_MBX_VLAN_RX_OFF_CFG); 1721 send_msg.data[0] = enable ? 1 : 0; 1722 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1723 } 1724 1725 static int hclgevf_reset_tqp(struct hnae3_handle *handle) 1726 { 1727 #define HCLGEVF_RESET_ALL_QUEUE_DONE 1U 1728 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1729 struct hclge_vf_to_pf_msg send_msg; 1730 u8 return_status = 0; 1731 int ret; 1732 u16 i; 1733 1734 /* disable vf queue before send queue reset msg to PF */ 1735 ret = hclgevf_tqp_enable(handle, false); 1736 if (ret) { 1737 dev_err(&hdev->pdev->dev, "failed to disable tqp, ret = %d\n", 1738 ret); 1739 return ret; 1740 } 1741 1742 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 1743 1744 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &return_status, 1745 sizeof(return_status)); 1746 if (ret || return_status == HCLGEVF_RESET_ALL_QUEUE_DONE) 1747 return ret; 1748 1749 for (i = 1; i < handle->kinfo.num_tqps; i++) { 1750 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 1751 memcpy(send_msg.data, &i, sizeof(i)); 1752 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1753 if (ret) 1754 return ret; 1755 } 1756 1757 return 0; 1758 } 1759 1760 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1761 { 1762 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1763 struct hclge_vf_to_pf_msg send_msg; 1764 1765 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MTU, 0); 1766 memcpy(send_msg.data, &new_mtu, sizeof(new_mtu)); 1767 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1768 } 1769 1770 static int hclgevf_notify_client(struct hclgevf_dev *hdev, 1771 enum hnae3_reset_notify_type type) 1772 { 1773 struct hnae3_client *client = hdev->nic_client; 1774 struct hnae3_handle *handle = &hdev->nic; 1775 int ret; 1776 1777 if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 1778 !client) 1779 return 0; 1780 1781 if (!client->ops->reset_notify) 1782 return -EOPNOTSUPP; 1783 1784 ret = client->ops->reset_notify(handle, type); 1785 if (ret) 1786 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 1787 type, ret); 1788 1789 return ret; 1790 } 1791 1792 static int hclgevf_notify_roce_client(struct hclgevf_dev *hdev, 1793 enum hnae3_reset_notify_type type) 1794 { 1795 struct hnae3_client *client = hdev->roce_client; 1796 struct hnae3_handle *handle = &hdev->roce; 1797 int ret; 1798 1799 if (!test_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state) || !client) 1800 return 0; 1801 1802 if (!client->ops->reset_notify) 1803 return -EOPNOTSUPP; 1804 1805 ret = client->ops->reset_notify(handle, type); 1806 if (ret) 1807 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 1808 type, ret); 1809 return ret; 1810 } 1811 1812 static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 1813 { 1814 #define HCLGEVF_RESET_WAIT_US 20000 1815 #define HCLGEVF_RESET_WAIT_CNT 2000 1816 #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1817 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1818 1819 u32 val; 1820 int ret; 1821 1822 if (hdev->reset_type == HNAE3_VF_RESET) 1823 ret = readl_poll_timeout(hdev->hw.io_base + 1824 HCLGEVF_VF_RST_ING, val, 1825 !(val & HCLGEVF_VF_RST_ING_BIT), 1826 HCLGEVF_RESET_WAIT_US, 1827 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1828 else 1829 ret = readl_poll_timeout(hdev->hw.io_base + 1830 HCLGEVF_RST_ING, val, 1831 !(val & HCLGEVF_RST_ING_BITS), 1832 HCLGEVF_RESET_WAIT_US, 1833 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1834 1835 /* hardware completion status should be available by this time */ 1836 if (ret) { 1837 dev_err(&hdev->pdev->dev, 1838 "couldn't get reset done status from h/w, timeout!\n"); 1839 return ret; 1840 } 1841 1842 /* we will wait a bit more to let reset of the stack to complete. This 1843 * might happen in case reset assertion was made by PF. Yes, this also 1844 * means we might end up waiting bit more even for VF reset. 1845 */ 1846 msleep(5000); 1847 1848 return 0; 1849 } 1850 1851 static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable) 1852 { 1853 u32 reg_val; 1854 1855 reg_val = hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG); 1856 if (enable) 1857 reg_val |= HCLGEVF_NIC_SW_RST_RDY; 1858 else 1859 reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; 1860 1861 hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 1862 reg_val); 1863 } 1864 1865 static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 1866 { 1867 int ret; 1868 1869 /* uninitialize the nic client */ 1870 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 1871 if (ret) 1872 return ret; 1873 1874 /* re-initialize the hclge device */ 1875 ret = hclgevf_reset_hdev(hdev); 1876 if (ret) { 1877 dev_err(&hdev->pdev->dev, 1878 "hclge device re-init failed, VF is disabled!\n"); 1879 return ret; 1880 } 1881 1882 /* bring up the nic client again */ 1883 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 1884 if (ret) 1885 return ret; 1886 1887 /* clear handshake status with IMP */ 1888 hclgevf_reset_handshake(hdev, false); 1889 1890 /* bring up the nic to enable TX/RX again */ 1891 return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 1892 } 1893 1894 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1895 { 1896 #define HCLGEVF_RESET_SYNC_TIME 100 1897 1898 if (hdev->reset_type == HNAE3_VF_FUNC_RESET) { 1899 struct hclge_vf_to_pf_msg send_msg; 1900 int ret; 1901 1902 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_RESET, 0); 1903 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1904 if (ret) { 1905 dev_err(&hdev->pdev->dev, 1906 "failed to assert VF reset, ret = %d\n", ret); 1907 return ret; 1908 } 1909 hdev->rst_stats.vf_func_rst_cnt++; 1910 } 1911 1912 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1913 /* inform hardware that preparatory work is done */ 1914 msleep(HCLGEVF_RESET_SYNC_TIME); 1915 hclgevf_reset_handshake(hdev, true); 1916 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done\n", 1917 hdev->reset_type); 1918 1919 return 0; 1920 } 1921 1922 static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev) 1923 { 1924 dev_info(&hdev->pdev->dev, "VF function reset count: %u\n", 1925 hdev->rst_stats.vf_func_rst_cnt); 1926 dev_info(&hdev->pdev->dev, "FLR reset count: %u\n", 1927 hdev->rst_stats.flr_rst_cnt); 1928 dev_info(&hdev->pdev->dev, "VF reset count: %u\n", 1929 hdev->rst_stats.vf_rst_cnt); 1930 dev_info(&hdev->pdev->dev, "reset done count: %u\n", 1931 hdev->rst_stats.rst_done_cnt); 1932 dev_info(&hdev->pdev->dev, "HW reset done count: %u\n", 1933 hdev->rst_stats.hw_rst_done_cnt); 1934 dev_info(&hdev->pdev->dev, "reset count: %u\n", 1935 hdev->rst_stats.rst_cnt); 1936 dev_info(&hdev->pdev->dev, "reset fail count: %u\n", 1937 hdev->rst_stats.rst_fail_cnt); 1938 dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n", 1939 hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE)); 1940 dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n", 1941 hclgevf_read_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_STATE_REG)); 1942 dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n", 1943 hclgevf_read_dev(&hdev->hw, HCLGEVF_CMDQ_TX_DEPTH_REG)); 1944 dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n", 1945 hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING)); 1946 dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state); 1947 } 1948 1949 static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1950 { 1951 /* recover handshake status with IMP when reset fail */ 1952 hclgevf_reset_handshake(hdev, true); 1953 hdev->rst_stats.rst_fail_cnt++; 1954 dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n", 1955 hdev->rst_stats.rst_fail_cnt); 1956 1957 if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1958 set_bit(hdev->reset_type, &hdev->reset_pending); 1959 1960 if (hclgevf_is_reset_pending(hdev)) { 1961 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1962 hclgevf_reset_task_schedule(hdev); 1963 } else { 1964 set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1965 hclgevf_dump_rst_info(hdev); 1966 } 1967 } 1968 1969 static int hclgevf_reset_prepare(struct hclgevf_dev *hdev) 1970 { 1971 int ret; 1972 1973 hdev->rst_stats.rst_cnt++; 1974 1975 /* perform reset of the stack & ae device for a client */ 1976 ret = hclgevf_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 1977 if (ret) 1978 return ret; 1979 1980 rtnl_lock(); 1981 /* bring down the nic to stop any ongoing TX/RX */ 1982 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 1983 rtnl_unlock(); 1984 if (ret) 1985 return ret; 1986 1987 return hclgevf_reset_prepare_wait(hdev); 1988 } 1989 1990 static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev) 1991 { 1992 int ret; 1993 1994 hdev->rst_stats.hw_rst_done_cnt++; 1995 ret = hclgevf_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 1996 if (ret) 1997 return ret; 1998 1999 rtnl_lock(); 2000 /* now, re-initialize the nic client and ae device */ 2001 ret = hclgevf_reset_stack(hdev); 2002 rtnl_unlock(); 2003 if (ret) { 2004 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 2005 return ret; 2006 } 2007 2008 ret = hclgevf_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 2009 /* ignore RoCE notify error if it fails HCLGEVF_RESET_MAX_FAIL_CNT - 1 2010 * times 2011 */ 2012 if (ret && 2013 hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT - 1) 2014 return ret; 2015 2016 ret = hclgevf_notify_roce_client(hdev, HNAE3_UP_CLIENT); 2017 if (ret) 2018 return ret; 2019 2020 hdev->last_reset_time = jiffies; 2021 hdev->rst_stats.rst_done_cnt++; 2022 hdev->rst_stats.rst_fail_cnt = 0; 2023 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 2024 2025 return 0; 2026 } 2027 2028 static void hclgevf_reset(struct hclgevf_dev *hdev) 2029 { 2030 if (hclgevf_reset_prepare(hdev)) 2031 goto err_reset; 2032 2033 /* check if VF could successfully fetch the hardware reset completion 2034 * status from the hardware 2035 */ 2036 if (hclgevf_reset_wait(hdev)) { 2037 /* can't do much in this situation, will disable VF */ 2038 dev_err(&hdev->pdev->dev, 2039 "failed to fetch H/W reset completion status\n"); 2040 goto err_reset; 2041 } 2042 2043 if (hclgevf_reset_rebuild(hdev)) 2044 goto err_reset; 2045 2046 return; 2047 2048 err_reset: 2049 hclgevf_reset_err_handle(hdev); 2050 } 2051 2052 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 2053 unsigned long *addr) 2054 { 2055 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 2056 2057 /* return the highest priority reset level amongst all */ 2058 if (test_bit(HNAE3_VF_RESET, addr)) { 2059 rst_level = HNAE3_VF_RESET; 2060 clear_bit(HNAE3_VF_RESET, addr); 2061 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 2062 clear_bit(HNAE3_VF_FUNC_RESET, addr); 2063 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 2064 rst_level = HNAE3_VF_FULL_RESET; 2065 clear_bit(HNAE3_VF_FULL_RESET, addr); 2066 clear_bit(HNAE3_VF_FUNC_RESET, addr); 2067 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 2068 rst_level = HNAE3_VF_PF_FUNC_RESET; 2069 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 2070 clear_bit(HNAE3_VF_FUNC_RESET, addr); 2071 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 2072 rst_level = HNAE3_VF_FUNC_RESET; 2073 clear_bit(HNAE3_VF_FUNC_RESET, addr); 2074 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 2075 rst_level = HNAE3_FLR_RESET; 2076 clear_bit(HNAE3_FLR_RESET, addr); 2077 } 2078 2079 return rst_level; 2080 } 2081 2082 static void hclgevf_reset_event(struct pci_dev *pdev, 2083 struct hnae3_handle *handle) 2084 { 2085 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2086 struct hclgevf_dev *hdev = ae_dev->priv; 2087 2088 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 2089 2090 if (hdev->default_reset_request) 2091 hdev->reset_level = 2092 hclgevf_get_reset_level(hdev, 2093 &hdev->default_reset_request); 2094 else 2095 hdev->reset_level = HNAE3_VF_FUNC_RESET; 2096 2097 /* reset of this VF requested */ 2098 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 2099 hclgevf_reset_task_schedule(hdev); 2100 2101 hdev->last_reset_time = jiffies; 2102 } 2103 2104 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 2105 enum hnae3_reset_type rst_type) 2106 { 2107 struct hclgevf_dev *hdev = ae_dev->priv; 2108 2109 set_bit(rst_type, &hdev->default_reset_request); 2110 } 2111 2112 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 2113 { 2114 writel(en ? 1 : 0, vector->addr); 2115 } 2116 2117 static void hclgevf_reset_prepare_general(struct hnae3_ae_dev *ae_dev, 2118 enum hnae3_reset_type rst_type) 2119 { 2120 #define HCLGEVF_RESET_RETRY_WAIT_MS 500 2121 #define HCLGEVF_RESET_RETRY_CNT 5 2122 2123 struct hclgevf_dev *hdev = ae_dev->priv; 2124 int retry_cnt = 0; 2125 int ret; 2126 2127 retry: 2128 down(&hdev->reset_sem); 2129 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2130 hdev->reset_type = rst_type; 2131 ret = hclgevf_reset_prepare(hdev); 2132 if (ret) { 2133 dev_err(&hdev->pdev->dev, "fail to prepare to reset, ret=%d\n", 2134 ret); 2135 if (hdev->reset_pending || 2136 retry_cnt++ < HCLGEVF_RESET_RETRY_CNT) { 2137 dev_err(&hdev->pdev->dev, 2138 "reset_pending:0x%lx, retry_cnt:%d\n", 2139 hdev->reset_pending, retry_cnt); 2140 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2141 up(&hdev->reset_sem); 2142 msleep(HCLGEVF_RESET_RETRY_WAIT_MS); 2143 goto retry; 2144 } 2145 } 2146 2147 /* disable misc vector before reset done */ 2148 hclgevf_enable_vector(&hdev->misc_vector, false); 2149 2150 if (hdev->reset_type == HNAE3_FLR_RESET) 2151 hdev->rst_stats.flr_rst_cnt++; 2152 } 2153 2154 static void hclgevf_reset_done(struct hnae3_ae_dev *ae_dev) 2155 { 2156 struct hclgevf_dev *hdev = ae_dev->priv; 2157 int ret; 2158 2159 hclgevf_enable_vector(&hdev->misc_vector, true); 2160 2161 ret = hclgevf_reset_rebuild(hdev); 2162 if (ret) 2163 dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", 2164 ret); 2165 2166 hdev->reset_type = HNAE3_NONE_RESET; 2167 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2168 up(&hdev->reset_sem); 2169 } 2170 2171 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 2172 { 2173 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2174 2175 return hdev->fw_version; 2176 } 2177 2178 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 2179 { 2180 struct hclgevf_misc_vector *vector = &hdev->misc_vector; 2181 2182 vector->vector_irq = pci_irq_vector(hdev->pdev, 2183 HCLGEVF_MISC_VECTOR_NUM); 2184 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 2185 /* vector status always valid for Vector 0 */ 2186 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 2187 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 2188 2189 hdev->num_msi_left -= 1; 2190 hdev->num_msi_used += 1; 2191 } 2192 2193 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 2194 { 2195 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2196 !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, 2197 &hdev->state)) 2198 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 2199 } 2200 2201 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 2202 { 2203 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2204 !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, 2205 &hdev->state)) 2206 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 2207 } 2208 2209 static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 2210 unsigned long delay) 2211 { 2212 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2213 !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 2214 mod_delayed_work(hclgevf_wq, &hdev->service_task, delay); 2215 } 2216 2217 static void hclgevf_reset_service_task(struct hclgevf_dev *hdev) 2218 { 2219 #define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3 2220 2221 if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state)) 2222 return; 2223 2224 down(&hdev->reset_sem); 2225 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2226 2227 if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 2228 &hdev->reset_state)) { 2229 /* PF has intimated that it is about to reset the hardware. 2230 * We now have to poll & check if hardware has actually 2231 * completed the reset sequence. On hardware reset completion, 2232 * VF needs to reset the client and ae device. 2233 */ 2234 hdev->reset_attempts = 0; 2235 2236 hdev->last_reset_time = jiffies; 2237 while ((hdev->reset_type = 2238 hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 2239 != HNAE3_NONE_RESET) 2240 hclgevf_reset(hdev); 2241 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 2242 &hdev->reset_state)) { 2243 /* we could be here when either of below happens: 2244 * 1. reset was initiated due to watchdog timeout caused by 2245 * a. IMP was earlier reset and our TX got choked down and 2246 * which resulted in watchdog reacting and inducing VF 2247 * reset. This also means our cmdq would be unreliable. 2248 * b. problem in TX due to other lower layer(example link 2249 * layer not functioning properly etc.) 2250 * 2. VF reset might have been initiated due to some config 2251 * change. 2252 * 2253 * NOTE: Theres no clear way to detect above cases than to react 2254 * to the response of PF for this reset request. PF will ack the 2255 * 1b and 2. cases but we will not get any intimation about 1a 2256 * from PF as cmdq would be in unreliable state i.e. mailbox 2257 * communication between PF and VF would be broken. 2258 * 2259 * if we are never geting into pending state it means either: 2260 * 1. PF is not receiving our request which could be due to IMP 2261 * reset 2262 * 2. PF is screwed 2263 * We cannot do much for 2. but to check first we can try reset 2264 * our PCIe + stack and see if it alleviates the problem. 2265 */ 2266 if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) { 2267 /* prepare for full reset of stack + pcie interface */ 2268 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 2269 2270 /* "defer" schedule the reset task again */ 2271 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2272 } else { 2273 hdev->reset_attempts++; 2274 2275 set_bit(hdev->reset_level, &hdev->reset_pending); 2276 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2277 } 2278 hclgevf_reset_task_schedule(hdev); 2279 } 2280 2281 hdev->reset_type = HNAE3_NONE_RESET; 2282 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2283 up(&hdev->reset_sem); 2284 } 2285 2286 static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev) 2287 { 2288 if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state)) 2289 return; 2290 2291 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 2292 return; 2293 2294 hclgevf_mbx_async_handler(hdev); 2295 2296 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2297 } 2298 2299 static void hclgevf_keep_alive(struct hclgevf_dev *hdev) 2300 { 2301 struct hclge_vf_to_pf_msg send_msg; 2302 int ret; 2303 2304 if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 2305 return; 2306 2307 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_KEEP_ALIVE, 0); 2308 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2309 if (ret) 2310 dev_err(&hdev->pdev->dev, 2311 "VF sends keep alive cmd failed(=%d)\n", ret); 2312 } 2313 2314 static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev) 2315 { 2316 unsigned long delta = round_jiffies_relative(HZ); 2317 struct hnae3_handle *handle = &hdev->nic; 2318 2319 if (test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 2320 return; 2321 2322 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 2323 delta = jiffies - hdev->last_serv_processed; 2324 2325 if (delta < round_jiffies_relative(HZ)) { 2326 delta = round_jiffies_relative(HZ) - delta; 2327 goto out; 2328 } 2329 } 2330 2331 hdev->serv_processed_cnt++; 2332 if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL)) 2333 hclgevf_keep_alive(hdev); 2334 2335 if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) { 2336 hdev->last_serv_processed = jiffies; 2337 goto out; 2338 } 2339 2340 if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL)) 2341 hclgevf_tqps_update_stats(handle); 2342 2343 /* VF does not need to request link status when this bit is set, because 2344 * PF will push its link status to VFs when link status changed. 2345 */ 2346 if (!test_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state)) 2347 hclgevf_request_link_info(hdev); 2348 2349 hclgevf_update_link_mode(hdev); 2350 2351 hclgevf_sync_vlan_filter(hdev); 2352 2353 hclgevf_sync_mac_table(hdev); 2354 2355 hclgevf_sync_promisc_mode(hdev); 2356 2357 hdev->last_serv_processed = jiffies; 2358 2359 out: 2360 hclgevf_task_schedule(hdev, delta); 2361 } 2362 2363 static void hclgevf_service_task(struct work_struct *work) 2364 { 2365 struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev, 2366 service_task.work); 2367 2368 hclgevf_reset_service_task(hdev); 2369 hclgevf_mailbox_service_task(hdev); 2370 hclgevf_periodic_service_task(hdev); 2371 2372 /* Handle reset and mbx again in case periodical task delays the 2373 * handling by calling hclgevf_task_schedule() in 2374 * hclgevf_periodic_service_task() 2375 */ 2376 hclgevf_reset_service_task(hdev); 2377 hclgevf_mailbox_service_task(hdev); 2378 } 2379 2380 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 2381 { 2382 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 2383 } 2384 2385 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 2386 u32 *clearval) 2387 { 2388 u32 val, cmdq_stat_reg, rst_ing_reg; 2389 2390 /* fetch the events from their corresponding regs */ 2391 cmdq_stat_reg = hclgevf_read_dev(&hdev->hw, 2392 HCLGEVF_VECTOR0_CMDQ_STATE_REG); 2393 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 2394 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 2395 dev_info(&hdev->pdev->dev, 2396 "receive reset interrupt 0x%x!\n", rst_ing_reg); 2397 set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 2398 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2399 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 2400 *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B); 2401 hdev->rst_stats.vf_rst_cnt++; 2402 /* set up VF hardware reset status, its PF will clear 2403 * this status when PF has initialized done. 2404 */ 2405 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING); 2406 hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING, 2407 val | HCLGEVF_VF_RST_ING_BIT); 2408 return HCLGEVF_VECTOR0_EVENT_RST; 2409 } 2410 2411 /* check for vector0 mailbox(=CMDQ RX) event source */ 2412 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 2413 /* for revision 0x21, clearing interrupt is writing bit 0 2414 * to the clear register, writing bit 1 means to keep the 2415 * old value. 2416 * for revision 0x20, the clear register is a read & write 2417 * register, so we should just write 0 to the bit we are 2418 * handling, and keep other bits as cmdq_stat_reg. 2419 */ 2420 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) 2421 *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 2422 else 2423 *clearval = cmdq_stat_reg & 2424 ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 2425 2426 return HCLGEVF_VECTOR0_EVENT_MBX; 2427 } 2428 2429 /* print other vector0 event source */ 2430 dev_info(&hdev->pdev->dev, 2431 "vector 0 interrupt from unknown source, cmdq_src = %#x\n", 2432 cmdq_stat_reg); 2433 2434 return HCLGEVF_VECTOR0_EVENT_OTHER; 2435 } 2436 2437 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 2438 { 2439 enum hclgevf_evt_cause event_cause; 2440 struct hclgevf_dev *hdev = data; 2441 u32 clearval; 2442 2443 hclgevf_enable_vector(&hdev->misc_vector, false); 2444 event_cause = hclgevf_check_evt_cause(hdev, &clearval); 2445 2446 switch (event_cause) { 2447 case HCLGEVF_VECTOR0_EVENT_RST: 2448 hclgevf_reset_task_schedule(hdev); 2449 break; 2450 case HCLGEVF_VECTOR0_EVENT_MBX: 2451 hclgevf_mbx_handler(hdev); 2452 break; 2453 default: 2454 break; 2455 } 2456 2457 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 2458 hclgevf_clear_event_cause(hdev, clearval); 2459 hclgevf_enable_vector(&hdev->misc_vector, true); 2460 } 2461 2462 return IRQ_HANDLED; 2463 } 2464 2465 static int hclgevf_configure(struct hclgevf_dev *hdev) 2466 { 2467 int ret; 2468 2469 /* get current port based vlan state from PF */ 2470 ret = hclgevf_get_port_base_vlan_filter_state(hdev); 2471 if (ret) 2472 return ret; 2473 2474 /* get queue configuration from PF */ 2475 ret = hclgevf_get_queue_info(hdev); 2476 if (ret) 2477 return ret; 2478 2479 /* get queue depth info from PF */ 2480 ret = hclgevf_get_queue_depth(hdev); 2481 if (ret) 2482 return ret; 2483 2484 ret = hclgevf_get_pf_media_type(hdev); 2485 if (ret) 2486 return ret; 2487 2488 /* get tc configuration from PF */ 2489 return hclgevf_get_tc_info(hdev); 2490 } 2491 2492 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 2493 { 2494 struct pci_dev *pdev = ae_dev->pdev; 2495 struct hclgevf_dev *hdev; 2496 2497 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 2498 if (!hdev) 2499 return -ENOMEM; 2500 2501 hdev->pdev = pdev; 2502 hdev->ae_dev = ae_dev; 2503 ae_dev->priv = hdev; 2504 2505 return 0; 2506 } 2507 2508 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 2509 { 2510 struct hnae3_handle *roce = &hdev->roce; 2511 struct hnae3_handle *nic = &hdev->nic; 2512 2513 roce->rinfo.num_vectors = hdev->num_roce_msix; 2514 2515 if (hdev->num_msi_left < roce->rinfo.num_vectors || 2516 hdev->num_msi_left == 0) 2517 return -EINVAL; 2518 2519 roce->rinfo.base_vector = hdev->roce_base_vector; 2520 2521 roce->rinfo.netdev = nic->kinfo.netdev; 2522 roce->rinfo.roce_io_base = hdev->hw.io_base; 2523 roce->rinfo.roce_mem_base = hdev->hw.mem_base; 2524 2525 roce->pdev = nic->pdev; 2526 roce->ae_algo = nic->ae_algo; 2527 roce->numa_node_mask = nic->numa_node_mask; 2528 2529 return 0; 2530 } 2531 2532 static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 2533 { 2534 struct hclgevf_cfg_gro_status_cmd *req; 2535 struct hclgevf_desc desc; 2536 int ret; 2537 2538 if (!hnae3_dev_gro_supported(hdev)) 2539 return 0; 2540 2541 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 2542 false); 2543 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2544 2545 req->gro_en = en ? 1 : 0; 2546 2547 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2548 if (ret) 2549 dev_err(&hdev->pdev->dev, 2550 "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2551 2552 return ret; 2553 } 2554 2555 static int hclgevf_rss_init_cfg(struct hclgevf_dev *hdev) 2556 { 2557 u16 rss_ind_tbl_size = hdev->ae_dev->dev_specs.rss_ind_tbl_size; 2558 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2559 struct hclgevf_rss_tuple_cfg *tuple_sets; 2560 u32 i; 2561 2562 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 2563 rss_cfg->rss_size = hdev->nic.kinfo.rss_size; 2564 tuple_sets = &rss_cfg->rss_tuple_sets; 2565 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 2566 u8 *rss_ind_tbl; 2567 2568 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 2569 2570 rss_ind_tbl = devm_kcalloc(&hdev->pdev->dev, rss_ind_tbl_size, 2571 sizeof(*rss_ind_tbl), GFP_KERNEL); 2572 if (!rss_ind_tbl) 2573 return -ENOMEM; 2574 2575 rss_cfg->rss_indirection_tbl = rss_ind_tbl; 2576 memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 2577 HCLGEVF_RSS_KEY_SIZE); 2578 2579 tuple_sets->ipv4_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2580 tuple_sets->ipv4_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2581 tuple_sets->ipv4_sctp_en = HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2582 tuple_sets->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2583 tuple_sets->ipv6_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2584 tuple_sets->ipv6_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2585 tuple_sets->ipv6_sctp_en = 2586 hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 ? 2587 HCLGEVF_RSS_INPUT_TUPLE_SCTP_NO_PORT : 2588 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2589 tuple_sets->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2590 } 2591 2592 /* Initialize RSS indirect table */ 2593 for (i = 0; i < rss_ind_tbl_size; i++) 2594 rss_cfg->rss_indirection_tbl[i] = i % rss_cfg->rss_size; 2595 2596 return 0; 2597 } 2598 2599 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2600 { 2601 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2602 int ret; 2603 2604 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 2605 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 2606 rss_cfg->rss_hash_key); 2607 if (ret) 2608 return ret; 2609 2610 ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 2611 if (ret) 2612 return ret; 2613 } 2614 2615 ret = hclgevf_set_rss_indir_table(hdev); 2616 if (ret) 2617 return ret; 2618 2619 return hclgevf_set_rss_tc_mode(hdev, rss_cfg->rss_size); 2620 } 2621 2622 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2623 { 2624 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2625 false); 2626 } 2627 2628 static void hclgevf_flush_link_update(struct hclgevf_dev *hdev) 2629 { 2630 #define HCLGEVF_FLUSH_LINK_TIMEOUT 100000 2631 2632 unsigned long last = hdev->serv_processed_cnt; 2633 int i = 0; 2634 2635 while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) && 2636 i++ < HCLGEVF_FLUSH_LINK_TIMEOUT && 2637 last == hdev->serv_processed_cnt) 2638 usleep_range(1, 1); 2639 } 2640 2641 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 2642 { 2643 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2644 2645 if (enable) { 2646 hclgevf_task_schedule(hdev, 0); 2647 } else { 2648 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2649 2650 /* flush memory to make sure DOWN is seen by service task */ 2651 smp_mb__before_atomic(); 2652 hclgevf_flush_link_update(hdev); 2653 } 2654 } 2655 2656 static int hclgevf_ae_start(struct hnae3_handle *handle) 2657 { 2658 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2659 2660 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2661 clear_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state); 2662 2663 hclgevf_reset_tqp_stats(handle); 2664 2665 hclgevf_request_link_info(hdev); 2666 2667 hclgevf_update_link_mode(hdev); 2668 2669 return 0; 2670 } 2671 2672 static void hclgevf_ae_stop(struct hnae3_handle *handle) 2673 { 2674 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2675 2676 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2677 2678 if (hdev->reset_type != HNAE3_VF_RESET) 2679 hclgevf_reset_tqp(handle); 2680 2681 hclgevf_reset_tqp_stats(handle); 2682 hclgevf_update_link_status(hdev, 0); 2683 } 2684 2685 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2686 { 2687 #define HCLGEVF_STATE_ALIVE 1 2688 #define HCLGEVF_STATE_NOT_ALIVE 0 2689 2690 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2691 struct hclge_vf_to_pf_msg send_msg; 2692 2693 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_ALIVE, 0); 2694 send_msg.data[0] = alive ? HCLGEVF_STATE_ALIVE : 2695 HCLGEVF_STATE_NOT_ALIVE; 2696 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2697 } 2698 2699 static int hclgevf_client_start(struct hnae3_handle *handle) 2700 { 2701 return hclgevf_set_alive(handle, true); 2702 } 2703 2704 static void hclgevf_client_stop(struct hnae3_handle *handle) 2705 { 2706 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2707 int ret; 2708 2709 ret = hclgevf_set_alive(handle, false); 2710 if (ret) 2711 dev_warn(&hdev->pdev->dev, 2712 "%s failed %d\n", __func__, ret); 2713 } 2714 2715 static void hclgevf_state_init(struct hclgevf_dev *hdev) 2716 { 2717 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2718 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2719 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 2720 2721 INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task); 2722 2723 mutex_init(&hdev->mbx_resp.mbx_mutex); 2724 sema_init(&hdev->reset_sem, 1); 2725 2726 spin_lock_init(&hdev->mac_table.mac_list_lock); 2727 INIT_LIST_HEAD(&hdev->mac_table.uc_mac_list); 2728 INIT_LIST_HEAD(&hdev->mac_table.mc_mac_list); 2729 2730 /* bring the device down */ 2731 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2732 } 2733 2734 static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2735 { 2736 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2737 set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2738 2739 if (hdev->service_task.work.func) 2740 cancel_delayed_work_sync(&hdev->service_task); 2741 2742 mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2743 } 2744 2745 static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2746 { 2747 struct pci_dev *pdev = hdev->pdev; 2748 int vectors; 2749 int i; 2750 2751 if (hnae3_dev_roce_supported(hdev)) 2752 vectors = pci_alloc_irq_vectors(pdev, 2753 hdev->roce_base_msix_offset + 1, 2754 hdev->num_msi, 2755 PCI_IRQ_MSIX); 2756 else 2757 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2758 hdev->num_msi, 2759 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2760 2761 if (vectors < 0) { 2762 dev_err(&pdev->dev, 2763 "failed(%d) to allocate MSI/MSI-X vectors\n", 2764 vectors); 2765 return vectors; 2766 } 2767 if (vectors < hdev->num_msi) 2768 dev_warn(&hdev->pdev->dev, 2769 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2770 hdev->num_msi, vectors); 2771 2772 hdev->num_msi = vectors; 2773 hdev->num_msi_left = vectors; 2774 2775 hdev->base_msi_vector = pdev->irq; 2776 hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2777 2778 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2779 sizeof(u16), GFP_KERNEL); 2780 if (!hdev->vector_status) { 2781 pci_free_irq_vectors(pdev); 2782 return -ENOMEM; 2783 } 2784 2785 for (i = 0; i < hdev->num_msi; i++) 2786 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2787 2788 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2789 sizeof(int), GFP_KERNEL); 2790 if (!hdev->vector_irq) { 2791 devm_kfree(&pdev->dev, hdev->vector_status); 2792 pci_free_irq_vectors(pdev); 2793 return -ENOMEM; 2794 } 2795 2796 return 0; 2797 } 2798 2799 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2800 { 2801 struct pci_dev *pdev = hdev->pdev; 2802 2803 devm_kfree(&pdev->dev, hdev->vector_status); 2804 devm_kfree(&pdev->dev, hdev->vector_irq); 2805 pci_free_irq_vectors(pdev); 2806 } 2807 2808 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2809 { 2810 int ret; 2811 2812 hclgevf_get_misc_vector(hdev); 2813 2814 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 2815 HCLGEVF_NAME, pci_name(hdev->pdev)); 2816 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2817 0, hdev->misc_vector.name, hdev); 2818 if (ret) { 2819 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2820 hdev->misc_vector.vector_irq); 2821 return ret; 2822 } 2823 2824 hclgevf_clear_event_cause(hdev, 0); 2825 2826 /* enable misc. vector(vector 0) */ 2827 hclgevf_enable_vector(&hdev->misc_vector, true); 2828 2829 return ret; 2830 } 2831 2832 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2833 { 2834 /* disable misc vector(vector 0) */ 2835 hclgevf_enable_vector(&hdev->misc_vector, false); 2836 synchronize_irq(hdev->misc_vector.vector_irq); 2837 free_irq(hdev->misc_vector.vector_irq, hdev); 2838 hclgevf_free_vector(hdev, 0); 2839 } 2840 2841 static void hclgevf_info_show(struct hclgevf_dev *hdev) 2842 { 2843 struct device *dev = &hdev->pdev->dev; 2844 2845 dev_info(dev, "VF info begin:\n"); 2846 2847 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 2848 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 2849 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 2850 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 2851 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 2852 dev_info(dev, "PF media type of this VF: %u\n", 2853 hdev->hw.mac.media_type); 2854 2855 dev_info(dev, "VF info end.\n"); 2856 } 2857 2858 static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 2859 struct hnae3_client *client) 2860 { 2861 struct hclgevf_dev *hdev = ae_dev->priv; 2862 int rst_cnt = hdev->rst_stats.rst_cnt; 2863 int ret; 2864 2865 ret = client->ops->init_instance(&hdev->nic); 2866 if (ret) 2867 return ret; 2868 2869 set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2870 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 2871 rst_cnt != hdev->rst_stats.rst_cnt) { 2872 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2873 2874 client->ops->uninit_instance(&hdev->nic, 0); 2875 return -EBUSY; 2876 } 2877 2878 hnae3_set_client_init_flag(client, ae_dev, 1); 2879 2880 if (netif_msg_drv(&hdev->nic)) 2881 hclgevf_info_show(hdev); 2882 2883 return 0; 2884 } 2885 2886 static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 2887 struct hnae3_client *client) 2888 { 2889 struct hclgevf_dev *hdev = ae_dev->priv; 2890 int ret; 2891 2892 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 2893 !hdev->nic_client) 2894 return 0; 2895 2896 ret = hclgevf_init_roce_base_info(hdev); 2897 if (ret) 2898 return ret; 2899 2900 ret = client->ops->init_instance(&hdev->roce); 2901 if (ret) 2902 return ret; 2903 2904 set_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 2905 hnae3_set_client_init_flag(client, ae_dev, 1); 2906 2907 return 0; 2908 } 2909 2910 static int hclgevf_init_client_instance(struct hnae3_client *client, 2911 struct hnae3_ae_dev *ae_dev) 2912 { 2913 struct hclgevf_dev *hdev = ae_dev->priv; 2914 int ret; 2915 2916 switch (client->type) { 2917 case HNAE3_CLIENT_KNIC: 2918 hdev->nic_client = client; 2919 hdev->nic.client = client; 2920 2921 ret = hclgevf_init_nic_client_instance(ae_dev, client); 2922 if (ret) 2923 goto clear_nic; 2924 2925 ret = hclgevf_init_roce_client_instance(ae_dev, 2926 hdev->roce_client); 2927 if (ret) 2928 goto clear_roce; 2929 2930 break; 2931 case HNAE3_CLIENT_ROCE: 2932 if (hnae3_dev_roce_supported(hdev)) { 2933 hdev->roce_client = client; 2934 hdev->roce.client = client; 2935 } 2936 2937 ret = hclgevf_init_roce_client_instance(ae_dev, client); 2938 if (ret) 2939 goto clear_roce; 2940 2941 break; 2942 default: 2943 return -EINVAL; 2944 } 2945 2946 return 0; 2947 2948 clear_nic: 2949 hdev->nic_client = NULL; 2950 hdev->nic.client = NULL; 2951 return ret; 2952 clear_roce: 2953 hdev->roce_client = NULL; 2954 hdev->roce.client = NULL; 2955 return ret; 2956 } 2957 2958 static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2959 struct hnae3_ae_dev *ae_dev) 2960 { 2961 struct hclgevf_dev *hdev = ae_dev->priv; 2962 2963 /* un-init roce, if it exists */ 2964 if (hdev->roce_client) { 2965 clear_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 2966 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 2967 hdev->roce_client = NULL; 2968 hdev->roce.client = NULL; 2969 } 2970 2971 /* un-init nic/unic, if this was not called by roce client */ 2972 if (client->ops->uninit_instance && hdev->nic_client && 2973 client->type != HNAE3_CLIENT_ROCE) { 2974 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2975 2976 client->ops->uninit_instance(&hdev->nic, 0); 2977 hdev->nic_client = NULL; 2978 hdev->nic.client = NULL; 2979 } 2980 } 2981 2982 static int hclgevf_dev_mem_map(struct hclgevf_dev *hdev) 2983 { 2984 #define HCLGEVF_MEM_BAR 4 2985 2986 struct pci_dev *pdev = hdev->pdev; 2987 struct hclgevf_hw *hw = &hdev->hw; 2988 2989 /* for device does not have device memory, return directly */ 2990 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGEVF_MEM_BAR))) 2991 return 0; 2992 2993 hw->mem_base = devm_ioremap_wc(&pdev->dev, 2994 pci_resource_start(pdev, 2995 HCLGEVF_MEM_BAR), 2996 pci_resource_len(pdev, HCLGEVF_MEM_BAR)); 2997 if (!hw->mem_base) { 2998 dev_err(&pdev->dev, "failed to map device memory\n"); 2999 return -EFAULT; 3000 } 3001 3002 return 0; 3003 } 3004 3005 static int hclgevf_pci_init(struct hclgevf_dev *hdev) 3006 { 3007 struct pci_dev *pdev = hdev->pdev; 3008 struct hclgevf_hw *hw; 3009 int ret; 3010 3011 ret = pci_enable_device(pdev); 3012 if (ret) { 3013 dev_err(&pdev->dev, "failed to enable PCI device\n"); 3014 return ret; 3015 } 3016 3017 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3018 if (ret) { 3019 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 3020 goto err_disable_device; 3021 } 3022 3023 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 3024 if (ret) { 3025 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 3026 goto err_disable_device; 3027 } 3028 3029 pci_set_master(pdev); 3030 hw = &hdev->hw; 3031 hw->hdev = hdev; 3032 hw->io_base = pci_iomap(pdev, 2, 0); 3033 if (!hw->io_base) { 3034 dev_err(&pdev->dev, "can't map configuration register space\n"); 3035 ret = -ENOMEM; 3036 goto err_clr_master; 3037 } 3038 3039 ret = hclgevf_dev_mem_map(hdev); 3040 if (ret) 3041 goto err_unmap_io_base; 3042 3043 return 0; 3044 3045 err_unmap_io_base: 3046 pci_iounmap(pdev, hdev->hw.io_base); 3047 err_clr_master: 3048 pci_clear_master(pdev); 3049 pci_release_regions(pdev); 3050 err_disable_device: 3051 pci_disable_device(pdev); 3052 3053 return ret; 3054 } 3055 3056 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 3057 { 3058 struct pci_dev *pdev = hdev->pdev; 3059 3060 if (hdev->hw.mem_base) 3061 devm_iounmap(&pdev->dev, hdev->hw.mem_base); 3062 3063 pci_iounmap(pdev, hdev->hw.io_base); 3064 pci_clear_master(pdev); 3065 pci_release_regions(pdev); 3066 pci_disable_device(pdev); 3067 } 3068 3069 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 3070 { 3071 struct hclgevf_query_res_cmd *req; 3072 struct hclgevf_desc desc; 3073 int ret; 3074 3075 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 3076 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 3077 if (ret) { 3078 dev_err(&hdev->pdev->dev, 3079 "query vf resource failed, ret = %d.\n", ret); 3080 return ret; 3081 } 3082 3083 req = (struct hclgevf_query_res_cmd *)desc.data; 3084 3085 if (hnae3_dev_roce_supported(hdev)) { 3086 hdev->roce_base_msix_offset = 3087 hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee), 3088 HCLGEVF_MSIX_OFT_ROCEE_M, 3089 HCLGEVF_MSIX_OFT_ROCEE_S); 3090 hdev->num_roce_msix = 3091 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 3092 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 3093 3094 /* nic's msix numbers is always equals to the roce's. */ 3095 hdev->num_nic_msix = hdev->num_roce_msix; 3096 3097 /* VF should have NIC vectors and Roce vectors, NIC vectors 3098 * are queued before Roce vectors. The offset is fixed to 64. 3099 */ 3100 hdev->num_msi = hdev->num_roce_msix + 3101 hdev->roce_base_msix_offset; 3102 } else { 3103 hdev->num_msi = 3104 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 3105 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 3106 3107 hdev->num_nic_msix = hdev->num_msi; 3108 } 3109 3110 if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) { 3111 dev_err(&hdev->pdev->dev, 3112 "Just %u msi resources, not enough for vf(min:2).\n", 3113 hdev->num_nic_msix); 3114 return -EINVAL; 3115 } 3116 3117 return 0; 3118 } 3119 3120 static void hclgevf_set_default_dev_specs(struct hclgevf_dev *hdev) 3121 { 3122 #define HCLGEVF_MAX_NON_TSO_BD_NUM 8U 3123 3124 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 3125 3126 ae_dev->dev_specs.max_non_tso_bd_num = 3127 HCLGEVF_MAX_NON_TSO_BD_NUM; 3128 ae_dev->dev_specs.rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 3129 ae_dev->dev_specs.rss_key_size = HCLGEVF_RSS_KEY_SIZE; 3130 ae_dev->dev_specs.max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 3131 ae_dev->dev_specs.max_frm_size = HCLGEVF_MAC_MAX_FRAME; 3132 } 3133 3134 static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev, 3135 struct hclgevf_desc *desc) 3136 { 3137 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 3138 struct hclgevf_dev_specs_0_cmd *req0; 3139 struct hclgevf_dev_specs_1_cmd *req1; 3140 3141 req0 = (struct hclgevf_dev_specs_0_cmd *)desc[0].data; 3142 req1 = (struct hclgevf_dev_specs_1_cmd *)desc[1].data; 3143 3144 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 3145 ae_dev->dev_specs.rss_ind_tbl_size = 3146 le16_to_cpu(req0->rss_ind_tbl_size); 3147 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 3148 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 3149 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 3150 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 3151 } 3152 3153 static void hclgevf_check_dev_specs(struct hclgevf_dev *hdev) 3154 { 3155 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 3156 3157 if (!dev_specs->max_non_tso_bd_num) 3158 dev_specs->max_non_tso_bd_num = HCLGEVF_MAX_NON_TSO_BD_NUM; 3159 if (!dev_specs->rss_ind_tbl_size) 3160 dev_specs->rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 3161 if (!dev_specs->rss_key_size) 3162 dev_specs->rss_key_size = HCLGEVF_RSS_KEY_SIZE; 3163 if (!dev_specs->max_int_gl) 3164 dev_specs->max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 3165 if (!dev_specs->max_frm_size) 3166 dev_specs->max_frm_size = HCLGEVF_MAC_MAX_FRAME; 3167 } 3168 3169 static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev) 3170 { 3171 struct hclgevf_desc desc[HCLGEVF_QUERY_DEV_SPECS_BD_NUM]; 3172 int ret; 3173 int i; 3174 3175 /* set default specifications as devices lower than version V3 do not 3176 * support querying specifications from firmware. 3177 */ 3178 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 3179 hclgevf_set_default_dev_specs(hdev); 3180 return 0; 3181 } 3182 3183 for (i = 0; i < HCLGEVF_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 3184 hclgevf_cmd_setup_basic_desc(&desc[i], 3185 HCLGEVF_OPC_QUERY_DEV_SPECS, true); 3186 desc[i].flag |= cpu_to_le16(HCLGEVF_CMD_FLAG_NEXT); 3187 } 3188 hclgevf_cmd_setup_basic_desc(&desc[i], HCLGEVF_OPC_QUERY_DEV_SPECS, 3189 true); 3190 3191 ret = hclgevf_cmd_send(&hdev->hw, desc, HCLGEVF_QUERY_DEV_SPECS_BD_NUM); 3192 if (ret) 3193 return ret; 3194 3195 hclgevf_parse_dev_specs(hdev, desc); 3196 hclgevf_check_dev_specs(hdev); 3197 3198 return 0; 3199 } 3200 3201 static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 3202 { 3203 struct pci_dev *pdev = hdev->pdev; 3204 int ret = 0; 3205 3206 if (hdev->reset_type == HNAE3_VF_FULL_RESET && 3207 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3208 hclgevf_misc_irq_uninit(hdev); 3209 hclgevf_uninit_msi(hdev); 3210 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3211 } 3212 3213 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3214 pci_set_master(pdev); 3215 ret = hclgevf_init_msi(hdev); 3216 if (ret) { 3217 dev_err(&pdev->dev, 3218 "failed(%d) to init MSI/MSI-X\n", ret); 3219 return ret; 3220 } 3221 3222 ret = hclgevf_misc_irq_init(hdev); 3223 if (ret) { 3224 hclgevf_uninit_msi(hdev); 3225 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 3226 ret); 3227 return ret; 3228 } 3229 3230 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3231 } 3232 3233 return ret; 3234 } 3235 3236 static int hclgevf_clear_vport_list(struct hclgevf_dev *hdev) 3237 { 3238 struct hclge_vf_to_pf_msg send_msg; 3239 3240 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_HANDLE_VF_TBL, 3241 HCLGE_MBX_VPORT_LIST_CLEAR); 3242 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3243 } 3244 3245 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 3246 { 3247 struct pci_dev *pdev = hdev->pdev; 3248 int ret; 3249 3250 ret = hclgevf_pci_reset(hdev); 3251 if (ret) { 3252 dev_err(&pdev->dev, "pci reset failed %d\n", ret); 3253 return ret; 3254 } 3255 3256 ret = hclgevf_cmd_init(hdev); 3257 if (ret) { 3258 dev_err(&pdev->dev, "cmd failed %d\n", ret); 3259 return ret; 3260 } 3261 3262 ret = hclgevf_rss_init_hw(hdev); 3263 if (ret) { 3264 dev_err(&hdev->pdev->dev, 3265 "failed(%d) to initialize RSS\n", ret); 3266 return ret; 3267 } 3268 3269 ret = hclgevf_config_gro(hdev, true); 3270 if (ret) 3271 return ret; 3272 3273 ret = hclgevf_init_vlan_config(hdev); 3274 if (ret) { 3275 dev_err(&hdev->pdev->dev, 3276 "failed(%d) to initialize VLAN config\n", ret); 3277 return ret; 3278 } 3279 3280 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 3281 3282 dev_info(&hdev->pdev->dev, "Reset done\n"); 3283 3284 return 0; 3285 } 3286 3287 static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 3288 { 3289 struct pci_dev *pdev = hdev->pdev; 3290 int ret; 3291 3292 ret = hclgevf_pci_init(hdev); 3293 if (ret) 3294 return ret; 3295 3296 ret = hclgevf_cmd_queue_init(hdev); 3297 if (ret) 3298 goto err_cmd_queue_init; 3299 3300 ret = hclgevf_cmd_init(hdev); 3301 if (ret) 3302 goto err_cmd_init; 3303 3304 /* Get vf resource */ 3305 ret = hclgevf_query_vf_resource(hdev); 3306 if (ret) 3307 goto err_cmd_init; 3308 3309 ret = hclgevf_query_dev_specs(hdev); 3310 if (ret) { 3311 dev_err(&pdev->dev, 3312 "failed to query dev specifications, ret = %d\n", ret); 3313 goto err_cmd_init; 3314 } 3315 3316 ret = hclgevf_init_msi(hdev); 3317 if (ret) { 3318 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 3319 goto err_cmd_init; 3320 } 3321 3322 hclgevf_state_init(hdev); 3323 hdev->reset_level = HNAE3_VF_FUNC_RESET; 3324 hdev->reset_type = HNAE3_NONE_RESET; 3325 3326 ret = hclgevf_misc_irq_init(hdev); 3327 if (ret) 3328 goto err_misc_irq_init; 3329 3330 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3331 3332 ret = hclgevf_configure(hdev); 3333 if (ret) { 3334 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 3335 goto err_config; 3336 } 3337 3338 ret = hclgevf_alloc_tqps(hdev); 3339 if (ret) { 3340 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 3341 goto err_config; 3342 } 3343 3344 ret = hclgevf_set_handle_info(hdev); 3345 if (ret) 3346 goto err_config; 3347 3348 ret = hclgevf_config_gro(hdev, true); 3349 if (ret) 3350 goto err_config; 3351 3352 /* Initialize RSS for this VF */ 3353 ret = hclgevf_rss_init_cfg(hdev); 3354 if (ret) { 3355 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 3356 goto err_config; 3357 } 3358 3359 ret = hclgevf_rss_init_hw(hdev); 3360 if (ret) { 3361 dev_err(&hdev->pdev->dev, 3362 "failed(%d) to initialize RSS\n", ret); 3363 goto err_config; 3364 } 3365 3366 /* ensure vf tbl list as empty before init*/ 3367 ret = hclgevf_clear_vport_list(hdev); 3368 if (ret) { 3369 dev_err(&pdev->dev, 3370 "failed to clear tbl list configuration, ret = %d.\n", 3371 ret); 3372 goto err_config; 3373 } 3374 3375 ret = hclgevf_init_vlan_config(hdev); 3376 if (ret) { 3377 dev_err(&hdev->pdev->dev, 3378 "failed(%d) to initialize VLAN config\n", ret); 3379 goto err_config; 3380 } 3381 3382 hdev->last_reset_time = jiffies; 3383 dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 3384 HCLGEVF_DRIVER_NAME); 3385 3386 hclgevf_task_schedule(hdev, round_jiffies_relative(HZ)); 3387 3388 return 0; 3389 3390 err_config: 3391 hclgevf_misc_irq_uninit(hdev); 3392 err_misc_irq_init: 3393 hclgevf_state_uninit(hdev); 3394 hclgevf_uninit_msi(hdev); 3395 err_cmd_init: 3396 hclgevf_cmd_uninit(hdev); 3397 err_cmd_queue_init: 3398 hclgevf_pci_uninit(hdev); 3399 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3400 return ret; 3401 } 3402 3403 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 3404 { 3405 struct hclge_vf_to_pf_msg send_msg; 3406 3407 hclgevf_state_uninit(hdev); 3408 3409 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_VF_UNINIT, 0); 3410 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3411 3412 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3413 hclgevf_misc_irq_uninit(hdev); 3414 hclgevf_uninit_msi(hdev); 3415 } 3416 3417 hclgevf_cmd_uninit(hdev); 3418 hclgevf_pci_uninit(hdev); 3419 hclgevf_uninit_mac_list(hdev); 3420 } 3421 3422 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 3423 { 3424 struct pci_dev *pdev = ae_dev->pdev; 3425 int ret; 3426 3427 ret = hclgevf_alloc_hdev(ae_dev); 3428 if (ret) { 3429 dev_err(&pdev->dev, "hclge device allocation failed\n"); 3430 return ret; 3431 } 3432 3433 ret = hclgevf_init_hdev(ae_dev->priv); 3434 if (ret) { 3435 dev_err(&pdev->dev, "hclge device initialization failed\n"); 3436 return ret; 3437 } 3438 3439 return 0; 3440 } 3441 3442 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 3443 { 3444 struct hclgevf_dev *hdev = ae_dev->priv; 3445 3446 hclgevf_uninit_hdev(hdev); 3447 ae_dev->priv = NULL; 3448 } 3449 3450 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 3451 { 3452 struct hnae3_handle *nic = &hdev->nic; 3453 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 3454 3455 return min_t(u32, hdev->rss_size_max, 3456 hdev->num_tqps / kinfo->tc_info.num_tc); 3457 } 3458 3459 /** 3460 * hclgevf_get_channels - Get the current channels enabled and max supported. 3461 * @handle: hardware information for network interface 3462 * @ch: ethtool channels structure 3463 * 3464 * We don't support separate tx and rx queues as channels. The other count 3465 * represents how many queues are being used for control. max_combined counts 3466 * how many queue pairs we can support. They may not be mapped 1 to 1 with 3467 * q_vectors since we support a lot more queue pairs than q_vectors. 3468 **/ 3469 static void hclgevf_get_channels(struct hnae3_handle *handle, 3470 struct ethtool_channels *ch) 3471 { 3472 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3473 3474 ch->max_combined = hclgevf_get_max_channels(hdev); 3475 ch->other_count = 0; 3476 ch->max_other = 0; 3477 ch->combined_count = handle->kinfo.rss_size; 3478 } 3479 3480 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 3481 u16 *alloc_tqps, u16 *max_rss_size) 3482 { 3483 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3484 3485 *alloc_tqps = hdev->num_tqps; 3486 *max_rss_size = hdev->rss_size_max; 3487 } 3488 3489 static void hclgevf_update_rss_size(struct hnae3_handle *handle, 3490 u32 new_tqps_num) 3491 { 3492 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3493 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3494 u16 max_rss_size; 3495 3496 kinfo->req_rss_size = new_tqps_num; 3497 3498 max_rss_size = min_t(u16, hdev->rss_size_max, 3499 hdev->num_tqps / kinfo->tc_info.num_tc); 3500 3501 /* Use the user's configuration when it is not larger than 3502 * max_rss_size, otherwise, use the maximum specification value. 3503 */ 3504 if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 3505 kinfo->req_rss_size <= max_rss_size) 3506 kinfo->rss_size = kinfo->req_rss_size; 3507 else if (kinfo->rss_size > max_rss_size || 3508 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) 3509 kinfo->rss_size = max_rss_size; 3510 3511 kinfo->num_tqps = kinfo->tc_info.num_tc * kinfo->rss_size; 3512 } 3513 3514 static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 3515 bool rxfh_configured) 3516 { 3517 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3518 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3519 u16 cur_rss_size = kinfo->rss_size; 3520 u16 cur_tqps = kinfo->num_tqps; 3521 u32 *rss_indir; 3522 unsigned int i; 3523 int ret; 3524 3525 hclgevf_update_rss_size(handle, new_tqps_num); 3526 3527 ret = hclgevf_set_rss_tc_mode(hdev, kinfo->rss_size); 3528 if (ret) 3529 return ret; 3530 3531 /* RSS indirection table has been configured by user */ 3532 if (rxfh_configured) 3533 goto out; 3534 3535 /* Reinitializes the rss indirect table according to the new RSS size */ 3536 rss_indir = kcalloc(hdev->ae_dev->dev_specs.rss_ind_tbl_size, 3537 sizeof(u32), GFP_KERNEL); 3538 if (!rss_indir) 3539 return -ENOMEM; 3540 3541 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 3542 rss_indir[i] = i % kinfo->rss_size; 3543 3544 hdev->rss_cfg.rss_size = kinfo->rss_size; 3545 3546 ret = hclgevf_set_rss(handle, rss_indir, NULL, 0); 3547 if (ret) 3548 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 3549 ret); 3550 3551 kfree(rss_indir); 3552 3553 out: 3554 if (!ret) 3555 dev_info(&hdev->pdev->dev, 3556 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 3557 cur_rss_size, kinfo->rss_size, 3558 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 3559 3560 return ret; 3561 } 3562 3563 static int hclgevf_get_status(struct hnae3_handle *handle) 3564 { 3565 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3566 3567 return hdev->hw.mac.link; 3568 } 3569 3570 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 3571 u8 *auto_neg, u32 *speed, 3572 u8 *duplex) 3573 { 3574 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3575 3576 if (speed) 3577 *speed = hdev->hw.mac.speed; 3578 if (duplex) 3579 *duplex = hdev->hw.mac.duplex; 3580 if (auto_neg) 3581 *auto_neg = AUTONEG_DISABLE; 3582 } 3583 3584 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 3585 u8 duplex) 3586 { 3587 hdev->hw.mac.speed = speed; 3588 hdev->hw.mac.duplex = duplex; 3589 } 3590 3591 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 3592 { 3593 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3594 3595 return hclgevf_config_gro(hdev, enable); 3596 } 3597 3598 static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 3599 u8 *module_type) 3600 { 3601 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3602 3603 if (media_type) 3604 *media_type = hdev->hw.mac.media_type; 3605 3606 if (module_type) 3607 *module_type = hdev->hw.mac.module_type; 3608 } 3609 3610 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 3611 { 3612 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3613 3614 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 3615 } 3616 3617 static bool hclgevf_get_cmdq_stat(struct hnae3_handle *handle) 3618 { 3619 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3620 3621 return test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 3622 } 3623 3624 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 3625 { 3626 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3627 3628 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 3629 } 3630 3631 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 3632 { 3633 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3634 3635 return hdev->rst_stats.hw_rst_done_cnt; 3636 } 3637 3638 static void hclgevf_get_link_mode(struct hnae3_handle *handle, 3639 unsigned long *supported, 3640 unsigned long *advertising) 3641 { 3642 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3643 3644 *supported = hdev->hw.mac.supported; 3645 *advertising = hdev->hw.mac.advertising; 3646 } 3647 3648 #define MAX_SEPARATE_NUM 4 3649 #define SEPARATOR_VALUE 0xFDFCFBFA 3650 #define REG_NUM_PER_LINE 4 3651 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 3652 3653 static int hclgevf_get_regs_len(struct hnae3_handle *handle) 3654 { 3655 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 3656 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3657 3658 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 3659 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 3660 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 3661 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 3662 3663 return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 3664 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 3665 } 3666 3667 static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 3668 void *data) 3669 { 3670 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3671 int i, j, reg_um, separator_num; 3672 u32 *reg = data; 3673 3674 *version = hdev->fw_version; 3675 3676 /* fetching per-VF registers values from VF PCIe register space */ 3677 reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 3678 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3679 for (i = 0; i < reg_um; i++) 3680 *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 3681 for (i = 0; i < separator_num; i++) 3682 *reg++ = SEPARATOR_VALUE; 3683 3684 reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 3685 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3686 for (i = 0; i < reg_um; i++) 3687 *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 3688 for (i = 0; i < separator_num; i++) 3689 *reg++ = SEPARATOR_VALUE; 3690 3691 reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 3692 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3693 for (j = 0; j < hdev->num_tqps; j++) { 3694 for (i = 0; i < reg_um; i++) 3695 *reg++ = hclgevf_read_dev(&hdev->hw, 3696 ring_reg_addr_list[i] + 3697 0x200 * j); 3698 for (i = 0; i < separator_num; i++) 3699 *reg++ = SEPARATOR_VALUE; 3700 } 3701 3702 reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 3703 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3704 for (j = 0; j < hdev->num_msi_used - 1; j++) { 3705 for (i = 0; i < reg_um; i++) 3706 *reg++ = hclgevf_read_dev(&hdev->hw, 3707 tqp_intr_reg_addr_list[i] + 3708 4 * j); 3709 for (i = 0; i < separator_num; i++) 3710 *reg++ = SEPARATOR_VALUE; 3711 } 3712 } 3713 3714 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 3715 u8 *port_base_vlan_info, u8 data_size) 3716 { 3717 struct hnae3_handle *nic = &hdev->nic; 3718 struct hclge_vf_to_pf_msg send_msg; 3719 int ret; 3720 3721 rtnl_lock(); 3722 3723 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 3724 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) { 3725 dev_warn(&hdev->pdev->dev, 3726 "is resetting when updating port based vlan info\n"); 3727 rtnl_unlock(); 3728 return; 3729 } 3730 3731 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 3732 if (ret) { 3733 rtnl_unlock(); 3734 return; 3735 } 3736 3737 /* send msg to PF and wait update port based vlan info */ 3738 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 3739 HCLGE_MBX_PORT_BASE_VLAN_CFG); 3740 memcpy(send_msg.data, port_base_vlan_info, data_size); 3741 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3742 if (!ret) { 3743 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 3744 nic->port_base_vlan_state = state; 3745 else 3746 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 3747 } 3748 3749 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 3750 rtnl_unlock(); 3751 } 3752 3753 static const struct hnae3_ae_ops hclgevf_ops = { 3754 .init_ae_dev = hclgevf_init_ae_dev, 3755 .uninit_ae_dev = hclgevf_uninit_ae_dev, 3756 .reset_prepare = hclgevf_reset_prepare_general, 3757 .reset_done = hclgevf_reset_done, 3758 .init_client_instance = hclgevf_init_client_instance, 3759 .uninit_client_instance = hclgevf_uninit_client_instance, 3760 .start = hclgevf_ae_start, 3761 .stop = hclgevf_ae_stop, 3762 .client_start = hclgevf_client_start, 3763 .client_stop = hclgevf_client_stop, 3764 .map_ring_to_vector = hclgevf_map_ring_to_vector, 3765 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 3766 .get_vector = hclgevf_get_vector, 3767 .put_vector = hclgevf_put_vector, 3768 .reset_queue = hclgevf_reset_tqp, 3769 .get_mac_addr = hclgevf_get_mac_addr, 3770 .set_mac_addr = hclgevf_set_mac_addr, 3771 .add_uc_addr = hclgevf_add_uc_addr, 3772 .rm_uc_addr = hclgevf_rm_uc_addr, 3773 .add_mc_addr = hclgevf_add_mc_addr, 3774 .rm_mc_addr = hclgevf_rm_mc_addr, 3775 .get_stats = hclgevf_get_stats, 3776 .update_stats = hclgevf_update_stats, 3777 .get_strings = hclgevf_get_strings, 3778 .get_sset_count = hclgevf_get_sset_count, 3779 .get_rss_key_size = hclgevf_get_rss_key_size, 3780 .get_rss = hclgevf_get_rss, 3781 .set_rss = hclgevf_set_rss, 3782 .get_rss_tuple = hclgevf_get_rss_tuple, 3783 .set_rss_tuple = hclgevf_set_rss_tuple, 3784 .get_tc_size = hclgevf_get_tc_size, 3785 .get_fw_version = hclgevf_get_fw_version, 3786 .set_vlan_filter = hclgevf_set_vlan_filter, 3787 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 3788 .reset_event = hclgevf_reset_event, 3789 .set_default_reset_request = hclgevf_set_def_reset_request, 3790 .set_channels = hclgevf_set_channels, 3791 .get_channels = hclgevf_get_channels, 3792 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 3793 .get_regs_len = hclgevf_get_regs_len, 3794 .get_regs = hclgevf_get_regs, 3795 .get_status = hclgevf_get_status, 3796 .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3797 .get_media_type = hclgevf_get_media_type, 3798 .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 3799 .ae_dev_resetting = hclgevf_ae_dev_resetting, 3800 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 3801 .set_gro_en = hclgevf_gro_en, 3802 .set_mtu = hclgevf_set_mtu, 3803 .get_global_queue_id = hclgevf_get_qid_global, 3804 .set_timer_task = hclgevf_set_timer_task, 3805 .get_link_mode = hclgevf_get_link_mode, 3806 .set_promisc_mode = hclgevf_set_promisc_mode, 3807 .request_update_promisc_mode = hclgevf_request_update_promisc_mode, 3808 .get_cmdq_stat = hclgevf_get_cmdq_stat, 3809 }; 3810 3811 static struct hnae3_ae_algo ae_algovf = { 3812 .ops = &hclgevf_ops, 3813 .pdev_id_table = ae_algovf_pci_tbl, 3814 }; 3815 3816 static int hclgevf_init(void) 3817 { 3818 pr_info("%s is initializing\n", HCLGEVF_NAME); 3819 3820 hclgevf_wq = alloc_workqueue("%s", 0, 0, HCLGEVF_NAME); 3821 if (!hclgevf_wq) { 3822 pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME); 3823 return -ENOMEM; 3824 } 3825 3826 hnae3_register_ae_algo(&ae_algovf); 3827 3828 return 0; 3829 } 3830 3831 static void hclgevf_exit(void) 3832 { 3833 hnae3_unregister_ae_algo(&ae_algovf); 3834 destroy_workqueue(hclgevf_wq); 3835 } 3836 module_init(hclgevf_init); 3837 module_exit(hclgevf_exit); 3838 3839 MODULE_LICENSE("GPL"); 3840 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3841 MODULE_DESCRIPTION("HCLGEVF Driver"); 3842 MODULE_VERSION(HCLGEVF_MOD_VERSION); 3843