1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include <linux/iopoll.h> 6 #include <net/rtnetlink.h> 7 #include "hclgevf_cmd.h" 8 #include "hclgevf_main.h" 9 #include "hclge_mbx.h" 10 #include "hnae3.h" 11 #include "hclgevf_devlink.h" 12 #include "hclge_comm_rss.h" 13 14 #define HCLGEVF_NAME "hclgevf" 15 16 #define HCLGEVF_RESET_MAX_FAIL_CNT 5 17 18 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 19 static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 20 unsigned long delay); 21 22 static struct hnae3_ae_algo ae_algovf; 23 24 static struct workqueue_struct *hclgevf_wq; 25 26 static const struct pci_device_id ae_algovf_pci_tbl[] = { 27 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0}, 28 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 29 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 30 /* required last entry */ 31 {0, } 32 }; 33 34 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 35 36 static const u32 cmdq_reg_addr_list[] = {HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG, 37 HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG, 38 HCLGE_COMM_NIC_CSQ_DEPTH_REG, 39 HCLGE_COMM_NIC_CSQ_TAIL_REG, 40 HCLGE_COMM_NIC_CSQ_HEAD_REG, 41 HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG, 42 HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG, 43 HCLGE_COMM_NIC_CRQ_DEPTH_REG, 44 HCLGE_COMM_NIC_CRQ_TAIL_REG, 45 HCLGE_COMM_NIC_CRQ_HEAD_REG, 46 HCLGE_COMM_VECTOR0_CMDQ_SRC_REG, 47 HCLGE_COMM_VECTOR0_CMDQ_STATE_REG, 48 HCLGE_COMM_CMDQ_INTR_EN_REG, 49 HCLGE_COMM_CMDQ_INTR_GEN_REG}; 50 51 static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 52 HCLGEVF_RST_ING, 53 HCLGEVF_GRO_EN_REG}; 54 55 static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 56 HCLGEVF_RING_RX_ADDR_H_REG, 57 HCLGEVF_RING_RX_BD_NUM_REG, 58 HCLGEVF_RING_RX_BD_LENGTH_REG, 59 HCLGEVF_RING_RX_MERGE_EN_REG, 60 HCLGEVF_RING_RX_TAIL_REG, 61 HCLGEVF_RING_RX_HEAD_REG, 62 HCLGEVF_RING_RX_FBD_NUM_REG, 63 HCLGEVF_RING_RX_OFFSET_REG, 64 HCLGEVF_RING_RX_FBD_OFFSET_REG, 65 HCLGEVF_RING_RX_STASH_REG, 66 HCLGEVF_RING_RX_BD_ERR_REG, 67 HCLGEVF_RING_TX_ADDR_L_REG, 68 HCLGEVF_RING_TX_ADDR_H_REG, 69 HCLGEVF_RING_TX_BD_NUM_REG, 70 HCLGEVF_RING_TX_PRIORITY_REG, 71 HCLGEVF_RING_TX_TC_REG, 72 HCLGEVF_RING_TX_MERGE_EN_REG, 73 HCLGEVF_RING_TX_TAIL_REG, 74 HCLGEVF_RING_TX_HEAD_REG, 75 HCLGEVF_RING_TX_FBD_NUM_REG, 76 HCLGEVF_RING_TX_OFFSET_REG, 77 HCLGEVF_RING_TX_EBD_NUM_REG, 78 HCLGEVF_RING_TX_EBD_OFFSET_REG, 79 HCLGEVF_RING_TX_BD_ERR_REG, 80 HCLGEVF_RING_EN_REG}; 81 82 static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 83 HCLGEVF_TQP_INTR_GL0_REG, 84 HCLGEVF_TQP_INTR_GL1_REG, 85 HCLGEVF_TQP_INTR_GL2_REG, 86 HCLGEVF_TQP_INTR_RL_REG}; 87 88 /* hclgevf_cmd_send - send command to command queue 89 * @hw: pointer to the hw struct 90 * @desc: prefilled descriptor for describing the command 91 * @num : the number of descriptors to be sent 92 * 93 * This is the main send command for command queue, it 94 * sends the queue, cleans the queue, etc 95 */ 96 int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclge_desc *desc, int num) 97 { 98 return hclge_comm_cmd_send(&hw->hw, desc, num); 99 } 100 101 void hclgevf_arq_init(struct hclgevf_dev *hdev) 102 { 103 struct hclge_comm_cmq *cmdq = &hdev->hw.hw.cmq; 104 105 spin_lock(&cmdq->crq.lock); 106 /* initialize the pointers of async rx queue of mailbox */ 107 hdev->arq.hdev = hdev; 108 hdev->arq.head = 0; 109 hdev->arq.tail = 0; 110 atomic_set(&hdev->arq.count, 0); 111 spin_unlock(&cmdq->crq.lock); 112 } 113 114 static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 115 { 116 if (!handle->client) 117 return container_of(handle, struct hclgevf_dev, nic); 118 else if (handle->client->type == HNAE3_CLIENT_ROCE) 119 return container_of(handle, struct hclgevf_dev, roce); 120 else 121 return container_of(handle, struct hclgevf_dev, nic); 122 } 123 124 static void hclgevf_update_stats(struct hnae3_handle *handle, 125 struct net_device_stats *net_stats) 126 { 127 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 128 int status; 129 130 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 131 if (status) 132 dev_err(&hdev->pdev->dev, 133 "VF update of TQPS stats fail, status = %d.\n", 134 status); 135 } 136 137 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 138 { 139 if (strset == ETH_SS_TEST) 140 return -EOPNOTSUPP; 141 else if (strset == ETH_SS_STATS) 142 return hclge_comm_tqps_get_sset_count(handle); 143 144 return 0; 145 } 146 147 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 148 u8 *data) 149 { 150 u8 *p = (char *)data; 151 152 if (strset == ETH_SS_STATS) 153 p = hclge_comm_tqps_get_strings(handle, p); 154 } 155 156 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 157 { 158 hclge_comm_tqps_get_stats(handle, data); 159 } 160 161 static void hclgevf_build_send_msg(struct hclge_vf_to_pf_msg *msg, u8 code, 162 u8 subcode) 163 { 164 if (msg) { 165 memset(msg, 0, sizeof(struct hclge_vf_to_pf_msg)); 166 msg->code = code; 167 msg->subcode = subcode; 168 } 169 } 170 171 static int hclgevf_get_basic_info(struct hclgevf_dev *hdev) 172 { 173 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 174 u8 resp_msg[HCLGE_MBX_MAX_RESP_DATA_SIZE]; 175 struct hclge_basic_info *basic_info; 176 struct hclge_vf_to_pf_msg send_msg; 177 unsigned long caps; 178 int status; 179 180 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_BASIC_INFO, 0); 181 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 182 sizeof(resp_msg)); 183 if (status) { 184 dev_err(&hdev->pdev->dev, 185 "failed to get basic info from pf, ret = %d", status); 186 return status; 187 } 188 189 basic_info = (struct hclge_basic_info *)resp_msg; 190 191 hdev->hw_tc_map = basic_info->hw_tc_map; 192 hdev->mbx_api_version = basic_info->mbx_api_version; 193 caps = basic_info->pf_caps; 194 if (test_bit(HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B, &caps)) 195 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps); 196 197 return 0; 198 } 199 200 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 201 { 202 struct hnae3_handle *nic = &hdev->nic; 203 struct hclge_vf_to_pf_msg send_msg; 204 u8 resp_msg; 205 int ret; 206 207 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 208 HCLGE_MBX_GET_PORT_BASE_VLAN_STATE); 209 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg, 210 sizeof(u8)); 211 if (ret) { 212 dev_err(&hdev->pdev->dev, 213 "VF request to get port based vlan state failed %d", 214 ret); 215 return ret; 216 } 217 218 nic->port_base_vlan_state = resp_msg; 219 220 return 0; 221 } 222 223 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 224 { 225 #define HCLGEVF_TQPS_RSS_INFO_LEN 6 226 #define HCLGEVF_TQPS_ALLOC_OFFSET 0 227 #define HCLGEVF_TQPS_RSS_SIZE_OFFSET 2 228 #define HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET 4 229 230 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 231 struct hclge_vf_to_pf_msg send_msg; 232 int status; 233 234 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QINFO, 0); 235 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 236 HCLGEVF_TQPS_RSS_INFO_LEN); 237 if (status) { 238 dev_err(&hdev->pdev->dev, 239 "VF request to get tqp info from PF failed %d", 240 status); 241 return status; 242 } 243 244 memcpy(&hdev->num_tqps, &resp_msg[HCLGEVF_TQPS_ALLOC_OFFSET], 245 sizeof(u16)); 246 memcpy(&hdev->rss_size_max, &resp_msg[HCLGEVF_TQPS_RSS_SIZE_OFFSET], 247 sizeof(u16)); 248 memcpy(&hdev->rx_buf_len, &resp_msg[HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET], 249 sizeof(u16)); 250 251 return 0; 252 } 253 254 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 255 { 256 #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 257 #define HCLGEVF_TQPS_NUM_TX_DESC_OFFSET 0 258 #define HCLGEVF_TQPS_NUM_RX_DESC_OFFSET 2 259 260 u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 261 struct hclge_vf_to_pf_msg send_msg; 262 int ret; 263 264 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QDEPTH, 0); 265 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 266 HCLGEVF_TQPS_DEPTH_INFO_LEN); 267 if (ret) { 268 dev_err(&hdev->pdev->dev, 269 "VF request to get tqp depth info from PF failed %d", 270 ret); 271 return ret; 272 } 273 274 memcpy(&hdev->num_tx_desc, &resp_msg[HCLGEVF_TQPS_NUM_TX_DESC_OFFSET], 275 sizeof(u16)); 276 memcpy(&hdev->num_rx_desc, &resp_msg[HCLGEVF_TQPS_NUM_RX_DESC_OFFSET], 277 sizeof(u16)); 278 279 return 0; 280 } 281 282 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 283 { 284 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 285 struct hclge_vf_to_pf_msg send_msg; 286 u16 qid_in_pf = 0; 287 u8 resp_data[2]; 288 int ret; 289 290 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QID_IN_PF, 0); 291 memcpy(send_msg.data, &queue_id, sizeof(queue_id)); 292 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_data, 293 sizeof(resp_data)); 294 if (!ret) 295 qid_in_pf = *(u16 *)resp_data; 296 297 return qid_in_pf; 298 } 299 300 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 301 { 302 struct hclge_vf_to_pf_msg send_msg; 303 u8 resp_msg[2]; 304 int ret; 305 306 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MEDIA_TYPE, 0); 307 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 308 sizeof(resp_msg)); 309 if (ret) { 310 dev_err(&hdev->pdev->dev, 311 "VF request to get the pf port media type failed %d", 312 ret); 313 return ret; 314 } 315 316 hdev->hw.mac.media_type = resp_msg[0]; 317 hdev->hw.mac.module_type = resp_msg[1]; 318 319 return 0; 320 } 321 322 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 323 { 324 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 325 struct hclge_comm_tqp *tqp; 326 int i; 327 328 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 329 sizeof(struct hclge_comm_tqp), GFP_KERNEL); 330 if (!hdev->htqp) 331 return -ENOMEM; 332 333 tqp = hdev->htqp; 334 335 for (i = 0; i < hdev->num_tqps; i++) { 336 tqp->dev = &hdev->pdev->dev; 337 tqp->index = i; 338 339 tqp->q.ae_algo = &ae_algovf; 340 tqp->q.buf_size = hdev->rx_buf_len; 341 tqp->q.tx_desc_num = hdev->num_tx_desc; 342 tqp->q.rx_desc_num = hdev->num_rx_desc; 343 344 /* need an extended offset to configure queues >= 345 * HCLGEVF_TQP_MAX_SIZE_DEV_V2. 346 */ 347 if (i < HCLGEVF_TQP_MAX_SIZE_DEV_V2) 348 tqp->q.io_base = hdev->hw.hw.io_base + 349 HCLGEVF_TQP_REG_OFFSET + 350 i * HCLGEVF_TQP_REG_SIZE; 351 else 352 tqp->q.io_base = hdev->hw.hw.io_base + 353 HCLGEVF_TQP_REG_OFFSET + 354 HCLGEVF_TQP_EXT_REG_OFFSET + 355 (i - HCLGEVF_TQP_MAX_SIZE_DEV_V2) * 356 HCLGEVF_TQP_REG_SIZE; 357 358 /* when device supports tx push and has device memory, 359 * the queue can execute push mode or doorbell mode on 360 * device memory. 361 */ 362 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps)) 363 tqp->q.mem_base = hdev->hw.hw.mem_base + 364 HCLGEVF_TQP_MEM_OFFSET(hdev, i); 365 366 tqp++; 367 } 368 369 return 0; 370 } 371 372 static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 373 { 374 struct hnae3_handle *nic = &hdev->nic; 375 struct hnae3_knic_private_info *kinfo; 376 u16 new_tqps = hdev->num_tqps; 377 unsigned int i; 378 u8 num_tc = 0; 379 380 kinfo = &nic->kinfo; 381 kinfo->num_tx_desc = hdev->num_tx_desc; 382 kinfo->num_rx_desc = hdev->num_rx_desc; 383 kinfo->rx_buf_len = hdev->rx_buf_len; 384 for (i = 0; i < HCLGE_COMM_MAX_TC_NUM; i++) 385 if (hdev->hw_tc_map & BIT(i)) 386 num_tc++; 387 388 num_tc = num_tc ? num_tc : 1; 389 kinfo->tc_info.num_tc = num_tc; 390 kinfo->rss_size = min_t(u16, hdev->rss_size_max, new_tqps / num_tc); 391 new_tqps = kinfo->rss_size * num_tc; 392 kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 393 394 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 395 sizeof(struct hnae3_queue *), GFP_KERNEL); 396 if (!kinfo->tqp) 397 return -ENOMEM; 398 399 for (i = 0; i < kinfo->num_tqps; i++) { 400 hdev->htqp[i].q.handle = &hdev->nic; 401 hdev->htqp[i].q.tqp_index = i; 402 kinfo->tqp[i] = &hdev->htqp[i].q; 403 } 404 405 /* after init the max rss_size and tqps, adjust the default tqp numbers 406 * and rss size with the actual vector numbers 407 */ 408 kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps); 409 kinfo->rss_size = min_t(u16, kinfo->num_tqps / num_tc, 410 kinfo->rss_size); 411 412 return 0; 413 } 414 415 static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 416 { 417 struct hclge_vf_to_pf_msg send_msg; 418 int status; 419 420 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_STATUS, 0); 421 status = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 422 if (status) 423 dev_err(&hdev->pdev->dev, 424 "VF failed to fetch link status(%d) from PF", status); 425 } 426 427 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 428 { 429 struct hnae3_handle *rhandle = &hdev->roce; 430 struct hnae3_handle *handle = &hdev->nic; 431 struct hnae3_client *rclient; 432 struct hnae3_client *client; 433 434 if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state)) 435 return; 436 437 client = handle->client; 438 rclient = hdev->roce_client; 439 440 link_state = 441 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 442 if (link_state != hdev->hw.mac.link) { 443 hdev->hw.mac.link = link_state; 444 client->ops->link_status_change(handle, !!link_state); 445 if (rclient && rclient->ops->link_status_change) 446 rclient->ops->link_status_change(rhandle, !!link_state); 447 } 448 449 clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state); 450 } 451 452 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 453 { 454 #define HCLGEVF_ADVERTISING 0 455 #define HCLGEVF_SUPPORTED 1 456 457 struct hclge_vf_to_pf_msg send_msg; 458 459 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_MODE, 0); 460 send_msg.data[0] = HCLGEVF_ADVERTISING; 461 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 462 send_msg.data[0] = HCLGEVF_SUPPORTED; 463 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 464 } 465 466 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 467 { 468 struct hnae3_handle *nic = &hdev->nic; 469 int ret; 470 471 nic->ae_algo = &ae_algovf; 472 nic->pdev = hdev->pdev; 473 nic->numa_node_mask = hdev->numa_node_mask; 474 nic->flags |= HNAE3_SUPPORT_VF; 475 nic->kinfo.io_base = hdev->hw.hw.io_base; 476 477 ret = hclgevf_knic_setup(hdev); 478 if (ret) 479 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 480 ret); 481 return ret; 482 } 483 484 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 485 { 486 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 487 dev_warn(&hdev->pdev->dev, 488 "vector(vector_id %d) has been freed.\n", vector_id); 489 return; 490 } 491 492 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 493 hdev->num_msi_left += 1; 494 hdev->num_msi_used -= 1; 495 } 496 497 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 498 struct hnae3_vector_info *vector_info) 499 { 500 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 501 struct hnae3_vector_info *vector = vector_info; 502 int alloc = 0; 503 int i, j; 504 505 vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num); 506 vector_num = min(hdev->num_msi_left, vector_num); 507 508 for (j = 0; j < vector_num; j++) { 509 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 510 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 511 vector->vector = pci_irq_vector(hdev->pdev, i); 512 vector->io_addr = hdev->hw.hw.io_base + 513 HCLGEVF_VECTOR_REG_BASE + 514 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 515 hdev->vector_status[i] = 0; 516 hdev->vector_irq[i] = vector->vector; 517 518 vector++; 519 alloc++; 520 521 break; 522 } 523 } 524 } 525 hdev->num_msi_left -= alloc; 526 hdev->num_msi_used += alloc; 527 528 return alloc; 529 } 530 531 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 532 { 533 int i; 534 535 for (i = 0; i < hdev->num_msi; i++) 536 if (vector == hdev->vector_irq[i]) 537 return i; 538 539 return -EINVAL; 540 } 541 542 /* for revision 0x20, vf shared the same rss config with pf */ 543 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 544 { 545 #define HCLGEVF_RSS_MBX_RESP_LEN 8 546 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 547 u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 548 struct hclge_vf_to_pf_msg send_msg; 549 u16 msg_num, hash_key_index; 550 u8 index; 551 int ret; 552 553 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_RSS_KEY, 0); 554 msg_num = (HCLGE_COMM_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 555 HCLGEVF_RSS_MBX_RESP_LEN; 556 for (index = 0; index < msg_num; index++) { 557 send_msg.data[0] = index; 558 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 559 HCLGEVF_RSS_MBX_RESP_LEN); 560 if (ret) { 561 dev_err(&hdev->pdev->dev, 562 "VF get rss hash key from PF failed, ret=%d", 563 ret); 564 return ret; 565 } 566 567 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 568 if (index == msg_num - 1) 569 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 570 &resp_msg[0], 571 HCLGE_COMM_RSS_KEY_SIZE - hash_key_index); 572 else 573 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 574 &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 575 } 576 577 return 0; 578 } 579 580 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 581 u8 *hfunc) 582 { 583 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 584 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 585 int ret; 586 587 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 588 hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc); 589 } else { 590 if (hfunc) 591 *hfunc = ETH_RSS_HASH_TOP; 592 if (key) { 593 ret = hclgevf_get_rss_hash_key(hdev); 594 if (ret) 595 return ret; 596 memcpy(key, rss_cfg->rss_hash_key, 597 HCLGE_COMM_RSS_KEY_SIZE); 598 } 599 } 600 601 hclge_comm_get_rss_indir_tbl(rss_cfg, indir, 602 hdev->ae_dev->dev_specs.rss_ind_tbl_size); 603 604 return 0; 605 } 606 607 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 608 const u8 *key, const u8 hfunc) 609 { 610 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 611 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 612 int ret, i; 613 614 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 615 ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, 616 hfunc); 617 if (ret) 618 return ret; 619 } 620 621 /* update the shadow RSS table with user specified qids */ 622 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 623 rss_cfg->rss_indirection_tbl[i] = indir[i]; 624 625 /* update the hardware */ 626 return hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 627 rss_cfg->rss_indirection_tbl); 628 } 629 630 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 631 struct ethtool_rxnfc *nfc) 632 { 633 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 634 int ret; 635 636 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 637 return -EOPNOTSUPP; 638 639 ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw, 640 &hdev->rss_cfg, nfc); 641 if (ret) 642 dev_err(&hdev->pdev->dev, 643 "failed to set rss tuple, ret = %d.\n", ret); 644 645 return ret; 646 } 647 648 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 649 struct ethtool_rxnfc *nfc) 650 { 651 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 652 u8 tuple_sets; 653 int ret; 654 655 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 656 return -EOPNOTSUPP; 657 658 nfc->data = 0; 659 660 ret = hclge_comm_get_rss_tuple(&hdev->rss_cfg, nfc->flow_type, 661 &tuple_sets); 662 if (ret || !tuple_sets) 663 return ret; 664 665 nfc->data = hclge_comm_convert_rss_tuple(tuple_sets); 666 667 return 0; 668 } 669 670 static int hclgevf_get_tc_size(struct hnae3_handle *handle) 671 { 672 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 673 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 674 675 return rss_cfg->rss_size; 676 } 677 678 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 679 int vector_id, 680 struct hnae3_ring_chain_node *ring_chain) 681 { 682 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 683 struct hclge_vf_to_pf_msg send_msg; 684 struct hnae3_ring_chain_node *node; 685 int status; 686 int i = 0; 687 688 memset(&send_msg, 0, sizeof(send_msg)); 689 send_msg.code = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 690 HCLGE_MBX_UNMAP_RING_TO_VECTOR; 691 send_msg.vector_id = vector_id; 692 693 for (node = ring_chain; node; node = node->next) { 694 send_msg.param[i].ring_type = 695 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 696 697 send_msg.param[i].tqp_index = node->tqp_index; 698 send_msg.param[i].int_gl_index = 699 hnae3_get_field(node->int_gl_idx, 700 HNAE3_RING_GL_IDX_M, 701 HNAE3_RING_GL_IDX_S); 702 703 i++; 704 if (i == HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM || !node->next) { 705 send_msg.ring_num = i; 706 707 status = hclgevf_send_mbx_msg(hdev, &send_msg, false, 708 NULL, 0); 709 if (status) { 710 dev_err(&hdev->pdev->dev, 711 "Map TQP fail, status is %d.\n", 712 status); 713 return status; 714 } 715 i = 0; 716 } 717 } 718 719 return 0; 720 } 721 722 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 723 struct hnae3_ring_chain_node *ring_chain) 724 { 725 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 726 int vector_id; 727 728 vector_id = hclgevf_get_vector_index(hdev, vector); 729 if (vector_id < 0) { 730 dev_err(&handle->pdev->dev, 731 "Get vector index fail. ret =%d\n", vector_id); 732 return vector_id; 733 } 734 735 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 736 } 737 738 static int hclgevf_unmap_ring_from_vector( 739 struct hnae3_handle *handle, 740 int vector, 741 struct hnae3_ring_chain_node *ring_chain) 742 { 743 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 744 int ret, vector_id; 745 746 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 747 return 0; 748 749 vector_id = hclgevf_get_vector_index(hdev, vector); 750 if (vector_id < 0) { 751 dev_err(&handle->pdev->dev, 752 "Get vector index fail. ret =%d\n", vector_id); 753 return vector_id; 754 } 755 756 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 757 if (ret) 758 dev_err(&handle->pdev->dev, 759 "Unmap ring from vector fail. vector=%d, ret =%d\n", 760 vector_id, 761 ret); 762 763 return ret; 764 } 765 766 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 767 { 768 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 769 int vector_id; 770 771 vector_id = hclgevf_get_vector_index(hdev, vector); 772 if (vector_id < 0) { 773 dev_err(&handle->pdev->dev, 774 "hclgevf_put_vector get vector index fail. ret =%d\n", 775 vector_id); 776 return vector_id; 777 } 778 779 hclgevf_free_vector(hdev, vector_id); 780 781 return 0; 782 } 783 784 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 785 bool en_uc_pmc, bool en_mc_pmc, 786 bool en_bc_pmc) 787 { 788 struct hnae3_handle *handle = &hdev->nic; 789 struct hclge_vf_to_pf_msg send_msg; 790 int ret; 791 792 memset(&send_msg, 0, sizeof(send_msg)); 793 send_msg.code = HCLGE_MBX_SET_PROMISC_MODE; 794 send_msg.en_bc = en_bc_pmc ? 1 : 0; 795 send_msg.en_uc = en_uc_pmc ? 1 : 0; 796 send_msg.en_mc = en_mc_pmc ? 1 : 0; 797 send_msg.en_limit_promisc = test_bit(HNAE3_PFLAG_LIMIT_PROMISC, 798 &handle->priv_flags) ? 1 : 0; 799 800 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 801 if (ret) 802 dev_err(&hdev->pdev->dev, 803 "Set promisc mode fail, status is %d.\n", ret); 804 805 return ret; 806 } 807 808 static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 809 bool en_mc_pmc) 810 { 811 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 812 bool en_bc_pmc; 813 814 en_bc_pmc = hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2; 815 816 return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc, 817 en_bc_pmc); 818 } 819 820 static void hclgevf_request_update_promisc_mode(struct hnae3_handle *handle) 821 { 822 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 823 824 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 825 hclgevf_task_schedule(hdev, 0); 826 } 827 828 static void hclgevf_sync_promisc_mode(struct hclgevf_dev *hdev) 829 { 830 struct hnae3_handle *handle = &hdev->nic; 831 bool en_uc_pmc = handle->netdev_flags & HNAE3_UPE; 832 bool en_mc_pmc = handle->netdev_flags & HNAE3_MPE; 833 int ret; 834 835 if (test_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state)) { 836 ret = hclgevf_set_promisc_mode(handle, en_uc_pmc, en_mc_pmc); 837 if (!ret) 838 clear_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 839 } 840 } 841 842 static int hclgevf_tqp_enable_cmd_send(struct hclgevf_dev *hdev, u16 tqp_id, 843 u16 stream_id, bool enable) 844 { 845 struct hclgevf_cfg_com_tqp_queue_cmd *req; 846 struct hclge_desc desc; 847 848 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 849 850 hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); 851 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 852 req->stream_id = cpu_to_le16(stream_id); 853 if (enable) 854 req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 855 856 return hclgevf_cmd_send(&hdev->hw, &desc, 1); 857 } 858 859 static int hclgevf_tqp_enable(struct hnae3_handle *handle, bool enable) 860 { 861 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 862 int ret; 863 u16 i; 864 865 for (i = 0; i < handle->kinfo.num_tqps; i++) { 866 ret = hclgevf_tqp_enable_cmd_send(hdev, i, 0, enable); 867 if (ret) 868 return ret; 869 } 870 871 return 0; 872 } 873 874 static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p) 875 { 876 struct hclge_vf_to_pf_msg send_msg; 877 u8 host_mac[ETH_ALEN]; 878 int status; 879 880 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MAC_ADDR, 0); 881 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, host_mac, 882 ETH_ALEN); 883 if (status) { 884 dev_err(&hdev->pdev->dev, 885 "fail to get VF MAC from host %d", status); 886 return status; 887 } 888 889 ether_addr_copy(p, host_mac); 890 891 return 0; 892 } 893 894 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 895 { 896 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 897 u8 host_mac_addr[ETH_ALEN]; 898 899 if (hclgevf_get_host_mac_addr(hdev, host_mac_addr)) 900 return; 901 902 hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr); 903 if (hdev->has_pf_mac) 904 ether_addr_copy(p, host_mac_addr); 905 else 906 ether_addr_copy(p, hdev->hw.mac.mac_addr); 907 } 908 909 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, const void *p, 910 bool is_first) 911 { 912 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 913 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 914 struct hclge_vf_to_pf_msg send_msg; 915 u8 *new_mac_addr = (u8 *)p; 916 int status; 917 918 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 0); 919 send_msg.subcode = HCLGE_MBX_MAC_VLAN_UC_MODIFY; 920 ether_addr_copy(send_msg.data, new_mac_addr); 921 if (is_first && !hdev->has_pf_mac) 922 eth_zero_addr(&send_msg.data[ETH_ALEN]); 923 else 924 ether_addr_copy(&send_msg.data[ETH_ALEN], old_mac_addr); 925 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 926 if (!status) 927 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 928 929 return status; 930 } 931 932 static struct hclgevf_mac_addr_node * 933 hclgevf_find_mac_node(struct list_head *list, const u8 *mac_addr) 934 { 935 struct hclgevf_mac_addr_node *mac_node, *tmp; 936 937 list_for_each_entry_safe(mac_node, tmp, list, node) 938 if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 939 return mac_node; 940 941 return NULL; 942 } 943 944 static void hclgevf_update_mac_node(struct hclgevf_mac_addr_node *mac_node, 945 enum HCLGEVF_MAC_NODE_STATE state) 946 { 947 switch (state) { 948 /* from set_rx_mode or tmp_add_list */ 949 case HCLGEVF_MAC_TO_ADD: 950 if (mac_node->state == HCLGEVF_MAC_TO_DEL) 951 mac_node->state = HCLGEVF_MAC_ACTIVE; 952 break; 953 /* only from set_rx_mode */ 954 case HCLGEVF_MAC_TO_DEL: 955 if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 956 list_del(&mac_node->node); 957 kfree(mac_node); 958 } else { 959 mac_node->state = HCLGEVF_MAC_TO_DEL; 960 } 961 break; 962 /* only from tmp_add_list, the mac_node->state won't be 963 * HCLGEVF_MAC_ACTIVE 964 */ 965 case HCLGEVF_MAC_ACTIVE: 966 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 967 mac_node->state = HCLGEVF_MAC_ACTIVE; 968 break; 969 } 970 } 971 972 static int hclgevf_update_mac_list(struct hnae3_handle *handle, 973 enum HCLGEVF_MAC_NODE_STATE state, 974 enum HCLGEVF_MAC_ADDR_TYPE mac_type, 975 const unsigned char *addr) 976 { 977 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 978 struct hclgevf_mac_addr_node *mac_node; 979 struct list_head *list; 980 981 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 982 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 983 984 spin_lock_bh(&hdev->mac_table.mac_list_lock); 985 986 /* if the mac addr is already in the mac list, no need to add a new 987 * one into it, just check the mac addr state, convert it to a new 988 * new state, or just remove it, or do nothing. 989 */ 990 mac_node = hclgevf_find_mac_node(list, addr); 991 if (mac_node) { 992 hclgevf_update_mac_node(mac_node, state); 993 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 994 return 0; 995 } 996 /* if this address is never added, unnecessary to delete */ 997 if (state == HCLGEVF_MAC_TO_DEL) { 998 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 999 return -ENOENT; 1000 } 1001 1002 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 1003 if (!mac_node) { 1004 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1005 return -ENOMEM; 1006 } 1007 1008 mac_node->state = state; 1009 ether_addr_copy(mac_node->mac_addr, addr); 1010 list_add_tail(&mac_node->node, list); 1011 1012 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1013 return 0; 1014 } 1015 1016 static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1017 const unsigned char *addr) 1018 { 1019 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1020 HCLGEVF_MAC_ADDR_UC, addr); 1021 } 1022 1023 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1024 const unsigned char *addr) 1025 { 1026 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1027 HCLGEVF_MAC_ADDR_UC, addr); 1028 } 1029 1030 static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1031 const unsigned char *addr) 1032 { 1033 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1034 HCLGEVF_MAC_ADDR_MC, addr); 1035 } 1036 1037 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1038 const unsigned char *addr) 1039 { 1040 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1041 HCLGEVF_MAC_ADDR_MC, addr); 1042 } 1043 1044 static int hclgevf_add_del_mac_addr(struct hclgevf_dev *hdev, 1045 struct hclgevf_mac_addr_node *mac_node, 1046 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1047 { 1048 struct hclge_vf_to_pf_msg send_msg; 1049 u8 code, subcode; 1050 1051 if (mac_type == HCLGEVF_MAC_ADDR_UC) { 1052 code = HCLGE_MBX_SET_UNICAST; 1053 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1054 subcode = HCLGE_MBX_MAC_VLAN_UC_ADD; 1055 else 1056 subcode = HCLGE_MBX_MAC_VLAN_UC_REMOVE; 1057 } else { 1058 code = HCLGE_MBX_SET_MULTICAST; 1059 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1060 subcode = HCLGE_MBX_MAC_VLAN_MC_ADD; 1061 else 1062 subcode = HCLGE_MBX_MAC_VLAN_MC_REMOVE; 1063 } 1064 1065 hclgevf_build_send_msg(&send_msg, code, subcode); 1066 ether_addr_copy(send_msg.data, mac_node->mac_addr); 1067 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1068 } 1069 1070 static void hclgevf_config_mac_list(struct hclgevf_dev *hdev, 1071 struct list_head *list, 1072 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1073 { 1074 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 1075 struct hclgevf_mac_addr_node *mac_node, *tmp; 1076 int ret; 1077 1078 list_for_each_entry_safe(mac_node, tmp, list, node) { 1079 ret = hclgevf_add_del_mac_addr(hdev, mac_node, mac_type); 1080 if (ret) { 1081 hnae3_format_mac_addr(format_mac_addr, 1082 mac_node->mac_addr); 1083 dev_err(&hdev->pdev->dev, 1084 "failed to configure mac %s, state = %d, ret = %d\n", 1085 format_mac_addr, mac_node->state, ret); 1086 return; 1087 } 1088 if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1089 mac_node->state = HCLGEVF_MAC_ACTIVE; 1090 } else { 1091 list_del(&mac_node->node); 1092 kfree(mac_node); 1093 } 1094 } 1095 } 1096 1097 static void hclgevf_sync_from_add_list(struct list_head *add_list, 1098 struct list_head *mac_list) 1099 { 1100 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1101 1102 list_for_each_entry_safe(mac_node, tmp, add_list, node) { 1103 /* if the mac address from tmp_add_list is not in the 1104 * uc/mc_mac_list, it means have received a TO_DEL request 1105 * during the time window of sending mac config request to PF 1106 * If mac_node state is ACTIVE, then change its state to TO_DEL, 1107 * then it will be removed at next time. If is TO_ADD, it means 1108 * send TO_ADD request failed, so just remove the mac node. 1109 */ 1110 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1111 if (new_node) { 1112 hclgevf_update_mac_node(new_node, mac_node->state); 1113 list_del(&mac_node->node); 1114 kfree(mac_node); 1115 } else if (mac_node->state == HCLGEVF_MAC_ACTIVE) { 1116 mac_node->state = HCLGEVF_MAC_TO_DEL; 1117 list_move_tail(&mac_node->node, mac_list); 1118 } else { 1119 list_del(&mac_node->node); 1120 kfree(mac_node); 1121 } 1122 } 1123 } 1124 1125 static void hclgevf_sync_from_del_list(struct list_head *del_list, 1126 struct list_head *mac_list) 1127 { 1128 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1129 1130 list_for_each_entry_safe(mac_node, tmp, del_list, node) { 1131 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1132 if (new_node) { 1133 /* If the mac addr is exist in the mac list, it means 1134 * received a new request TO_ADD during the time window 1135 * of sending mac addr configurrequest to PF, so just 1136 * change the mac state to ACTIVE. 1137 */ 1138 new_node->state = HCLGEVF_MAC_ACTIVE; 1139 list_del(&mac_node->node); 1140 kfree(mac_node); 1141 } else { 1142 list_move_tail(&mac_node->node, mac_list); 1143 } 1144 } 1145 } 1146 1147 static void hclgevf_clear_list(struct list_head *list) 1148 { 1149 struct hclgevf_mac_addr_node *mac_node, *tmp; 1150 1151 list_for_each_entry_safe(mac_node, tmp, list, node) { 1152 list_del(&mac_node->node); 1153 kfree(mac_node); 1154 } 1155 } 1156 1157 static void hclgevf_sync_mac_list(struct hclgevf_dev *hdev, 1158 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1159 { 1160 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1161 struct list_head tmp_add_list, tmp_del_list; 1162 struct list_head *list; 1163 1164 INIT_LIST_HEAD(&tmp_add_list); 1165 INIT_LIST_HEAD(&tmp_del_list); 1166 1167 /* move the mac addr to the tmp_add_list and tmp_del_list, then 1168 * we can add/delete these mac addr outside the spin lock 1169 */ 1170 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1171 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1172 1173 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1174 1175 list_for_each_entry_safe(mac_node, tmp, list, node) { 1176 switch (mac_node->state) { 1177 case HCLGEVF_MAC_TO_DEL: 1178 list_move_tail(&mac_node->node, &tmp_del_list); 1179 break; 1180 case HCLGEVF_MAC_TO_ADD: 1181 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 1182 if (!new_node) 1183 goto stop_traverse; 1184 1185 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 1186 new_node->state = mac_node->state; 1187 list_add_tail(&new_node->node, &tmp_add_list); 1188 break; 1189 default: 1190 break; 1191 } 1192 } 1193 1194 stop_traverse: 1195 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1196 1197 /* delete first, in order to get max mac table space for adding */ 1198 hclgevf_config_mac_list(hdev, &tmp_del_list, mac_type); 1199 hclgevf_config_mac_list(hdev, &tmp_add_list, mac_type); 1200 1201 /* if some mac addresses were added/deleted fail, move back to the 1202 * mac_list, and retry at next time. 1203 */ 1204 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1205 1206 hclgevf_sync_from_del_list(&tmp_del_list, list); 1207 hclgevf_sync_from_add_list(&tmp_add_list, list); 1208 1209 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1210 } 1211 1212 static void hclgevf_sync_mac_table(struct hclgevf_dev *hdev) 1213 { 1214 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_UC); 1215 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_MC); 1216 } 1217 1218 static void hclgevf_uninit_mac_list(struct hclgevf_dev *hdev) 1219 { 1220 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1221 1222 hclgevf_clear_list(&hdev->mac_table.uc_mac_list); 1223 hclgevf_clear_list(&hdev->mac_table.mc_mac_list); 1224 1225 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1226 } 1227 1228 static int hclgevf_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 1229 { 1230 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1231 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 1232 struct hclge_vf_to_pf_msg send_msg; 1233 1234 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 1235 return -EOPNOTSUPP; 1236 1237 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1238 HCLGE_MBX_ENABLE_VLAN_FILTER); 1239 send_msg.data[0] = enable ? 1 : 0; 1240 1241 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1242 } 1243 1244 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1245 __be16 proto, u16 vlan_id, 1246 bool is_kill) 1247 { 1248 #define HCLGEVF_VLAN_MBX_IS_KILL_OFFSET 0 1249 #define HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET 1 1250 #define HCLGEVF_VLAN_MBX_PROTO_OFFSET 3 1251 1252 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1253 struct hclge_vf_to_pf_msg send_msg; 1254 int ret; 1255 1256 if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1257 return -EINVAL; 1258 1259 if (proto != htons(ETH_P_8021Q)) 1260 return -EPROTONOSUPPORT; 1261 1262 /* When device is resetting or reset failed, firmware is unable to 1263 * handle mailbox. Just record the vlan id, and remove it after 1264 * reset finished. 1265 */ 1266 if ((test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 1267 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) && is_kill) { 1268 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1269 return -EBUSY; 1270 } 1271 1272 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1273 HCLGE_MBX_VLAN_FILTER); 1274 send_msg.data[HCLGEVF_VLAN_MBX_IS_KILL_OFFSET] = is_kill; 1275 memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET], &vlan_id, 1276 sizeof(vlan_id)); 1277 memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_PROTO_OFFSET], &proto, 1278 sizeof(proto)); 1279 /* when remove hw vlan filter failed, record the vlan id, 1280 * and try to remove it from hw later, to be consistence 1281 * with stack. 1282 */ 1283 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1284 if (is_kill && ret) 1285 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1286 1287 return ret; 1288 } 1289 1290 static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1291 { 1292 #define HCLGEVF_MAX_SYNC_COUNT 60 1293 struct hnae3_handle *handle = &hdev->nic; 1294 int ret, sync_cnt = 0; 1295 u16 vlan_id; 1296 1297 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1298 while (vlan_id != VLAN_N_VID) { 1299 ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1300 vlan_id, true); 1301 if (ret) 1302 return; 1303 1304 clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1305 sync_cnt++; 1306 if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1307 return; 1308 1309 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1310 } 1311 } 1312 1313 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1314 { 1315 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1316 struct hclge_vf_to_pf_msg send_msg; 1317 1318 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1319 HCLGE_MBX_VLAN_RX_OFF_CFG); 1320 send_msg.data[0] = enable ? 1 : 0; 1321 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1322 } 1323 1324 static int hclgevf_reset_tqp(struct hnae3_handle *handle) 1325 { 1326 #define HCLGEVF_RESET_ALL_QUEUE_DONE 1U 1327 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1328 struct hclge_vf_to_pf_msg send_msg; 1329 u8 return_status = 0; 1330 int ret; 1331 u16 i; 1332 1333 /* disable vf queue before send queue reset msg to PF */ 1334 ret = hclgevf_tqp_enable(handle, false); 1335 if (ret) { 1336 dev_err(&hdev->pdev->dev, "failed to disable tqp, ret = %d\n", 1337 ret); 1338 return ret; 1339 } 1340 1341 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 1342 1343 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &return_status, 1344 sizeof(return_status)); 1345 if (ret || return_status == HCLGEVF_RESET_ALL_QUEUE_DONE) 1346 return ret; 1347 1348 for (i = 1; i < handle->kinfo.num_tqps; i++) { 1349 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 1350 memcpy(send_msg.data, &i, sizeof(i)); 1351 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1352 if (ret) 1353 return ret; 1354 } 1355 1356 return 0; 1357 } 1358 1359 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1360 { 1361 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1362 struct hclge_vf_to_pf_msg send_msg; 1363 1364 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MTU, 0); 1365 memcpy(send_msg.data, &new_mtu, sizeof(new_mtu)); 1366 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1367 } 1368 1369 static int hclgevf_notify_client(struct hclgevf_dev *hdev, 1370 enum hnae3_reset_notify_type type) 1371 { 1372 struct hnae3_client *client = hdev->nic_client; 1373 struct hnae3_handle *handle = &hdev->nic; 1374 int ret; 1375 1376 if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 1377 !client) 1378 return 0; 1379 1380 if (!client->ops->reset_notify) 1381 return -EOPNOTSUPP; 1382 1383 ret = client->ops->reset_notify(handle, type); 1384 if (ret) 1385 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 1386 type, ret); 1387 1388 return ret; 1389 } 1390 1391 static int hclgevf_notify_roce_client(struct hclgevf_dev *hdev, 1392 enum hnae3_reset_notify_type type) 1393 { 1394 struct hnae3_client *client = hdev->roce_client; 1395 struct hnae3_handle *handle = &hdev->roce; 1396 int ret; 1397 1398 if (!test_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state) || !client) 1399 return 0; 1400 1401 if (!client->ops->reset_notify) 1402 return -EOPNOTSUPP; 1403 1404 ret = client->ops->reset_notify(handle, type); 1405 if (ret) 1406 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 1407 type, ret); 1408 return ret; 1409 } 1410 1411 static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 1412 { 1413 #define HCLGEVF_RESET_WAIT_US 20000 1414 #define HCLGEVF_RESET_WAIT_CNT 2000 1415 #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1416 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1417 1418 u32 val; 1419 int ret; 1420 1421 if (hdev->reset_type == HNAE3_VF_RESET) 1422 ret = readl_poll_timeout(hdev->hw.hw.io_base + 1423 HCLGEVF_VF_RST_ING, val, 1424 !(val & HCLGEVF_VF_RST_ING_BIT), 1425 HCLGEVF_RESET_WAIT_US, 1426 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1427 else 1428 ret = readl_poll_timeout(hdev->hw.hw.io_base + 1429 HCLGEVF_RST_ING, val, 1430 !(val & HCLGEVF_RST_ING_BITS), 1431 HCLGEVF_RESET_WAIT_US, 1432 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1433 1434 /* hardware completion status should be available by this time */ 1435 if (ret) { 1436 dev_err(&hdev->pdev->dev, 1437 "couldn't get reset done status from h/w, timeout!\n"); 1438 return ret; 1439 } 1440 1441 /* we will wait a bit more to let reset of the stack to complete. This 1442 * might happen in case reset assertion was made by PF. Yes, this also 1443 * means we might end up waiting bit more even for VF reset. 1444 */ 1445 msleep(5000); 1446 1447 return 0; 1448 } 1449 1450 static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable) 1451 { 1452 u32 reg_val; 1453 1454 reg_val = hclgevf_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG); 1455 if (enable) 1456 reg_val |= HCLGEVF_NIC_SW_RST_RDY; 1457 else 1458 reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; 1459 1460 hclgevf_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, 1461 reg_val); 1462 } 1463 1464 static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 1465 { 1466 int ret; 1467 1468 /* uninitialize the nic client */ 1469 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 1470 if (ret) 1471 return ret; 1472 1473 /* re-initialize the hclge device */ 1474 ret = hclgevf_reset_hdev(hdev); 1475 if (ret) { 1476 dev_err(&hdev->pdev->dev, 1477 "hclge device re-init failed, VF is disabled!\n"); 1478 return ret; 1479 } 1480 1481 /* bring up the nic client again */ 1482 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 1483 if (ret) 1484 return ret; 1485 1486 /* clear handshake status with IMP */ 1487 hclgevf_reset_handshake(hdev, false); 1488 1489 /* bring up the nic to enable TX/RX again */ 1490 return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 1491 } 1492 1493 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1494 { 1495 #define HCLGEVF_RESET_SYNC_TIME 100 1496 1497 if (hdev->reset_type == HNAE3_VF_FUNC_RESET) { 1498 struct hclge_vf_to_pf_msg send_msg; 1499 int ret; 1500 1501 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_RESET, 0); 1502 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1503 if (ret) { 1504 dev_err(&hdev->pdev->dev, 1505 "failed to assert VF reset, ret = %d\n", ret); 1506 return ret; 1507 } 1508 hdev->rst_stats.vf_func_rst_cnt++; 1509 } 1510 1511 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 1512 /* inform hardware that preparatory work is done */ 1513 msleep(HCLGEVF_RESET_SYNC_TIME); 1514 hclgevf_reset_handshake(hdev, true); 1515 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done\n", 1516 hdev->reset_type); 1517 1518 return 0; 1519 } 1520 1521 static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev) 1522 { 1523 dev_info(&hdev->pdev->dev, "VF function reset count: %u\n", 1524 hdev->rst_stats.vf_func_rst_cnt); 1525 dev_info(&hdev->pdev->dev, "FLR reset count: %u\n", 1526 hdev->rst_stats.flr_rst_cnt); 1527 dev_info(&hdev->pdev->dev, "VF reset count: %u\n", 1528 hdev->rst_stats.vf_rst_cnt); 1529 dev_info(&hdev->pdev->dev, "reset done count: %u\n", 1530 hdev->rst_stats.rst_done_cnt); 1531 dev_info(&hdev->pdev->dev, "HW reset done count: %u\n", 1532 hdev->rst_stats.hw_rst_done_cnt); 1533 dev_info(&hdev->pdev->dev, "reset count: %u\n", 1534 hdev->rst_stats.rst_cnt); 1535 dev_info(&hdev->pdev->dev, "reset fail count: %u\n", 1536 hdev->rst_stats.rst_fail_cnt); 1537 dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n", 1538 hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE)); 1539 dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n", 1540 hclgevf_read_dev(&hdev->hw, HCLGE_COMM_VECTOR0_CMDQ_STATE_REG)); 1541 dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n", 1542 hclgevf_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG)); 1543 dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n", 1544 hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING)); 1545 dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state); 1546 } 1547 1548 static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1549 { 1550 /* recover handshake status with IMP when reset fail */ 1551 hclgevf_reset_handshake(hdev, true); 1552 hdev->rst_stats.rst_fail_cnt++; 1553 dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n", 1554 hdev->rst_stats.rst_fail_cnt); 1555 1556 if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1557 set_bit(hdev->reset_type, &hdev->reset_pending); 1558 1559 if (hclgevf_is_reset_pending(hdev)) { 1560 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1561 hclgevf_reset_task_schedule(hdev); 1562 } else { 1563 set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1564 hclgevf_dump_rst_info(hdev); 1565 } 1566 } 1567 1568 static int hclgevf_reset_prepare(struct hclgevf_dev *hdev) 1569 { 1570 int ret; 1571 1572 hdev->rst_stats.rst_cnt++; 1573 1574 /* perform reset of the stack & ae device for a client */ 1575 ret = hclgevf_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 1576 if (ret) 1577 return ret; 1578 1579 rtnl_lock(); 1580 /* bring down the nic to stop any ongoing TX/RX */ 1581 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 1582 rtnl_unlock(); 1583 if (ret) 1584 return ret; 1585 1586 return hclgevf_reset_prepare_wait(hdev); 1587 } 1588 1589 static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev) 1590 { 1591 int ret; 1592 1593 hdev->rst_stats.hw_rst_done_cnt++; 1594 ret = hclgevf_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 1595 if (ret) 1596 return ret; 1597 1598 rtnl_lock(); 1599 /* now, re-initialize the nic client and ae device */ 1600 ret = hclgevf_reset_stack(hdev); 1601 rtnl_unlock(); 1602 if (ret) { 1603 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 1604 return ret; 1605 } 1606 1607 ret = hclgevf_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 1608 /* ignore RoCE notify error if it fails HCLGEVF_RESET_MAX_FAIL_CNT - 1 1609 * times 1610 */ 1611 if (ret && 1612 hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT - 1) 1613 return ret; 1614 1615 ret = hclgevf_notify_roce_client(hdev, HNAE3_UP_CLIENT); 1616 if (ret) 1617 return ret; 1618 1619 hdev->last_reset_time = jiffies; 1620 hdev->rst_stats.rst_done_cnt++; 1621 hdev->rst_stats.rst_fail_cnt = 0; 1622 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1623 1624 return 0; 1625 } 1626 1627 static void hclgevf_reset(struct hclgevf_dev *hdev) 1628 { 1629 if (hclgevf_reset_prepare(hdev)) 1630 goto err_reset; 1631 1632 /* check if VF could successfully fetch the hardware reset completion 1633 * status from the hardware 1634 */ 1635 if (hclgevf_reset_wait(hdev)) { 1636 /* can't do much in this situation, will disable VF */ 1637 dev_err(&hdev->pdev->dev, 1638 "failed to fetch H/W reset completion status\n"); 1639 goto err_reset; 1640 } 1641 1642 if (hclgevf_reset_rebuild(hdev)) 1643 goto err_reset; 1644 1645 return; 1646 1647 err_reset: 1648 hclgevf_reset_err_handle(hdev); 1649 } 1650 1651 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1652 unsigned long *addr) 1653 { 1654 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1655 1656 /* return the highest priority reset level amongst all */ 1657 if (test_bit(HNAE3_VF_RESET, addr)) { 1658 rst_level = HNAE3_VF_RESET; 1659 clear_bit(HNAE3_VF_RESET, addr); 1660 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1661 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1662 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1663 rst_level = HNAE3_VF_FULL_RESET; 1664 clear_bit(HNAE3_VF_FULL_RESET, addr); 1665 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1666 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1667 rst_level = HNAE3_VF_PF_FUNC_RESET; 1668 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1669 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1670 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1671 rst_level = HNAE3_VF_FUNC_RESET; 1672 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1673 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 1674 rst_level = HNAE3_FLR_RESET; 1675 clear_bit(HNAE3_FLR_RESET, addr); 1676 } 1677 1678 return rst_level; 1679 } 1680 1681 static void hclgevf_reset_event(struct pci_dev *pdev, 1682 struct hnae3_handle *handle) 1683 { 1684 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1685 struct hclgevf_dev *hdev = ae_dev->priv; 1686 1687 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 1688 1689 if (hdev->default_reset_request) 1690 hdev->reset_level = 1691 hclgevf_get_reset_level(hdev, 1692 &hdev->default_reset_request); 1693 else 1694 hdev->reset_level = HNAE3_VF_FUNC_RESET; 1695 1696 /* reset of this VF requested */ 1697 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1698 hclgevf_reset_task_schedule(hdev); 1699 1700 hdev->last_reset_time = jiffies; 1701 } 1702 1703 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1704 enum hnae3_reset_type rst_type) 1705 { 1706 struct hclgevf_dev *hdev = ae_dev->priv; 1707 1708 set_bit(rst_type, &hdev->default_reset_request); 1709 } 1710 1711 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1712 { 1713 writel(en ? 1 : 0, vector->addr); 1714 } 1715 1716 static void hclgevf_reset_prepare_general(struct hnae3_ae_dev *ae_dev, 1717 enum hnae3_reset_type rst_type) 1718 { 1719 #define HCLGEVF_RESET_RETRY_WAIT_MS 500 1720 #define HCLGEVF_RESET_RETRY_CNT 5 1721 1722 struct hclgevf_dev *hdev = ae_dev->priv; 1723 int retry_cnt = 0; 1724 int ret; 1725 1726 while (retry_cnt++ < HCLGEVF_RESET_RETRY_CNT) { 1727 down(&hdev->reset_sem); 1728 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1729 hdev->reset_type = rst_type; 1730 ret = hclgevf_reset_prepare(hdev); 1731 if (!ret && !hdev->reset_pending) 1732 break; 1733 1734 dev_err(&hdev->pdev->dev, 1735 "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n", 1736 ret, hdev->reset_pending, retry_cnt); 1737 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1738 up(&hdev->reset_sem); 1739 msleep(HCLGEVF_RESET_RETRY_WAIT_MS); 1740 } 1741 1742 /* disable misc vector before reset done */ 1743 hclgevf_enable_vector(&hdev->misc_vector, false); 1744 1745 if (hdev->reset_type == HNAE3_FLR_RESET) 1746 hdev->rst_stats.flr_rst_cnt++; 1747 } 1748 1749 static void hclgevf_reset_done(struct hnae3_ae_dev *ae_dev) 1750 { 1751 struct hclgevf_dev *hdev = ae_dev->priv; 1752 int ret; 1753 1754 hclgevf_enable_vector(&hdev->misc_vector, true); 1755 1756 ret = hclgevf_reset_rebuild(hdev); 1757 if (ret) 1758 dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", 1759 ret); 1760 1761 hdev->reset_type = HNAE3_NONE_RESET; 1762 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1763 up(&hdev->reset_sem); 1764 } 1765 1766 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1767 { 1768 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1769 1770 return hdev->fw_version; 1771 } 1772 1773 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1774 { 1775 struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1776 1777 vector->vector_irq = pci_irq_vector(hdev->pdev, 1778 HCLGEVF_MISC_VECTOR_NUM); 1779 vector->addr = hdev->hw.hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1780 /* vector status always valid for Vector 0 */ 1781 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1782 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1783 1784 hdev->num_msi_left -= 1; 1785 hdev->num_msi_used += 1; 1786 } 1787 1788 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 1789 { 1790 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1791 test_bit(HCLGEVF_STATE_SERVICE_INITED, &hdev->state) && 1792 !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, 1793 &hdev->state)) 1794 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 1795 } 1796 1797 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1798 { 1799 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1800 !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, 1801 &hdev->state)) 1802 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 1803 } 1804 1805 static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 1806 unsigned long delay) 1807 { 1808 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1809 !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 1810 mod_delayed_work(hclgevf_wq, &hdev->service_task, delay); 1811 } 1812 1813 static void hclgevf_reset_service_task(struct hclgevf_dev *hdev) 1814 { 1815 #define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3 1816 1817 if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state)) 1818 return; 1819 1820 down(&hdev->reset_sem); 1821 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1822 1823 if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1824 &hdev->reset_state)) { 1825 /* PF has intimated that it is about to reset the hardware. 1826 * We now have to poll & check if hardware has actually 1827 * completed the reset sequence. On hardware reset completion, 1828 * VF needs to reset the client and ae device. 1829 */ 1830 hdev->reset_attempts = 0; 1831 1832 hdev->last_reset_time = jiffies; 1833 hdev->reset_type = 1834 hclgevf_get_reset_level(hdev, &hdev->reset_pending); 1835 if (hdev->reset_type != HNAE3_NONE_RESET) 1836 hclgevf_reset(hdev); 1837 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1838 &hdev->reset_state)) { 1839 /* we could be here when either of below happens: 1840 * 1. reset was initiated due to watchdog timeout caused by 1841 * a. IMP was earlier reset and our TX got choked down and 1842 * which resulted in watchdog reacting and inducing VF 1843 * reset. This also means our cmdq would be unreliable. 1844 * b. problem in TX due to other lower layer(example link 1845 * layer not functioning properly etc.) 1846 * 2. VF reset might have been initiated due to some config 1847 * change. 1848 * 1849 * NOTE: Theres no clear way to detect above cases than to react 1850 * to the response of PF for this reset request. PF will ack the 1851 * 1b and 2. cases but we will not get any intimation about 1a 1852 * from PF as cmdq would be in unreliable state i.e. mailbox 1853 * communication between PF and VF would be broken. 1854 * 1855 * if we are never geting into pending state it means either: 1856 * 1. PF is not receiving our request which could be due to IMP 1857 * reset 1858 * 2. PF is screwed 1859 * We cannot do much for 2. but to check first we can try reset 1860 * our PCIe + stack and see if it alleviates the problem. 1861 */ 1862 if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) { 1863 /* prepare for full reset of stack + pcie interface */ 1864 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1865 1866 /* "defer" schedule the reset task again */ 1867 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1868 } else { 1869 hdev->reset_attempts++; 1870 1871 set_bit(hdev->reset_level, &hdev->reset_pending); 1872 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1873 } 1874 hclgevf_reset_task_schedule(hdev); 1875 } 1876 1877 hdev->reset_type = HNAE3_NONE_RESET; 1878 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1879 up(&hdev->reset_sem); 1880 } 1881 1882 static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev) 1883 { 1884 if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state)) 1885 return; 1886 1887 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1888 return; 1889 1890 hclgevf_mbx_async_handler(hdev); 1891 1892 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1893 } 1894 1895 static void hclgevf_keep_alive(struct hclgevf_dev *hdev) 1896 { 1897 struct hclge_vf_to_pf_msg send_msg; 1898 int ret; 1899 1900 if (test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state)) 1901 return; 1902 1903 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_KEEP_ALIVE, 0); 1904 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1905 if (ret) 1906 dev_err(&hdev->pdev->dev, 1907 "VF sends keep alive cmd failed(=%d)\n", ret); 1908 } 1909 1910 static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev) 1911 { 1912 unsigned long delta = round_jiffies_relative(HZ); 1913 struct hnae3_handle *handle = &hdev->nic; 1914 1915 if (test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 1916 return; 1917 1918 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 1919 delta = jiffies - hdev->last_serv_processed; 1920 1921 if (delta < round_jiffies_relative(HZ)) { 1922 delta = round_jiffies_relative(HZ) - delta; 1923 goto out; 1924 } 1925 } 1926 1927 hdev->serv_processed_cnt++; 1928 if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL)) 1929 hclgevf_keep_alive(hdev); 1930 1931 if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) { 1932 hdev->last_serv_processed = jiffies; 1933 goto out; 1934 } 1935 1936 if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL)) 1937 hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 1938 1939 /* VF does not need to request link status when this bit is set, because 1940 * PF will push its link status to VFs when link status changed. 1941 */ 1942 if (!test_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state)) 1943 hclgevf_request_link_info(hdev); 1944 1945 hclgevf_update_link_mode(hdev); 1946 1947 hclgevf_sync_vlan_filter(hdev); 1948 1949 hclgevf_sync_mac_table(hdev); 1950 1951 hclgevf_sync_promisc_mode(hdev); 1952 1953 hdev->last_serv_processed = jiffies; 1954 1955 out: 1956 hclgevf_task_schedule(hdev, delta); 1957 } 1958 1959 static void hclgevf_service_task(struct work_struct *work) 1960 { 1961 struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev, 1962 service_task.work); 1963 1964 hclgevf_reset_service_task(hdev); 1965 hclgevf_mailbox_service_task(hdev); 1966 hclgevf_periodic_service_task(hdev); 1967 1968 /* Handle reset and mbx again in case periodical task delays the 1969 * handling by calling hclgevf_task_schedule() in 1970 * hclgevf_periodic_service_task() 1971 */ 1972 hclgevf_reset_service_task(hdev); 1973 hclgevf_mailbox_service_task(hdev); 1974 } 1975 1976 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1977 { 1978 hclgevf_write_dev(&hdev->hw, HCLGE_COMM_VECTOR0_CMDQ_SRC_REG, regclr); 1979 } 1980 1981 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1982 u32 *clearval) 1983 { 1984 u32 val, cmdq_stat_reg, rst_ing_reg; 1985 1986 /* fetch the events from their corresponding regs */ 1987 cmdq_stat_reg = hclgevf_read_dev(&hdev->hw, 1988 HCLGE_COMM_VECTOR0_CMDQ_STATE_REG); 1989 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 1990 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1991 dev_info(&hdev->pdev->dev, 1992 "receive reset interrupt 0x%x!\n", rst_ing_reg); 1993 set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1994 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1995 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 1996 *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B); 1997 hdev->rst_stats.vf_rst_cnt++; 1998 /* set up VF hardware reset status, its PF will clear 1999 * this status when PF has initialized done. 2000 */ 2001 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING); 2002 hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING, 2003 val | HCLGEVF_VF_RST_ING_BIT); 2004 return HCLGEVF_VECTOR0_EVENT_RST; 2005 } 2006 2007 /* check for vector0 mailbox(=CMDQ RX) event source */ 2008 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 2009 /* for revision 0x21, clearing interrupt is writing bit 0 2010 * to the clear register, writing bit 1 means to keep the 2011 * old value. 2012 * for revision 0x20, the clear register is a read & write 2013 * register, so we should just write 0 to the bit we are 2014 * handling, and keep other bits as cmdq_stat_reg. 2015 */ 2016 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) 2017 *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 2018 else 2019 *clearval = cmdq_stat_reg & 2020 ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 2021 2022 return HCLGEVF_VECTOR0_EVENT_MBX; 2023 } 2024 2025 /* print other vector0 event source */ 2026 dev_info(&hdev->pdev->dev, 2027 "vector 0 interrupt from unknown source, cmdq_src = %#x\n", 2028 cmdq_stat_reg); 2029 2030 return HCLGEVF_VECTOR0_EVENT_OTHER; 2031 } 2032 2033 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 2034 { 2035 enum hclgevf_evt_cause event_cause; 2036 struct hclgevf_dev *hdev = data; 2037 u32 clearval; 2038 2039 hclgevf_enable_vector(&hdev->misc_vector, false); 2040 event_cause = hclgevf_check_evt_cause(hdev, &clearval); 2041 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) 2042 hclgevf_clear_event_cause(hdev, clearval); 2043 2044 switch (event_cause) { 2045 case HCLGEVF_VECTOR0_EVENT_RST: 2046 hclgevf_reset_task_schedule(hdev); 2047 break; 2048 case HCLGEVF_VECTOR0_EVENT_MBX: 2049 hclgevf_mbx_handler(hdev); 2050 break; 2051 default: 2052 break; 2053 } 2054 2055 hclgevf_enable_vector(&hdev->misc_vector, true); 2056 2057 return IRQ_HANDLED; 2058 } 2059 2060 static int hclgevf_configure(struct hclgevf_dev *hdev) 2061 { 2062 int ret; 2063 2064 hdev->gro_en = true; 2065 2066 ret = hclgevf_get_basic_info(hdev); 2067 if (ret) 2068 return ret; 2069 2070 /* get current port based vlan state from PF */ 2071 ret = hclgevf_get_port_base_vlan_filter_state(hdev); 2072 if (ret) 2073 return ret; 2074 2075 /* get queue configuration from PF */ 2076 ret = hclgevf_get_queue_info(hdev); 2077 if (ret) 2078 return ret; 2079 2080 /* get queue depth info from PF */ 2081 ret = hclgevf_get_queue_depth(hdev); 2082 if (ret) 2083 return ret; 2084 2085 return hclgevf_get_pf_media_type(hdev); 2086 } 2087 2088 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 2089 { 2090 struct pci_dev *pdev = ae_dev->pdev; 2091 struct hclgevf_dev *hdev; 2092 2093 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 2094 if (!hdev) 2095 return -ENOMEM; 2096 2097 hdev->pdev = pdev; 2098 hdev->ae_dev = ae_dev; 2099 ae_dev->priv = hdev; 2100 2101 return 0; 2102 } 2103 2104 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 2105 { 2106 struct hnae3_handle *roce = &hdev->roce; 2107 struct hnae3_handle *nic = &hdev->nic; 2108 2109 roce->rinfo.num_vectors = hdev->num_roce_msix; 2110 2111 if (hdev->num_msi_left < roce->rinfo.num_vectors || 2112 hdev->num_msi_left == 0) 2113 return -EINVAL; 2114 2115 roce->rinfo.base_vector = hdev->roce_base_msix_offset; 2116 2117 roce->rinfo.netdev = nic->kinfo.netdev; 2118 roce->rinfo.roce_io_base = hdev->hw.hw.io_base; 2119 roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base; 2120 2121 roce->pdev = nic->pdev; 2122 roce->ae_algo = nic->ae_algo; 2123 roce->numa_node_mask = nic->numa_node_mask; 2124 2125 return 0; 2126 } 2127 2128 static int hclgevf_config_gro(struct hclgevf_dev *hdev) 2129 { 2130 struct hclgevf_cfg_gro_status_cmd *req; 2131 struct hclge_desc desc; 2132 int ret; 2133 2134 if (!hnae3_dev_gro_supported(hdev)) 2135 return 0; 2136 2137 hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, 2138 false); 2139 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2140 2141 req->gro_en = hdev->gro_en ? 1 : 0; 2142 2143 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2144 if (ret) 2145 dev_err(&hdev->pdev->dev, 2146 "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2147 2148 return ret; 2149 } 2150 2151 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2152 { 2153 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 2154 u16 tc_offset[HCLGE_COMM_MAX_TC_NUM]; 2155 u16 tc_valid[HCLGE_COMM_MAX_TC_NUM]; 2156 u16 tc_size[HCLGE_COMM_MAX_TC_NUM]; 2157 int ret; 2158 2159 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 2160 ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, 2161 rss_cfg->rss_algo, 2162 rss_cfg->rss_hash_key); 2163 if (ret) 2164 return ret; 2165 2166 ret = hclge_comm_set_rss_input_tuple(&hdev->nic, &hdev->hw.hw, 2167 false, rss_cfg); 2168 if (ret) 2169 return ret; 2170 } 2171 2172 ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 2173 rss_cfg->rss_indirection_tbl); 2174 if (ret) 2175 return ret; 2176 2177 hclge_comm_get_rss_tc_info(rss_cfg->rss_size, hdev->hw_tc_map, 2178 tc_offset, tc_valid, tc_size); 2179 2180 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, 2181 tc_valid, tc_size); 2182 } 2183 2184 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2185 { 2186 struct hnae3_handle *nic = &hdev->nic; 2187 int ret; 2188 2189 ret = hclgevf_en_hw_strip_rxvtag(nic, true); 2190 if (ret) { 2191 dev_err(&hdev->pdev->dev, 2192 "failed to enable rx vlan offload, ret = %d\n", ret); 2193 return ret; 2194 } 2195 2196 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2197 false); 2198 } 2199 2200 static void hclgevf_flush_link_update(struct hclgevf_dev *hdev) 2201 { 2202 #define HCLGEVF_FLUSH_LINK_TIMEOUT 100000 2203 2204 unsigned long last = hdev->serv_processed_cnt; 2205 int i = 0; 2206 2207 while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) && 2208 i++ < HCLGEVF_FLUSH_LINK_TIMEOUT && 2209 last == hdev->serv_processed_cnt) 2210 usleep_range(1, 1); 2211 } 2212 2213 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 2214 { 2215 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2216 2217 if (enable) { 2218 hclgevf_task_schedule(hdev, 0); 2219 } else { 2220 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2221 2222 /* flush memory to make sure DOWN is seen by service task */ 2223 smp_mb__before_atomic(); 2224 hclgevf_flush_link_update(hdev); 2225 } 2226 } 2227 2228 static int hclgevf_ae_start(struct hnae3_handle *handle) 2229 { 2230 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2231 2232 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2233 clear_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state); 2234 2235 hclge_comm_reset_tqp_stats(handle); 2236 2237 hclgevf_request_link_info(hdev); 2238 2239 hclgevf_update_link_mode(hdev); 2240 2241 return 0; 2242 } 2243 2244 static void hclgevf_ae_stop(struct hnae3_handle *handle) 2245 { 2246 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2247 2248 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2249 2250 if (hdev->reset_type != HNAE3_VF_RESET) 2251 hclgevf_reset_tqp(handle); 2252 2253 hclge_comm_reset_tqp_stats(handle); 2254 hclgevf_update_link_status(hdev, 0); 2255 } 2256 2257 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2258 { 2259 #define HCLGEVF_STATE_ALIVE 1 2260 #define HCLGEVF_STATE_NOT_ALIVE 0 2261 2262 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2263 struct hclge_vf_to_pf_msg send_msg; 2264 2265 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_ALIVE, 0); 2266 send_msg.data[0] = alive ? HCLGEVF_STATE_ALIVE : 2267 HCLGEVF_STATE_NOT_ALIVE; 2268 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2269 } 2270 2271 static int hclgevf_client_start(struct hnae3_handle *handle) 2272 { 2273 return hclgevf_set_alive(handle, true); 2274 } 2275 2276 static void hclgevf_client_stop(struct hnae3_handle *handle) 2277 { 2278 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2279 int ret; 2280 2281 ret = hclgevf_set_alive(handle, false); 2282 if (ret) 2283 dev_warn(&hdev->pdev->dev, 2284 "%s failed %d\n", __func__, ret); 2285 } 2286 2287 static void hclgevf_state_init(struct hclgevf_dev *hdev) 2288 { 2289 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2290 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2291 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 2292 2293 INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task); 2294 2295 mutex_init(&hdev->mbx_resp.mbx_mutex); 2296 sema_init(&hdev->reset_sem, 1); 2297 2298 spin_lock_init(&hdev->mac_table.mac_list_lock); 2299 INIT_LIST_HEAD(&hdev->mac_table.uc_mac_list); 2300 INIT_LIST_HEAD(&hdev->mac_table.mc_mac_list); 2301 2302 /* bring the device down */ 2303 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2304 } 2305 2306 static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2307 { 2308 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2309 set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2310 2311 if (hdev->service_task.work.func) 2312 cancel_delayed_work_sync(&hdev->service_task); 2313 2314 mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2315 } 2316 2317 static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2318 { 2319 struct pci_dev *pdev = hdev->pdev; 2320 int vectors; 2321 int i; 2322 2323 if (hnae3_dev_roce_supported(hdev)) 2324 vectors = pci_alloc_irq_vectors(pdev, 2325 hdev->roce_base_msix_offset + 1, 2326 hdev->num_msi, 2327 PCI_IRQ_MSIX); 2328 else 2329 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2330 hdev->num_msi, 2331 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2332 2333 if (vectors < 0) { 2334 dev_err(&pdev->dev, 2335 "failed(%d) to allocate MSI/MSI-X vectors\n", 2336 vectors); 2337 return vectors; 2338 } 2339 if (vectors < hdev->num_msi) 2340 dev_warn(&hdev->pdev->dev, 2341 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2342 hdev->num_msi, vectors); 2343 2344 hdev->num_msi = vectors; 2345 hdev->num_msi_left = vectors; 2346 2347 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2348 sizeof(u16), GFP_KERNEL); 2349 if (!hdev->vector_status) { 2350 pci_free_irq_vectors(pdev); 2351 return -ENOMEM; 2352 } 2353 2354 for (i = 0; i < hdev->num_msi; i++) 2355 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2356 2357 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2358 sizeof(int), GFP_KERNEL); 2359 if (!hdev->vector_irq) { 2360 devm_kfree(&pdev->dev, hdev->vector_status); 2361 pci_free_irq_vectors(pdev); 2362 return -ENOMEM; 2363 } 2364 2365 return 0; 2366 } 2367 2368 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2369 { 2370 struct pci_dev *pdev = hdev->pdev; 2371 2372 devm_kfree(&pdev->dev, hdev->vector_status); 2373 devm_kfree(&pdev->dev, hdev->vector_irq); 2374 pci_free_irq_vectors(pdev); 2375 } 2376 2377 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2378 { 2379 int ret; 2380 2381 hclgevf_get_misc_vector(hdev); 2382 2383 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 2384 HCLGEVF_NAME, pci_name(hdev->pdev)); 2385 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2386 0, hdev->misc_vector.name, hdev); 2387 if (ret) { 2388 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2389 hdev->misc_vector.vector_irq); 2390 return ret; 2391 } 2392 2393 hclgevf_clear_event_cause(hdev, 0); 2394 2395 /* enable misc. vector(vector 0) */ 2396 hclgevf_enable_vector(&hdev->misc_vector, true); 2397 2398 return ret; 2399 } 2400 2401 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2402 { 2403 /* disable misc vector(vector 0) */ 2404 hclgevf_enable_vector(&hdev->misc_vector, false); 2405 synchronize_irq(hdev->misc_vector.vector_irq); 2406 free_irq(hdev->misc_vector.vector_irq, hdev); 2407 hclgevf_free_vector(hdev, 0); 2408 } 2409 2410 static void hclgevf_info_show(struct hclgevf_dev *hdev) 2411 { 2412 struct device *dev = &hdev->pdev->dev; 2413 2414 dev_info(dev, "VF info begin:\n"); 2415 2416 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 2417 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 2418 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 2419 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 2420 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 2421 dev_info(dev, "PF media type of this VF: %u\n", 2422 hdev->hw.mac.media_type); 2423 2424 dev_info(dev, "VF info end.\n"); 2425 } 2426 2427 static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 2428 struct hnae3_client *client) 2429 { 2430 struct hclgevf_dev *hdev = ae_dev->priv; 2431 int rst_cnt = hdev->rst_stats.rst_cnt; 2432 int ret; 2433 2434 ret = client->ops->init_instance(&hdev->nic); 2435 if (ret) 2436 return ret; 2437 2438 set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2439 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 2440 rst_cnt != hdev->rst_stats.rst_cnt) { 2441 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2442 2443 client->ops->uninit_instance(&hdev->nic, 0); 2444 return -EBUSY; 2445 } 2446 2447 hnae3_set_client_init_flag(client, ae_dev, 1); 2448 2449 if (netif_msg_drv(&hdev->nic)) 2450 hclgevf_info_show(hdev); 2451 2452 return 0; 2453 } 2454 2455 static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 2456 struct hnae3_client *client) 2457 { 2458 struct hclgevf_dev *hdev = ae_dev->priv; 2459 int ret; 2460 2461 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 2462 !hdev->nic_client) 2463 return 0; 2464 2465 ret = hclgevf_init_roce_base_info(hdev); 2466 if (ret) 2467 return ret; 2468 2469 ret = client->ops->init_instance(&hdev->roce); 2470 if (ret) 2471 return ret; 2472 2473 set_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 2474 hnae3_set_client_init_flag(client, ae_dev, 1); 2475 2476 return 0; 2477 } 2478 2479 static int hclgevf_init_client_instance(struct hnae3_client *client, 2480 struct hnae3_ae_dev *ae_dev) 2481 { 2482 struct hclgevf_dev *hdev = ae_dev->priv; 2483 int ret; 2484 2485 switch (client->type) { 2486 case HNAE3_CLIENT_KNIC: 2487 hdev->nic_client = client; 2488 hdev->nic.client = client; 2489 2490 ret = hclgevf_init_nic_client_instance(ae_dev, client); 2491 if (ret) 2492 goto clear_nic; 2493 2494 ret = hclgevf_init_roce_client_instance(ae_dev, 2495 hdev->roce_client); 2496 if (ret) 2497 goto clear_roce; 2498 2499 break; 2500 case HNAE3_CLIENT_ROCE: 2501 if (hnae3_dev_roce_supported(hdev)) { 2502 hdev->roce_client = client; 2503 hdev->roce.client = client; 2504 } 2505 2506 ret = hclgevf_init_roce_client_instance(ae_dev, client); 2507 if (ret) 2508 goto clear_roce; 2509 2510 break; 2511 default: 2512 return -EINVAL; 2513 } 2514 2515 return 0; 2516 2517 clear_nic: 2518 hdev->nic_client = NULL; 2519 hdev->nic.client = NULL; 2520 return ret; 2521 clear_roce: 2522 hdev->roce_client = NULL; 2523 hdev->roce.client = NULL; 2524 return ret; 2525 } 2526 2527 static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2528 struct hnae3_ae_dev *ae_dev) 2529 { 2530 struct hclgevf_dev *hdev = ae_dev->priv; 2531 2532 /* un-init roce, if it exists */ 2533 if (hdev->roce_client) { 2534 while (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 2535 msleep(HCLGEVF_WAIT_RESET_DONE); 2536 clear_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 2537 2538 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 2539 hdev->roce_client = NULL; 2540 hdev->roce.client = NULL; 2541 } 2542 2543 /* un-init nic/unic, if this was not called by roce client */ 2544 if (client->ops->uninit_instance && hdev->nic_client && 2545 client->type != HNAE3_CLIENT_ROCE) { 2546 while (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 2547 msleep(HCLGEVF_WAIT_RESET_DONE); 2548 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2549 2550 client->ops->uninit_instance(&hdev->nic, 0); 2551 hdev->nic_client = NULL; 2552 hdev->nic.client = NULL; 2553 } 2554 } 2555 2556 static int hclgevf_dev_mem_map(struct hclgevf_dev *hdev) 2557 { 2558 struct pci_dev *pdev = hdev->pdev; 2559 struct hclgevf_hw *hw = &hdev->hw; 2560 2561 /* for device does not have device memory, return directly */ 2562 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGEVF_MEM_BAR))) 2563 return 0; 2564 2565 hw->hw.mem_base = 2566 devm_ioremap_wc(&pdev->dev, 2567 pci_resource_start(pdev, HCLGEVF_MEM_BAR), 2568 pci_resource_len(pdev, HCLGEVF_MEM_BAR)); 2569 if (!hw->hw.mem_base) { 2570 dev_err(&pdev->dev, "failed to map device memory\n"); 2571 return -EFAULT; 2572 } 2573 2574 return 0; 2575 } 2576 2577 static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2578 { 2579 struct pci_dev *pdev = hdev->pdev; 2580 struct hclgevf_hw *hw; 2581 int ret; 2582 2583 ret = pci_enable_device(pdev); 2584 if (ret) { 2585 dev_err(&pdev->dev, "failed to enable PCI device\n"); 2586 return ret; 2587 } 2588 2589 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2590 if (ret) { 2591 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2592 goto err_disable_device; 2593 } 2594 2595 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2596 if (ret) { 2597 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2598 goto err_disable_device; 2599 } 2600 2601 pci_set_master(pdev); 2602 hw = &hdev->hw; 2603 hw->hw.io_base = pci_iomap(pdev, 2, 0); 2604 if (!hw->hw.io_base) { 2605 dev_err(&pdev->dev, "can't map configuration register space\n"); 2606 ret = -ENOMEM; 2607 goto err_clr_master; 2608 } 2609 2610 ret = hclgevf_dev_mem_map(hdev); 2611 if (ret) 2612 goto err_unmap_io_base; 2613 2614 return 0; 2615 2616 err_unmap_io_base: 2617 pci_iounmap(pdev, hdev->hw.hw.io_base); 2618 err_clr_master: 2619 pci_clear_master(pdev); 2620 pci_release_regions(pdev); 2621 err_disable_device: 2622 pci_disable_device(pdev); 2623 2624 return ret; 2625 } 2626 2627 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2628 { 2629 struct pci_dev *pdev = hdev->pdev; 2630 2631 if (hdev->hw.hw.mem_base) 2632 devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base); 2633 2634 pci_iounmap(pdev, hdev->hw.hw.io_base); 2635 pci_clear_master(pdev); 2636 pci_release_regions(pdev); 2637 pci_disable_device(pdev); 2638 } 2639 2640 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 2641 { 2642 struct hclgevf_query_res_cmd *req; 2643 struct hclge_desc desc; 2644 int ret; 2645 2646 hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RSRC, true); 2647 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2648 if (ret) { 2649 dev_err(&hdev->pdev->dev, 2650 "query vf resource failed, ret = %d.\n", ret); 2651 return ret; 2652 } 2653 2654 req = (struct hclgevf_query_res_cmd *)desc.data; 2655 2656 if (hnae3_dev_roce_supported(hdev)) { 2657 hdev->roce_base_msix_offset = 2658 hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee), 2659 HCLGEVF_MSIX_OFT_ROCEE_M, 2660 HCLGEVF_MSIX_OFT_ROCEE_S); 2661 hdev->num_roce_msix = 2662 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 2663 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2664 2665 /* nic's msix numbers is always equals to the roce's. */ 2666 hdev->num_nic_msix = hdev->num_roce_msix; 2667 2668 /* VF should have NIC vectors and Roce vectors, NIC vectors 2669 * are queued before Roce vectors. The offset is fixed to 64. 2670 */ 2671 hdev->num_msi = hdev->num_roce_msix + 2672 hdev->roce_base_msix_offset; 2673 } else { 2674 hdev->num_msi = 2675 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 2676 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2677 2678 hdev->num_nic_msix = hdev->num_msi; 2679 } 2680 2681 if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) { 2682 dev_err(&hdev->pdev->dev, 2683 "Just %u msi resources, not enough for vf(min:2).\n", 2684 hdev->num_nic_msix); 2685 return -EINVAL; 2686 } 2687 2688 return 0; 2689 } 2690 2691 static void hclgevf_set_default_dev_specs(struct hclgevf_dev *hdev) 2692 { 2693 #define HCLGEVF_MAX_NON_TSO_BD_NUM 8U 2694 2695 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2696 2697 ae_dev->dev_specs.max_non_tso_bd_num = 2698 HCLGEVF_MAX_NON_TSO_BD_NUM; 2699 ae_dev->dev_specs.rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 2700 ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 2701 ae_dev->dev_specs.max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 2702 ae_dev->dev_specs.max_frm_size = HCLGEVF_MAC_MAX_FRAME; 2703 } 2704 2705 static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev, 2706 struct hclge_desc *desc) 2707 { 2708 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2709 struct hclgevf_dev_specs_0_cmd *req0; 2710 struct hclgevf_dev_specs_1_cmd *req1; 2711 2712 req0 = (struct hclgevf_dev_specs_0_cmd *)desc[0].data; 2713 req1 = (struct hclgevf_dev_specs_1_cmd *)desc[1].data; 2714 2715 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 2716 ae_dev->dev_specs.rss_ind_tbl_size = 2717 le16_to_cpu(req0->rss_ind_tbl_size); 2718 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 2719 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 2720 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 2721 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 2722 } 2723 2724 static void hclgevf_check_dev_specs(struct hclgevf_dev *hdev) 2725 { 2726 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 2727 2728 if (!dev_specs->max_non_tso_bd_num) 2729 dev_specs->max_non_tso_bd_num = HCLGEVF_MAX_NON_TSO_BD_NUM; 2730 if (!dev_specs->rss_ind_tbl_size) 2731 dev_specs->rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 2732 if (!dev_specs->rss_key_size) 2733 dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 2734 if (!dev_specs->max_int_gl) 2735 dev_specs->max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 2736 if (!dev_specs->max_frm_size) 2737 dev_specs->max_frm_size = HCLGEVF_MAC_MAX_FRAME; 2738 } 2739 2740 static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev) 2741 { 2742 struct hclge_desc desc[HCLGEVF_QUERY_DEV_SPECS_BD_NUM]; 2743 int ret; 2744 int i; 2745 2746 /* set default specifications as devices lower than version V3 do not 2747 * support querying specifications from firmware. 2748 */ 2749 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 2750 hclgevf_set_default_dev_specs(hdev); 2751 return 0; 2752 } 2753 2754 for (i = 0; i < HCLGEVF_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 2755 hclgevf_cmd_setup_basic_desc(&desc[i], 2756 HCLGE_OPC_QUERY_DEV_SPECS, true); 2757 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2758 } 2759 hclgevf_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true); 2760 2761 ret = hclgevf_cmd_send(&hdev->hw, desc, HCLGEVF_QUERY_DEV_SPECS_BD_NUM); 2762 if (ret) 2763 return ret; 2764 2765 hclgevf_parse_dev_specs(hdev, desc); 2766 hclgevf_check_dev_specs(hdev); 2767 2768 return 0; 2769 } 2770 2771 static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2772 { 2773 struct pci_dev *pdev = hdev->pdev; 2774 int ret = 0; 2775 2776 if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2777 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2778 hclgevf_misc_irq_uninit(hdev); 2779 hclgevf_uninit_msi(hdev); 2780 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2781 } 2782 2783 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2784 pci_set_master(pdev); 2785 ret = hclgevf_init_msi(hdev); 2786 if (ret) { 2787 dev_err(&pdev->dev, 2788 "failed(%d) to init MSI/MSI-X\n", ret); 2789 return ret; 2790 } 2791 2792 ret = hclgevf_misc_irq_init(hdev); 2793 if (ret) { 2794 hclgevf_uninit_msi(hdev); 2795 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2796 ret); 2797 return ret; 2798 } 2799 2800 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2801 } 2802 2803 return ret; 2804 } 2805 2806 static int hclgevf_clear_vport_list(struct hclgevf_dev *hdev) 2807 { 2808 struct hclge_vf_to_pf_msg send_msg; 2809 2810 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_HANDLE_VF_TBL, 2811 HCLGE_MBX_VPORT_LIST_CLEAR); 2812 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2813 } 2814 2815 static void hclgevf_init_rxd_adv_layout(struct hclgevf_dev *hdev) 2816 { 2817 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 2818 hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 1); 2819 } 2820 2821 static void hclgevf_uninit_rxd_adv_layout(struct hclgevf_dev *hdev) 2822 { 2823 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 2824 hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 0); 2825 } 2826 2827 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2828 { 2829 struct pci_dev *pdev = hdev->pdev; 2830 int ret; 2831 2832 ret = hclgevf_pci_reset(hdev); 2833 if (ret) { 2834 dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2835 return ret; 2836 } 2837 2838 hclgevf_arq_init(hdev); 2839 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, 2840 &hdev->fw_version, false, 2841 hdev->reset_pending); 2842 if (ret) { 2843 dev_err(&pdev->dev, "cmd failed %d\n", ret); 2844 return ret; 2845 } 2846 2847 ret = hclgevf_rss_init_hw(hdev); 2848 if (ret) { 2849 dev_err(&hdev->pdev->dev, 2850 "failed(%d) to initialize RSS\n", ret); 2851 return ret; 2852 } 2853 2854 ret = hclgevf_config_gro(hdev); 2855 if (ret) 2856 return ret; 2857 2858 ret = hclgevf_init_vlan_config(hdev); 2859 if (ret) { 2860 dev_err(&hdev->pdev->dev, 2861 "failed(%d) to initialize VLAN config\n", ret); 2862 return ret; 2863 } 2864 2865 /* get current port based vlan state from PF */ 2866 ret = hclgevf_get_port_base_vlan_filter_state(hdev); 2867 if (ret) 2868 return ret; 2869 2870 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 2871 2872 hclgevf_init_rxd_adv_layout(hdev); 2873 2874 dev_info(&hdev->pdev->dev, "Reset done\n"); 2875 2876 return 0; 2877 } 2878 2879 static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 2880 { 2881 struct pci_dev *pdev = hdev->pdev; 2882 int ret; 2883 2884 ret = hclgevf_pci_init(hdev); 2885 if (ret) 2886 return ret; 2887 2888 ret = hclgevf_devlink_init(hdev); 2889 if (ret) 2890 goto err_devlink_init; 2891 2892 ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw); 2893 if (ret) 2894 goto err_cmd_queue_init; 2895 2896 hclgevf_arq_init(hdev); 2897 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, 2898 &hdev->fw_version, false, 2899 hdev->reset_pending); 2900 if (ret) 2901 goto err_cmd_init; 2902 2903 /* Get vf resource */ 2904 ret = hclgevf_query_vf_resource(hdev); 2905 if (ret) 2906 goto err_cmd_init; 2907 2908 ret = hclgevf_query_dev_specs(hdev); 2909 if (ret) { 2910 dev_err(&pdev->dev, 2911 "failed to query dev specifications, ret = %d\n", ret); 2912 goto err_cmd_init; 2913 } 2914 2915 ret = hclgevf_init_msi(hdev); 2916 if (ret) { 2917 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 2918 goto err_cmd_init; 2919 } 2920 2921 hclgevf_state_init(hdev); 2922 hdev->reset_level = HNAE3_VF_FUNC_RESET; 2923 hdev->reset_type = HNAE3_NONE_RESET; 2924 2925 ret = hclgevf_misc_irq_init(hdev); 2926 if (ret) 2927 goto err_misc_irq_init; 2928 2929 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2930 2931 ret = hclgevf_configure(hdev); 2932 if (ret) { 2933 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2934 goto err_config; 2935 } 2936 2937 ret = hclgevf_alloc_tqps(hdev); 2938 if (ret) { 2939 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2940 goto err_config; 2941 } 2942 2943 ret = hclgevf_set_handle_info(hdev); 2944 if (ret) 2945 goto err_config; 2946 2947 ret = hclgevf_config_gro(hdev); 2948 if (ret) 2949 goto err_config; 2950 2951 /* Initialize RSS for this VF */ 2952 ret = hclge_comm_rss_init_cfg(&hdev->nic, hdev->ae_dev, 2953 &hdev->rss_cfg); 2954 if (ret) { 2955 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 2956 goto err_config; 2957 } 2958 2959 ret = hclgevf_rss_init_hw(hdev); 2960 if (ret) { 2961 dev_err(&hdev->pdev->dev, 2962 "failed(%d) to initialize RSS\n", ret); 2963 goto err_config; 2964 } 2965 2966 /* ensure vf tbl list as empty before init*/ 2967 ret = hclgevf_clear_vport_list(hdev); 2968 if (ret) { 2969 dev_err(&pdev->dev, 2970 "failed to clear tbl list configuration, ret = %d.\n", 2971 ret); 2972 goto err_config; 2973 } 2974 2975 ret = hclgevf_init_vlan_config(hdev); 2976 if (ret) { 2977 dev_err(&hdev->pdev->dev, 2978 "failed(%d) to initialize VLAN config\n", ret); 2979 goto err_config; 2980 } 2981 2982 hclgevf_init_rxd_adv_layout(hdev); 2983 2984 set_bit(HCLGEVF_STATE_SERVICE_INITED, &hdev->state); 2985 2986 hdev->last_reset_time = jiffies; 2987 dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 2988 HCLGEVF_DRIVER_NAME); 2989 2990 hclgevf_task_schedule(hdev, round_jiffies_relative(HZ)); 2991 2992 return 0; 2993 2994 err_config: 2995 hclgevf_misc_irq_uninit(hdev); 2996 err_misc_irq_init: 2997 hclgevf_state_uninit(hdev); 2998 hclgevf_uninit_msi(hdev); 2999 err_cmd_init: 3000 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 3001 err_cmd_queue_init: 3002 hclgevf_devlink_uninit(hdev); 3003 err_devlink_init: 3004 hclgevf_pci_uninit(hdev); 3005 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3006 return ret; 3007 } 3008 3009 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 3010 { 3011 struct hclge_vf_to_pf_msg send_msg; 3012 3013 hclgevf_state_uninit(hdev); 3014 hclgevf_uninit_rxd_adv_layout(hdev); 3015 3016 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_VF_UNINIT, 0); 3017 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3018 3019 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3020 hclgevf_misc_irq_uninit(hdev); 3021 hclgevf_uninit_msi(hdev); 3022 } 3023 3024 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 3025 hclgevf_devlink_uninit(hdev); 3026 hclgevf_pci_uninit(hdev); 3027 hclgevf_uninit_mac_list(hdev); 3028 } 3029 3030 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 3031 { 3032 struct pci_dev *pdev = ae_dev->pdev; 3033 int ret; 3034 3035 ret = hclgevf_alloc_hdev(ae_dev); 3036 if (ret) { 3037 dev_err(&pdev->dev, "hclge device allocation failed\n"); 3038 return ret; 3039 } 3040 3041 ret = hclgevf_init_hdev(ae_dev->priv); 3042 if (ret) { 3043 dev_err(&pdev->dev, "hclge device initialization failed\n"); 3044 return ret; 3045 } 3046 3047 return 0; 3048 } 3049 3050 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 3051 { 3052 struct hclgevf_dev *hdev = ae_dev->priv; 3053 3054 hclgevf_uninit_hdev(hdev); 3055 ae_dev->priv = NULL; 3056 } 3057 3058 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 3059 { 3060 struct hnae3_handle *nic = &hdev->nic; 3061 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 3062 3063 return min_t(u32, hdev->rss_size_max, 3064 hdev->num_tqps / kinfo->tc_info.num_tc); 3065 } 3066 3067 /** 3068 * hclgevf_get_channels - Get the current channels enabled and max supported. 3069 * @handle: hardware information for network interface 3070 * @ch: ethtool channels structure 3071 * 3072 * We don't support separate tx and rx queues as channels. The other count 3073 * represents how many queues are being used for control. max_combined counts 3074 * how many queue pairs we can support. They may not be mapped 1 to 1 with 3075 * q_vectors since we support a lot more queue pairs than q_vectors. 3076 **/ 3077 static void hclgevf_get_channels(struct hnae3_handle *handle, 3078 struct ethtool_channels *ch) 3079 { 3080 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3081 3082 ch->max_combined = hclgevf_get_max_channels(hdev); 3083 ch->other_count = 0; 3084 ch->max_other = 0; 3085 ch->combined_count = handle->kinfo.rss_size; 3086 } 3087 3088 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 3089 u16 *alloc_tqps, u16 *max_rss_size) 3090 { 3091 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3092 3093 *alloc_tqps = hdev->num_tqps; 3094 *max_rss_size = hdev->rss_size_max; 3095 } 3096 3097 static void hclgevf_update_rss_size(struct hnae3_handle *handle, 3098 u32 new_tqps_num) 3099 { 3100 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3101 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3102 u16 max_rss_size; 3103 3104 kinfo->req_rss_size = new_tqps_num; 3105 3106 max_rss_size = min_t(u16, hdev->rss_size_max, 3107 hdev->num_tqps / kinfo->tc_info.num_tc); 3108 3109 /* Use the user's configuration when it is not larger than 3110 * max_rss_size, otherwise, use the maximum specification value. 3111 */ 3112 if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 3113 kinfo->req_rss_size <= max_rss_size) 3114 kinfo->rss_size = kinfo->req_rss_size; 3115 else if (kinfo->rss_size > max_rss_size || 3116 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) 3117 kinfo->rss_size = max_rss_size; 3118 3119 kinfo->num_tqps = kinfo->tc_info.num_tc * kinfo->rss_size; 3120 } 3121 3122 static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 3123 bool rxfh_configured) 3124 { 3125 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3126 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3127 u16 tc_offset[HCLGE_COMM_MAX_TC_NUM]; 3128 u16 tc_valid[HCLGE_COMM_MAX_TC_NUM]; 3129 u16 tc_size[HCLGE_COMM_MAX_TC_NUM]; 3130 u16 cur_rss_size = kinfo->rss_size; 3131 u16 cur_tqps = kinfo->num_tqps; 3132 u32 *rss_indir; 3133 unsigned int i; 3134 int ret; 3135 3136 hclgevf_update_rss_size(handle, new_tqps_num); 3137 3138 hclge_comm_get_rss_tc_info(cur_rss_size, hdev->hw_tc_map, 3139 tc_offset, tc_valid, tc_size); 3140 ret = hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, 3141 tc_valid, tc_size); 3142 if (ret) 3143 return ret; 3144 3145 /* RSS indirection table has been configured by user */ 3146 if (rxfh_configured) 3147 goto out; 3148 3149 /* Reinitializes the rss indirect table according to the new RSS size */ 3150 rss_indir = kcalloc(hdev->ae_dev->dev_specs.rss_ind_tbl_size, 3151 sizeof(u32), GFP_KERNEL); 3152 if (!rss_indir) 3153 return -ENOMEM; 3154 3155 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 3156 rss_indir[i] = i % kinfo->rss_size; 3157 3158 hdev->rss_cfg.rss_size = kinfo->rss_size; 3159 3160 ret = hclgevf_set_rss(handle, rss_indir, NULL, 0); 3161 if (ret) 3162 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 3163 ret); 3164 3165 kfree(rss_indir); 3166 3167 out: 3168 if (!ret) 3169 dev_info(&hdev->pdev->dev, 3170 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 3171 cur_rss_size, kinfo->rss_size, 3172 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 3173 3174 return ret; 3175 } 3176 3177 static int hclgevf_get_status(struct hnae3_handle *handle) 3178 { 3179 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3180 3181 return hdev->hw.mac.link; 3182 } 3183 3184 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 3185 u8 *auto_neg, u32 *speed, 3186 u8 *duplex) 3187 { 3188 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3189 3190 if (speed) 3191 *speed = hdev->hw.mac.speed; 3192 if (duplex) 3193 *duplex = hdev->hw.mac.duplex; 3194 if (auto_neg) 3195 *auto_neg = AUTONEG_DISABLE; 3196 } 3197 3198 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 3199 u8 duplex) 3200 { 3201 hdev->hw.mac.speed = speed; 3202 hdev->hw.mac.duplex = duplex; 3203 } 3204 3205 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 3206 { 3207 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3208 bool gro_en_old = hdev->gro_en; 3209 int ret; 3210 3211 hdev->gro_en = enable; 3212 ret = hclgevf_config_gro(hdev); 3213 if (ret) 3214 hdev->gro_en = gro_en_old; 3215 3216 return ret; 3217 } 3218 3219 static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 3220 u8 *module_type) 3221 { 3222 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3223 3224 if (media_type) 3225 *media_type = hdev->hw.mac.media_type; 3226 3227 if (module_type) 3228 *module_type = hdev->hw.mac.module_type; 3229 } 3230 3231 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 3232 { 3233 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3234 3235 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 3236 } 3237 3238 static bool hclgevf_get_cmdq_stat(struct hnae3_handle *handle) 3239 { 3240 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3241 3242 return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3243 } 3244 3245 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 3246 { 3247 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3248 3249 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 3250 } 3251 3252 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 3253 { 3254 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3255 3256 return hdev->rst_stats.hw_rst_done_cnt; 3257 } 3258 3259 static void hclgevf_get_link_mode(struct hnae3_handle *handle, 3260 unsigned long *supported, 3261 unsigned long *advertising) 3262 { 3263 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3264 3265 *supported = hdev->hw.mac.supported; 3266 *advertising = hdev->hw.mac.advertising; 3267 } 3268 3269 #define MAX_SEPARATE_NUM 4 3270 #define SEPARATOR_VALUE 0xFDFCFBFA 3271 #define REG_NUM_PER_LINE 4 3272 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 3273 3274 static int hclgevf_get_regs_len(struct hnae3_handle *handle) 3275 { 3276 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 3277 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3278 3279 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 3280 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 3281 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 3282 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 3283 3284 return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 3285 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 3286 } 3287 3288 static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 3289 void *data) 3290 { 3291 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3292 int i, j, reg_um, separator_num; 3293 u32 *reg = data; 3294 3295 *version = hdev->fw_version; 3296 3297 /* fetching per-VF registers values from VF PCIe register space */ 3298 reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 3299 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3300 for (i = 0; i < reg_um; i++) 3301 *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 3302 for (i = 0; i < separator_num; i++) 3303 *reg++ = SEPARATOR_VALUE; 3304 3305 reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 3306 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3307 for (i = 0; i < reg_um; i++) 3308 *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 3309 for (i = 0; i < separator_num; i++) 3310 *reg++ = SEPARATOR_VALUE; 3311 3312 reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 3313 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3314 for (j = 0; j < hdev->num_tqps; j++) { 3315 for (i = 0; i < reg_um; i++) 3316 *reg++ = hclgevf_read_dev(&hdev->hw, 3317 ring_reg_addr_list[i] + 3318 0x200 * j); 3319 for (i = 0; i < separator_num; i++) 3320 *reg++ = SEPARATOR_VALUE; 3321 } 3322 3323 reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 3324 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3325 for (j = 0; j < hdev->num_msi_used - 1; j++) { 3326 for (i = 0; i < reg_um; i++) 3327 *reg++ = hclgevf_read_dev(&hdev->hw, 3328 tqp_intr_reg_addr_list[i] + 3329 4 * j); 3330 for (i = 0; i < separator_num; i++) 3331 *reg++ = SEPARATOR_VALUE; 3332 } 3333 } 3334 3335 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 3336 u8 *port_base_vlan_info, u8 data_size) 3337 { 3338 struct hnae3_handle *nic = &hdev->nic; 3339 struct hclge_vf_to_pf_msg send_msg; 3340 int ret; 3341 3342 rtnl_lock(); 3343 3344 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 3345 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) { 3346 dev_warn(&hdev->pdev->dev, 3347 "is resetting when updating port based vlan info\n"); 3348 rtnl_unlock(); 3349 return; 3350 } 3351 3352 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 3353 if (ret) { 3354 rtnl_unlock(); 3355 return; 3356 } 3357 3358 /* send msg to PF and wait update port based vlan info */ 3359 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 3360 HCLGE_MBX_PORT_BASE_VLAN_CFG); 3361 memcpy(send_msg.data, port_base_vlan_info, data_size); 3362 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3363 if (!ret) { 3364 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 3365 nic->port_base_vlan_state = state; 3366 else 3367 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 3368 } 3369 3370 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 3371 rtnl_unlock(); 3372 } 3373 3374 static const struct hnae3_ae_ops hclgevf_ops = { 3375 .init_ae_dev = hclgevf_init_ae_dev, 3376 .uninit_ae_dev = hclgevf_uninit_ae_dev, 3377 .reset_prepare = hclgevf_reset_prepare_general, 3378 .reset_done = hclgevf_reset_done, 3379 .init_client_instance = hclgevf_init_client_instance, 3380 .uninit_client_instance = hclgevf_uninit_client_instance, 3381 .start = hclgevf_ae_start, 3382 .stop = hclgevf_ae_stop, 3383 .client_start = hclgevf_client_start, 3384 .client_stop = hclgevf_client_stop, 3385 .map_ring_to_vector = hclgevf_map_ring_to_vector, 3386 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 3387 .get_vector = hclgevf_get_vector, 3388 .put_vector = hclgevf_put_vector, 3389 .reset_queue = hclgevf_reset_tqp, 3390 .get_mac_addr = hclgevf_get_mac_addr, 3391 .set_mac_addr = hclgevf_set_mac_addr, 3392 .add_uc_addr = hclgevf_add_uc_addr, 3393 .rm_uc_addr = hclgevf_rm_uc_addr, 3394 .add_mc_addr = hclgevf_add_mc_addr, 3395 .rm_mc_addr = hclgevf_rm_mc_addr, 3396 .get_stats = hclgevf_get_stats, 3397 .update_stats = hclgevf_update_stats, 3398 .get_strings = hclgevf_get_strings, 3399 .get_sset_count = hclgevf_get_sset_count, 3400 .get_rss_key_size = hclge_comm_get_rss_key_size, 3401 .get_rss = hclgevf_get_rss, 3402 .set_rss = hclgevf_set_rss, 3403 .get_rss_tuple = hclgevf_get_rss_tuple, 3404 .set_rss_tuple = hclgevf_set_rss_tuple, 3405 .get_tc_size = hclgevf_get_tc_size, 3406 .get_fw_version = hclgevf_get_fw_version, 3407 .set_vlan_filter = hclgevf_set_vlan_filter, 3408 .enable_vlan_filter = hclgevf_enable_vlan_filter, 3409 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 3410 .reset_event = hclgevf_reset_event, 3411 .set_default_reset_request = hclgevf_set_def_reset_request, 3412 .set_channels = hclgevf_set_channels, 3413 .get_channels = hclgevf_get_channels, 3414 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 3415 .get_regs_len = hclgevf_get_regs_len, 3416 .get_regs = hclgevf_get_regs, 3417 .get_status = hclgevf_get_status, 3418 .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3419 .get_media_type = hclgevf_get_media_type, 3420 .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 3421 .ae_dev_resetting = hclgevf_ae_dev_resetting, 3422 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 3423 .set_gro_en = hclgevf_gro_en, 3424 .set_mtu = hclgevf_set_mtu, 3425 .get_global_queue_id = hclgevf_get_qid_global, 3426 .set_timer_task = hclgevf_set_timer_task, 3427 .get_link_mode = hclgevf_get_link_mode, 3428 .set_promisc_mode = hclgevf_set_promisc_mode, 3429 .request_update_promisc_mode = hclgevf_request_update_promisc_mode, 3430 .get_cmdq_stat = hclgevf_get_cmdq_stat, 3431 }; 3432 3433 static struct hnae3_ae_algo ae_algovf = { 3434 .ops = &hclgevf_ops, 3435 .pdev_id_table = ae_algovf_pci_tbl, 3436 }; 3437 3438 static int hclgevf_init(void) 3439 { 3440 pr_info("%s is initializing\n", HCLGEVF_NAME); 3441 3442 hclgevf_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGEVF_NAME); 3443 if (!hclgevf_wq) { 3444 pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME); 3445 return -ENOMEM; 3446 } 3447 3448 hnae3_register_ae_algo(&ae_algovf); 3449 3450 return 0; 3451 } 3452 3453 static void hclgevf_exit(void) 3454 { 3455 hnae3_unregister_ae_algo(&ae_algovf); 3456 destroy_workqueue(hclgevf_wq); 3457 } 3458 module_init(hclgevf_init); 3459 module_exit(hclgevf_exit); 3460 3461 MODULE_LICENSE("GPL"); 3462 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3463 MODULE_DESCRIPTION("HCLGEVF Driver"); 3464 MODULE_VERSION(HCLGEVF_MOD_VERSION); 3465