1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include <linux/iopoll.h> 6 #include <net/rtnetlink.h> 7 #include "hclgevf_cmd.h" 8 #include "hclgevf_main.h" 9 #include "hclge_mbx.h" 10 #include "hnae3.h" 11 12 #define HCLGEVF_NAME "hclgevf" 13 14 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 15 static struct hnae3_ae_algo ae_algovf; 16 17 static const struct pci_device_id ae_algovf_pci_tbl[] = { 18 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 19 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 20 /* required last entry */ 21 {0, } 22 }; 23 24 static const u8 hclgevf_hash_key[] = { 25 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 26 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 27 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 28 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 29 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 30 }; 31 32 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 33 34 static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 35 HCLGEVF_CMDQ_TX_ADDR_H_REG, 36 HCLGEVF_CMDQ_TX_DEPTH_REG, 37 HCLGEVF_CMDQ_TX_TAIL_REG, 38 HCLGEVF_CMDQ_TX_HEAD_REG, 39 HCLGEVF_CMDQ_RX_ADDR_L_REG, 40 HCLGEVF_CMDQ_RX_ADDR_H_REG, 41 HCLGEVF_CMDQ_RX_DEPTH_REG, 42 HCLGEVF_CMDQ_RX_TAIL_REG, 43 HCLGEVF_CMDQ_RX_HEAD_REG, 44 HCLGEVF_VECTOR0_CMDQ_SRC_REG, 45 HCLGEVF_CMDQ_INTR_STS_REG, 46 HCLGEVF_CMDQ_INTR_EN_REG, 47 HCLGEVF_CMDQ_INTR_GEN_REG}; 48 49 static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 50 HCLGEVF_RST_ING, 51 HCLGEVF_GRO_EN_REG}; 52 53 static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 54 HCLGEVF_RING_RX_ADDR_H_REG, 55 HCLGEVF_RING_RX_BD_NUM_REG, 56 HCLGEVF_RING_RX_BD_LENGTH_REG, 57 HCLGEVF_RING_RX_MERGE_EN_REG, 58 HCLGEVF_RING_RX_TAIL_REG, 59 HCLGEVF_RING_RX_HEAD_REG, 60 HCLGEVF_RING_RX_FBD_NUM_REG, 61 HCLGEVF_RING_RX_OFFSET_REG, 62 HCLGEVF_RING_RX_FBD_OFFSET_REG, 63 HCLGEVF_RING_RX_STASH_REG, 64 HCLGEVF_RING_RX_BD_ERR_REG, 65 HCLGEVF_RING_TX_ADDR_L_REG, 66 HCLGEVF_RING_TX_ADDR_H_REG, 67 HCLGEVF_RING_TX_BD_NUM_REG, 68 HCLGEVF_RING_TX_PRIORITY_REG, 69 HCLGEVF_RING_TX_TC_REG, 70 HCLGEVF_RING_TX_MERGE_EN_REG, 71 HCLGEVF_RING_TX_TAIL_REG, 72 HCLGEVF_RING_TX_HEAD_REG, 73 HCLGEVF_RING_TX_FBD_NUM_REG, 74 HCLGEVF_RING_TX_OFFSET_REG, 75 HCLGEVF_RING_TX_EBD_NUM_REG, 76 HCLGEVF_RING_TX_EBD_OFFSET_REG, 77 HCLGEVF_RING_TX_BD_ERR_REG, 78 HCLGEVF_RING_EN_REG}; 79 80 static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 81 HCLGEVF_TQP_INTR_GL0_REG, 82 HCLGEVF_TQP_INTR_GL1_REG, 83 HCLGEVF_TQP_INTR_GL2_REG, 84 HCLGEVF_TQP_INTR_RL_REG}; 85 86 static inline struct hclgevf_dev *hclgevf_ae_get_hdev( 87 struct hnae3_handle *handle) 88 { 89 if (!handle->client) 90 return container_of(handle, struct hclgevf_dev, nic); 91 else if (handle->client->type == HNAE3_CLIENT_ROCE) 92 return container_of(handle, struct hclgevf_dev, roce); 93 else 94 return container_of(handle, struct hclgevf_dev, nic); 95 } 96 97 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 98 { 99 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 100 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 101 struct hclgevf_desc desc; 102 struct hclgevf_tqp *tqp; 103 int status; 104 int i; 105 106 for (i = 0; i < kinfo->num_tqps; i++) { 107 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 108 hclgevf_cmd_setup_basic_desc(&desc, 109 HCLGEVF_OPC_QUERY_RX_STATUS, 110 true); 111 112 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 113 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 114 if (status) { 115 dev_err(&hdev->pdev->dev, 116 "Query tqp stat fail, status = %d,queue = %d\n", 117 status, i); 118 return status; 119 } 120 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 121 le32_to_cpu(desc.data[1]); 122 123 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 124 true); 125 126 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 127 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 128 if (status) { 129 dev_err(&hdev->pdev->dev, 130 "Query tqp stat fail, status = %d,queue = %d\n", 131 status, i); 132 return status; 133 } 134 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 135 le32_to_cpu(desc.data[1]); 136 } 137 138 return 0; 139 } 140 141 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 142 { 143 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 144 struct hclgevf_tqp *tqp; 145 u64 *buff = data; 146 int i; 147 148 for (i = 0; i < kinfo->num_tqps; i++) { 149 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 150 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 151 } 152 for (i = 0; i < kinfo->num_tqps; i++) { 153 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 154 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 155 } 156 157 return buff; 158 } 159 160 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 161 { 162 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 163 164 return kinfo->num_tqps * 2; 165 } 166 167 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 168 { 169 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 170 u8 *buff = data; 171 int i = 0; 172 173 for (i = 0; i < kinfo->num_tqps; i++) { 174 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 175 struct hclgevf_tqp, q); 176 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 177 tqp->index); 178 buff += ETH_GSTRING_LEN; 179 } 180 181 for (i = 0; i < kinfo->num_tqps; i++) { 182 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 183 struct hclgevf_tqp, q); 184 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 185 tqp->index); 186 buff += ETH_GSTRING_LEN; 187 } 188 189 return buff; 190 } 191 192 static void hclgevf_update_stats(struct hnae3_handle *handle, 193 struct net_device_stats *net_stats) 194 { 195 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 196 int status; 197 198 status = hclgevf_tqps_update_stats(handle); 199 if (status) 200 dev_err(&hdev->pdev->dev, 201 "VF update of TQPS stats fail, status = %d.\n", 202 status); 203 } 204 205 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 206 { 207 if (strset == ETH_SS_TEST) 208 return -EOPNOTSUPP; 209 else if (strset == ETH_SS_STATS) 210 return hclgevf_tqps_get_sset_count(handle, strset); 211 212 return 0; 213 } 214 215 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 216 u8 *data) 217 { 218 u8 *p = (char *)data; 219 220 if (strset == ETH_SS_STATS) 221 p = hclgevf_tqps_get_strings(handle, p); 222 } 223 224 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 225 { 226 hclgevf_tqps_get_stats(handle, data); 227 } 228 229 static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 230 { 231 u8 resp_msg; 232 int status; 233 234 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 235 true, &resp_msg, sizeof(u8)); 236 if (status) { 237 dev_err(&hdev->pdev->dev, 238 "VF request to get TC info from PF failed %d", 239 status); 240 return status; 241 } 242 243 hdev->hw_tc_map = resp_msg; 244 245 return 0; 246 } 247 248 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 249 { 250 struct hnae3_handle *nic = &hdev->nic; 251 u8 resp_msg; 252 int ret; 253 254 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 255 HCLGE_MBX_GET_PORT_BASE_VLAN_STATE, 256 NULL, 0, true, &resp_msg, sizeof(u8)); 257 if (ret) { 258 dev_err(&hdev->pdev->dev, 259 "VF request to get port based vlan state failed %d", 260 ret); 261 return ret; 262 } 263 264 nic->port_base_vlan_state = resp_msg; 265 266 return 0; 267 } 268 269 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 270 { 271 #define HCLGEVF_TQPS_RSS_INFO_LEN 6 272 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 273 int status; 274 275 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 276 true, resp_msg, 277 HCLGEVF_TQPS_RSS_INFO_LEN); 278 if (status) { 279 dev_err(&hdev->pdev->dev, 280 "VF request to get tqp info from PF failed %d", 281 status); 282 return status; 283 } 284 285 memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 286 memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 287 memcpy(&hdev->rx_buf_len, &resp_msg[4], sizeof(u16)); 288 289 return 0; 290 } 291 292 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 293 { 294 #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 295 u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 296 int ret; 297 298 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QDEPTH, 0, NULL, 0, 299 true, resp_msg, 300 HCLGEVF_TQPS_DEPTH_INFO_LEN); 301 if (ret) { 302 dev_err(&hdev->pdev->dev, 303 "VF request to get tqp depth info from PF failed %d", 304 ret); 305 return ret; 306 } 307 308 memcpy(&hdev->num_tx_desc, &resp_msg[0], sizeof(u16)); 309 memcpy(&hdev->num_rx_desc, &resp_msg[2], sizeof(u16)); 310 311 return 0; 312 } 313 314 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 315 { 316 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 317 u8 msg_data[2], resp_data[2]; 318 u16 qid_in_pf = 0; 319 int ret; 320 321 memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 322 323 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data, 324 2, true, resp_data, 2); 325 if (!ret) 326 qid_in_pf = *(u16 *)resp_data; 327 328 return qid_in_pf; 329 } 330 331 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 332 { 333 u8 resp_msg[2]; 334 int ret; 335 336 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_MEDIA_TYPE, 0, NULL, 0, 337 true, resp_msg, sizeof(resp_msg)); 338 if (ret) { 339 dev_err(&hdev->pdev->dev, 340 "VF request to get the pf port media type failed %d", 341 ret); 342 return ret; 343 } 344 345 hdev->hw.mac.media_type = resp_msg[0]; 346 hdev->hw.mac.module_type = resp_msg[1]; 347 348 return 0; 349 } 350 351 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 352 { 353 struct hclgevf_tqp *tqp; 354 int i; 355 356 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 357 sizeof(struct hclgevf_tqp), GFP_KERNEL); 358 if (!hdev->htqp) 359 return -ENOMEM; 360 361 tqp = hdev->htqp; 362 363 for (i = 0; i < hdev->num_tqps; i++) { 364 tqp->dev = &hdev->pdev->dev; 365 tqp->index = i; 366 367 tqp->q.ae_algo = &ae_algovf; 368 tqp->q.buf_size = hdev->rx_buf_len; 369 tqp->q.tx_desc_num = hdev->num_tx_desc; 370 tqp->q.rx_desc_num = hdev->num_rx_desc; 371 tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 372 i * HCLGEVF_TQP_REG_SIZE; 373 374 tqp++; 375 } 376 377 return 0; 378 } 379 380 static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 381 { 382 struct hnae3_handle *nic = &hdev->nic; 383 struct hnae3_knic_private_info *kinfo; 384 u16 new_tqps = hdev->num_tqps; 385 int i; 386 387 kinfo = &nic->kinfo; 388 kinfo->num_tc = 0; 389 kinfo->num_tx_desc = hdev->num_tx_desc; 390 kinfo->num_rx_desc = hdev->num_rx_desc; 391 kinfo->rx_buf_len = hdev->rx_buf_len; 392 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 393 if (hdev->hw_tc_map & BIT(i)) 394 kinfo->num_tc++; 395 396 kinfo->rss_size 397 = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 398 new_tqps = kinfo->rss_size * kinfo->num_tc; 399 kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 400 401 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 402 sizeof(struct hnae3_queue *), GFP_KERNEL); 403 if (!kinfo->tqp) 404 return -ENOMEM; 405 406 for (i = 0; i < kinfo->num_tqps; i++) { 407 hdev->htqp[i].q.handle = &hdev->nic; 408 hdev->htqp[i].q.tqp_index = i; 409 kinfo->tqp[i] = &hdev->htqp[i].q; 410 } 411 412 return 0; 413 } 414 415 static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 416 { 417 int status; 418 u8 resp_msg; 419 420 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 421 0, false, &resp_msg, sizeof(u8)); 422 if (status) 423 dev_err(&hdev->pdev->dev, 424 "VF failed to fetch link status(%d) from PF", status); 425 } 426 427 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 428 { 429 struct hnae3_handle *rhandle = &hdev->roce; 430 struct hnae3_handle *handle = &hdev->nic; 431 struct hnae3_client *rclient; 432 struct hnae3_client *client; 433 434 client = handle->client; 435 rclient = hdev->roce_client; 436 437 link_state = 438 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 439 440 if (link_state != hdev->hw.mac.link) { 441 client->ops->link_status_change(handle, !!link_state); 442 if (rclient && rclient->ops->link_status_change) 443 rclient->ops->link_status_change(rhandle, !!link_state); 444 hdev->hw.mac.link = link_state; 445 } 446 } 447 448 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 449 { 450 #define HCLGEVF_ADVERTISING 0 451 #define HCLGEVF_SUPPORTED 1 452 u8 send_msg; 453 u8 resp_msg; 454 455 send_msg = HCLGEVF_ADVERTISING; 456 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, &send_msg, 457 sizeof(u8), false, &resp_msg, sizeof(u8)); 458 send_msg = HCLGEVF_SUPPORTED; 459 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, &send_msg, 460 sizeof(u8), false, &resp_msg, sizeof(u8)); 461 } 462 463 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 464 { 465 struct hnae3_handle *nic = &hdev->nic; 466 int ret; 467 468 nic->ae_algo = &ae_algovf; 469 nic->pdev = hdev->pdev; 470 nic->numa_node_mask = hdev->numa_node_mask; 471 nic->flags |= HNAE3_SUPPORT_VF; 472 473 if (hdev->ae_dev->dev_type != HNAE3_DEV_KNIC) { 474 dev_err(&hdev->pdev->dev, "unsupported device type %d\n", 475 hdev->ae_dev->dev_type); 476 return -EINVAL; 477 } 478 479 ret = hclgevf_knic_setup(hdev); 480 if (ret) 481 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 482 ret); 483 return ret; 484 } 485 486 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 487 { 488 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 489 dev_warn(&hdev->pdev->dev, 490 "vector(vector_id %d) has been freed.\n", vector_id); 491 return; 492 } 493 494 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 495 hdev->num_msi_left += 1; 496 hdev->num_msi_used -= 1; 497 } 498 499 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 500 struct hnae3_vector_info *vector_info) 501 { 502 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 503 struct hnae3_vector_info *vector = vector_info; 504 int alloc = 0; 505 int i, j; 506 507 vector_num = min(hdev->num_msi_left, vector_num); 508 509 for (j = 0; j < vector_num; j++) { 510 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 511 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 512 vector->vector = pci_irq_vector(hdev->pdev, i); 513 vector->io_addr = hdev->hw.io_base + 514 HCLGEVF_VECTOR_REG_BASE + 515 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 516 hdev->vector_status[i] = 0; 517 hdev->vector_irq[i] = vector->vector; 518 519 vector++; 520 alloc++; 521 522 break; 523 } 524 } 525 } 526 hdev->num_msi_left -= alloc; 527 hdev->num_msi_used += alloc; 528 529 return alloc; 530 } 531 532 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 533 { 534 int i; 535 536 for (i = 0; i < hdev->num_msi; i++) 537 if (vector == hdev->vector_irq[i]) 538 return i; 539 540 return -EINVAL; 541 } 542 543 static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 544 const u8 hfunc, const u8 *key) 545 { 546 struct hclgevf_rss_config_cmd *req; 547 struct hclgevf_desc desc; 548 int key_offset; 549 int key_size; 550 int ret; 551 552 req = (struct hclgevf_rss_config_cmd *)desc.data; 553 554 for (key_offset = 0; key_offset < 3; key_offset++) { 555 hclgevf_cmd_setup_basic_desc(&desc, 556 HCLGEVF_OPC_RSS_GENERIC_CONFIG, 557 false); 558 559 req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 560 req->hash_config |= 561 (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 562 563 if (key_offset == 2) 564 key_size = 565 HCLGEVF_RSS_KEY_SIZE - HCLGEVF_RSS_HASH_KEY_NUM * 2; 566 else 567 key_size = HCLGEVF_RSS_HASH_KEY_NUM; 568 569 memcpy(req->hash_key, 570 key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 571 572 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 573 if (ret) { 574 dev_err(&hdev->pdev->dev, 575 "Configure RSS config fail, status = %d\n", 576 ret); 577 return ret; 578 } 579 } 580 581 return 0; 582 } 583 584 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 585 { 586 return HCLGEVF_RSS_KEY_SIZE; 587 } 588 589 static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 590 { 591 return HCLGEVF_RSS_IND_TBL_SIZE; 592 } 593 594 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 595 { 596 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 597 struct hclgevf_rss_indirection_table_cmd *req; 598 struct hclgevf_desc desc; 599 int status; 600 int i, j; 601 602 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 603 604 for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 605 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 606 false); 607 req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 608 req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 609 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 610 req->rss_result[j] = 611 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 612 613 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 614 if (status) { 615 dev_err(&hdev->pdev->dev, 616 "VF failed(=%d) to set RSS indirection table\n", 617 status); 618 return status; 619 } 620 } 621 622 return 0; 623 } 624 625 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 626 { 627 struct hclgevf_rss_tc_mode_cmd *req; 628 u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 629 u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 630 u16 tc_size[HCLGEVF_MAX_TC_NUM]; 631 struct hclgevf_desc desc; 632 u16 roundup_size; 633 int status; 634 int i; 635 636 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 637 638 roundup_size = roundup_pow_of_two(rss_size); 639 roundup_size = ilog2(roundup_size); 640 641 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 642 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 643 tc_size[i] = roundup_size; 644 tc_offset[i] = rss_size * i; 645 } 646 647 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 648 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 649 hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 650 (tc_valid[i] & 0x1)); 651 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 652 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 653 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 654 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 655 } 656 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 657 if (status) 658 dev_err(&hdev->pdev->dev, 659 "VF failed(=%d) to set rss tc mode\n", status); 660 661 return status; 662 } 663 664 /* for revision 0x20, vf shared the same rss config with pf */ 665 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 666 { 667 #define HCLGEVF_RSS_MBX_RESP_LEN 8 668 669 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 670 u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 671 u16 msg_num, hash_key_index; 672 u8 index; 673 int ret; 674 675 msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 676 HCLGEVF_RSS_MBX_RESP_LEN; 677 for (index = 0; index < msg_num; index++) { 678 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_RSS_KEY, 0, 679 &index, sizeof(index), 680 true, resp_msg, 681 HCLGEVF_RSS_MBX_RESP_LEN); 682 if (ret) { 683 dev_err(&hdev->pdev->dev, 684 "VF get rss hash key from PF failed, ret=%d", 685 ret); 686 return ret; 687 } 688 689 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 690 if (index == msg_num - 1) 691 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 692 &resp_msg[0], 693 HCLGEVF_RSS_KEY_SIZE - hash_key_index); 694 else 695 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 696 &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 697 } 698 699 return 0; 700 } 701 702 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 703 u8 *hfunc) 704 { 705 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 706 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 707 int i, ret; 708 709 if (handle->pdev->revision >= 0x21) { 710 /* Get hash algorithm */ 711 if (hfunc) { 712 switch (rss_cfg->hash_algo) { 713 case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 714 *hfunc = ETH_RSS_HASH_TOP; 715 break; 716 case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 717 *hfunc = ETH_RSS_HASH_XOR; 718 break; 719 default: 720 *hfunc = ETH_RSS_HASH_UNKNOWN; 721 break; 722 } 723 } 724 725 /* Get the RSS Key required by the user */ 726 if (key) 727 memcpy(key, rss_cfg->rss_hash_key, 728 HCLGEVF_RSS_KEY_SIZE); 729 } else { 730 if (hfunc) 731 *hfunc = ETH_RSS_HASH_TOP; 732 if (key) { 733 ret = hclgevf_get_rss_hash_key(hdev); 734 if (ret) 735 return ret; 736 memcpy(key, rss_cfg->rss_hash_key, 737 HCLGEVF_RSS_KEY_SIZE); 738 } 739 } 740 741 if (indir) 742 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 743 indir[i] = rss_cfg->rss_indirection_tbl[i]; 744 745 return 0; 746 } 747 748 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 749 const u8 *key, const u8 hfunc) 750 { 751 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 752 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 753 int ret, i; 754 755 if (handle->pdev->revision >= 0x21) { 756 /* Set the RSS Hash Key if specififed by the user */ 757 if (key) { 758 switch (hfunc) { 759 case ETH_RSS_HASH_TOP: 760 rss_cfg->hash_algo = 761 HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 762 break; 763 case ETH_RSS_HASH_XOR: 764 rss_cfg->hash_algo = 765 HCLGEVF_RSS_HASH_ALGO_SIMPLE; 766 break; 767 case ETH_RSS_HASH_NO_CHANGE: 768 break; 769 default: 770 return -EINVAL; 771 } 772 773 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 774 key); 775 if (ret) 776 return ret; 777 778 /* Update the shadow RSS key with user specified qids */ 779 memcpy(rss_cfg->rss_hash_key, key, 780 HCLGEVF_RSS_KEY_SIZE); 781 } 782 } 783 784 /* update the shadow RSS table with user specified qids */ 785 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 786 rss_cfg->rss_indirection_tbl[i] = indir[i]; 787 788 /* update the hardware */ 789 return hclgevf_set_rss_indir_table(hdev); 790 } 791 792 static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 793 { 794 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 795 796 if (nfc->data & RXH_L4_B_2_3) 797 hash_sets |= HCLGEVF_D_PORT_BIT; 798 else 799 hash_sets &= ~HCLGEVF_D_PORT_BIT; 800 801 if (nfc->data & RXH_IP_SRC) 802 hash_sets |= HCLGEVF_S_IP_BIT; 803 else 804 hash_sets &= ~HCLGEVF_S_IP_BIT; 805 806 if (nfc->data & RXH_IP_DST) 807 hash_sets |= HCLGEVF_D_IP_BIT; 808 else 809 hash_sets &= ~HCLGEVF_D_IP_BIT; 810 811 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 812 hash_sets |= HCLGEVF_V_TAG_BIT; 813 814 return hash_sets; 815 } 816 817 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 818 struct ethtool_rxnfc *nfc) 819 { 820 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 821 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 822 struct hclgevf_rss_input_tuple_cmd *req; 823 struct hclgevf_desc desc; 824 u8 tuple_sets; 825 int ret; 826 827 if (handle->pdev->revision == 0x20) 828 return -EOPNOTSUPP; 829 830 if (nfc->data & 831 ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 832 return -EINVAL; 833 834 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 835 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 836 837 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 838 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 839 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 840 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 841 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 842 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 843 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 844 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 845 846 tuple_sets = hclgevf_get_rss_hash_bits(nfc); 847 switch (nfc->flow_type) { 848 case TCP_V4_FLOW: 849 req->ipv4_tcp_en = tuple_sets; 850 break; 851 case TCP_V6_FLOW: 852 req->ipv6_tcp_en = tuple_sets; 853 break; 854 case UDP_V4_FLOW: 855 req->ipv4_udp_en = tuple_sets; 856 break; 857 case UDP_V6_FLOW: 858 req->ipv6_udp_en = tuple_sets; 859 break; 860 case SCTP_V4_FLOW: 861 req->ipv4_sctp_en = tuple_sets; 862 break; 863 case SCTP_V6_FLOW: 864 if ((nfc->data & RXH_L4_B_0_1) || 865 (nfc->data & RXH_L4_B_2_3)) 866 return -EINVAL; 867 868 req->ipv6_sctp_en = tuple_sets; 869 break; 870 case IPV4_FLOW: 871 req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 872 break; 873 case IPV6_FLOW: 874 req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 875 break; 876 default: 877 return -EINVAL; 878 } 879 880 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 881 if (ret) { 882 dev_err(&hdev->pdev->dev, 883 "Set rss tuple fail, status = %d\n", ret); 884 return ret; 885 } 886 887 rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 888 rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 889 rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 890 rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 891 rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 892 rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 893 rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 894 rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 895 return 0; 896 } 897 898 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 899 struct ethtool_rxnfc *nfc) 900 { 901 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 902 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 903 u8 tuple_sets; 904 905 if (handle->pdev->revision == 0x20) 906 return -EOPNOTSUPP; 907 908 nfc->data = 0; 909 910 switch (nfc->flow_type) { 911 case TCP_V4_FLOW: 912 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 913 break; 914 case UDP_V4_FLOW: 915 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 916 break; 917 case TCP_V6_FLOW: 918 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 919 break; 920 case UDP_V6_FLOW: 921 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 922 break; 923 case SCTP_V4_FLOW: 924 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 925 break; 926 case SCTP_V6_FLOW: 927 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 928 break; 929 case IPV4_FLOW: 930 case IPV6_FLOW: 931 tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 932 break; 933 default: 934 return -EINVAL; 935 } 936 937 if (!tuple_sets) 938 return 0; 939 940 if (tuple_sets & HCLGEVF_D_PORT_BIT) 941 nfc->data |= RXH_L4_B_2_3; 942 if (tuple_sets & HCLGEVF_S_PORT_BIT) 943 nfc->data |= RXH_L4_B_0_1; 944 if (tuple_sets & HCLGEVF_D_IP_BIT) 945 nfc->data |= RXH_IP_DST; 946 if (tuple_sets & HCLGEVF_S_IP_BIT) 947 nfc->data |= RXH_IP_SRC; 948 949 return 0; 950 } 951 952 static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 953 struct hclgevf_rss_cfg *rss_cfg) 954 { 955 struct hclgevf_rss_input_tuple_cmd *req; 956 struct hclgevf_desc desc; 957 int ret; 958 959 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 960 961 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 962 963 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 964 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 965 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 966 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 967 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 968 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 969 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 970 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 971 972 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 973 if (ret) 974 dev_err(&hdev->pdev->dev, 975 "Configure rss input fail, status = %d\n", ret); 976 return ret; 977 } 978 979 static int hclgevf_get_tc_size(struct hnae3_handle *handle) 980 { 981 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 982 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 983 984 return rss_cfg->rss_size; 985 } 986 987 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 988 int vector_id, 989 struct hnae3_ring_chain_node *ring_chain) 990 { 991 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 992 struct hnae3_ring_chain_node *node; 993 struct hclge_mbx_vf_to_pf_cmd *req; 994 struct hclgevf_desc desc; 995 int i = 0; 996 int status; 997 u8 type; 998 999 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1000 1001 for (node = ring_chain; node; node = node->next) { 1002 int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 1003 HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 1004 1005 if (i == 0) { 1006 hclgevf_cmd_setup_basic_desc(&desc, 1007 HCLGEVF_OPC_MBX_VF_TO_PF, 1008 false); 1009 type = en ? 1010 HCLGE_MBX_MAP_RING_TO_VECTOR : 1011 HCLGE_MBX_UNMAP_RING_TO_VECTOR; 1012 req->msg[0] = type; 1013 req->msg[1] = vector_id; 1014 } 1015 1016 req->msg[idx_offset] = 1017 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 1018 req->msg[idx_offset + 1] = node->tqp_index; 1019 req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 1020 HNAE3_RING_GL_IDX_M, 1021 HNAE3_RING_GL_IDX_S); 1022 1023 i++; 1024 if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 1025 HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 1026 HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 1027 !node->next) { 1028 req->msg[2] = i; 1029 1030 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1031 if (status) { 1032 dev_err(&hdev->pdev->dev, 1033 "Map TQP fail, status is %d.\n", 1034 status); 1035 return status; 1036 } 1037 i = 0; 1038 hclgevf_cmd_setup_basic_desc(&desc, 1039 HCLGEVF_OPC_MBX_VF_TO_PF, 1040 false); 1041 req->msg[0] = type; 1042 req->msg[1] = vector_id; 1043 } 1044 } 1045 1046 return 0; 1047 } 1048 1049 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1050 struct hnae3_ring_chain_node *ring_chain) 1051 { 1052 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1053 int vector_id; 1054 1055 vector_id = hclgevf_get_vector_index(hdev, vector); 1056 if (vector_id < 0) { 1057 dev_err(&handle->pdev->dev, 1058 "Get vector index fail. ret =%d\n", vector_id); 1059 return vector_id; 1060 } 1061 1062 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1063 } 1064 1065 static int hclgevf_unmap_ring_from_vector( 1066 struct hnae3_handle *handle, 1067 int vector, 1068 struct hnae3_ring_chain_node *ring_chain) 1069 { 1070 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1071 int ret, vector_id; 1072 1073 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1074 return 0; 1075 1076 vector_id = hclgevf_get_vector_index(hdev, vector); 1077 if (vector_id < 0) { 1078 dev_err(&handle->pdev->dev, 1079 "Get vector index fail. ret =%d\n", vector_id); 1080 return vector_id; 1081 } 1082 1083 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 1084 if (ret) 1085 dev_err(&handle->pdev->dev, 1086 "Unmap ring from vector fail. vector=%d, ret =%d\n", 1087 vector_id, 1088 ret); 1089 1090 return ret; 1091 } 1092 1093 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 1094 { 1095 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1096 int vector_id; 1097 1098 vector_id = hclgevf_get_vector_index(hdev, vector); 1099 if (vector_id < 0) { 1100 dev_err(&handle->pdev->dev, 1101 "hclgevf_put_vector get vector index fail. ret =%d\n", 1102 vector_id); 1103 return vector_id; 1104 } 1105 1106 hclgevf_free_vector(hdev, vector_id); 1107 1108 return 0; 1109 } 1110 1111 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1112 bool en_bc_pmc) 1113 { 1114 struct hclge_mbx_vf_to_pf_cmd *req; 1115 struct hclgevf_desc desc; 1116 int ret; 1117 1118 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1119 1120 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 1121 req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 1122 req->msg[1] = en_bc_pmc ? 1 : 0; 1123 1124 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1125 if (ret) 1126 dev_err(&hdev->pdev->dev, 1127 "Set promisc mode fail, status is %d.\n", ret); 1128 1129 return ret; 1130 } 1131 1132 static int hclgevf_set_promisc_mode(struct hclgevf_dev *hdev, bool en_bc_pmc) 1133 { 1134 return hclgevf_cmd_set_promisc_mode(hdev, en_bc_pmc); 1135 } 1136 1137 static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, int tqp_id, 1138 int stream_id, bool enable) 1139 { 1140 struct hclgevf_cfg_com_tqp_queue_cmd *req; 1141 struct hclgevf_desc desc; 1142 int status; 1143 1144 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1145 1146 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1147 false); 1148 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1149 req->stream_id = cpu_to_le16(stream_id); 1150 req->enable |= enable << HCLGEVF_TQP_ENABLE_B; 1151 1152 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1153 if (status) 1154 dev_err(&hdev->pdev->dev, 1155 "TQP enable fail, status =%d.\n", status); 1156 1157 return status; 1158 } 1159 1160 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1161 { 1162 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1163 struct hclgevf_tqp *tqp; 1164 int i; 1165 1166 for (i = 0; i < kinfo->num_tqps; i++) { 1167 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1168 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1169 } 1170 } 1171 1172 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1173 { 1174 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1175 1176 ether_addr_copy(p, hdev->hw.mac.mac_addr); 1177 } 1178 1179 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 1180 bool is_first) 1181 { 1182 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1183 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1184 u8 *new_mac_addr = (u8 *)p; 1185 u8 msg_data[ETH_ALEN * 2]; 1186 u16 subcode; 1187 int status; 1188 1189 ether_addr_copy(msg_data, new_mac_addr); 1190 ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 1191 1192 subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 1193 HCLGE_MBX_MAC_VLAN_UC_MODIFY; 1194 1195 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1196 subcode, msg_data, ETH_ALEN * 2, 1197 true, NULL, 0); 1198 if (!status) 1199 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1200 1201 return status; 1202 } 1203 1204 static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1205 const unsigned char *addr) 1206 { 1207 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1208 1209 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1210 HCLGE_MBX_MAC_VLAN_UC_ADD, 1211 addr, ETH_ALEN, false, NULL, 0); 1212 } 1213 1214 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1215 const unsigned char *addr) 1216 { 1217 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1218 1219 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1220 HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1221 addr, ETH_ALEN, false, NULL, 0); 1222 } 1223 1224 static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1225 const unsigned char *addr) 1226 { 1227 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1228 1229 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1230 HCLGE_MBX_MAC_VLAN_MC_ADD, 1231 addr, ETH_ALEN, false, NULL, 0); 1232 } 1233 1234 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1235 const unsigned char *addr) 1236 { 1237 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1238 1239 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1240 HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1241 addr, ETH_ALEN, false, NULL, 0); 1242 } 1243 1244 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1245 __be16 proto, u16 vlan_id, 1246 bool is_kill) 1247 { 1248 #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1249 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1250 u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1251 1252 if (vlan_id > 4095) 1253 return -EINVAL; 1254 1255 if (proto != htons(ETH_P_8021Q)) 1256 return -EPROTONOSUPPORT; 1257 1258 msg_data[0] = is_kill; 1259 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1260 memcpy(&msg_data[3], &proto, sizeof(proto)); 1261 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1262 HCLGE_MBX_VLAN_FILTER, msg_data, 1263 HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 1264 } 1265 1266 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1267 { 1268 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1269 u8 msg_data; 1270 1271 msg_data = enable ? 1 : 0; 1272 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1273 HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1274 1, false, NULL, 0); 1275 } 1276 1277 static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1278 { 1279 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1280 u8 msg_data[2]; 1281 int ret; 1282 1283 memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 1284 1285 /* disable vf queue before send queue reset msg to PF */ 1286 ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 1287 if (ret) 1288 return ret; 1289 1290 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 1291 2, true, NULL, 0); 1292 } 1293 1294 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1295 { 1296 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1297 1298 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu, 1299 sizeof(new_mtu), true, NULL, 0); 1300 } 1301 1302 static int hclgevf_notify_client(struct hclgevf_dev *hdev, 1303 enum hnae3_reset_notify_type type) 1304 { 1305 struct hnae3_client *client = hdev->nic_client; 1306 struct hnae3_handle *handle = &hdev->nic; 1307 int ret; 1308 1309 if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 1310 !client) 1311 return 0; 1312 1313 if (!client->ops->reset_notify) 1314 return -EOPNOTSUPP; 1315 1316 ret = client->ops->reset_notify(handle, type); 1317 if (ret) 1318 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 1319 type, ret); 1320 1321 return ret; 1322 } 1323 1324 static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 1325 { 1326 struct hclgevf_dev *hdev = ae_dev->priv; 1327 1328 set_bit(HNAE3_FLR_DONE, &hdev->flr_state); 1329 } 1330 1331 static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev, 1332 unsigned long delay_us, 1333 unsigned long wait_cnt) 1334 { 1335 unsigned long cnt = 0; 1336 1337 while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) && 1338 cnt++ < wait_cnt) 1339 usleep_range(delay_us, delay_us * 2); 1340 1341 if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) { 1342 dev_err(&hdev->pdev->dev, 1343 "flr wait timeout\n"); 1344 return -ETIMEDOUT; 1345 } 1346 1347 return 0; 1348 } 1349 1350 static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 1351 { 1352 #define HCLGEVF_RESET_WAIT_US 20000 1353 #define HCLGEVF_RESET_WAIT_CNT 2000 1354 #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1355 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1356 1357 u32 val; 1358 int ret; 1359 1360 /* wait to check the hardware reset completion status */ 1361 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1362 dev_info(&hdev->pdev->dev, "checking vf resetting status: %x\n", val); 1363 1364 if (hdev->reset_type == HNAE3_FLR_RESET) 1365 return hclgevf_flr_poll_timeout(hdev, 1366 HCLGEVF_RESET_WAIT_US, 1367 HCLGEVF_RESET_WAIT_CNT); 1368 1369 ret = readl_poll_timeout(hdev->hw.io_base + HCLGEVF_RST_ING, val, 1370 !(val & HCLGEVF_RST_ING_BITS), 1371 HCLGEVF_RESET_WAIT_US, 1372 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1373 1374 /* hardware completion status should be available by this time */ 1375 if (ret) { 1376 dev_err(&hdev->pdev->dev, 1377 "could'nt get reset done status from h/w, timeout!\n"); 1378 return ret; 1379 } 1380 1381 /* we will wait a bit more to let reset of the stack to complete. This 1382 * might happen in case reset assertion was made by PF. Yes, this also 1383 * means we might end up waiting bit more even for VF reset. 1384 */ 1385 msleep(5000); 1386 1387 return 0; 1388 } 1389 1390 static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 1391 { 1392 int ret; 1393 1394 /* uninitialize the nic client */ 1395 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 1396 if (ret) 1397 return ret; 1398 1399 /* re-initialize the hclge device */ 1400 ret = hclgevf_reset_hdev(hdev); 1401 if (ret) { 1402 dev_err(&hdev->pdev->dev, 1403 "hclge device re-init failed, VF is disabled!\n"); 1404 return ret; 1405 } 1406 1407 /* bring up the nic client again */ 1408 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 1409 if (ret) 1410 return ret; 1411 1412 return hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT); 1413 } 1414 1415 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1416 { 1417 int ret = 0; 1418 1419 switch (hdev->reset_type) { 1420 case HNAE3_VF_FUNC_RESET: 1421 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1422 0, true, NULL, sizeof(u8)); 1423 hdev->rst_stats.vf_func_rst_cnt++; 1424 break; 1425 case HNAE3_FLR_RESET: 1426 set_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1427 hdev->rst_stats.flr_rst_cnt++; 1428 break; 1429 default: 1430 break; 1431 } 1432 1433 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1434 1435 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1436 hdev->reset_type, ret); 1437 1438 return ret; 1439 } 1440 1441 static int hclgevf_reset(struct hclgevf_dev *hdev) 1442 { 1443 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1444 int ret; 1445 1446 /* Initialize ae_dev reset status as well, in case enet layer wants to 1447 * know if device is undergoing reset 1448 */ 1449 ae_dev->reset_type = hdev->reset_type; 1450 hdev->rst_stats.rst_cnt++; 1451 rtnl_lock(); 1452 1453 /* bring down the nic to stop any ongoing TX/RX */ 1454 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 1455 if (ret) 1456 goto err_reset_lock; 1457 1458 rtnl_unlock(); 1459 1460 ret = hclgevf_reset_prepare_wait(hdev); 1461 if (ret) 1462 goto err_reset; 1463 1464 /* check if VF could successfully fetch the hardware reset completion 1465 * status from the hardware 1466 */ 1467 ret = hclgevf_reset_wait(hdev); 1468 if (ret) { 1469 /* can't do much in this situation, will disable VF */ 1470 dev_err(&hdev->pdev->dev, 1471 "VF failed(=%d) to fetch H/W reset completion status\n", 1472 ret); 1473 goto err_reset; 1474 } 1475 1476 hdev->rst_stats.hw_rst_done_cnt++; 1477 1478 rtnl_lock(); 1479 1480 /* now, re-initialize the nic client and ae device*/ 1481 ret = hclgevf_reset_stack(hdev); 1482 if (ret) { 1483 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 1484 goto err_reset_lock; 1485 } 1486 1487 /* bring up the nic to enable TX/RX again */ 1488 ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 1489 if (ret) 1490 goto err_reset_lock; 1491 1492 rtnl_unlock(); 1493 1494 hdev->last_reset_time = jiffies; 1495 ae_dev->reset_type = HNAE3_NONE_RESET; 1496 hdev->rst_stats.rst_done_cnt++; 1497 1498 return ret; 1499 err_reset_lock: 1500 rtnl_unlock(); 1501 err_reset: 1502 /* When VF reset failed, only the higher level reset asserted by PF 1503 * can restore it, so re-initialize the command queue to receive 1504 * this higher reset event. 1505 */ 1506 hclgevf_cmd_init(hdev); 1507 dev_err(&hdev->pdev->dev, "failed to reset VF\n"); 1508 if (hclgevf_is_reset_pending(hdev)) 1509 hclgevf_reset_task_schedule(hdev); 1510 1511 return ret; 1512 } 1513 1514 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1515 unsigned long *addr) 1516 { 1517 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1518 1519 /* return the highest priority reset level amongst all */ 1520 if (test_bit(HNAE3_VF_RESET, addr)) { 1521 rst_level = HNAE3_VF_RESET; 1522 clear_bit(HNAE3_VF_RESET, addr); 1523 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1524 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1525 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1526 rst_level = HNAE3_VF_FULL_RESET; 1527 clear_bit(HNAE3_VF_FULL_RESET, addr); 1528 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1529 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1530 rst_level = HNAE3_VF_PF_FUNC_RESET; 1531 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1532 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1533 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1534 rst_level = HNAE3_VF_FUNC_RESET; 1535 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1536 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 1537 rst_level = HNAE3_FLR_RESET; 1538 clear_bit(HNAE3_FLR_RESET, addr); 1539 } 1540 1541 return rst_level; 1542 } 1543 1544 static void hclgevf_reset_event(struct pci_dev *pdev, 1545 struct hnae3_handle *handle) 1546 { 1547 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1548 struct hclgevf_dev *hdev = ae_dev->priv; 1549 1550 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 1551 1552 if (hdev->default_reset_request) 1553 hdev->reset_level = 1554 hclgevf_get_reset_level(hdev, 1555 &hdev->default_reset_request); 1556 else 1557 hdev->reset_level = HNAE3_VF_FUNC_RESET; 1558 1559 /* reset of this VF requested */ 1560 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1561 hclgevf_reset_task_schedule(hdev); 1562 1563 hdev->last_reset_time = jiffies; 1564 } 1565 1566 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1567 enum hnae3_reset_type rst_type) 1568 { 1569 struct hclgevf_dev *hdev = ae_dev->priv; 1570 1571 set_bit(rst_type, &hdev->default_reset_request); 1572 } 1573 1574 static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 1575 { 1576 #define HCLGEVF_FLR_WAIT_MS 100 1577 #define HCLGEVF_FLR_WAIT_CNT 50 1578 struct hclgevf_dev *hdev = ae_dev->priv; 1579 int cnt = 0; 1580 1581 clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1582 clear_bit(HNAE3_FLR_DONE, &hdev->flr_state); 1583 set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request); 1584 hclgevf_reset_event(hdev->pdev, NULL); 1585 1586 while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) && 1587 cnt++ < HCLGEVF_FLR_WAIT_CNT) 1588 msleep(HCLGEVF_FLR_WAIT_MS); 1589 1590 if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state)) 1591 dev_err(&hdev->pdev->dev, 1592 "flr wait down timeout: %d\n", cnt); 1593 } 1594 1595 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1596 { 1597 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1598 1599 return hdev->fw_version; 1600 } 1601 1602 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1603 { 1604 struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1605 1606 vector->vector_irq = pci_irq_vector(hdev->pdev, 1607 HCLGEVF_MISC_VECTOR_NUM); 1608 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1609 /* vector status always valid for Vector 0 */ 1610 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1611 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1612 1613 hdev->num_msi_left -= 1; 1614 hdev->num_msi_used += 1; 1615 } 1616 1617 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 1618 { 1619 if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state)) { 1620 set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 1621 schedule_work(&hdev->rst_service_task); 1622 } 1623 } 1624 1625 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1626 { 1627 if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) && 1628 !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) { 1629 set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1630 schedule_work(&hdev->mbx_service_task); 1631 } 1632 } 1633 1634 static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 1635 { 1636 if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 1637 !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 1638 schedule_work(&hdev->service_task); 1639 } 1640 1641 static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev) 1642 { 1643 /* if we have any pending mailbox event then schedule the mbx task */ 1644 if (hdev->mbx_event_pending) 1645 hclgevf_mbx_task_schedule(hdev); 1646 1647 if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state)) 1648 hclgevf_reset_task_schedule(hdev); 1649 } 1650 1651 static void hclgevf_service_timer(struct timer_list *t) 1652 { 1653 struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 1654 1655 mod_timer(&hdev->service_timer, jiffies + 5 * HZ); 1656 1657 hdev->stats_timer++; 1658 hclgevf_task_schedule(hdev); 1659 } 1660 1661 static void hclgevf_reset_service_task(struct work_struct *work) 1662 { 1663 struct hclgevf_dev *hdev = 1664 container_of(work, struct hclgevf_dev, rst_service_task); 1665 int ret; 1666 1667 if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1668 return; 1669 1670 clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 1671 1672 if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1673 &hdev->reset_state)) { 1674 /* PF has initmated that it is about to reset the hardware. 1675 * We now have to poll & check if harware has actually completed 1676 * the reset sequence. On hardware reset completion, VF needs to 1677 * reset the client and ae device. 1678 */ 1679 hdev->reset_attempts = 0; 1680 1681 hdev->last_reset_time = jiffies; 1682 while ((hdev->reset_type = 1683 hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 1684 != HNAE3_NONE_RESET) { 1685 ret = hclgevf_reset(hdev); 1686 if (ret) 1687 dev_err(&hdev->pdev->dev, 1688 "VF stack reset failed %d.\n", ret); 1689 } 1690 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1691 &hdev->reset_state)) { 1692 /* we could be here when either of below happens: 1693 * 1. reset was initiated due to watchdog timeout due to 1694 * a. IMP was earlier reset and our TX got choked down and 1695 * which resulted in watchdog reacting and inducing VF 1696 * reset. This also means our cmdq would be unreliable. 1697 * b. problem in TX due to other lower layer(example link 1698 * layer not functioning properly etc.) 1699 * 2. VF reset might have been initiated due to some config 1700 * change. 1701 * 1702 * NOTE: Theres no clear way to detect above cases than to react 1703 * to the response of PF for this reset request. PF will ack the 1704 * 1b and 2. cases but we will not get any intimation about 1a 1705 * from PF as cmdq would be in unreliable state i.e. mailbox 1706 * communication between PF and VF would be broken. 1707 */ 1708 1709 /* if we are never geting into pending state it means either: 1710 * 1. PF is not receiving our request which could be due to IMP 1711 * reset 1712 * 2. PF is screwed 1713 * We cannot do much for 2. but to check first we can try reset 1714 * our PCIe + stack and see if it alleviates the problem. 1715 */ 1716 if (hdev->reset_attempts > 3) { 1717 /* prepare for full reset of stack + pcie interface */ 1718 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1719 1720 /* "defer" schedule the reset task again */ 1721 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1722 } else { 1723 hdev->reset_attempts++; 1724 1725 set_bit(hdev->reset_level, &hdev->reset_pending); 1726 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1727 } 1728 hclgevf_reset_task_schedule(hdev); 1729 } 1730 1731 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1732 } 1733 1734 static void hclgevf_mailbox_service_task(struct work_struct *work) 1735 { 1736 struct hclgevf_dev *hdev; 1737 1738 hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 1739 1740 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1741 return; 1742 1743 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1744 1745 hclgevf_mbx_async_handler(hdev); 1746 1747 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1748 } 1749 1750 static void hclgevf_keep_alive_timer(struct timer_list *t) 1751 { 1752 struct hclgevf_dev *hdev = from_timer(hdev, t, keep_alive_timer); 1753 1754 schedule_work(&hdev->keep_alive_task); 1755 mod_timer(&hdev->keep_alive_timer, jiffies + 2 * HZ); 1756 } 1757 1758 static void hclgevf_keep_alive_task(struct work_struct *work) 1759 { 1760 struct hclgevf_dev *hdev; 1761 u8 respmsg; 1762 int ret; 1763 1764 hdev = container_of(work, struct hclgevf_dev, keep_alive_task); 1765 1766 if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 1767 return; 1768 1769 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL, 1770 0, false, &respmsg, sizeof(u8)); 1771 if (ret) 1772 dev_err(&hdev->pdev->dev, 1773 "VF sends keep alive cmd failed(=%d)\n", ret); 1774 } 1775 1776 static void hclgevf_service_task(struct work_struct *work) 1777 { 1778 struct hnae3_handle *handle; 1779 struct hclgevf_dev *hdev; 1780 1781 hdev = container_of(work, struct hclgevf_dev, service_task); 1782 handle = &hdev->nic; 1783 1784 if (hdev->stats_timer >= HCLGEVF_STATS_TIMER_INTERVAL) { 1785 hclgevf_tqps_update_stats(handle); 1786 hdev->stats_timer = 0; 1787 } 1788 1789 /* request the link status from the PF. PF would be able to tell VF 1790 * about such updates in future so we might remove this later 1791 */ 1792 hclgevf_request_link_info(hdev); 1793 1794 hclgevf_update_link_mode(hdev); 1795 1796 hclgevf_deferred_task_schedule(hdev); 1797 1798 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1799 } 1800 1801 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1802 { 1803 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1804 } 1805 1806 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1807 u32 *clearval) 1808 { 1809 u32 cmdq_src_reg, rst_ing_reg; 1810 1811 /* fetch the events from their corresponding regs */ 1812 cmdq_src_reg = hclgevf_read_dev(&hdev->hw, 1813 HCLGEVF_VECTOR0_CMDQ_SRC_REG); 1814 1815 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_src_reg) { 1816 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1817 dev_info(&hdev->pdev->dev, 1818 "receive reset interrupt 0x%x!\n", rst_ing_reg); 1819 set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1820 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1821 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1822 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RST_INT_B); 1823 *clearval = cmdq_src_reg; 1824 hdev->rst_stats.vf_rst_cnt++; 1825 return HCLGEVF_VECTOR0_EVENT_RST; 1826 } 1827 1828 /* check for vector0 mailbox(=CMDQ RX) event source */ 1829 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 1830 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1831 *clearval = cmdq_src_reg; 1832 return HCLGEVF_VECTOR0_EVENT_MBX; 1833 } 1834 1835 dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 1836 1837 return HCLGEVF_VECTOR0_EVENT_OTHER; 1838 } 1839 1840 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1841 { 1842 writel(en ? 1 : 0, vector->addr); 1843 } 1844 1845 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1846 { 1847 enum hclgevf_evt_cause event_cause; 1848 struct hclgevf_dev *hdev = data; 1849 u32 clearval; 1850 1851 hclgevf_enable_vector(&hdev->misc_vector, false); 1852 event_cause = hclgevf_check_evt_cause(hdev, &clearval); 1853 1854 switch (event_cause) { 1855 case HCLGEVF_VECTOR0_EVENT_RST: 1856 hclgevf_reset_task_schedule(hdev); 1857 break; 1858 case HCLGEVF_VECTOR0_EVENT_MBX: 1859 hclgevf_mbx_handler(hdev); 1860 break; 1861 default: 1862 break; 1863 } 1864 1865 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 1866 hclgevf_clear_event_cause(hdev, clearval); 1867 hclgevf_enable_vector(&hdev->misc_vector, true); 1868 } 1869 1870 return IRQ_HANDLED; 1871 } 1872 1873 static int hclgevf_configure(struct hclgevf_dev *hdev) 1874 { 1875 int ret; 1876 1877 /* get current port based vlan state from PF */ 1878 ret = hclgevf_get_port_base_vlan_filter_state(hdev); 1879 if (ret) 1880 return ret; 1881 1882 /* get queue configuration from PF */ 1883 ret = hclgevf_get_queue_info(hdev); 1884 if (ret) 1885 return ret; 1886 1887 /* get queue depth info from PF */ 1888 ret = hclgevf_get_queue_depth(hdev); 1889 if (ret) 1890 return ret; 1891 1892 ret = hclgevf_get_pf_media_type(hdev); 1893 if (ret) 1894 return ret; 1895 1896 /* get tc configuration from PF */ 1897 return hclgevf_get_tc_info(hdev); 1898 } 1899 1900 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 1901 { 1902 struct pci_dev *pdev = ae_dev->pdev; 1903 struct hclgevf_dev *hdev; 1904 1905 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 1906 if (!hdev) 1907 return -ENOMEM; 1908 1909 hdev->pdev = pdev; 1910 hdev->ae_dev = ae_dev; 1911 ae_dev->priv = hdev; 1912 1913 return 0; 1914 } 1915 1916 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 1917 { 1918 struct hnae3_handle *roce = &hdev->roce; 1919 struct hnae3_handle *nic = &hdev->nic; 1920 1921 roce->rinfo.num_vectors = hdev->num_roce_msix; 1922 1923 if (hdev->num_msi_left < roce->rinfo.num_vectors || 1924 hdev->num_msi_left == 0) 1925 return -EINVAL; 1926 1927 roce->rinfo.base_vector = hdev->roce_base_vector; 1928 1929 roce->rinfo.netdev = nic->kinfo.netdev; 1930 roce->rinfo.roce_io_base = hdev->hw.io_base; 1931 1932 roce->pdev = nic->pdev; 1933 roce->ae_algo = nic->ae_algo; 1934 roce->numa_node_mask = nic->numa_node_mask; 1935 1936 return 0; 1937 } 1938 1939 static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 1940 { 1941 struct hclgevf_cfg_gro_status_cmd *req; 1942 struct hclgevf_desc desc; 1943 int ret; 1944 1945 if (!hnae3_dev_gro_supported(hdev)) 1946 return 0; 1947 1948 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 1949 false); 1950 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 1951 1952 req->gro_en = cpu_to_le16(en ? 1 : 0); 1953 1954 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1955 if (ret) 1956 dev_err(&hdev->pdev->dev, 1957 "VF GRO hardware config cmd failed, ret = %d.\n", ret); 1958 1959 return ret; 1960 } 1961 1962 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 1963 { 1964 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1965 int i, ret; 1966 1967 rss_cfg->rss_size = hdev->rss_size_max; 1968 1969 if (hdev->pdev->revision >= 0x21) { 1970 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 1971 memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 1972 HCLGEVF_RSS_KEY_SIZE); 1973 1974 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 1975 rss_cfg->rss_hash_key); 1976 if (ret) 1977 return ret; 1978 1979 rss_cfg->rss_tuple_sets.ipv4_tcp_en = 1980 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1981 rss_cfg->rss_tuple_sets.ipv4_udp_en = 1982 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1983 rss_cfg->rss_tuple_sets.ipv4_sctp_en = 1984 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1985 rss_cfg->rss_tuple_sets.ipv4_fragment_en = 1986 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1987 rss_cfg->rss_tuple_sets.ipv6_tcp_en = 1988 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1989 rss_cfg->rss_tuple_sets.ipv6_udp_en = 1990 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1991 rss_cfg->rss_tuple_sets.ipv6_sctp_en = 1992 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1993 rss_cfg->rss_tuple_sets.ipv6_fragment_en = 1994 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1995 1996 ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 1997 if (ret) 1998 return ret; 1999 2000 } 2001 2002 /* Initialize RSS indirect table for each vport */ 2003 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 2004 rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max; 2005 2006 ret = hclgevf_set_rss_indir_table(hdev); 2007 if (ret) 2008 return ret; 2009 2010 return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max); 2011 } 2012 2013 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2014 { 2015 /* other vlan config(like, VLAN TX/RX offload) would also be added 2016 * here later 2017 */ 2018 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2019 false); 2020 } 2021 2022 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 2023 { 2024 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2025 2026 if (enable) { 2027 mod_timer(&hdev->service_timer, jiffies + HZ); 2028 } else { 2029 del_timer_sync(&hdev->service_timer); 2030 cancel_work_sync(&hdev->service_task); 2031 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2032 } 2033 } 2034 2035 static int hclgevf_ae_start(struct hnae3_handle *handle) 2036 { 2037 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2038 2039 /* reset tqp stats */ 2040 hclgevf_reset_tqp_stats(handle); 2041 2042 hclgevf_request_link_info(hdev); 2043 2044 hclgevf_update_link_mode(hdev); 2045 2046 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2047 2048 return 0; 2049 } 2050 2051 static void hclgevf_ae_stop(struct hnae3_handle *handle) 2052 { 2053 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2054 int i; 2055 2056 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2057 2058 if (hdev->reset_type != HNAE3_VF_RESET) 2059 for (i = 0; i < handle->kinfo.num_tqps; i++) 2060 if (hclgevf_reset_tqp(handle, i)) 2061 break; 2062 2063 /* reset tqp stats */ 2064 hclgevf_reset_tqp_stats(handle); 2065 hclgevf_update_link_status(hdev, 0); 2066 } 2067 2068 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2069 { 2070 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2071 u8 msg_data; 2072 2073 msg_data = alive ? 1 : 0; 2074 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE, 2075 0, &msg_data, 1, false, NULL, 0); 2076 } 2077 2078 static int hclgevf_client_start(struct hnae3_handle *handle) 2079 { 2080 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2081 int ret; 2082 2083 ret = hclgevf_set_alive(handle, true); 2084 if (ret) 2085 return ret; 2086 2087 mod_timer(&hdev->keep_alive_timer, jiffies + 2 * HZ); 2088 2089 return 0; 2090 } 2091 2092 static void hclgevf_client_stop(struct hnae3_handle *handle) 2093 { 2094 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2095 int ret; 2096 2097 ret = hclgevf_set_alive(handle, false); 2098 if (ret) 2099 dev_warn(&hdev->pdev->dev, 2100 "%s failed %d\n", __func__, ret); 2101 2102 del_timer_sync(&hdev->keep_alive_timer); 2103 cancel_work_sync(&hdev->keep_alive_task); 2104 } 2105 2106 static void hclgevf_state_init(struct hclgevf_dev *hdev) 2107 { 2108 /* setup tasks for the MBX */ 2109 INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 2110 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2111 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2112 2113 /* setup tasks for service timer */ 2114 timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 2115 2116 INIT_WORK(&hdev->service_task, hclgevf_service_task); 2117 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2118 2119 INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task); 2120 2121 mutex_init(&hdev->mbx_resp.mbx_mutex); 2122 2123 /* bring the device down */ 2124 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2125 } 2126 2127 static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2128 { 2129 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2130 2131 if (hdev->keep_alive_timer.function) 2132 del_timer_sync(&hdev->keep_alive_timer); 2133 if (hdev->keep_alive_task.func) 2134 cancel_work_sync(&hdev->keep_alive_task); 2135 if (hdev->service_timer.function) 2136 del_timer_sync(&hdev->service_timer); 2137 if (hdev->service_task.func) 2138 cancel_work_sync(&hdev->service_task); 2139 if (hdev->mbx_service_task.func) 2140 cancel_work_sync(&hdev->mbx_service_task); 2141 if (hdev->rst_service_task.func) 2142 cancel_work_sync(&hdev->rst_service_task); 2143 2144 mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2145 } 2146 2147 static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2148 { 2149 struct pci_dev *pdev = hdev->pdev; 2150 int vectors; 2151 int i; 2152 2153 if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) 2154 vectors = pci_alloc_irq_vectors(pdev, 2155 hdev->roce_base_msix_offset + 1, 2156 hdev->num_msi, 2157 PCI_IRQ_MSIX); 2158 else 2159 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 2160 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2161 2162 if (vectors < 0) { 2163 dev_err(&pdev->dev, 2164 "failed(%d) to allocate MSI/MSI-X vectors\n", 2165 vectors); 2166 return vectors; 2167 } 2168 if (vectors < hdev->num_msi) 2169 dev_warn(&hdev->pdev->dev, 2170 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2171 hdev->num_msi, vectors); 2172 2173 hdev->num_msi = vectors; 2174 hdev->num_msi_left = vectors; 2175 hdev->base_msi_vector = pdev->irq; 2176 hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2177 2178 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2179 sizeof(u16), GFP_KERNEL); 2180 if (!hdev->vector_status) { 2181 pci_free_irq_vectors(pdev); 2182 return -ENOMEM; 2183 } 2184 2185 for (i = 0; i < hdev->num_msi; i++) 2186 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2187 2188 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2189 sizeof(int), GFP_KERNEL); 2190 if (!hdev->vector_irq) { 2191 devm_kfree(&pdev->dev, hdev->vector_status); 2192 pci_free_irq_vectors(pdev); 2193 return -ENOMEM; 2194 } 2195 2196 return 0; 2197 } 2198 2199 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2200 { 2201 struct pci_dev *pdev = hdev->pdev; 2202 2203 devm_kfree(&pdev->dev, hdev->vector_status); 2204 devm_kfree(&pdev->dev, hdev->vector_irq); 2205 pci_free_irq_vectors(pdev); 2206 } 2207 2208 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2209 { 2210 int ret = 0; 2211 2212 hclgevf_get_misc_vector(hdev); 2213 2214 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2215 0, "hclgevf_cmd", hdev); 2216 if (ret) { 2217 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2218 hdev->misc_vector.vector_irq); 2219 return ret; 2220 } 2221 2222 hclgevf_clear_event_cause(hdev, 0); 2223 2224 /* enable misc. vector(vector 0) */ 2225 hclgevf_enable_vector(&hdev->misc_vector, true); 2226 2227 return ret; 2228 } 2229 2230 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2231 { 2232 /* disable misc vector(vector 0) */ 2233 hclgevf_enable_vector(&hdev->misc_vector, false); 2234 synchronize_irq(hdev->misc_vector.vector_irq); 2235 free_irq(hdev->misc_vector.vector_irq, hdev); 2236 hclgevf_free_vector(hdev, 0); 2237 } 2238 2239 static void hclgevf_info_show(struct hclgevf_dev *hdev) 2240 { 2241 struct device *dev = &hdev->pdev->dev; 2242 2243 dev_info(dev, "VF info begin:\n"); 2244 2245 dev_info(dev, "Task queue pairs numbers: %d\n", hdev->num_tqps); 2246 dev_info(dev, "Desc num per TX queue: %d\n", hdev->num_tx_desc); 2247 dev_info(dev, "Desc num per RX queue: %d\n", hdev->num_rx_desc); 2248 dev_info(dev, "Numbers of vports: %d\n", hdev->num_alloc_vport); 2249 dev_info(dev, "HW tc map: %d\n", hdev->hw_tc_map); 2250 dev_info(dev, "PF media type of this VF: %d\n", 2251 hdev->hw.mac.media_type); 2252 2253 dev_info(dev, "VF info end.\n"); 2254 } 2255 2256 static int hclgevf_init_client_instance(struct hnae3_client *client, 2257 struct hnae3_ae_dev *ae_dev) 2258 { 2259 struct hclgevf_dev *hdev = ae_dev->priv; 2260 int ret; 2261 2262 switch (client->type) { 2263 case HNAE3_CLIENT_KNIC: 2264 hdev->nic_client = client; 2265 hdev->nic.client = client; 2266 2267 ret = client->ops->init_instance(&hdev->nic); 2268 if (ret) 2269 goto clear_nic; 2270 2271 hnae3_set_client_init_flag(client, ae_dev, 1); 2272 set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2273 2274 if (netif_msg_drv(&hdev->nic)) 2275 hclgevf_info_show(hdev); 2276 2277 if (hdev->roce_client && hnae3_dev_roce_supported(hdev)) { 2278 struct hnae3_client *rc = hdev->roce_client; 2279 2280 ret = hclgevf_init_roce_base_info(hdev); 2281 if (ret) 2282 goto clear_roce; 2283 ret = rc->ops->init_instance(&hdev->roce); 2284 if (ret) 2285 goto clear_roce; 2286 2287 hnae3_set_client_init_flag(hdev->roce_client, ae_dev, 2288 1); 2289 } 2290 break; 2291 case HNAE3_CLIENT_UNIC: 2292 hdev->nic_client = client; 2293 hdev->nic.client = client; 2294 2295 ret = client->ops->init_instance(&hdev->nic); 2296 if (ret) 2297 goto clear_nic; 2298 2299 hnae3_set_client_init_flag(client, ae_dev, 1); 2300 break; 2301 case HNAE3_CLIENT_ROCE: 2302 if (hnae3_dev_roce_supported(hdev)) { 2303 hdev->roce_client = client; 2304 hdev->roce.client = client; 2305 } 2306 2307 if (hdev->roce_client && hdev->nic_client) { 2308 ret = hclgevf_init_roce_base_info(hdev); 2309 if (ret) 2310 goto clear_roce; 2311 2312 ret = client->ops->init_instance(&hdev->roce); 2313 if (ret) 2314 goto clear_roce; 2315 } 2316 2317 hnae3_set_client_init_flag(client, ae_dev, 1); 2318 break; 2319 default: 2320 return -EINVAL; 2321 } 2322 2323 return 0; 2324 2325 clear_nic: 2326 hdev->nic_client = NULL; 2327 hdev->nic.client = NULL; 2328 return ret; 2329 clear_roce: 2330 hdev->roce_client = NULL; 2331 hdev->roce.client = NULL; 2332 return ret; 2333 } 2334 2335 static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2336 struct hnae3_ae_dev *ae_dev) 2337 { 2338 struct hclgevf_dev *hdev = ae_dev->priv; 2339 2340 /* un-init roce, if it exists */ 2341 if (hdev->roce_client) { 2342 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 2343 hdev->roce_client = NULL; 2344 hdev->roce.client = NULL; 2345 } 2346 2347 /* un-init nic/unic, if this was not called by roce client */ 2348 if (client->ops->uninit_instance && hdev->nic_client && 2349 client->type != HNAE3_CLIENT_ROCE) { 2350 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2351 2352 client->ops->uninit_instance(&hdev->nic, 0); 2353 hdev->nic_client = NULL; 2354 hdev->nic.client = NULL; 2355 } 2356 } 2357 2358 static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2359 { 2360 struct pci_dev *pdev = hdev->pdev; 2361 struct hclgevf_hw *hw; 2362 int ret; 2363 2364 ret = pci_enable_device(pdev); 2365 if (ret) { 2366 dev_err(&pdev->dev, "failed to enable PCI device\n"); 2367 return ret; 2368 } 2369 2370 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2371 if (ret) { 2372 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2373 goto err_disable_device; 2374 } 2375 2376 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2377 if (ret) { 2378 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2379 goto err_disable_device; 2380 } 2381 2382 pci_set_master(pdev); 2383 hw = &hdev->hw; 2384 hw->hdev = hdev; 2385 hw->io_base = pci_iomap(pdev, 2, 0); 2386 if (!hw->io_base) { 2387 dev_err(&pdev->dev, "can't map configuration register space\n"); 2388 ret = -ENOMEM; 2389 goto err_clr_master; 2390 } 2391 2392 return 0; 2393 2394 err_clr_master: 2395 pci_clear_master(pdev); 2396 pci_release_regions(pdev); 2397 err_disable_device: 2398 pci_disable_device(pdev); 2399 2400 return ret; 2401 } 2402 2403 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2404 { 2405 struct pci_dev *pdev = hdev->pdev; 2406 2407 pci_iounmap(pdev, hdev->hw.io_base); 2408 pci_clear_master(pdev); 2409 pci_release_regions(pdev); 2410 pci_disable_device(pdev); 2411 } 2412 2413 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 2414 { 2415 struct hclgevf_query_res_cmd *req; 2416 struct hclgevf_desc desc; 2417 int ret; 2418 2419 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 2420 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2421 if (ret) { 2422 dev_err(&hdev->pdev->dev, 2423 "query vf resource failed, ret = %d.\n", ret); 2424 return ret; 2425 } 2426 2427 req = (struct hclgevf_query_res_cmd *)desc.data; 2428 2429 if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) { 2430 hdev->roce_base_msix_offset = 2431 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 2432 HCLGEVF_MSIX_OFT_ROCEE_M, 2433 HCLGEVF_MSIX_OFT_ROCEE_S); 2434 hdev->num_roce_msix = 2435 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 2436 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2437 2438 /* VF should have NIC vectors and Roce vectors, NIC vectors 2439 * are queued before Roce vectors. The offset is fixed to 64. 2440 */ 2441 hdev->num_msi = hdev->num_roce_msix + 2442 hdev->roce_base_msix_offset; 2443 } else { 2444 hdev->num_msi = 2445 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 2446 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2447 } 2448 2449 return 0; 2450 } 2451 2452 static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2453 { 2454 struct pci_dev *pdev = hdev->pdev; 2455 int ret = 0; 2456 2457 if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2458 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2459 hclgevf_misc_irq_uninit(hdev); 2460 hclgevf_uninit_msi(hdev); 2461 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2462 } 2463 2464 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2465 pci_set_master(pdev); 2466 ret = hclgevf_init_msi(hdev); 2467 if (ret) { 2468 dev_err(&pdev->dev, 2469 "failed(%d) to init MSI/MSI-X\n", ret); 2470 return ret; 2471 } 2472 2473 ret = hclgevf_misc_irq_init(hdev); 2474 if (ret) { 2475 hclgevf_uninit_msi(hdev); 2476 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2477 ret); 2478 return ret; 2479 } 2480 2481 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2482 } 2483 2484 return ret; 2485 } 2486 2487 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2488 { 2489 struct pci_dev *pdev = hdev->pdev; 2490 int ret; 2491 2492 ret = hclgevf_pci_reset(hdev); 2493 if (ret) { 2494 dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2495 return ret; 2496 } 2497 2498 ret = hclgevf_cmd_init(hdev); 2499 if (ret) { 2500 dev_err(&pdev->dev, "cmd failed %d\n", ret); 2501 return ret; 2502 } 2503 2504 ret = hclgevf_rss_init_hw(hdev); 2505 if (ret) { 2506 dev_err(&hdev->pdev->dev, 2507 "failed(%d) to initialize RSS\n", ret); 2508 return ret; 2509 } 2510 2511 ret = hclgevf_config_gro(hdev, true); 2512 if (ret) 2513 return ret; 2514 2515 ret = hclgevf_init_vlan_config(hdev); 2516 if (ret) { 2517 dev_err(&hdev->pdev->dev, 2518 "failed(%d) to initialize VLAN config\n", ret); 2519 return ret; 2520 } 2521 2522 dev_info(&hdev->pdev->dev, "Reset done\n"); 2523 2524 return 0; 2525 } 2526 2527 static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 2528 { 2529 struct pci_dev *pdev = hdev->pdev; 2530 int ret; 2531 2532 ret = hclgevf_pci_init(hdev); 2533 if (ret) { 2534 dev_err(&pdev->dev, "PCI initialization failed\n"); 2535 return ret; 2536 } 2537 2538 ret = hclgevf_cmd_queue_init(hdev); 2539 if (ret) { 2540 dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret); 2541 goto err_cmd_queue_init; 2542 } 2543 2544 ret = hclgevf_cmd_init(hdev); 2545 if (ret) 2546 goto err_cmd_init; 2547 2548 /* Get vf resource */ 2549 ret = hclgevf_query_vf_resource(hdev); 2550 if (ret) { 2551 dev_err(&hdev->pdev->dev, 2552 "Query vf status error, ret = %d.\n", ret); 2553 goto err_cmd_init; 2554 } 2555 2556 ret = hclgevf_init_msi(hdev); 2557 if (ret) { 2558 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 2559 goto err_cmd_init; 2560 } 2561 2562 hclgevf_state_init(hdev); 2563 hdev->reset_level = HNAE3_VF_FUNC_RESET; 2564 2565 ret = hclgevf_misc_irq_init(hdev); 2566 if (ret) { 2567 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2568 ret); 2569 goto err_misc_irq_init; 2570 } 2571 2572 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2573 2574 ret = hclgevf_configure(hdev); 2575 if (ret) { 2576 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2577 goto err_config; 2578 } 2579 2580 ret = hclgevf_alloc_tqps(hdev); 2581 if (ret) { 2582 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2583 goto err_config; 2584 } 2585 2586 ret = hclgevf_set_handle_info(hdev); 2587 if (ret) { 2588 dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 2589 goto err_config; 2590 } 2591 2592 ret = hclgevf_config_gro(hdev, true); 2593 if (ret) 2594 goto err_config; 2595 2596 /* vf is not allowed to enable unicast/multicast promisc mode. 2597 * For revision 0x20, default to disable broadcast promisc mode, 2598 * firmware makes sure broadcast packets can be accepted. 2599 * For revision 0x21, default to enable broadcast promisc mode. 2600 */ 2601 ret = hclgevf_set_promisc_mode(hdev, true); 2602 if (ret) 2603 goto err_config; 2604 2605 /* Initialize RSS for this VF */ 2606 ret = hclgevf_rss_init_hw(hdev); 2607 if (ret) { 2608 dev_err(&hdev->pdev->dev, 2609 "failed(%d) to initialize RSS\n", ret); 2610 goto err_config; 2611 } 2612 2613 ret = hclgevf_init_vlan_config(hdev); 2614 if (ret) { 2615 dev_err(&hdev->pdev->dev, 2616 "failed(%d) to initialize VLAN config\n", ret); 2617 goto err_config; 2618 } 2619 2620 hdev->last_reset_time = jiffies; 2621 pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME); 2622 2623 return 0; 2624 2625 err_config: 2626 hclgevf_misc_irq_uninit(hdev); 2627 err_misc_irq_init: 2628 hclgevf_state_uninit(hdev); 2629 hclgevf_uninit_msi(hdev); 2630 err_cmd_init: 2631 hclgevf_cmd_uninit(hdev); 2632 err_cmd_queue_init: 2633 hclgevf_pci_uninit(hdev); 2634 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2635 return ret; 2636 } 2637 2638 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2639 { 2640 hclgevf_state_uninit(hdev); 2641 2642 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2643 hclgevf_misc_irq_uninit(hdev); 2644 hclgevf_uninit_msi(hdev); 2645 } 2646 2647 hclgevf_pci_uninit(hdev); 2648 hclgevf_cmd_uninit(hdev); 2649 } 2650 2651 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 2652 { 2653 struct pci_dev *pdev = ae_dev->pdev; 2654 struct hclgevf_dev *hdev; 2655 int ret; 2656 2657 ret = hclgevf_alloc_hdev(ae_dev); 2658 if (ret) { 2659 dev_err(&pdev->dev, "hclge device allocation failed\n"); 2660 return ret; 2661 } 2662 2663 ret = hclgevf_init_hdev(ae_dev->priv); 2664 if (ret) { 2665 dev_err(&pdev->dev, "hclge device initialization failed\n"); 2666 return ret; 2667 } 2668 2669 hdev = ae_dev->priv; 2670 timer_setup(&hdev->keep_alive_timer, hclgevf_keep_alive_timer, 0); 2671 INIT_WORK(&hdev->keep_alive_task, hclgevf_keep_alive_task); 2672 2673 return 0; 2674 } 2675 2676 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 2677 { 2678 struct hclgevf_dev *hdev = ae_dev->priv; 2679 2680 hclgevf_uninit_hdev(hdev); 2681 ae_dev->priv = NULL; 2682 } 2683 2684 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2685 { 2686 struct hnae3_handle *nic = &hdev->nic; 2687 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2688 2689 return min_t(u32, hdev->rss_size_max, 2690 hdev->num_tqps / kinfo->num_tc); 2691 } 2692 2693 /** 2694 * hclgevf_get_channels - Get the current channels enabled and max supported. 2695 * @handle: hardware information for network interface 2696 * @ch: ethtool channels structure 2697 * 2698 * We don't support separate tx and rx queues as channels. The other count 2699 * represents how many queues are being used for control. max_combined counts 2700 * how many queue pairs we can support. They may not be mapped 1 to 1 with 2701 * q_vectors since we support a lot more queue pairs than q_vectors. 2702 **/ 2703 static void hclgevf_get_channels(struct hnae3_handle *handle, 2704 struct ethtool_channels *ch) 2705 { 2706 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2707 2708 ch->max_combined = hclgevf_get_max_channels(hdev); 2709 ch->other_count = 0; 2710 ch->max_other = 0; 2711 ch->combined_count = handle->kinfo.rss_size; 2712 } 2713 2714 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 2715 u16 *alloc_tqps, u16 *max_rss_size) 2716 { 2717 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2718 2719 *alloc_tqps = hdev->num_tqps; 2720 *max_rss_size = hdev->rss_size_max; 2721 } 2722 2723 static int hclgevf_get_status(struct hnae3_handle *handle) 2724 { 2725 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2726 2727 return hdev->hw.mac.link; 2728 } 2729 2730 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 2731 u8 *auto_neg, u32 *speed, 2732 u8 *duplex) 2733 { 2734 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2735 2736 if (speed) 2737 *speed = hdev->hw.mac.speed; 2738 if (duplex) 2739 *duplex = hdev->hw.mac.duplex; 2740 if (auto_neg) 2741 *auto_neg = AUTONEG_DISABLE; 2742 } 2743 2744 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 2745 u8 duplex) 2746 { 2747 hdev->hw.mac.speed = speed; 2748 hdev->hw.mac.duplex = duplex; 2749 } 2750 2751 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 2752 { 2753 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2754 2755 return hclgevf_config_gro(hdev, enable); 2756 } 2757 2758 static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 2759 u8 *module_type) 2760 { 2761 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2762 2763 if (media_type) 2764 *media_type = hdev->hw.mac.media_type; 2765 2766 if (module_type) 2767 *module_type = hdev->hw.mac.module_type; 2768 } 2769 2770 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 2771 { 2772 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2773 2774 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 2775 } 2776 2777 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 2778 { 2779 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2780 2781 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2782 } 2783 2784 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 2785 { 2786 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2787 2788 return hdev->rst_stats.hw_rst_done_cnt; 2789 } 2790 2791 static void hclgevf_get_link_mode(struct hnae3_handle *handle, 2792 unsigned long *supported, 2793 unsigned long *advertising) 2794 { 2795 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2796 2797 *supported = hdev->hw.mac.supported; 2798 *advertising = hdev->hw.mac.advertising; 2799 } 2800 2801 #define MAX_SEPARATE_NUM 4 2802 #define SEPARATOR_VALUE 0xFFFFFFFF 2803 #define REG_NUM_PER_LINE 4 2804 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 2805 2806 static int hclgevf_get_regs_len(struct hnae3_handle *handle) 2807 { 2808 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 2809 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2810 2811 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 2812 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 2813 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 2814 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 2815 2816 return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 2817 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 2818 } 2819 2820 static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 2821 void *data) 2822 { 2823 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2824 int i, j, reg_um, separator_num; 2825 u32 *reg = data; 2826 2827 *version = hdev->fw_version; 2828 2829 /* fetching per-VF registers values from VF PCIe register space */ 2830 reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 2831 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2832 for (i = 0; i < reg_um; i++) 2833 *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 2834 for (i = 0; i < separator_num; i++) 2835 *reg++ = SEPARATOR_VALUE; 2836 2837 reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 2838 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2839 for (i = 0; i < reg_um; i++) 2840 *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 2841 for (i = 0; i < separator_num; i++) 2842 *reg++ = SEPARATOR_VALUE; 2843 2844 reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 2845 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2846 for (j = 0; j < hdev->num_tqps; j++) { 2847 for (i = 0; i < reg_um; i++) 2848 *reg++ = hclgevf_read_dev(&hdev->hw, 2849 ring_reg_addr_list[i] + 2850 0x200 * j); 2851 for (i = 0; i < separator_num; i++) 2852 *reg++ = SEPARATOR_VALUE; 2853 } 2854 2855 reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 2856 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2857 for (j = 0; j < hdev->num_msi_used - 1; j++) { 2858 for (i = 0; i < reg_um; i++) 2859 *reg++ = hclgevf_read_dev(&hdev->hw, 2860 tqp_intr_reg_addr_list[i] + 2861 4 * j); 2862 for (i = 0; i < separator_num; i++) 2863 *reg++ = SEPARATOR_VALUE; 2864 } 2865 } 2866 2867 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 2868 u8 *port_base_vlan_info, u8 data_size) 2869 { 2870 struct hnae3_handle *nic = &hdev->nic; 2871 2872 rtnl_lock(); 2873 hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 2874 rtnl_unlock(); 2875 2876 /* send msg to PF and wait update port based vlan info */ 2877 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 2878 HCLGE_MBX_PORT_BASE_VLAN_CFG, 2879 port_base_vlan_info, data_size, 2880 false, NULL, 0); 2881 2882 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 2883 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 2884 else 2885 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 2886 2887 rtnl_lock(); 2888 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 2889 rtnl_unlock(); 2890 } 2891 2892 static const struct hnae3_ae_ops hclgevf_ops = { 2893 .init_ae_dev = hclgevf_init_ae_dev, 2894 .uninit_ae_dev = hclgevf_uninit_ae_dev, 2895 .flr_prepare = hclgevf_flr_prepare, 2896 .flr_done = hclgevf_flr_done, 2897 .init_client_instance = hclgevf_init_client_instance, 2898 .uninit_client_instance = hclgevf_uninit_client_instance, 2899 .start = hclgevf_ae_start, 2900 .stop = hclgevf_ae_stop, 2901 .client_start = hclgevf_client_start, 2902 .client_stop = hclgevf_client_stop, 2903 .map_ring_to_vector = hclgevf_map_ring_to_vector, 2904 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 2905 .get_vector = hclgevf_get_vector, 2906 .put_vector = hclgevf_put_vector, 2907 .reset_queue = hclgevf_reset_tqp, 2908 .get_mac_addr = hclgevf_get_mac_addr, 2909 .set_mac_addr = hclgevf_set_mac_addr, 2910 .add_uc_addr = hclgevf_add_uc_addr, 2911 .rm_uc_addr = hclgevf_rm_uc_addr, 2912 .add_mc_addr = hclgevf_add_mc_addr, 2913 .rm_mc_addr = hclgevf_rm_mc_addr, 2914 .get_stats = hclgevf_get_stats, 2915 .update_stats = hclgevf_update_stats, 2916 .get_strings = hclgevf_get_strings, 2917 .get_sset_count = hclgevf_get_sset_count, 2918 .get_rss_key_size = hclgevf_get_rss_key_size, 2919 .get_rss_indir_size = hclgevf_get_rss_indir_size, 2920 .get_rss = hclgevf_get_rss, 2921 .set_rss = hclgevf_set_rss, 2922 .get_rss_tuple = hclgevf_get_rss_tuple, 2923 .set_rss_tuple = hclgevf_set_rss_tuple, 2924 .get_tc_size = hclgevf_get_tc_size, 2925 .get_fw_version = hclgevf_get_fw_version, 2926 .set_vlan_filter = hclgevf_set_vlan_filter, 2927 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 2928 .reset_event = hclgevf_reset_event, 2929 .set_default_reset_request = hclgevf_set_def_reset_request, 2930 .get_channels = hclgevf_get_channels, 2931 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 2932 .get_regs_len = hclgevf_get_regs_len, 2933 .get_regs = hclgevf_get_regs, 2934 .get_status = hclgevf_get_status, 2935 .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 2936 .get_media_type = hclgevf_get_media_type, 2937 .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 2938 .ae_dev_resetting = hclgevf_ae_dev_resetting, 2939 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 2940 .set_gro_en = hclgevf_gro_en, 2941 .set_mtu = hclgevf_set_mtu, 2942 .get_global_queue_id = hclgevf_get_qid_global, 2943 .set_timer_task = hclgevf_set_timer_task, 2944 .get_link_mode = hclgevf_get_link_mode, 2945 }; 2946 2947 static struct hnae3_ae_algo ae_algovf = { 2948 .ops = &hclgevf_ops, 2949 .pdev_id_table = ae_algovf_pci_tbl, 2950 }; 2951 2952 static int hclgevf_init(void) 2953 { 2954 pr_info("%s is initializing\n", HCLGEVF_NAME); 2955 2956 hnae3_register_ae_algo(&ae_algovf); 2957 2958 return 0; 2959 } 2960 2961 static void hclgevf_exit(void) 2962 { 2963 hnae3_unregister_ae_algo(&ae_algovf); 2964 } 2965 module_init(hclgevf_init); 2966 module_exit(hclgevf_exit); 2967 2968 MODULE_LICENSE("GPL"); 2969 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 2970 MODULE_DESCRIPTION("HCLGEVF Driver"); 2971 MODULE_VERSION(HCLGEVF_MOD_VERSION); 2972