1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include "hclgevf_cmd.h" 6 #include "hclgevf_main.h" 7 #include "hclge_mbx.h" 8 #include "hnae3.h" 9 10 #define HCLGEVF_NAME "hclgevf" 11 12 static struct hnae3_ae_algo ae_algovf; 13 14 static const struct pci_device_id ae_algovf_pci_tbl[] = { 15 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 16 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 17 /* required last entry */ 18 {0, } 19 }; 20 21 static inline struct hclgevf_dev *hclgevf_ae_get_hdev( 22 struct hnae3_handle *handle) 23 { 24 return container_of(handle, struct hclgevf_dev, nic); 25 } 26 27 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 28 { 29 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 30 struct hnae3_queue *queue; 31 struct hclgevf_desc desc; 32 struct hclgevf_tqp *tqp; 33 int status; 34 int i; 35 36 for (i = 0; i < hdev->num_tqps; i++) { 37 queue = handle->kinfo.tqp[i]; 38 tqp = container_of(queue, struct hclgevf_tqp, q); 39 hclgevf_cmd_setup_basic_desc(&desc, 40 HCLGEVF_OPC_QUERY_RX_STATUS, 41 true); 42 43 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 44 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 45 if (status) { 46 dev_err(&hdev->pdev->dev, 47 "Query tqp stat fail, status = %d,queue = %d\n", 48 status, i); 49 return status; 50 } 51 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 52 le32_to_cpu(desc.data[1]); 53 54 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 55 true); 56 57 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 58 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 59 if (status) { 60 dev_err(&hdev->pdev->dev, 61 "Query tqp stat fail, status = %d,queue = %d\n", 62 status, i); 63 return status; 64 } 65 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 66 le32_to_cpu(desc.data[1]); 67 } 68 69 return 0; 70 } 71 72 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 73 { 74 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 75 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 76 struct hclgevf_tqp *tqp; 77 u64 *buff = data; 78 int i; 79 80 for (i = 0; i < hdev->num_tqps; i++) { 81 tqp = container_of(handle->kinfo.tqp[i], struct hclgevf_tqp, q); 82 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 83 } 84 for (i = 0; i < kinfo->num_tqps; i++) { 85 tqp = container_of(handle->kinfo.tqp[i], struct hclgevf_tqp, q); 86 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 87 } 88 89 return buff; 90 } 91 92 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 93 { 94 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 95 96 return hdev->num_tqps * 2; 97 } 98 99 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 100 { 101 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 102 u8 *buff = data; 103 int i = 0; 104 105 for (i = 0; i < hdev->num_tqps; i++) { 106 struct hclgevf_tqp *tqp = container_of(handle->kinfo.tqp[i], 107 struct hclgevf_tqp, q); 108 snprintf(buff, ETH_GSTRING_LEN, "txq#%d_pktnum_rcd", 109 tqp->index); 110 buff += ETH_GSTRING_LEN; 111 } 112 113 for (i = 0; i < hdev->num_tqps; i++) { 114 struct hclgevf_tqp *tqp = container_of(handle->kinfo.tqp[i], 115 struct hclgevf_tqp, q); 116 snprintf(buff, ETH_GSTRING_LEN, "rxq#%d_pktnum_rcd", 117 tqp->index); 118 buff += ETH_GSTRING_LEN; 119 } 120 121 return buff; 122 } 123 124 static void hclgevf_update_stats(struct hnae3_handle *handle, 125 struct net_device_stats *net_stats) 126 { 127 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 128 int status; 129 130 status = hclgevf_tqps_update_stats(handle); 131 if (status) 132 dev_err(&hdev->pdev->dev, 133 "VF update of TQPS stats fail, status = %d.\n", 134 status); 135 } 136 137 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 138 { 139 if (strset == ETH_SS_TEST) 140 return -EOPNOTSUPP; 141 else if (strset == ETH_SS_STATS) 142 return hclgevf_tqps_get_sset_count(handle, strset); 143 144 return 0; 145 } 146 147 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 148 u8 *data) 149 { 150 u8 *p = (char *)data; 151 152 if (strset == ETH_SS_STATS) 153 p = hclgevf_tqps_get_strings(handle, p); 154 } 155 156 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 157 { 158 hclgevf_tqps_get_stats(handle, data); 159 } 160 161 static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 162 { 163 u8 resp_msg; 164 int status; 165 166 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 167 true, &resp_msg, sizeof(u8)); 168 if (status) { 169 dev_err(&hdev->pdev->dev, 170 "VF request to get TC info from PF failed %d", 171 status); 172 return status; 173 } 174 175 hdev->hw_tc_map = resp_msg; 176 177 return 0; 178 } 179 180 static int hclge_get_queue_info(struct hclgevf_dev *hdev) 181 { 182 #define HCLGEVF_TQPS_RSS_INFO_LEN 8 183 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 184 int status; 185 186 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 187 true, resp_msg, 188 HCLGEVF_TQPS_RSS_INFO_LEN); 189 if (status) { 190 dev_err(&hdev->pdev->dev, 191 "VF request to get tqp info from PF failed %d", 192 status); 193 return status; 194 } 195 196 memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 197 memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 198 memcpy(&hdev->num_desc, &resp_msg[4], sizeof(u16)); 199 memcpy(&hdev->rx_buf_len, &resp_msg[6], sizeof(u16)); 200 201 return 0; 202 } 203 204 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 205 { 206 struct hclgevf_tqp *tqp; 207 int i; 208 209 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 210 sizeof(struct hclgevf_tqp), GFP_KERNEL); 211 if (!hdev->htqp) 212 return -ENOMEM; 213 214 tqp = hdev->htqp; 215 216 for (i = 0; i < hdev->num_tqps; i++) { 217 tqp->dev = &hdev->pdev->dev; 218 tqp->index = i; 219 220 tqp->q.ae_algo = &ae_algovf; 221 tqp->q.buf_size = hdev->rx_buf_len; 222 tqp->q.desc_num = hdev->num_desc; 223 tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 224 i * HCLGEVF_TQP_REG_SIZE; 225 226 tqp++; 227 } 228 229 return 0; 230 } 231 232 static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 233 { 234 struct hnae3_handle *nic = &hdev->nic; 235 struct hnae3_knic_private_info *kinfo; 236 u16 new_tqps = hdev->num_tqps; 237 int i; 238 239 kinfo = &nic->kinfo; 240 kinfo->num_tc = 0; 241 kinfo->num_desc = hdev->num_desc; 242 kinfo->rx_buf_len = hdev->rx_buf_len; 243 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 244 if (hdev->hw_tc_map & BIT(i)) 245 kinfo->num_tc++; 246 247 kinfo->rss_size 248 = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 249 new_tqps = kinfo->rss_size * kinfo->num_tc; 250 kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 251 252 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 253 sizeof(struct hnae3_queue *), GFP_KERNEL); 254 if (!kinfo->tqp) 255 return -ENOMEM; 256 257 for (i = 0; i < kinfo->num_tqps; i++) { 258 hdev->htqp[i].q.handle = &hdev->nic; 259 hdev->htqp[i].q.tqp_index = i; 260 kinfo->tqp[i] = &hdev->htqp[i].q; 261 } 262 263 return 0; 264 } 265 266 static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 267 { 268 int status; 269 u8 resp_msg; 270 271 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 272 0, false, &resp_msg, sizeof(u8)); 273 if (status) 274 dev_err(&hdev->pdev->dev, 275 "VF failed to fetch link status(%d) from PF", status); 276 } 277 278 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 279 { 280 struct hnae3_handle *handle = &hdev->nic; 281 struct hnae3_client *client; 282 283 client = handle->client; 284 285 if (link_state != hdev->hw.mac.link) { 286 client->ops->link_status_change(handle, !!link_state); 287 hdev->hw.mac.link = link_state; 288 } 289 } 290 291 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 292 { 293 struct hnae3_handle *nic = &hdev->nic; 294 int ret; 295 296 nic->ae_algo = &ae_algovf; 297 nic->pdev = hdev->pdev; 298 nic->numa_node_mask = hdev->numa_node_mask; 299 nic->flags |= HNAE3_SUPPORT_VF; 300 301 if (hdev->ae_dev->dev_type != HNAE3_DEV_KNIC) { 302 dev_err(&hdev->pdev->dev, "unsupported device type %d\n", 303 hdev->ae_dev->dev_type); 304 return -EINVAL; 305 } 306 307 ret = hclgevf_knic_setup(hdev); 308 if (ret) 309 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 310 ret); 311 return ret; 312 } 313 314 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 315 { 316 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 317 hdev->num_msi_left += 1; 318 hdev->num_msi_used -= 1; 319 } 320 321 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 322 struct hnae3_vector_info *vector_info) 323 { 324 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 325 struct hnae3_vector_info *vector = vector_info; 326 int alloc = 0; 327 int i, j; 328 329 vector_num = min(hdev->num_msi_left, vector_num); 330 331 for (j = 0; j < vector_num; j++) { 332 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 333 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 334 vector->vector = pci_irq_vector(hdev->pdev, i); 335 vector->io_addr = hdev->hw.io_base + 336 HCLGEVF_VECTOR_REG_BASE + 337 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 338 hdev->vector_status[i] = 0; 339 hdev->vector_irq[i] = vector->vector; 340 341 vector++; 342 alloc++; 343 344 break; 345 } 346 } 347 } 348 hdev->num_msi_left -= alloc; 349 hdev->num_msi_used += alloc; 350 351 return alloc; 352 } 353 354 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 355 { 356 int i; 357 358 for (i = 0; i < hdev->num_msi; i++) 359 if (vector == hdev->vector_irq[i]) 360 return i; 361 362 return -EINVAL; 363 } 364 365 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 366 { 367 return HCLGEVF_RSS_KEY_SIZE; 368 } 369 370 static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 371 { 372 return HCLGEVF_RSS_IND_TBL_SIZE; 373 } 374 375 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 376 { 377 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 378 struct hclgevf_rss_indirection_table_cmd *req; 379 struct hclgevf_desc desc; 380 int status; 381 int i, j; 382 383 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 384 385 for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 386 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 387 false); 388 req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 389 req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 390 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 391 req->rss_result[j] = 392 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 393 394 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 395 if (status) { 396 dev_err(&hdev->pdev->dev, 397 "VF failed(=%d) to set RSS indirection table\n", 398 status); 399 return status; 400 } 401 } 402 403 return 0; 404 } 405 406 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 407 { 408 struct hclgevf_rss_tc_mode_cmd *req; 409 u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 410 u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 411 u16 tc_size[HCLGEVF_MAX_TC_NUM]; 412 struct hclgevf_desc desc; 413 u16 roundup_size; 414 int status; 415 int i; 416 417 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 418 419 roundup_size = roundup_pow_of_two(rss_size); 420 roundup_size = ilog2(roundup_size); 421 422 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 423 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 424 tc_size[i] = roundup_size; 425 tc_offset[i] = rss_size * i; 426 } 427 428 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 429 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 430 hnae_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 431 (tc_valid[i] & 0x1)); 432 hnae_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 433 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 434 hnae_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 435 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 436 } 437 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 438 if (status) 439 dev_err(&hdev->pdev->dev, 440 "VF failed(=%d) to set rss tc mode\n", status); 441 442 return status; 443 } 444 445 static int hclgevf_get_rss_hw_cfg(struct hnae3_handle *handle, u8 *hash, 446 u8 *key) 447 { 448 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 449 struct hclgevf_rss_config_cmd *req; 450 int lkup_times = key ? 3 : 1; 451 struct hclgevf_desc desc; 452 int key_offset; 453 int key_size; 454 int status; 455 456 req = (struct hclgevf_rss_config_cmd *)desc.data; 457 lkup_times = (lkup_times == 3) ? 3 : ((hash) ? 1 : 0); 458 459 for (key_offset = 0; key_offset < lkup_times; key_offset++) { 460 hclgevf_cmd_setup_basic_desc(&desc, 461 HCLGEVF_OPC_RSS_GENERIC_CONFIG, 462 true); 463 req->hash_config |= (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET); 464 465 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 466 if (status) { 467 dev_err(&hdev->pdev->dev, 468 "failed to get hardware RSS cfg, status = %d\n", 469 status); 470 return status; 471 } 472 473 if (key_offset == 2) 474 key_size = 475 HCLGEVF_RSS_KEY_SIZE - HCLGEVF_RSS_HASH_KEY_NUM * 2; 476 else 477 key_size = HCLGEVF_RSS_HASH_KEY_NUM; 478 479 if (key) 480 memcpy(key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, 481 req->hash_key, 482 key_size); 483 } 484 485 if (hash) { 486 if ((req->hash_config & 0xf) == HCLGEVF_RSS_HASH_ALGO_TOEPLITZ) 487 *hash = ETH_RSS_HASH_TOP; 488 else 489 *hash = ETH_RSS_HASH_UNKNOWN; 490 } 491 492 return 0; 493 } 494 495 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 496 u8 *hfunc) 497 { 498 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 499 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 500 int i; 501 502 if (indir) 503 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 504 indir[i] = rss_cfg->rss_indirection_tbl[i]; 505 506 return hclgevf_get_rss_hw_cfg(handle, hfunc, key); 507 } 508 509 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 510 const u8 *key, const u8 hfunc) 511 { 512 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 513 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 514 int i; 515 516 /* update the shadow RSS table with user specified qids */ 517 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 518 rss_cfg->rss_indirection_tbl[i] = indir[i]; 519 520 /* update the hardware */ 521 return hclgevf_set_rss_indir_table(hdev); 522 } 523 524 static int hclgevf_get_tc_size(struct hnae3_handle *handle) 525 { 526 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 527 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 528 529 return rss_cfg->rss_size; 530 } 531 532 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 533 int vector, 534 struct hnae3_ring_chain_node *ring_chain) 535 { 536 #define HCLGEVF_RING_NODE_VARIABLE_NUM 3 537 #define HCLGEVF_RING_MAP_MBX_BASIC_MSG_NUM 3 538 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 539 struct hnae3_ring_chain_node *node; 540 struct hclge_mbx_vf_to_pf_cmd *req; 541 struct hclgevf_desc desc; 542 int i, vector_id; 543 int status; 544 u8 type; 545 546 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 547 vector_id = hclgevf_get_vector_index(hdev, vector); 548 if (vector_id < 0) { 549 dev_err(&handle->pdev->dev, 550 "Get vector index fail. ret =%d\n", vector_id); 551 return vector_id; 552 } 553 554 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 555 type = en ? 556 HCLGE_MBX_MAP_RING_TO_VECTOR : HCLGE_MBX_UNMAP_RING_TO_VECTOR; 557 req->msg[0] = type; 558 req->msg[1] = vector_id; /* vector_id should be id in VF */ 559 560 i = 0; 561 for (node = ring_chain; node; node = node->next) { 562 i++; 563 /* msg[2] is cause num */ 564 req->msg[HCLGEVF_RING_NODE_VARIABLE_NUM * i] = 565 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B); 566 req->msg[HCLGEVF_RING_NODE_VARIABLE_NUM * i + 1] = 567 node->tqp_index; 568 req->msg[HCLGEVF_RING_NODE_VARIABLE_NUM * i + 2] = 569 hnae_get_field(node->int_gl_idx, 570 HNAE3_RING_GL_IDX_M, 571 HNAE3_RING_GL_IDX_S); 572 573 if (i == (HCLGE_MBX_VF_MSG_DATA_NUM - 574 HCLGEVF_RING_MAP_MBX_BASIC_MSG_NUM) / 575 HCLGEVF_RING_NODE_VARIABLE_NUM) { 576 req->msg[2] = i; 577 578 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 579 if (status) { 580 dev_err(&hdev->pdev->dev, 581 "Map TQP fail, status is %d.\n", 582 status); 583 return status; 584 } 585 i = 0; 586 hclgevf_cmd_setup_basic_desc(&desc, 587 HCLGEVF_OPC_MBX_VF_TO_PF, 588 false); 589 req->msg[0] = type; 590 req->msg[1] = vector_id; 591 } 592 } 593 594 if (i > 0) { 595 req->msg[2] = i; 596 597 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 598 if (status) { 599 dev_err(&hdev->pdev->dev, 600 "Map TQP fail, status is %d.\n", status); 601 return status; 602 } 603 } 604 605 return 0; 606 } 607 608 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 609 struct hnae3_ring_chain_node *ring_chain) 610 { 611 return hclgevf_bind_ring_to_vector(handle, true, vector, ring_chain); 612 } 613 614 static int hclgevf_unmap_ring_from_vector( 615 struct hnae3_handle *handle, 616 int vector, 617 struct hnae3_ring_chain_node *ring_chain) 618 { 619 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 620 int ret, vector_id; 621 622 vector_id = hclgevf_get_vector_index(hdev, vector); 623 if (vector_id < 0) { 624 dev_err(&handle->pdev->dev, 625 "Get vector index fail. ret =%d\n", vector_id); 626 return vector_id; 627 } 628 629 ret = hclgevf_bind_ring_to_vector(handle, false, vector, ring_chain); 630 if (ret) 631 dev_err(&handle->pdev->dev, 632 "Unmap ring from vector fail. vector=%d, ret =%d\n", 633 vector_id, 634 ret); 635 636 return ret; 637 } 638 639 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 640 { 641 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 642 643 hclgevf_free_vector(hdev, vector); 644 645 return 0; 646 } 647 648 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, u32 en) 649 { 650 struct hclge_mbx_vf_to_pf_cmd *req; 651 struct hclgevf_desc desc; 652 int status; 653 654 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 655 656 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 657 req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 658 req->msg[1] = en; 659 660 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 661 if (status) 662 dev_err(&hdev->pdev->dev, 663 "Set promisc mode fail, status is %d.\n", status); 664 665 return status; 666 } 667 668 static void hclgevf_set_promisc_mode(struct hnae3_handle *handle, u32 en) 669 { 670 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 671 672 hclgevf_cmd_set_promisc_mode(hdev, en); 673 } 674 675 static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, int tqp_id, 676 int stream_id, bool enable) 677 { 678 struct hclgevf_cfg_com_tqp_queue_cmd *req; 679 struct hclgevf_desc desc; 680 int status; 681 682 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 683 684 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 685 false); 686 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 687 req->stream_id = cpu_to_le16(stream_id); 688 req->enable |= enable << HCLGEVF_TQP_ENABLE_B; 689 690 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 691 if (status) 692 dev_err(&hdev->pdev->dev, 693 "TQP enable fail, status =%d.\n", status); 694 695 return status; 696 } 697 698 static int hclgevf_get_queue_id(struct hnae3_queue *queue) 699 { 700 struct hclgevf_tqp *tqp = container_of(queue, struct hclgevf_tqp, q); 701 702 return tqp->index; 703 } 704 705 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 706 { 707 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 708 struct hnae3_queue *queue; 709 struct hclgevf_tqp *tqp; 710 int i; 711 712 for (i = 0; i < hdev->num_tqps; i++) { 713 queue = handle->kinfo.tqp[i]; 714 tqp = container_of(queue, struct hclgevf_tqp, q); 715 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 716 } 717 } 718 719 static int hclgevf_cfg_func_mta_filter(struct hnae3_handle *handle, bool en) 720 { 721 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 722 u8 msg[2] = {0}; 723 724 msg[0] = en; 725 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 726 HCLGE_MBX_MAC_VLAN_MC_FUNC_MTA_ENABLE, 727 msg, 1, false, NULL, 0); 728 } 729 730 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 731 { 732 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 733 734 ether_addr_copy(p, hdev->hw.mac.mac_addr); 735 } 736 737 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p) 738 { 739 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 740 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 741 u8 *new_mac_addr = (u8 *)p; 742 u8 msg_data[ETH_ALEN * 2]; 743 int status; 744 745 ether_addr_copy(msg_data, new_mac_addr); 746 ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 747 748 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 749 HCLGE_MBX_MAC_VLAN_UC_MODIFY, 750 msg_data, ETH_ALEN * 2, 751 false, NULL, 0); 752 if (!status) 753 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 754 755 return status; 756 } 757 758 static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 759 const unsigned char *addr) 760 { 761 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 762 763 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 764 HCLGE_MBX_MAC_VLAN_UC_ADD, 765 addr, ETH_ALEN, false, NULL, 0); 766 } 767 768 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 769 const unsigned char *addr) 770 { 771 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 772 773 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 774 HCLGE_MBX_MAC_VLAN_UC_REMOVE, 775 addr, ETH_ALEN, false, NULL, 0); 776 } 777 778 static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 779 const unsigned char *addr) 780 { 781 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 782 783 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 784 HCLGE_MBX_MAC_VLAN_MC_ADD, 785 addr, ETH_ALEN, false, NULL, 0); 786 } 787 788 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 789 const unsigned char *addr) 790 { 791 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 792 793 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 794 HCLGE_MBX_MAC_VLAN_MC_REMOVE, 795 addr, ETH_ALEN, false, NULL, 0); 796 } 797 798 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 799 __be16 proto, u16 vlan_id, 800 bool is_kill) 801 { 802 #define HCLGEVF_VLAN_MBX_MSG_LEN 5 803 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 804 u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 805 806 if (vlan_id > 4095) 807 return -EINVAL; 808 809 if (proto != htons(ETH_P_8021Q)) 810 return -EPROTONOSUPPORT; 811 812 msg_data[0] = is_kill; 813 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 814 memcpy(&msg_data[3], &proto, sizeof(proto)); 815 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 816 HCLGE_MBX_VLAN_FILTER, msg_data, 817 HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 818 } 819 820 static void hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 821 { 822 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 823 u8 msg_data[2]; 824 825 memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 826 827 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 2, false, 828 NULL, 0); 829 } 830 831 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 832 { 833 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 834 835 return hdev->fw_version; 836 } 837 838 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 839 { 840 struct hclgevf_misc_vector *vector = &hdev->misc_vector; 841 842 vector->vector_irq = pci_irq_vector(hdev->pdev, 843 HCLGEVF_MISC_VECTOR_NUM); 844 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 845 /* vector status always valid for Vector 0 */ 846 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 847 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 848 849 hdev->num_msi_left -= 1; 850 hdev->num_msi_used += 1; 851 } 852 853 static void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 854 { 855 if (!test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state)) 856 schedule_work(&hdev->mbx_service_task); 857 } 858 859 static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 860 { 861 if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 862 !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 863 schedule_work(&hdev->service_task); 864 } 865 866 static void hclgevf_service_timer(struct timer_list *t) 867 { 868 struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 869 870 mod_timer(&hdev->service_timer, jiffies + 5 * HZ); 871 872 hclgevf_task_schedule(hdev); 873 } 874 875 static void hclgevf_mailbox_service_task(struct work_struct *work) 876 { 877 struct hclgevf_dev *hdev; 878 879 hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 880 881 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 882 return; 883 884 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 885 886 hclgevf_mbx_handler(hdev); 887 888 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 889 } 890 891 static void hclgevf_service_task(struct work_struct *work) 892 { 893 struct hclgevf_dev *hdev; 894 895 hdev = container_of(work, struct hclgevf_dev, service_task); 896 897 /* request the link status from the PF. PF would be able to tell VF 898 * about such updates in future so we might remove this later 899 */ 900 hclgevf_request_link_info(hdev); 901 902 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 903 } 904 905 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 906 { 907 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 908 } 909 910 static bool hclgevf_check_event_cause(struct hclgevf_dev *hdev, u32 *clearval) 911 { 912 u32 cmdq_src_reg; 913 914 /* fetch the events from their corresponding regs */ 915 cmdq_src_reg = hclgevf_read_dev(&hdev->hw, 916 HCLGEVF_VECTOR0_CMDQ_SRC_REG); 917 918 /* check for vector0 mailbox(=CMDQ RX) event source */ 919 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 920 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 921 *clearval = cmdq_src_reg; 922 return true; 923 } 924 925 dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 926 927 return false; 928 } 929 930 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 931 { 932 writel(en ? 1 : 0, vector->addr); 933 } 934 935 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 936 { 937 struct hclgevf_dev *hdev = data; 938 u32 clearval; 939 940 hclgevf_enable_vector(&hdev->misc_vector, false); 941 if (!hclgevf_check_event_cause(hdev, &clearval)) 942 goto skip_sched; 943 944 /* schedule the VF mailbox service task, if not already scheduled */ 945 hclgevf_mbx_task_schedule(hdev); 946 947 hclgevf_clear_event_cause(hdev, clearval); 948 949 skip_sched: 950 hclgevf_enable_vector(&hdev->misc_vector, true); 951 952 return IRQ_HANDLED; 953 } 954 955 static int hclgevf_configure(struct hclgevf_dev *hdev) 956 { 957 int ret; 958 959 /* get queue configuration from PF */ 960 ret = hclge_get_queue_info(hdev); 961 if (ret) 962 return ret; 963 /* get tc configuration from PF */ 964 return hclgevf_get_tc_info(hdev); 965 } 966 967 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 968 { 969 struct hnae3_handle *roce = &hdev->roce; 970 struct hnae3_handle *nic = &hdev->nic; 971 972 roce->rinfo.num_vectors = HCLGEVF_ROCEE_VECTOR_NUM; 973 974 if (hdev->num_msi_left < roce->rinfo.num_vectors || 975 hdev->num_msi_left == 0) 976 return -EINVAL; 977 978 roce->rinfo.base_vector = 979 hdev->vector_status[hdev->num_msi_used]; 980 981 roce->rinfo.netdev = nic->kinfo.netdev; 982 roce->rinfo.roce_io_base = hdev->hw.io_base; 983 984 roce->pdev = nic->pdev; 985 roce->ae_algo = nic->ae_algo; 986 roce->numa_node_mask = nic->numa_node_mask; 987 988 return 0; 989 } 990 991 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 992 { 993 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 994 int i, ret; 995 996 rss_cfg->rss_size = hdev->rss_size_max; 997 998 /* Initialize RSS indirect table for each vport */ 999 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 1000 rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max; 1001 1002 ret = hclgevf_set_rss_indir_table(hdev); 1003 if (ret) 1004 return ret; 1005 1006 return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max); 1007 } 1008 1009 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 1010 { 1011 /* other vlan config(like, VLAN TX/RX offload) would also be added 1012 * here later 1013 */ 1014 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 1015 false); 1016 } 1017 1018 static int hclgevf_ae_start(struct hnae3_handle *handle) 1019 { 1020 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1021 int i, queue_id; 1022 1023 for (i = 0; i < handle->kinfo.num_tqps; i++) { 1024 /* ring enable */ 1025 queue_id = hclgevf_get_queue_id(handle->kinfo.tqp[i]); 1026 if (queue_id < 0) { 1027 dev_warn(&hdev->pdev->dev, 1028 "Get invalid queue id, ignore it\n"); 1029 continue; 1030 } 1031 1032 hclgevf_tqp_enable(hdev, queue_id, 0, true); 1033 } 1034 1035 /* reset tqp stats */ 1036 hclgevf_reset_tqp_stats(handle); 1037 1038 hclgevf_request_link_info(hdev); 1039 1040 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1041 mod_timer(&hdev->service_timer, jiffies + HZ); 1042 1043 return 0; 1044 } 1045 1046 static void hclgevf_ae_stop(struct hnae3_handle *handle) 1047 { 1048 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1049 int i, queue_id; 1050 1051 for (i = 0; i < hdev->num_tqps; i++) { 1052 /* Ring disable */ 1053 queue_id = hclgevf_get_queue_id(handle->kinfo.tqp[i]); 1054 if (queue_id < 0) { 1055 dev_warn(&hdev->pdev->dev, 1056 "Get invalid queue id, ignore it\n"); 1057 continue; 1058 } 1059 1060 hclgevf_tqp_enable(hdev, queue_id, 0, false); 1061 } 1062 1063 /* reset tqp stats */ 1064 hclgevf_reset_tqp_stats(handle); 1065 } 1066 1067 static void hclgevf_state_init(struct hclgevf_dev *hdev) 1068 { 1069 /* setup tasks for the MBX */ 1070 INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 1071 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1072 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1073 1074 /* setup tasks for service timer */ 1075 timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 1076 1077 INIT_WORK(&hdev->service_task, hclgevf_service_task); 1078 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1079 1080 mutex_init(&hdev->mbx_resp.mbx_mutex); 1081 1082 /* bring the device down */ 1083 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1084 } 1085 1086 static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 1087 { 1088 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1089 1090 if (hdev->service_timer.function) 1091 del_timer_sync(&hdev->service_timer); 1092 if (hdev->service_task.func) 1093 cancel_work_sync(&hdev->service_task); 1094 if (hdev->mbx_service_task.func) 1095 cancel_work_sync(&hdev->mbx_service_task); 1096 1097 mutex_destroy(&hdev->mbx_resp.mbx_mutex); 1098 } 1099 1100 static int hclgevf_init_msi(struct hclgevf_dev *hdev) 1101 { 1102 struct pci_dev *pdev = hdev->pdev; 1103 int vectors; 1104 int i; 1105 1106 hdev->num_msi = HCLGEVF_MAX_VF_VECTOR_NUM; 1107 1108 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 1109 PCI_IRQ_MSI | PCI_IRQ_MSIX); 1110 if (vectors < 0) { 1111 dev_err(&pdev->dev, 1112 "failed(%d) to allocate MSI/MSI-X vectors\n", 1113 vectors); 1114 return vectors; 1115 } 1116 if (vectors < hdev->num_msi) 1117 dev_warn(&hdev->pdev->dev, 1118 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 1119 hdev->num_msi, vectors); 1120 1121 hdev->num_msi = vectors; 1122 hdev->num_msi_left = vectors; 1123 hdev->base_msi_vector = pdev->irq; 1124 1125 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 1126 sizeof(u16), GFP_KERNEL); 1127 if (!hdev->vector_status) { 1128 pci_free_irq_vectors(pdev); 1129 return -ENOMEM; 1130 } 1131 1132 for (i = 0; i < hdev->num_msi; i++) 1133 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 1134 1135 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 1136 sizeof(int), GFP_KERNEL); 1137 if (!hdev->vector_irq) { 1138 pci_free_irq_vectors(pdev); 1139 return -ENOMEM; 1140 } 1141 1142 return 0; 1143 } 1144 1145 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 1146 { 1147 struct pci_dev *pdev = hdev->pdev; 1148 1149 pci_free_irq_vectors(pdev); 1150 } 1151 1152 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 1153 { 1154 int ret = 0; 1155 1156 hclgevf_get_misc_vector(hdev); 1157 1158 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 1159 0, "hclgevf_cmd", hdev); 1160 if (ret) { 1161 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 1162 hdev->misc_vector.vector_irq); 1163 return ret; 1164 } 1165 1166 /* enable misc. vector(vector 0) */ 1167 hclgevf_enable_vector(&hdev->misc_vector, true); 1168 1169 return ret; 1170 } 1171 1172 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 1173 { 1174 /* disable misc vector(vector 0) */ 1175 hclgevf_enable_vector(&hdev->misc_vector, false); 1176 free_irq(hdev->misc_vector.vector_irq, hdev); 1177 hclgevf_free_vector(hdev, 0); 1178 } 1179 1180 static int hclgevf_init_instance(struct hclgevf_dev *hdev, 1181 struct hnae3_client *client) 1182 { 1183 int ret; 1184 1185 switch (client->type) { 1186 case HNAE3_CLIENT_KNIC: 1187 hdev->nic_client = client; 1188 hdev->nic.client = client; 1189 1190 ret = client->ops->init_instance(&hdev->nic); 1191 if (ret) 1192 return ret; 1193 1194 if (hdev->roce_client && hnae3_dev_roce_supported(hdev)) { 1195 struct hnae3_client *rc = hdev->roce_client; 1196 1197 ret = hclgevf_init_roce_base_info(hdev); 1198 if (ret) 1199 return ret; 1200 ret = rc->ops->init_instance(&hdev->roce); 1201 if (ret) 1202 return ret; 1203 } 1204 break; 1205 case HNAE3_CLIENT_UNIC: 1206 hdev->nic_client = client; 1207 hdev->nic.client = client; 1208 1209 ret = client->ops->init_instance(&hdev->nic); 1210 if (ret) 1211 return ret; 1212 break; 1213 case HNAE3_CLIENT_ROCE: 1214 hdev->roce_client = client; 1215 hdev->roce.client = client; 1216 1217 if (hdev->roce_client && hnae3_dev_roce_supported(hdev)) { 1218 ret = hclgevf_init_roce_base_info(hdev); 1219 if (ret) 1220 return ret; 1221 1222 ret = client->ops->init_instance(&hdev->roce); 1223 if (ret) 1224 return ret; 1225 } 1226 } 1227 1228 return 0; 1229 } 1230 1231 static void hclgevf_uninit_instance(struct hclgevf_dev *hdev, 1232 struct hnae3_client *client) 1233 { 1234 /* un-init roce, if it exists */ 1235 if (hdev->roce_client) 1236 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 1237 1238 /* un-init nic/unic, if this was not called by roce client */ 1239 if ((client->ops->uninit_instance) && 1240 (client->type != HNAE3_CLIENT_ROCE)) 1241 client->ops->uninit_instance(&hdev->nic, 0); 1242 } 1243 1244 static int hclgevf_register_client(struct hnae3_client *client, 1245 struct hnae3_ae_dev *ae_dev) 1246 { 1247 struct hclgevf_dev *hdev = ae_dev->priv; 1248 1249 return hclgevf_init_instance(hdev, client); 1250 } 1251 1252 static void hclgevf_unregister_client(struct hnae3_client *client, 1253 struct hnae3_ae_dev *ae_dev) 1254 { 1255 struct hclgevf_dev *hdev = ae_dev->priv; 1256 1257 hclgevf_uninit_instance(hdev, client); 1258 } 1259 1260 static int hclgevf_pci_init(struct hclgevf_dev *hdev) 1261 { 1262 struct pci_dev *pdev = hdev->pdev; 1263 struct hclgevf_hw *hw; 1264 int ret; 1265 1266 ret = pci_enable_device(pdev); 1267 if (ret) { 1268 dev_err(&pdev->dev, "failed to enable PCI device\n"); 1269 goto err_no_drvdata; 1270 } 1271 1272 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 1273 if (ret) { 1274 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 1275 goto err_disable_device; 1276 } 1277 1278 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 1279 if (ret) { 1280 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 1281 goto err_disable_device; 1282 } 1283 1284 pci_set_master(pdev); 1285 hw = &hdev->hw; 1286 hw->hdev = hdev; 1287 hw->io_base = pci_iomap(pdev, 2, 0); 1288 if (!hw->io_base) { 1289 dev_err(&pdev->dev, "can't map configuration register space\n"); 1290 ret = -ENOMEM; 1291 goto err_clr_master; 1292 } 1293 1294 return 0; 1295 1296 err_clr_master: 1297 pci_clear_master(pdev); 1298 pci_release_regions(pdev); 1299 err_disable_device: 1300 pci_disable_device(pdev); 1301 err_no_drvdata: 1302 pci_set_drvdata(pdev, NULL); 1303 return ret; 1304 } 1305 1306 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 1307 { 1308 struct pci_dev *pdev = hdev->pdev; 1309 1310 pci_iounmap(pdev, hdev->hw.io_base); 1311 pci_clear_master(pdev); 1312 pci_release_regions(pdev); 1313 pci_disable_device(pdev); 1314 pci_set_drvdata(pdev, NULL); 1315 } 1316 1317 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 1318 { 1319 struct pci_dev *pdev = ae_dev->pdev; 1320 struct hclgevf_dev *hdev; 1321 int ret; 1322 1323 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 1324 if (!hdev) 1325 return -ENOMEM; 1326 1327 hdev->pdev = pdev; 1328 hdev->ae_dev = ae_dev; 1329 ae_dev->priv = hdev; 1330 1331 ret = hclgevf_pci_init(hdev); 1332 if (ret) { 1333 dev_err(&pdev->dev, "PCI initialization failed\n"); 1334 return ret; 1335 } 1336 1337 ret = hclgevf_init_msi(hdev); 1338 if (ret) { 1339 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 1340 goto err_irq_init; 1341 } 1342 1343 hclgevf_state_init(hdev); 1344 1345 ret = hclgevf_misc_irq_init(hdev); 1346 if (ret) { 1347 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 1348 ret); 1349 goto err_misc_irq_init; 1350 } 1351 1352 ret = hclgevf_cmd_init(hdev); 1353 if (ret) 1354 goto err_cmd_init; 1355 1356 ret = hclgevf_configure(hdev); 1357 if (ret) { 1358 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 1359 goto err_config; 1360 } 1361 1362 ret = hclgevf_alloc_tqps(hdev); 1363 if (ret) { 1364 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 1365 goto err_config; 1366 } 1367 1368 ret = hclgevf_set_handle_info(hdev); 1369 if (ret) { 1370 dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 1371 goto err_config; 1372 } 1373 1374 /* Initialize VF's MTA */ 1375 hdev->accept_mta_mc = true; 1376 ret = hclgevf_cfg_func_mta_filter(&hdev->nic, hdev->accept_mta_mc); 1377 if (ret) { 1378 dev_err(&hdev->pdev->dev, 1379 "failed(%d) to set mta filter mode\n", ret); 1380 goto err_config; 1381 } 1382 1383 /* Initialize RSS for this VF */ 1384 ret = hclgevf_rss_init_hw(hdev); 1385 if (ret) { 1386 dev_err(&hdev->pdev->dev, 1387 "failed(%d) to initialize RSS\n", ret); 1388 goto err_config; 1389 } 1390 1391 ret = hclgevf_init_vlan_config(hdev); 1392 if (ret) { 1393 dev_err(&hdev->pdev->dev, 1394 "failed(%d) to initialize VLAN config\n", ret); 1395 goto err_config; 1396 } 1397 1398 pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME); 1399 1400 return 0; 1401 1402 err_config: 1403 hclgevf_cmd_uninit(hdev); 1404 err_cmd_init: 1405 hclgevf_misc_irq_uninit(hdev); 1406 err_misc_irq_init: 1407 hclgevf_state_uninit(hdev); 1408 hclgevf_uninit_msi(hdev); 1409 err_irq_init: 1410 hclgevf_pci_uninit(hdev); 1411 return ret; 1412 } 1413 1414 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 1415 { 1416 struct hclgevf_dev *hdev = ae_dev->priv; 1417 1418 hclgevf_cmd_uninit(hdev); 1419 hclgevf_misc_irq_uninit(hdev); 1420 hclgevf_state_uninit(hdev); 1421 hclgevf_uninit_msi(hdev); 1422 hclgevf_pci_uninit(hdev); 1423 ae_dev->priv = NULL; 1424 } 1425 1426 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 1427 { 1428 struct hnae3_handle *nic = &hdev->nic; 1429 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 1430 1431 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps); 1432 } 1433 1434 /** 1435 * hclgevf_get_channels - Get the current channels enabled and max supported. 1436 * @handle: hardware information for network interface 1437 * @ch: ethtool channels structure 1438 * 1439 * We don't support separate tx and rx queues as channels. The other count 1440 * represents how many queues are being used for control. max_combined counts 1441 * how many queue pairs we can support. They may not be mapped 1 to 1 with 1442 * q_vectors since we support a lot more queue pairs than q_vectors. 1443 **/ 1444 static void hclgevf_get_channels(struct hnae3_handle *handle, 1445 struct ethtool_channels *ch) 1446 { 1447 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1448 1449 ch->max_combined = hclgevf_get_max_channels(hdev); 1450 ch->other_count = 0; 1451 ch->max_other = 0; 1452 ch->combined_count = hdev->num_tqps; 1453 } 1454 1455 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 1456 u16 *free_tqps, u16 *max_rss_size) 1457 { 1458 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1459 1460 *free_tqps = 0; 1461 *max_rss_size = hdev->rss_size_max; 1462 } 1463 1464 static const struct hnae3_ae_ops hclgevf_ops = { 1465 .init_ae_dev = hclgevf_init_ae_dev, 1466 .uninit_ae_dev = hclgevf_uninit_ae_dev, 1467 .init_client_instance = hclgevf_register_client, 1468 .uninit_client_instance = hclgevf_unregister_client, 1469 .start = hclgevf_ae_start, 1470 .stop = hclgevf_ae_stop, 1471 .map_ring_to_vector = hclgevf_map_ring_to_vector, 1472 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 1473 .get_vector = hclgevf_get_vector, 1474 .put_vector = hclgevf_put_vector, 1475 .reset_queue = hclgevf_reset_tqp, 1476 .set_promisc_mode = hclgevf_set_promisc_mode, 1477 .get_mac_addr = hclgevf_get_mac_addr, 1478 .set_mac_addr = hclgevf_set_mac_addr, 1479 .add_uc_addr = hclgevf_add_uc_addr, 1480 .rm_uc_addr = hclgevf_rm_uc_addr, 1481 .add_mc_addr = hclgevf_add_mc_addr, 1482 .rm_mc_addr = hclgevf_rm_mc_addr, 1483 .get_stats = hclgevf_get_stats, 1484 .update_stats = hclgevf_update_stats, 1485 .get_strings = hclgevf_get_strings, 1486 .get_sset_count = hclgevf_get_sset_count, 1487 .get_rss_key_size = hclgevf_get_rss_key_size, 1488 .get_rss_indir_size = hclgevf_get_rss_indir_size, 1489 .get_rss = hclgevf_get_rss, 1490 .set_rss = hclgevf_set_rss, 1491 .get_tc_size = hclgevf_get_tc_size, 1492 .get_fw_version = hclgevf_get_fw_version, 1493 .set_vlan_filter = hclgevf_set_vlan_filter, 1494 .get_channels = hclgevf_get_channels, 1495 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 1496 }; 1497 1498 static struct hnae3_ae_algo ae_algovf = { 1499 .ops = &hclgevf_ops, 1500 .name = HCLGEVF_NAME, 1501 .pdev_id_table = ae_algovf_pci_tbl, 1502 }; 1503 1504 static int hclgevf_init(void) 1505 { 1506 pr_info("%s is initializing\n", HCLGEVF_NAME); 1507 1508 return hnae3_register_ae_algo(&ae_algovf); 1509 } 1510 1511 static void hclgevf_exit(void) 1512 { 1513 hnae3_unregister_ae_algo(&ae_algovf); 1514 } 1515 module_init(hclgevf_init); 1516 module_exit(hclgevf_exit); 1517 1518 MODULE_LICENSE("GPL"); 1519 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 1520 MODULE_DESCRIPTION("HCLGEVF Driver"); 1521 MODULE_VERSION(HCLGEVF_MOD_VERSION); 1522