1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include <linux/iopoll.h> 6 #include <net/rtnetlink.h> 7 #include "hclgevf_cmd.h" 8 #include "hclgevf_main.h" 9 #include "hclge_mbx.h" 10 #include "hnae3.h" 11 12 #define HCLGEVF_NAME "hclgevf" 13 14 #define HCLGEVF_RESET_MAX_FAIL_CNT 5 15 16 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 17 static struct hnae3_ae_algo ae_algovf; 18 19 static const struct pci_device_id ae_algovf_pci_tbl[] = { 20 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 21 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 22 /* required last entry */ 23 {0, } 24 }; 25 26 static const u8 hclgevf_hash_key[] = { 27 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 28 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 29 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 30 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 31 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 32 }; 33 34 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 35 36 static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 37 HCLGEVF_CMDQ_TX_ADDR_H_REG, 38 HCLGEVF_CMDQ_TX_DEPTH_REG, 39 HCLGEVF_CMDQ_TX_TAIL_REG, 40 HCLGEVF_CMDQ_TX_HEAD_REG, 41 HCLGEVF_CMDQ_RX_ADDR_L_REG, 42 HCLGEVF_CMDQ_RX_ADDR_H_REG, 43 HCLGEVF_CMDQ_RX_DEPTH_REG, 44 HCLGEVF_CMDQ_RX_TAIL_REG, 45 HCLGEVF_CMDQ_RX_HEAD_REG, 46 HCLGEVF_VECTOR0_CMDQ_SRC_REG, 47 HCLGEVF_CMDQ_INTR_STS_REG, 48 HCLGEVF_CMDQ_INTR_EN_REG, 49 HCLGEVF_CMDQ_INTR_GEN_REG}; 50 51 static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 52 HCLGEVF_RST_ING, 53 HCLGEVF_GRO_EN_REG}; 54 55 static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 56 HCLGEVF_RING_RX_ADDR_H_REG, 57 HCLGEVF_RING_RX_BD_NUM_REG, 58 HCLGEVF_RING_RX_BD_LENGTH_REG, 59 HCLGEVF_RING_RX_MERGE_EN_REG, 60 HCLGEVF_RING_RX_TAIL_REG, 61 HCLGEVF_RING_RX_HEAD_REG, 62 HCLGEVF_RING_RX_FBD_NUM_REG, 63 HCLGEVF_RING_RX_OFFSET_REG, 64 HCLGEVF_RING_RX_FBD_OFFSET_REG, 65 HCLGEVF_RING_RX_STASH_REG, 66 HCLGEVF_RING_RX_BD_ERR_REG, 67 HCLGEVF_RING_TX_ADDR_L_REG, 68 HCLGEVF_RING_TX_ADDR_H_REG, 69 HCLGEVF_RING_TX_BD_NUM_REG, 70 HCLGEVF_RING_TX_PRIORITY_REG, 71 HCLGEVF_RING_TX_TC_REG, 72 HCLGEVF_RING_TX_MERGE_EN_REG, 73 HCLGEVF_RING_TX_TAIL_REG, 74 HCLGEVF_RING_TX_HEAD_REG, 75 HCLGEVF_RING_TX_FBD_NUM_REG, 76 HCLGEVF_RING_TX_OFFSET_REG, 77 HCLGEVF_RING_TX_EBD_NUM_REG, 78 HCLGEVF_RING_TX_EBD_OFFSET_REG, 79 HCLGEVF_RING_TX_BD_ERR_REG, 80 HCLGEVF_RING_EN_REG}; 81 82 static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 83 HCLGEVF_TQP_INTR_GL0_REG, 84 HCLGEVF_TQP_INTR_GL1_REG, 85 HCLGEVF_TQP_INTR_GL2_REG, 86 HCLGEVF_TQP_INTR_RL_REG}; 87 88 static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 89 { 90 if (!handle->client) 91 return container_of(handle, struct hclgevf_dev, nic); 92 else if (handle->client->type == HNAE3_CLIENT_ROCE) 93 return container_of(handle, struct hclgevf_dev, roce); 94 else 95 return container_of(handle, struct hclgevf_dev, nic); 96 } 97 98 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 99 { 100 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 101 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 102 struct hclgevf_desc desc; 103 struct hclgevf_tqp *tqp; 104 int status; 105 int i; 106 107 for (i = 0; i < kinfo->num_tqps; i++) { 108 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 109 hclgevf_cmd_setup_basic_desc(&desc, 110 HCLGEVF_OPC_QUERY_RX_STATUS, 111 true); 112 113 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 114 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 115 if (status) { 116 dev_err(&hdev->pdev->dev, 117 "Query tqp stat fail, status = %d,queue = %d\n", 118 status, i); 119 return status; 120 } 121 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 122 le32_to_cpu(desc.data[1]); 123 124 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 125 true); 126 127 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 128 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 129 if (status) { 130 dev_err(&hdev->pdev->dev, 131 "Query tqp stat fail, status = %d,queue = %d\n", 132 status, i); 133 return status; 134 } 135 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 136 le32_to_cpu(desc.data[1]); 137 } 138 139 return 0; 140 } 141 142 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 143 { 144 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 145 struct hclgevf_tqp *tqp; 146 u64 *buff = data; 147 int i; 148 149 for (i = 0; i < kinfo->num_tqps; i++) { 150 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 151 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 152 } 153 for (i = 0; i < kinfo->num_tqps; i++) { 154 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 155 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 156 } 157 158 return buff; 159 } 160 161 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 162 { 163 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 164 165 return kinfo->num_tqps * 2; 166 } 167 168 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 169 { 170 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 171 u8 *buff = data; 172 int i = 0; 173 174 for (i = 0; i < kinfo->num_tqps; i++) { 175 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 176 struct hclgevf_tqp, q); 177 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 178 tqp->index); 179 buff += ETH_GSTRING_LEN; 180 } 181 182 for (i = 0; i < kinfo->num_tqps; i++) { 183 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 184 struct hclgevf_tqp, q); 185 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 186 tqp->index); 187 buff += ETH_GSTRING_LEN; 188 } 189 190 return buff; 191 } 192 193 static void hclgevf_update_stats(struct hnae3_handle *handle, 194 struct net_device_stats *net_stats) 195 { 196 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 197 int status; 198 199 status = hclgevf_tqps_update_stats(handle); 200 if (status) 201 dev_err(&hdev->pdev->dev, 202 "VF update of TQPS stats fail, status = %d.\n", 203 status); 204 } 205 206 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 207 { 208 if (strset == ETH_SS_TEST) 209 return -EOPNOTSUPP; 210 else if (strset == ETH_SS_STATS) 211 return hclgevf_tqps_get_sset_count(handle, strset); 212 213 return 0; 214 } 215 216 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 217 u8 *data) 218 { 219 u8 *p = (char *)data; 220 221 if (strset == ETH_SS_STATS) 222 p = hclgevf_tqps_get_strings(handle, p); 223 } 224 225 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 226 { 227 hclgevf_tqps_get_stats(handle, data); 228 } 229 230 static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 231 { 232 u8 resp_msg; 233 int status; 234 235 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 236 true, &resp_msg, sizeof(resp_msg)); 237 if (status) { 238 dev_err(&hdev->pdev->dev, 239 "VF request to get TC info from PF failed %d", 240 status); 241 return status; 242 } 243 244 hdev->hw_tc_map = resp_msg; 245 246 return 0; 247 } 248 249 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 250 { 251 struct hnae3_handle *nic = &hdev->nic; 252 u8 resp_msg; 253 int ret; 254 255 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 256 HCLGE_MBX_GET_PORT_BASE_VLAN_STATE, 257 NULL, 0, true, &resp_msg, sizeof(u8)); 258 if (ret) { 259 dev_err(&hdev->pdev->dev, 260 "VF request to get port based vlan state failed %d", 261 ret); 262 return ret; 263 } 264 265 nic->port_base_vlan_state = resp_msg; 266 267 return 0; 268 } 269 270 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 271 { 272 #define HCLGEVF_TQPS_RSS_INFO_LEN 6 273 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 274 int status; 275 276 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 277 true, resp_msg, 278 HCLGEVF_TQPS_RSS_INFO_LEN); 279 if (status) { 280 dev_err(&hdev->pdev->dev, 281 "VF request to get tqp info from PF failed %d", 282 status); 283 return status; 284 } 285 286 memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 287 memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 288 memcpy(&hdev->rx_buf_len, &resp_msg[4], sizeof(u16)); 289 290 return 0; 291 } 292 293 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 294 { 295 #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 296 u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 297 int ret; 298 299 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QDEPTH, 0, NULL, 0, 300 true, resp_msg, 301 HCLGEVF_TQPS_DEPTH_INFO_LEN); 302 if (ret) { 303 dev_err(&hdev->pdev->dev, 304 "VF request to get tqp depth info from PF failed %d", 305 ret); 306 return ret; 307 } 308 309 memcpy(&hdev->num_tx_desc, &resp_msg[0], sizeof(u16)); 310 memcpy(&hdev->num_rx_desc, &resp_msg[2], sizeof(u16)); 311 312 return 0; 313 } 314 315 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 316 { 317 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 318 u8 msg_data[2], resp_data[2]; 319 u16 qid_in_pf = 0; 320 int ret; 321 322 memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 323 324 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data, 325 sizeof(msg_data), true, resp_data, 326 sizeof(resp_data)); 327 if (!ret) 328 qid_in_pf = *(u16 *)resp_data; 329 330 return qid_in_pf; 331 } 332 333 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 334 { 335 u8 resp_msg[2]; 336 int ret; 337 338 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_MEDIA_TYPE, 0, NULL, 0, 339 true, resp_msg, sizeof(resp_msg)); 340 if (ret) { 341 dev_err(&hdev->pdev->dev, 342 "VF request to get the pf port media type failed %d", 343 ret); 344 return ret; 345 } 346 347 hdev->hw.mac.media_type = resp_msg[0]; 348 hdev->hw.mac.module_type = resp_msg[1]; 349 350 return 0; 351 } 352 353 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 354 { 355 struct hclgevf_tqp *tqp; 356 int i; 357 358 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 359 sizeof(struct hclgevf_tqp), GFP_KERNEL); 360 if (!hdev->htqp) 361 return -ENOMEM; 362 363 tqp = hdev->htqp; 364 365 for (i = 0; i < hdev->num_tqps; i++) { 366 tqp->dev = &hdev->pdev->dev; 367 tqp->index = i; 368 369 tqp->q.ae_algo = &ae_algovf; 370 tqp->q.buf_size = hdev->rx_buf_len; 371 tqp->q.tx_desc_num = hdev->num_tx_desc; 372 tqp->q.rx_desc_num = hdev->num_rx_desc; 373 tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 374 i * HCLGEVF_TQP_REG_SIZE; 375 376 tqp++; 377 } 378 379 return 0; 380 } 381 382 static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 383 { 384 struct hnae3_handle *nic = &hdev->nic; 385 struct hnae3_knic_private_info *kinfo; 386 u16 new_tqps = hdev->num_tqps; 387 unsigned int i; 388 389 kinfo = &nic->kinfo; 390 kinfo->num_tc = 0; 391 kinfo->num_tx_desc = hdev->num_tx_desc; 392 kinfo->num_rx_desc = hdev->num_rx_desc; 393 kinfo->rx_buf_len = hdev->rx_buf_len; 394 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 395 if (hdev->hw_tc_map & BIT(i)) 396 kinfo->num_tc++; 397 398 kinfo->rss_size 399 = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 400 new_tqps = kinfo->rss_size * kinfo->num_tc; 401 kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 402 403 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 404 sizeof(struct hnae3_queue *), GFP_KERNEL); 405 if (!kinfo->tqp) 406 return -ENOMEM; 407 408 for (i = 0; i < kinfo->num_tqps; i++) { 409 hdev->htqp[i].q.handle = &hdev->nic; 410 hdev->htqp[i].q.tqp_index = i; 411 kinfo->tqp[i] = &hdev->htqp[i].q; 412 } 413 414 return 0; 415 } 416 417 static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 418 { 419 int status; 420 u8 resp_msg; 421 422 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 423 0, false, &resp_msg, sizeof(resp_msg)); 424 if (status) 425 dev_err(&hdev->pdev->dev, 426 "VF failed to fetch link status(%d) from PF", status); 427 } 428 429 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 430 { 431 struct hnae3_handle *rhandle = &hdev->roce; 432 struct hnae3_handle *handle = &hdev->nic; 433 struct hnae3_client *rclient; 434 struct hnae3_client *client; 435 436 client = handle->client; 437 rclient = hdev->roce_client; 438 439 link_state = 440 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 441 442 if (link_state != hdev->hw.mac.link) { 443 client->ops->link_status_change(handle, !!link_state); 444 if (rclient && rclient->ops->link_status_change) 445 rclient->ops->link_status_change(rhandle, !!link_state); 446 hdev->hw.mac.link = link_state; 447 } 448 } 449 450 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 451 { 452 #define HCLGEVF_ADVERTISING 0 453 #define HCLGEVF_SUPPORTED 1 454 u8 send_msg; 455 u8 resp_msg; 456 457 send_msg = HCLGEVF_ADVERTISING; 458 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 459 &send_msg, sizeof(send_msg), false, 460 &resp_msg, sizeof(resp_msg)); 461 send_msg = HCLGEVF_SUPPORTED; 462 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 463 &send_msg, sizeof(send_msg), false, 464 &resp_msg, sizeof(resp_msg)); 465 } 466 467 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 468 { 469 struct hnae3_handle *nic = &hdev->nic; 470 int ret; 471 472 nic->ae_algo = &ae_algovf; 473 nic->pdev = hdev->pdev; 474 nic->numa_node_mask = hdev->numa_node_mask; 475 nic->flags |= HNAE3_SUPPORT_VF; 476 477 ret = hclgevf_knic_setup(hdev); 478 if (ret) 479 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 480 ret); 481 return ret; 482 } 483 484 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 485 { 486 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 487 dev_warn(&hdev->pdev->dev, 488 "vector(vector_id %d) has been freed.\n", vector_id); 489 return; 490 } 491 492 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 493 hdev->num_msi_left += 1; 494 hdev->num_msi_used -= 1; 495 } 496 497 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 498 struct hnae3_vector_info *vector_info) 499 { 500 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 501 struct hnae3_vector_info *vector = vector_info; 502 int alloc = 0; 503 int i, j; 504 505 vector_num = min(hdev->num_msi_left, vector_num); 506 507 for (j = 0; j < vector_num; j++) { 508 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 509 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 510 vector->vector = pci_irq_vector(hdev->pdev, i); 511 vector->io_addr = hdev->hw.io_base + 512 HCLGEVF_VECTOR_REG_BASE + 513 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 514 hdev->vector_status[i] = 0; 515 hdev->vector_irq[i] = vector->vector; 516 517 vector++; 518 alloc++; 519 520 break; 521 } 522 } 523 } 524 hdev->num_msi_left -= alloc; 525 hdev->num_msi_used += alloc; 526 527 return alloc; 528 } 529 530 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 531 { 532 int i; 533 534 for (i = 0; i < hdev->num_msi; i++) 535 if (vector == hdev->vector_irq[i]) 536 return i; 537 538 return -EINVAL; 539 } 540 541 static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 542 const u8 hfunc, const u8 *key) 543 { 544 struct hclgevf_rss_config_cmd *req; 545 unsigned int key_offset = 0; 546 struct hclgevf_desc desc; 547 int key_counts; 548 int key_size; 549 int ret; 550 551 key_counts = HCLGEVF_RSS_KEY_SIZE; 552 req = (struct hclgevf_rss_config_cmd *)desc.data; 553 554 while (key_counts) { 555 hclgevf_cmd_setup_basic_desc(&desc, 556 HCLGEVF_OPC_RSS_GENERIC_CONFIG, 557 false); 558 559 req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 560 req->hash_config |= 561 (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 562 563 key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts); 564 memcpy(req->hash_key, 565 key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 566 567 key_counts -= key_size; 568 key_offset++; 569 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 570 if (ret) { 571 dev_err(&hdev->pdev->dev, 572 "Configure RSS config fail, status = %d\n", 573 ret); 574 return ret; 575 } 576 } 577 578 return 0; 579 } 580 581 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 582 { 583 return HCLGEVF_RSS_KEY_SIZE; 584 } 585 586 static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 587 { 588 return HCLGEVF_RSS_IND_TBL_SIZE; 589 } 590 591 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 592 { 593 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 594 struct hclgevf_rss_indirection_table_cmd *req; 595 struct hclgevf_desc desc; 596 int status; 597 int i, j; 598 599 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 600 601 for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 602 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 603 false); 604 req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 605 req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 606 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 607 req->rss_result[j] = 608 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 609 610 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 611 if (status) { 612 dev_err(&hdev->pdev->dev, 613 "VF failed(=%d) to set RSS indirection table\n", 614 status); 615 return status; 616 } 617 } 618 619 return 0; 620 } 621 622 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 623 { 624 struct hclgevf_rss_tc_mode_cmd *req; 625 u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 626 u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 627 u16 tc_size[HCLGEVF_MAX_TC_NUM]; 628 struct hclgevf_desc desc; 629 u16 roundup_size; 630 int status; 631 unsigned int i; 632 633 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 634 635 roundup_size = roundup_pow_of_two(rss_size); 636 roundup_size = ilog2(roundup_size); 637 638 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 639 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 640 tc_size[i] = roundup_size; 641 tc_offset[i] = rss_size * i; 642 } 643 644 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 645 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 646 hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 647 (tc_valid[i] & 0x1)); 648 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 649 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 650 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 651 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 652 } 653 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 654 if (status) 655 dev_err(&hdev->pdev->dev, 656 "VF failed(=%d) to set rss tc mode\n", status); 657 658 return status; 659 } 660 661 /* for revision 0x20, vf shared the same rss config with pf */ 662 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 663 { 664 #define HCLGEVF_RSS_MBX_RESP_LEN 8 665 666 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 667 u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 668 u16 msg_num, hash_key_index; 669 u8 index; 670 int ret; 671 672 msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 673 HCLGEVF_RSS_MBX_RESP_LEN; 674 for (index = 0; index < msg_num; index++) { 675 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_RSS_KEY, 0, 676 &index, sizeof(index), 677 true, resp_msg, 678 HCLGEVF_RSS_MBX_RESP_LEN); 679 if (ret) { 680 dev_err(&hdev->pdev->dev, 681 "VF get rss hash key from PF failed, ret=%d", 682 ret); 683 return ret; 684 } 685 686 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 687 if (index == msg_num - 1) 688 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 689 &resp_msg[0], 690 HCLGEVF_RSS_KEY_SIZE - hash_key_index); 691 else 692 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 693 &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 694 } 695 696 return 0; 697 } 698 699 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 700 u8 *hfunc) 701 { 702 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 703 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 704 int i, ret; 705 706 if (handle->pdev->revision >= 0x21) { 707 /* Get hash algorithm */ 708 if (hfunc) { 709 switch (rss_cfg->hash_algo) { 710 case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 711 *hfunc = ETH_RSS_HASH_TOP; 712 break; 713 case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 714 *hfunc = ETH_RSS_HASH_XOR; 715 break; 716 default: 717 *hfunc = ETH_RSS_HASH_UNKNOWN; 718 break; 719 } 720 } 721 722 /* Get the RSS Key required by the user */ 723 if (key) 724 memcpy(key, rss_cfg->rss_hash_key, 725 HCLGEVF_RSS_KEY_SIZE); 726 } else { 727 if (hfunc) 728 *hfunc = ETH_RSS_HASH_TOP; 729 if (key) { 730 ret = hclgevf_get_rss_hash_key(hdev); 731 if (ret) 732 return ret; 733 memcpy(key, rss_cfg->rss_hash_key, 734 HCLGEVF_RSS_KEY_SIZE); 735 } 736 } 737 738 if (indir) 739 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 740 indir[i] = rss_cfg->rss_indirection_tbl[i]; 741 742 return 0; 743 } 744 745 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 746 const u8 *key, const u8 hfunc) 747 { 748 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 749 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 750 int ret, i; 751 752 if (handle->pdev->revision >= 0x21) { 753 /* Set the RSS Hash Key if specififed by the user */ 754 if (key) { 755 switch (hfunc) { 756 case ETH_RSS_HASH_TOP: 757 rss_cfg->hash_algo = 758 HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 759 break; 760 case ETH_RSS_HASH_XOR: 761 rss_cfg->hash_algo = 762 HCLGEVF_RSS_HASH_ALGO_SIMPLE; 763 break; 764 case ETH_RSS_HASH_NO_CHANGE: 765 break; 766 default: 767 return -EINVAL; 768 } 769 770 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 771 key); 772 if (ret) 773 return ret; 774 775 /* Update the shadow RSS key with user specified qids */ 776 memcpy(rss_cfg->rss_hash_key, key, 777 HCLGEVF_RSS_KEY_SIZE); 778 } 779 } 780 781 /* update the shadow RSS table with user specified qids */ 782 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 783 rss_cfg->rss_indirection_tbl[i] = indir[i]; 784 785 /* update the hardware */ 786 return hclgevf_set_rss_indir_table(hdev); 787 } 788 789 static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 790 { 791 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 792 793 if (nfc->data & RXH_L4_B_2_3) 794 hash_sets |= HCLGEVF_D_PORT_BIT; 795 else 796 hash_sets &= ~HCLGEVF_D_PORT_BIT; 797 798 if (nfc->data & RXH_IP_SRC) 799 hash_sets |= HCLGEVF_S_IP_BIT; 800 else 801 hash_sets &= ~HCLGEVF_S_IP_BIT; 802 803 if (nfc->data & RXH_IP_DST) 804 hash_sets |= HCLGEVF_D_IP_BIT; 805 else 806 hash_sets &= ~HCLGEVF_D_IP_BIT; 807 808 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 809 hash_sets |= HCLGEVF_V_TAG_BIT; 810 811 return hash_sets; 812 } 813 814 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 815 struct ethtool_rxnfc *nfc) 816 { 817 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 818 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 819 struct hclgevf_rss_input_tuple_cmd *req; 820 struct hclgevf_desc desc; 821 u8 tuple_sets; 822 int ret; 823 824 if (handle->pdev->revision == 0x20) 825 return -EOPNOTSUPP; 826 827 if (nfc->data & 828 ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 829 return -EINVAL; 830 831 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 832 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 833 834 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 835 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 836 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 837 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 838 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 839 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 840 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 841 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 842 843 tuple_sets = hclgevf_get_rss_hash_bits(nfc); 844 switch (nfc->flow_type) { 845 case TCP_V4_FLOW: 846 req->ipv4_tcp_en = tuple_sets; 847 break; 848 case TCP_V6_FLOW: 849 req->ipv6_tcp_en = tuple_sets; 850 break; 851 case UDP_V4_FLOW: 852 req->ipv4_udp_en = tuple_sets; 853 break; 854 case UDP_V6_FLOW: 855 req->ipv6_udp_en = tuple_sets; 856 break; 857 case SCTP_V4_FLOW: 858 req->ipv4_sctp_en = tuple_sets; 859 break; 860 case SCTP_V6_FLOW: 861 if ((nfc->data & RXH_L4_B_0_1) || 862 (nfc->data & RXH_L4_B_2_3)) 863 return -EINVAL; 864 865 req->ipv6_sctp_en = tuple_sets; 866 break; 867 case IPV4_FLOW: 868 req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 869 break; 870 case IPV6_FLOW: 871 req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 872 break; 873 default: 874 return -EINVAL; 875 } 876 877 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 878 if (ret) { 879 dev_err(&hdev->pdev->dev, 880 "Set rss tuple fail, status = %d\n", ret); 881 return ret; 882 } 883 884 rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 885 rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 886 rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 887 rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 888 rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 889 rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 890 rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 891 rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 892 return 0; 893 } 894 895 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 896 struct ethtool_rxnfc *nfc) 897 { 898 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 899 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 900 u8 tuple_sets; 901 902 if (handle->pdev->revision == 0x20) 903 return -EOPNOTSUPP; 904 905 nfc->data = 0; 906 907 switch (nfc->flow_type) { 908 case TCP_V4_FLOW: 909 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 910 break; 911 case UDP_V4_FLOW: 912 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 913 break; 914 case TCP_V6_FLOW: 915 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 916 break; 917 case UDP_V6_FLOW: 918 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 919 break; 920 case SCTP_V4_FLOW: 921 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 922 break; 923 case SCTP_V6_FLOW: 924 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 925 break; 926 case IPV4_FLOW: 927 case IPV6_FLOW: 928 tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 929 break; 930 default: 931 return -EINVAL; 932 } 933 934 if (!tuple_sets) 935 return 0; 936 937 if (tuple_sets & HCLGEVF_D_PORT_BIT) 938 nfc->data |= RXH_L4_B_2_3; 939 if (tuple_sets & HCLGEVF_S_PORT_BIT) 940 nfc->data |= RXH_L4_B_0_1; 941 if (tuple_sets & HCLGEVF_D_IP_BIT) 942 nfc->data |= RXH_IP_DST; 943 if (tuple_sets & HCLGEVF_S_IP_BIT) 944 nfc->data |= RXH_IP_SRC; 945 946 return 0; 947 } 948 949 static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 950 struct hclgevf_rss_cfg *rss_cfg) 951 { 952 struct hclgevf_rss_input_tuple_cmd *req; 953 struct hclgevf_desc desc; 954 int ret; 955 956 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 957 958 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 959 960 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 961 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 962 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 963 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 964 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 965 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 966 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 967 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 968 969 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 970 if (ret) 971 dev_err(&hdev->pdev->dev, 972 "Configure rss input fail, status = %d\n", ret); 973 return ret; 974 } 975 976 static int hclgevf_get_tc_size(struct hnae3_handle *handle) 977 { 978 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 979 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 980 981 return rss_cfg->rss_size; 982 } 983 984 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 985 int vector_id, 986 struct hnae3_ring_chain_node *ring_chain) 987 { 988 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 989 struct hnae3_ring_chain_node *node; 990 struct hclge_mbx_vf_to_pf_cmd *req; 991 struct hclgevf_desc desc; 992 int i = 0; 993 int status; 994 u8 type; 995 996 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 997 type = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 998 HCLGE_MBX_UNMAP_RING_TO_VECTOR; 999 1000 for (node = ring_chain; node; node = node->next) { 1001 int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 1002 HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 1003 1004 if (i == 0) { 1005 hclgevf_cmd_setup_basic_desc(&desc, 1006 HCLGEVF_OPC_MBX_VF_TO_PF, 1007 false); 1008 req->msg[0] = type; 1009 req->msg[1] = vector_id; 1010 } 1011 1012 req->msg[idx_offset] = 1013 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 1014 req->msg[idx_offset + 1] = node->tqp_index; 1015 req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 1016 HNAE3_RING_GL_IDX_M, 1017 HNAE3_RING_GL_IDX_S); 1018 1019 i++; 1020 if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 1021 HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 1022 HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 1023 !node->next) { 1024 req->msg[2] = i; 1025 1026 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1027 if (status) { 1028 dev_err(&hdev->pdev->dev, 1029 "Map TQP fail, status is %d.\n", 1030 status); 1031 return status; 1032 } 1033 i = 0; 1034 hclgevf_cmd_setup_basic_desc(&desc, 1035 HCLGEVF_OPC_MBX_VF_TO_PF, 1036 false); 1037 req->msg[0] = type; 1038 req->msg[1] = vector_id; 1039 } 1040 } 1041 1042 return 0; 1043 } 1044 1045 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1046 struct hnae3_ring_chain_node *ring_chain) 1047 { 1048 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1049 int vector_id; 1050 1051 vector_id = hclgevf_get_vector_index(hdev, vector); 1052 if (vector_id < 0) { 1053 dev_err(&handle->pdev->dev, 1054 "Get vector index fail. ret =%d\n", vector_id); 1055 return vector_id; 1056 } 1057 1058 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1059 } 1060 1061 static int hclgevf_unmap_ring_from_vector( 1062 struct hnae3_handle *handle, 1063 int vector, 1064 struct hnae3_ring_chain_node *ring_chain) 1065 { 1066 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1067 int ret, vector_id; 1068 1069 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1070 return 0; 1071 1072 vector_id = hclgevf_get_vector_index(hdev, vector); 1073 if (vector_id < 0) { 1074 dev_err(&handle->pdev->dev, 1075 "Get vector index fail. ret =%d\n", vector_id); 1076 return vector_id; 1077 } 1078 1079 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 1080 if (ret) 1081 dev_err(&handle->pdev->dev, 1082 "Unmap ring from vector fail. vector=%d, ret =%d\n", 1083 vector_id, 1084 ret); 1085 1086 return ret; 1087 } 1088 1089 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 1090 { 1091 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1092 int vector_id; 1093 1094 vector_id = hclgevf_get_vector_index(hdev, vector); 1095 if (vector_id < 0) { 1096 dev_err(&handle->pdev->dev, 1097 "hclgevf_put_vector get vector index fail. ret =%d\n", 1098 vector_id); 1099 return vector_id; 1100 } 1101 1102 hclgevf_free_vector(hdev, vector_id); 1103 1104 return 0; 1105 } 1106 1107 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1108 bool en_bc_pmc) 1109 { 1110 struct hclge_mbx_vf_to_pf_cmd *req; 1111 struct hclgevf_desc desc; 1112 int ret; 1113 1114 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1115 1116 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 1117 req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 1118 req->msg[1] = en_bc_pmc ? 1 : 0; 1119 1120 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1121 if (ret) 1122 dev_err(&hdev->pdev->dev, 1123 "Set promisc mode fail, status is %d.\n", ret); 1124 1125 return ret; 1126 } 1127 1128 static int hclgevf_set_promisc_mode(struct hclgevf_dev *hdev, bool en_bc_pmc) 1129 { 1130 return hclgevf_cmd_set_promisc_mode(hdev, en_bc_pmc); 1131 } 1132 1133 static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, unsigned int tqp_id, 1134 int stream_id, bool enable) 1135 { 1136 struct hclgevf_cfg_com_tqp_queue_cmd *req; 1137 struct hclgevf_desc desc; 1138 int status; 1139 1140 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1141 1142 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1143 false); 1144 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1145 req->stream_id = cpu_to_le16(stream_id); 1146 if (enable) 1147 req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 1148 1149 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1150 if (status) 1151 dev_err(&hdev->pdev->dev, 1152 "TQP enable fail, status =%d.\n", status); 1153 1154 return status; 1155 } 1156 1157 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1158 { 1159 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1160 struct hclgevf_tqp *tqp; 1161 int i; 1162 1163 for (i = 0; i < kinfo->num_tqps; i++) { 1164 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1165 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1166 } 1167 } 1168 1169 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1170 { 1171 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1172 1173 ether_addr_copy(p, hdev->hw.mac.mac_addr); 1174 } 1175 1176 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 1177 bool is_first) 1178 { 1179 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1180 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1181 u8 *new_mac_addr = (u8 *)p; 1182 u8 msg_data[ETH_ALEN * 2]; 1183 u16 subcode; 1184 int status; 1185 1186 ether_addr_copy(msg_data, new_mac_addr); 1187 ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 1188 1189 subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 1190 HCLGE_MBX_MAC_VLAN_UC_MODIFY; 1191 1192 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1193 subcode, msg_data, sizeof(msg_data), 1194 true, NULL, 0); 1195 if (!status) 1196 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1197 1198 return status; 1199 } 1200 1201 static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1202 const unsigned char *addr) 1203 { 1204 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1205 1206 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1207 HCLGE_MBX_MAC_VLAN_UC_ADD, 1208 addr, ETH_ALEN, false, NULL, 0); 1209 } 1210 1211 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1212 const unsigned char *addr) 1213 { 1214 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1215 1216 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1217 HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1218 addr, ETH_ALEN, false, NULL, 0); 1219 } 1220 1221 static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1222 const unsigned char *addr) 1223 { 1224 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1225 1226 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1227 HCLGE_MBX_MAC_VLAN_MC_ADD, 1228 addr, ETH_ALEN, false, NULL, 0); 1229 } 1230 1231 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1232 const unsigned char *addr) 1233 { 1234 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1235 1236 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1237 HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1238 addr, ETH_ALEN, false, NULL, 0); 1239 } 1240 1241 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1242 __be16 proto, u16 vlan_id, 1243 bool is_kill) 1244 { 1245 #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1246 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1247 u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1248 int ret; 1249 1250 if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1251 return -EINVAL; 1252 1253 if (proto != htons(ETH_P_8021Q)) 1254 return -EPROTONOSUPPORT; 1255 1256 /* When device is resetting, firmware is unable to handle 1257 * mailbox. Just record the vlan id, and remove it after 1258 * reset finished. 1259 */ 1260 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) && is_kill) { 1261 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1262 return -EBUSY; 1263 } 1264 1265 msg_data[0] = is_kill; 1266 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1267 memcpy(&msg_data[3], &proto, sizeof(proto)); 1268 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1269 HCLGE_MBX_VLAN_FILTER, msg_data, 1270 HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 1271 1272 /* When remove hw vlan filter failed, record the vlan id, 1273 * and try to remove it from hw later, to be consistence 1274 * with stack. 1275 */ 1276 if (is_kill && ret) 1277 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1278 1279 return ret; 1280 } 1281 1282 static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1283 { 1284 #define HCLGEVF_MAX_SYNC_COUNT 60 1285 struct hnae3_handle *handle = &hdev->nic; 1286 int ret, sync_cnt = 0; 1287 u16 vlan_id; 1288 1289 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1290 while (vlan_id != VLAN_N_VID) { 1291 ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1292 vlan_id, true); 1293 if (ret) 1294 return; 1295 1296 clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1297 sync_cnt++; 1298 if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1299 return; 1300 1301 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1302 } 1303 } 1304 1305 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1306 { 1307 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1308 u8 msg_data; 1309 1310 msg_data = enable ? 1 : 0; 1311 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1312 HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1313 1, false, NULL, 0); 1314 } 1315 1316 static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1317 { 1318 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1319 u8 msg_data[2]; 1320 int ret; 1321 1322 memcpy(msg_data, &queue_id, sizeof(queue_id)); 1323 1324 /* disable vf queue before send queue reset msg to PF */ 1325 ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 1326 if (ret) 1327 return ret; 1328 1329 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 1330 sizeof(msg_data), true, NULL, 0); 1331 } 1332 1333 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1334 { 1335 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1336 1337 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu, 1338 sizeof(new_mtu), true, NULL, 0); 1339 } 1340 1341 static int hclgevf_notify_client(struct hclgevf_dev *hdev, 1342 enum hnae3_reset_notify_type type) 1343 { 1344 struct hnae3_client *client = hdev->nic_client; 1345 struct hnae3_handle *handle = &hdev->nic; 1346 int ret; 1347 1348 if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 1349 !client) 1350 return 0; 1351 1352 if (!client->ops->reset_notify) 1353 return -EOPNOTSUPP; 1354 1355 ret = client->ops->reset_notify(handle, type); 1356 if (ret) 1357 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 1358 type, ret); 1359 1360 return ret; 1361 } 1362 1363 static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 1364 { 1365 struct hclgevf_dev *hdev = ae_dev->priv; 1366 1367 set_bit(HNAE3_FLR_DONE, &hdev->flr_state); 1368 } 1369 1370 static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev, 1371 unsigned long delay_us, 1372 unsigned long wait_cnt) 1373 { 1374 unsigned long cnt = 0; 1375 1376 while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) && 1377 cnt++ < wait_cnt) 1378 usleep_range(delay_us, delay_us * 2); 1379 1380 if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) { 1381 dev_err(&hdev->pdev->dev, 1382 "flr wait timeout\n"); 1383 return -ETIMEDOUT; 1384 } 1385 1386 return 0; 1387 } 1388 1389 static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 1390 { 1391 #define HCLGEVF_RESET_WAIT_US 20000 1392 #define HCLGEVF_RESET_WAIT_CNT 2000 1393 #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1394 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1395 1396 u32 val; 1397 int ret; 1398 1399 /* wait to check the hardware reset completion status */ 1400 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1401 dev_info(&hdev->pdev->dev, "checking vf resetting status: %x\n", val); 1402 1403 if (hdev->reset_type == HNAE3_FLR_RESET) 1404 return hclgevf_flr_poll_timeout(hdev, 1405 HCLGEVF_RESET_WAIT_US, 1406 HCLGEVF_RESET_WAIT_CNT); 1407 1408 ret = readl_poll_timeout(hdev->hw.io_base + HCLGEVF_RST_ING, val, 1409 !(val & HCLGEVF_RST_ING_BITS), 1410 HCLGEVF_RESET_WAIT_US, 1411 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1412 1413 /* hardware completion status should be available by this time */ 1414 if (ret) { 1415 dev_err(&hdev->pdev->dev, 1416 "could'nt get reset done status from h/w, timeout!\n"); 1417 return ret; 1418 } 1419 1420 /* we will wait a bit more to let reset of the stack to complete. This 1421 * might happen in case reset assertion was made by PF. Yes, this also 1422 * means we might end up waiting bit more even for VF reset. 1423 */ 1424 msleep(5000); 1425 1426 return 0; 1427 } 1428 1429 static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 1430 { 1431 int ret; 1432 1433 /* uninitialize the nic client */ 1434 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 1435 if (ret) 1436 return ret; 1437 1438 /* re-initialize the hclge device */ 1439 ret = hclgevf_reset_hdev(hdev); 1440 if (ret) { 1441 dev_err(&hdev->pdev->dev, 1442 "hclge device re-init failed, VF is disabled!\n"); 1443 return ret; 1444 } 1445 1446 /* bring up the nic client again */ 1447 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 1448 if (ret) 1449 return ret; 1450 1451 return hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT); 1452 } 1453 1454 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1455 { 1456 #define HCLGEVF_RESET_SYNC_TIME 100 1457 1458 int ret = 0; 1459 1460 switch (hdev->reset_type) { 1461 case HNAE3_VF_FUNC_RESET: 1462 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1463 0, true, NULL, sizeof(u8)); 1464 hdev->rst_stats.vf_func_rst_cnt++; 1465 break; 1466 case HNAE3_FLR_RESET: 1467 set_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1468 hdev->rst_stats.flr_rst_cnt++; 1469 break; 1470 default: 1471 break; 1472 } 1473 1474 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1475 /* inform hardware that preparatory work is done */ 1476 msleep(HCLGEVF_RESET_SYNC_TIME); 1477 hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 1478 HCLGEVF_NIC_CMQ_ENABLE); 1479 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1480 hdev->reset_type, ret); 1481 1482 return ret; 1483 } 1484 1485 static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1486 { 1487 hdev->rst_stats.rst_fail_cnt++; 1488 dev_err(&hdev->pdev->dev, "failed to reset VF(%d)\n", 1489 hdev->rst_stats.rst_fail_cnt); 1490 1491 if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1492 set_bit(hdev->reset_type, &hdev->reset_pending); 1493 1494 if (hclgevf_is_reset_pending(hdev)) { 1495 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1496 hclgevf_reset_task_schedule(hdev); 1497 } else { 1498 hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 1499 HCLGEVF_NIC_CMQ_ENABLE); 1500 } 1501 } 1502 1503 static int hclgevf_reset(struct hclgevf_dev *hdev) 1504 { 1505 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1506 int ret; 1507 1508 /* Initialize ae_dev reset status as well, in case enet layer wants to 1509 * know if device is undergoing reset 1510 */ 1511 ae_dev->reset_type = hdev->reset_type; 1512 hdev->rst_stats.rst_cnt++; 1513 rtnl_lock(); 1514 1515 /* bring down the nic to stop any ongoing TX/RX */ 1516 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 1517 if (ret) 1518 goto err_reset_lock; 1519 1520 rtnl_unlock(); 1521 1522 ret = hclgevf_reset_prepare_wait(hdev); 1523 if (ret) 1524 goto err_reset; 1525 1526 /* check if VF could successfully fetch the hardware reset completion 1527 * status from the hardware 1528 */ 1529 ret = hclgevf_reset_wait(hdev); 1530 if (ret) { 1531 /* can't do much in this situation, will disable VF */ 1532 dev_err(&hdev->pdev->dev, 1533 "VF failed(=%d) to fetch H/W reset completion status\n", 1534 ret); 1535 goto err_reset; 1536 } 1537 1538 hdev->rst_stats.hw_rst_done_cnt++; 1539 1540 rtnl_lock(); 1541 1542 /* now, re-initialize the nic client and ae device*/ 1543 ret = hclgevf_reset_stack(hdev); 1544 if (ret) { 1545 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 1546 goto err_reset_lock; 1547 } 1548 1549 /* bring up the nic to enable TX/RX again */ 1550 ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 1551 if (ret) 1552 goto err_reset_lock; 1553 1554 rtnl_unlock(); 1555 1556 hdev->last_reset_time = jiffies; 1557 ae_dev->reset_type = HNAE3_NONE_RESET; 1558 hdev->rst_stats.rst_done_cnt++; 1559 hdev->rst_stats.rst_fail_cnt = 0; 1560 1561 return ret; 1562 err_reset_lock: 1563 rtnl_unlock(); 1564 err_reset: 1565 hclgevf_reset_err_handle(hdev); 1566 1567 return ret; 1568 } 1569 1570 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1571 unsigned long *addr) 1572 { 1573 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1574 1575 /* return the highest priority reset level amongst all */ 1576 if (test_bit(HNAE3_VF_RESET, addr)) { 1577 rst_level = HNAE3_VF_RESET; 1578 clear_bit(HNAE3_VF_RESET, addr); 1579 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1580 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1581 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1582 rst_level = HNAE3_VF_FULL_RESET; 1583 clear_bit(HNAE3_VF_FULL_RESET, addr); 1584 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1585 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1586 rst_level = HNAE3_VF_PF_FUNC_RESET; 1587 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1588 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1589 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1590 rst_level = HNAE3_VF_FUNC_RESET; 1591 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1592 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 1593 rst_level = HNAE3_FLR_RESET; 1594 clear_bit(HNAE3_FLR_RESET, addr); 1595 } 1596 1597 return rst_level; 1598 } 1599 1600 static void hclgevf_reset_event(struct pci_dev *pdev, 1601 struct hnae3_handle *handle) 1602 { 1603 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1604 struct hclgevf_dev *hdev = ae_dev->priv; 1605 1606 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 1607 1608 if (hdev->default_reset_request) 1609 hdev->reset_level = 1610 hclgevf_get_reset_level(hdev, 1611 &hdev->default_reset_request); 1612 else 1613 hdev->reset_level = HNAE3_VF_FUNC_RESET; 1614 1615 /* reset of this VF requested */ 1616 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1617 hclgevf_reset_task_schedule(hdev); 1618 1619 hdev->last_reset_time = jiffies; 1620 } 1621 1622 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1623 enum hnae3_reset_type rst_type) 1624 { 1625 struct hclgevf_dev *hdev = ae_dev->priv; 1626 1627 set_bit(rst_type, &hdev->default_reset_request); 1628 } 1629 1630 static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 1631 { 1632 #define HCLGEVF_FLR_WAIT_MS 100 1633 #define HCLGEVF_FLR_WAIT_CNT 50 1634 struct hclgevf_dev *hdev = ae_dev->priv; 1635 int cnt = 0; 1636 1637 clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1638 clear_bit(HNAE3_FLR_DONE, &hdev->flr_state); 1639 set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request); 1640 hclgevf_reset_event(hdev->pdev, NULL); 1641 1642 while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) && 1643 cnt++ < HCLGEVF_FLR_WAIT_CNT) 1644 msleep(HCLGEVF_FLR_WAIT_MS); 1645 1646 if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state)) 1647 dev_err(&hdev->pdev->dev, 1648 "flr wait down timeout: %d\n", cnt); 1649 } 1650 1651 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1652 { 1653 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1654 1655 return hdev->fw_version; 1656 } 1657 1658 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1659 { 1660 struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1661 1662 vector->vector_irq = pci_irq_vector(hdev->pdev, 1663 HCLGEVF_MISC_VECTOR_NUM); 1664 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1665 /* vector status always valid for Vector 0 */ 1666 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1667 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1668 1669 hdev->num_msi_left -= 1; 1670 hdev->num_msi_used += 1; 1671 } 1672 1673 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 1674 { 1675 if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) && 1676 !test_bit(HCLGEVF_STATE_REMOVING, &hdev->state)) { 1677 set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 1678 schedule_work(&hdev->rst_service_task); 1679 } 1680 } 1681 1682 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1683 { 1684 if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) && 1685 !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) { 1686 set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1687 schedule_work(&hdev->mbx_service_task); 1688 } 1689 } 1690 1691 static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 1692 { 1693 if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 1694 !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 1695 schedule_work(&hdev->service_task); 1696 } 1697 1698 static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev) 1699 { 1700 /* if we have any pending mailbox event then schedule the mbx task */ 1701 if (hdev->mbx_event_pending) 1702 hclgevf_mbx_task_schedule(hdev); 1703 1704 if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state)) 1705 hclgevf_reset_task_schedule(hdev); 1706 } 1707 1708 static void hclgevf_service_timer(struct timer_list *t) 1709 { 1710 struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 1711 1712 mod_timer(&hdev->service_timer, jiffies + 1713 HCLGEVF_GENERAL_TASK_INTERVAL * HZ); 1714 1715 hdev->stats_timer++; 1716 hclgevf_task_schedule(hdev); 1717 } 1718 1719 static void hclgevf_reset_service_task(struct work_struct *work) 1720 { 1721 struct hclgevf_dev *hdev = 1722 container_of(work, struct hclgevf_dev, rst_service_task); 1723 int ret; 1724 1725 if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1726 return; 1727 1728 clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 1729 1730 if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1731 &hdev->reset_state)) { 1732 /* PF has initmated that it is about to reset the hardware. 1733 * We now have to poll & check if hardware has actually 1734 * completed the reset sequence. On hardware reset completion, 1735 * VF needs to reset the client and ae device. 1736 */ 1737 hdev->reset_attempts = 0; 1738 1739 hdev->last_reset_time = jiffies; 1740 while ((hdev->reset_type = 1741 hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 1742 != HNAE3_NONE_RESET) { 1743 ret = hclgevf_reset(hdev); 1744 if (ret) 1745 dev_err(&hdev->pdev->dev, 1746 "VF stack reset failed %d.\n", ret); 1747 } 1748 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1749 &hdev->reset_state)) { 1750 /* we could be here when either of below happens: 1751 * 1. reset was initiated due to watchdog timeout caused by 1752 * a. IMP was earlier reset and our TX got choked down and 1753 * which resulted in watchdog reacting and inducing VF 1754 * reset. This also means our cmdq would be unreliable. 1755 * b. problem in TX due to other lower layer(example link 1756 * layer not functioning properly etc.) 1757 * 2. VF reset might have been initiated due to some config 1758 * change. 1759 * 1760 * NOTE: Theres no clear way to detect above cases than to react 1761 * to the response of PF for this reset request. PF will ack the 1762 * 1b and 2. cases but we will not get any intimation about 1a 1763 * from PF as cmdq would be in unreliable state i.e. mailbox 1764 * communication between PF and VF would be broken. 1765 */ 1766 1767 /* if we are never geting into pending state it means either: 1768 * 1. PF is not receiving our request which could be due to IMP 1769 * reset 1770 * 2. PF is screwed 1771 * We cannot do much for 2. but to check first we can try reset 1772 * our PCIe + stack and see if it alleviates the problem. 1773 */ 1774 if (hdev->reset_attempts > 3) { 1775 /* prepare for full reset of stack + pcie interface */ 1776 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1777 1778 /* "defer" schedule the reset task again */ 1779 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1780 } else { 1781 hdev->reset_attempts++; 1782 1783 set_bit(hdev->reset_level, &hdev->reset_pending); 1784 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1785 } 1786 hclgevf_reset_task_schedule(hdev); 1787 } 1788 1789 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1790 } 1791 1792 static void hclgevf_mailbox_service_task(struct work_struct *work) 1793 { 1794 struct hclgevf_dev *hdev; 1795 1796 hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 1797 1798 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1799 return; 1800 1801 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1802 1803 hclgevf_mbx_async_handler(hdev); 1804 1805 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1806 } 1807 1808 static void hclgevf_keep_alive_timer(struct timer_list *t) 1809 { 1810 struct hclgevf_dev *hdev = from_timer(hdev, t, keep_alive_timer); 1811 1812 schedule_work(&hdev->keep_alive_task); 1813 mod_timer(&hdev->keep_alive_timer, jiffies + 1814 HCLGEVF_KEEP_ALIVE_TASK_INTERVAL * HZ); 1815 } 1816 1817 static void hclgevf_keep_alive_task(struct work_struct *work) 1818 { 1819 struct hclgevf_dev *hdev; 1820 u8 respmsg; 1821 int ret; 1822 1823 hdev = container_of(work, struct hclgevf_dev, keep_alive_task); 1824 1825 if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 1826 return; 1827 1828 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL, 1829 0, false, &respmsg, sizeof(respmsg)); 1830 if (ret) 1831 dev_err(&hdev->pdev->dev, 1832 "VF sends keep alive cmd failed(=%d)\n", ret); 1833 } 1834 1835 static void hclgevf_service_task(struct work_struct *work) 1836 { 1837 struct hnae3_handle *handle; 1838 struct hclgevf_dev *hdev; 1839 1840 hdev = container_of(work, struct hclgevf_dev, service_task); 1841 handle = &hdev->nic; 1842 1843 if (hdev->stats_timer >= HCLGEVF_STATS_TIMER_INTERVAL) { 1844 hclgevf_tqps_update_stats(handle); 1845 hdev->stats_timer = 0; 1846 } 1847 1848 /* request the link status from the PF. PF would be able to tell VF 1849 * about such updates in future so we might remove this later 1850 */ 1851 hclgevf_request_link_info(hdev); 1852 1853 hclgevf_update_link_mode(hdev); 1854 1855 hclgevf_sync_vlan_filter(hdev); 1856 1857 hclgevf_deferred_task_schedule(hdev); 1858 1859 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1860 } 1861 1862 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1863 { 1864 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1865 } 1866 1867 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1868 u32 *clearval) 1869 { 1870 u32 cmdq_src_reg, rst_ing_reg; 1871 1872 /* fetch the events from their corresponding regs */ 1873 cmdq_src_reg = hclgevf_read_dev(&hdev->hw, 1874 HCLGEVF_VECTOR0_CMDQ_SRC_REG); 1875 1876 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_src_reg) { 1877 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1878 dev_info(&hdev->pdev->dev, 1879 "receive reset interrupt 0x%x!\n", rst_ing_reg); 1880 set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1881 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1882 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1883 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RST_INT_B); 1884 *clearval = cmdq_src_reg; 1885 hdev->rst_stats.vf_rst_cnt++; 1886 return HCLGEVF_VECTOR0_EVENT_RST; 1887 } 1888 1889 /* check for vector0 mailbox(=CMDQ RX) event source */ 1890 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 1891 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1892 *clearval = cmdq_src_reg; 1893 return HCLGEVF_VECTOR0_EVENT_MBX; 1894 } 1895 1896 dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 1897 1898 return HCLGEVF_VECTOR0_EVENT_OTHER; 1899 } 1900 1901 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1902 { 1903 writel(en ? 1 : 0, vector->addr); 1904 } 1905 1906 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1907 { 1908 enum hclgevf_evt_cause event_cause; 1909 struct hclgevf_dev *hdev = data; 1910 u32 clearval; 1911 1912 hclgevf_enable_vector(&hdev->misc_vector, false); 1913 event_cause = hclgevf_check_evt_cause(hdev, &clearval); 1914 1915 switch (event_cause) { 1916 case HCLGEVF_VECTOR0_EVENT_RST: 1917 hclgevf_reset_task_schedule(hdev); 1918 break; 1919 case HCLGEVF_VECTOR0_EVENT_MBX: 1920 hclgevf_mbx_handler(hdev); 1921 break; 1922 default: 1923 break; 1924 } 1925 1926 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 1927 hclgevf_clear_event_cause(hdev, clearval); 1928 hclgevf_enable_vector(&hdev->misc_vector, true); 1929 } 1930 1931 return IRQ_HANDLED; 1932 } 1933 1934 static int hclgevf_configure(struct hclgevf_dev *hdev) 1935 { 1936 int ret; 1937 1938 /* get current port based vlan state from PF */ 1939 ret = hclgevf_get_port_base_vlan_filter_state(hdev); 1940 if (ret) 1941 return ret; 1942 1943 /* get queue configuration from PF */ 1944 ret = hclgevf_get_queue_info(hdev); 1945 if (ret) 1946 return ret; 1947 1948 /* get queue depth info from PF */ 1949 ret = hclgevf_get_queue_depth(hdev); 1950 if (ret) 1951 return ret; 1952 1953 ret = hclgevf_get_pf_media_type(hdev); 1954 if (ret) 1955 return ret; 1956 1957 /* get tc configuration from PF */ 1958 return hclgevf_get_tc_info(hdev); 1959 } 1960 1961 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 1962 { 1963 struct pci_dev *pdev = ae_dev->pdev; 1964 struct hclgevf_dev *hdev; 1965 1966 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 1967 if (!hdev) 1968 return -ENOMEM; 1969 1970 hdev->pdev = pdev; 1971 hdev->ae_dev = ae_dev; 1972 ae_dev->priv = hdev; 1973 1974 return 0; 1975 } 1976 1977 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 1978 { 1979 struct hnae3_handle *roce = &hdev->roce; 1980 struct hnae3_handle *nic = &hdev->nic; 1981 1982 roce->rinfo.num_vectors = hdev->num_roce_msix; 1983 1984 if (hdev->num_msi_left < roce->rinfo.num_vectors || 1985 hdev->num_msi_left == 0) 1986 return -EINVAL; 1987 1988 roce->rinfo.base_vector = hdev->roce_base_vector; 1989 1990 roce->rinfo.netdev = nic->kinfo.netdev; 1991 roce->rinfo.roce_io_base = hdev->hw.io_base; 1992 1993 roce->pdev = nic->pdev; 1994 roce->ae_algo = nic->ae_algo; 1995 roce->numa_node_mask = nic->numa_node_mask; 1996 1997 return 0; 1998 } 1999 2000 static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 2001 { 2002 struct hclgevf_cfg_gro_status_cmd *req; 2003 struct hclgevf_desc desc; 2004 int ret; 2005 2006 if (!hnae3_dev_gro_supported(hdev)) 2007 return 0; 2008 2009 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 2010 false); 2011 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2012 2013 req->gro_en = cpu_to_le16(en ? 1 : 0); 2014 2015 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2016 if (ret) 2017 dev_err(&hdev->pdev->dev, 2018 "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2019 2020 return ret; 2021 } 2022 2023 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2024 { 2025 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2026 int i, ret; 2027 2028 rss_cfg->rss_size = hdev->rss_size_max; 2029 2030 if (hdev->pdev->revision >= 0x21) { 2031 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 2032 memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 2033 HCLGEVF_RSS_KEY_SIZE); 2034 2035 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 2036 rss_cfg->rss_hash_key); 2037 if (ret) 2038 return ret; 2039 2040 rss_cfg->rss_tuple_sets.ipv4_tcp_en = 2041 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2042 rss_cfg->rss_tuple_sets.ipv4_udp_en = 2043 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2044 rss_cfg->rss_tuple_sets.ipv4_sctp_en = 2045 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2046 rss_cfg->rss_tuple_sets.ipv4_fragment_en = 2047 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2048 rss_cfg->rss_tuple_sets.ipv6_tcp_en = 2049 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2050 rss_cfg->rss_tuple_sets.ipv6_udp_en = 2051 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2052 rss_cfg->rss_tuple_sets.ipv6_sctp_en = 2053 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2054 rss_cfg->rss_tuple_sets.ipv6_fragment_en = 2055 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2056 2057 ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 2058 if (ret) 2059 return ret; 2060 2061 } 2062 2063 /* Initialize RSS indirect table */ 2064 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 2065 rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max; 2066 2067 ret = hclgevf_set_rss_indir_table(hdev); 2068 if (ret) 2069 return ret; 2070 2071 return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max); 2072 } 2073 2074 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2075 { 2076 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2077 false); 2078 } 2079 2080 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 2081 { 2082 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2083 2084 if (enable) { 2085 mod_timer(&hdev->service_timer, jiffies + HZ); 2086 } else { 2087 del_timer_sync(&hdev->service_timer); 2088 cancel_work_sync(&hdev->service_task); 2089 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2090 } 2091 } 2092 2093 static int hclgevf_ae_start(struct hnae3_handle *handle) 2094 { 2095 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2096 2097 hclgevf_reset_tqp_stats(handle); 2098 2099 hclgevf_request_link_info(hdev); 2100 2101 hclgevf_update_link_mode(hdev); 2102 2103 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2104 2105 return 0; 2106 } 2107 2108 static void hclgevf_ae_stop(struct hnae3_handle *handle) 2109 { 2110 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2111 int i; 2112 2113 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2114 2115 if (hdev->reset_type != HNAE3_VF_RESET) 2116 for (i = 0; i < handle->kinfo.num_tqps; i++) 2117 if (hclgevf_reset_tqp(handle, i)) 2118 break; 2119 2120 hclgevf_reset_tqp_stats(handle); 2121 hclgevf_update_link_status(hdev, 0); 2122 } 2123 2124 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2125 { 2126 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2127 u8 msg_data; 2128 2129 msg_data = alive ? 1 : 0; 2130 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE, 2131 0, &msg_data, 1, false, NULL, 0); 2132 } 2133 2134 static int hclgevf_client_start(struct hnae3_handle *handle) 2135 { 2136 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2137 int ret; 2138 2139 ret = hclgevf_set_alive(handle, true); 2140 if (ret) 2141 return ret; 2142 2143 mod_timer(&hdev->keep_alive_timer, jiffies + 2144 HCLGEVF_KEEP_ALIVE_TASK_INTERVAL * HZ); 2145 2146 return 0; 2147 } 2148 2149 static void hclgevf_client_stop(struct hnae3_handle *handle) 2150 { 2151 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2152 int ret; 2153 2154 ret = hclgevf_set_alive(handle, false); 2155 if (ret) 2156 dev_warn(&hdev->pdev->dev, 2157 "%s failed %d\n", __func__, ret); 2158 2159 del_timer_sync(&hdev->keep_alive_timer); 2160 cancel_work_sync(&hdev->keep_alive_task); 2161 } 2162 2163 static void hclgevf_state_init(struct hclgevf_dev *hdev) 2164 { 2165 /* setup tasks for the MBX */ 2166 INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 2167 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2168 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2169 2170 /* setup tasks for service timer */ 2171 timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 2172 2173 INIT_WORK(&hdev->service_task, hclgevf_service_task); 2174 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2175 2176 INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task); 2177 2178 mutex_init(&hdev->mbx_resp.mbx_mutex); 2179 2180 /* bring the device down */ 2181 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2182 } 2183 2184 static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2185 { 2186 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2187 set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2188 2189 if (hdev->keep_alive_timer.function) 2190 del_timer_sync(&hdev->keep_alive_timer); 2191 if (hdev->keep_alive_task.func) 2192 cancel_work_sync(&hdev->keep_alive_task); 2193 if (hdev->service_timer.function) 2194 del_timer_sync(&hdev->service_timer); 2195 if (hdev->service_task.func) 2196 cancel_work_sync(&hdev->service_task); 2197 if (hdev->mbx_service_task.func) 2198 cancel_work_sync(&hdev->mbx_service_task); 2199 if (hdev->rst_service_task.func) 2200 cancel_work_sync(&hdev->rst_service_task); 2201 2202 mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2203 } 2204 2205 static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2206 { 2207 struct pci_dev *pdev = hdev->pdev; 2208 int vectors; 2209 int i; 2210 2211 if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) 2212 vectors = pci_alloc_irq_vectors(pdev, 2213 hdev->roce_base_msix_offset + 1, 2214 hdev->num_msi, 2215 PCI_IRQ_MSIX); 2216 else 2217 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 2218 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2219 2220 if (vectors < 0) { 2221 dev_err(&pdev->dev, 2222 "failed(%d) to allocate MSI/MSI-X vectors\n", 2223 vectors); 2224 return vectors; 2225 } 2226 if (vectors < hdev->num_msi) 2227 dev_warn(&hdev->pdev->dev, 2228 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2229 hdev->num_msi, vectors); 2230 2231 hdev->num_msi = vectors; 2232 hdev->num_msi_left = vectors; 2233 hdev->base_msi_vector = pdev->irq; 2234 hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2235 2236 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2237 sizeof(u16), GFP_KERNEL); 2238 if (!hdev->vector_status) { 2239 pci_free_irq_vectors(pdev); 2240 return -ENOMEM; 2241 } 2242 2243 for (i = 0; i < hdev->num_msi; i++) 2244 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2245 2246 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2247 sizeof(int), GFP_KERNEL); 2248 if (!hdev->vector_irq) { 2249 devm_kfree(&pdev->dev, hdev->vector_status); 2250 pci_free_irq_vectors(pdev); 2251 return -ENOMEM; 2252 } 2253 2254 return 0; 2255 } 2256 2257 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2258 { 2259 struct pci_dev *pdev = hdev->pdev; 2260 2261 devm_kfree(&pdev->dev, hdev->vector_status); 2262 devm_kfree(&pdev->dev, hdev->vector_irq); 2263 pci_free_irq_vectors(pdev); 2264 } 2265 2266 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2267 { 2268 int ret = 0; 2269 2270 hclgevf_get_misc_vector(hdev); 2271 2272 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2273 0, "hclgevf_cmd", hdev); 2274 if (ret) { 2275 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2276 hdev->misc_vector.vector_irq); 2277 return ret; 2278 } 2279 2280 hclgevf_clear_event_cause(hdev, 0); 2281 2282 /* enable misc. vector(vector 0) */ 2283 hclgevf_enable_vector(&hdev->misc_vector, true); 2284 2285 return ret; 2286 } 2287 2288 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2289 { 2290 /* disable misc vector(vector 0) */ 2291 hclgevf_enable_vector(&hdev->misc_vector, false); 2292 synchronize_irq(hdev->misc_vector.vector_irq); 2293 free_irq(hdev->misc_vector.vector_irq, hdev); 2294 hclgevf_free_vector(hdev, 0); 2295 } 2296 2297 static void hclgevf_info_show(struct hclgevf_dev *hdev) 2298 { 2299 struct device *dev = &hdev->pdev->dev; 2300 2301 dev_info(dev, "VF info begin:\n"); 2302 2303 dev_info(dev, "Task queue pairs numbers: %d\n", hdev->num_tqps); 2304 dev_info(dev, "Desc num per TX queue: %d\n", hdev->num_tx_desc); 2305 dev_info(dev, "Desc num per RX queue: %d\n", hdev->num_rx_desc); 2306 dev_info(dev, "Numbers of vports: %d\n", hdev->num_alloc_vport); 2307 dev_info(dev, "HW tc map: %d\n", hdev->hw_tc_map); 2308 dev_info(dev, "PF media type of this VF: %d\n", 2309 hdev->hw.mac.media_type); 2310 2311 dev_info(dev, "VF info end.\n"); 2312 } 2313 2314 static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 2315 struct hnae3_client *client) 2316 { 2317 struct hclgevf_dev *hdev = ae_dev->priv; 2318 int ret; 2319 2320 ret = client->ops->init_instance(&hdev->nic); 2321 if (ret) 2322 return ret; 2323 2324 set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2325 hnae3_set_client_init_flag(client, ae_dev, 1); 2326 2327 if (netif_msg_drv(&hdev->nic)) 2328 hclgevf_info_show(hdev); 2329 2330 return 0; 2331 } 2332 2333 static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 2334 struct hnae3_client *client) 2335 { 2336 struct hclgevf_dev *hdev = ae_dev->priv; 2337 int ret; 2338 2339 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 2340 !hdev->nic_client) 2341 return 0; 2342 2343 ret = hclgevf_init_roce_base_info(hdev); 2344 if (ret) 2345 return ret; 2346 2347 ret = client->ops->init_instance(&hdev->roce); 2348 if (ret) 2349 return ret; 2350 2351 hnae3_set_client_init_flag(client, ae_dev, 1); 2352 2353 return 0; 2354 } 2355 2356 static int hclgevf_init_client_instance(struct hnae3_client *client, 2357 struct hnae3_ae_dev *ae_dev) 2358 { 2359 struct hclgevf_dev *hdev = ae_dev->priv; 2360 int ret; 2361 2362 switch (client->type) { 2363 case HNAE3_CLIENT_KNIC: 2364 hdev->nic_client = client; 2365 hdev->nic.client = client; 2366 2367 ret = hclgevf_init_nic_client_instance(ae_dev, client); 2368 if (ret) 2369 goto clear_nic; 2370 2371 ret = hclgevf_init_roce_client_instance(ae_dev, 2372 hdev->roce_client); 2373 if (ret) 2374 goto clear_roce; 2375 2376 break; 2377 case HNAE3_CLIENT_ROCE: 2378 if (hnae3_dev_roce_supported(hdev)) { 2379 hdev->roce_client = client; 2380 hdev->roce.client = client; 2381 } 2382 2383 ret = hclgevf_init_roce_client_instance(ae_dev, client); 2384 if (ret) 2385 goto clear_roce; 2386 2387 break; 2388 default: 2389 return -EINVAL; 2390 } 2391 2392 return 0; 2393 2394 clear_nic: 2395 hdev->nic_client = NULL; 2396 hdev->nic.client = NULL; 2397 return ret; 2398 clear_roce: 2399 hdev->roce_client = NULL; 2400 hdev->roce.client = NULL; 2401 return ret; 2402 } 2403 2404 static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2405 struct hnae3_ae_dev *ae_dev) 2406 { 2407 struct hclgevf_dev *hdev = ae_dev->priv; 2408 2409 /* un-init roce, if it exists */ 2410 if (hdev->roce_client) { 2411 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 2412 hdev->roce_client = NULL; 2413 hdev->roce.client = NULL; 2414 } 2415 2416 /* un-init nic/unic, if this was not called by roce client */ 2417 if (client->ops->uninit_instance && hdev->nic_client && 2418 client->type != HNAE3_CLIENT_ROCE) { 2419 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2420 2421 client->ops->uninit_instance(&hdev->nic, 0); 2422 hdev->nic_client = NULL; 2423 hdev->nic.client = NULL; 2424 } 2425 } 2426 2427 static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2428 { 2429 struct pci_dev *pdev = hdev->pdev; 2430 struct hclgevf_hw *hw; 2431 int ret; 2432 2433 ret = pci_enable_device(pdev); 2434 if (ret) { 2435 dev_err(&pdev->dev, "failed to enable PCI device\n"); 2436 return ret; 2437 } 2438 2439 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2440 if (ret) { 2441 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2442 goto err_disable_device; 2443 } 2444 2445 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2446 if (ret) { 2447 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2448 goto err_disable_device; 2449 } 2450 2451 pci_set_master(pdev); 2452 hw = &hdev->hw; 2453 hw->hdev = hdev; 2454 hw->io_base = pci_iomap(pdev, 2, 0); 2455 if (!hw->io_base) { 2456 dev_err(&pdev->dev, "can't map configuration register space\n"); 2457 ret = -ENOMEM; 2458 goto err_clr_master; 2459 } 2460 2461 return 0; 2462 2463 err_clr_master: 2464 pci_clear_master(pdev); 2465 pci_release_regions(pdev); 2466 err_disable_device: 2467 pci_disable_device(pdev); 2468 2469 return ret; 2470 } 2471 2472 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2473 { 2474 struct pci_dev *pdev = hdev->pdev; 2475 2476 pci_iounmap(pdev, hdev->hw.io_base); 2477 pci_clear_master(pdev); 2478 pci_release_regions(pdev); 2479 pci_disable_device(pdev); 2480 } 2481 2482 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 2483 { 2484 struct hclgevf_query_res_cmd *req; 2485 struct hclgevf_desc desc; 2486 int ret; 2487 2488 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 2489 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2490 if (ret) { 2491 dev_err(&hdev->pdev->dev, 2492 "query vf resource failed, ret = %d.\n", ret); 2493 return ret; 2494 } 2495 2496 req = (struct hclgevf_query_res_cmd *)desc.data; 2497 2498 if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) { 2499 hdev->roce_base_msix_offset = 2500 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 2501 HCLGEVF_MSIX_OFT_ROCEE_M, 2502 HCLGEVF_MSIX_OFT_ROCEE_S); 2503 hdev->num_roce_msix = 2504 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 2505 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2506 2507 /* VF should have NIC vectors and Roce vectors, NIC vectors 2508 * are queued before Roce vectors. The offset is fixed to 64. 2509 */ 2510 hdev->num_msi = hdev->num_roce_msix + 2511 hdev->roce_base_msix_offset; 2512 } else { 2513 hdev->num_msi = 2514 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 2515 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2516 } 2517 2518 return 0; 2519 } 2520 2521 static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2522 { 2523 struct pci_dev *pdev = hdev->pdev; 2524 int ret = 0; 2525 2526 if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2527 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2528 hclgevf_misc_irq_uninit(hdev); 2529 hclgevf_uninit_msi(hdev); 2530 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2531 } 2532 2533 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2534 pci_set_master(pdev); 2535 ret = hclgevf_init_msi(hdev); 2536 if (ret) { 2537 dev_err(&pdev->dev, 2538 "failed(%d) to init MSI/MSI-X\n", ret); 2539 return ret; 2540 } 2541 2542 ret = hclgevf_misc_irq_init(hdev); 2543 if (ret) { 2544 hclgevf_uninit_msi(hdev); 2545 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2546 ret); 2547 return ret; 2548 } 2549 2550 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2551 } 2552 2553 return ret; 2554 } 2555 2556 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2557 { 2558 struct pci_dev *pdev = hdev->pdev; 2559 int ret; 2560 2561 ret = hclgevf_pci_reset(hdev); 2562 if (ret) { 2563 dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2564 return ret; 2565 } 2566 2567 ret = hclgevf_cmd_init(hdev); 2568 if (ret) { 2569 dev_err(&pdev->dev, "cmd failed %d\n", ret); 2570 return ret; 2571 } 2572 2573 ret = hclgevf_rss_init_hw(hdev); 2574 if (ret) { 2575 dev_err(&hdev->pdev->dev, 2576 "failed(%d) to initialize RSS\n", ret); 2577 return ret; 2578 } 2579 2580 ret = hclgevf_config_gro(hdev, true); 2581 if (ret) 2582 return ret; 2583 2584 ret = hclgevf_init_vlan_config(hdev); 2585 if (ret) { 2586 dev_err(&hdev->pdev->dev, 2587 "failed(%d) to initialize VLAN config\n", ret); 2588 return ret; 2589 } 2590 2591 if (pdev->revision >= 0x21) { 2592 ret = hclgevf_set_promisc_mode(hdev, true); 2593 if (ret) 2594 return ret; 2595 } 2596 2597 dev_info(&hdev->pdev->dev, "Reset done\n"); 2598 2599 return 0; 2600 } 2601 2602 static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 2603 { 2604 struct pci_dev *pdev = hdev->pdev; 2605 int ret; 2606 2607 ret = hclgevf_pci_init(hdev); 2608 if (ret) { 2609 dev_err(&pdev->dev, "PCI initialization failed\n"); 2610 return ret; 2611 } 2612 2613 ret = hclgevf_cmd_queue_init(hdev); 2614 if (ret) { 2615 dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret); 2616 goto err_cmd_queue_init; 2617 } 2618 2619 ret = hclgevf_cmd_init(hdev); 2620 if (ret) 2621 goto err_cmd_init; 2622 2623 /* Get vf resource */ 2624 ret = hclgevf_query_vf_resource(hdev); 2625 if (ret) { 2626 dev_err(&hdev->pdev->dev, 2627 "Query vf status error, ret = %d.\n", ret); 2628 goto err_cmd_init; 2629 } 2630 2631 ret = hclgevf_init_msi(hdev); 2632 if (ret) { 2633 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 2634 goto err_cmd_init; 2635 } 2636 2637 hclgevf_state_init(hdev); 2638 hdev->reset_level = HNAE3_VF_FUNC_RESET; 2639 2640 ret = hclgevf_misc_irq_init(hdev); 2641 if (ret) { 2642 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2643 ret); 2644 goto err_misc_irq_init; 2645 } 2646 2647 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2648 2649 ret = hclgevf_configure(hdev); 2650 if (ret) { 2651 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2652 goto err_config; 2653 } 2654 2655 ret = hclgevf_alloc_tqps(hdev); 2656 if (ret) { 2657 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2658 goto err_config; 2659 } 2660 2661 ret = hclgevf_set_handle_info(hdev); 2662 if (ret) { 2663 dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 2664 goto err_config; 2665 } 2666 2667 ret = hclgevf_config_gro(hdev, true); 2668 if (ret) 2669 goto err_config; 2670 2671 /* vf is not allowed to enable unicast/multicast promisc mode. 2672 * For revision 0x20, default to disable broadcast promisc mode, 2673 * firmware makes sure broadcast packets can be accepted. 2674 * For revision 0x21, default to enable broadcast promisc mode. 2675 */ 2676 if (pdev->revision >= 0x21) { 2677 ret = hclgevf_set_promisc_mode(hdev, true); 2678 if (ret) 2679 goto err_config; 2680 } 2681 2682 /* Initialize RSS for this VF */ 2683 ret = hclgevf_rss_init_hw(hdev); 2684 if (ret) { 2685 dev_err(&hdev->pdev->dev, 2686 "failed(%d) to initialize RSS\n", ret); 2687 goto err_config; 2688 } 2689 2690 ret = hclgevf_init_vlan_config(hdev); 2691 if (ret) { 2692 dev_err(&hdev->pdev->dev, 2693 "failed(%d) to initialize VLAN config\n", ret); 2694 goto err_config; 2695 } 2696 2697 hdev->last_reset_time = jiffies; 2698 dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 2699 HCLGEVF_DRIVER_NAME); 2700 2701 return 0; 2702 2703 err_config: 2704 hclgevf_misc_irq_uninit(hdev); 2705 err_misc_irq_init: 2706 hclgevf_state_uninit(hdev); 2707 hclgevf_uninit_msi(hdev); 2708 err_cmd_init: 2709 hclgevf_cmd_uninit(hdev); 2710 err_cmd_queue_init: 2711 hclgevf_pci_uninit(hdev); 2712 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2713 return ret; 2714 } 2715 2716 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2717 { 2718 hclgevf_state_uninit(hdev); 2719 2720 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2721 hclgevf_misc_irq_uninit(hdev); 2722 hclgevf_uninit_msi(hdev); 2723 } 2724 2725 hclgevf_pci_uninit(hdev); 2726 hclgevf_cmd_uninit(hdev); 2727 } 2728 2729 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 2730 { 2731 struct pci_dev *pdev = ae_dev->pdev; 2732 struct hclgevf_dev *hdev; 2733 int ret; 2734 2735 ret = hclgevf_alloc_hdev(ae_dev); 2736 if (ret) { 2737 dev_err(&pdev->dev, "hclge device allocation failed\n"); 2738 return ret; 2739 } 2740 2741 ret = hclgevf_init_hdev(ae_dev->priv); 2742 if (ret) { 2743 dev_err(&pdev->dev, "hclge device initialization failed\n"); 2744 return ret; 2745 } 2746 2747 hdev = ae_dev->priv; 2748 timer_setup(&hdev->keep_alive_timer, hclgevf_keep_alive_timer, 0); 2749 INIT_WORK(&hdev->keep_alive_task, hclgevf_keep_alive_task); 2750 2751 return 0; 2752 } 2753 2754 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 2755 { 2756 struct hclgevf_dev *hdev = ae_dev->priv; 2757 2758 hclgevf_uninit_hdev(hdev); 2759 ae_dev->priv = NULL; 2760 } 2761 2762 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2763 { 2764 struct hnae3_handle *nic = &hdev->nic; 2765 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2766 2767 return min_t(u32, hdev->rss_size_max, 2768 hdev->num_tqps / kinfo->num_tc); 2769 } 2770 2771 /** 2772 * hclgevf_get_channels - Get the current channels enabled and max supported. 2773 * @handle: hardware information for network interface 2774 * @ch: ethtool channels structure 2775 * 2776 * We don't support separate tx and rx queues as channels. The other count 2777 * represents how many queues are being used for control. max_combined counts 2778 * how many queue pairs we can support. They may not be mapped 1 to 1 with 2779 * q_vectors since we support a lot more queue pairs than q_vectors. 2780 **/ 2781 static void hclgevf_get_channels(struct hnae3_handle *handle, 2782 struct ethtool_channels *ch) 2783 { 2784 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2785 2786 ch->max_combined = hclgevf_get_max_channels(hdev); 2787 ch->other_count = 0; 2788 ch->max_other = 0; 2789 ch->combined_count = handle->kinfo.rss_size; 2790 } 2791 2792 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 2793 u16 *alloc_tqps, u16 *max_rss_size) 2794 { 2795 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2796 2797 *alloc_tqps = hdev->num_tqps; 2798 *max_rss_size = hdev->rss_size_max; 2799 } 2800 2801 static int hclgevf_get_status(struct hnae3_handle *handle) 2802 { 2803 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2804 2805 return hdev->hw.mac.link; 2806 } 2807 2808 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 2809 u8 *auto_neg, u32 *speed, 2810 u8 *duplex) 2811 { 2812 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2813 2814 if (speed) 2815 *speed = hdev->hw.mac.speed; 2816 if (duplex) 2817 *duplex = hdev->hw.mac.duplex; 2818 if (auto_neg) 2819 *auto_neg = AUTONEG_DISABLE; 2820 } 2821 2822 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 2823 u8 duplex) 2824 { 2825 hdev->hw.mac.speed = speed; 2826 hdev->hw.mac.duplex = duplex; 2827 } 2828 2829 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 2830 { 2831 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2832 2833 return hclgevf_config_gro(hdev, enable); 2834 } 2835 2836 static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 2837 u8 *module_type) 2838 { 2839 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2840 2841 if (media_type) 2842 *media_type = hdev->hw.mac.media_type; 2843 2844 if (module_type) 2845 *module_type = hdev->hw.mac.module_type; 2846 } 2847 2848 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 2849 { 2850 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2851 2852 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 2853 } 2854 2855 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 2856 { 2857 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2858 2859 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2860 } 2861 2862 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 2863 { 2864 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2865 2866 return hdev->rst_stats.hw_rst_done_cnt; 2867 } 2868 2869 static void hclgevf_get_link_mode(struct hnae3_handle *handle, 2870 unsigned long *supported, 2871 unsigned long *advertising) 2872 { 2873 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2874 2875 *supported = hdev->hw.mac.supported; 2876 *advertising = hdev->hw.mac.advertising; 2877 } 2878 2879 #define MAX_SEPARATE_NUM 4 2880 #define SEPARATOR_VALUE 0xFFFFFFFF 2881 #define REG_NUM_PER_LINE 4 2882 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 2883 2884 static int hclgevf_get_regs_len(struct hnae3_handle *handle) 2885 { 2886 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 2887 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2888 2889 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 2890 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 2891 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 2892 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 2893 2894 return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 2895 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 2896 } 2897 2898 static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 2899 void *data) 2900 { 2901 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2902 int i, j, reg_um, separator_num; 2903 u32 *reg = data; 2904 2905 *version = hdev->fw_version; 2906 2907 /* fetching per-VF registers values from VF PCIe register space */ 2908 reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 2909 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2910 for (i = 0; i < reg_um; i++) 2911 *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 2912 for (i = 0; i < separator_num; i++) 2913 *reg++ = SEPARATOR_VALUE; 2914 2915 reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 2916 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2917 for (i = 0; i < reg_um; i++) 2918 *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 2919 for (i = 0; i < separator_num; i++) 2920 *reg++ = SEPARATOR_VALUE; 2921 2922 reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 2923 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2924 for (j = 0; j < hdev->num_tqps; j++) { 2925 for (i = 0; i < reg_um; i++) 2926 *reg++ = hclgevf_read_dev(&hdev->hw, 2927 ring_reg_addr_list[i] + 2928 0x200 * j); 2929 for (i = 0; i < separator_num; i++) 2930 *reg++ = SEPARATOR_VALUE; 2931 } 2932 2933 reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 2934 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2935 for (j = 0; j < hdev->num_msi_used - 1; j++) { 2936 for (i = 0; i < reg_um; i++) 2937 *reg++ = hclgevf_read_dev(&hdev->hw, 2938 tqp_intr_reg_addr_list[i] + 2939 4 * j); 2940 for (i = 0; i < separator_num; i++) 2941 *reg++ = SEPARATOR_VALUE; 2942 } 2943 } 2944 2945 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 2946 u8 *port_base_vlan_info, u8 data_size) 2947 { 2948 struct hnae3_handle *nic = &hdev->nic; 2949 2950 rtnl_lock(); 2951 hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 2952 rtnl_unlock(); 2953 2954 /* send msg to PF and wait update port based vlan info */ 2955 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 2956 HCLGE_MBX_PORT_BASE_VLAN_CFG, 2957 port_base_vlan_info, data_size, 2958 false, NULL, 0); 2959 2960 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 2961 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 2962 else 2963 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 2964 2965 rtnl_lock(); 2966 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 2967 rtnl_unlock(); 2968 } 2969 2970 static const struct hnae3_ae_ops hclgevf_ops = { 2971 .init_ae_dev = hclgevf_init_ae_dev, 2972 .uninit_ae_dev = hclgevf_uninit_ae_dev, 2973 .flr_prepare = hclgevf_flr_prepare, 2974 .flr_done = hclgevf_flr_done, 2975 .init_client_instance = hclgevf_init_client_instance, 2976 .uninit_client_instance = hclgevf_uninit_client_instance, 2977 .start = hclgevf_ae_start, 2978 .stop = hclgevf_ae_stop, 2979 .client_start = hclgevf_client_start, 2980 .client_stop = hclgevf_client_stop, 2981 .map_ring_to_vector = hclgevf_map_ring_to_vector, 2982 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 2983 .get_vector = hclgevf_get_vector, 2984 .put_vector = hclgevf_put_vector, 2985 .reset_queue = hclgevf_reset_tqp, 2986 .get_mac_addr = hclgevf_get_mac_addr, 2987 .set_mac_addr = hclgevf_set_mac_addr, 2988 .add_uc_addr = hclgevf_add_uc_addr, 2989 .rm_uc_addr = hclgevf_rm_uc_addr, 2990 .add_mc_addr = hclgevf_add_mc_addr, 2991 .rm_mc_addr = hclgevf_rm_mc_addr, 2992 .get_stats = hclgevf_get_stats, 2993 .update_stats = hclgevf_update_stats, 2994 .get_strings = hclgevf_get_strings, 2995 .get_sset_count = hclgevf_get_sset_count, 2996 .get_rss_key_size = hclgevf_get_rss_key_size, 2997 .get_rss_indir_size = hclgevf_get_rss_indir_size, 2998 .get_rss = hclgevf_get_rss, 2999 .set_rss = hclgevf_set_rss, 3000 .get_rss_tuple = hclgevf_get_rss_tuple, 3001 .set_rss_tuple = hclgevf_set_rss_tuple, 3002 .get_tc_size = hclgevf_get_tc_size, 3003 .get_fw_version = hclgevf_get_fw_version, 3004 .set_vlan_filter = hclgevf_set_vlan_filter, 3005 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 3006 .reset_event = hclgevf_reset_event, 3007 .set_default_reset_request = hclgevf_set_def_reset_request, 3008 .get_channels = hclgevf_get_channels, 3009 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 3010 .get_regs_len = hclgevf_get_regs_len, 3011 .get_regs = hclgevf_get_regs, 3012 .get_status = hclgevf_get_status, 3013 .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3014 .get_media_type = hclgevf_get_media_type, 3015 .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 3016 .ae_dev_resetting = hclgevf_ae_dev_resetting, 3017 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 3018 .set_gro_en = hclgevf_gro_en, 3019 .set_mtu = hclgevf_set_mtu, 3020 .get_global_queue_id = hclgevf_get_qid_global, 3021 .set_timer_task = hclgevf_set_timer_task, 3022 .get_link_mode = hclgevf_get_link_mode, 3023 }; 3024 3025 static struct hnae3_ae_algo ae_algovf = { 3026 .ops = &hclgevf_ops, 3027 .pdev_id_table = ae_algovf_pci_tbl, 3028 }; 3029 3030 static int hclgevf_init(void) 3031 { 3032 pr_info("%s is initializing\n", HCLGEVF_NAME); 3033 3034 hnae3_register_ae_algo(&ae_algovf); 3035 3036 return 0; 3037 } 3038 3039 static void hclgevf_exit(void) 3040 { 3041 hnae3_unregister_ae_algo(&ae_algovf); 3042 } 3043 module_init(hclgevf_init); 3044 module_exit(hclgevf_exit); 3045 3046 MODULE_LICENSE("GPL"); 3047 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3048 MODULE_DESCRIPTION("HCLGEVF Driver"); 3049 MODULE_VERSION(HCLGEVF_MOD_VERSION); 3050