1e2cb1decSSalil Mehta // SPDX-License-Identifier: GPL-2.0+ 2e2cb1decSSalil Mehta // Copyright (c) 2016-2017 Hisilicon Limited. 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #include <linux/etherdevice.h> 5aa5c4f17SHuazhong Tan #include <linux/iopoll.h> 66988eb2aSSalil Mehta #include <net/rtnetlink.h> 7e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 8e2cb1decSSalil Mehta #include "hclgevf_main.h" 9939ccd10SJijie Shao #include "hclgevf_regs.h" 10e2cb1decSSalil Mehta #include "hclge_mbx.h" 11e2cb1decSSalil Mehta #include "hnae3.h" 12cd624299SYufeng Mo #include "hclgevf_devlink.h" 13027733b1SJie Wang #include "hclge_comm_rss.h" 14e2cb1decSSalil Mehta 15e2cb1decSSalil Mehta #define HCLGEVF_NAME "hclgevf" 16e2cb1decSSalil Mehta 17bbe6540eSHuazhong Tan #define HCLGEVF_RESET_MAX_FAIL_CNT 5 18bbe6540eSHuazhong Tan 199c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 205e7414cdSJian Shen static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 215e7414cdSJian Shen unsigned long delay); 225e7414cdSJian Shen 23e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf; 24e2cb1decSSalil Mehta 250ea68902SYunsheng Lin static struct workqueue_struct *hclgevf_wq; 260ea68902SYunsheng Lin 27e2cb1decSSalil Mehta static const struct pci_device_id ae_algovf_pci_tbl[] = { 28c155e22bSGuangbin Huang {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0}, 29c155e22bSGuangbin Huang {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 30c155e22bSGuangbin Huang HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 31e2cb1decSSalil Mehta /* required last entry */ 32e2cb1decSSalil Mehta {0, } 33e2cb1decSSalil Mehta }; 34e2cb1decSSalil Mehta 352f550a46SYunsheng Lin MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 362f550a46SYunsheng Lin 37aab8d1c6SJie Wang /* hclgevf_cmd_send - send command to command queue 38aab8d1c6SJie Wang * @hw: pointer to the hw struct 39aab8d1c6SJie Wang * @desc: prefilled descriptor for describing the command 40aab8d1c6SJie Wang * @num : the number of descriptors to be sent 41aab8d1c6SJie Wang * 42aab8d1c6SJie Wang * This is the main send command for command queue, it 43aab8d1c6SJie Wang * sends the queue, cleans the queue, etc 44aab8d1c6SJie Wang */ 45aab8d1c6SJie Wang int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclge_desc *desc, int num) 46aab8d1c6SJie Wang { 479970308fSJie Wang return hclge_comm_cmd_send(&hw->hw, desc, num); 48aab8d1c6SJie Wang } 49aab8d1c6SJie Wang 50aab8d1c6SJie Wang void hclgevf_arq_init(struct hclgevf_dev *hdev) 51aab8d1c6SJie Wang { 52aab8d1c6SJie Wang struct hclge_comm_cmq *cmdq = &hdev->hw.hw.cmq; 53aab8d1c6SJie Wang 54aab8d1c6SJie Wang spin_lock(&cmdq->crq.lock); 55aab8d1c6SJie Wang /* initialize the pointers of async rx queue of mailbox */ 56aab8d1c6SJie Wang hdev->arq.hdev = hdev; 57aab8d1c6SJie Wang hdev->arq.head = 0; 58aab8d1c6SJie Wang hdev->arq.tail = 0; 59aab8d1c6SJie Wang atomic_set(&hdev->arq.count, 0); 60aab8d1c6SJie Wang spin_unlock(&cmdq->crq.lock); 61aab8d1c6SJie Wang } 62aab8d1c6SJie Wang 63939ccd10SJijie Shao struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 64e2cb1decSSalil Mehta { 65eed9535fSPeng Li if (!handle->client) 66eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, nic); 67eed9535fSPeng Li else if (handle->client->type == HNAE3_CLIENT_ROCE) 68eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, roce); 69eed9535fSPeng Li else 70e2cb1decSSalil Mehta return container_of(handle, struct hclgevf_dev, nic); 71e2cb1decSSalil Mehta } 72e2cb1decSSalil Mehta 73ed1c6f35SPeiyang Wang static void hclgevf_update_stats(struct hnae3_handle *handle) 74e2cb1decSSalil Mehta { 75e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 76e2cb1decSSalil Mehta int status; 77e2cb1decSSalil Mehta 784afc310cSJie Wang status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 79e2cb1decSSalil Mehta if (status) 80e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 81e2cb1decSSalil Mehta "VF update of TQPS stats fail, status = %d.\n", 82e2cb1decSSalil Mehta status); 83e2cb1decSSalil Mehta } 84e2cb1decSSalil Mehta 85e2cb1decSSalil Mehta static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 86e2cb1decSSalil Mehta { 87e2cb1decSSalil Mehta if (strset == ETH_SS_TEST) 88e2cb1decSSalil Mehta return -EOPNOTSUPP; 89e2cb1decSSalil Mehta else if (strset == ETH_SS_STATS) 904afc310cSJie Wang return hclge_comm_tqps_get_sset_count(handle); 91e2cb1decSSalil Mehta 92e2cb1decSSalil Mehta return 0; 93e2cb1decSSalil Mehta } 94e2cb1decSSalil Mehta 95e2cb1decSSalil Mehta static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 96e2cb1decSSalil Mehta u8 *data) 97e2cb1decSSalil Mehta { 98e2cb1decSSalil Mehta u8 *p = (char *)data; 99e2cb1decSSalil Mehta 100e2cb1decSSalil Mehta if (strset == ETH_SS_STATS) 1014afc310cSJie Wang p = hclge_comm_tqps_get_strings(handle, p); 102e2cb1decSSalil Mehta } 103e2cb1decSSalil Mehta 104e2cb1decSSalil Mehta static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 105e2cb1decSSalil Mehta { 1064afc310cSJie Wang hclge_comm_tqps_get_stats(handle, data); 107e2cb1decSSalil Mehta } 108e2cb1decSSalil Mehta 109d3410018SYufeng Mo static void hclgevf_build_send_msg(struct hclge_vf_to_pf_msg *msg, u8 code, 110d3410018SYufeng Mo u8 subcode) 111d3410018SYufeng Mo { 112d3410018SYufeng Mo if (msg) { 113d3410018SYufeng Mo memset(msg, 0, sizeof(struct hclge_vf_to_pf_msg)); 114d3410018SYufeng Mo msg->code = code; 115d3410018SYufeng Mo msg->subcode = subcode; 116d3410018SYufeng Mo } 117d3410018SYufeng Mo } 118d3410018SYufeng Mo 11932e6d104SJian Shen static int hclgevf_get_basic_info(struct hclgevf_dev *hdev) 120e2cb1decSSalil Mehta { 12132e6d104SJian Shen struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 12232e6d104SJian Shen u8 resp_msg[HCLGE_MBX_MAX_RESP_DATA_SIZE]; 12332e6d104SJian Shen struct hclge_basic_info *basic_info; 124d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 12532e6d104SJian Shen unsigned long caps; 126e2cb1decSSalil Mehta int status; 127e2cb1decSSalil Mehta 12832e6d104SJian Shen hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_BASIC_INFO, 0); 12932e6d104SJian Shen status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 130d3410018SYufeng Mo sizeof(resp_msg)); 131e2cb1decSSalil Mehta if (status) { 132e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 13332e6d104SJian Shen "failed to get basic info from pf, ret = %d", status); 134e2cb1decSSalil Mehta return status; 135e2cb1decSSalil Mehta } 136e2cb1decSSalil Mehta 13732e6d104SJian Shen basic_info = (struct hclge_basic_info *)resp_msg; 13832e6d104SJian Shen 13932e6d104SJian Shen hdev->hw_tc_map = basic_info->hw_tc_map; 140416eedb6SJie Wang hdev->mbx_api_version = le16_to_cpu(basic_info->mbx_api_version); 141416eedb6SJie Wang caps = le32_to_cpu(basic_info->pf_caps); 14232e6d104SJian Shen if (test_bit(HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B, &caps)) 14332e6d104SJian Shen set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps); 144e2cb1decSSalil Mehta 145e2cb1decSSalil Mehta return 0; 146e2cb1decSSalil Mehta } 147e2cb1decSSalil Mehta 14892f11ea1SJian Shen static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 14992f11ea1SJian Shen { 15092f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 151d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 15292f11ea1SJian Shen u8 resp_msg; 15392f11ea1SJian Shen int ret; 15492f11ea1SJian Shen 155d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 156d3410018SYufeng Mo HCLGE_MBX_GET_PORT_BASE_VLAN_STATE); 157d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg, 158d3410018SYufeng Mo sizeof(u8)); 15992f11ea1SJian Shen if (ret) { 16092f11ea1SJian Shen dev_err(&hdev->pdev->dev, 16192f11ea1SJian Shen "VF request to get port based vlan state failed %d", 16292f11ea1SJian Shen ret); 16392f11ea1SJian Shen return ret; 16492f11ea1SJian Shen } 16592f11ea1SJian Shen 16692f11ea1SJian Shen nic->port_base_vlan_state = resp_msg; 16792f11ea1SJian Shen 16892f11ea1SJian Shen return 0; 16992f11ea1SJian Shen } 17092f11ea1SJian Shen 1716cee6fc3SJian Shen static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 172e2cb1decSSalil Mehta { 173c0425944SPeng Li #define HCLGEVF_TQPS_RSS_INFO_LEN 6 174d3410018SYufeng Mo 175416eedb6SJie Wang struct hclge_mbx_vf_queue_info *queue_info; 176e2cb1decSSalil Mehta u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 177d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 178e2cb1decSSalil Mehta int status; 179e2cb1decSSalil Mehta 180d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QINFO, 0); 181d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 182e2cb1decSSalil Mehta HCLGEVF_TQPS_RSS_INFO_LEN); 183e2cb1decSSalil Mehta if (status) { 184e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 185e2cb1decSSalil Mehta "VF request to get tqp info from PF failed %d", 186e2cb1decSSalil Mehta status); 187e2cb1decSSalil Mehta return status; 188e2cb1decSSalil Mehta } 189e2cb1decSSalil Mehta 190416eedb6SJie Wang queue_info = (struct hclge_mbx_vf_queue_info *)resp_msg; 191416eedb6SJie Wang hdev->num_tqps = le16_to_cpu(queue_info->num_tqps); 192416eedb6SJie Wang hdev->rss_size_max = le16_to_cpu(queue_info->rss_size); 193416eedb6SJie Wang hdev->rx_buf_len = le16_to_cpu(queue_info->rx_buf_len); 194c0425944SPeng Li 195c0425944SPeng Li return 0; 196c0425944SPeng Li } 197c0425944SPeng Li 198c0425944SPeng Li static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 199c0425944SPeng Li { 200c0425944SPeng Li #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 201d3410018SYufeng Mo 202416eedb6SJie Wang struct hclge_mbx_vf_queue_depth *queue_depth; 203c0425944SPeng Li u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 204d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 205c0425944SPeng Li int ret; 206c0425944SPeng Li 207d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QDEPTH, 0); 208d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 209c0425944SPeng Li HCLGEVF_TQPS_DEPTH_INFO_LEN); 210c0425944SPeng Li if (ret) { 211c0425944SPeng Li dev_err(&hdev->pdev->dev, 212c0425944SPeng Li "VF request to get tqp depth info from PF failed %d", 213c0425944SPeng Li ret); 214c0425944SPeng Li return ret; 215c0425944SPeng Li } 216c0425944SPeng Li 217416eedb6SJie Wang queue_depth = (struct hclge_mbx_vf_queue_depth *)resp_msg; 218416eedb6SJie Wang hdev->num_tx_desc = le16_to_cpu(queue_depth->num_tx_desc); 219416eedb6SJie Wang hdev->num_rx_desc = le16_to_cpu(queue_depth->num_rx_desc); 220e2cb1decSSalil Mehta 221e2cb1decSSalil Mehta return 0; 222e2cb1decSSalil Mehta } 223e2cb1decSSalil Mehta 2240c29d191Sliuzhongzhu static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 2250c29d191Sliuzhongzhu { 2260c29d191Sliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 227d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 2280c29d191Sliuzhongzhu u16 qid_in_pf = 0; 229d3410018SYufeng Mo u8 resp_data[2]; 2300c29d191Sliuzhongzhu int ret; 2310c29d191Sliuzhongzhu 232d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QID_IN_PF, 0); 233416eedb6SJie Wang *(__le16 *)send_msg.data = cpu_to_le16(queue_id); 234d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_data, 23563cbf7a9SYufeng Mo sizeof(resp_data)); 2360c29d191Sliuzhongzhu if (!ret) 237416eedb6SJie Wang qid_in_pf = le16_to_cpu(*(__le16 *)resp_data); 2380c29d191Sliuzhongzhu 2390c29d191Sliuzhongzhu return qid_in_pf; 2400c29d191Sliuzhongzhu } 2410c29d191Sliuzhongzhu 2429c3e7130Sliuzhongzhu static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 2439c3e7130Sliuzhongzhu { 244d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 24588d10bd6SJian Shen u8 resp_msg[2]; 2469c3e7130Sliuzhongzhu int ret; 2479c3e7130Sliuzhongzhu 248d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MEDIA_TYPE, 0); 249d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 250d3410018SYufeng Mo sizeof(resp_msg)); 2519c3e7130Sliuzhongzhu if (ret) { 2529c3e7130Sliuzhongzhu dev_err(&hdev->pdev->dev, 2539c3e7130Sliuzhongzhu "VF request to get the pf port media type failed %d", 2549c3e7130Sliuzhongzhu ret); 2559c3e7130Sliuzhongzhu return ret; 2569c3e7130Sliuzhongzhu } 2579c3e7130Sliuzhongzhu 25888d10bd6SJian Shen hdev->hw.mac.media_type = resp_msg[0]; 25988d10bd6SJian Shen hdev->hw.mac.module_type = resp_msg[1]; 2609c3e7130Sliuzhongzhu 2619c3e7130Sliuzhongzhu return 0; 2629c3e7130Sliuzhongzhu } 2639c3e7130Sliuzhongzhu 264e2cb1decSSalil Mehta static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 265e2cb1decSSalil Mehta { 26687a9b2fdSYufeng Mo struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2674afc310cSJie Wang struct hclge_comm_tqp *tqp; 268e2cb1decSSalil Mehta int i; 269e2cb1decSSalil Mehta 270e2cb1decSSalil Mehta hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 2714afc310cSJie Wang sizeof(struct hclge_comm_tqp), GFP_KERNEL); 272e2cb1decSSalil Mehta if (!hdev->htqp) 273e2cb1decSSalil Mehta return -ENOMEM; 274e2cb1decSSalil Mehta 275e2cb1decSSalil Mehta tqp = hdev->htqp; 276e2cb1decSSalil Mehta 277e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 278e2cb1decSSalil Mehta tqp->dev = &hdev->pdev->dev; 279e2cb1decSSalil Mehta tqp->index = i; 280e2cb1decSSalil Mehta 281e2cb1decSSalil Mehta tqp->q.ae_algo = &ae_algovf; 282e2cb1decSSalil Mehta tqp->q.buf_size = hdev->rx_buf_len; 283c0425944SPeng Li tqp->q.tx_desc_num = hdev->num_tx_desc; 284c0425944SPeng Li tqp->q.rx_desc_num = hdev->num_rx_desc; 2859a5ef4aaSYonglong Liu 2869a5ef4aaSYonglong Liu /* need an extended offset to configure queues >= 2879a5ef4aaSYonglong Liu * HCLGEVF_TQP_MAX_SIZE_DEV_V2. 2889a5ef4aaSYonglong Liu */ 2899a5ef4aaSYonglong Liu if (i < HCLGEVF_TQP_MAX_SIZE_DEV_V2) 290076bb537SJie Wang tqp->q.io_base = hdev->hw.hw.io_base + 2919a5ef4aaSYonglong Liu HCLGEVF_TQP_REG_OFFSET + 292e2cb1decSSalil Mehta i * HCLGEVF_TQP_REG_SIZE; 2939a5ef4aaSYonglong Liu else 294076bb537SJie Wang tqp->q.io_base = hdev->hw.hw.io_base + 2959a5ef4aaSYonglong Liu HCLGEVF_TQP_REG_OFFSET + 2969a5ef4aaSYonglong Liu HCLGEVF_TQP_EXT_REG_OFFSET + 2979a5ef4aaSYonglong Liu (i - HCLGEVF_TQP_MAX_SIZE_DEV_V2) * 2989a5ef4aaSYonglong Liu HCLGEVF_TQP_REG_SIZE; 299e2cb1decSSalil Mehta 30087a9b2fdSYufeng Mo /* when device supports tx push and has device memory, 30187a9b2fdSYufeng Mo * the queue can execute push mode or doorbell mode on 30287a9b2fdSYufeng Mo * device memory. 30387a9b2fdSYufeng Mo */ 30487a9b2fdSYufeng Mo if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps)) 30587a9b2fdSYufeng Mo tqp->q.mem_base = hdev->hw.hw.mem_base + 30687a9b2fdSYufeng Mo HCLGEVF_TQP_MEM_OFFSET(hdev, i); 30787a9b2fdSYufeng Mo 308e2cb1decSSalil Mehta tqp++; 309e2cb1decSSalil Mehta } 310e2cb1decSSalil Mehta 311e2cb1decSSalil Mehta return 0; 312e2cb1decSSalil Mehta } 313e2cb1decSSalil Mehta 314e2cb1decSSalil Mehta static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 315e2cb1decSSalil Mehta { 316e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 317e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo; 318e2cb1decSSalil Mehta u16 new_tqps = hdev->num_tqps; 319ebaf1908SWeihang Li unsigned int i; 32035244430SJian Shen u8 num_tc = 0; 321e2cb1decSSalil Mehta 322e2cb1decSSalil Mehta kinfo = &nic->kinfo; 323c0425944SPeng Li kinfo->num_tx_desc = hdev->num_tx_desc; 324c0425944SPeng Li kinfo->num_rx_desc = hdev->num_rx_desc; 325e2cb1decSSalil Mehta kinfo->rx_buf_len = hdev->rx_buf_len; 32693969dc1SJie Wang for (i = 0; i < HCLGE_COMM_MAX_TC_NUM; i++) 327e2cb1decSSalil Mehta if (hdev->hw_tc_map & BIT(i)) 32835244430SJian Shen num_tc++; 329e2cb1decSSalil Mehta 33035244430SJian Shen num_tc = num_tc ? num_tc : 1; 33135244430SJian Shen kinfo->tc_info.num_tc = num_tc; 33235244430SJian Shen kinfo->rss_size = min_t(u16, hdev->rss_size_max, new_tqps / num_tc); 33335244430SJian Shen new_tqps = kinfo->rss_size * num_tc; 334e2cb1decSSalil Mehta kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 335e2cb1decSSalil Mehta 336e2cb1decSSalil Mehta kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 337e2cb1decSSalil Mehta sizeof(struct hnae3_queue *), GFP_KERNEL); 338e2cb1decSSalil Mehta if (!kinfo->tqp) 339e2cb1decSSalil Mehta return -ENOMEM; 340e2cb1decSSalil Mehta 341e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 342e2cb1decSSalil Mehta hdev->htqp[i].q.handle = &hdev->nic; 343e2cb1decSSalil Mehta hdev->htqp[i].q.tqp_index = i; 344e2cb1decSSalil Mehta kinfo->tqp[i] = &hdev->htqp[i].q; 345e2cb1decSSalil Mehta } 346e2cb1decSSalil Mehta 347580a05f9SYonglong Liu /* after init the max rss_size and tqps, adjust the default tqp numbers 348580a05f9SYonglong Liu * and rss size with the actual vector numbers 349580a05f9SYonglong Liu */ 350580a05f9SYonglong Liu kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps); 35135244430SJian Shen kinfo->rss_size = min_t(u16, kinfo->num_tqps / num_tc, 352580a05f9SYonglong Liu kinfo->rss_size); 353580a05f9SYonglong Liu 354e2cb1decSSalil Mehta return 0; 355e2cb1decSSalil Mehta } 356e2cb1decSSalil Mehta 357e2cb1decSSalil Mehta static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 358e2cb1decSSalil Mehta { 359d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 360e2cb1decSSalil Mehta int status; 361e2cb1decSSalil Mehta 362d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_STATUS, 0); 363d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 364e2cb1decSSalil Mehta if (status) 365e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 366e2cb1decSSalil Mehta "VF failed to fetch link status(%d) from PF", status); 367e2cb1decSSalil Mehta } 368e2cb1decSSalil Mehta 369e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 370e2cb1decSSalil Mehta { 37145e92b7eSPeng Li struct hnae3_handle *rhandle = &hdev->roce; 372e2cb1decSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 37345e92b7eSPeng Li struct hnae3_client *rclient; 374e2cb1decSSalil Mehta struct hnae3_client *client; 375e2cb1decSSalil Mehta 376ff200099SYunsheng Lin if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state)) 377ff200099SYunsheng Lin return; 378ff200099SYunsheng Lin 379e2cb1decSSalil Mehta client = handle->client; 38045e92b7eSPeng Li rclient = hdev->roce_client; 381e2cb1decSSalil Mehta 382582d37bbSPeng Li link_state = 383582d37bbSPeng Li test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 384e2cb1decSSalil Mehta if (link_state != hdev->hw.mac.link) { 385b15c072aSYonglong Liu hdev->hw.mac.link = link_state; 386e2cb1decSSalil Mehta client->ops->link_status_change(handle, !!link_state); 38745e92b7eSPeng Li if (rclient && rclient->ops->link_status_change) 38845e92b7eSPeng Li rclient->ops->link_status_change(rhandle, !!link_state); 389e2cb1decSSalil Mehta } 390ff200099SYunsheng Lin 391ff200099SYunsheng Lin clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state); 392e2cb1decSSalil Mehta } 393e2cb1decSSalil Mehta 394538abaf3SYueHaibing static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 3959194d18bSliuzhongzhu { 3969194d18bSliuzhongzhu #define HCLGEVF_ADVERTISING 0 3979194d18bSliuzhongzhu #define HCLGEVF_SUPPORTED 1 3989194d18bSliuzhongzhu 399d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 400d3410018SYufeng Mo 401d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_MODE, 0); 402d3410018SYufeng Mo send_msg.data[0] = HCLGEVF_ADVERTISING; 403d3410018SYufeng Mo hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 404d3410018SYufeng Mo send_msg.data[0] = HCLGEVF_SUPPORTED; 405d3410018SYufeng Mo hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 4069194d18bSliuzhongzhu } 4079194d18bSliuzhongzhu 408e2cb1decSSalil Mehta static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 409e2cb1decSSalil Mehta { 410e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 411e2cb1decSSalil Mehta int ret; 412e2cb1decSSalil Mehta 413e2cb1decSSalil Mehta nic->ae_algo = &ae_algovf; 414e2cb1decSSalil Mehta nic->pdev = hdev->pdev; 415e2cb1decSSalil Mehta nic->numa_node_mask = hdev->numa_node_mask; 416424eb834SSalil Mehta nic->flags |= HNAE3_SUPPORT_VF; 417076bb537SJie Wang nic->kinfo.io_base = hdev->hw.hw.io_base; 418e2cb1decSSalil Mehta 419e2cb1decSSalil Mehta ret = hclgevf_knic_setup(hdev); 420e2cb1decSSalil Mehta if (ret) 421e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 422e2cb1decSSalil Mehta ret); 423e2cb1decSSalil Mehta return ret; 424e2cb1decSSalil Mehta } 425e2cb1decSSalil Mehta 426e2cb1decSSalil Mehta static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 427e2cb1decSSalil Mehta { 42836cbbdf6SPeng Li if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 42936cbbdf6SPeng Li dev_warn(&hdev->pdev->dev, 43036cbbdf6SPeng Li "vector(vector_id %d) has been freed.\n", vector_id); 43136cbbdf6SPeng Li return; 43236cbbdf6SPeng Li } 43336cbbdf6SPeng Li 434e2cb1decSSalil Mehta hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 435e2cb1decSSalil Mehta hdev->num_msi_left += 1; 436e2cb1decSSalil Mehta hdev->num_msi_used -= 1; 437e2cb1decSSalil Mehta } 438e2cb1decSSalil Mehta 439e2cb1decSSalil Mehta static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 440e2cb1decSSalil Mehta struct hnae3_vector_info *vector_info) 441e2cb1decSSalil Mehta { 442e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 443e2cb1decSSalil Mehta struct hnae3_vector_info *vector = vector_info; 444e2cb1decSSalil Mehta int alloc = 0; 445e2cb1decSSalil Mehta int i, j; 446e2cb1decSSalil Mehta 447580a05f9SYonglong Liu vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num); 448e2cb1decSSalil Mehta vector_num = min(hdev->num_msi_left, vector_num); 449e2cb1decSSalil Mehta 450e2cb1decSSalil Mehta for (j = 0; j < vector_num; j++) { 451e2cb1decSSalil Mehta for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 452e2cb1decSSalil Mehta if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 453e2cb1decSSalil Mehta vector->vector = pci_irq_vector(hdev->pdev, i); 454076bb537SJie Wang vector->io_addr = hdev->hw.hw.io_base + 455e2cb1decSSalil Mehta HCLGEVF_VECTOR_REG_BASE + 456e2cb1decSSalil Mehta (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 457e2cb1decSSalil Mehta hdev->vector_status[i] = 0; 458e2cb1decSSalil Mehta hdev->vector_irq[i] = vector->vector; 459e2cb1decSSalil Mehta 460e2cb1decSSalil Mehta vector++; 461e2cb1decSSalil Mehta alloc++; 462e2cb1decSSalil Mehta 463e2cb1decSSalil Mehta break; 464e2cb1decSSalil Mehta } 465e2cb1decSSalil Mehta } 466e2cb1decSSalil Mehta } 467e2cb1decSSalil Mehta hdev->num_msi_left -= alloc; 468e2cb1decSSalil Mehta hdev->num_msi_used += alloc; 469e2cb1decSSalil Mehta 470e2cb1decSSalil Mehta return alloc; 471e2cb1decSSalil Mehta } 472e2cb1decSSalil Mehta 473e2cb1decSSalil Mehta static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 474e2cb1decSSalil Mehta { 475e2cb1decSSalil Mehta int i; 476e2cb1decSSalil Mehta 477e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 478e2cb1decSSalil Mehta if (vector == hdev->vector_irq[i]) 479e2cb1decSSalil Mehta return i; 480e2cb1decSSalil Mehta 481e2cb1decSSalil Mehta return -EINVAL; 482e2cb1decSSalil Mehta } 483e2cb1decSSalil Mehta 484a638b1d8SJian Shen /* for revision 0x20, vf shared the same rss config with pf */ 485a638b1d8SJian Shen static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 486a638b1d8SJian Shen { 487a638b1d8SJian Shen #define HCLGEVF_RSS_MBX_RESP_LEN 8 488027733b1SJie Wang struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 489a638b1d8SJian Shen u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 490d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 491a638b1d8SJian Shen u16 msg_num, hash_key_index; 492a638b1d8SJian Shen u8 index; 493a638b1d8SJian Shen int ret; 494a638b1d8SJian Shen 495d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_RSS_KEY, 0); 4967428d6c9SJie Wang msg_num = (HCLGE_COMM_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 497a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN; 498a638b1d8SJian Shen for (index = 0; index < msg_num; index++) { 499d3410018SYufeng Mo send_msg.data[0] = index; 500d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 501a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN); 502a638b1d8SJian Shen if (ret) { 503a638b1d8SJian Shen dev_err(&hdev->pdev->dev, 504a638b1d8SJian Shen "VF get rss hash key from PF failed, ret=%d", 505a638b1d8SJian Shen ret); 506a638b1d8SJian Shen return ret; 507a638b1d8SJian Shen } 508a638b1d8SJian Shen 509a638b1d8SJian Shen hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 510a638b1d8SJian Shen if (index == msg_num - 1) 511a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 512a638b1d8SJian Shen &resp_msg[0], 5137428d6c9SJie Wang HCLGE_COMM_RSS_KEY_SIZE - hash_key_index); 514a638b1d8SJian Shen else 515a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 516a638b1d8SJian Shen &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 517a638b1d8SJian Shen } 518a638b1d8SJian Shen 519a638b1d8SJian Shen return 0; 520a638b1d8SJian Shen } 521a638b1d8SJian Shen 522e2cb1decSSalil Mehta static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 523e2cb1decSSalil Mehta u8 *hfunc) 524e2cb1decSSalil Mehta { 525e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 526027733b1SJie Wang struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 5277428d6c9SJie Wang int ret; 528e2cb1decSSalil Mehta 529295ba232SGuangbin Huang if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 5307428d6c9SJie Wang hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc); 531a638b1d8SJian Shen } else { 532a638b1d8SJian Shen if (hfunc) 533a638b1d8SJian Shen *hfunc = ETH_RSS_HASH_TOP; 534a638b1d8SJian Shen if (key) { 535a638b1d8SJian Shen ret = hclgevf_get_rss_hash_key(hdev); 536a638b1d8SJian Shen if (ret) 537a638b1d8SJian Shen return ret; 538a638b1d8SJian Shen memcpy(key, rss_cfg->rss_hash_key, 5397428d6c9SJie Wang HCLGE_COMM_RSS_KEY_SIZE); 540a638b1d8SJian Shen } 541374ad291SJian Shen } 542374ad291SJian Shen 5437428d6c9SJie Wang hclge_comm_get_rss_indir_tbl(rss_cfg, indir, 5447428d6c9SJie Wang hdev->ae_dev->dev_specs.rss_ind_tbl_size); 545e2cb1decSSalil Mehta 546374ad291SJian Shen return 0; 547e2cb1decSSalil Mehta } 548e2cb1decSSalil Mehta 549e2cb1decSSalil Mehta static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 550e2cb1decSSalil Mehta const u8 *key, const u8 hfunc) 551e2cb1decSSalil Mehta { 552e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 553027733b1SJie Wang struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 554374ad291SJian Shen int ret, i; 555374ad291SJian Shen 556295ba232SGuangbin Huang if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 55793969dc1SJie Wang ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, 55893969dc1SJie Wang hfunc); 559374ad291SJian Shen if (ret) 560374ad291SJian Shen return ret; 561374ad291SJian Shen } 562e2cb1decSSalil Mehta 563e2cb1decSSalil Mehta /* update the shadow RSS table with user specified qids */ 56487ce161eSGuangbin Huang for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 565e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = indir[i]; 566e2cb1decSSalil Mehta 567e2cb1decSSalil Mehta /* update the hardware */ 5687428d6c9SJie Wang return hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 5697428d6c9SJie Wang rss_cfg->rss_indirection_tbl); 5705fd0e7b4SHuazhong Tan } 5715fd0e7b4SHuazhong Tan 5725fd0e7b4SHuazhong Tan static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 5735fd0e7b4SHuazhong Tan struct ethtool_rxnfc *nfc) 5745fd0e7b4SHuazhong Tan { 5755fd0e7b4SHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 5765fd0e7b4SHuazhong Tan int ret; 5775fd0e7b4SHuazhong Tan 5785fd0e7b4SHuazhong Tan if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 5795fd0e7b4SHuazhong Tan return -EOPNOTSUPP; 5805fd0e7b4SHuazhong Tan 58193969dc1SJie Wang ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw, 58293969dc1SJie Wang &hdev->rss_cfg, nfc); 58393969dc1SJie Wang if (ret) 5845fd0e7b4SHuazhong Tan dev_err(&hdev->pdev->dev, 58593969dc1SJie Wang "failed to set rss tuple, ret = %d.\n", ret); 5865fd0e7b4SHuazhong Tan 587d97b3072SJian Shen return ret; 588d97b3072SJian Shen } 589d97b3072SJian Shen 590d97b3072SJian Shen static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 591d97b3072SJian Shen struct ethtool_rxnfc *nfc) 592d97b3072SJian Shen { 593d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 594d97b3072SJian Shen u8 tuple_sets; 59573f7767eSJian Shen int ret; 596d97b3072SJian Shen 597295ba232SGuangbin Huang if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 598d97b3072SJian Shen return -EOPNOTSUPP; 599d97b3072SJian Shen 600d97b3072SJian Shen nfc->data = 0; 601d97b3072SJian Shen 602027733b1SJie Wang ret = hclge_comm_get_rss_tuple(&hdev->rss_cfg, nfc->flow_type, 60373f7767eSJian Shen &tuple_sets); 60473f7767eSJian Shen if (ret || !tuple_sets) 60573f7767eSJian Shen return ret; 606d97b3072SJian Shen 6077428d6c9SJie Wang nfc->data = hclge_comm_convert_rss_tuple(tuple_sets); 608d97b3072SJian Shen 609d97b3072SJian Shen return 0; 610d97b3072SJian Shen } 611d97b3072SJian Shen 612e2cb1decSSalil Mehta static int hclgevf_get_tc_size(struct hnae3_handle *handle) 613e2cb1decSSalil Mehta { 614e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 615027733b1SJie Wang struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 616e2cb1decSSalil Mehta 617e2cb1decSSalil Mehta return rss_cfg->rss_size; 618e2cb1decSSalil Mehta } 619e2cb1decSSalil Mehta 620e2cb1decSSalil Mehta static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 621b204bc74SPeng Li int vector_id, 622e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 623e2cb1decSSalil Mehta { 624e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 625d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 626e2cb1decSSalil Mehta struct hnae3_ring_chain_node *node; 627e2cb1decSSalil Mehta int status; 628d3410018SYufeng Mo int i = 0; 629e2cb1decSSalil Mehta 630d3410018SYufeng Mo memset(&send_msg, 0, sizeof(send_msg)); 631d3410018SYufeng Mo send_msg.code = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 632c09ba484SPeng Li HCLGE_MBX_UNMAP_RING_TO_VECTOR; 633d3410018SYufeng Mo send_msg.vector_id = vector_id; 634e2cb1decSSalil Mehta 635e2cb1decSSalil Mehta for (node = ring_chain; node; node = node->next) { 636d3410018SYufeng Mo send_msg.param[i].ring_type = 637e4e87715SPeng Li hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 638d3410018SYufeng Mo 639d3410018SYufeng Mo send_msg.param[i].tqp_index = node->tqp_index; 640d3410018SYufeng Mo send_msg.param[i].int_gl_index = 641d3410018SYufeng Mo hnae3_get_field(node->int_gl_idx, 64279eee410SFuyun Liang HNAE3_RING_GL_IDX_M, 64379eee410SFuyun Liang HNAE3_RING_GL_IDX_S); 64479eee410SFuyun Liang 6455d02a58dSYunsheng Lin i++; 646d3410018SYufeng Mo if (i == HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM || !node->next) { 647d3410018SYufeng Mo send_msg.ring_num = i; 648e2cb1decSSalil Mehta 649d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, false, 650d3410018SYufeng Mo NULL, 0); 651e2cb1decSSalil Mehta if (status) { 652e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 653e2cb1decSSalil Mehta "Map TQP fail, status is %d.\n", 654e2cb1decSSalil Mehta status); 655e2cb1decSSalil Mehta return status; 656e2cb1decSSalil Mehta } 657e2cb1decSSalil Mehta i = 0; 658e2cb1decSSalil Mehta } 659e2cb1decSSalil Mehta } 660e2cb1decSSalil Mehta 661e2cb1decSSalil Mehta return 0; 662e2cb1decSSalil Mehta } 663e2cb1decSSalil Mehta 664e2cb1decSSalil Mehta static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 665e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 666e2cb1decSSalil Mehta { 667b204bc74SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 668b204bc74SPeng Li int vector_id; 669b204bc74SPeng Li 670b204bc74SPeng Li vector_id = hclgevf_get_vector_index(hdev, vector); 671b204bc74SPeng Li if (vector_id < 0) { 672b204bc74SPeng Li dev_err(&handle->pdev->dev, 673b204bc74SPeng Li "Get vector index fail. ret =%d\n", vector_id); 674b204bc74SPeng Li return vector_id; 675b204bc74SPeng Li } 676b204bc74SPeng Li 677b204bc74SPeng Li return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 678e2cb1decSSalil Mehta } 679e2cb1decSSalil Mehta 680e2cb1decSSalil Mehta static int hclgevf_unmap_ring_from_vector( 681e2cb1decSSalil Mehta struct hnae3_handle *handle, 682e2cb1decSSalil Mehta int vector, 683e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 684e2cb1decSSalil Mehta { 685e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 686e2cb1decSSalil Mehta int ret, vector_id; 687e2cb1decSSalil Mehta 688dea846e8SHuazhong Tan if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 689dea846e8SHuazhong Tan return 0; 690dea846e8SHuazhong Tan 691e2cb1decSSalil Mehta vector_id = hclgevf_get_vector_index(hdev, vector); 692e2cb1decSSalil Mehta if (vector_id < 0) { 693e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 694e2cb1decSSalil Mehta "Get vector index fail. ret =%d\n", vector_id); 695e2cb1decSSalil Mehta return vector_id; 696e2cb1decSSalil Mehta } 697e2cb1decSSalil Mehta 698b204bc74SPeng Li ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 6990d3e6631SYunsheng Lin if (ret) 700e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 701e2cb1decSSalil Mehta "Unmap ring from vector fail. vector=%d, ret =%d\n", 702e2cb1decSSalil Mehta vector_id, 703e2cb1decSSalil Mehta ret); 7040d3e6631SYunsheng Lin 705e2cb1decSSalil Mehta return ret; 706e2cb1decSSalil Mehta } 707e2cb1decSSalil Mehta 7080d3e6631SYunsheng Lin static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 7090d3e6631SYunsheng Lin { 7100d3e6631SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 71103718db9SYunsheng Lin int vector_id; 7120d3e6631SYunsheng Lin 71303718db9SYunsheng Lin vector_id = hclgevf_get_vector_index(hdev, vector); 71403718db9SYunsheng Lin if (vector_id < 0) { 71503718db9SYunsheng Lin dev_err(&handle->pdev->dev, 71603718db9SYunsheng Lin "hclgevf_put_vector get vector index fail. ret =%d\n", 71703718db9SYunsheng Lin vector_id); 71803718db9SYunsheng Lin return vector_id; 71903718db9SYunsheng Lin } 72003718db9SYunsheng Lin 72103718db9SYunsheng Lin hclgevf_free_vector(hdev, vector_id); 722e2cb1decSSalil Mehta 723e2cb1decSSalil Mehta return 0; 724e2cb1decSSalil Mehta } 725e2cb1decSSalil Mehta 7263b75c3dfSPeng Li static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 727e196ec75SJian Shen bool en_uc_pmc, bool en_mc_pmc, 728f01f5559SJian Shen bool en_bc_pmc) 729e2cb1decSSalil Mehta { 7305e7414cdSJian Shen struct hnae3_handle *handle = &hdev->nic; 731d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 732f01f5559SJian Shen int ret; 733e2cb1decSSalil Mehta 734d3410018SYufeng Mo memset(&send_msg, 0, sizeof(send_msg)); 735d3410018SYufeng Mo send_msg.code = HCLGE_MBX_SET_PROMISC_MODE; 736d3410018SYufeng Mo send_msg.en_bc = en_bc_pmc ? 1 : 0; 737d3410018SYufeng Mo send_msg.en_uc = en_uc_pmc ? 1 : 0; 738d3410018SYufeng Mo send_msg.en_mc = en_mc_pmc ? 1 : 0; 7395e7414cdSJian Shen send_msg.en_limit_promisc = test_bit(HNAE3_PFLAG_LIMIT_PROMISC, 7405e7414cdSJian Shen &handle->priv_flags) ? 1 : 0; 741e2cb1decSSalil Mehta 742d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 743f01f5559SJian Shen if (ret) 744e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 745f01f5559SJian Shen "Set promisc mode fail, status is %d.\n", ret); 746e2cb1decSSalil Mehta 747f01f5559SJian Shen return ret; 748e2cb1decSSalil Mehta } 749e2cb1decSSalil Mehta 750e196ec75SJian Shen static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 751e196ec75SJian Shen bool en_mc_pmc) 752e2cb1decSSalil Mehta { 753e196ec75SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 754e196ec75SJian Shen bool en_bc_pmc; 755e196ec75SJian Shen 756295ba232SGuangbin Huang en_bc_pmc = hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2; 757e196ec75SJian Shen 758e196ec75SJian Shen return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc, 759e196ec75SJian Shen en_bc_pmc); 760e2cb1decSSalil Mehta } 761e2cb1decSSalil Mehta 762c631c696SJian Shen static void hclgevf_request_update_promisc_mode(struct hnae3_handle *handle) 763c631c696SJian Shen { 764c631c696SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 765c631c696SJian Shen 766c631c696SJian Shen set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 7675e7414cdSJian Shen hclgevf_task_schedule(hdev, 0); 768c631c696SJian Shen } 769c631c696SJian Shen 770c631c696SJian Shen static void hclgevf_sync_promisc_mode(struct hclgevf_dev *hdev) 771c631c696SJian Shen { 772c631c696SJian Shen struct hnae3_handle *handle = &hdev->nic; 773c631c696SJian Shen bool en_uc_pmc = handle->netdev_flags & HNAE3_UPE; 774c631c696SJian Shen bool en_mc_pmc = handle->netdev_flags & HNAE3_MPE; 775c631c696SJian Shen int ret; 776c631c696SJian Shen 777c631c696SJian Shen if (test_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state)) { 778c631c696SJian Shen ret = hclgevf_set_promisc_mode(handle, en_uc_pmc, en_mc_pmc); 779c631c696SJian Shen if (!ret) 780c631c696SJian Shen clear_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 781c631c696SJian Shen } 782c631c696SJian Shen } 783c631c696SJian Shen 7848fa86551SYufeng Mo static int hclgevf_tqp_enable_cmd_send(struct hclgevf_dev *hdev, u16 tqp_id, 7858fa86551SYufeng Mo u16 stream_id, bool enable) 786e2cb1decSSalil Mehta { 787e2cb1decSSalil Mehta struct hclgevf_cfg_com_tqp_queue_cmd *req; 7886befad60SJie Wang struct hclge_desc desc; 789e2cb1decSSalil Mehta 790e2cb1decSSalil Mehta req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 791e2cb1decSSalil Mehta 79243710bfeSJie Wang hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); 793e2cb1decSSalil Mehta req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 794e2cb1decSSalil Mehta req->stream_id = cpu_to_le16(stream_id); 795ebaf1908SWeihang Li if (enable) 796ebaf1908SWeihang Li req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 797e2cb1decSSalil Mehta 7988fa86551SYufeng Mo return hclgevf_cmd_send(&hdev->hw, &desc, 1); 7998fa86551SYufeng Mo } 800e2cb1decSSalil Mehta 8018fa86551SYufeng Mo static int hclgevf_tqp_enable(struct hnae3_handle *handle, bool enable) 8028fa86551SYufeng Mo { 8038fa86551SYufeng Mo struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 8048fa86551SYufeng Mo int ret; 8058fa86551SYufeng Mo u16 i; 8068fa86551SYufeng Mo 8078fa86551SYufeng Mo for (i = 0; i < handle->kinfo.num_tqps; i++) { 8088fa86551SYufeng Mo ret = hclgevf_tqp_enable_cmd_send(hdev, i, 0, enable); 8098fa86551SYufeng Mo if (ret) 8108fa86551SYufeng Mo return ret; 8118fa86551SYufeng Mo } 8128fa86551SYufeng Mo 8138fa86551SYufeng Mo return 0; 814e2cb1decSSalil Mehta } 815e2cb1decSSalil Mehta 8168e6de441SHuazhong Tan static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p) 8178e6de441SHuazhong Tan { 818d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 8198e6de441SHuazhong Tan u8 host_mac[ETH_ALEN]; 8208e6de441SHuazhong Tan int status; 8218e6de441SHuazhong Tan 822d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MAC_ADDR, 0); 823d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, true, host_mac, 824d3410018SYufeng Mo ETH_ALEN); 8258e6de441SHuazhong Tan if (status) { 8268e6de441SHuazhong Tan dev_err(&hdev->pdev->dev, 8278e6de441SHuazhong Tan "fail to get VF MAC from host %d", status); 8288e6de441SHuazhong Tan return status; 8298e6de441SHuazhong Tan } 8308e6de441SHuazhong Tan 8318e6de441SHuazhong Tan ether_addr_copy(p, host_mac); 8328e6de441SHuazhong Tan 8338e6de441SHuazhong Tan return 0; 8348e6de441SHuazhong Tan } 8358e6de441SHuazhong Tan 836e2cb1decSSalil Mehta static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 837e2cb1decSSalil Mehta { 838e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 8398e6de441SHuazhong Tan u8 host_mac_addr[ETH_ALEN]; 840e2cb1decSSalil Mehta 8418e6de441SHuazhong Tan if (hclgevf_get_host_mac_addr(hdev, host_mac_addr)) 8428e6de441SHuazhong Tan return; 8438e6de441SHuazhong Tan 8448e6de441SHuazhong Tan hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr); 8458e6de441SHuazhong Tan if (hdev->has_pf_mac) 8468e6de441SHuazhong Tan ether_addr_copy(p, host_mac_addr); 8478e6de441SHuazhong Tan else 848e2cb1decSSalil Mehta ether_addr_copy(p, hdev->hw.mac.mac_addr); 849e2cb1decSSalil Mehta } 850e2cb1decSSalil Mehta 85176660757SJakub Kicinski static int hclgevf_set_mac_addr(struct hnae3_handle *handle, const void *p, 85259098055SFuyun Liang bool is_first) 853e2cb1decSSalil Mehta { 854e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 855e2cb1decSSalil Mehta u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 856d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 857e2cb1decSSalil Mehta u8 *new_mac_addr = (u8 *)p; 858e2cb1decSSalil Mehta int status; 859e2cb1decSSalil Mehta 860d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 0); 861ee4bcd3bSJian Shen send_msg.subcode = HCLGE_MBX_MAC_VLAN_UC_MODIFY; 862d3410018SYufeng Mo ether_addr_copy(send_msg.data, new_mac_addr); 863ee4bcd3bSJian Shen if (is_first && !hdev->has_pf_mac) 864ee4bcd3bSJian Shen eth_zero_addr(&send_msg.data[ETH_ALEN]); 865ee4bcd3bSJian Shen else 866d3410018SYufeng Mo ether_addr_copy(&send_msg.data[ETH_ALEN], old_mac_addr); 867d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 868e2cb1decSSalil Mehta if (!status) 869e2cb1decSSalil Mehta ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 870e2cb1decSSalil Mehta 871e2cb1decSSalil Mehta return status; 872e2cb1decSSalil Mehta } 873e2cb1decSSalil Mehta 874ee4bcd3bSJian Shen static struct hclgevf_mac_addr_node * 875ee4bcd3bSJian Shen hclgevf_find_mac_node(struct list_head *list, const u8 *mac_addr) 876ee4bcd3bSJian Shen { 877ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp; 878ee4bcd3bSJian Shen 879ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, list, node) 880ee4bcd3bSJian Shen if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 881ee4bcd3bSJian Shen return mac_node; 882ee4bcd3bSJian Shen 883ee4bcd3bSJian Shen return NULL; 884ee4bcd3bSJian Shen } 885ee4bcd3bSJian Shen 886ee4bcd3bSJian Shen static void hclgevf_update_mac_node(struct hclgevf_mac_addr_node *mac_node, 887ee4bcd3bSJian Shen enum HCLGEVF_MAC_NODE_STATE state) 888ee4bcd3bSJian Shen { 889ee4bcd3bSJian Shen switch (state) { 890ee4bcd3bSJian Shen /* from set_rx_mode or tmp_add_list */ 891ee4bcd3bSJian Shen case HCLGEVF_MAC_TO_ADD: 892ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_DEL) 893ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_ACTIVE; 894ee4bcd3bSJian Shen break; 895ee4bcd3bSJian Shen /* only from set_rx_mode */ 896ee4bcd3bSJian Shen case HCLGEVF_MAC_TO_DEL: 897ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 898ee4bcd3bSJian Shen list_del(&mac_node->node); 899ee4bcd3bSJian Shen kfree(mac_node); 900ee4bcd3bSJian Shen } else { 901ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_TO_DEL; 902ee4bcd3bSJian Shen } 903ee4bcd3bSJian Shen break; 904ee4bcd3bSJian Shen /* only from tmp_add_list, the mac_node->state won't be 905ee4bcd3bSJian Shen * HCLGEVF_MAC_ACTIVE 906ee4bcd3bSJian Shen */ 907ee4bcd3bSJian Shen case HCLGEVF_MAC_ACTIVE: 908ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) 909ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_ACTIVE; 910ee4bcd3bSJian Shen break; 911ee4bcd3bSJian Shen } 912ee4bcd3bSJian Shen } 913ee4bcd3bSJian Shen 914ee4bcd3bSJian Shen static int hclgevf_update_mac_list(struct hnae3_handle *handle, 915ee4bcd3bSJian Shen enum HCLGEVF_MAC_NODE_STATE state, 916ee4bcd3bSJian Shen enum HCLGEVF_MAC_ADDR_TYPE mac_type, 917e2cb1decSSalil Mehta const unsigned char *addr) 918e2cb1decSSalil Mehta { 919e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 920ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node; 921ee4bcd3bSJian Shen struct list_head *list; 922e2cb1decSSalil Mehta 923ee4bcd3bSJian Shen list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 924ee4bcd3bSJian Shen &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 925ee4bcd3bSJian Shen 926ee4bcd3bSJian Shen spin_lock_bh(&hdev->mac_table.mac_list_lock); 927ee4bcd3bSJian Shen 928ee4bcd3bSJian Shen /* if the mac addr is already in the mac list, no need to add a new 929ee4bcd3bSJian Shen * one into it, just check the mac addr state, convert it to a new 93034eff17eSJilin Yuan * state, or just remove it, or do nothing. 931ee4bcd3bSJian Shen */ 932ee4bcd3bSJian Shen mac_node = hclgevf_find_mac_node(list, addr); 933ee4bcd3bSJian Shen if (mac_node) { 934ee4bcd3bSJian Shen hclgevf_update_mac_node(mac_node, state); 935ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 936ee4bcd3bSJian Shen return 0; 937ee4bcd3bSJian Shen } 938ee4bcd3bSJian Shen /* if this address is never added, unnecessary to delete */ 939ee4bcd3bSJian Shen if (state == HCLGEVF_MAC_TO_DEL) { 940ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 941ee4bcd3bSJian Shen return -ENOENT; 942ee4bcd3bSJian Shen } 943ee4bcd3bSJian Shen 944ee4bcd3bSJian Shen mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 945ee4bcd3bSJian Shen if (!mac_node) { 946ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 947ee4bcd3bSJian Shen return -ENOMEM; 948ee4bcd3bSJian Shen } 949ee4bcd3bSJian Shen 950ee4bcd3bSJian Shen mac_node->state = state; 951ee4bcd3bSJian Shen ether_addr_copy(mac_node->mac_addr, addr); 952ee4bcd3bSJian Shen list_add_tail(&mac_node->node, list); 953ee4bcd3bSJian Shen 954ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 955ee4bcd3bSJian Shen return 0; 956ee4bcd3bSJian Shen } 957ee4bcd3bSJian Shen 958ee4bcd3bSJian Shen static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 959ee4bcd3bSJian Shen const unsigned char *addr) 960ee4bcd3bSJian Shen { 961ee4bcd3bSJian Shen return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 962ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_UC, addr); 963e2cb1decSSalil Mehta } 964e2cb1decSSalil Mehta 965e2cb1decSSalil Mehta static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 966e2cb1decSSalil Mehta const unsigned char *addr) 967e2cb1decSSalil Mehta { 968ee4bcd3bSJian Shen return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 969ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_UC, addr); 970e2cb1decSSalil Mehta } 971e2cb1decSSalil Mehta 972e2cb1decSSalil Mehta static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 973e2cb1decSSalil Mehta const unsigned char *addr) 974e2cb1decSSalil Mehta { 975ee4bcd3bSJian Shen return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 976ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_MC, addr); 977e2cb1decSSalil Mehta } 978e2cb1decSSalil Mehta 979e2cb1decSSalil Mehta static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 980e2cb1decSSalil Mehta const unsigned char *addr) 981e2cb1decSSalil Mehta { 982ee4bcd3bSJian Shen return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 983ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_MC, addr); 984ee4bcd3bSJian Shen } 985e2cb1decSSalil Mehta 986ee4bcd3bSJian Shen static int hclgevf_add_del_mac_addr(struct hclgevf_dev *hdev, 987ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, 988ee4bcd3bSJian Shen enum HCLGEVF_MAC_ADDR_TYPE mac_type) 989ee4bcd3bSJian Shen { 990ee4bcd3bSJian Shen struct hclge_vf_to_pf_msg send_msg; 991ee4bcd3bSJian Shen u8 code, subcode; 992ee4bcd3bSJian Shen 993ee4bcd3bSJian Shen if (mac_type == HCLGEVF_MAC_ADDR_UC) { 994ee4bcd3bSJian Shen code = HCLGE_MBX_SET_UNICAST; 995ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) 996ee4bcd3bSJian Shen subcode = HCLGE_MBX_MAC_VLAN_UC_ADD; 997ee4bcd3bSJian Shen else 998ee4bcd3bSJian Shen subcode = HCLGE_MBX_MAC_VLAN_UC_REMOVE; 999ee4bcd3bSJian Shen } else { 1000ee4bcd3bSJian Shen code = HCLGE_MBX_SET_MULTICAST; 1001ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1002ee4bcd3bSJian Shen subcode = HCLGE_MBX_MAC_VLAN_MC_ADD; 1003ee4bcd3bSJian Shen else 1004ee4bcd3bSJian Shen subcode = HCLGE_MBX_MAC_VLAN_MC_REMOVE; 1005ee4bcd3bSJian Shen } 1006ee4bcd3bSJian Shen 1007ee4bcd3bSJian Shen hclgevf_build_send_msg(&send_msg, code, subcode); 1008ee4bcd3bSJian Shen ether_addr_copy(send_msg.data, mac_node->mac_addr); 1009d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1010e2cb1decSSalil Mehta } 1011e2cb1decSSalil Mehta 1012ee4bcd3bSJian Shen static void hclgevf_config_mac_list(struct hclgevf_dev *hdev, 1013ee4bcd3bSJian Shen struct list_head *list, 1014ee4bcd3bSJian Shen enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1015ee4bcd3bSJian Shen { 10164f331fdaSYufeng Mo char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 1017ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp; 1018ee4bcd3bSJian Shen int ret; 1019ee4bcd3bSJian Shen 1020ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, list, node) { 1021ee4bcd3bSJian Shen ret = hclgevf_add_del_mac_addr(hdev, mac_node, mac_type); 1022ee4bcd3bSJian Shen if (ret) { 10234f331fdaSYufeng Mo hnae3_format_mac_addr(format_mac_addr, 10244f331fdaSYufeng Mo mac_node->mac_addr); 1025ee4bcd3bSJian Shen dev_err(&hdev->pdev->dev, 10264f331fdaSYufeng Mo "failed to configure mac %s, state = %d, ret = %d\n", 10274f331fdaSYufeng Mo format_mac_addr, mac_node->state, ret); 1028ee4bcd3bSJian Shen return; 1029ee4bcd3bSJian Shen } 1030ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1031ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_ACTIVE; 1032ee4bcd3bSJian Shen } else { 1033ee4bcd3bSJian Shen list_del(&mac_node->node); 1034ee4bcd3bSJian Shen kfree(mac_node); 1035ee4bcd3bSJian Shen } 1036ee4bcd3bSJian Shen } 1037ee4bcd3bSJian Shen } 1038ee4bcd3bSJian Shen 1039ee4bcd3bSJian Shen static void hclgevf_sync_from_add_list(struct list_head *add_list, 1040ee4bcd3bSJian Shen struct list_head *mac_list) 1041ee4bcd3bSJian Shen { 1042ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1043ee4bcd3bSJian Shen 1044ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, add_list, node) { 1045ee4bcd3bSJian Shen /* if the mac address from tmp_add_list is not in the 1046ee4bcd3bSJian Shen * uc/mc_mac_list, it means have received a TO_DEL request 1047ee4bcd3bSJian Shen * during the time window of sending mac config request to PF 1048ee4bcd3bSJian Shen * If mac_node state is ACTIVE, then change its state to TO_DEL, 1049ee4bcd3bSJian Shen * then it will be removed at next time. If is TO_ADD, it means 1050ee4bcd3bSJian Shen * send TO_ADD request failed, so just remove the mac node. 1051ee4bcd3bSJian Shen */ 1052ee4bcd3bSJian Shen new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1053ee4bcd3bSJian Shen if (new_node) { 1054ee4bcd3bSJian Shen hclgevf_update_mac_node(new_node, mac_node->state); 1055ee4bcd3bSJian Shen list_del(&mac_node->node); 1056ee4bcd3bSJian Shen kfree(mac_node); 1057ee4bcd3bSJian Shen } else if (mac_node->state == HCLGEVF_MAC_ACTIVE) { 1058ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_TO_DEL; 105949768ce9SBaokun Li list_move_tail(&mac_node->node, mac_list); 1060ee4bcd3bSJian Shen } else { 1061ee4bcd3bSJian Shen list_del(&mac_node->node); 1062ee4bcd3bSJian Shen kfree(mac_node); 1063ee4bcd3bSJian Shen } 1064ee4bcd3bSJian Shen } 1065ee4bcd3bSJian Shen } 1066ee4bcd3bSJian Shen 1067ee4bcd3bSJian Shen static void hclgevf_sync_from_del_list(struct list_head *del_list, 1068ee4bcd3bSJian Shen struct list_head *mac_list) 1069ee4bcd3bSJian Shen { 1070ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1071ee4bcd3bSJian Shen 1072ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, del_list, node) { 1073ee4bcd3bSJian Shen new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1074ee4bcd3bSJian Shen if (new_node) { 1075ee4bcd3bSJian Shen /* If the mac addr is exist in the mac list, it means 1076ee4bcd3bSJian Shen * received a new request TO_ADD during the time window 1077ee4bcd3bSJian Shen * of sending mac addr configurrequest to PF, so just 1078ee4bcd3bSJian Shen * change the mac state to ACTIVE. 1079ee4bcd3bSJian Shen */ 1080ee4bcd3bSJian Shen new_node->state = HCLGEVF_MAC_ACTIVE; 1081ee4bcd3bSJian Shen list_del(&mac_node->node); 1082ee4bcd3bSJian Shen kfree(mac_node); 1083ee4bcd3bSJian Shen } else { 108449768ce9SBaokun Li list_move_tail(&mac_node->node, mac_list); 1085ee4bcd3bSJian Shen } 1086ee4bcd3bSJian Shen } 1087ee4bcd3bSJian Shen } 1088ee4bcd3bSJian Shen 1089ee4bcd3bSJian Shen static void hclgevf_clear_list(struct list_head *list) 1090ee4bcd3bSJian Shen { 1091ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp; 1092ee4bcd3bSJian Shen 1093ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, list, node) { 1094ee4bcd3bSJian Shen list_del(&mac_node->node); 1095ee4bcd3bSJian Shen kfree(mac_node); 1096ee4bcd3bSJian Shen } 1097ee4bcd3bSJian Shen } 1098ee4bcd3bSJian Shen 1099ee4bcd3bSJian Shen static void hclgevf_sync_mac_list(struct hclgevf_dev *hdev, 1100ee4bcd3bSJian Shen enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1101ee4bcd3bSJian Shen { 1102ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1103ee4bcd3bSJian Shen struct list_head tmp_add_list, tmp_del_list; 1104ee4bcd3bSJian Shen struct list_head *list; 1105ee4bcd3bSJian Shen 1106ee4bcd3bSJian Shen INIT_LIST_HEAD(&tmp_add_list); 1107ee4bcd3bSJian Shen INIT_LIST_HEAD(&tmp_del_list); 1108ee4bcd3bSJian Shen 1109ee4bcd3bSJian Shen /* move the mac addr to the tmp_add_list and tmp_del_list, then 1110ee4bcd3bSJian Shen * we can add/delete these mac addr outside the spin lock 1111ee4bcd3bSJian Shen */ 1112ee4bcd3bSJian Shen list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1113ee4bcd3bSJian Shen &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1114ee4bcd3bSJian Shen 1115ee4bcd3bSJian Shen spin_lock_bh(&hdev->mac_table.mac_list_lock); 1116ee4bcd3bSJian Shen 1117ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, list, node) { 1118ee4bcd3bSJian Shen switch (mac_node->state) { 1119ee4bcd3bSJian Shen case HCLGEVF_MAC_TO_DEL: 112049768ce9SBaokun Li list_move_tail(&mac_node->node, &tmp_del_list); 1121ee4bcd3bSJian Shen break; 1122ee4bcd3bSJian Shen case HCLGEVF_MAC_TO_ADD: 1123ee4bcd3bSJian Shen new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 1124ee4bcd3bSJian Shen if (!new_node) 1125ee4bcd3bSJian Shen goto stop_traverse; 1126ee4bcd3bSJian Shen 1127ee4bcd3bSJian Shen ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 1128ee4bcd3bSJian Shen new_node->state = mac_node->state; 1129ee4bcd3bSJian Shen list_add_tail(&new_node->node, &tmp_add_list); 1130ee4bcd3bSJian Shen break; 1131ee4bcd3bSJian Shen default: 1132ee4bcd3bSJian Shen break; 1133ee4bcd3bSJian Shen } 1134ee4bcd3bSJian Shen } 1135ee4bcd3bSJian Shen 1136ee4bcd3bSJian Shen stop_traverse: 1137ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1138ee4bcd3bSJian Shen 1139ee4bcd3bSJian Shen /* delete first, in order to get max mac table space for adding */ 1140ee4bcd3bSJian Shen hclgevf_config_mac_list(hdev, &tmp_del_list, mac_type); 1141ee4bcd3bSJian Shen hclgevf_config_mac_list(hdev, &tmp_add_list, mac_type); 1142ee4bcd3bSJian Shen 1143ee4bcd3bSJian Shen /* if some mac addresses were added/deleted fail, move back to the 1144ee4bcd3bSJian Shen * mac_list, and retry at next time. 1145ee4bcd3bSJian Shen */ 1146ee4bcd3bSJian Shen spin_lock_bh(&hdev->mac_table.mac_list_lock); 1147ee4bcd3bSJian Shen 1148ee4bcd3bSJian Shen hclgevf_sync_from_del_list(&tmp_del_list, list); 1149ee4bcd3bSJian Shen hclgevf_sync_from_add_list(&tmp_add_list, list); 1150ee4bcd3bSJian Shen 1151ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1152ee4bcd3bSJian Shen } 1153ee4bcd3bSJian Shen 1154ee4bcd3bSJian Shen static void hclgevf_sync_mac_table(struct hclgevf_dev *hdev) 1155ee4bcd3bSJian Shen { 1156ee4bcd3bSJian Shen hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_UC); 1157ee4bcd3bSJian Shen hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_MC); 1158ee4bcd3bSJian Shen } 1159ee4bcd3bSJian Shen 1160ee4bcd3bSJian Shen static void hclgevf_uninit_mac_list(struct hclgevf_dev *hdev) 1161ee4bcd3bSJian Shen { 1162ee4bcd3bSJian Shen spin_lock_bh(&hdev->mac_table.mac_list_lock); 1163ee4bcd3bSJian Shen 1164ee4bcd3bSJian Shen hclgevf_clear_list(&hdev->mac_table.uc_mac_list); 1165ee4bcd3bSJian Shen hclgevf_clear_list(&hdev->mac_table.mc_mac_list); 1166ee4bcd3bSJian Shen 1167ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1168ee4bcd3bSJian Shen } 1169ee4bcd3bSJian Shen 1170fa6a262aSJian Shen static int hclgevf_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 1171fa6a262aSJian Shen { 1172fa6a262aSJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1173fa6a262aSJian Shen struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 1174fa6a262aSJian Shen struct hclge_vf_to_pf_msg send_msg; 1175fa6a262aSJian Shen 1176fa6a262aSJian Shen if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 1177fa6a262aSJian Shen return -EOPNOTSUPP; 1178fa6a262aSJian Shen 1179fa6a262aSJian Shen hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1180fa6a262aSJian Shen HCLGE_MBX_ENABLE_VLAN_FILTER); 1181fa6a262aSJian Shen send_msg.data[0] = enable ? 1 : 0; 1182fa6a262aSJian Shen 1183fa6a262aSJian Shen return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1184fa6a262aSJian Shen } 1185fa6a262aSJian Shen 1186e2cb1decSSalil Mehta static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1187e2cb1decSSalil Mehta __be16 proto, u16 vlan_id, 1188e2cb1decSSalil Mehta bool is_kill) 1189e2cb1decSSalil Mehta { 1190e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1191416eedb6SJie Wang struct hclge_mbx_vlan_filter *vlan_filter; 1192d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1193fe4144d4SJian Shen int ret; 1194e2cb1decSSalil Mehta 1195b37ce587SYufeng Mo if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1196e2cb1decSSalil Mehta return -EINVAL; 1197e2cb1decSSalil Mehta 1198e2cb1decSSalil Mehta if (proto != htons(ETH_P_8021Q)) 1199e2cb1decSSalil Mehta return -EPROTONOSUPPORT; 1200e2cb1decSSalil Mehta 1201b7b5d25bSGuojia Liao /* When device is resetting or reset failed, firmware is unable to 1202b7b5d25bSGuojia Liao * handle mailbox. Just record the vlan id, and remove it after 1203fe4144d4SJian Shen * reset finished. 1204fe4144d4SJian Shen */ 1205b7b5d25bSGuojia Liao if ((test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 1206b7b5d25bSGuojia Liao test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) && is_kill) { 1207fe4144d4SJian Shen set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1208fe4144d4SJian Shen return -EBUSY; 120991442441SJian Shen } else if (!is_kill && test_bit(vlan_id, hdev->vlan_del_fail_bmap)) { 121091442441SJian Shen clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1211fe4144d4SJian Shen } 1212fe4144d4SJian Shen 1213d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1214d3410018SYufeng Mo HCLGE_MBX_VLAN_FILTER); 1215416eedb6SJie Wang vlan_filter = (struct hclge_mbx_vlan_filter *)send_msg.data; 1216416eedb6SJie Wang vlan_filter->is_kill = is_kill; 1217416eedb6SJie Wang vlan_filter->vlan_id = cpu_to_le16(vlan_id); 1218416eedb6SJie Wang vlan_filter->proto = cpu_to_le16(be16_to_cpu(proto)); 1219416eedb6SJie Wang 122046ee7350SGuojia Liao /* when remove hw vlan filter failed, record the vlan id, 1221fe4144d4SJian Shen * and try to remove it from hw later, to be consistence 1222fe4144d4SJian Shen * with stack. 1223fe4144d4SJian Shen */ 1224d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1225fe4144d4SJian Shen if (is_kill && ret) 1226fe4144d4SJian Shen set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1227fe4144d4SJian Shen 1228fe4144d4SJian Shen return ret; 1229fe4144d4SJian Shen } 1230fe4144d4SJian Shen 1231fe4144d4SJian Shen static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1232fe4144d4SJian Shen { 1233fe4144d4SJian Shen #define HCLGEVF_MAX_SYNC_COUNT 60 1234fe4144d4SJian Shen struct hnae3_handle *handle = &hdev->nic; 1235fe4144d4SJian Shen int ret, sync_cnt = 0; 1236fe4144d4SJian Shen u16 vlan_id; 1237fe4144d4SJian Shen 123891442441SJian Shen if (bitmap_empty(hdev->vlan_del_fail_bmap, VLAN_N_VID)) 123991442441SJian Shen return; 124091442441SJian Shen 124191442441SJian Shen rtnl_lock(); 1242fe4144d4SJian Shen vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1243fe4144d4SJian Shen while (vlan_id != VLAN_N_VID) { 1244fe4144d4SJian Shen ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1245fe4144d4SJian Shen vlan_id, true); 1246fe4144d4SJian Shen if (ret) 124791442441SJian Shen break; 1248fe4144d4SJian Shen 1249fe4144d4SJian Shen clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1250fe4144d4SJian Shen sync_cnt++; 1251fe4144d4SJian Shen if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 125291442441SJian Shen break; 1253fe4144d4SJian Shen 1254fe4144d4SJian Shen vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1255fe4144d4SJian Shen } 125691442441SJian Shen rtnl_unlock(); 1257e2cb1decSSalil Mehta } 1258e2cb1decSSalil Mehta 1259b2641e2aSYunsheng Lin static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1260b2641e2aSYunsheng Lin { 1261b2641e2aSYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1262d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1263b2641e2aSYunsheng Lin 1264d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1265d3410018SYufeng Mo HCLGE_MBX_VLAN_RX_OFF_CFG); 1266d3410018SYufeng Mo send_msg.data[0] = enable ? 1 : 0; 1267d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1268b2641e2aSYunsheng Lin } 1269b2641e2aSYunsheng Lin 12708fa86551SYufeng Mo static int hclgevf_reset_tqp(struct hnae3_handle *handle) 1271e2cb1decSSalil Mehta { 12728fa86551SYufeng Mo #define HCLGEVF_RESET_ALL_QUEUE_DONE 1U 1273e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1274d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 12758fa86551SYufeng Mo u8 return_status = 0; 12761a426f8bSPeng Li int ret; 12778fa86551SYufeng Mo u16 i; 1278e2cb1decSSalil Mehta 12791a426f8bSPeng Li /* disable vf queue before send queue reset msg to PF */ 12808fa86551SYufeng Mo ret = hclgevf_tqp_enable(handle, false); 12818fa86551SYufeng Mo if (ret) { 12828fa86551SYufeng Mo dev_err(&hdev->pdev->dev, "failed to disable tqp, ret = %d\n", 12838fa86551SYufeng Mo ret); 12847fa6be4fSHuazhong Tan return ret; 12858fa86551SYufeng Mo } 12861a426f8bSPeng Li 1287d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 12888fa86551SYufeng Mo 12898fa86551SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &return_status, 12908fa86551SYufeng Mo sizeof(return_status)); 12918fa86551SYufeng Mo if (ret || return_status == HCLGEVF_RESET_ALL_QUEUE_DONE) 12928fa86551SYufeng Mo return ret; 12938fa86551SYufeng Mo 12948fa86551SYufeng Mo for (i = 1; i < handle->kinfo.num_tqps; i++) { 12958fa86551SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 1296416eedb6SJie Wang *(__le16 *)send_msg.data = cpu_to_le16(i); 12978fa86551SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 12988fa86551SYufeng Mo if (ret) 12998fa86551SYufeng Mo return ret; 13008fa86551SYufeng Mo } 13018fa86551SYufeng Mo 13028fa86551SYufeng Mo return 0; 1303e2cb1decSSalil Mehta } 1304e2cb1decSSalil Mehta 1305818f1675SYunsheng Lin static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1306818f1675SYunsheng Lin { 1307818f1675SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1308416eedb6SJie Wang struct hclge_mbx_mtu_info *mtu_info; 1309d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1310818f1675SYunsheng Lin 1311d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MTU, 0); 1312416eedb6SJie Wang mtu_info = (struct hclge_mbx_mtu_info *)send_msg.data; 1313416eedb6SJie Wang mtu_info->mtu = cpu_to_le32(new_mtu); 1314416eedb6SJie Wang 1315d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1316818f1675SYunsheng Lin } 1317818f1675SYunsheng Lin 13186988eb2aSSalil Mehta static int hclgevf_notify_client(struct hclgevf_dev *hdev, 13196988eb2aSSalil Mehta enum hnae3_reset_notify_type type) 13206988eb2aSSalil Mehta { 13216988eb2aSSalil Mehta struct hnae3_client *client = hdev->nic_client; 13226988eb2aSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 13236a5f6fa3SHuazhong Tan int ret; 13246988eb2aSSalil Mehta 132525d1817cSHuazhong Tan if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 132625d1817cSHuazhong Tan !client) 132725d1817cSHuazhong Tan return 0; 132825d1817cSHuazhong Tan 13296988eb2aSSalil Mehta if (!client->ops->reset_notify) 13306988eb2aSSalil Mehta return -EOPNOTSUPP; 13316988eb2aSSalil Mehta 13326a5f6fa3SHuazhong Tan ret = client->ops->reset_notify(handle, type); 13336a5f6fa3SHuazhong Tan if (ret) 13346a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 13356a5f6fa3SHuazhong Tan type, ret); 13366a5f6fa3SHuazhong Tan 13376a5f6fa3SHuazhong Tan return ret; 13386988eb2aSSalil Mehta } 13396988eb2aSSalil Mehta 1340fe735c84SHuazhong Tan static int hclgevf_notify_roce_client(struct hclgevf_dev *hdev, 1341fe735c84SHuazhong Tan enum hnae3_reset_notify_type type) 1342fe735c84SHuazhong Tan { 1343fe735c84SHuazhong Tan struct hnae3_client *client = hdev->roce_client; 1344fe735c84SHuazhong Tan struct hnae3_handle *handle = &hdev->roce; 1345fe735c84SHuazhong Tan int ret; 1346fe735c84SHuazhong Tan 1347fe735c84SHuazhong Tan if (!test_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state) || !client) 1348fe735c84SHuazhong Tan return 0; 1349fe735c84SHuazhong Tan 1350fe735c84SHuazhong Tan if (!client->ops->reset_notify) 1351fe735c84SHuazhong Tan return -EOPNOTSUPP; 1352fe735c84SHuazhong Tan 1353fe735c84SHuazhong Tan ret = client->ops->reset_notify(handle, type); 1354fe735c84SHuazhong Tan if (ret) 1355fe735c84SHuazhong Tan dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 1356fe735c84SHuazhong Tan type, ret); 1357fe735c84SHuazhong Tan return ret; 1358fe735c84SHuazhong Tan } 1359fe735c84SHuazhong Tan 13606988eb2aSSalil Mehta static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 13616988eb2aSSalil Mehta { 1362aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_US 20000 1363aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_CNT 2000 1364aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1365aa5c4f17SHuazhong Tan (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1366aa5c4f17SHuazhong Tan 1367aa5c4f17SHuazhong Tan u32 val; 1368aa5c4f17SHuazhong Tan int ret; 13696988eb2aSSalil Mehta 1370f28368bbSHuazhong Tan if (hdev->reset_type == HNAE3_VF_RESET) 1371076bb537SJie Wang ret = readl_poll_timeout(hdev->hw.hw.io_base + 137272e2fb07SHuazhong Tan HCLGEVF_VF_RST_ING, val, 137372e2fb07SHuazhong Tan !(val & HCLGEVF_VF_RST_ING_BIT), 137472e2fb07SHuazhong Tan HCLGEVF_RESET_WAIT_US, 137572e2fb07SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 137672e2fb07SHuazhong Tan else 1377076bb537SJie Wang ret = readl_poll_timeout(hdev->hw.hw.io_base + 137872e2fb07SHuazhong Tan HCLGEVF_RST_ING, val, 1379aa5c4f17SHuazhong Tan !(val & HCLGEVF_RST_ING_BITS), 1380aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_US, 1381aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 13826988eb2aSSalil Mehta 13836988eb2aSSalil Mehta /* hardware completion status should be available by this time */ 1384aa5c4f17SHuazhong Tan if (ret) { 1385aa5c4f17SHuazhong Tan dev_err(&hdev->pdev->dev, 13868912fd6aSColin Ian King "couldn't get reset done status from h/w, timeout!\n"); 1387aa5c4f17SHuazhong Tan return ret; 13886988eb2aSSalil Mehta } 13896988eb2aSSalil Mehta 13906988eb2aSSalil Mehta /* we will wait a bit more to let reset of the stack to complete. This 13916988eb2aSSalil Mehta * might happen in case reset assertion was made by PF. Yes, this also 13926988eb2aSSalil Mehta * means we might end up waiting bit more even for VF reset. 13936988eb2aSSalil Mehta */ 1394814d0c78SJie Wang if (hdev->reset_type == HNAE3_VF_FULL_RESET) 13956988eb2aSSalil Mehta msleep(5000); 1396814d0c78SJie Wang else 1397814d0c78SJie Wang msleep(500); 13986988eb2aSSalil Mehta 13996988eb2aSSalil Mehta return 0; 14006988eb2aSSalil Mehta } 14016988eb2aSSalil Mehta 14026b428b4fSHuazhong Tan static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable) 14036b428b4fSHuazhong Tan { 14046b428b4fSHuazhong Tan u32 reg_val; 14056b428b4fSHuazhong Tan 1406cb413bfaSJie Wang reg_val = hclgevf_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG); 14076b428b4fSHuazhong Tan if (enable) 14086b428b4fSHuazhong Tan reg_val |= HCLGEVF_NIC_SW_RST_RDY; 14096b428b4fSHuazhong Tan else 14106b428b4fSHuazhong Tan reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; 14116b428b4fSHuazhong Tan 1412cb413bfaSJie Wang hclgevf_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, 14136b428b4fSHuazhong Tan reg_val); 14146b428b4fSHuazhong Tan } 14156b428b4fSHuazhong Tan 14166988eb2aSSalil Mehta static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 14176988eb2aSSalil Mehta { 14187a01c897SSalil Mehta int ret; 14197a01c897SSalil Mehta 14206988eb2aSSalil Mehta /* uninitialize the nic client */ 14216a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 14226a5f6fa3SHuazhong Tan if (ret) 14236a5f6fa3SHuazhong Tan return ret; 14246988eb2aSSalil Mehta 14257a01c897SSalil Mehta /* re-initialize the hclge device */ 14269c6f7085SHuazhong Tan ret = hclgevf_reset_hdev(hdev); 14277a01c897SSalil Mehta if (ret) { 14287a01c897SSalil Mehta dev_err(&hdev->pdev->dev, 14297a01c897SSalil Mehta "hclge device re-init failed, VF is disabled!\n"); 14307a01c897SSalil Mehta return ret; 14317a01c897SSalil Mehta } 14326988eb2aSSalil Mehta 14336988eb2aSSalil Mehta /* bring up the nic client again */ 14346a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 14356a5f6fa3SHuazhong Tan if (ret) 14366a5f6fa3SHuazhong Tan return ret; 14376988eb2aSSalil Mehta 14386b428b4fSHuazhong Tan /* clear handshake status with IMP */ 14396b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, false); 14406b428b4fSHuazhong Tan 14411cc9bc6eSHuazhong Tan /* bring up the nic to enable TX/RX again */ 14421cc9bc6eSHuazhong Tan return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 14436988eb2aSSalil Mehta } 14446988eb2aSSalil Mehta 1445dea846e8SHuazhong Tan static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1446dea846e8SHuazhong Tan { 1447ada13ee3SHuazhong Tan #define HCLGEVF_RESET_SYNC_TIME 100 1448ada13ee3SHuazhong Tan 1449f28368bbSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FUNC_RESET) { 1450d41884eeSHuazhong Tan struct hclge_vf_to_pf_msg send_msg; 1451d41884eeSHuazhong Tan int ret; 1452d41884eeSHuazhong Tan 1453d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_RESET, 0); 1454d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1455cddd5648SHuazhong Tan if (ret) { 1456cddd5648SHuazhong Tan dev_err(&hdev->pdev->dev, 1457cddd5648SHuazhong Tan "failed to assert VF reset, ret = %d\n", ret); 1458cddd5648SHuazhong Tan return ret; 1459cddd5648SHuazhong Tan } 1460c88a6e7dSHuazhong Tan hdev->rst_stats.vf_func_rst_cnt++; 1461dea846e8SHuazhong Tan } 1462dea846e8SHuazhong Tan 1463076bb537SJie Wang set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 1464ada13ee3SHuazhong Tan /* inform hardware that preparatory work is done */ 1465ada13ee3SHuazhong Tan msleep(HCLGEVF_RESET_SYNC_TIME); 14666b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, true); 1467d41884eeSHuazhong Tan dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done\n", 1468d41884eeSHuazhong Tan hdev->reset_type); 1469dea846e8SHuazhong Tan 1470d41884eeSHuazhong Tan return 0; 1471dea846e8SHuazhong Tan } 1472dea846e8SHuazhong Tan 14733d77d0cbSHuazhong Tan static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev) 14743d77d0cbSHuazhong Tan { 14753d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "VF function reset count: %u\n", 14763d77d0cbSHuazhong Tan hdev->rst_stats.vf_func_rst_cnt); 14773d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "FLR reset count: %u\n", 14783d77d0cbSHuazhong Tan hdev->rst_stats.flr_rst_cnt); 14793d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "VF reset count: %u\n", 14803d77d0cbSHuazhong Tan hdev->rst_stats.vf_rst_cnt); 14813d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "reset done count: %u\n", 14823d77d0cbSHuazhong Tan hdev->rst_stats.rst_done_cnt); 14833d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "HW reset done count: %u\n", 14843d77d0cbSHuazhong Tan hdev->rst_stats.hw_rst_done_cnt); 14853d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "reset count: %u\n", 14863d77d0cbSHuazhong Tan hdev->rst_stats.rst_cnt); 14873d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "reset fail count: %u\n", 14883d77d0cbSHuazhong Tan hdev->rst_stats.rst_fail_cnt); 14893d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n", 14903d77d0cbSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE)); 14913d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n", 1492cb413bfaSJie Wang hclgevf_read_dev(&hdev->hw, HCLGE_COMM_VECTOR0_CMDQ_STATE_REG)); 14933d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n", 1494cb413bfaSJie Wang hclgevf_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG)); 14953d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n", 14963d77d0cbSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING)); 14973d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state); 14983d77d0cbSHuazhong Tan } 14993d77d0cbSHuazhong Tan 1500bbe6540eSHuazhong Tan static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1501bbe6540eSHuazhong Tan { 15026b428b4fSHuazhong Tan /* recover handshake status with IMP when reset fail */ 15036b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, true); 1504bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt++; 1505adcf738bSGuojia Liao dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n", 1506bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt); 1507bbe6540eSHuazhong Tan 1508bbe6540eSHuazhong Tan if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1509bbe6540eSHuazhong Tan set_bit(hdev->reset_type, &hdev->reset_pending); 1510bbe6540eSHuazhong Tan 1511bbe6540eSHuazhong Tan if (hclgevf_is_reset_pending(hdev)) { 1512bbe6540eSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1513bbe6540eSHuazhong Tan hclgevf_reset_task_schedule(hdev); 15143d77d0cbSHuazhong Tan } else { 1515d5432455SGuojia Liao set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 15163d77d0cbSHuazhong Tan hclgevf_dump_rst_info(hdev); 1517bbe6540eSHuazhong Tan } 1518bbe6540eSHuazhong Tan } 1519bbe6540eSHuazhong Tan 15201cc9bc6eSHuazhong Tan static int hclgevf_reset_prepare(struct hclgevf_dev *hdev) 15216988eb2aSSalil Mehta { 15226988eb2aSSalil Mehta int ret; 15236988eb2aSSalil Mehta 1524c88a6e7dSHuazhong Tan hdev->rst_stats.rst_cnt++; 15256988eb2aSSalil Mehta 1526fe735c84SHuazhong Tan /* perform reset of the stack & ae device for a client */ 1527fe735c84SHuazhong Tan ret = hclgevf_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 1528fe735c84SHuazhong Tan if (ret) 1529fe735c84SHuazhong Tan return ret; 1530fe735c84SHuazhong Tan 15311cc9bc6eSHuazhong Tan rtnl_lock(); 15326988eb2aSSalil Mehta /* bring down the nic to stop any ongoing TX/RX */ 15336a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 153429118ab9SHuazhong Tan rtnl_unlock(); 15356a5f6fa3SHuazhong Tan if (ret) 15361cc9bc6eSHuazhong Tan return ret; 1537dea846e8SHuazhong Tan 15381cc9bc6eSHuazhong Tan return hclgevf_reset_prepare_wait(hdev); 15396988eb2aSSalil Mehta } 15406988eb2aSSalil Mehta 15411cc9bc6eSHuazhong Tan static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev) 15421cc9bc6eSHuazhong Tan { 15431cc9bc6eSHuazhong Tan int ret; 15441cc9bc6eSHuazhong Tan 1545c88a6e7dSHuazhong Tan hdev->rst_stats.hw_rst_done_cnt++; 1546fe735c84SHuazhong Tan ret = hclgevf_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 1547fe735c84SHuazhong Tan if (ret) 1548fe735c84SHuazhong Tan return ret; 1549c88a6e7dSHuazhong Tan 155029118ab9SHuazhong Tan rtnl_lock(); 15516988eb2aSSalil Mehta /* now, re-initialize the nic client and ae device */ 15526988eb2aSSalil Mehta ret = hclgevf_reset_stack(hdev); 15531cc9bc6eSHuazhong Tan rtnl_unlock(); 15546a5f6fa3SHuazhong Tan if (ret) { 15556988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 15561cc9bc6eSHuazhong Tan return ret; 15576a5f6fa3SHuazhong Tan } 15586988eb2aSSalil Mehta 1559fe735c84SHuazhong Tan ret = hclgevf_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 1560fe735c84SHuazhong Tan /* ignore RoCE notify error if it fails HCLGEVF_RESET_MAX_FAIL_CNT - 1 1561fe735c84SHuazhong Tan * times 1562fe735c84SHuazhong Tan */ 1563fe735c84SHuazhong Tan if (ret && 1564fe735c84SHuazhong Tan hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT - 1) 1565fe735c84SHuazhong Tan return ret; 1566fe735c84SHuazhong Tan 1567fe735c84SHuazhong Tan ret = hclgevf_notify_roce_client(hdev, HNAE3_UP_CLIENT); 1568fe735c84SHuazhong Tan if (ret) 1569fe735c84SHuazhong Tan return ret; 1570fe735c84SHuazhong Tan 1571b644a8d4SHuazhong Tan hdev->last_reset_time = jiffies; 1572c88a6e7dSHuazhong Tan hdev->rst_stats.rst_done_cnt++; 1573bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt = 0; 1574d5432455SGuojia Liao clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1575b644a8d4SHuazhong Tan 15761cc9bc6eSHuazhong Tan return 0; 15771cc9bc6eSHuazhong Tan } 15781cc9bc6eSHuazhong Tan 15791cc9bc6eSHuazhong Tan static void hclgevf_reset(struct hclgevf_dev *hdev) 15801cc9bc6eSHuazhong Tan { 15811cc9bc6eSHuazhong Tan if (hclgevf_reset_prepare(hdev)) 15821cc9bc6eSHuazhong Tan goto err_reset; 15831cc9bc6eSHuazhong Tan 15841cc9bc6eSHuazhong Tan /* check if VF could successfully fetch the hardware reset completion 15851cc9bc6eSHuazhong Tan * status from the hardware 15861cc9bc6eSHuazhong Tan */ 15871cc9bc6eSHuazhong Tan if (hclgevf_reset_wait(hdev)) { 15881cc9bc6eSHuazhong Tan /* can't do much in this situation, will disable VF */ 15891cc9bc6eSHuazhong Tan dev_err(&hdev->pdev->dev, 15901cc9bc6eSHuazhong Tan "failed to fetch H/W reset completion status\n"); 15911cc9bc6eSHuazhong Tan goto err_reset; 15921cc9bc6eSHuazhong Tan } 15931cc9bc6eSHuazhong Tan 15941cc9bc6eSHuazhong Tan if (hclgevf_reset_rebuild(hdev)) 15951cc9bc6eSHuazhong Tan goto err_reset; 15961cc9bc6eSHuazhong Tan 15971cc9bc6eSHuazhong Tan return; 15981cc9bc6eSHuazhong Tan 15996a5f6fa3SHuazhong Tan err_reset: 1600bbe6540eSHuazhong Tan hclgevf_reset_err_handle(hdev); 16016988eb2aSSalil Mehta } 16026988eb2aSSalil Mehta 1603ed1c6f35SPeiyang Wang static enum hnae3_reset_type hclgevf_get_reset_level(unsigned long *addr) 1604720bd583SHuazhong Tan { 1605720bd583SHuazhong Tan enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1606720bd583SHuazhong Tan 1607dea846e8SHuazhong Tan /* return the highest priority reset level amongst all */ 1608b90fcc5bSHuazhong Tan if (test_bit(HNAE3_VF_RESET, addr)) { 1609b90fcc5bSHuazhong Tan rst_level = HNAE3_VF_RESET; 1610b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_RESET, addr); 1611b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1612b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1613b90fcc5bSHuazhong Tan } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1614dea846e8SHuazhong Tan rst_level = HNAE3_VF_FULL_RESET; 1615dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FULL_RESET, addr); 1616dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1617aa5c4f17SHuazhong Tan } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1618aa5c4f17SHuazhong Tan rst_level = HNAE3_VF_PF_FUNC_RESET; 1619aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1620aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1621dea846e8SHuazhong Tan } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1622dea846e8SHuazhong Tan rst_level = HNAE3_VF_FUNC_RESET; 1623dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 16246ff3cf07SHuazhong Tan } else if (test_bit(HNAE3_FLR_RESET, addr)) { 16256ff3cf07SHuazhong Tan rst_level = HNAE3_FLR_RESET; 16266ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_RESET, addr); 1627720bd583SHuazhong Tan } 1628720bd583SHuazhong Tan 1629720bd583SHuazhong Tan return rst_level; 1630720bd583SHuazhong Tan } 1631720bd583SHuazhong Tan 16326ae4e733SShiju Jose static void hclgevf_reset_event(struct pci_dev *pdev, 16336ae4e733SShiju Jose struct hnae3_handle *handle) 16346d4c3981SSalil Mehta { 16356ff3cf07SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 16366ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 16376d4c3981SSalil Mehta 16386d4c3981SSalil Mehta dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 16396d4c3981SSalil Mehta 16406ff3cf07SHuazhong Tan if (hdev->default_reset_request) 16410742ed7cSHuazhong Tan hdev->reset_level = 1642ed1c6f35SPeiyang Wang hclgevf_get_reset_level(&hdev->default_reset_request); 1643720bd583SHuazhong Tan else 1644dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 16456d4c3981SSalil Mehta 1646436667d2SSalil Mehta /* reset of this VF requested */ 1647436667d2SSalil Mehta set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1648436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 16496d4c3981SSalil Mehta 16500742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 16516d4c3981SSalil Mehta } 16526d4c3981SSalil Mehta 1653720bd583SHuazhong Tan static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1654720bd583SHuazhong Tan enum hnae3_reset_type rst_type) 1655720bd583SHuazhong Tan { 1656720bd583SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1657720bd583SHuazhong Tan 1658720bd583SHuazhong Tan set_bit(rst_type, &hdev->default_reset_request); 1659720bd583SHuazhong Tan } 1660720bd583SHuazhong Tan 1661f28368bbSHuazhong Tan static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1662f28368bbSHuazhong Tan { 1663f28368bbSHuazhong Tan writel(en ? 1 : 0, vector->addr); 1664f28368bbSHuazhong Tan } 1665f28368bbSHuazhong Tan 1666bb1890d5SJiaran Zhang static void hclgevf_reset_prepare_general(struct hnae3_ae_dev *ae_dev, 1667bb1890d5SJiaran Zhang enum hnae3_reset_type rst_type) 16686ff3cf07SHuazhong Tan { 1669bb1890d5SJiaran Zhang #define HCLGEVF_RESET_RETRY_WAIT_MS 500 1670bb1890d5SJiaran Zhang #define HCLGEVF_RESET_RETRY_CNT 5 1671f28368bbSHuazhong Tan 16726ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1673f28368bbSHuazhong Tan int retry_cnt = 0; 1674f28368bbSHuazhong Tan int ret; 16756ff3cf07SHuazhong Tan 1676ed0e658cSJiaran Zhang while (retry_cnt++ < HCLGEVF_RESET_RETRY_CNT) { 1677f28368bbSHuazhong Tan down(&hdev->reset_sem); 1678f28368bbSHuazhong Tan set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1679bb1890d5SJiaran Zhang hdev->reset_type = rst_type; 1680f28368bbSHuazhong Tan ret = hclgevf_reset_prepare(hdev); 1681ed0e658cSJiaran Zhang if (!ret && !hdev->reset_pending) 1682ed0e658cSJiaran Zhang break; 1683ed0e658cSJiaran Zhang 16846ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 1685ed0e658cSJiaran Zhang "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n", 1686ed0e658cSJiaran Zhang ret, hdev->reset_pending, retry_cnt); 1687f28368bbSHuazhong Tan clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1688f28368bbSHuazhong Tan up(&hdev->reset_sem); 1689bb1890d5SJiaran Zhang msleep(HCLGEVF_RESET_RETRY_WAIT_MS); 1690f28368bbSHuazhong Tan } 1691f28368bbSHuazhong Tan 1692bb1890d5SJiaran Zhang /* disable misc vector before reset done */ 1693f28368bbSHuazhong Tan hclgevf_enable_vector(&hdev->misc_vector, false); 1694bb1890d5SJiaran Zhang 1695bb1890d5SJiaran Zhang if (hdev->reset_type == HNAE3_FLR_RESET) 1696f28368bbSHuazhong Tan hdev->rst_stats.flr_rst_cnt++; 1697f28368bbSHuazhong Tan } 1698f28368bbSHuazhong Tan 1699bb1890d5SJiaran Zhang static void hclgevf_reset_done(struct hnae3_ae_dev *ae_dev) 1700f28368bbSHuazhong Tan { 1701f28368bbSHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1702f28368bbSHuazhong Tan int ret; 1703f28368bbSHuazhong Tan 1704f28368bbSHuazhong Tan hclgevf_enable_vector(&hdev->misc_vector, true); 1705f28368bbSHuazhong Tan 1706f28368bbSHuazhong Tan ret = hclgevf_reset_rebuild(hdev); 1707f28368bbSHuazhong Tan if (ret) 1708f28368bbSHuazhong Tan dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", 1709f28368bbSHuazhong Tan ret); 1710f28368bbSHuazhong Tan 1711f28368bbSHuazhong Tan hdev->reset_type = HNAE3_NONE_RESET; 1712f28368bbSHuazhong Tan clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1713f28368bbSHuazhong Tan up(&hdev->reset_sem); 17146ff3cf07SHuazhong Tan } 17156ff3cf07SHuazhong Tan 1716e2cb1decSSalil Mehta static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1717e2cb1decSSalil Mehta { 1718e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1719e2cb1decSSalil Mehta 1720e2cb1decSSalil Mehta return hdev->fw_version; 1721e2cb1decSSalil Mehta } 1722e2cb1decSSalil Mehta 1723e2cb1decSSalil Mehta static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1724e2cb1decSSalil Mehta { 1725e2cb1decSSalil Mehta struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1726e2cb1decSSalil Mehta 1727e2cb1decSSalil Mehta vector->vector_irq = pci_irq_vector(hdev->pdev, 1728e2cb1decSSalil Mehta HCLGEVF_MISC_VECTOR_NUM); 1729076bb537SJie Wang vector->addr = hdev->hw.hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1730e2cb1decSSalil Mehta /* vector status always valid for Vector 0 */ 1731e2cb1decSSalil Mehta hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1732e2cb1decSSalil Mehta hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1733e2cb1decSSalil Mehta 1734e2cb1decSSalil Mehta hdev->num_msi_left -= 1; 1735e2cb1decSSalil Mehta hdev->num_msi_used += 1; 1736e2cb1decSSalil Mehta } 1737e2cb1decSSalil Mehta 173835a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 173935a1e503SSalil Mehta { 1740ff200099SYunsheng Lin if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 17410251d196SGuangbin Huang test_bit(HCLGEVF_STATE_SERVICE_INITED, &hdev->state) && 1742ff200099SYunsheng Lin !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, 1743ff200099SYunsheng Lin &hdev->state)) 17440ea68902SYunsheng Lin mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 174535a1e503SSalil Mehta } 174635a1e503SSalil Mehta 174707a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1748e2cb1decSSalil Mehta { 1749ff200099SYunsheng Lin if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1750ff200099SYunsheng Lin !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, 1751ff200099SYunsheng Lin &hdev->state)) 17520ea68902SYunsheng Lin mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 175307a0556aSSalil Mehta } 1754e2cb1decSSalil Mehta 1755ff200099SYunsheng Lin static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 1756ff200099SYunsheng Lin unsigned long delay) 1757e2cb1decSSalil Mehta { 1758d5432455SGuojia Liao if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1759d5432455SGuojia Liao !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 17600ea68902SYunsheng Lin mod_delayed_work(hclgevf_wq, &hdev->service_task, delay); 1761e2cb1decSSalil Mehta } 1762e2cb1decSSalil Mehta 1763ff200099SYunsheng Lin static void hclgevf_reset_service_task(struct hclgevf_dev *hdev) 176435a1e503SSalil Mehta { 1765d6ad7c53SGuojia Liao #define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3 1766d6ad7c53SGuojia Liao 1767ff200099SYunsheng Lin if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state)) 1768ff200099SYunsheng Lin return; 1769ff200099SYunsheng Lin 1770f28368bbSHuazhong Tan down(&hdev->reset_sem); 1771f28368bbSHuazhong Tan set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 177235a1e503SSalil Mehta 1773436667d2SSalil Mehta if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1774436667d2SSalil Mehta &hdev->reset_state)) { 1775cd7e963dSSalil Mehta /* PF has intimated that it is about to reset the hardware. 17769b2f3477SWeihang Li * We now have to poll & check if hardware has actually 17779b2f3477SWeihang Li * completed the reset sequence. On hardware reset completion, 17789b2f3477SWeihang Li * VF needs to reset the client and ae device. 177935a1e503SSalil Mehta */ 1780436667d2SSalil Mehta hdev->reset_attempts = 0; 1781436667d2SSalil Mehta 1782dea846e8SHuazhong Tan hdev->last_reset_time = jiffies; 17831385cc81SYufeng Mo hdev->reset_type = 1784ed1c6f35SPeiyang Wang hclgevf_get_reset_level(&hdev->reset_pending); 17851385cc81SYufeng Mo if (hdev->reset_type != HNAE3_NONE_RESET) 17861cc9bc6eSHuazhong Tan hclgevf_reset(hdev); 1787436667d2SSalil Mehta } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1788436667d2SSalil Mehta &hdev->reset_state)) { 1789436667d2SSalil Mehta /* we could be here when either of below happens: 17909b2f3477SWeihang Li * 1. reset was initiated due to watchdog timeout caused by 1791436667d2SSalil Mehta * a. IMP was earlier reset and our TX got choked down and 1792436667d2SSalil Mehta * which resulted in watchdog reacting and inducing VF 1793436667d2SSalil Mehta * reset. This also means our cmdq would be unreliable. 1794436667d2SSalil Mehta * b. problem in TX due to other lower layer(example link 1795436667d2SSalil Mehta * layer not functioning properly etc.) 1796436667d2SSalil Mehta * 2. VF reset might have been initiated due to some config 1797436667d2SSalil Mehta * change. 1798436667d2SSalil Mehta * 1799436667d2SSalil Mehta * NOTE: Theres no clear way to detect above cases than to react 1800436667d2SSalil Mehta * to the response of PF for this reset request. PF will ack the 1801436667d2SSalil Mehta * 1b and 2. cases but we will not get any intimation about 1a 1802436667d2SSalil Mehta * from PF as cmdq would be in unreliable state i.e. mailbox 1803436667d2SSalil Mehta * communication between PF and VF would be broken. 180446ee7350SGuojia Liao * 180546ee7350SGuojia Liao * if we are never geting into pending state it means either: 1806436667d2SSalil Mehta * 1. PF is not receiving our request which could be due to IMP 1807436667d2SSalil Mehta * reset 1808436667d2SSalil Mehta * 2. PF is screwed 1809436667d2SSalil Mehta * We cannot do much for 2. but to check first we can try reset 1810436667d2SSalil Mehta * our PCIe + stack and see if it alleviates the problem. 1811436667d2SSalil Mehta */ 1812d6ad7c53SGuojia Liao if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) { 1813436667d2SSalil Mehta /* prepare for full reset of stack + pcie interface */ 1814dea846e8SHuazhong Tan set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1815436667d2SSalil Mehta 1816436667d2SSalil Mehta /* "defer" schedule the reset task again */ 1817436667d2SSalil Mehta set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1818436667d2SSalil Mehta } else { 1819436667d2SSalil Mehta hdev->reset_attempts++; 1820436667d2SSalil Mehta 1821dea846e8SHuazhong Tan set_bit(hdev->reset_level, &hdev->reset_pending); 1822dea846e8SHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1823436667d2SSalil Mehta } 1824dea846e8SHuazhong Tan hclgevf_reset_task_schedule(hdev); 1825436667d2SSalil Mehta } 182635a1e503SSalil Mehta 1827afb6afdbSHuazhong Tan hdev->reset_type = HNAE3_NONE_RESET; 182835a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1829f28368bbSHuazhong Tan up(&hdev->reset_sem); 183035a1e503SSalil Mehta } 183135a1e503SSalil Mehta 1832ff200099SYunsheng Lin static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev) 1833e2cb1decSSalil Mehta { 1834ff200099SYunsheng Lin if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state)) 1835ff200099SYunsheng Lin return; 1836e2cb1decSSalil Mehta 1837e2cb1decSSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1838e2cb1decSSalil Mehta return; 1839e2cb1decSSalil Mehta 184007a0556aSSalil Mehta hclgevf_mbx_async_handler(hdev); 1841e2cb1decSSalil Mehta 1842e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1843e2cb1decSSalil Mehta } 1844e2cb1decSSalil Mehta 1845ff200099SYunsheng Lin static void hclgevf_keep_alive(struct hclgevf_dev *hdev) 1846a6d818e3SYunsheng Lin { 1847d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1848a6d818e3SYunsheng Lin int ret; 1849a6d818e3SYunsheng Lin 1850076bb537SJie Wang if (test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state)) 1851c59a85c0SJian Shen return; 1852c59a85c0SJian Shen 1853d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_KEEP_ALIVE, 0); 1854d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1855a6d818e3SYunsheng Lin if (ret) 1856a6d818e3SYunsheng Lin dev_err(&hdev->pdev->dev, 1857a6d818e3SYunsheng Lin "VF sends keep alive cmd failed(=%d)\n", ret); 1858a6d818e3SYunsheng Lin } 1859a6d818e3SYunsheng Lin 1860ff200099SYunsheng Lin static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev) 1861e2cb1decSSalil Mehta { 1862ff200099SYunsheng Lin unsigned long delta = round_jiffies_relative(HZ); 1863ff200099SYunsheng Lin struct hnae3_handle *handle = &hdev->nic; 1864e2cb1decSSalil Mehta 1865bd3caddfSJie Wang if (test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state) || 1866bd3caddfSJie Wang test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state)) 1867e6394363SGuangbin Huang return; 1868e6394363SGuangbin Huang 1869ff200099SYunsheng Lin if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 1870ff200099SYunsheng Lin delta = jiffies - hdev->last_serv_processed; 1871db01afebSliuzhongzhu 1872ff200099SYunsheng Lin if (delta < round_jiffies_relative(HZ)) { 1873ff200099SYunsheng Lin delta = round_jiffies_relative(HZ) - delta; 1874ff200099SYunsheng Lin goto out; 1875db01afebSliuzhongzhu } 1876ff200099SYunsheng Lin } 1877ff200099SYunsheng Lin 1878ff200099SYunsheng Lin hdev->serv_processed_cnt++; 1879ff200099SYunsheng Lin if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL)) 1880ff200099SYunsheng Lin hclgevf_keep_alive(hdev); 1881ff200099SYunsheng Lin 1882ff200099SYunsheng Lin if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) { 1883ff200099SYunsheng Lin hdev->last_serv_processed = jiffies; 1884ff200099SYunsheng Lin goto out; 1885ff200099SYunsheng Lin } 1886ff200099SYunsheng Lin 1887ff200099SYunsheng Lin if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL)) 18884afc310cSJie Wang hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 1889e2cb1decSSalil Mehta 189001305e16SGuangbin Huang /* VF does not need to request link status when this bit is set, because 189101305e16SGuangbin Huang * PF will push its link status to VFs when link status changed. 1892e2cb1decSSalil Mehta */ 189301305e16SGuangbin Huang if (!test_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state)) 1894e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1895e2cb1decSSalil Mehta 18969194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 18979194d18bSliuzhongzhu 1898fe4144d4SJian Shen hclgevf_sync_vlan_filter(hdev); 1899fe4144d4SJian Shen 1900ee4bcd3bSJian Shen hclgevf_sync_mac_table(hdev); 1901ee4bcd3bSJian Shen 1902c631c696SJian Shen hclgevf_sync_promisc_mode(hdev); 1903c631c696SJian Shen 1904ff200099SYunsheng Lin hdev->last_serv_processed = jiffies; 1905436667d2SSalil Mehta 1906ff200099SYunsheng Lin out: 1907ff200099SYunsheng Lin hclgevf_task_schedule(hdev, delta); 1908ff200099SYunsheng Lin } 1909b3c3fe8eSYunsheng Lin 1910ff200099SYunsheng Lin static void hclgevf_service_task(struct work_struct *work) 1911ff200099SYunsheng Lin { 1912ff200099SYunsheng Lin struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev, 1913ff200099SYunsheng Lin service_task.work); 1914ff200099SYunsheng Lin 1915ff200099SYunsheng Lin hclgevf_reset_service_task(hdev); 1916ff200099SYunsheng Lin hclgevf_mailbox_service_task(hdev); 1917ff200099SYunsheng Lin hclgevf_periodic_service_task(hdev); 1918ff200099SYunsheng Lin 1919ff200099SYunsheng Lin /* Handle reset and mbx again in case periodical task delays the 1920ff200099SYunsheng Lin * handling by calling hclgevf_task_schedule() in 1921ff200099SYunsheng Lin * hclgevf_periodic_service_task() 1922ff200099SYunsheng Lin */ 1923ff200099SYunsheng Lin hclgevf_reset_service_task(hdev); 1924ff200099SYunsheng Lin hclgevf_mailbox_service_task(hdev); 1925e2cb1decSSalil Mehta } 1926e2cb1decSSalil Mehta 1927e2cb1decSSalil Mehta static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1928e2cb1decSSalil Mehta { 1929cb413bfaSJie Wang hclgevf_write_dev(&hdev->hw, HCLGE_COMM_VECTOR0_CMDQ_SRC_REG, regclr); 1930e2cb1decSSalil Mehta } 1931e2cb1decSSalil Mehta 1932b90fcc5bSHuazhong Tan static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1933b90fcc5bSHuazhong Tan u32 *clearval) 1934e2cb1decSSalil Mehta { 193513050921SHuazhong Tan u32 val, cmdq_stat_reg, rst_ing_reg; 1936e2cb1decSSalil Mehta 1937e2cb1decSSalil Mehta /* fetch the events from their corresponding regs */ 193813050921SHuazhong Tan cmdq_stat_reg = hclgevf_read_dev(&hdev->hw, 1939cb413bfaSJie Wang HCLGE_COMM_VECTOR0_CMDQ_STATE_REG); 194013050921SHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 1941b90fcc5bSHuazhong Tan rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1942b90fcc5bSHuazhong Tan dev_info(&hdev->pdev->dev, 1943b90fcc5bSHuazhong Tan "receive reset interrupt 0x%x!\n", rst_ing_reg); 1944b90fcc5bSHuazhong Tan set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1945b90fcc5bSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1946076bb537SJie Wang set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 194713050921SHuazhong Tan *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B); 1948c88a6e7dSHuazhong Tan hdev->rst_stats.vf_rst_cnt++; 194972e2fb07SHuazhong Tan /* set up VF hardware reset status, its PF will clear 195072e2fb07SHuazhong Tan * this status when PF has initialized done. 195172e2fb07SHuazhong Tan */ 195272e2fb07SHuazhong Tan val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING); 195372e2fb07SHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING, 195472e2fb07SHuazhong Tan val | HCLGEVF_VF_RST_ING_BIT); 1955b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_RST; 1956b90fcc5bSHuazhong Tan } 1957b90fcc5bSHuazhong Tan 1958e2cb1decSSalil Mehta /* check for vector0 mailbox(=CMDQ RX) event source */ 195913050921SHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 196013050921SHuazhong Tan /* for revision 0x21, clearing interrupt is writing bit 0 196113050921SHuazhong Tan * to the clear register, writing bit 1 means to keep the 196213050921SHuazhong Tan * old value. 196313050921SHuazhong Tan * for revision 0x20, the clear register is a read & write 196413050921SHuazhong Tan * register, so we should just write 0 to the bit we are 196513050921SHuazhong Tan * handling, and keep other bits as cmdq_stat_reg. 196613050921SHuazhong Tan */ 1967295ba232SGuangbin Huang if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) 196813050921SHuazhong Tan *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 196913050921SHuazhong Tan else 197013050921SHuazhong Tan *clearval = cmdq_stat_reg & 197113050921SHuazhong Tan ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 197213050921SHuazhong Tan 1973b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_MBX; 1974e2cb1decSSalil Mehta } 1975e2cb1decSSalil Mehta 1976e45afb39SHuazhong Tan /* print other vector0 event source */ 1977e45afb39SHuazhong Tan dev_info(&hdev->pdev->dev, 1978e45afb39SHuazhong Tan "vector 0 interrupt from unknown source, cmdq_src = %#x\n", 1979e45afb39SHuazhong Tan cmdq_stat_reg); 1980e2cb1decSSalil Mehta 1981b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_OTHER; 1982e2cb1decSSalil Mehta } 1983e2cb1decSSalil Mehta 1984*fbcad948SJijie Shao static void hclgevf_reset_timer(struct timer_list *t) 1985*fbcad948SJijie Shao { 1986*fbcad948SJijie Shao struct hclgevf_dev *hdev = from_timer(hdev, t, reset_timer); 1987*fbcad948SJijie Shao 1988*fbcad948SJijie Shao hclgevf_clear_event_cause(hdev, HCLGEVF_VECTOR0_EVENT_RST); 1989*fbcad948SJijie Shao hclgevf_reset_task_schedule(hdev); 1990*fbcad948SJijie Shao } 1991*fbcad948SJijie Shao 1992e2cb1decSSalil Mehta static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1993e2cb1decSSalil Mehta { 1994*fbcad948SJijie Shao #define HCLGEVF_RESET_DELAY 5 1995*fbcad948SJijie Shao 1996b90fcc5bSHuazhong Tan enum hclgevf_evt_cause event_cause; 1997e2cb1decSSalil Mehta struct hclgevf_dev *hdev = data; 1998e2cb1decSSalil Mehta u32 clearval; 1999e2cb1decSSalil Mehta 2000e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 2001b90fcc5bSHuazhong Tan event_cause = hclgevf_check_evt_cause(hdev, &clearval); 2002427900d2SJiaran Zhang if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) 2003427900d2SJiaran Zhang hclgevf_clear_event_cause(hdev, clearval); 2004e2cb1decSSalil Mehta 2005b90fcc5bSHuazhong Tan switch (event_cause) { 2006b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_RST: 2007*fbcad948SJijie Shao mod_timer(&hdev->reset_timer, 2008*fbcad948SJijie Shao jiffies + msecs_to_jiffies(HCLGEVF_RESET_DELAY)); 2009b90fcc5bSHuazhong Tan break; 2010b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_MBX: 201107a0556aSSalil Mehta hclgevf_mbx_handler(hdev); 2012b90fcc5bSHuazhong Tan break; 2013b90fcc5bSHuazhong Tan default: 2014b90fcc5bSHuazhong Tan break; 2015b90fcc5bSHuazhong Tan } 2016e2cb1decSSalil Mehta 2017e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2018e2cb1decSSalil Mehta 2019e2cb1decSSalil Mehta return IRQ_HANDLED; 2020e2cb1decSSalil Mehta } 2021e2cb1decSSalil Mehta 2022e2cb1decSSalil Mehta static int hclgevf_configure(struct hclgevf_dev *hdev) 2023e2cb1decSSalil Mehta { 2024e2cb1decSSalil Mehta int ret; 2025e2cb1decSSalil Mehta 20263462207dSYufeng Mo hdev->gro_en = true; 20273462207dSYufeng Mo 202832e6d104SJian Shen ret = hclgevf_get_basic_info(hdev); 202932e6d104SJian Shen if (ret) 203032e6d104SJian Shen return ret; 203132e6d104SJian Shen 203292f11ea1SJian Shen /* get current port based vlan state from PF */ 203392f11ea1SJian Shen ret = hclgevf_get_port_base_vlan_filter_state(hdev); 203492f11ea1SJian Shen if (ret) 203592f11ea1SJian Shen return ret; 203692f11ea1SJian Shen 2037e2cb1decSSalil Mehta /* get queue configuration from PF */ 20386cee6fc3SJian Shen ret = hclgevf_get_queue_info(hdev); 2039e2cb1decSSalil Mehta if (ret) 2040e2cb1decSSalil Mehta return ret; 2041c0425944SPeng Li 2042c0425944SPeng Li /* get queue depth info from PF */ 2043c0425944SPeng Li ret = hclgevf_get_queue_depth(hdev); 2044c0425944SPeng Li if (ret) 2045c0425944SPeng Li return ret; 2046c0425944SPeng Li 204732e6d104SJian Shen return hclgevf_get_pf_media_type(hdev); 2048e2cb1decSSalil Mehta } 2049e2cb1decSSalil Mehta 20507a01c897SSalil Mehta static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 20517a01c897SSalil Mehta { 20527a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 20531154bb26SPeng Li struct hclgevf_dev *hdev; 20547a01c897SSalil Mehta 20557a01c897SSalil Mehta hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 20567a01c897SSalil Mehta if (!hdev) 20577a01c897SSalil Mehta return -ENOMEM; 20587a01c897SSalil Mehta 20597a01c897SSalil Mehta hdev->pdev = pdev; 20607a01c897SSalil Mehta hdev->ae_dev = ae_dev; 20617a01c897SSalil Mehta ae_dev->priv = hdev; 20627a01c897SSalil Mehta 20637a01c897SSalil Mehta return 0; 20647a01c897SSalil Mehta } 20657a01c897SSalil Mehta 2066e2cb1decSSalil Mehta static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 2067e2cb1decSSalil Mehta { 2068e2cb1decSSalil Mehta struct hnae3_handle *roce = &hdev->roce; 2069e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 2070e2cb1decSSalil Mehta 207107acf909SJian Shen roce->rinfo.num_vectors = hdev->num_roce_msix; 2072e2cb1decSSalil Mehta 2073e2cb1decSSalil Mehta if (hdev->num_msi_left < roce->rinfo.num_vectors || 2074e2cb1decSSalil Mehta hdev->num_msi_left == 0) 2075e2cb1decSSalil Mehta return -EINVAL; 2076e2cb1decSSalil Mehta 2077beb27ca4SJie Wang roce->rinfo.base_vector = hdev->roce_base_msix_offset; 2078e2cb1decSSalil Mehta 2079e2cb1decSSalil Mehta roce->rinfo.netdev = nic->kinfo.netdev; 2080076bb537SJie Wang roce->rinfo.roce_io_base = hdev->hw.hw.io_base; 2081076bb537SJie Wang roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base; 2082e2cb1decSSalil Mehta 2083e2cb1decSSalil Mehta roce->pdev = nic->pdev; 2084e2cb1decSSalil Mehta roce->ae_algo = nic->ae_algo; 2085e2cb1decSSalil Mehta roce->numa_node_mask = nic->numa_node_mask; 2086e2cb1decSSalil Mehta 2087e2cb1decSSalil Mehta return 0; 2088e2cb1decSSalil Mehta } 2089e2cb1decSSalil Mehta 20903462207dSYufeng Mo static int hclgevf_config_gro(struct hclgevf_dev *hdev) 2091b26a6feaSPeng Li { 2092b26a6feaSPeng Li struct hclgevf_cfg_gro_status_cmd *req; 20936befad60SJie Wang struct hclge_desc desc; 2094b26a6feaSPeng Li int ret; 2095b26a6feaSPeng Li 2096507e46aeSGuangbin Huang if (!hnae3_ae_dev_gro_supported(hdev->ae_dev)) 2097b26a6feaSPeng Li return 0; 2098b26a6feaSPeng Li 209943710bfeSJie Wang hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, 2100b26a6feaSPeng Li false); 2101b26a6feaSPeng Li req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2102b26a6feaSPeng Li 21033462207dSYufeng Mo req->gro_en = hdev->gro_en ? 1 : 0; 2104b26a6feaSPeng Li 2105b26a6feaSPeng Li ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2106b26a6feaSPeng Li if (ret) 2107b26a6feaSPeng Li dev_err(&hdev->pdev->dev, 2108b26a6feaSPeng Li "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2109b26a6feaSPeng Li 2110b26a6feaSPeng Li return ret; 2111b26a6feaSPeng Li } 2112b26a6feaSPeng Li 2113944de484SGuojia Liao static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2114944de484SGuojia Liao { 2115027733b1SJie Wang struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 211693969dc1SJie Wang u16 tc_offset[HCLGE_COMM_MAX_TC_NUM]; 211793969dc1SJie Wang u16 tc_valid[HCLGE_COMM_MAX_TC_NUM]; 211893969dc1SJie Wang u16 tc_size[HCLGE_COMM_MAX_TC_NUM]; 2119944de484SGuojia Liao int ret; 2120944de484SGuojia Liao 2121295ba232SGuangbin Huang if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 21227428d6c9SJie Wang ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, 21237428d6c9SJie Wang rss_cfg->rss_algo, 2124944de484SGuojia Liao rss_cfg->rss_hash_key); 2125944de484SGuojia Liao if (ret) 2126944de484SGuojia Liao return ret; 2127944de484SGuojia Liao 2128ed1c6f35SPeiyang Wang ret = hclge_comm_set_rss_input_tuple(&hdev->hw.hw, rss_cfg); 2129944de484SGuojia Liao if (ret) 2130944de484SGuojia Liao return ret; 2131944de484SGuojia Liao } 2132e2cb1decSSalil Mehta 21337428d6c9SJie Wang ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 21347428d6c9SJie Wang rss_cfg->rss_indirection_tbl); 2135e2cb1decSSalil Mehta if (ret) 2136e2cb1decSSalil Mehta return ret; 2137e2cb1decSSalil Mehta 213893969dc1SJie Wang hclge_comm_get_rss_tc_info(rss_cfg->rss_size, hdev->hw_tc_map, 213993969dc1SJie Wang tc_offset, tc_valid, tc_size); 214093969dc1SJie Wang 214193969dc1SJie Wang return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, 214293969dc1SJie Wang tc_valid, tc_size); 2143e2cb1decSSalil Mehta } 2144e2cb1decSSalil Mehta 2145e2cb1decSSalil Mehta static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2146e2cb1decSSalil Mehta { 2147bbfd4506SJian Shen struct hnae3_handle *nic = &hdev->nic; 2148bbfd4506SJian Shen int ret; 2149bbfd4506SJian Shen 2150bbfd4506SJian Shen ret = hclgevf_en_hw_strip_rxvtag(nic, true); 2151bbfd4506SJian Shen if (ret) { 2152bbfd4506SJian Shen dev_err(&hdev->pdev->dev, 2153bbfd4506SJian Shen "failed to enable rx vlan offload, ret = %d\n", ret); 2154bbfd4506SJian Shen return ret; 2155bbfd4506SJian Shen } 2156bbfd4506SJian Shen 2157e2cb1decSSalil Mehta return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2158e2cb1decSSalil Mehta false); 2159e2cb1decSSalil Mehta } 2160e2cb1decSSalil Mehta 2161ff200099SYunsheng Lin static void hclgevf_flush_link_update(struct hclgevf_dev *hdev) 2162ff200099SYunsheng Lin { 2163ff200099SYunsheng Lin #define HCLGEVF_FLUSH_LINK_TIMEOUT 100000 2164ff200099SYunsheng Lin 2165ff200099SYunsheng Lin unsigned long last = hdev->serv_processed_cnt; 2166ff200099SYunsheng Lin int i = 0; 2167ff200099SYunsheng Lin 2168ff200099SYunsheng Lin while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) && 2169ff200099SYunsheng Lin i++ < HCLGEVF_FLUSH_LINK_TIMEOUT && 2170ff200099SYunsheng Lin last == hdev->serv_processed_cnt) 2171ff200099SYunsheng Lin usleep_range(1, 1); 2172ff200099SYunsheng Lin } 2173ff200099SYunsheng Lin 21748cdb992fSJian Shen static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 21758cdb992fSJian Shen { 21768cdb992fSJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 21778cdb992fSJian Shen 21788cdb992fSJian Shen if (enable) { 2179ff200099SYunsheng Lin hclgevf_task_schedule(hdev, 0); 21808cdb992fSJian Shen } else { 2181b3c3fe8eSYunsheng Lin set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2182ff200099SYunsheng Lin 2183ff200099SYunsheng Lin /* flush memory to make sure DOWN is seen by service task */ 2184ff200099SYunsheng Lin smp_mb__before_atomic(); 2185ff200099SYunsheng Lin hclgevf_flush_link_update(hdev); 21868cdb992fSJian Shen } 21878cdb992fSJian Shen } 21888cdb992fSJian Shen 2189e2cb1decSSalil Mehta static int hclgevf_ae_start(struct hnae3_handle *handle) 2190e2cb1decSSalil Mehta { 2191e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2192e2cb1decSSalil Mehta 2193ed7bedd2SGuangbin Huang clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 219401305e16SGuangbin Huang clear_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state); 2195ed7bedd2SGuangbin Huang 21964afc310cSJie Wang hclge_comm_reset_tqp_stats(handle); 2197e2cb1decSSalil Mehta 2198e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 2199e2cb1decSSalil Mehta 22009194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 22019194d18bSliuzhongzhu 2202e2cb1decSSalil Mehta return 0; 2203e2cb1decSSalil Mehta } 2204e2cb1decSSalil Mehta 2205e2cb1decSSalil Mehta static void hclgevf_ae_stop(struct hnae3_handle *handle) 2206e2cb1decSSalil Mehta { 2207e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2208e2cb1decSSalil Mehta 22092f7e4896SFuyun Liang set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 22102f7e4896SFuyun Liang 2211146e92c1SHuazhong Tan if (hdev->reset_type != HNAE3_VF_RESET) 22128fa86551SYufeng Mo hclgevf_reset_tqp(handle); 221339cfbc9cSHuazhong Tan 22144afc310cSJie Wang hclge_comm_reset_tqp_stats(handle); 22158cc6c1f7SFuyun Liang hclgevf_update_link_status(hdev, 0); 2216e2cb1decSSalil Mehta } 2217e2cb1decSSalil Mehta 2218a6d818e3SYunsheng Lin static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2219a6d818e3SYunsheng Lin { 2220d3410018SYufeng Mo #define HCLGEVF_STATE_ALIVE 1 2221d3410018SYufeng Mo #define HCLGEVF_STATE_NOT_ALIVE 0 2222a6d818e3SYunsheng Lin 2223d3410018SYufeng Mo struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2224d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 2225d3410018SYufeng Mo 2226d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_ALIVE, 0); 2227d3410018SYufeng Mo send_msg.data[0] = alive ? HCLGEVF_STATE_ALIVE : 2228d3410018SYufeng Mo HCLGEVF_STATE_NOT_ALIVE; 2229d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2230a6d818e3SYunsheng Lin } 2231a6d818e3SYunsheng Lin 2232a6d818e3SYunsheng Lin static int hclgevf_client_start(struct hnae3_handle *handle) 2233a6d818e3SYunsheng Lin { 2234f621df96SQinglang Miao return hclgevf_set_alive(handle, true); 2235a6d818e3SYunsheng Lin } 2236a6d818e3SYunsheng Lin 2237a6d818e3SYunsheng Lin static void hclgevf_client_stop(struct hnae3_handle *handle) 2238a6d818e3SYunsheng Lin { 2239a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2240a6d818e3SYunsheng Lin int ret; 2241a6d818e3SYunsheng Lin 2242a6d818e3SYunsheng Lin ret = hclgevf_set_alive(handle, false); 2243a6d818e3SYunsheng Lin if (ret) 2244a6d818e3SYunsheng Lin dev_warn(&hdev->pdev->dev, 2245a6d818e3SYunsheng Lin "%s failed %d\n", __func__, ret); 2246a6d818e3SYunsheng Lin } 2247a6d818e3SYunsheng Lin 2248e2cb1decSSalil Mehta static void hclgevf_state_init(struct hclgevf_dev *hdev) 2249e2cb1decSSalil Mehta { 2250e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2251e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2252d5432455SGuojia Liao clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 2253e2cb1decSSalil Mehta 2254b3c3fe8eSYunsheng Lin INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task); 225535a1e503SSalil Mehta 2256e2cb1decSSalil Mehta mutex_init(&hdev->mbx_resp.mbx_mutex); 2257f28368bbSHuazhong Tan sema_init(&hdev->reset_sem, 1); 2258e2cb1decSSalil Mehta 2259ee4bcd3bSJian Shen spin_lock_init(&hdev->mac_table.mac_list_lock); 2260ee4bcd3bSJian Shen INIT_LIST_HEAD(&hdev->mac_table.uc_mac_list); 2261ee4bcd3bSJian Shen INIT_LIST_HEAD(&hdev->mac_table.mc_mac_list); 2262ee4bcd3bSJian Shen 2263e2cb1decSSalil Mehta /* bring the device down */ 2264e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2265e2cb1decSSalil Mehta } 2266e2cb1decSSalil Mehta 2267e2cb1decSSalil Mehta static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2268e2cb1decSSalil Mehta { 2269e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2270acfc3d55SHuazhong Tan set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2271e2cb1decSSalil Mehta 2272b3c3fe8eSYunsheng Lin if (hdev->service_task.work.func) 2273b3c3fe8eSYunsheng Lin cancel_delayed_work_sync(&hdev->service_task); 2274e2cb1decSSalil Mehta 2275e2cb1decSSalil Mehta mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2276e2cb1decSSalil Mehta } 2277e2cb1decSSalil Mehta 2278e2cb1decSSalil Mehta static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2279e2cb1decSSalil Mehta { 2280e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2281e2cb1decSSalil Mehta int vectors; 2282e2cb1decSSalil Mehta int i; 2283e2cb1decSSalil Mehta 2284580a05f9SYonglong Liu if (hnae3_dev_roce_supported(hdev)) 228507acf909SJian Shen vectors = pci_alloc_irq_vectors(pdev, 228607acf909SJian Shen hdev->roce_base_msix_offset + 1, 228707acf909SJian Shen hdev->num_msi, 228807acf909SJian Shen PCI_IRQ_MSIX); 228907acf909SJian Shen else 2290580a05f9SYonglong Liu vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2291580a05f9SYonglong Liu hdev->num_msi, 2292e2cb1decSSalil Mehta PCI_IRQ_MSI | PCI_IRQ_MSIX); 229307acf909SJian Shen 2294e2cb1decSSalil Mehta if (vectors < 0) { 2295e2cb1decSSalil Mehta dev_err(&pdev->dev, 2296e2cb1decSSalil Mehta "failed(%d) to allocate MSI/MSI-X vectors\n", 2297e2cb1decSSalil Mehta vectors); 2298e2cb1decSSalil Mehta return vectors; 2299e2cb1decSSalil Mehta } 2300e2cb1decSSalil Mehta if (vectors < hdev->num_msi) 2301e2cb1decSSalil Mehta dev_warn(&hdev->pdev->dev, 2302adcf738bSGuojia Liao "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2303e2cb1decSSalil Mehta hdev->num_msi, vectors); 2304e2cb1decSSalil Mehta 2305e2cb1decSSalil Mehta hdev->num_msi = vectors; 2306e2cb1decSSalil Mehta hdev->num_msi_left = vectors; 2307580a05f9SYonglong Liu 2308e2cb1decSSalil Mehta hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2309e2cb1decSSalil Mehta sizeof(u16), GFP_KERNEL); 2310e2cb1decSSalil Mehta if (!hdev->vector_status) { 2311e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2312e2cb1decSSalil Mehta return -ENOMEM; 2313e2cb1decSSalil Mehta } 2314e2cb1decSSalil Mehta 2315e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 2316e2cb1decSSalil Mehta hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2317e2cb1decSSalil Mehta 2318e2cb1decSSalil Mehta hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2319e2cb1decSSalil Mehta sizeof(int), GFP_KERNEL); 2320e2cb1decSSalil Mehta if (!hdev->vector_irq) { 2321862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2322e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2323e2cb1decSSalil Mehta return -ENOMEM; 2324e2cb1decSSalil Mehta } 2325e2cb1decSSalil Mehta 2326e2cb1decSSalil Mehta return 0; 2327e2cb1decSSalil Mehta } 2328e2cb1decSSalil Mehta 2329e2cb1decSSalil Mehta static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2330e2cb1decSSalil Mehta { 2331e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2332e2cb1decSSalil Mehta 2333862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2334862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_irq); 2335e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2336e2cb1decSSalil Mehta } 2337e2cb1decSSalil Mehta 2338e2cb1decSSalil Mehta static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2339e2cb1decSSalil Mehta { 2340cdd332acSGuojia Liao int ret; 2341e2cb1decSSalil Mehta 2342e2cb1decSSalil Mehta hclgevf_get_misc_vector(hdev); 2343e2cb1decSSalil Mehta 2344f97c4d82SYonglong Liu snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 2345f97c4d82SYonglong Liu HCLGEVF_NAME, pci_name(hdev->pdev)); 2346e2cb1decSSalil Mehta ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2347f97c4d82SYonglong Liu 0, hdev->misc_vector.name, hdev); 2348e2cb1decSSalil Mehta if (ret) { 2349e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2350e2cb1decSSalil Mehta hdev->misc_vector.vector_irq); 2351e2cb1decSSalil Mehta return ret; 2352e2cb1decSSalil Mehta } 2353e2cb1decSSalil Mehta 23541819e409SXi Wang hclgevf_clear_event_cause(hdev, 0); 23551819e409SXi Wang 2356e2cb1decSSalil Mehta /* enable misc. vector(vector 0) */ 2357e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2358e2cb1decSSalil Mehta 2359e2cb1decSSalil Mehta return ret; 2360e2cb1decSSalil Mehta } 2361e2cb1decSSalil Mehta 2362e2cb1decSSalil Mehta static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2363e2cb1decSSalil Mehta { 2364e2cb1decSSalil Mehta /* disable misc vector(vector 0) */ 2365e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 23661819e409SXi Wang synchronize_irq(hdev->misc_vector.vector_irq); 2367e2cb1decSSalil Mehta free_irq(hdev->misc_vector.vector_irq, hdev); 2368e2cb1decSSalil Mehta hclgevf_free_vector(hdev, 0); 2369e2cb1decSSalil Mehta } 2370e2cb1decSSalil Mehta 2371bb87be87SYonglong Liu static void hclgevf_info_show(struct hclgevf_dev *hdev) 2372bb87be87SYonglong Liu { 2373bb87be87SYonglong Liu struct device *dev = &hdev->pdev->dev; 2374bb87be87SYonglong Liu 2375bb87be87SYonglong Liu dev_info(dev, "VF info begin:\n"); 2376bb87be87SYonglong Liu 2377adcf738bSGuojia Liao dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 2378adcf738bSGuojia Liao dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 2379adcf738bSGuojia Liao dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 2380adcf738bSGuojia Liao dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 2381adcf738bSGuojia Liao dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 2382adcf738bSGuojia Liao dev_info(dev, "PF media type of this VF: %u\n", 2383bb87be87SYonglong Liu hdev->hw.mac.media_type); 2384bb87be87SYonglong Liu 2385bb87be87SYonglong Liu dev_info(dev, "VF info end.\n"); 2386bb87be87SYonglong Liu } 2387bb87be87SYonglong Liu 23881db58f86SHuazhong Tan static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 23891db58f86SHuazhong Tan struct hnae3_client *client) 23901db58f86SHuazhong Tan { 23911db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 23924cd5beaaSGuangbin Huang int rst_cnt = hdev->rst_stats.rst_cnt; 23931db58f86SHuazhong Tan int ret; 23941db58f86SHuazhong Tan 23951db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->nic); 23961db58f86SHuazhong Tan if (ret) 23971db58f86SHuazhong Tan return ret; 23981db58f86SHuazhong Tan 23991db58f86SHuazhong Tan set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 24004cd5beaaSGuangbin Huang if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 24014cd5beaaSGuangbin Huang rst_cnt != hdev->rst_stats.rst_cnt) { 24024cd5beaaSGuangbin Huang clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 24034cd5beaaSGuangbin Huang 24044cd5beaaSGuangbin Huang client->ops->uninit_instance(&hdev->nic, 0); 24054cd5beaaSGuangbin Huang return -EBUSY; 24064cd5beaaSGuangbin Huang } 24074cd5beaaSGuangbin Huang 24081db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 24091db58f86SHuazhong Tan 24101db58f86SHuazhong Tan if (netif_msg_drv(&hdev->nic)) 24111db58f86SHuazhong Tan hclgevf_info_show(hdev); 24121db58f86SHuazhong Tan 24131db58f86SHuazhong Tan return 0; 24141db58f86SHuazhong Tan } 24151db58f86SHuazhong Tan 24161db58f86SHuazhong Tan static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 24171db58f86SHuazhong Tan struct hnae3_client *client) 24181db58f86SHuazhong Tan { 24191db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 24201db58f86SHuazhong Tan int ret; 24211db58f86SHuazhong Tan 24221db58f86SHuazhong Tan if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 24231db58f86SHuazhong Tan !hdev->nic_client) 24241db58f86SHuazhong Tan return 0; 24251db58f86SHuazhong Tan 24261db58f86SHuazhong Tan ret = hclgevf_init_roce_base_info(hdev); 24271db58f86SHuazhong Tan if (ret) 24281db58f86SHuazhong Tan return ret; 24291db58f86SHuazhong Tan 24301db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->roce); 24311db58f86SHuazhong Tan if (ret) 24321db58f86SHuazhong Tan return ret; 24331db58f86SHuazhong Tan 2434fe735c84SHuazhong Tan set_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 24351db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 24361db58f86SHuazhong Tan 24371db58f86SHuazhong Tan return 0; 24381db58f86SHuazhong Tan } 24391db58f86SHuazhong Tan 2440e718a93fSPeng Li static int hclgevf_init_client_instance(struct hnae3_client *client, 2441e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2442e2cb1decSSalil Mehta { 2443e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2444e2cb1decSSalil Mehta int ret; 2445e2cb1decSSalil Mehta 2446e2cb1decSSalil Mehta switch (client->type) { 2447e2cb1decSSalil Mehta case HNAE3_CLIENT_KNIC: 2448e2cb1decSSalil Mehta hdev->nic_client = client; 2449e2cb1decSSalil Mehta hdev->nic.client = client; 2450e2cb1decSSalil Mehta 24511db58f86SHuazhong Tan ret = hclgevf_init_nic_client_instance(ae_dev, client); 2452e2cb1decSSalil Mehta if (ret) 245349dd8054SJian Shen goto clear_nic; 2454e2cb1decSSalil Mehta 24551db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, 24561db58f86SHuazhong Tan hdev->roce_client); 2457e2cb1decSSalil Mehta if (ret) 245849dd8054SJian Shen goto clear_roce; 2459d9f28fc2SJian Shen 2460e2cb1decSSalil Mehta break; 2461e2cb1decSSalil Mehta case HNAE3_CLIENT_ROCE: 2462544a7bcdSLijun Ou if (hnae3_dev_roce_supported(hdev)) { 2463e2cb1decSSalil Mehta hdev->roce_client = client; 2464e2cb1decSSalil Mehta hdev->roce.client = client; 2465544a7bcdSLijun Ou } 2466e2cb1decSSalil Mehta 24671db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, client); 2468e2cb1decSSalil Mehta if (ret) 246949dd8054SJian Shen goto clear_roce; 2470e2cb1decSSalil Mehta 2471fa7a4bd5SJian Shen break; 2472fa7a4bd5SJian Shen default: 2473fa7a4bd5SJian Shen return -EINVAL; 2474e2cb1decSSalil Mehta } 2475e2cb1decSSalil Mehta 2476e2cb1decSSalil Mehta return 0; 247749dd8054SJian Shen 247849dd8054SJian Shen clear_nic: 247949dd8054SJian Shen hdev->nic_client = NULL; 248049dd8054SJian Shen hdev->nic.client = NULL; 248149dd8054SJian Shen return ret; 248249dd8054SJian Shen clear_roce: 248349dd8054SJian Shen hdev->roce_client = NULL; 248449dd8054SJian Shen hdev->roce.client = NULL; 248549dd8054SJian Shen return ret; 2486e2cb1decSSalil Mehta } 2487e2cb1decSSalil Mehta 2488e718a93fSPeng Li static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2489e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2490e2cb1decSSalil Mehta { 2491e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2492e718a93fSPeng Li 2493e2cb1decSSalil Mehta /* un-init roce, if it exists */ 249449dd8054SJian Shen if (hdev->roce_client) { 2495e140c798SYufeng Mo while (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 2496e140c798SYufeng Mo msleep(HCLGEVF_WAIT_RESET_DONE); 2497fe735c84SHuazhong Tan clear_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 2498e140c798SYufeng Mo 2499e2cb1decSSalil Mehta hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 250049dd8054SJian Shen hdev->roce_client = NULL; 250149dd8054SJian Shen hdev->roce.client = NULL; 250249dd8054SJian Shen } 2503e2cb1decSSalil Mehta 2504e2cb1decSSalil Mehta /* un-init nic/unic, if this was not called by roce client */ 250549dd8054SJian Shen if (client->ops->uninit_instance && hdev->nic_client && 250649dd8054SJian Shen client->type != HNAE3_CLIENT_ROCE) { 2507e140c798SYufeng Mo while (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 2508e140c798SYufeng Mo msleep(HCLGEVF_WAIT_RESET_DONE); 250925d1817cSHuazhong Tan clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 251025d1817cSHuazhong Tan 2511e2cb1decSSalil Mehta client->ops->uninit_instance(&hdev->nic, 0); 251249dd8054SJian Shen hdev->nic_client = NULL; 251349dd8054SJian Shen hdev->nic.client = NULL; 251449dd8054SJian Shen } 2515e2cb1decSSalil Mehta } 2516e2cb1decSSalil Mehta 251730ae7f8aSHuazhong Tan static int hclgevf_dev_mem_map(struct hclgevf_dev *hdev) 251830ae7f8aSHuazhong Tan { 251930ae7f8aSHuazhong Tan struct pci_dev *pdev = hdev->pdev; 252030ae7f8aSHuazhong Tan struct hclgevf_hw *hw = &hdev->hw; 252130ae7f8aSHuazhong Tan 252230ae7f8aSHuazhong Tan /* for device does not have device memory, return directly */ 252330ae7f8aSHuazhong Tan if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGEVF_MEM_BAR))) 252430ae7f8aSHuazhong Tan return 0; 252530ae7f8aSHuazhong Tan 2526076bb537SJie Wang hw->hw.mem_base = 2527076bb537SJie Wang devm_ioremap_wc(&pdev->dev, 2528076bb537SJie Wang pci_resource_start(pdev, HCLGEVF_MEM_BAR), 252930ae7f8aSHuazhong Tan pci_resource_len(pdev, HCLGEVF_MEM_BAR)); 2530076bb537SJie Wang if (!hw->hw.mem_base) { 2531be419fcaSColin Ian King dev_err(&pdev->dev, "failed to map device memory\n"); 253230ae7f8aSHuazhong Tan return -EFAULT; 253330ae7f8aSHuazhong Tan } 253430ae7f8aSHuazhong Tan 253530ae7f8aSHuazhong Tan return 0; 253630ae7f8aSHuazhong Tan } 253730ae7f8aSHuazhong Tan 2538e2cb1decSSalil Mehta static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2539e2cb1decSSalil Mehta { 2540e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2541e2cb1decSSalil Mehta struct hclgevf_hw *hw; 2542e2cb1decSSalil Mehta int ret; 2543e2cb1decSSalil Mehta 2544e2cb1decSSalil Mehta ret = pci_enable_device(pdev); 2545e2cb1decSSalil Mehta if (ret) { 2546e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed to enable PCI device\n"); 25473e249d3bSFuyun Liang return ret; 2548e2cb1decSSalil Mehta } 2549e2cb1decSSalil Mehta 2550e2cb1decSSalil Mehta ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2551e2cb1decSSalil Mehta if (ret) { 2552e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2553e2cb1decSSalil Mehta goto err_disable_device; 2554e2cb1decSSalil Mehta } 2555e2cb1decSSalil Mehta 2556e2cb1decSSalil Mehta ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2557e2cb1decSSalil Mehta if (ret) { 2558e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2559e2cb1decSSalil Mehta goto err_disable_device; 2560e2cb1decSSalil Mehta } 2561e2cb1decSSalil Mehta 2562e2cb1decSSalil Mehta pci_set_master(pdev); 2563e2cb1decSSalil Mehta hw = &hdev->hw; 2564076bb537SJie Wang hw->hw.io_base = pci_iomap(pdev, 2, 0); 2565076bb537SJie Wang if (!hw->hw.io_base) { 2566e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't map configuration register space\n"); 2567e2cb1decSSalil Mehta ret = -ENOMEM; 2568fc3e07e8SCai Huoqing goto err_release_regions; 2569e2cb1decSSalil Mehta } 2570e2cb1decSSalil Mehta 257130ae7f8aSHuazhong Tan ret = hclgevf_dev_mem_map(hdev); 257230ae7f8aSHuazhong Tan if (ret) 257330ae7f8aSHuazhong Tan goto err_unmap_io_base; 257430ae7f8aSHuazhong Tan 2575e2cb1decSSalil Mehta return 0; 2576e2cb1decSSalil Mehta 257730ae7f8aSHuazhong Tan err_unmap_io_base: 2578076bb537SJie Wang pci_iounmap(pdev, hdev->hw.hw.io_base); 2579fc3e07e8SCai Huoqing err_release_regions: 2580e2cb1decSSalil Mehta pci_release_regions(pdev); 2581e2cb1decSSalil Mehta err_disable_device: 2582e2cb1decSSalil Mehta pci_disable_device(pdev); 25833e249d3bSFuyun Liang 2584e2cb1decSSalil Mehta return ret; 2585e2cb1decSSalil Mehta } 2586e2cb1decSSalil Mehta 2587e2cb1decSSalil Mehta static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2588e2cb1decSSalil Mehta { 2589e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2590e2cb1decSSalil Mehta 2591076bb537SJie Wang if (hdev->hw.hw.mem_base) 2592076bb537SJie Wang devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base); 259330ae7f8aSHuazhong Tan 2594076bb537SJie Wang pci_iounmap(pdev, hdev->hw.hw.io_base); 2595e2cb1decSSalil Mehta pci_release_regions(pdev); 2596e2cb1decSSalil Mehta pci_disable_device(pdev); 2597e2cb1decSSalil Mehta } 2598e2cb1decSSalil Mehta 259907acf909SJian Shen static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 260007acf909SJian Shen { 260107acf909SJian Shen struct hclgevf_query_res_cmd *req; 26026befad60SJie Wang struct hclge_desc desc; 260307acf909SJian Shen int ret; 260407acf909SJian Shen 260543710bfeSJie Wang hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RSRC, true); 260607acf909SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 260707acf909SJian Shen if (ret) { 260807acf909SJian Shen dev_err(&hdev->pdev->dev, 260907acf909SJian Shen "query vf resource failed, ret = %d.\n", ret); 261007acf909SJian Shen return ret; 261107acf909SJian Shen } 261207acf909SJian Shen 261307acf909SJian Shen req = (struct hclgevf_query_res_cmd *)desc.data; 261407acf909SJian Shen 2615580a05f9SYonglong Liu if (hnae3_dev_roce_supported(hdev)) { 261607acf909SJian Shen hdev->roce_base_msix_offset = 261760df7e91SHuazhong Tan hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee), 261807acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_M, 261907acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_S); 262007acf909SJian Shen hdev->num_roce_msix = 262160df7e91SHuazhong Tan hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 262207acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 262307acf909SJian Shen 2624580a05f9SYonglong Liu /* nic's msix numbers is always equals to the roce's. */ 2625580a05f9SYonglong Liu hdev->num_nic_msix = hdev->num_roce_msix; 2626580a05f9SYonglong Liu 262707acf909SJian Shen /* VF should have NIC vectors and Roce vectors, NIC vectors 262807acf909SJian Shen * are queued before Roce vectors. The offset is fixed to 64. 262907acf909SJian Shen */ 263007acf909SJian Shen hdev->num_msi = hdev->num_roce_msix + 263107acf909SJian Shen hdev->roce_base_msix_offset; 263207acf909SJian Shen } else { 263307acf909SJian Shen hdev->num_msi = 263460df7e91SHuazhong Tan hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 263507acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2636580a05f9SYonglong Liu 2637580a05f9SYonglong Liu hdev->num_nic_msix = hdev->num_msi; 2638580a05f9SYonglong Liu } 2639580a05f9SYonglong Liu 2640580a05f9SYonglong Liu if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) { 2641580a05f9SYonglong Liu dev_err(&hdev->pdev->dev, 2642580a05f9SYonglong Liu "Just %u msi resources, not enough for vf(min:2).\n", 2643580a05f9SYonglong Liu hdev->num_nic_msix); 2644580a05f9SYonglong Liu return -EINVAL; 264507acf909SJian Shen } 264607acf909SJian Shen 264707acf909SJian Shen return 0; 264807acf909SJian Shen } 264907acf909SJian Shen 2650af2aedc5SGuangbin Huang static void hclgevf_set_default_dev_specs(struct hclgevf_dev *hdev) 2651af2aedc5SGuangbin Huang { 2652af2aedc5SGuangbin Huang #define HCLGEVF_MAX_NON_TSO_BD_NUM 8U 2653af2aedc5SGuangbin Huang 2654af2aedc5SGuangbin Huang struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2655af2aedc5SGuangbin Huang 2656af2aedc5SGuangbin Huang ae_dev->dev_specs.max_non_tso_bd_num = 2657af2aedc5SGuangbin Huang HCLGEVF_MAX_NON_TSO_BD_NUM; 2658af2aedc5SGuangbin Huang ae_dev->dev_specs.rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 26597428d6c9SJie Wang ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 2660ab16b49cSHuazhong Tan ae_dev->dev_specs.max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 2661e070c8b9SYufeng Mo ae_dev->dev_specs.max_frm_size = HCLGEVF_MAC_MAX_FRAME; 2662af2aedc5SGuangbin Huang } 2663af2aedc5SGuangbin Huang 2664af2aedc5SGuangbin Huang static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev, 26656befad60SJie Wang struct hclge_desc *desc) 2666af2aedc5SGuangbin Huang { 2667af2aedc5SGuangbin Huang struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2668af2aedc5SGuangbin Huang struct hclgevf_dev_specs_0_cmd *req0; 2669ab16b49cSHuazhong Tan struct hclgevf_dev_specs_1_cmd *req1; 2670af2aedc5SGuangbin Huang 2671af2aedc5SGuangbin Huang req0 = (struct hclgevf_dev_specs_0_cmd *)desc[0].data; 2672ab16b49cSHuazhong Tan req1 = (struct hclgevf_dev_specs_1_cmd *)desc[1].data; 2673af2aedc5SGuangbin Huang 2674af2aedc5SGuangbin Huang ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 2675af2aedc5SGuangbin Huang ae_dev->dev_specs.rss_ind_tbl_size = 2676af2aedc5SGuangbin Huang le16_to_cpu(req0->rss_ind_tbl_size); 267791bfae25SHuazhong Tan ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 2678af2aedc5SGuangbin Huang ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 2679ab16b49cSHuazhong Tan ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 2680e070c8b9SYufeng Mo ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 2681af2aedc5SGuangbin Huang } 2682af2aedc5SGuangbin Huang 268313297028SGuangbin Huang static void hclgevf_check_dev_specs(struct hclgevf_dev *hdev) 268413297028SGuangbin Huang { 268513297028SGuangbin Huang struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 268613297028SGuangbin Huang 268713297028SGuangbin Huang if (!dev_specs->max_non_tso_bd_num) 268813297028SGuangbin Huang dev_specs->max_non_tso_bd_num = HCLGEVF_MAX_NON_TSO_BD_NUM; 268913297028SGuangbin Huang if (!dev_specs->rss_ind_tbl_size) 269013297028SGuangbin Huang dev_specs->rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 269113297028SGuangbin Huang if (!dev_specs->rss_key_size) 26927428d6c9SJie Wang dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 2693ab16b49cSHuazhong Tan if (!dev_specs->max_int_gl) 2694ab16b49cSHuazhong Tan dev_specs->max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 2695e070c8b9SYufeng Mo if (!dev_specs->max_frm_size) 2696e070c8b9SYufeng Mo dev_specs->max_frm_size = HCLGEVF_MAC_MAX_FRAME; 269713297028SGuangbin Huang } 269813297028SGuangbin Huang 2699af2aedc5SGuangbin Huang static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev) 2700af2aedc5SGuangbin Huang { 27016befad60SJie Wang struct hclge_desc desc[HCLGEVF_QUERY_DEV_SPECS_BD_NUM]; 2702af2aedc5SGuangbin Huang int ret; 2703af2aedc5SGuangbin Huang int i; 2704af2aedc5SGuangbin Huang 2705af2aedc5SGuangbin Huang /* set default specifications as devices lower than version V3 do not 2706af2aedc5SGuangbin Huang * support querying specifications from firmware. 2707af2aedc5SGuangbin Huang */ 2708af2aedc5SGuangbin Huang if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 2709af2aedc5SGuangbin Huang hclgevf_set_default_dev_specs(hdev); 2710af2aedc5SGuangbin Huang return 0; 2711af2aedc5SGuangbin Huang } 2712af2aedc5SGuangbin Huang 2713af2aedc5SGuangbin Huang for (i = 0; i < HCLGEVF_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 2714af2aedc5SGuangbin Huang hclgevf_cmd_setup_basic_desc(&desc[i], 271543710bfeSJie Wang HCLGE_OPC_QUERY_DEV_SPECS, true); 2716cb413bfaSJie Wang desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2717af2aedc5SGuangbin Huang } 271843710bfeSJie Wang hclgevf_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true); 2719af2aedc5SGuangbin Huang 2720af2aedc5SGuangbin Huang ret = hclgevf_cmd_send(&hdev->hw, desc, HCLGEVF_QUERY_DEV_SPECS_BD_NUM); 2721af2aedc5SGuangbin Huang if (ret) 2722af2aedc5SGuangbin Huang return ret; 2723af2aedc5SGuangbin Huang 2724af2aedc5SGuangbin Huang hclgevf_parse_dev_specs(hdev, desc); 272513297028SGuangbin Huang hclgevf_check_dev_specs(hdev); 2726af2aedc5SGuangbin Huang 2727af2aedc5SGuangbin Huang return 0; 2728af2aedc5SGuangbin Huang } 2729af2aedc5SGuangbin Huang 2730862d969aSHuazhong Tan static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2731862d969aSHuazhong Tan { 2732862d969aSHuazhong Tan struct pci_dev *pdev = hdev->pdev; 2733862d969aSHuazhong Tan int ret = 0; 2734862d969aSHuazhong Tan 273509e6b30eSJie Wang if ((hdev->reset_type == HNAE3_VF_FULL_RESET || 273609e6b30eSJie Wang hdev->reset_type == HNAE3_FLR_RESET) && 2737862d969aSHuazhong Tan test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2738862d969aSHuazhong Tan hclgevf_misc_irq_uninit(hdev); 2739862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2740862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2741862d969aSHuazhong Tan } 2742862d969aSHuazhong Tan 2743862d969aSHuazhong Tan if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2744862d969aSHuazhong Tan pci_set_master(pdev); 2745862d969aSHuazhong Tan ret = hclgevf_init_msi(hdev); 2746862d969aSHuazhong Tan if (ret) { 2747862d969aSHuazhong Tan dev_err(&pdev->dev, 2748862d969aSHuazhong Tan "failed(%d) to init MSI/MSI-X\n", ret); 2749862d969aSHuazhong Tan return ret; 2750862d969aSHuazhong Tan } 2751862d969aSHuazhong Tan 2752862d969aSHuazhong Tan ret = hclgevf_misc_irq_init(hdev); 2753862d969aSHuazhong Tan if (ret) { 2754862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2755862d969aSHuazhong Tan dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2756862d969aSHuazhong Tan ret); 2757862d969aSHuazhong Tan return ret; 2758862d969aSHuazhong Tan } 2759862d969aSHuazhong Tan 2760862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2761862d969aSHuazhong Tan } 2762862d969aSHuazhong Tan 2763862d969aSHuazhong Tan return ret; 2764862d969aSHuazhong Tan } 2765862d969aSHuazhong Tan 2766039ba863SJian Shen static int hclgevf_clear_vport_list(struct hclgevf_dev *hdev) 2767039ba863SJian Shen { 2768039ba863SJian Shen struct hclge_vf_to_pf_msg send_msg; 2769039ba863SJian Shen 2770039ba863SJian Shen hclgevf_build_send_msg(&send_msg, HCLGE_MBX_HANDLE_VF_TBL, 2771039ba863SJian Shen HCLGE_MBX_VPORT_LIST_CLEAR); 2772039ba863SJian Shen return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2773039ba863SJian Shen } 2774039ba863SJian Shen 277579664077SHuazhong Tan static void hclgevf_init_rxd_adv_layout(struct hclgevf_dev *hdev) 277679664077SHuazhong Tan { 277779664077SHuazhong Tan if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 277879664077SHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 1); 277979664077SHuazhong Tan } 278079664077SHuazhong Tan 278179664077SHuazhong Tan static void hclgevf_uninit_rxd_adv_layout(struct hclgevf_dev *hdev) 278279664077SHuazhong Tan { 278379664077SHuazhong Tan if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 278479664077SHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 0); 278579664077SHuazhong Tan } 278679664077SHuazhong Tan 27879c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2788e2cb1decSSalil Mehta { 27897a01c897SSalil Mehta struct pci_dev *pdev = hdev->pdev; 2790e2cb1decSSalil Mehta int ret; 2791e2cb1decSSalil Mehta 2792862d969aSHuazhong Tan ret = hclgevf_pci_reset(hdev); 2793862d969aSHuazhong Tan if (ret) { 2794862d969aSHuazhong Tan dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2795862d969aSHuazhong Tan return ret; 2796862d969aSHuazhong Tan } 2797862d969aSHuazhong Tan 2798cb413bfaSJie Wang hclgevf_arq_init(hdev); 2799cb413bfaSJie Wang ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, 2800cb413bfaSJie Wang &hdev->fw_version, false, 2801cb413bfaSJie Wang hdev->reset_pending); 28029c6f7085SHuazhong Tan if (ret) { 28039c6f7085SHuazhong Tan dev_err(&pdev->dev, "cmd failed %d\n", ret); 28049c6f7085SHuazhong Tan return ret; 28057a01c897SSalil Mehta } 2806e2cb1decSSalil Mehta 28079c6f7085SHuazhong Tan ret = hclgevf_rss_init_hw(hdev); 28089c6f7085SHuazhong Tan if (ret) { 28099c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 28109c6f7085SHuazhong Tan "failed(%d) to initialize RSS\n", ret); 28119c6f7085SHuazhong Tan return ret; 28129c6f7085SHuazhong Tan } 28139c6f7085SHuazhong Tan 28143462207dSYufeng Mo ret = hclgevf_config_gro(hdev); 2815b26a6feaSPeng Li if (ret) 2816b26a6feaSPeng Li return ret; 2817b26a6feaSPeng Li 28189c6f7085SHuazhong Tan ret = hclgevf_init_vlan_config(hdev); 28199c6f7085SHuazhong Tan if (ret) { 28209c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 28219c6f7085SHuazhong Tan "failed(%d) to initialize VLAN config\n", ret); 28229c6f7085SHuazhong Tan return ret; 28239c6f7085SHuazhong Tan } 28249c6f7085SHuazhong Tan 2825190cd8a7SJian Shen /* get current port based vlan state from PF */ 2826190cd8a7SJian Shen ret = hclgevf_get_port_base_vlan_filter_state(hdev); 2827190cd8a7SJian Shen if (ret) 2828190cd8a7SJian Shen return ret; 2829190cd8a7SJian Shen 2830c631c696SJian Shen set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 2831c631c696SJian Shen 283279664077SHuazhong Tan hclgevf_init_rxd_adv_layout(hdev); 283379664077SHuazhong Tan 28349c6f7085SHuazhong Tan dev_info(&hdev->pdev->dev, "Reset done\n"); 28359c6f7085SHuazhong Tan 28369c6f7085SHuazhong Tan return 0; 28379c6f7085SHuazhong Tan } 28389c6f7085SHuazhong Tan 28399c6f7085SHuazhong Tan static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 28409c6f7085SHuazhong Tan { 28419c6f7085SHuazhong Tan struct pci_dev *pdev = hdev->pdev; 28429c6f7085SHuazhong Tan int ret; 28439c6f7085SHuazhong Tan 2844e2cb1decSSalil Mehta ret = hclgevf_pci_init(hdev); 284560df7e91SHuazhong Tan if (ret) 2846e2cb1decSSalil Mehta return ret; 2847e2cb1decSSalil Mehta 2848cd624299SYufeng Mo ret = hclgevf_devlink_init(hdev); 2849cd624299SYufeng Mo if (ret) 2850cd624299SYufeng Mo goto err_devlink_init; 2851cd624299SYufeng Mo 2852cb413bfaSJie Wang ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw); 285360df7e91SHuazhong Tan if (ret) 28548b0195a3SHuazhong Tan goto err_cmd_queue_init; 28558b0195a3SHuazhong Tan 2856cb413bfaSJie Wang hclgevf_arq_init(hdev); 2857cb413bfaSJie Wang ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, 2858cb413bfaSJie Wang &hdev->fw_version, false, 2859cb413bfaSJie Wang hdev->reset_pending); 2860eddf0462SYunsheng Lin if (ret) 2861eddf0462SYunsheng Lin goto err_cmd_init; 2862eddf0462SYunsheng Lin 286307acf909SJian Shen /* Get vf resource */ 286407acf909SJian Shen ret = hclgevf_query_vf_resource(hdev); 286560df7e91SHuazhong Tan if (ret) 28668b0195a3SHuazhong Tan goto err_cmd_init; 286707acf909SJian Shen 2868af2aedc5SGuangbin Huang ret = hclgevf_query_dev_specs(hdev); 2869af2aedc5SGuangbin Huang if (ret) { 2870af2aedc5SGuangbin Huang dev_err(&pdev->dev, 2871af2aedc5SGuangbin Huang "failed to query dev specifications, ret = %d\n", ret); 2872af2aedc5SGuangbin Huang goto err_cmd_init; 2873af2aedc5SGuangbin Huang } 2874af2aedc5SGuangbin Huang 287507acf909SJian Shen ret = hclgevf_init_msi(hdev); 287607acf909SJian Shen if (ret) { 287707acf909SJian Shen dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 28788b0195a3SHuazhong Tan goto err_cmd_init; 287907acf909SJian Shen } 288007acf909SJian Shen 288107acf909SJian Shen hclgevf_state_init(hdev); 2882dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 2883afb6afdbSHuazhong Tan hdev->reset_type = HNAE3_NONE_RESET; 288407acf909SJian Shen 2885e2cb1decSSalil Mehta ret = hclgevf_misc_irq_init(hdev); 288660df7e91SHuazhong Tan if (ret) 2887e2cb1decSSalil Mehta goto err_misc_irq_init; 2888e2cb1decSSalil Mehta 2889862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2890862d969aSHuazhong Tan 2891e2cb1decSSalil Mehta ret = hclgevf_configure(hdev); 2892e2cb1decSSalil Mehta if (ret) { 2893e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2894e2cb1decSSalil Mehta goto err_config; 2895e2cb1decSSalil Mehta } 2896e2cb1decSSalil Mehta 2897e2cb1decSSalil Mehta ret = hclgevf_alloc_tqps(hdev); 2898e2cb1decSSalil Mehta if (ret) { 2899e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2900e2cb1decSSalil Mehta goto err_config; 2901e2cb1decSSalil Mehta } 2902e2cb1decSSalil Mehta 2903e2cb1decSSalil Mehta ret = hclgevf_set_handle_info(hdev); 290460df7e91SHuazhong Tan if (ret) 2905e2cb1decSSalil Mehta goto err_config; 2906e2cb1decSSalil Mehta 29073462207dSYufeng Mo ret = hclgevf_config_gro(hdev); 2908b26a6feaSPeng Li if (ret) 2909b26a6feaSPeng Li goto err_config; 2910b26a6feaSPeng Li 2911e2cb1decSSalil Mehta /* Initialize RSS for this VF */ 291293969dc1SJie Wang ret = hclge_comm_rss_init_cfg(&hdev->nic, hdev->ae_dev, 291393969dc1SJie Wang &hdev->rss_cfg); 291487ce161eSGuangbin Huang if (ret) { 291587ce161eSGuangbin Huang dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 291687ce161eSGuangbin Huang goto err_config; 291787ce161eSGuangbin Huang } 291887ce161eSGuangbin Huang 2919e2cb1decSSalil Mehta ret = hclgevf_rss_init_hw(hdev); 2920e2cb1decSSalil Mehta if (ret) { 2921e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2922e2cb1decSSalil Mehta "failed(%d) to initialize RSS\n", ret); 2923e2cb1decSSalil Mehta goto err_config; 2924e2cb1decSSalil Mehta } 2925e2cb1decSSalil Mehta 2926039ba863SJian Shen /* ensure vf tbl list as empty before init */ 2927039ba863SJian Shen ret = hclgevf_clear_vport_list(hdev); 2928039ba863SJian Shen if (ret) { 2929039ba863SJian Shen dev_err(&pdev->dev, 2930039ba863SJian Shen "failed to clear tbl list configuration, ret = %d.\n", 2931039ba863SJian Shen ret); 2932039ba863SJian Shen goto err_config; 2933039ba863SJian Shen } 2934039ba863SJian Shen 2935e2cb1decSSalil Mehta ret = hclgevf_init_vlan_config(hdev); 2936e2cb1decSSalil Mehta if (ret) { 2937e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2938e2cb1decSSalil Mehta "failed(%d) to initialize VLAN config\n", ret); 2939e2cb1decSSalil Mehta goto err_config; 2940e2cb1decSSalil Mehta } 2941e2cb1decSSalil Mehta 294279664077SHuazhong Tan hclgevf_init_rxd_adv_layout(hdev); 294379664077SHuazhong Tan 29440251d196SGuangbin Huang set_bit(HCLGEVF_STATE_SERVICE_INITED, &hdev->state); 29450251d196SGuangbin Huang 29460742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 294708d80a4cSHuazhong Tan dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 294808d80a4cSHuazhong Tan HCLGEVF_DRIVER_NAME); 2949e2cb1decSSalil Mehta 2950ff200099SYunsheng Lin hclgevf_task_schedule(hdev, round_jiffies_relative(HZ)); 2951*fbcad948SJijie Shao timer_setup(&hdev->reset_timer, hclgevf_reset_timer, 0); 2952ff200099SYunsheng Lin 2953e2cb1decSSalil Mehta return 0; 2954e2cb1decSSalil Mehta 2955e2cb1decSSalil Mehta err_config: 2956e2cb1decSSalil Mehta hclgevf_misc_irq_uninit(hdev); 2957e2cb1decSSalil Mehta err_misc_irq_init: 2958e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2959e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 296007acf909SJian Shen err_cmd_init: 29619970308fSJie Wang hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 29628b0195a3SHuazhong Tan err_cmd_queue_init: 2963cd624299SYufeng Mo hclgevf_devlink_uninit(hdev); 2964cd624299SYufeng Mo err_devlink_init: 2965e2cb1decSSalil Mehta hclgevf_pci_uninit(hdev); 2966862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2967e2cb1decSSalil Mehta return ret; 2968e2cb1decSSalil Mehta } 2969e2cb1decSSalil Mehta 29707a01c897SSalil Mehta static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2971e2cb1decSSalil Mehta { 2972d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 2973d3410018SYufeng Mo 2974e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 297579664077SHuazhong Tan hclgevf_uninit_rxd_adv_layout(hdev); 2976862d969aSHuazhong Tan 2977d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_VF_UNINIT, 0); 2978d3410018SYufeng Mo hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 297923b4201dSJian Shen 2980862d969aSHuazhong Tan if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2981eddf0462SYunsheng Lin hclgevf_misc_irq_uninit(hdev); 2982e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 29837a01c897SSalil Mehta } 29847a01c897SSalil Mehta 29859970308fSJie Wang hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 2986cd624299SYufeng Mo hclgevf_devlink_uninit(hdev); 2987e3364c5fSZenghui Yu hclgevf_pci_uninit(hdev); 2988ee4bcd3bSJian Shen hclgevf_uninit_mac_list(hdev); 2989862d969aSHuazhong Tan } 2990862d969aSHuazhong Tan 29917a01c897SSalil Mehta static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 29927a01c897SSalil Mehta { 29937a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 29947a01c897SSalil Mehta int ret; 29957a01c897SSalil Mehta 29967a01c897SSalil Mehta ret = hclgevf_alloc_hdev(ae_dev); 29977a01c897SSalil Mehta if (ret) { 29987a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device allocation failed\n"); 29997a01c897SSalil Mehta return ret; 30007a01c897SSalil Mehta } 30017a01c897SSalil Mehta 30027a01c897SSalil Mehta ret = hclgevf_init_hdev(ae_dev->priv); 3003a6d818e3SYunsheng Lin if (ret) { 30047a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device initialization failed\n"); 30057a01c897SSalil Mehta return ret; 30067a01c897SSalil Mehta } 30077a01c897SSalil Mehta 3008a6d818e3SYunsheng Lin return 0; 3009a6d818e3SYunsheng Lin } 3010a6d818e3SYunsheng Lin 30117a01c897SSalil Mehta static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 30127a01c897SSalil Mehta { 30137a01c897SSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 30147a01c897SSalil Mehta 30157a01c897SSalil Mehta hclgevf_uninit_hdev(hdev); 3016e2cb1decSSalil Mehta ae_dev->priv = NULL; 3017e2cb1decSSalil Mehta } 3018e2cb1decSSalil Mehta 3019849e4607SPeng Li static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 3020849e4607SPeng Li { 3021849e4607SPeng Li struct hnae3_handle *nic = &hdev->nic; 3022849e4607SPeng Li struct hnae3_knic_private_info *kinfo = &nic->kinfo; 3023849e4607SPeng Li 30248be73621SHuazhong Tan return min_t(u32, hdev->rss_size_max, 302535244430SJian Shen hdev->num_tqps / kinfo->tc_info.num_tc); 3026849e4607SPeng Li } 3027849e4607SPeng Li 3028849e4607SPeng Li /** 3029849e4607SPeng Li * hclgevf_get_channels - Get the current channels enabled and max supported. 3030849e4607SPeng Li * @handle: hardware information for network interface 3031849e4607SPeng Li * @ch: ethtool channels structure 3032849e4607SPeng Li * 3033849e4607SPeng Li * We don't support separate tx and rx queues as channels. The other count 3034849e4607SPeng Li * represents how many queues are being used for control. max_combined counts 3035849e4607SPeng Li * how many queue pairs we can support. They may not be mapped 1 to 1 with 3036849e4607SPeng Li * q_vectors since we support a lot more queue pairs than q_vectors. 3037849e4607SPeng Li **/ 3038849e4607SPeng Li static void hclgevf_get_channels(struct hnae3_handle *handle, 3039849e4607SPeng Li struct ethtool_channels *ch) 3040849e4607SPeng Li { 3041849e4607SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3042849e4607SPeng Li 3043849e4607SPeng Li ch->max_combined = hclgevf_get_max_channels(hdev); 3044849e4607SPeng Li ch->other_count = 0; 3045849e4607SPeng Li ch->max_other = 0; 30468be73621SHuazhong Tan ch->combined_count = handle->kinfo.rss_size; 3047849e4607SPeng Li } 3048849e4607SPeng Li 3049cc719218SPeng Li static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 30500d43bf45SHuazhong Tan u16 *alloc_tqps, u16 *max_rss_size) 3051cc719218SPeng Li { 3052cc719218SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3053cc719218SPeng Li 30540d43bf45SHuazhong Tan *alloc_tqps = hdev->num_tqps; 3055cc719218SPeng Li *max_rss_size = hdev->rss_size_max; 3056cc719218SPeng Li } 3057cc719218SPeng Li 30584093d1a2SGuangbin Huang static void hclgevf_update_rss_size(struct hnae3_handle *handle, 30594093d1a2SGuangbin Huang u32 new_tqps_num) 30604093d1a2SGuangbin Huang { 30614093d1a2SGuangbin Huang struct hnae3_knic_private_info *kinfo = &handle->kinfo; 30624093d1a2SGuangbin Huang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 30634093d1a2SGuangbin Huang u16 max_rss_size; 30644093d1a2SGuangbin Huang 30654093d1a2SGuangbin Huang kinfo->req_rss_size = new_tqps_num; 30664093d1a2SGuangbin Huang 30674093d1a2SGuangbin Huang max_rss_size = min_t(u16, hdev->rss_size_max, 306835244430SJian Shen hdev->num_tqps / kinfo->tc_info.num_tc); 30694093d1a2SGuangbin Huang 30704093d1a2SGuangbin Huang /* Use the user's configuration when it is not larger than 30714093d1a2SGuangbin Huang * max_rss_size, otherwise, use the maximum specification value. 30724093d1a2SGuangbin Huang */ 30734093d1a2SGuangbin Huang if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 30744093d1a2SGuangbin Huang kinfo->req_rss_size <= max_rss_size) 30754093d1a2SGuangbin Huang kinfo->rss_size = kinfo->req_rss_size; 30764093d1a2SGuangbin Huang else if (kinfo->rss_size > max_rss_size || 30774093d1a2SGuangbin Huang (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) 30784093d1a2SGuangbin Huang kinfo->rss_size = max_rss_size; 30794093d1a2SGuangbin Huang 308035244430SJian Shen kinfo->num_tqps = kinfo->tc_info.num_tc * kinfo->rss_size; 30814093d1a2SGuangbin Huang } 30824093d1a2SGuangbin Huang 30834093d1a2SGuangbin Huang static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 30844093d1a2SGuangbin Huang bool rxfh_configured) 30854093d1a2SGuangbin Huang { 30864093d1a2SGuangbin Huang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 30874093d1a2SGuangbin Huang struct hnae3_knic_private_info *kinfo = &handle->kinfo; 308893969dc1SJie Wang u16 tc_offset[HCLGE_COMM_MAX_TC_NUM]; 308993969dc1SJie Wang u16 tc_valid[HCLGE_COMM_MAX_TC_NUM]; 309093969dc1SJie Wang u16 tc_size[HCLGE_COMM_MAX_TC_NUM]; 30914093d1a2SGuangbin Huang u16 cur_rss_size = kinfo->rss_size; 30924093d1a2SGuangbin Huang u16 cur_tqps = kinfo->num_tqps; 30934093d1a2SGuangbin Huang u32 *rss_indir; 30944093d1a2SGuangbin Huang unsigned int i; 30954093d1a2SGuangbin Huang int ret; 30964093d1a2SGuangbin Huang 30974093d1a2SGuangbin Huang hclgevf_update_rss_size(handle, new_tqps_num); 30984093d1a2SGuangbin Huang 3099ae9f29fdSJie Wang hclge_comm_get_rss_tc_info(kinfo->rss_size, hdev->hw_tc_map, 310093969dc1SJie Wang tc_offset, tc_valid, tc_size); 310193969dc1SJie Wang ret = hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, 310293969dc1SJie Wang tc_valid, tc_size); 31034093d1a2SGuangbin Huang if (ret) 31044093d1a2SGuangbin Huang return ret; 31054093d1a2SGuangbin Huang 3106cd7e963dSSalil Mehta /* RSS indirection table has been configured by user */ 31074093d1a2SGuangbin Huang if (rxfh_configured) 31084093d1a2SGuangbin Huang goto out; 31094093d1a2SGuangbin Huang 31104093d1a2SGuangbin Huang /* Reinitializes the rss indirect table according to the new RSS size */ 311187ce161eSGuangbin Huang rss_indir = kcalloc(hdev->ae_dev->dev_specs.rss_ind_tbl_size, 311287ce161eSGuangbin Huang sizeof(u32), GFP_KERNEL); 31134093d1a2SGuangbin Huang if (!rss_indir) 31144093d1a2SGuangbin Huang return -ENOMEM; 31154093d1a2SGuangbin Huang 311687ce161eSGuangbin Huang for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 31174093d1a2SGuangbin Huang rss_indir[i] = i % kinfo->rss_size; 31184093d1a2SGuangbin Huang 3119944de484SGuojia Liao hdev->rss_cfg.rss_size = kinfo->rss_size; 3120944de484SGuojia Liao 31214093d1a2SGuangbin Huang ret = hclgevf_set_rss(handle, rss_indir, NULL, 0); 31224093d1a2SGuangbin Huang if (ret) 31234093d1a2SGuangbin Huang dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 31244093d1a2SGuangbin Huang ret); 31254093d1a2SGuangbin Huang 31264093d1a2SGuangbin Huang kfree(rss_indir); 31274093d1a2SGuangbin Huang 31284093d1a2SGuangbin Huang out: 31294093d1a2SGuangbin Huang if (!ret) 31304093d1a2SGuangbin Huang dev_info(&hdev->pdev->dev, 31314093d1a2SGuangbin Huang "Channels changed, rss_size from %u to %u, tqps from %u to %u", 31324093d1a2SGuangbin Huang cur_rss_size, kinfo->rss_size, 313335244430SJian Shen cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 31344093d1a2SGuangbin Huang 31354093d1a2SGuangbin Huang return ret; 31364093d1a2SGuangbin Huang } 31374093d1a2SGuangbin Huang 3138175ec96bSFuyun Liang static int hclgevf_get_status(struct hnae3_handle *handle) 3139175ec96bSFuyun Liang { 3140175ec96bSFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3141175ec96bSFuyun Liang 3142175ec96bSFuyun Liang return hdev->hw.mac.link; 3143175ec96bSFuyun Liang } 3144175ec96bSFuyun Liang 31454a152de9SFuyun Liang static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 31464a152de9SFuyun Liang u8 *auto_neg, u32 *speed, 31470f032f93SHao Chen u8 *duplex, u32 *lane_num) 31484a152de9SFuyun Liang { 31494a152de9SFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 31504a152de9SFuyun Liang 31514a152de9SFuyun Liang if (speed) 31524a152de9SFuyun Liang *speed = hdev->hw.mac.speed; 31534a152de9SFuyun Liang if (duplex) 31544a152de9SFuyun Liang *duplex = hdev->hw.mac.duplex; 31554a152de9SFuyun Liang if (auto_neg) 31564a152de9SFuyun Liang *auto_neg = AUTONEG_DISABLE; 31574a152de9SFuyun Liang } 31584a152de9SFuyun Liang 31594a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 31604a152de9SFuyun Liang u8 duplex) 31614a152de9SFuyun Liang { 31624a152de9SFuyun Liang hdev->hw.mac.speed = speed; 31634a152de9SFuyun Liang hdev->hw.mac.duplex = duplex; 31644a152de9SFuyun Liang } 31654a152de9SFuyun Liang 31661731be4cSYonglong Liu static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 31675c9f6b39SPeng Li { 31685c9f6b39SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 31693462207dSYufeng Mo bool gro_en_old = hdev->gro_en; 31703462207dSYufeng Mo int ret; 31715c9f6b39SPeng Li 31723462207dSYufeng Mo hdev->gro_en = enable; 31733462207dSYufeng Mo ret = hclgevf_config_gro(hdev); 31743462207dSYufeng Mo if (ret) 31753462207dSYufeng Mo hdev->gro_en = gro_en_old; 31763462207dSYufeng Mo 31773462207dSYufeng Mo return ret; 31785c9f6b39SPeng Li } 31795c9f6b39SPeng Li 318088d10bd6SJian Shen static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 318188d10bd6SJian Shen u8 *module_type) 3182c136b884SPeng Li { 3183c136b884SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 318488d10bd6SJian Shen 3185c136b884SPeng Li if (media_type) 3186c136b884SPeng Li *media_type = hdev->hw.mac.media_type; 318788d10bd6SJian Shen 318888d10bd6SJian Shen if (module_type) 318988d10bd6SJian Shen *module_type = hdev->hw.mac.module_type; 3190c136b884SPeng Li } 3191c136b884SPeng Li 31924d60291bSHuazhong Tan static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 31934d60291bSHuazhong Tan { 31944d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 31954d60291bSHuazhong Tan 3196aa5c4f17SHuazhong Tan return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 31974d60291bSHuazhong Tan } 31984d60291bSHuazhong Tan 3199fe735c84SHuazhong Tan static bool hclgevf_get_cmdq_stat(struct hnae3_handle *handle) 3200fe735c84SHuazhong Tan { 3201fe735c84SHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3202fe735c84SHuazhong Tan 3203076bb537SJie Wang return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3204fe735c84SHuazhong Tan } 3205fe735c84SHuazhong Tan 32064d60291bSHuazhong Tan static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 32074d60291bSHuazhong Tan { 32084d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 32094d60291bSHuazhong Tan 32104d60291bSHuazhong Tan return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 32114d60291bSHuazhong Tan } 32124d60291bSHuazhong Tan 32134d60291bSHuazhong Tan static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 32144d60291bSHuazhong Tan { 32154d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 32164d60291bSHuazhong Tan 3217c88a6e7dSHuazhong Tan return hdev->rst_stats.hw_rst_done_cnt; 32184d60291bSHuazhong Tan } 32194d60291bSHuazhong Tan 32209194d18bSliuzhongzhu static void hclgevf_get_link_mode(struct hnae3_handle *handle, 32219194d18bSliuzhongzhu unsigned long *supported, 32229194d18bSliuzhongzhu unsigned long *advertising) 32239194d18bSliuzhongzhu { 32249194d18bSliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 32259194d18bSliuzhongzhu 32269194d18bSliuzhongzhu *supported = hdev->hw.mac.supported; 32279194d18bSliuzhongzhu *advertising = hdev->hw.mac.advertising; 32289194d18bSliuzhongzhu } 32299194d18bSliuzhongzhu 323092f11ea1SJian Shen void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 3231767975e5SJie Wang struct hclge_mbx_port_base_vlan *port_base_vlan) 323292f11ea1SJian Shen { 323392f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 3234d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 3235a6f7bfdcSJian Shen int ret; 323692f11ea1SJian Shen 323792f11ea1SJian Shen rtnl_lock(); 3238a6f7bfdcSJian Shen 3239b7b5d25bSGuojia Liao if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 3240b7b5d25bSGuojia Liao test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) { 3241a6f7bfdcSJian Shen dev_warn(&hdev->pdev->dev, 3242a6f7bfdcSJian Shen "is resetting when updating port based vlan info\n"); 324392f11ea1SJian Shen rtnl_unlock(); 3244a6f7bfdcSJian Shen return; 3245a6f7bfdcSJian Shen } 3246a6f7bfdcSJian Shen 3247a6f7bfdcSJian Shen ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 3248a6f7bfdcSJian Shen if (ret) { 3249a6f7bfdcSJian Shen rtnl_unlock(); 3250a6f7bfdcSJian Shen return; 3251a6f7bfdcSJian Shen } 325292f11ea1SJian Shen 325392f11ea1SJian Shen /* send msg to PF and wait update port based vlan info */ 3254d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 3255d3410018SYufeng Mo HCLGE_MBX_PORT_BASE_VLAN_CFG); 3256767975e5SJie Wang memcpy(send_msg.data, port_base_vlan, sizeof(*port_base_vlan)); 3257a6f7bfdcSJian Shen ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3258a6f7bfdcSJian Shen if (!ret) { 325992f11ea1SJian Shen if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 3260a6f7bfdcSJian Shen nic->port_base_vlan_state = state; 326192f11ea1SJian Shen else 326292f11ea1SJian Shen nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 3263a6f7bfdcSJian Shen } 326492f11ea1SJian Shen 326592f11ea1SJian Shen hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 326692f11ea1SJian Shen rtnl_unlock(); 326792f11ea1SJian Shen } 326892f11ea1SJian Shen 3269e2cb1decSSalil Mehta static const struct hnae3_ae_ops hclgevf_ops = { 3270e2cb1decSSalil Mehta .init_ae_dev = hclgevf_init_ae_dev, 3271e2cb1decSSalil Mehta .uninit_ae_dev = hclgevf_uninit_ae_dev, 3272bb1890d5SJiaran Zhang .reset_prepare = hclgevf_reset_prepare_general, 3273bb1890d5SJiaran Zhang .reset_done = hclgevf_reset_done, 3274e718a93fSPeng Li .init_client_instance = hclgevf_init_client_instance, 3275e718a93fSPeng Li .uninit_client_instance = hclgevf_uninit_client_instance, 3276e2cb1decSSalil Mehta .start = hclgevf_ae_start, 3277e2cb1decSSalil Mehta .stop = hclgevf_ae_stop, 3278a6d818e3SYunsheng Lin .client_start = hclgevf_client_start, 3279a6d818e3SYunsheng Lin .client_stop = hclgevf_client_stop, 3280e2cb1decSSalil Mehta .map_ring_to_vector = hclgevf_map_ring_to_vector, 3281e2cb1decSSalil Mehta .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 3282e2cb1decSSalil Mehta .get_vector = hclgevf_get_vector, 32830d3e6631SYunsheng Lin .put_vector = hclgevf_put_vector, 3284e2cb1decSSalil Mehta .reset_queue = hclgevf_reset_tqp, 3285e2cb1decSSalil Mehta .get_mac_addr = hclgevf_get_mac_addr, 3286e2cb1decSSalil Mehta .set_mac_addr = hclgevf_set_mac_addr, 3287e2cb1decSSalil Mehta .add_uc_addr = hclgevf_add_uc_addr, 3288e2cb1decSSalil Mehta .rm_uc_addr = hclgevf_rm_uc_addr, 3289e2cb1decSSalil Mehta .add_mc_addr = hclgevf_add_mc_addr, 3290e2cb1decSSalil Mehta .rm_mc_addr = hclgevf_rm_mc_addr, 3291e2cb1decSSalil Mehta .get_stats = hclgevf_get_stats, 3292e2cb1decSSalil Mehta .update_stats = hclgevf_update_stats, 3293e2cb1decSSalil Mehta .get_strings = hclgevf_get_strings, 3294e2cb1decSSalil Mehta .get_sset_count = hclgevf_get_sset_count, 3295027733b1SJie Wang .get_rss_key_size = hclge_comm_get_rss_key_size, 3296e2cb1decSSalil Mehta .get_rss = hclgevf_get_rss, 3297e2cb1decSSalil Mehta .set_rss = hclgevf_set_rss, 3298d97b3072SJian Shen .get_rss_tuple = hclgevf_get_rss_tuple, 3299d97b3072SJian Shen .set_rss_tuple = hclgevf_set_rss_tuple, 3300e2cb1decSSalil Mehta .get_tc_size = hclgevf_get_tc_size, 3301e2cb1decSSalil Mehta .get_fw_version = hclgevf_get_fw_version, 3302e2cb1decSSalil Mehta .set_vlan_filter = hclgevf_set_vlan_filter, 3303fa6a262aSJian Shen .enable_vlan_filter = hclgevf_enable_vlan_filter, 3304b2641e2aSYunsheng Lin .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 33056d4c3981SSalil Mehta .reset_event = hclgevf_reset_event, 3306720bd583SHuazhong Tan .set_default_reset_request = hclgevf_set_def_reset_request, 33074093d1a2SGuangbin Huang .set_channels = hclgevf_set_channels, 3308849e4607SPeng Li .get_channels = hclgevf_get_channels, 3309cc719218SPeng Li .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 33101600c3e5SJian Shen .get_regs_len = hclgevf_get_regs_len, 33111600c3e5SJian Shen .get_regs = hclgevf_get_regs, 3312175ec96bSFuyun Liang .get_status = hclgevf_get_status, 33134a152de9SFuyun Liang .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3314c136b884SPeng Li .get_media_type = hclgevf_get_media_type, 33154d60291bSHuazhong Tan .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 33164d60291bSHuazhong Tan .ae_dev_resetting = hclgevf_ae_dev_resetting, 33174d60291bSHuazhong Tan .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 33185c9f6b39SPeng Li .set_gro_en = hclgevf_gro_en, 3319818f1675SYunsheng Lin .set_mtu = hclgevf_set_mtu, 33200c29d191Sliuzhongzhu .get_global_queue_id = hclgevf_get_qid_global, 33218cdb992fSJian Shen .set_timer_task = hclgevf_set_timer_task, 33229194d18bSliuzhongzhu .get_link_mode = hclgevf_get_link_mode, 3323e196ec75SJian Shen .set_promisc_mode = hclgevf_set_promisc_mode, 3324c631c696SJian Shen .request_update_promisc_mode = hclgevf_request_update_promisc_mode, 3325fe735c84SHuazhong Tan .get_cmdq_stat = hclgevf_get_cmdq_stat, 3326e2cb1decSSalil Mehta }; 3327e2cb1decSSalil Mehta 3328e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf = { 3329e2cb1decSSalil Mehta .ops = &hclgevf_ops, 3330e2cb1decSSalil Mehta .pdev_id_table = ae_algovf_pci_tbl, 3331e2cb1decSSalil Mehta }; 3332e2cb1decSSalil Mehta 3333134a4647SXiu Jianfeng static int __init hclgevf_init(void) 3334e2cb1decSSalil Mehta { 3335e2cb1decSSalil Mehta pr_info("%s is initializing\n", HCLGEVF_NAME); 3336e2cb1decSSalil Mehta 3337f29da408SYufeng Mo hclgevf_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGEVF_NAME); 33380ea68902SYunsheng Lin if (!hclgevf_wq) { 33390ea68902SYunsheng Lin pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME); 33400ea68902SYunsheng Lin return -ENOMEM; 33410ea68902SYunsheng Lin } 33420ea68902SYunsheng Lin 3343854cf33aSFuyun Liang hnae3_register_ae_algo(&ae_algovf); 3344854cf33aSFuyun Liang 3345854cf33aSFuyun Liang return 0; 3346e2cb1decSSalil Mehta } 3347e2cb1decSSalil Mehta 3348134a4647SXiu Jianfeng static void __exit hclgevf_exit(void) 3349e2cb1decSSalil Mehta { 3350e2cb1decSSalil Mehta hnae3_unregister_ae_algo(&ae_algovf); 33510ea68902SYunsheng Lin destroy_workqueue(hclgevf_wq); 3352e2cb1decSSalil Mehta } 3353e2cb1decSSalil Mehta module_init(hclgevf_init); 3354e2cb1decSSalil Mehta module_exit(hclgevf_exit); 3355e2cb1decSSalil Mehta 3356e2cb1decSSalil Mehta MODULE_LICENSE("GPL"); 3357e2cb1decSSalil Mehta MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3358e2cb1decSSalil Mehta MODULE_DESCRIPTION("HCLGEVF Driver"); 3359e2cb1decSSalil Mehta MODULE_VERSION(HCLGEVF_MOD_VERSION); 3360