1e2cb1decSSalil Mehta // SPDX-License-Identifier: GPL-2.0+ 2e2cb1decSSalil Mehta // Copyright (c) 2016-2017 Hisilicon Limited. 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #include <linux/etherdevice.h> 5aa5c4f17SHuazhong Tan #include <linux/iopoll.h> 66988eb2aSSalil Mehta #include <net/rtnetlink.h> 7e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 8e2cb1decSSalil Mehta #include "hclgevf_main.h" 9e2cb1decSSalil Mehta #include "hclge_mbx.h" 10e2cb1decSSalil Mehta #include "hnae3.h" 11e2cb1decSSalil Mehta 12e2cb1decSSalil Mehta #define HCLGEVF_NAME "hclgevf" 13e2cb1decSSalil Mehta 149c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 15e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf; 16e2cb1decSSalil Mehta 17e2cb1decSSalil Mehta static const struct pci_device_id ae_algovf_pci_tbl[] = { 18e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 19e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 20e2cb1decSSalil Mehta /* required last entry */ 21e2cb1decSSalil Mehta {0, } 22e2cb1decSSalil Mehta }; 23e2cb1decSSalil Mehta 24472d7eceSJian Shen static const u8 hclgevf_hash_key[] = { 25472d7eceSJian Shen 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 26472d7eceSJian Shen 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 27472d7eceSJian Shen 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 28472d7eceSJian Shen 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 29472d7eceSJian Shen 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 30472d7eceSJian Shen }; 31472d7eceSJian Shen 322f550a46SYunsheng Lin MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 332f550a46SYunsheng Lin 341600c3e5SJian Shen static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 351600c3e5SJian Shen HCLGEVF_CMDQ_TX_ADDR_H_REG, 361600c3e5SJian Shen HCLGEVF_CMDQ_TX_DEPTH_REG, 371600c3e5SJian Shen HCLGEVF_CMDQ_TX_TAIL_REG, 381600c3e5SJian Shen HCLGEVF_CMDQ_TX_HEAD_REG, 391600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_L_REG, 401600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_H_REG, 411600c3e5SJian Shen HCLGEVF_CMDQ_RX_DEPTH_REG, 421600c3e5SJian Shen HCLGEVF_CMDQ_RX_TAIL_REG, 431600c3e5SJian Shen HCLGEVF_CMDQ_RX_HEAD_REG, 441600c3e5SJian Shen HCLGEVF_VECTOR0_CMDQ_SRC_REG, 451600c3e5SJian Shen HCLGEVF_CMDQ_INTR_STS_REG, 461600c3e5SJian Shen HCLGEVF_CMDQ_INTR_EN_REG, 471600c3e5SJian Shen HCLGEVF_CMDQ_INTR_GEN_REG}; 481600c3e5SJian Shen 491600c3e5SJian Shen static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 501600c3e5SJian Shen HCLGEVF_RST_ING, 511600c3e5SJian Shen HCLGEVF_GRO_EN_REG}; 521600c3e5SJian Shen 531600c3e5SJian Shen static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 541600c3e5SJian Shen HCLGEVF_RING_RX_ADDR_H_REG, 551600c3e5SJian Shen HCLGEVF_RING_RX_BD_NUM_REG, 561600c3e5SJian Shen HCLGEVF_RING_RX_BD_LENGTH_REG, 571600c3e5SJian Shen HCLGEVF_RING_RX_MERGE_EN_REG, 581600c3e5SJian Shen HCLGEVF_RING_RX_TAIL_REG, 591600c3e5SJian Shen HCLGEVF_RING_RX_HEAD_REG, 601600c3e5SJian Shen HCLGEVF_RING_RX_FBD_NUM_REG, 611600c3e5SJian Shen HCLGEVF_RING_RX_OFFSET_REG, 621600c3e5SJian Shen HCLGEVF_RING_RX_FBD_OFFSET_REG, 631600c3e5SJian Shen HCLGEVF_RING_RX_STASH_REG, 641600c3e5SJian Shen HCLGEVF_RING_RX_BD_ERR_REG, 651600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_L_REG, 661600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_H_REG, 671600c3e5SJian Shen HCLGEVF_RING_TX_BD_NUM_REG, 681600c3e5SJian Shen HCLGEVF_RING_TX_PRIORITY_REG, 691600c3e5SJian Shen HCLGEVF_RING_TX_TC_REG, 701600c3e5SJian Shen HCLGEVF_RING_TX_MERGE_EN_REG, 711600c3e5SJian Shen HCLGEVF_RING_TX_TAIL_REG, 721600c3e5SJian Shen HCLGEVF_RING_TX_HEAD_REG, 731600c3e5SJian Shen HCLGEVF_RING_TX_FBD_NUM_REG, 741600c3e5SJian Shen HCLGEVF_RING_TX_OFFSET_REG, 751600c3e5SJian Shen HCLGEVF_RING_TX_EBD_NUM_REG, 761600c3e5SJian Shen HCLGEVF_RING_TX_EBD_OFFSET_REG, 771600c3e5SJian Shen HCLGEVF_RING_TX_BD_ERR_REG, 781600c3e5SJian Shen HCLGEVF_RING_EN_REG}; 791600c3e5SJian Shen 801600c3e5SJian Shen static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 811600c3e5SJian Shen HCLGEVF_TQP_INTR_GL0_REG, 821600c3e5SJian Shen HCLGEVF_TQP_INTR_GL1_REG, 831600c3e5SJian Shen HCLGEVF_TQP_INTR_GL2_REG, 841600c3e5SJian Shen HCLGEVF_TQP_INTR_RL_REG}; 851600c3e5SJian Shen 869b2f3477SWeihang Li static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 87e2cb1decSSalil Mehta { 88eed9535fSPeng Li if (!handle->client) 89eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, nic); 90eed9535fSPeng Li else if (handle->client->type == HNAE3_CLIENT_ROCE) 91eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, roce); 92eed9535fSPeng Li else 93e2cb1decSSalil Mehta return container_of(handle, struct hclgevf_dev, nic); 94e2cb1decSSalil Mehta } 95e2cb1decSSalil Mehta 96e2cb1decSSalil Mehta static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 97e2cb1decSSalil Mehta { 98b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 99e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 100e2cb1decSSalil Mehta struct hclgevf_desc desc; 101e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 102e2cb1decSSalil Mehta int status; 103e2cb1decSSalil Mehta int i; 104e2cb1decSSalil Mehta 105b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 106b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 107e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 108e2cb1decSSalil Mehta HCLGEVF_OPC_QUERY_RX_STATUS, 109e2cb1decSSalil Mehta true); 110e2cb1decSSalil Mehta 111e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 112e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 113e2cb1decSSalil Mehta if (status) { 114e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 115e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 116e2cb1decSSalil Mehta status, i); 117e2cb1decSSalil Mehta return status; 118e2cb1decSSalil Mehta } 119e2cb1decSSalil Mehta tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 120cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 121e2cb1decSSalil Mehta 122e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 123e2cb1decSSalil Mehta true); 124e2cb1decSSalil Mehta 125e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 126e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 127e2cb1decSSalil Mehta if (status) { 128e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 129e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 130e2cb1decSSalil Mehta status, i); 131e2cb1decSSalil Mehta return status; 132e2cb1decSSalil Mehta } 133e2cb1decSSalil Mehta tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 134cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 135e2cb1decSSalil Mehta } 136e2cb1decSSalil Mehta 137e2cb1decSSalil Mehta return 0; 138e2cb1decSSalil Mehta } 139e2cb1decSSalil Mehta 140e2cb1decSSalil Mehta static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 141e2cb1decSSalil Mehta { 142e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo = &handle->kinfo; 143e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 144e2cb1decSSalil Mehta u64 *buff = data; 145e2cb1decSSalil Mehta int i; 146e2cb1decSSalil Mehta 147b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 148b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 149e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 150e2cb1decSSalil Mehta } 151e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 152b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 153e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 154e2cb1decSSalil Mehta } 155e2cb1decSSalil Mehta 156e2cb1decSSalil Mehta return buff; 157e2cb1decSSalil Mehta } 158e2cb1decSSalil Mehta 159e2cb1decSSalil Mehta static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 160e2cb1decSSalil Mehta { 161b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 162e2cb1decSSalil Mehta 163b4f1d303SJian Shen return kinfo->num_tqps * 2; 164e2cb1decSSalil Mehta } 165e2cb1decSSalil Mehta 166e2cb1decSSalil Mehta static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 167e2cb1decSSalil Mehta { 168b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 169e2cb1decSSalil Mehta u8 *buff = data; 170e2cb1decSSalil Mehta int i = 0; 171e2cb1decSSalil Mehta 172b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 173b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 174e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1750c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 176e2cb1decSSalil Mehta tqp->index); 177e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 178e2cb1decSSalil Mehta } 179e2cb1decSSalil Mehta 180b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 181b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 182e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1830c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 184e2cb1decSSalil Mehta tqp->index); 185e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 186e2cb1decSSalil Mehta } 187e2cb1decSSalil Mehta 188e2cb1decSSalil Mehta return buff; 189e2cb1decSSalil Mehta } 190e2cb1decSSalil Mehta 191e2cb1decSSalil Mehta static void hclgevf_update_stats(struct hnae3_handle *handle, 192e2cb1decSSalil Mehta struct net_device_stats *net_stats) 193e2cb1decSSalil Mehta { 194e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 195e2cb1decSSalil Mehta int status; 196e2cb1decSSalil Mehta 197e2cb1decSSalil Mehta status = hclgevf_tqps_update_stats(handle); 198e2cb1decSSalil Mehta if (status) 199e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 200e2cb1decSSalil Mehta "VF update of TQPS stats fail, status = %d.\n", 201e2cb1decSSalil Mehta status); 202e2cb1decSSalil Mehta } 203e2cb1decSSalil Mehta 204e2cb1decSSalil Mehta static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 205e2cb1decSSalil Mehta { 206e2cb1decSSalil Mehta if (strset == ETH_SS_TEST) 207e2cb1decSSalil Mehta return -EOPNOTSUPP; 208e2cb1decSSalil Mehta else if (strset == ETH_SS_STATS) 209e2cb1decSSalil Mehta return hclgevf_tqps_get_sset_count(handle, strset); 210e2cb1decSSalil Mehta 211e2cb1decSSalil Mehta return 0; 212e2cb1decSSalil Mehta } 213e2cb1decSSalil Mehta 214e2cb1decSSalil Mehta static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 215e2cb1decSSalil Mehta u8 *data) 216e2cb1decSSalil Mehta { 217e2cb1decSSalil Mehta u8 *p = (char *)data; 218e2cb1decSSalil Mehta 219e2cb1decSSalil Mehta if (strset == ETH_SS_STATS) 220e2cb1decSSalil Mehta p = hclgevf_tqps_get_strings(handle, p); 221e2cb1decSSalil Mehta } 222e2cb1decSSalil Mehta 223e2cb1decSSalil Mehta static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 224e2cb1decSSalil Mehta { 225e2cb1decSSalil Mehta hclgevf_tqps_get_stats(handle, data); 226e2cb1decSSalil Mehta } 227e2cb1decSSalil Mehta 228e2cb1decSSalil Mehta static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 229e2cb1decSSalil Mehta { 230e2cb1decSSalil Mehta u8 resp_msg; 231e2cb1decSSalil Mehta int status; 232e2cb1decSSalil Mehta 233e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 23463cbf7a9SYufeng Mo true, &resp_msg, sizeof(resp_msg)); 235e2cb1decSSalil Mehta if (status) { 236e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 237e2cb1decSSalil Mehta "VF request to get TC info from PF failed %d", 238e2cb1decSSalil Mehta status); 239e2cb1decSSalil Mehta return status; 240e2cb1decSSalil Mehta } 241e2cb1decSSalil Mehta 242e2cb1decSSalil Mehta hdev->hw_tc_map = resp_msg; 243e2cb1decSSalil Mehta 244e2cb1decSSalil Mehta return 0; 245e2cb1decSSalil Mehta } 246e2cb1decSSalil Mehta 24792f11ea1SJian Shen static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 24892f11ea1SJian Shen { 24992f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 25092f11ea1SJian Shen u8 resp_msg; 25192f11ea1SJian Shen int ret; 25292f11ea1SJian Shen 25392f11ea1SJian Shen ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 25492f11ea1SJian Shen HCLGE_MBX_GET_PORT_BASE_VLAN_STATE, 25592f11ea1SJian Shen NULL, 0, true, &resp_msg, sizeof(u8)); 25692f11ea1SJian Shen if (ret) { 25792f11ea1SJian Shen dev_err(&hdev->pdev->dev, 25892f11ea1SJian Shen "VF request to get port based vlan state failed %d", 25992f11ea1SJian Shen ret); 26092f11ea1SJian Shen return ret; 26192f11ea1SJian Shen } 26292f11ea1SJian Shen 26392f11ea1SJian Shen nic->port_base_vlan_state = resp_msg; 26492f11ea1SJian Shen 26592f11ea1SJian Shen return 0; 26692f11ea1SJian Shen } 26792f11ea1SJian Shen 2686cee6fc3SJian Shen static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 269e2cb1decSSalil Mehta { 270c0425944SPeng Li #define HCLGEVF_TQPS_RSS_INFO_LEN 6 271e2cb1decSSalil Mehta u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 272e2cb1decSSalil Mehta int status; 273e2cb1decSSalil Mehta 274e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 275e2cb1decSSalil Mehta true, resp_msg, 276e2cb1decSSalil Mehta HCLGEVF_TQPS_RSS_INFO_LEN); 277e2cb1decSSalil Mehta if (status) { 278e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 279e2cb1decSSalil Mehta "VF request to get tqp info from PF failed %d", 280e2cb1decSSalil Mehta status); 281e2cb1decSSalil Mehta return status; 282e2cb1decSSalil Mehta } 283e2cb1decSSalil Mehta 284e2cb1decSSalil Mehta memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 285e2cb1decSSalil Mehta memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 286c0425944SPeng Li memcpy(&hdev->rx_buf_len, &resp_msg[4], sizeof(u16)); 287c0425944SPeng Li 288c0425944SPeng Li return 0; 289c0425944SPeng Li } 290c0425944SPeng Li 291c0425944SPeng Li static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 292c0425944SPeng Li { 293c0425944SPeng Li #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 294c0425944SPeng Li u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 295c0425944SPeng Li int ret; 296c0425944SPeng Li 297c0425944SPeng Li ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QDEPTH, 0, NULL, 0, 298c0425944SPeng Li true, resp_msg, 299c0425944SPeng Li HCLGEVF_TQPS_DEPTH_INFO_LEN); 300c0425944SPeng Li if (ret) { 301c0425944SPeng Li dev_err(&hdev->pdev->dev, 302c0425944SPeng Li "VF request to get tqp depth info from PF failed %d", 303c0425944SPeng Li ret); 304c0425944SPeng Li return ret; 305c0425944SPeng Li } 306c0425944SPeng Li 307c0425944SPeng Li memcpy(&hdev->num_tx_desc, &resp_msg[0], sizeof(u16)); 308c0425944SPeng Li memcpy(&hdev->num_rx_desc, &resp_msg[2], sizeof(u16)); 309e2cb1decSSalil Mehta 310e2cb1decSSalil Mehta return 0; 311e2cb1decSSalil Mehta } 312e2cb1decSSalil Mehta 3130c29d191Sliuzhongzhu static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 3140c29d191Sliuzhongzhu { 3150c29d191Sliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3160c29d191Sliuzhongzhu u8 msg_data[2], resp_data[2]; 3170c29d191Sliuzhongzhu u16 qid_in_pf = 0; 3180c29d191Sliuzhongzhu int ret; 3190c29d191Sliuzhongzhu 3200c29d191Sliuzhongzhu memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 3210c29d191Sliuzhongzhu 3220c29d191Sliuzhongzhu ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data, 32363cbf7a9SYufeng Mo sizeof(msg_data), true, resp_data, 32463cbf7a9SYufeng Mo sizeof(resp_data)); 3250c29d191Sliuzhongzhu if (!ret) 3260c29d191Sliuzhongzhu qid_in_pf = *(u16 *)resp_data; 3270c29d191Sliuzhongzhu 3280c29d191Sliuzhongzhu return qid_in_pf; 3290c29d191Sliuzhongzhu } 3300c29d191Sliuzhongzhu 3319c3e7130Sliuzhongzhu static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 3329c3e7130Sliuzhongzhu { 33388d10bd6SJian Shen u8 resp_msg[2]; 3349c3e7130Sliuzhongzhu int ret; 3359c3e7130Sliuzhongzhu 3369c3e7130Sliuzhongzhu ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_MEDIA_TYPE, 0, NULL, 0, 33788d10bd6SJian Shen true, resp_msg, sizeof(resp_msg)); 3389c3e7130Sliuzhongzhu if (ret) { 3399c3e7130Sliuzhongzhu dev_err(&hdev->pdev->dev, 3409c3e7130Sliuzhongzhu "VF request to get the pf port media type failed %d", 3419c3e7130Sliuzhongzhu ret); 3429c3e7130Sliuzhongzhu return ret; 3439c3e7130Sliuzhongzhu } 3449c3e7130Sliuzhongzhu 34588d10bd6SJian Shen hdev->hw.mac.media_type = resp_msg[0]; 34688d10bd6SJian Shen hdev->hw.mac.module_type = resp_msg[1]; 3479c3e7130Sliuzhongzhu 3489c3e7130Sliuzhongzhu return 0; 3499c3e7130Sliuzhongzhu } 3509c3e7130Sliuzhongzhu 351e2cb1decSSalil Mehta static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 352e2cb1decSSalil Mehta { 353e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 354e2cb1decSSalil Mehta int i; 355e2cb1decSSalil Mehta 356e2cb1decSSalil Mehta hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 357e2cb1decSSalil Mehta sizeof(struct hclgevf_tqp), GFP_KERNEL); 358e2cb1decSSalil Mehta if (!hdev->htqp) 359e2cb1decSSalil Mehta return -ENOMEM; 360e2cb1decSSalil Mehta 361e2cb1decSSalil Mehta tqp = hdev->htqp; 362e2cb1decSSalil Mehta 363e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 364e2cb1decSSalil Mehta tqp->dev = &hdev->pdev->dev; 365e2cb1decSSalil Mehta tqp->index = i; 366e2cb1decSSalil Mehta 367e2cb1decSSalil Mehta tqp->q.ae_algo = &ae_algovf; 368e2cb1decSSalil Mehta tqp->q.buf_size = hdev->rx_buf_len; 369c0425944SPeng Li tqp->q.tx_desc_num = hdev->num_tx_desc; 370c0425944SPeng Li tqp->q.rx_desc_num = hdev->num_rx_desc; 371e2cb1decSSalil Mehta tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 372e2cb1decSSalil Mehta i * HCLGEVF_TQP_REG_SIZE; 373e2cb1decSSalil Mehta 374e2cb1decSSalil Mehta tqp++; 375e2cb1decSSalil Mehta } 376e2cb1decSSalil Mehta 377e2cb1decSSalil Mehta return 0; 378e2cb1decSSalil Mehta } 379e2cb1decSSalil Mehta 380e2cb1decSSalil Mehta static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 381e2cb1decSSalil Mehta { 382e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 383e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo; 384e2cb1decSSalil Mehta u16 new_tqps = hdev->num_tqps; 385ebaf1908SWeihang Li unsigned int i; 386e2cb1decSSalil Mehta 387e2cb1decSSalil Mehta kinfo = &nic->kinfo; 388e2cb1decSSalil Mehta kinfo->num_tc = 0; 389c0425944SPeng Li kinfo->num_tx_desc = hdev->num_tx_desc; 390c0425944SPeng Li kinfo->num_rx_desc = hdev->num_rx_desc; 391e2cb1decSSalil Mehta kinfo->rx_buf_len = hdev->rx_buf_len; 392e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 393e2cb1decSSalil Mehta if (hdev->hw_tc_map & BIT(i)) 394e2cb1decSSalil Mehta kinfo->num_tc++; 395e2cb1decSSalil Mehta 396e2cb1decSSalil Mehta kinfo->rss_size 397e2cb1decSSalil Mehta = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 398e2cb1decSSalil Mehta new_tqps = kinfo->rss_size * kinfo->num_tc; 399e2cb1decSSalil Mehta kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 400e2cb1decSSalil Mehta 401e2cb1decSSalil Mehta kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 402e2cb1decSSalil Mehta sizeof(struct hnae3_queue *), GFP_KERNEL); 403e2cb1decSSalil Mehta if (!kinfo->tqp) 404e2cb1decSSalil Mehta return -ENOMEM; 405e2cb1decSSalil Mehta 406e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 407e2cb1decSSalil Mehta hdev->htqp[i].q.handle = &hdev->nic; 408e2cb1decSSalil Mehta hdev->htqp[i].q.tqp_index = i; 409e2cb1decSSalil Mehta kinfo->tqp[i] = &hdev->htqp[i].q; 410e2cb1decSSalil Mehta } 411e2cb1decSSalil Mehta 412e2cb1decSSalil Mehta return 0; 413e2cb1decSSalil Mehta } 414e2cb1decSSalil Mehta 415e2cb1decSSalil Mehta static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 416e2cb1decSSalil Mehta { 417e2cb1decSSalil Mehta int status; 418e2cb1decSSalil Mehta u8 resp_msg; 419e2cb1decSSalil Mehta 420e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 42163cbf7a9SYufeng Mo 0, false, &resp_msg, sizeof(resp_msg)); 422e2cb1decSSalil Mehta if (status) 423e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 424e2cb1decSSalil Mehta "VF failed to fetch link status(%d) from PF", status); 425e2cb1decSSalil Mehta } 426e2cb1decSSalil Mehta 427e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 428e2cb1decSSalil Mehta { 42945e92b7eSPeng Li struct hnae3_handle *rhandle = &hdev->roce; 430e2cb1decSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 43145e92b7eSPeng Li struct hnae3_client *rclient; 432e2cb1decSSalil Mehta struct hnae3_client *client; 433e2cb1decSSalil Mehta 434e2cb1decSSalil Mehta client = handle->client; 43545e92b7eSPeng Li rclient = hdev->roce_client; 436e2cb1decSSalil Mehta 437582d37bbSPeng Li link_state = 438582d37bbSPeng Li test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 439582d37bbSPeng Li 440e2cb1decSSalil Mehta if (link_state != hdev->hw.mac.link) { 441e2cb1decSSalil Mehta client->ops->link_status_change(handle, !!link_state); 44245e92b7eSPeng Li if (rclient && rclient->ops->link_status_change) 44345e92b7eSPeng Li rclient->ops->link_status_change(rhandle, !!link_state); 444e2cb1decSSalil Mehta hdev->hw.mac.link = link_state; 445e2cb1decSSalil Mehta } 446e2cb1decSSalil Mehta } 447e2cb1decSSalil Mehta 448538abaf3SYueHaibing static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 4499194d18bSliuzhongzhu { 4509194d18bSliuzhongzhu #define HCLGEVF_ADVERTISING 0 4519194d18bSliuzhongzhu #define HCLGEVF_SUPPORTED 1 4529194d18bSliuzhongzhu u8 send_msg; 4539194d18bSliuzhongzhu u8 resp_msg; 4549194d18bSliuzhongzhu 4559194d18bSliuzhongzhu send_msg = HCLGEVF_ADVERTISING; 45663cbf7a9SYufeng Mo hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 45763cbf7a9SYufeng Mo &send_msg, sizeof(send_msg), false, 45863cbf7a9SYufeng Mo &resp_msg, sizeof(resp_msg)); 4599194d18bSliuzhongzhu send_msg = HCLGEVF_SUPPORTED; 46063cbf7a9SYufeng Mo hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 46163cbf7a9SYufeng Mo &send_msg, sizeof(send_msg), false, 46263cbf7a9SYufeng Mo &resp_msg, sizeof(resp_msg)); 4639194d18bSliuzhongzhu } 4649194d18bSliuzhongzhu 465e2cb1decSSalil Mehta static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 466e2cb1decSSalil Mehta { 467e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 468e2cb1decSSalil Mehta int ret; 469e2cb1decSSalil Mehta 470e2cb1decSSalil Mehta nic->ae_algo = &ae_algovf; 471e2cb1decSSalil Mehta nic->pdev = hdev->pdev; 472e2cb1decSSalil Mehta nic->numa_node_mask = hdev->numa_node_mask; 473424eb834SSalil Mehta nic->flags |= HNAE3_SUPPORT_VF; 474e2cb1decSSalil Mehta 475e2cb1decSSalil Mehta ret = hclgevf_knic_setup(hdev); 476e2cb1decSSalil Mehta if (ret) 477e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 478e2cb1decSSalil Mehta ret); 479e2cb1decSSalil Mehta return ret; 480e2cb1decSSalil Mehta } 481e2cb1decSSalil Mehta 482e2cb1decSSalil Mehta static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 483e2cb1decSSalil Mehta { 48436cbbdf6SPeng Li if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 48536cbbdf6SPeng Li dev_warn(&hdev->pdev->dev, 48636cbbdf6SPeng Li "vector(vector_id %d) has been freed.\n", vector_id); 48736cbbdf6SPeng Li return; 48836cbbdf6SPeng Li } 48936cbbdf6SPeng Li 490e2cb1decSSalil Mehta hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 491e2cb1decSSalil Mehta hdev->num_msi_left += 1; 492e2cb1decSSalil Mehta hdev->num_msi_used -= 1; 493e2cb1decSSalil Mehta } 494e2cb1decSSalil Mehta 495e2cb1decSSalil Mehta static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 496e2cb1decSSalil Mehta struct hnae3_vector_info *vector_info) 497e2cb1decSSalil Mehta { 498e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 499e2cb1decSSalil Mehta struct hnae3_vector_info *vector = vector_info; 500e2cb1decSSalil Mehta int alloc = 0; 501e2cb1decSSalil Mehta int i, j; 502e2cb1decSSalil Mehta 503e2cb1decSSalil Mehta vector_num = min(hdev->num_msi_left, vector_num); 504e2cb1decSSalil Mehta 505e2cb1decSSalil Mehta for (j = 0; j < vector_num; j++) { 506e2cb1decSSalil Mehta for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 507e2cb1decSSalil Mehta if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 508e2cb1decSSalil Mehta vector->vector = pci_irq_vector(hdev->pdev, i); 509e2cb1decSSalil Mehta vector->io_addr = hdev->hw.io_base + 510e2cb1decSSalil Mehta HCLGEVF_VECTOR_REG_BASE + 511e2cb1decSSalil Mehta (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 512e2cb1decSSalil Mehta hdev->vector_status[i] = 0; 513e2cb1decSSalil Mehta hdev->vector_irq[i] = vector->vector; 514e2cb1decSSalil Mehta 515e2cb1decSSalil Mehta vector++; 516e2cb1decSSalil Mehta alloc++; 517e2cb1decSSalil Mehta 518e2cb1decSSalil Mehta break; 519e2cb1decSSalil Mehta } 520e2cb1decSSalil Mehta } 521e2cb1decSSalil Mehta } 522e2cb1decSSalil Mehta hdev->num_msi_left -= alloc; 523e2cb1decSSalil Mehta hdev->num_msi_used += alloc; 524e2cb1decSSalil Mehta 525e2cb1decSSalil Mehta return alloc; 526e2cb1decSSalil Mehta } 527e2cb1decSSalil Mehta 528e2cb1decSSalil Mehta static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 529e2cb1decSSalil Mehta { 530e2cb1decSSalil Mehta int i; 531e2cb1decSSalil Mehta 532e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 533e2cb1decSSalil Mehta if (vector == hdev->vector_irq[i]) 534e2cb1decSSalil Mehta return i; 535e2cb1decSSalil Mehta 536e2cb1decSSalil Mehta return -EINVAL; 537e2cb1decSSalil Mehta } 538e2cb1decSSalil Mehta 539374ad291SJian Shen static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 540374ad291SJian Shen const u8 hfunc, const u8 *key) 541374ad291SJian Shen { 542374ad291SJian Shen struct hclgevf_rss_config_cmd *req; 543ebaf1908SWeihang Li unsigned int key_offset = 0; 544374ad291SJian Shen struct hclgevf_desc desc; 5453caf772bSYufeng Mo int key_counts; 546374ad291SJian Shen int key_size; 547374ad291SJian Shen int ret; 548374ad291SJian Shen 5493caf772bSYufeng Mo key_counts = HCLGEVF_RSS_KEY_SIZE; 550374ad291SJian Shen req = (struct hclgevf_rss_config_cmd *)desc.data; 551374ad291SJian Shen 5523caf772bSYufeng Mo while (key_counts) { 553374ad291SJian Shen hclgevf_cmd_setup_basic_desc(&desc, 554374ad291SJian Shen HCLGEVF_OPC_RSS_GENERIC_CONFIG, 555374ad291SJian Shen false); 556374ad291SJian Shen 557374ad291SJian Shen req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 558374ad291SJian Shen req->hash_config |= 559374ad291SJian Shen (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 560374ad291SJian Shen 5613caf772bSYufeng Mo key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts); 562374ad291SJian Shen memcpy(req->hash_key, 563374ad291SJian Shen key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 564374ad291SJian Shen 5653caf772bSYufeng Mo key_counts -= key_size; 5663caf772bSYufeng Mo key_offset++; 567374ad291SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 568374ad291SJian Shen if (ret) { 569374ad291SJian Shen dev_err(&hdev->pdev->dev, 570374ad291SJian Shen "Configure RSS config fail, status = %d\n", 571374ad291SJian Shen ret); 572374ad291SJian Shen return ret; 573374ad291SJian Shen } 574374ad291SJian Shen } 575374ad291SJian Shen 576374ad291SJian Shen return 0; 577374ad291SJian Shen } 578374ad291SJian Shen 579e2cb1decSSalil Mehta static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 580e2cb1decSSalil Mehta { 581e2cb1decSSalil Mehta return HCLGEVF_RSS_KEY_SIZE; 582e2cb1decSSalil Mehta } 583e2cb1decSSalil Mehta 584e2cb1decSSalil Mehta static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 585e2cb1decSSalil Mehta { 586e2cb1decSSalil Mehta return HCLGEVF_RSS_IND_TBL_SIZE; 587e2cb1decSSalil Mehta } 588e2cb1decSSalil Mehta 589e2cb1decSSalil Mehta static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 590e2cb1decSSalil Mehta { 591e2cb1decSSalil Mehta const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 592e2cb1decSSalil Mehta struct hclgevf_rss_indirection_table_cmd *req; 593e2cb1decSSalil Mehta struct hclgevf_desc desc; 594e2cb1decSSalil Mehta int status; 595e2cb1decSSalil Mehta int i, j; 596e2cb1decSSalil Mehta 597e2cb1decSSalil Mehta req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 598e2cb1decSSalil Mehta 599e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 600e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 601e2cb1decSSalil Mehta false); 602e2cb1decSSalil Mehta req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 603e2cb1decSSalil Mehta req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 604e2cb1decSSalil Mehta for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 605e2cb1decSSalil Mehta req->rss_result[j] = 606e2cb1decSSalil Mehta indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 607e2cb1decSSalil Mehta 608e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 609e2cb1decSSalil Mehta if (status) { 610e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 611e2cb1decSSalil Mehta "VF failed(=%d) to set RSS indirection table\n", 612e2cb1decSSalil Mehta status); 613e2cb1decSSalil Mehta return status; 614e2cb1decSSalil Mehta } 615e2cb1decSSalil Mehta } 616e2cb1decSSalil Mehta 617e2cb1decSSalil Mehta return 0; 618e2cb1decSSalil Mehta } 619e2cb1decSSalil Mehta 620e2cb1decSSalil Mehta static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 621e2cb1decSSalil Mehta { 622e2cb1decSSalil Mehta struct hclgevf_rss_tc_mode_cmd *req; 623e2cb1decSSalil Mehta u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 624e2cb1decSSalil Mehta u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 625e2cb1decSSalil Mehta u16 tc_size[HCLGEVF_MAX_TC_NUM]; 626e2cb1decSSalil Mehta struct hclgevf_desc desc; 627e2cb1decSSalil Mehta u16 roundup_size; 628e2cb1decSSalil Mehta int status; 629ebaf1908SWeihang Li unsigned int i; 630e2cb1decSSalil Mehta 631e2cb1decSSalil Mehta req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 632e2cb1decSSalil Mehta 633e2cb1decSSalil Mehta roundup_size = roundup_pow_of_two(rss_size); 634e2cb1decSSalil Mehta roundup_size = ilog2(roundup_size); 635e2cb1decSSalil Mehta 636e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 637e2cb1decSSalil Mehta tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 638e2cb1decSSalil Mehta tc_size[i] = roundup_size; 639e2cb1decSSalil Mehta tc_offset[i] = rss_size * i; 640e2cb1decSSalil Mehta } 641e2cb1decSSalil Mehta 642e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 643e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 644e4e87715SPeng Li hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 645e2cb1decSSalil Mehta (tc_valid[i] & 0x1)); 646e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 647e2cb1decSSalil Mehta HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 648e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 649e2cb1decSSalil Mehta HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 650e2cb1decSSalil Mehta } 651e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 652e2cb1decSSalil Mehta if (status) 653e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 654e2cb1decSSalil Mehta "VF failed(=%d) to set rss tc mode\n", status); 655e2cb1decSSalil Mehta 656e2cb1decSSalil Mehta return status; 657e2cb1decSSalil Mehta } 658e2cb1decSSalil Mehta 659a638b1d8SJian Shen /* for revision 0x20, vf shared the same rss config with pf */ 660a638b1d8SJian Shen static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 661a638b1d8SJian Shen { 662a638b1d8SJian Shen #define HCLGEVF_RSS_MBX_RESP_LEN 8 663a638b1d8SJian Shen 664a638b1d8SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 665a638b1d8SJian Shen u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 666a638b1d8SJian Shen u16 msg_num, hash_key_index; 667a638b1d8SJian Shen u8 index; 668a638b1d8SJian Shen int ret; 669a638b1d8SJian Shen 670a638b1d8SJian Shen msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 671a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN; 672a638b1d8SJian Shen for (index = 0; index < msg_num; index++) { 673a638b1d8SJian Shen ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_RSS_KEY, 0, 674a638b1d8SJian Shen &index, sizeof(index), 675a638b1d8SJian Shen true, resp_msg, 676a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN); 677a638b1d8SJian Shen if (ret) { 678a638b1d8SJian Shen dev_err(&hdev->pdev->dev, 679a638b1d8SJian Shen "VF get rss hash key from PF failed, ret=%d", 680a638b1d8SJian Shen ret); 681a638b1d8SJian Shen return ret; 682a638b1d8SJian Shen } 683a638b1d8SJian Shen 684a638b1d8SJian Shen hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 685a638b1d8SJian Shen if (index == msg_num - 1) 686a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 687a638b1d8SJian Shen &resp_msg[0], 688a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE - hash_key_index); 689a638b1d8SJian Shen else 690a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 691a638b1d8SJian Shen &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 692a638b1d8SJian Shen } 693a638b1d8SJian Shen 694a638b1d8SJian Shen return 0; 695a638b1d8SJian Shen } 696a638b1d8SJian Shen 697e2cb1decSSalil Mehta static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 698e2cb1decSSalil Mehta u8 *hfunc) 699e2cb1decSSalil Mehta { 700e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 701e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 702a638b1d8SJian Shen int i, ret; 703e2cb1decSSalil Mehta 704374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 705374ad291SJian Shen /* Get hash algorithm */ 706374ad291SJian Shen if (hfunc) { 707374ad291SJian Shen switch (rss_cfg->hash_algo) { 708374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 709374ad291SJian Shen *hfunc = ETH_RSS_HASH_TOP; 710374ad291SJian Shen break; 711374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 712374ad291SJian Shen *hfunc = ETH_RSS_HASH_XOR; 713374ad291SJian Shen break; 714374ad291SJian Shen default: 715374ad291SJian Shen *hfunc = ETH_RSS_HASH_UNKNOWN; 716374ad291SJian Shen break; 717374ad291SJian Shen } 718374ad291SJian Shen } 719374ad291SJian Shen 720374ad291SJian Shen /* Get the RSS Key required by the user */ 721374ad291SJian Shen if (key) 722374ad291SJian Shen memcpy(key, rss_cfg->rss_hash_key, 723374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 724a638b1d8SJian Shen } else { 725a638b1d8SJian Shen if (hfunc) 726a638b1d8SJian Shen *hfunc = ETH_RSS_HASH_TOP; 727a638b1d8SJian Shen if (key) { 728a638b1d8SJian Shen ret = hclgevf_get_rss_hash_key(hdev); 729a638b1d8SJian Shen if (ret) 730a638b1d8SJian Shen return ret; 731a638b1d8SJian Shen memcpy(key, rss_cfg->rss_hash_key, 732a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE); 733a638b1d8SJian Shen } 734374ad291SJian Shen } 735374ad291SJian Shen 736e2cb1decSSalil Mehta if (indir) 737e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 738e2cb1decSSalil Mehta indir[i] = rss_cfg->rss_indirection_tbl[i]; 739e2cb1decSSalil Mehta 740374ad291SJian Shen return 0; 741e2cb1decSSalil Mehta } 742e2cb1decSSalil Mehta 743e2cb1decSSalil Mehta static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 744e2cb1decSSalil Mehta const u8 *key, const u8 hfunc) 745e2cb1decSSalil Mehta { 746e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 747e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 748374ad291SJian Shen int ret, i; 749374ad291SJian Shen 750374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 751374ad291SJian Shen /* Set the RSS Hash Key if specififed by the user */ 752374ad291SJian Shen if (key) { 753374ad291SJian Shen switch (hfunc) { 754374ad291SJian Shen case ETH_RSS_HASH_TOP: 755374ad291SJian Shen rss_cfg->hash_algo = 756374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 757374ad291SJian Shen break; 758374ad291SJian Shen case ETH_RSS_HASH_XOR: 759374ad291SJian Shen rss_cfg->hash_algo = 760374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_SIMPLE; 761374ad291SJian Shen break; 762374ad291SJian Shen case ETH_RSS_HASH_NO_CHANGE: 763374ad291SJian Shen break; 764374ad291SJian Shen default: 765374ad291SJian Shen return -EINVAL; 766374ad291SJian Shen } 767374ad291SJian Shen 768374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 769374ad291SJian Shen key); 770374ad291SJian Shen if (ret) 771374ad291SJian Shen return ret; 772374ad291SJian Shen 773374ad291SJian Shen /* Update the shadow RSS key with user specified qids */ 774374ad291SJian Shen memcpy(rss_cfg->rss_hash_key, key, 775374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 776374ad291SJian Shen } 777374ad291SJian Shen } 778e2cb1decSSalil Mehta 779e2cb1decSSalil Mehta /* update the shadow RSS table with user specified qids */ 780e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 781e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = indir[i]; 782e2cb1decSSalil Mehta 783e2cb1decSSalil Mehta /* update the hardware */ 784e2cb1decSSalil Mehta return hclgevf_set_rss_indir_table(hdev); 785e2cb1decSSalil Mehta } 786e2cb1decSSalil Mehta 787d97b3072SJian Shen static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 788d97b3072SJian Shen { 789d97b3072SJian Shen u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 790d97b3072SJian Shen 791d97b3072SJian Shen if (nfc->data & RXH_L4_B_2_3) 792d97b3072SJian Shen hash_sets |= HCLGEVF_D_PORT_BIT; 793d97b3072SJian Shen else 794d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_PORT_BIT; 795d97b3072SJian Shen 796d97b3072SJian Shen if (nfc->data & RXH_IP_SRC) 797d97b3072SJian Shen hash_sets |= HCLGEVF_S_IP_BIT; 798d97b3072SJian Shen else 799d97b3072SJian Shen hash_sets &= ~HCLGEVF_S_IP_BIT; 800d97b3072SJian Shen 801d97b3072SJian Shen if (nfc->data & RXH_IP_DST) 802d97b3072SJian Shen hash_sets |= HCLGEVF_D_IP_BIT; 803d97b3072SJian Shen else 804d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_IP_BIT; 805d97b3072SJian Shen 806d97b3072SJian Shen if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 807d97b3072SJian Shen hash_sets |= HCLGEVF_V_TAG_BIT; 808d97b3072SJian Shen 809d97b3072SJian Shen return hash_sets; 810d97b3072SJian Shen } 811d97b3072SJian Shen 812d97b3072SJian Shen static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 813d97b3072SJian Shen struct ethtool_rxnfc *nfc) 814d97b3072SJian Shen { 815d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 816d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 817d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 818d97b3072SJian Shen struct hclgevf_desc desc; 819d97b3072SJian Shen u8 tuple_sets; 820d97b3072SJian Shen int ret; 821d97b3072SJian Shen 822d97b3072SJian Shen if (handle->pdev->revision == 0x20) 823d97b3072SJian Shen return -EOPNOTSUPP; 824d97b3072SJian Shen 825d97b3072SJian Shen if (nfc->data & 826d97b3072SJian Shen ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 827d97b3072SJian Shen return -EINVAL; 828d97b3072SJian Shen 829d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 830d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 831d97b3072SJian Shen 832d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 833d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 834d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 835d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 836d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 837d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 838d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 839d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 840d97b3072SJian Shen 841d97b3072SJian Shen tuple_sets = hclgevf_get_rss_hash_bits(nfc); 842d97b3072SJian Shen switch (nfc->flow_type) { 843d97b3072SJian Shen case TCP_V4_FLOW: 844d97b3072SJian Shen req->ipv4_tcp_en = tuple_sets; 845d97b3072SJian Shen break; 846d97b3072SJian Shen case TCP_V6_FLOW: 847d97b3072SJian Shen req->ipv6_tcp_en = tuple_sets; 848d97b3072SJian Shen break; 849d97b3072SJian Shen case UDP_V4_FLOW: 850d97b3072SJian Shen req->ipv4_udp_en = tuple_sets; 851d97b3072SJian Shen break; 852d97b3072SJian Shen case UDP_V6_FLOW: 853d97b3072SJian Shen req->ipv6_udp_en = tuple_sets; 854d97b3072SJian Shen break; 855d97b3072SJian Shen case SCTP_V4_FLOW: 856d97b3072SJian Shen req->ipv4_sctp_en = tuple_sets; 857d97b3072SJian Shen break; 858d97b3072SJian Shen case SCTP_V6_FLOW: 859d97b3072SJian Shen if ((nfc->data & RXH_L4_B_0_1) || 860d97b3072SJian Shen (nfc->data & RXH_L4_B_2_3)) 861d97b3072SJian Shen return -EINVAL; 862d97b3072SJian Shen 863d97b3072SJian Shen req->ipv6_sctp_en = tuple_sets; 864d97b3072SJian Shen break; 865d97b3072SJian Shen case IPV4_FLOW: 866d97b3072SJian Shen req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 867d97b3072SJian Shen break; 868d97b3072SJian Shen case IPV6_FLOW: 869d97b3072SJian Shen req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 870d97b3072SJian Shen break; 871d97b3072SJian Shen default: 872d97b3072SJian Shen return -EINVAL; 873d97b3072SJian Shen } 874d97b3072SJian Shen 875d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 876d97b3072SJian Shen if (ret) { 877d97b3072SJian Shen dev_err(&hdev->pdev->dev, 878d97b3072SJian Shen "Set rss tuple fail, status = %d\n", ret); 879d97b3072SJian Shen return ret; 880d97b3072SJian Shen } 881d97b3072SJian Shen 882d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 883d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 884d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 885d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 886d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 887d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 888d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 889d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 890d97b3072SJian Shen return 0; 891d97b3072SJian Shen } 892d97b3072SJian Shen 893d97b3072SJian Shen static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 894d97b3072SJian Shen struct ethtool_rxnfc *nfc) 895d97b3072SJian Shen { 896d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 897d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 898d97b3072SJian Shen u8 tuple_sets; 899d97b3072SJian Shen 900d97b3072SJian Shen if (handle->pdev->revision == 0x20) 901d97b3072SJian Shen return -EOPNOTSUPP; 902d97b3072SJian Shen 903d97b3072SJian Shen nfc->data = 0; 904d97b3072SJian Shen 905d97b3072SJian Shen switch (nfc->flow_type) { 906d97b3072SJian Shen case TCP_V4_FLOW: 907d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 908d97b3072SJian Shen break; 909d97b3072SJian Shen case UDP_V4_FLOW: 910d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 911d97b3072SJian Shen break; 912d97b3072SJian Shen case TCP_V6_FLOW: 913d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 914d97b3072SJian Shen break; 915d97b3072SJian Shen case UDP_V6_FLOW: 916d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 917d97b3072SJian Shen break; 918d97b3072SJian Shen case SCTP_V4_FLOW: 919d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 920d97b3072SJian Shen break; 921d97b3072SJian Shen case SCTP_V6_FLOW: 922d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 923d97b3072SJian Shen break; 924d97b3072SJian Shen case IPV4_FLOW: 925d97b3072SJian Shen case IPV6_FLOW: 926d97b3072SJian Shen tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 927d97b3072SJian Shen break; 928d97b3072SJian Shen default: 929d97b3072SJian Shen return -EINVAL; 930d97b3072SJian Shen } 931d97b3072SJian Shen 932d97b3072SJian Shen if (!tuple_sets) 933d97b3072SJian Shen return 0; 934d97b3072SJian Shen 935d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_PORT_BIT) 936d97b3072SJian Shen nfc->data |= RXH_L4_B_2_3; 937d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_PORT_BIT) 938d97b3072SJian Shen nfc->data |= RXH_L4_B_0_1; 939d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_IP_BIT) 940d97b3072SJian Shen nfc->data |= RXH_IP_DST; 941d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_IP_BIT) 942d97b3072SJian Shen nfc->data |= RXH_IP_SRC; 943d97b3072SJian Shen 944d97b3072SJian Shen return 0; 945d97b3072SJian Shen } 946d97b3072SJian Shen 947d97b3072SJian Shen static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 948d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg) 949d97b3072SJian Shen { 950d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 951d97b3072SJian Shen struct hclgevf_desc desc; 952d97b3072SJian Shen int ret; 953d97b3072SJian Shen 954d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 955d97b3072SJian Shen 956d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 957d97b3072SJian Shen 958d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 959d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 960d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 961d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 962d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 963d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 964d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 965d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 966d97b3072SJian Shen 967d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 968d97b3072SJian Shen if (ret) 969d97b3072SJian Shen dev_err(&hdev->pdev->dev, 970d97b3072SJian Shen "Configure rss input fail, status = %d\n", ret); 971d97b3072SJian Shen return ret; 972d97b3072SJian Shen } 973d97b3072SJian Shen 974e2cb1decSSalil Mehta static int hclgevf_get_tc_size(struct hnae3_handle *handle) 975e2cb1decSSalil Mehta { 976e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 977e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 978e2cb1decSSalil Mehta 979e2cb1decSSalil Mehta return rss_cfg->rss_size; 980e2cb1decSSalil Mehta } 981e2cb1decSSalil Mehta 982e2cb1decSSalil Mehta static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 983b204bc74SPeng Li int vector_id, 984e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 985e2cb1decSSalil Mehta { 986e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 987e2cb1decSSalil Mehta struct hnae3_ring_chain_node *node; 988e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 989e2cb1decSSalil Mehta struct hclgevf_desc desc; 990b204bc74SPeng Li int i = 0; 991e2cb1decSSalil Mehta int status; 992e2cb1decSSalil Mehta u8 type; 993e2cb1decSSalil Mehta 994e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 995e2cb1decSSalil Mehta 996e2cb1decSSalil Mehta for (node = ring_chain; node; node = node->next) { 9975d02a58dSYunsheng Lin int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 9985d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 9995d02a58dSYunsheng Lin 10005d02a58dSYunsheng Lin if (i == 0) { 10015d02a58dSYunsheng Lin hclgevf_cmd_setup_basic_desc(&desc, 10025d02a58dSYunsheng Lin HCLGEVF_OPC_MBX_VF_TO_PF, 10035d02a58dSYunsheng Lin false); 10045d02a58dSYunsheng Lin type = en ? 10055d02a58dSYunsheng Lin HCLGE_MBX_MAP_RING_TO_VECTOR : 10065d02a58dSYunsheng Lin HCLGE_MBX_UNMAP_RING_TO_VECTOR; 10075d02a58dSYunsheng Lin req->msg[0] = type; 10085d02a58dSYunsheng Lin req->msg[1] = vector_id; 10095d02a58dSYunsheng Lin } 10105d02a58dSYunsheng Lin 10115d02a58dSYunsheng Lin req->msg[idx_offset] = 1012e4e87715SPeng Li hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 10135d02a58dSYunsheng Lin req->msg[idx_offset + 1] = node->tqp_index; 1014e4e87715SPeng Li req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 101579eee410SFuyun Liang HNAE3_RING_GL_IDX_M, 101679eee410SFuyun Liang HNAE3_RING_GL_IDX_S); 101779eee410SFuyun Liang 10185d02a58dSYunsheng Lin i++; 10195d02a58dSYunsheng Lin if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 10205d02a58dSYunsheng Lin HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 10215d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 10225d02a58dSYunsheng Lin !node->next) { 1023e2cb1decSSalil Mehta req->msg[2] = i; 1024e2cb1decSSalil Mehta 1025e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1026e2cb1decSSalil Mehta if (status) { 1027e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1028e2cb1decSSalil Mehta "Map TQP fail, status is %d.\n", 1029e2cb1decSSalil Mehta status); 1030e2cb1decSSalil Mehta return status; 1031e2cb1decSSalil Mehta } 1032e2cb1decSSalil Mehta i = 0; 1033e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 1034e2cb1decSSalil Mehta HCLGEVF_OPC_MBX_VF_TO_PF, 1035e2cb1decSSalil Mehta false); 1036e2cb1decSSalil Mehta req->msg[0] = type; 1037e2cb1decSSalil Mehta req->msg[1] = vector_id; 1038e2cb1decSSalil Mehta } 1039e2cb1decSSalil Mehta } 1040e2cb1decSSalil Mehta 1041e2cb1decSSalil Mehta return 0; 1042e2cb1decSSalil Mehta } 1043e2cb1decSSalil Mehta 1044e2cb1decSSalil Mehta static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1045e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1046e2cb1decSSalil Mehta { 1047b204bc74SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1048b204bc74SPeng Li int vector_id; 1049b204bc74SPeng Li 1050b204bc74SPeng Li vector_id = hclgevf_get_vector_index(hdev, vector); 1051b204bc74SPeng Li if (vector_id < 0) { 1052b204bc74SPeng Li dev_err(&handle->pdev->dev, 1053b204bc74SPeng Li "Get vector index fail. ret =%d\n", vector_id); 1054b204bc74SPeng Li return vector_id; 1055b204bc74SPeng Li } 1056b204bc74SPeng Li 1057b204bc74SPeng Li return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1058e2cb1decSSalil Mehta } 1059e2cb1decSSalil Mehta 1060e2cb1decSSalil Mehta static int hclgevf_unmap_ring_from_vector( 1061e2cb1decSSalil Mehta struct hnae3_handle *handle, 1062e2cb1decSSalil Mehta int vector, 1063e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1064e2cb1decSSalil Mehta { 1065e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1066e2cb1decSSalil Mehta int ret, vector_id; 1067e2cb1decSSalil Mehta 1068dea846e8SHuazhong Tan if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1069dea846e8SHuazhong Tan return 0; 1070dea846e8SHuazhong Tan 1071e2cb1decSSalil Mehta vector_id = hclgevf_get_vector_index(hdev, vector); 1072e2cb1decSSalil Mehta if (vector_id < 0) { 1073e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1074e2cb1decSSalil Mehta "Get vector index fail. ret =%d\n", vector_id); 1075e2cb1decSSalil Mehta return vector_id; 1076e2cb1decSSalil Mehta } 1077e2cb1decSSalil Mehta 1078b204bc74SPeng Li ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 10790d3e6631SYunsheng Lin if (ret) 1080e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1081e2cb1decSSalil Mehta "Unmap ring from vector fail. vector=%d, ret =%d\n", 1082e2cb1decSSalil Mehta vector_id, 1083e2cb1decSSalil Mehta ret); 10840d3e6631SYunsheng Lin 1085e2cb1decSSalil Mehta return ret; 1086e2cb1decSSalil Mehta } 1087e2cb1decSSalil Mehta 10880d3e6631SYunsheng Lin static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 10890d3e6631SYunsheng Lin { 10900d3e6631SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 109103718db9SYunsheng Lin int vector_id; 10920d3e6631SYunsheng Lin 109303718db9SYunsheng Lin vector_id = hclgevf_get_vector_index(hdev, vector); 109403718db9SYunsheng Lin if (vector_id < 0) { 109503718db9SYunsheng Lin dev_err(&handle->pdev->dev, 109603718db9SYunsheng Lin "hclgevf_put_vector get vector index fail. ret =%d\n", 109703718db9SYunsheng Lin vector_id); 109803718db9SYunsheng Lin return vector_id; 109903718db9SYunsheng Lin } 110003718db9SYunsheng Lin 110103718db9SYunsheng Lin hclgevf_free_vector(hdev, vector_id); 1102e2cb1decSSalil Mehta 1103e2cb1decSSalil Mehta return 0; 1104e2cb1decSSalil Mehta } 1105e2cb1decSSalil Mehta 11063b75c3dfSPeng Li static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1107f01f5559SJian Shen bool en_bc_pmc) 1108e2cb1decSSalil Mehta { 1109e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 1110e2cb1decSSalil Mehta struct hclgevf_desc desc; 1111f01f5559SJian Shen int ret; 1112e2cb1decSSalil Mehta 1113e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1114e2cb1decSSalil Mehta 1115e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 1116e2cb1decSSalil Mehta req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 1117f01f5559SJian Shen req->msg[1] = en_bc_pmc ? 1 : 0; 1118e2cb1decSSalil Mehta 1119f01f5559SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1120f01f5559SJian Shen if (ret) 1121e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1122f01f5559SJian Shen "Set promisc mode fail, status is %d.\n", ret); 1123e2cb1decSSalil Mehta 1124f01f5559SJian Shen return ret; 1125e2cb1decSSalil Mehta } 1126e2cb1decSSalil Mehta 1127f01f5559SJian Shen static int hclgevf_set_promisc_mode(struct hclgevf_dev *hdev, bool en_bc_pmc) 1128e2cb1decSSalil Mehta { 1129f01f5559SJian Shen return hclgevf_cmd_set_promisc_mode(hdev, en_bc_pmc); 1130e2cb1decSSalil Mehta } 1131e2cb1decSSalil Mehta 1132ebaf1908SWeihang Li static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, unsigned int tqp_id, 1133e2cb1decSSalil Mehta int stream_id, bool enable) 1134e2cb1decSSalil Mehta { 1135e2cb1decSSalil Mehta struct hclgevf_cfg_com_tqp_queue_cmd *req; 1136e2cb1decSSalil Mehta struct hclgevf_desc desc; 1137e2cb1decSSalil Mehta int status; 1138e2cb1decSSalil Mehta 1139e2cb1decSSalil Mehta req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1140e2cb1decSSalil Mehta 1141e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1142e2cb1decSSalil Mehta false); 1143e2cb1decSSalil Mehta req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1144e2cb1decSSalil Mehta req->stream_id = cpu_to_le16(stream_id); 1145ebaf1908SWeihang Li if (enable) 1146ebaf1908SWeihang Li req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 1147e2cb1decSSalil Mehta 1148e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1149e2cb1decSSalil Mehta if (status) 1150e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1151e2cb1decSSalil Mehta "TQP enable fail, status =%d.\n", status); 1152e2cb1decSSalil Mehta 1153e2cb1decSSalil Mehta return status; 1154e2cb1decSSalil Mehta } 1155e2cb1decSSalil Mehta 1156e2cb1decSSalil Mehta static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1157e2cb1decSSalil Mehta { 1158b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1159e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 1160e2cb1decSSalil Mehta int i; 1161e2cb1decSSalil Mehta 1162b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 1163b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1164e2cb1decSSalil Mehta memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1165e2cb1decSSalil Mehta } 1166e2cb1decSSalil Mehta } 1167e2cb1decSSalil Mehta 1168e2cb1decSSalil Mehta static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1169e2cb1decSSalil Mehta { 1170e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1171e2cb1decSSalil Mehta 1172e2cb1decSSalil Mehta ether_addr_copy(p, hdev->hw.mac.mac_addr); 1173e2cb1decSSalil Mehta } 1174e2cb1decSSalil Mehta 117559098055SFuyun Liang static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 117659098055SFuyun Liang bool is_first) 1177e2cb1decSSalil Mehta { 1178e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1179e2cb1decSSalil Mehta u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1180e2cb1decSSalil Mehta u8 *new_mac_addr = (u8 *)p; 1181e2cb1decSSalil Mehta u8 msg_data[ETH_ALEN * 2]; 118259098055SFuyun Liang u16 subcode; 1183e2cb1decSSalil Mehta int status; 1184e2cb1decSSalil Mehta 1185e2cb1decSSalil Mehta ether_addr_copy(msg_data, new_mac_addr); 1186e2cb1decSSalil Mehta ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 1187e2cb1decSSalil Mehta 118859098055SFuyun Liang subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 118959098055SFuyun Liang HCLGE_MBX_MAC_VLAN_UC_MODIFY; 119059098055SFuyun Liang 1191e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 119263cbf7a9SYufeng Mo subcode, msg_data, sizeof(msg_data), 11932097fdefSJian Shen true, NULL, 0); 1194e2cb1decSSalil Mehta if (!status) 1195e2cb1decSSalil Mehta ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1196e2cb1decSSalil Mehta 1197e2cb1decSSalil Mehta return status; 1198e2cb1decSSalil Mehta } 1199e2cb1decSSalil Mehta 1200e2cb1decSSalil Mehta static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1201e2cb1decSSalil Mehta const unsigned char *addr) 1202e2cb1decSSalil Mehta { 1203e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1204e2cb1decSSalil Mehta 1205e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1206e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_ADD, 1207e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1208e2cb1decSSalil Mehta } 1209e2cb1decSSalil Mehta 1210e2cb1decSSalil Mehta static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1211e2cb1decSSalil Mehta const unsigned char *addr) 1212e2cb1decSSalil Mehta { 1213e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1214e2cb1decSSalil Mehta 1215e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1216e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1217e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1218e2cb1decSSalil Mehta } 1219e2cb1decSSalil Mehta 1220e2cb1decSSalil Mehta static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1221e2cb1decSSalil Mehta const unsigned char *addr) 1222e2cb1decSSalil Mehta { 1223e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1224e2cb1decSSalil Mehta 1225e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1226e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_ADD, 1227e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1228e2cb1decSSalil Mehta } 1229e2cb1decSSalil Mehta 1230e2cb1decSSalil Mehta static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1231e2cb1decSSalil Mehta const unsigned char *addr) 1232e2cb1decSSalil Mehta { 1233e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1234e2cb1decSSalil Mehta 1235e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1236e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1237e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1238e2cb1decSSalil Mehta } 1239e2cb1decSSalil Mehta 1240e2cb1decSSalil Mehta static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1241e2cb1decSSalil Mehta __be16 proto, u16 vlan_id, 1242e2cb1decSSalil Mehta bool is_kill) 1243e2cb1decSSalil Mehta { 1244e2cb1decSSalil Mehta #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1245e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1246e2cb1decSSalil Mehta u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1247e2cb1decSSalil Mehta 1248b37ce587SYufeng Mo if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1249e2cb1decSSalil Mehta return -EINVAL; 1250e2cb1decSSalil Mehta 1251e2cb1decSSalil Mehta if (proto != htons(ETH_P_8021Q)) 1252e2cb1decSSalil Mehta return -EPROTONOSUPPORT; 1253e2cb1decSSalil Mehta 1254e2cb1decSSalil Mehta msg_data[0] = is_kill; 1255e2cb1decSSalil Mehta memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1256e2cb1decSSalil Mehta memcpy(&msg_data[3], &proto, sizeof(proto)); 1257e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1258e2cb1decSSalil Mehta HCLGE_MBX_VLAN_FILTER, msg_data, 1259e2cb1decSSalil Mehta HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 1260e2cb1decSSalil Mehta } 1261e2cb1decSSalil Mehta 1262b2641e2aSYunsheng Lin static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1263b2641e2aSYunsheng Lin { 1264b2641e2aSYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1265b2641e2aSYunsheng Lin u8 msg_data; 1266b2641e2aSYunsheng Lin 1267b2641e2aSYunsheng Lin msg_data = enable ? 1 : 0; 1268b2641e2aSYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1269b2641e2aSYunsheng Lin HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1270b2641e2aSYunsheng Lin 1, false, NULL, 0); 1271b2641e2aSYunsheng Lin } 1272b2641e2aSYunsheng Lin 12737fa6be4fSHuazhong Tan static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1274e2cb1decSSalil Mehta { 1275e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1276e2cb1decSSalil Mehta u8 msg_data[2]; 12771a426f8bSPeng Li int ret; 1278e2cb1decSSalil Mehta 127963cbf7a9SYufeng Mo memcpy(msg_data, &queue_id, sizeof(queue_id)); 1280e2cb1decSSalil Mehta 12811a426f8bSPeng Li /* disable vf queue before send queue reset msg to PF */ 12821a426f8bSPeng Li ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 12831a426f8bSPeng Li if (ret) 12847fa6be4fSHuazhong Tan return ret; 12851a426f8bSPeng Li 12867fa6be4fSHuazhong Tan return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 128763cbf7a9SYufeng Mo sizeof(msg_data), true, NULL, 0); 1288e2cb1decSSalil Mehta } 1289e2cb1decSSalil Mehta 1290818f1675SYunsheng Lin static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1291818f1675SYunsheng Lin { 1292818f1675SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1293818f1675SYunsheng Lin 1294818f1675SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu, 1295818f1675SYunsheng Lin sizeof(new_mtu), true, NULL, 0); 1296818f1675SYunsheng Lin } 1297818f1675SYunsheng Lin 12986988eb2aSSalil Mehta static int hclgevf_notify_client(struct hclgevf_dev *hdev, 12996988eb2aSSalil Mehta enum hnae3_reset_notify_type type) 13006988eb2aSSalil Mehta { 13016988eb2aSSalil Mehta struct hnae3_client *client = hdev->nic_client; 13026988eb2aSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 13036a5f6fa3SHuazhong Tan int ret; 13046988eb2aSSalil Mehta 130525d1817cSHuazhong Tan if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 130625d1817cSHuazhong Tan !client) 130725d1817cSHuazhong Tan return 0; 130825d1817cSHuazhong Tan 13096988eb2aSSalil Mehta if (!client->ops->reset_notify) 13106988eb2aSSalil Mehta return -EOPNOTSUPP; 13116988eb2aSSalil Mehta 13126a5f6fa3SHuazhong Tan ret = client->ops->reset_notify(handle, type); 13136a5f6fa3SHuazhong Tan if (ret) 13146a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 13156a5f6fa3SHuazhong Tan type, ret); 13166a5f6fa3SHuazhong Tan 13176a5f6fa3SHuazhong Tan return ret; 13186988eb2aSSalil Mehta } 13196988eb2aSSalil Mehta 13206ff3cf07SHuazhong Tan static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 13216ff3cf07SHuazhong Tan { 13226ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 13236ff3cf07SHuazhong Tan 13246ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DONE, &hdev->flr_state); 13256ff3cf07SHuazhong Tan } 13266ff3cf07SHuazhong Tan 13276ff3cf07SHuazhong Tan static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev, 13286ff3cf07SHuazhong Tan unsigned long delay_us, 13296ff3cf07SHuazhong Tan unsigned long wait_cnt) 13306ff3cf07SHuazhong Tan { 13316ff3cf07SHuazhong Tan unsigned long cnt = 0; 13326ff3cf07SHuazhong Tan 13336ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) && 13346ff3cf07SHuazhong Tan cnt++ < wait_cnt) 13356ff3cf07SHuazhong Tan usleep_range(delay_us, delay_us * 2); 13366ff3cf07SHuazhong Tan 13376ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) { 13386ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 13396ff3cf07SHuazhong Tan "flr wait timeout\n"); 13406ff3cf07SHuazhong Tan return -ETIMEDOUT; 13416ff3cf07SHuazhong Tan } 13426ff3cf07SHuazhong Tan 13436ff3cf07SHuazhong Tan return 0; 13446ff3cf07SHuazhong Tan } 13456ff3cf07SHuazhong Tan 13466988eb2aSSalil Mehta static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 13476988eb2aSSalil Mehta { 1348aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_US 20000 1349aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_CNT 2000 1350aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1351aa5c4f17SHuazhong Tan (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1352aa5c4f17SHuazhong Tan 1353aa5c4f17SHuazhong Tan u32 val; 1354aa5c4f17SHuazhong Tan int ret; 13556988eb2aSSalil Mehta 13566988eb2aSSalil Mehta /* wait to check the hardware reset completion status */ 1357aa5c4f17SHuazhong Tan val = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1358aa5c4f17SHuazhong Tan dev_info(&hdev->pdev->dev, "checking vf resetting status: %x\n", val); 1359aa5c4f17SHuazhong Tan 13606ff3cf07SHuazhong Tan if (hdev->reset_type == HNAE3_FLR_RESET) 13616ff3cf07SHuazhong Tan return hclgevf_flr_poll_timeout(hdev, 13626ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_US, 13636ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_CNT); 13646ff3cf07SHuazhong Tan 1365aa5c4f17SHuazhong Tan ret = readl_poll_timeout(hdev->hw.io_base + HCLGEVF_RST_ING, val, 1366aa5c4f17SHuazhong Tan !(val & HCLGEVF_RST_ING_BITS), 1367aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_US, 1368aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 13696988eb2aSSalil Mehta 13706988eb2aSSalil Mehta /* hardware completion status should be available by this time */ 1371aa5c4f17SHuazhong Tan if (ret) { 1372aa5c4f17SHuazhong Tan dev_err(&hdev->pdev->dev, 13736988eb2aSSalil Mehta "could'nt get reset done status from h/w, timeout!\n"); 1374aa5c4f17SHuazhong Tan return ret; 13756988eb2aSSalil Mehta } 13766988eb2aSSalil Mehta 13776988eb2aSSalil Mehta /* we will wait a bit more to let reset of the stack to complete. This 13786988eb2aSSalil Mehta * might happen in case reset assertion was made by PF. Yes, this also 13796988eb2aSSalil Mehta * means we might end up waiting bit more even for VF reset. 13806988eb2aSSalil Mehta */ 13816988eb2aSSalil Mehta msleep(5000); 13826988eb2aSSalil Mehta 13836988eb2aSSalil Mehta return 0; 13846988eb2aSSalil Mehta } 13856988eb2aSSalil Mehta 13866988eb2aSSalil Mehta static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 13876988eb2aSSalil Mehta { 13887a01c897SSalil Mehta int ret; 13897a01c897SSalil Mehta 13906988eb2aSSalil Mehta /* uninitialize the nic client */ 13916a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 13926a5f6fa3SHuazhong Tan if (ret) 13936a5f6fa3SHuazhong Tan return ret; 13946988eb2aSSalil Mehta 13957a01c897SSalil Mehta /* re-initialize the hclge device */ 13969c6f7085SHuazhong Tan ret = hclgevf_reset_hdev(hdev); 13977a01c897SSalil Mehta if (ret) { 13987a01c897SSalil Mehta dev_err(&hdev->pdev->dev, 13997a01c897SSalil Mehta "hclge device re-init failed, VF is disabled!\n"); 14007a01c897SSalil Mehta return ret; 14017a01c897SSalil Mehta } 14026988eb2aSSalil Mehta 14036988eb2aSSalil Mehta /* bring up the nic client again */ 14046a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 14056a5f6fa3SHuazhong Tan if (ret) 14066a5f6fa3SHuazhong Tan return ret; 14076988eb2aSSalil Mehta 14081f609492SYunsheng Lin return hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT); 14096988eb2aSSalil Mehta } 14106988eb2aSSalil Mehta 1411dea846e8SHuazhong Tan static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1412dea846e8SHuazhong Tan { 1413ada13ee3SHuazhong Tan #define HCLGEVF_RESET_SYNC_TIME 100 1414ada13ee3SHuazhong Tan 1415dea846e8SHuazhong Tan int ret = 0; 1416dea846e8SHuazhong Tan 1417dea846e8SHuazhong Tan switch (hdev->reset_type) { 1418dea846e8SHuazhong Tan case HNAE3_VF_FUNC_RESET: 1419dea846e8SHuazhong Tan ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1420dea846e8SHuazhong Tan 0, true, NULL, sizeof(u8)); 1421c88a6e7dSHuazhong Tan hdev->rst_stats.vf_func_rst_cnt++; 1422dea846e8SHuazhong Tan break; 14236ff3cf07SHuazhong Tan case HNAE3_FLR_RESET: 14246ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1425c88a6e7dSHuazhong Tan hdev->rst_stats.flr_rst_cnt++; 14266ff3cf07SHuazhong Tan break; 1427dea846e8SHuazhong Tan default: 1428dea846e8SHuazhong Tan break; 1429dea846e8SHuazhong Tan } 1430dea846e8SHuazhong Tan 1431ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1432ada13ee3SHuazhong Tan /* inform hardware that preparatory work is done */ 1433ada13ee3SHuazhong Tan msleep(HCLGEVF_RESET_SYNC_TIME); 1434ada13ee3SHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 1435ada13ee3SHuazhong Tan HCLGEVF_NIC_CMQ_ENABLE); 1436dea846e8SHuazhong Tan dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1437dea846e8SHuazhong Tan hdev->reset_type, ret); 1438dea846e8SHuazhong Tan 1439dea846e8SHuazhong Tan return ret; 1440dea846e8SHuazhong Tan } 1441dea846e8SHuazhong Tan 14426988eb2aSSalil Mehta static int hclgevf_reset(struct hclgevf_dev *hdev) 14436988eb2aSSalil Mehta { 1444dea846e8SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 14456988eb2aSSalil Mehta int ret; 14466988eb2aSSalil Mehta 1447dea846e8SHuazhong Tan /* Initialize ae_dev reset status as well, in case enet layer wants to 1448dea846e8SHuazhong Tan * know if device is undergoing reset 1449dea846e8SHuazhong Tan */ 1450dea846e8SHuazhong Tan ae_dev->reset_type = hdev->reset_type; 1451c88a6e7dSHuazhong Tan hdev->rst_stats.rst_cnt++; 14526988eb2aSSalil Mehta rtnl_lock(); 14536988eb2aSSalil Mehta 14546988eb2aSSalil Mehta /* bring down the nic to stop any ongoing TX/RX */ 14556a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 14566a5f6fa3SHuazhong Tan if (ret) 14576a5f6fa3SHuazhong Tan goto err_reset_lock; 14586988eb2aSSalil Mehta 145929118ab9SHuazhong Tan rtnl_unlock(); 146029118ab9SHuazhong Tan 14616a5f6fa3SHuazhong Tan ret = hclgevf_reset_prepare_wait(hdev); 14626a5f6fa3SHuazhong Tan if (ret) 14636a5f6fa3SHuazhong Tan goto err_reset; 1464dea846e8SHuazhong Tan 14656988eb2aSSalil Mehta /* check if VF could successfully fetch the hardware reset completion 14666988eb2aSSalil Mehta * status from the hardware 14676988eb2aSSalil Mehta */ 14686988eb2aSSalil Mehta ret = hclgevf_reset_wait(hdev); 14696988eb2aSSalil Mehta if (ret) { 14706988eb2aSSalil Mehta /* can't do much in this situation, will disable VF */ 14716988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, 14726988eb2aSSalil Mehta "VF failed(=%d) to fetch H/W reset completion status\n", 14736988eb2aSSalil Mehta ret); 14746a5f6fa3SHuazhong Tan goto err_reset; 14756988eb2aSSalil Mehta } 14766988eb2aSSalil Mehta 1477c88a6e7dSHuazhong Tan hdev->rst_stats.hw_rst_done_cnt++; 1478c88a6e7dSHuazhong Tan 147929118ab9SHuazhong Tan rtnl_lock(); 148029118ab9SHuazhong Tan 14816988eb2aSSalil Mehta /* now, re-initialize the nic client and ae device*/ 14826988eb2aSSalil Mehta ret = hclgevf_reset_stack(hdev); 14836a5f6fa3SHuazhong Tan if (ret) { 14846988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 14856a5f6fa3SHuazhong Tan goto err_reset_lock; 14866a5f6fa3SHuazhong Tan } 14876988eb2aSSalil Mehta 14886988eb2aSSalil Mehta /* bring up the nic to enable TX/RX again */ 14896a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 14906a5f6fa3SHuazhong Tan if (ret) 14916a5f6fa3SHuazhong Tan goto err_reset_lock; 14926988eb2aSSalil Mehta 14936988eb2aSSalil Mehta rtnl_unlock(); 14946988eb2aSSalil Mehta 1495b644a8d4SHuazhong Tan hdev->last_reset_time = jiffies; 1496b644a8d4SHuazhong Tan ae_dev->reset_type = HNAE3_NONE_RESET; 1497c88a6e7dSHuazhong Tan hdev->rst_stats.rst_done_cnt++; 1498b644a8d4SHuazhong Tan 14996988eb2aSSalil Mehta return ret; 15006a5f6fa3SHuazhong Tan err_reset_lock: 15016a5f6fa3SHuazhong Tan rtnl_unlock(); 15026a5f6fa3SHuazhong Tan err_reset: 15036a5f6fa3SHuazhong Tan /* When VF reset failed, only the higher level reset asserted by PF 15046a5f6fa3SHuazhong Tan * can restore it, so re-initialize the command queue to receive 15056a5f6fa3SHuazhong Tan * this higher reset event. 15066a5f6fa3SHuazhong Tan */ 15076a5f6fa3SHuazhong Tan hclgevf_cmd_init(hdev); 15086a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "failed to reset VF\n"); 1509cf1f2129SHuazhong Tan if (hclgevf_is_reset_pending(hdev)) 1510cf1f2129SHuazhong Tan hclgevf_reset_task_schedule(hdev); 15116a5f6fa3SHuazhong Tan 15126a5f6fa3SHuazhong Tan return ret; 15136988eb2aSSalil Mehta } 15146988eb2aSSalil Mehta 1515720bd583SHuazhong Tan static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1516720bd583SHuazhong Tan unsigned long *addr) 1517720bd583SHuazhong Tan { 1518720bd583SHuazhong Tan enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1519720bd583SHuazhong Tan 1520dea846e8SHuazhong Tan /* return the highest priority reset level amongst all */ 1521b90fcc5bSHuazhong Tan if (test_bit(HNAE3_VF_RESET, addr)) { 1522b90fcc5bSHuazhong Tan rst_level = HNAE3_VF_RESET; 1523b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_RESET, addr); 1524b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1525b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1526b90fcc5bSHuazhong Tan } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1527dea846e8SHuazhong Tan rst_level = HNAE3_VF_FULL_RESET; 1528dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FULL_RESET, addr); 1529dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1530aa5c4f17SHuazhong Tan } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1531aa5c4f17SHuazhong Tan rst_level = HNAE3_VF_PF_FUNC_RESET; 1532aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1533aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1534dea846e8SHuazhong Tan } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1535dea846e8SHuazhong Tan rst_level = HNAE3_VF_FUNC_RESET; 1536dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 15376ff3cf07SHuazhong Tan } else if (test_bit(HNAE3_FLR_RESET, addr)) { 15386ff3cf07SHuazhong Tan rst_level = HNAE3_FLR_RESET; 15396ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_RESET, addr); 1540720bd583SHuazhong Tan } 1541720bd583SHuazhong Tan 1542720bd583SHuazhong Tan return rst_level; 1543720bd583SHuazhong Tan } 1544720bd583SHuazhong Tan 15456ae4e733SShiju Jose static void hclgevf_reset_event(struct pci_dev *pdev, 15466ae4e733SShiju Jose struct hnae3_handle *handle) 15476d4c3981SSalil Mehta { 15486ff3cf07SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 15496ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 15506d4c3981SSalil Mehta 15516d4c3981SSalil Mehta dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 15526d4c3981SSalil Mehta 15536ff3cf07SHuazhong Tan if (hdev->default_reset_request) 15540742ed7cSHuazhong Tan hdev->reset_level = 1555720bd583SHuazhong Tan hclgevf_get_reset_level(hdev, 1556720bd583SHuazhong Tan &hdev->default_reset_request); 1557720bd583SHuazhong Tan else 1558dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 15596d4c3981SSalil Mehta 1560436667d2SSalil Mehta /* reset of this VF requested */ 1561436667d2SSalil Mehta set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1562436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 15636d4c3981SSalil Mehta 15640742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 15656d4c3981SSalil Mehta } 15666d4c3981SSalil Mehta 1567720bd583SHuazhong Tan static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1568720bd583SHuazhong Tan enum hnae3_reset_type rst_type) 1569720bd583SHuazhong Tan { 1570720bd583SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1571720bd583SHuazhong Tan 1572720bd583SHuazhong Tan set_bit(rst_type, &hdev->default_reset_request); 1573720bd583SHuazhong Tan } 1574720bd583SHuazhong Tan 15756ff3cf07SHuazhong Tan static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 15766ff3cf07SHuazhong Tan { 15776ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_MS 100 15786ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_CNT 50 15796ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 15806ff3cf07SHuazhong Tan int cnt = 0; 15816ff3cf07SHuazhong Tan 15826ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 15836ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DONE, &hdev->flr_state); 15846ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request); 15856ff3cf07SHuazhong Tan hclgevf_reset_event(hdev->pdev, NULL); 15866ff3cf07SHuazhong Tan 15876ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) && 15886ff3cf07SHuazhong Tan cnt++ < HCLGEVF_FLR_WAIT_CNT) 15896ff3cf07SHuazhong Tan msleep(HCLGEVF_FLR_WAIT_MS); 15906ff3cf07SHuazhong Tan 15916ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state)) 15926ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 15936ff3cf07SHuazhong Tan "flr wait down timeout: %d\n", cnt); 15946ff3cf07SHuazhong Tan } 15956ff3cf07SHuazhong Tan 1596e2cb1decSSalil Mehta static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1597e2cb1decSSalil Mehta { 1598e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1599e2cb1decSSalil Mehta 1600e2cb1decSSalil Mehta return hdev->fw_version; 1601e2cb1decSSalil Mehta } 1602e2cb1decSSalil Mehta 1603e2cb1decSSalil Mehta static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1604e2cb1decSSalil Mehta { 1605e2cb1decSSalil Mehta struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1606e2cb1decSSalil Mehta 1607e2cb1decSSalil Mehta vector->vector_irq = pci_irq_vector(hdev->pdev, 1608e2cb1decSSalil Mehta HCLGEVF_MISC_VECTOR_NUM); 1609e2cb1decSSalil Mehta vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1610e2cb1decSSalil Mehta /* vector status always valid for Vector 0 */ 1611e2cb1decSSalil Mehta hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1612e2cb1decSSalil Mehta hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1613e2cb1decSSalil Mehta 1614e2cb1decSSalil Mehta hdev->num_msi_left -= 1; 1615e2cb1decSSalil Mehta hdev->num_msi_used += 1; 1616e2cb1decSSalil Mehta } 1617e2cb1decSSalil Mehta 161835a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 161935a1e503SSalil Mehta { 1620acfc3d55SHuazhong Tan if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) && 1621acfc3d55SHuazhong Tan !test_bit(HCLGEVF_STATE_REMOVING, &hdev->state)) { 162235a1e503SSalil Mehta set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 162335a1e503SSalil Mehta schedule_work(&hdev->rst_service_task); 162435a1e503SSalil Mehta } 162535a1e503SSalil Mehta } 162635a1e503SSalil Mehta 162707a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1628e2cb1decSSalil Mehta { 162907a0556aSSalil Mehta if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) && 163007a0556aSSalil Mehta !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) { 163107a0556aSSalil Mehta set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1632e2cb1decSSalil Mehta schedule_work(&hdev->mbx_service_task); 1633e2cb1decSSalil Mehta } 163407a0556aSSalil Mehta } 1635e2cb1decSSalil Mehta 1636e2cb1decSSalil Mehta static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 1637e2cb1decSSalil Mehta { 1638e2cb1decSSalil Mehta if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 1639e2cb1decSSalil Mehta !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 1640e2cb1decSSalil Mehta schedule_work(&hdev->service_task); 1641e2cb1decSSalil Mehta } 1642e2cb1decSSalil Mehta 1643436667d2SSalil Mehta static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev) 1644436667d2SSalil Mehta { 164507a0556aSSalil Mehta /* if we have any pending mailbox event then schedule the mbx task */ 164607a0556aSSalil Mehta if (hdev->mbx_event_pending) 164707a0556aSSalil Mehta hclgevf_mbx_task_schedule(hdev); 164807a0556aSSalil Mehta 1649436667d2SSalil Mehta if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state)) 1650436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 1651436667d2SSalil Mehta } 1652436667d2SSalil Mehta 1653e2cb1decSSalil Mehta static void hclgevf_service_timer(struct timer_list *t) 1654e2cb1decSSalil Mehta { 1655e2cb1decSSalil Mehta struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 1656e2cb1decSSalil Mehta 1657b37ce587SYufeng Mo mod_timer(&hdev->service_timer, jiffies + 1658b37ce587SYufeng Mo HCLGEVF_GENERAL_TASK_INTERVAL * HZ); 1659e2cb1decSSalil Mehta 1660db01afebSliuzhongzhu hdev->stats_timer++; 1661e2cb1decSSalil Mehta hclgevf_task_schedule(hdev); 1662e2cb1decSSalil Mehta } 1663e2cb1decSSalil Mehta 166435a1e503SSalil Mehta static void hclgevf_reset_service_task(struct work_struct *work) 166535a1e503SSalil Mehta { 166635a1e503SSalil Mehta struct hclgevf_dev *hdev = 166735a1e503SSalil Mehta container_of(work, struct hclgevf_dev, rst_service_task); 1668a8dedb65SSalil Mehta int ret; 166935a1e503SSalil Mehta 167035a1e503SSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 167135a1e503SSalil Mehta return; 167235a1e503SSalil Mehta 167335a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 167435a1e503SSalil Mehta 1675436667d2SSalil Mehta if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1676436667d2SSalil Mehta &hdev->reset_state)) { 1677436667d2SSalil Mehta /* PF has initmated that it is about to reset the hardware. 16789b2f3477SWeihang Li * We now have to poll & check if hardware has actually 16799b2f3477SWeihang Li * completed the reset sequence. On hardware reset completion, 16809b2f3477SWeihang Li * VF needs to reset the client and ae device. 168135a1e503SSalil Mehta */ 1682436667d2SSalil Mehta hdev->reset_attempts = 0; 1683436667d2SSalil Mehta 1684dea846e8SHuazhong Tan hdev->last_reset_time = jiffies; 1685dea846e8SHuazhong Tan while ((hdev->reset_type = 1686dea846e8SHuazhong Tan hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 1687dea846e8SHuazhong Tan != HNAE3_NONE_RESET) { 16886988eb2aSSalil Mehta ret = hclgevf_reset(hdev); 16896988eb2aSSalil Mehta if (ret) 1690dea846e8SHuazhong Tan dev_err(&hdev->pdev->dev, 1691dea846e8SHuazhong Tan "VF stack reset failed %d.\n", ret); 1692dea846e8SHuazhong Tan } 1693436667d2SSalil Mehta } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1694436667d2SSalil Mehta &hdev->reset_state)) { 1695436667d2SSalil Mehta /* we could be here when either of below happens: 16969b2f3477SWeihang Li * 1. reset was initiated due to watchdog timeout caused by 1697436667d2SSalil Mehta * a. IMP was earlier reset and our TX got choked down and 1698436667d2SSalil Mehta * which resulted in watchdog reacting and inducing VF 1699436667d2SSalil Mehta * reset. This also means our cmdq would be unreliable. 1700436667d2SSalil Mehta * b. problem in TX due to other lower layer(example link 1701436667d2SSalil Mehta * layer not functioning properly etc.) 1702436667d2SSalil Mehta * 2. VF reset might have been initiated due to some config 1703436667d2SSalil Mehta * change. 1704436667d2SSalil Mehta * 1705436667d2SSalil Mehta * NOTE: Theres no clear way to detect above cases than to react 1706436667d2SSalil Mehta * to the response of PF for this reset request. PF will ack the 1707436667d2SSalil Mehta * 1b and 2. cases but we will not get any intimation about 1a 1708436667d2SSalil Mehta * from PF as cmdq would be in unreliable state i.e. mailbox 1709436667d2SSalil Mehta * communication between PF and VF would be broken. 1710436667d2SSalil Mehta */ 1711436667d2SSalil Mehta 1712436667d2SSalil Mehta /* if we are never geting into pending state it means either: 1713436667d2SSalil Mehta * 1. PF is not receiving our request which could be due to IMP 1714436667d2SSalil Mehta * reset 1715436667d2SSalil Mehta * 2. PF is screwed 1716436667d2SSalil Mehta * We cannot do much for 2. but to check first we can try reset 1717436667d2SSalil Mehta * our PCIe + stack and see if it alleviates the problem. 1718436667d2SSalil Mehta */ 1719436667d2SSalil Mehta if (hdev->reset_attempts > 3) { 1720436667d2SSalil Mehta /* prepare for full reset of stack + pcie interface */ 1721dea846e8SHuazhong Tan set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1722436667d2SSalil Mehta 1723436667d2SSalil Mehta /* "defer" schedule the reset task again */ 1724436667d2SSalil Mehta set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1725436667d2SSalil Mehta } else { 1726436667d2SSalil Mehta hdev->reset_attempts++; 1727436667d2SSalil Mehta 1728dea846e8SHuazhong Tan set_bit(hdev->reset_level, &hdev->reset_pending); 1729dea846e8SHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1730436667d2SSalil Mehta } 1731dea846e8SHuazhong Tan hclgevf_reset_task_schedule(hdev); 1732436667d2SSalil Mehta } 173335a1e503SSalil Mehta 173435a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 173535a1e503SSalil Mehta } 173635a1e503SSalil Mehta 1737e2cb1decSSalil Mehta static void hclgevf_mailbox_service_task(struct work_struct *work) 1738e2cb1decSSalil Mehta { 1739e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1740e2cb1decSSalil Mehta 1741e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 1742e2cb1decSSalil Mehta 1743e2cb1decSSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1744e2cb1decSSalil Mehta return; 1745e2cb1decSSalil Mehta 1746e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1747e2cb1decSSalil Mehta 174807a0556aSSalil Mehta hclgevf_mbx_async_handler(hdev); 1749e2cb1decSSalil Mehta 1750e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1751e2cb1decSSalil Mehta } 1752e2cb1decSSalil Mehta 1753a6d818e3SYunsheng Lin static void hclgevf_keep_alive_timer(struct timer_list *t) 1754a6d818e3SYunsheng Lin { 1755a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = from_timer(hdev, t, keep_alive_timer); 1756a6d818e3SYunsheng Lin 1757a6d818e3SYunsheng Lin schedule_work(&hdev->keep_alive_task); 1758b37ce587SYufeng Mo mod_timer(&hdev->keep_alive_timer, jiffies + 1759b37ce587SYufeng Mo HCLGEVF_KEEP_ALIVE_TASK_INTERVAL * HZ); 1760a6d818e3SYunsheng Lin } 1761a6d818e3SYunsheng Lin 1762a6d818e3SYunsheng Lin static void hclgevf_keep_alive_task(struct work_struct *work) 1763a6d818e3SYunsheng Lin { 1764a6d818e3SYunsheng Lin struct hclgevf_dev *hdev; 1765a6d818e3SYunsheng Lin u8 respmsg; 1766a6d818e3SYunsheng Lin int ret; 1767a6d818e3SYunsheng Lin 1768a6d818e3SYunsheng Lin hdev = container_of(work, struct hclgevf_dev, keep_alive_task); 1769c59a85c0SJian Shen 17701416d333SHuazhong Tan if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 1771c59a85c0SJian Shen return; 1772c59a85c0SJian Shen 1773a6d818e3SYunsheng Lin ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL, 177463cbf7a9SYufeng Mo 0, false, &respmsg, sizeof(respmsg)); 1775a6d818e3SYunsheng Lin if (ret) 1776a6d818e3SYunsheng Lin dev_err(&hdev->pdev->dev, 1777a6d818e3SYunsheng Lin "VF sends keep alive cmd failed(=%d)\n", ret); 1778a6d818e3SYunsheng Lin } 1779a6d818e3SYunsheng Lin 1780e2cb1decSSalil Mehta static void hclgevf_service_task(struct work_struct *work) 1781e2cb1decSSalil Mehta { 1782db01afebSliuzhongzhu struct hnae3_handle *handle; 1783e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1784e2cb1decSSalil Mehta 1785e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, service_task); 1786db01afebSliuzhongzhu handle = &hdev->nic; 1787db01afebSliuzhongzhu 1788db01afebSliuzhongzhu if (hdev->stats_timer >= HCLGEVF_STATS_TIMER_INTERVAL) { 1789db01afebSliuzhongzhu hclgevf_tqps_update_stats(handle); 1790db01afebSliuzhongzhu hdev->stats_timer = 0; 1791db01afebSliuzhongzhu } 1792e2cb1decSSalil Mehta 1793e2cb1decSSalil Mehta /* request the link status from the PF. PF would be able to tell VF 1794e2cb1decSSalil Mehta * about such updates in future so we might remove this later 1795e2cb1decSSalil Mehta */ 1796e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1797e2cb1decSSalil Mehta 17989194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 17999194d18bSliuzhongzhu 1800436667d2SSalil Mehta hclgevf_deferred_task_schedule(hdev); 1801436667d2SSalil Mehta 1802e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1803e2cb1decSSalil Mehta } 1804e2cb1decSSalil Mehta 1805e2cb1decSSalil Mehta static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1806e2cb1decSSalil Mehta { 1807e2cb1decSSalil Mehta hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1808e2cb1decSSalil Mehta } 1809e2cb1decSSalil Mehta 1810b90fcc5bSHuazhong Tan static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1811b90fcc5bSHuazhong Tan u32 *clearval) 1812e2cb1decSSalil Mehta { 1813b90fcc5bSHuazhong Tan u32 cmdq_src_reg, rst_ing_reg; 1814e2cb1decSSalil Mehta 1815e2cb1decSSalil Mehta /* fetch the events from their corresponding regs */ 1816e2cb1decSSalil Mehta cmdq_src_reg = hclgevf_read_dev(&hdev->hw, 1817e2cb1decSSalil Mehta HCLGEVF_VECTOR0_CMDQ_SRC_REG); 1818e2cb1decSSalil Mehta 1819b90fcc5bSHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_src_reg) { 1820b90fcc5bSHuazhong Tan rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1821b90fcc5bSHuazhong Tan dev_info(&hdev->pdev->dev, 1822b90fcc5bSHuazhong Tan "receive reset interrupt 0x%x!\n", rst_ing_reg); 1823b90fcc5bSHuazhong Tan set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1824b90fcc5bSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1825ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1826b90fcc5bSHuazhong Tan cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RST_INT_B); 1827b90fcc5bSHuazhong Tan *clearval = cmdq_src_reg; 1828c88a6e7dSHuazhong Tan hdev->rst_stats.vf_rst_cnt++; 1829b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_RST; 1830b90fcc5bSHuazhong Tan } 1831b90fcc5bSHuazhong Tan 1832e2cb1decSSalil Mehta /* check for vector0 mailbox(=CMDQ RX) event source */ 1833e2cb1decSSalil Mehta if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 1834e2cb1decSSalil Mehta cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1835e2cb1decSSalil Mehta *clearval = cmdq_src_reg; 1836b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_MBX; 1837e2cb1decSSalil Mehta } 1838e2cb1decSSalil Mehta 1839e2cb1decSSalil Mehta dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 1840e2cb1decSSalil Mehta 1841b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_OTHER; 1842e2cb1decSSalil Mehta } 1843e2cb1decSSalil Mehta 1844e2cb1decSSalil Mehta static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1845e2cb1decSSalil Mehta { 1846e2cb1decSSalil Mehta writel(en ? 1 : 0, vector->addr); 1847e2cb1decSSalil Mehta } 1848e2cb1decSSalil Mehta 1849e2cb1decSSalil Mehta static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1850e2cb1decSSalil Mehta { 1851b90fcc5bSHuazhong Tan enum hclgevf_evt_cause event_cause; 1852e2cb1decSSalil Mehta struct hclgevf_dev *hdev = data; 1853e2cb1decSSalil Mehta u32 clearval; 1854e2cb1decSSalil Mehta 1855e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 1856b90fcc5bSHuazhong Tan event_cause = hclgevf_check_evt_cause(hdev, &clearval); 1857e2cb1decSSalil Mehta 1858b90fcc5bSHuazhong Tan switch (event_cause) { 1859b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_RST: 1860b90fcc5bSHuazhong Tan hclgevf_reset_task_schedule(hdev); 1861b90fcc5bSHuazhong Tan break; 1862b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_MBX: 186307a0556aSSalil Mehta hclgevf_mbx_handler(hdev); 1864b90fcc5bSHuazhong Tan break; 1865b90fcc5bSHuazhong Tan default: 1866b90fcc5bSHuazhong Tan break; 1867b90fcc5bSHuazhong Tan } 1868e2cb1decSSalil Mehta 1869b90fcc5bSHuazhong Tan if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 1870e2cb1decSSalil Mehta hclgevf_clear_event_cause(hdev, clearval); 1871e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 1872b90fcc5bSHuazhong Tan } 1873e2cb1decSSalil Mehta 1874e2cb1decSSalil Mehta return IRQ_HANDLED; 1875e2cb1decSSalil Mehta } 1876e2cb1decSSalil Mehta 1877e2cb1decSSalil Mehta static int hclgevf_configure(struct hclgevf_dev *hdev) 1878e2cb1decSSalil Mehta { 1879e2cb1decSSalil Mehta int ret; 1880e2cb1decSSalil Mehta 188192f11ea1SJian Shen /* get current port based vlan state from PF */ 188292f11ea1SJian Shen ret = hclgevf_get_port_base_vlan_filter_state(hdev); 188392f11ea1SJian Shen if (ret) 188492f11ea1SJian Shen return ret; 188592f11ea1SJian Shen 1886e2cb1decSSalil Mehta /* get queue configuration from PF */ 18876cee6fc3SJian Shen ret = hclgevf_get_queue_info(hdev); 1888e2cb1decSSalil Mehta if (ret) 1889e2cb1decSSalil Mehta return ret; 1890c0425944SPeng Li 1891c0425944SPeng Li /* get queue depth info from PF */ 1892c0425944SPeng Li ret = hclgevf_get_queue_depth(hdev); 1893c0425944SPeng Li if (ret) 1894c0425944SPeng Li return ret; 1895c0425944SPeng Li 18969c3e7130Sliuzhongzhu ret = hclgevf_get_pf_media_type(hdev); 18979c3e7130Sliuzhongzhu if (ret) 18989c3e7130Sliuzhongzhu return ret; 18999c3e7130Sliuzhongzhu 1900e2cb1decSSalil Mehta /* get tc configuration from PF */ 1901e2cb1decSSalil Mehta return hclgevf_get_tc_info(hdev); 1902e2cb1decSSalil Mehta } 1903e2cb1decSSalil Mehta 19047a01c897SSalil Mehta static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 19057a01c897SSalil Mehta { 19067a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 19071154bb26SPeng Li struct hclgevf_dev *hdev; 19087a01c897SSalil Mehta 19097a01c897SSalil Mehta hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 19107a01c897SSalil Mehta if (!hdev) 19117a01c897SSalil Mehta return -ENOMEM; 19127a01c897SSalil Mehta 19137a01c897SSalil Mehta hdev->pdev = pdev; 19147a01c897SSalil Mehta hdev->ae_dev = ae_dev; 19157a01c897SSalil Mehta ae_dev->priv = hdev; 19167a01c897SSalil Mehta 19177a01c897SSalil Mehta return 0; 19187a01c897SSalil Mehta } 19197a01c897SSalil Mehta 1920e2cb1decSSalil Mehta static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 1921e2cb1decSSalil Mehta { 1922e2cb1decSSalil Mehta struct hnae3_handle *roce = &hdev->roce; 1923e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 1924e2cb1decSSalil Mehta 192507acf909SJian Shen roce->rinfo.num_vectors = hdev->num_roce_msix; 1926e2cb1decSSalil Mehta 1927e2cb1decSSalil Mehta if (hdev->num_msi_left < roce->rinfo.num_vectors || 1928e2cb1decSSalil Mehta hdev->num_msi_left == 0) 1929e2cb1decSSalil Mehta return -EINVAL; 1930e2cb1decSSalil Mehta 193107acf909SJian Shen roce->rinfo.base_vector = hdev->roce_base_vector; 1932e2cb1decSSalil Mehta 1933e2cb1decSSalil Mehta roce->rinfo.netdev = nic->kinfo.netdev; 1934e2cb1decSSalil Mehta roce->rinfo.roce_io_base = hdev->hw.io_base; 1935e2cb1decSSalil Mehta 1936e2cb1decSSalil Mehta roce->pdev = nic->pdev; 1937e2cb1decSSalil Mehta roce->ae_algo = nic->ae_algo; 1938e2cb1decSSalil Mehta roce->numa_node_mask = nic->numa_node_mask; 1939e2cb1decSSalil Mehta 1940e2cb1decSSalil Mehta return 0; 1941e2cb1decSSalil Mehta } 1942e2cb1decSSalil Mehta 1943b26a6feaSPeng Li static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 1944b26a6feaSPeng Li { 1945b26a6feaSPeng Li struct hclgevf_cfg_gro_status_cmd *req; 1946b26a6feaSPeng Li struct hclgevf_desc desc; 1947b26a6feaSPeng Li int ret; 1948b26a6feaSPeng Li 1949b26a6feaSPeng Li if (!hnae3_dev_gro_supported(hdev)) 1950b26a6feaSPeng Li return 0; 1951b26a6feaSPeng Li 1952b26a6feaSPeng Li hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 1953b26a6feaSPeng Li false); 1954b26a6feaSPeng Li req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 1955b26a6feaSPeng Li 1956b26a6feaSPeng Li req->gro_en = cpu_to_le16(en ? 1 : 0); 1957b26a6feaSPeng Li 1958b26a6feaSPeng Li ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1959b26a6feaSPeng Li if (ret) 1960b26a6feaSPeng Li dev_err(&hdev->pdev->dev, 1961b26a6feaSPeng Li "VF GRO hardware config cmd failed, ret = %d.\n", ret); 1962b26a6feaSPeng Li 1963b26a6feaSPeng Li return ret; 1964b26a6feaSPeng Li } 1965b26a6feaSPeng Li 1966e2cb1decSSalil Mehta static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 1967e2cb1decSSalil Mehta { 1968e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1969e2cb1decSSalil Mehta int i, ret; 1970e2cb1decSSalil Mehta 1971e2cb1decSSalil Mehta rss_cfg->rss_size = hdev->rss_size_max; 1972e2cb1decSSalil Mehta 1973374ad291SJian Shen if (hdev->pdev->revision >= 0x21) { 1974472d7eceSJian Shen rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 1975472d7eceSJian Shen memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 1976374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 1977374ad291SJian Shen 1978374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 1979374ad291SJian Shen rss_cfg->rss_hash_key); 1980374ad291SJian Shen if (ret) 1981374ad291SJian Shen return ret; 1982d97b3072SJian Shen 1983d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = 1984d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1985d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = 1986d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1987d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = 1988d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1989d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = 1990d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1991d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = 1992d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1993d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = 1994d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1995d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = 1996d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1997d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = 1998d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1999d97b3072SJian Shen 2000d97b3072SJian Shen ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 2001d97b3072SJian Shen if (ret) 2002d97b3072SJian Shen return ret; 2003d97b3072SJian Shen 2004374ad291SJian Shen } 2005374ad291SJian Shen 20069b2f3477SWeihang Li /* Initialize RSS indirect table */ 2007e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 2008e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max; 2009e2cb1decSSalil Mehta 2010e2cb1decSSalil Mehta ret = hclgevf_set_rss_indir_table(hdev); 2011e2cb1decSSalil Mehta if (ret) 2012e2cb1decSSalil Mehta return ret; 2013e2cb1decSSalil Mehta 2014e2cb1decSSalil Mehta return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max); 2015e2cb1decSSalil Mehta } 2016e2cb1decSSalil Mehta 2017e2cb1decSSalil Mehta static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2018e2cb1decSSalil Mehta { 2019e2cb1decSSalil Mehta return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2020e2cb1decSSalil Mehta false); 2021e2cb1decSSalil Mehta } 2022e2cb1decSSalil Mehta 20238cdb992fSJian Shen static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 20248cdb992fSJian Shen { 20258cdb992fSJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 20268cdb992fSJian Shen 20278cdb992fSJian Shen if (enable) { 20288cdb992fSJian Shen mod_timer(&hdev->service_timer, jiffies + HZ); 20298cdb992fSJian Shen } else { 20308cdb992fSJian Shen del_timer_sync(&hdev->service_timer); 20318cdb992fSJian Shen cancel_work_sync(&hdev->service_task); 20328cdb992fSJian Shen clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 20338cdb992fSJian Shen } 20348cdb992fSJian Shen } 20358cdb992fSJian Shen 2036e2cb1decSSalil Mehta static int hclgevf_ae_start(struct hnae3_handle *handle) 2037e2cb1decSSalil Mehta { 2038e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2039e2cb1decSSalil Mehta 2040e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 2041e2cb1decSSalil Mehta 2042e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 2043e2cb1decSSalil Mehta 20449194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 20459194d18bSliuzhongzhu 2046e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2047e2cb1decSSalil Mehta 2048e2cb1decSSalil Mehta return 0; 2049e2cb1decSSalil Mehta } 2050e2cb1decSSalil Mehta 2051e2cb1decSSalil Mehta static void hclgevf_ae_stop(struct hnae3_handle *handle) 2052e2cb1decSSalil Mehta { 2053e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 205439cfbc9cSHuazhong Tan int i; 2055e2cb1decSSalil Mehta 20562f7e4896SFuyun Liang set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 20572f7e4896SFuyun Liang 2058146e92c1SHuazhong Tan if (hdev->reset_type != HNAE3_VF_RESET) 205939cfbc9cSHuazhong Tan for (i = 0; i < handle->kinfo.num_tqps; i++) 2060146e92c1SHuazhong Tan if (hclgevf_reset_tqp(handle, i)) 2061146e92c1SHuazhong Tan break; 206239cfbc9cSHuazhong Tan 2063e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 20648cc6c1f7SFuyun Liang hclgevf_update_link_status(hdev, 0); 2065e2cb1decSSalil Mehta } 2066e2cb1decSSalil Mehta 2067a6d818e3SYunsheng Lin static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2068a6d818e3SYunsheng Lin { 2069a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2070a6d818e3SYunsheng Lin u8 msg_data; 2071a6d818e3SYunsheng Lin 2072a6d818e3SYunsheng Lin msg_data = alive ? 1 : 0; 2073a6d818e3SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE, 2074a6d818e3SYunsheng Lin 0, &msg_data, 1, false, NULL, 0); 2075a6d818e3SYunsheng Lin } 2076a6d818e3SYunsheng Lin 2077a6d818e3SYunsheng Lin static int hclgevf_client_start(struct hnae3_handle *handle) 2078a6d818e3SYunsheng Lin { 2079a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2080e233516eSHuazhong Tan int ret; 2081e233516eSHuazhong Tan 2082e233516eSHuazhong Tan ret = hclgevf_set_alive(handle, true); 2083e233516eSHuazhong Tan if (ret) 2084e233516eSHuazhong Tan return ret; 2085a6d818e3SYunsheng Lin 2086b37ce587SYufeng Mo mod_timer(&hdev->keep_alive_timer, jiffies + 2087b37ce587SYufeng Mo HCLGEVF_KEEP_ALIVE_TASK_INTERVAL * HZ); 2088e233516eSHuazhong Tan 2089e233516eSHuazhong Tan return 0; 2090a6d818e3SYunsheng Lin } 2091a6d818e3SYunsheng Lin 2092a6d818e3SYunsheng Lin static void hclgevf_client_stop(struct hnae3_handle *handle) 2093a6d818e3SYunsheng Lin { 2094a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2095a6d818e3SYunsheng Lin int ret; 2096a6d818e3SYunsheng Lin 2097a6d818e3SYunsheng Lin ret = hclgevf_set_alive(handle, false); 2098a6d818e3SYunsheng Lin if (ret) 2099a6d818e3SYunsheng Lin dev_warn(&hdev->pdev->dev, 2100a6d818e3SYunsheng Lin "%s failed %d\n", __func__, ret); 2101a6d818e3SYunsheng Lin 2102a6d818e3SYunsheng Lin del_timer_sync(&hdev->keep_alive_timer); 2103a6d818e3SYunsheng Lin cancel_work_sync(&hdev->keep_alive_task); 2104a6d818e3SYunsheng Lin } 2105a6d818e3SYunsheng Lin 2106e2cb1decSSalil Mehta static void hclgevf_state_init(struct hclgevf_dev *hdev) 2107e2cb1decSSalil Mehta { 2108e2cb1decSSalil Mehta /* setup tasks for the MBX */ 2109e2cb1decSSalil Mehta INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 2110e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2111e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2112e2cb1decSSalil Mehta 2113e2cb1decSSalil Mehta /* setup tasks for service timer */ 2114e2cb1decSSalil Mehta timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 2115e2cb1decSSalil Mehta 2116e2cb1decSSalil Mehta INIT_WORK(&hdev->service_task, hclgevf_service_task); 2117e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2118e2cb1decSSalil Mehta 211935a1e503SSalil Mehta INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task); 212035a1e503SSalil Mehta 2121e2cb1decSSalil Mehta mutex_init(&hdev->mbx_resp.mbx_mutex); 2122e2cb1decSSalil Mehta 2123e2cb1decSSalil Mehta /* bring the device down */ 2124e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2125e2cb1decSSalil Mehta } 2126e2cb1decSSalil Mehta 2127e2cb1decSSalil Mehta static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2128e2cb1decSSalil Mehta { 2129e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2130acfc3d55SHuazhong Tan set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2131e2cb1decSSalil Mehta 2132e233516eSHuazhong Tan if (hdev->keep_alive_timer.function) 2133e233516eSHuazhong Tan del_timer_sync(&hdev->keep_alive_timer); 2134e233516eSHuazhong Tan if (hdev->keep_alive_task.func) 2135e233516eSHuazhong Tan cancel_work_sync(&hdev->keep_alive_task); 2136e2cb1decSSalil Mehta if (hdev->service_timer.function) 2137e2cb1decSSalil Mehta del_timer_sync(&hdev->service_timer); 2138e2cb1decSSalil Mehta if (hdev->service_task.func) 2139e2cb1decSSalil Mehta cancel_work_sync(&hdev->service_task); 2140e2cb1decSSalil Mehta if (hdev->mbx_service_task.func) 2141e2cb1decSSalil Mehta cancel_work_sync(&hdev->mbx_service_task); 214235a1e503SSalil Mehta if (hdev->rst_service_task.func) 214335a1e503SSalil Mehta cancel_work_sync(&hdev->rst_service_task); 2144e2cb1decSSalil Mehta 2145e2cb1decSSalil Mehta mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2146e2cb1decSSalil Mehta } 2147e2cb1decSSalil Mehta 2148e2cb1decSSalil Mehta static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2149e2cb1decSSalil Mehta { 2150e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2151e2cb1decSSalil Mehta int vectors; 2152e2cb1decSSalil Mehta int i; 2153e2cb1decSSalil Mehta 215407acf909SJian Shen if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) 215507acf909SJian Shen vectors = pci_alloc_irq_vectors(pdev, 215607acf909SJian Shen hdev->roce_base_msix_offset + 1, 215707acf909SJian Shen hdev->num_msi, 215807acf909SJian Shen PCI_IRQ_MSIX); 215907acf909SJian Shen else 2160e2cb1decSSalil Mehta vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 2161e2cb1decSSalil Mehta PCI_IRQ_MSI | PCI_IRQ_MSIX); 216207acf909SJian Shen 2163e2cb1decSSalil Mehta if (vectors < 0) { 2164e2cb1decSSalil Mehta dev_err(&pdev->dev, 2165e2cb1decSSalil Mehta "failed(%d) to allocate MSI/MSI-X vectors\n", 2166e2cb1decSSalil Mehta vectors); 2167e2cb1decSSalil Mehta return vectors; 2168e2cb1decSSalil Mehta } 2169e2cb1decSSalil Mehta if (vectors < hdev->num_msi) 2170e2cb1decSSalil Mehta dev_warn(&hdev->pdev->dev, 2171e2cb1decSSalil Mehta "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2172e2cb1decSSalil Mehta hdev->num_msi, vectors); 2173e2cb1decSSalil Mehta 2174e2cb1decSSalil Mehta hdev->num_msi = vectors; 2175e2cb1decSSalil Mehta hdev->num_msi_left = vectors; 2176e2cb1decSSalil Mehta hdev->base_msi_vector = pdev->irq; 217707acf909SJian Shen hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2178e2cb1decSSalil Mehta 2179e2cb1decSSalil Mehta hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2180e2cb1decSSalil Mehta sizeof(u16), GFP_KERNEL); 2181e2cb1decSSalil Mehta if (!hdev->vector_status) { 2182e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2183e2cb1decSSalil Mehta return -ENOMEM; 2184e2cb1decSSalil Mehta } 2185e2cb1decSSalil Mehta 2186e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 2187e2cb1decSSalil Mehta hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2188e2cb1decSSalil Mehta 2189e2cb1decSSalil Mehta hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2190e2cb1decSSalil Mehta sizeof(int), GFP_KERNEL); 2191e2cb1decSSalil Mehta if (!hdev->vector_irq) { 2192862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2193e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2194e2cb1decSSalil Mehta return -ENOMEM; 2195e2cb1decSSalil Mehta } 2196e2cb1decSSalil Mehta 2197e2cb1decSSalil Mehta return 0; 2198e2cb1decSSalil Mehta } 2199e2cb1decSSalil Mehta 2200e2cb1decSSalil Mehta static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2201e2cb1decSSalil Mehta { 2202e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2203e2cb1decSSalil Mehta 2204862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2205862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_irq); 2206e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2207e2cb1decSSalil Mehta } 2208e2cb1decSSalil Mehta 2209e2cb1decSSalil Mehta static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2210e2cb1decSSalil Mehta { 2211e2cb1decSSalil Mehta int ret = 0; 2212e2cb1decSSalil Mehta 2213e2cb1decSSalil Mehta hclgevf_get_misc_vector(hdev); 2214e2cb1decSSalil Mehta 2215e2cb1decSSalil Mehta ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2216e2cb1decSSalil Mehta 0, "hclgevf_cmd", hdev); 2217e2cb1decSSalil Mehta if (ret) { 2218e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2219e2cb1decSSalil Mehta hdev->misc_vector.vector_irq); 2220e2cb1decSSalil Mehta return ret; 2221e2cb1decSSalil Mehta } 2222e2cb1decSSalil Mehta 22231819e409SXi Wang hclgevf_clear_event_cause(hdev, 0); 22241819e409SXi Wang 2225e2cb1decSSalil Mehta /* enable misc. vector(vector 0) */ 2226e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2227e2cb1decSSalil Mehta 2228e2cb1decSSalil Mehta return ret; 2229e2cb1decSSalil Mehta } 2230e2cb1decSSalil Mehta 2231e2cb1decSSalil Mehta static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2232e2cb1decSSalil Mehta { 2233e2cb1decSSalil Mehta /* disable misc vector(vector 0) */ 2234e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 22351819e409SXi Wang synchronize_irq(hdev->misc_vector.vector_irq); 2236e2cb1decSSalil Mehta free_irq(hdev->misc_vector.vector_irq, hdev); 2237e2cb1decSSalil Mehta hclgevf_free_vector(hdev, 0); 2238e2cb1decSSalil Mehta } 2239e2cb1decSSalil Mehta 2240bb87be87SYonglong Liu static void hclgevf_info_show(struct hclgevf_dev *hdev) 2241bb87be87SYonglong Liu { 2242bb87be87SYonglong Liu struct device *dev = &hdev->pdev->dev; 2243bb87be87SYonglong Liu 2244bb87be87SYonglong Liu dev_info(dev, "VF info begin:\n"); 2245bb87be87SYonglong Liu 2246bb87be87SYonglong Liu dev_info(dev, "Task queue pairs numbers: %d\n", hdev->num_tqps); 2247bb87be87SYonglong Liu dev_info(dev, "Desc num per TX queue: %d\n", hdev->num_tx_desc); 2248bb87be87SYonglong Liu dev_info(dev, "Desc num per RX queue: %d\n", hdev->num_rx_desc); 2249bb87be87SYonglong Liu dev_info(dev, "Numbers of vports: %d\n", hdev->num_alloc_vport); 2250bb87be87SYonglong Liu dev_info(dev, "HW tc map: %d\n", hdev->hw_tc_map); 2251bb87be87SYonglong Liu dev_info(dev, "PF media type of this VF: %d\n", 2252bb87be87SYonglong Liu hdev->hw.mac.media_type); 2253bb87be87SYonglong Liu 2254bb87be87SYonglong Liu dev_info(dev, "VF info end.\n"); 2255bb87be87SYonglong Liu } 2256bb87be87SYonglong Liu 22571db58f86SHuazhong Tan static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 22581db58f86SHuazhong Tan struct hnae3_client *client) 22591db58f86SHuazhong Tan { 22601db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 22611db58f86SHuazhong Tan int ret; 22621db58f86SHuazhong Tan 22631db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->nic); 22641db58f86SHuazhong Tan if (ret) 22651db58f86SHuazhong Tan return ret; 22661db58f86SHuazhong Tan 22671db58f86SHuazhong Tan set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 22681db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 22691db58f86SHuazhong Tan 22701db58f86SHuazhong Tan if (netif_msg_drv(&hdev->nic)) 22711db58f86SHuazhong Tan hclgevf_info_show(hdev); 22721db58f86SHuazhong Tan 22731db58f86SHuazhong Tan return 0; 22741db58f86SHuazhong Tan } 22751db58f86SHuazhong Tan 22761db58f86SHuazhong Tan static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 22771db58f86SHuazhong Tan struct hnae3_client *client) 22781db58f86SHuazhong Tan { 22791db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 22801db58f86SHuazhong Tan int ret; 22811db58f86SHuazhong Tan 22821db58f86SHuazhong Tan if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 22831db58f86SHuazhong Tan !hdev->nic_client) 22841db58f86SHuazhong Tan return 0; 22851db58f86SHuazhong Tan 22861db58f86SHuazhong Tan ret = hclgevf_init_roce_base_info(hdev); 22871db58f86SHuazhong Tan if (ret) 22881db58f86SHuazhong Tan return ret; 22891db58f86SHuazhong Tan 22901db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->roce); 22911db58f86SHuazhong Tan if (ret) 22921db58f86SHuazhong Tan return ret; 22931db58f86SHuazhong Tan 22941db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 22951db58f86SHuazhong Tan 22961db58f86SHuazhong Tan return 0; 22971db58f86SHuazhong Tan } 22981db58f86SHuazhong Tan 2299e718a93fSPeng Li static int hclgevf_init_client_instance(struct hnae3_client *client, 2300e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2301e2cb1decSSalil Mehta { 2302e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2303e2cb1decSSalil Mehta int ret; 2304e2cb1decSSalil Mehta 2305e2cb1decSSalil Mehta switch (client->type) { 2306e2cb1decSSalil Mehta case HNAE3_CLIENT_KNIC: 2307e2cb1decSSalil Mehta hdev->nic_client = client; 2308e2cb1decSSalil Mehta hdev->nic.client = client; 2309e2cb1decSSalil Mehta 23101db58f86SHuazhong Tan ret = hclgevf_init_nic_client_instance(ae_dev, client); 2311e2cb1decSSalil Mehta if (ret) 231249dd8054SJian Shen goto clear_nic; 2313e2cb1decSSalil Mehta 23141db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, 23151db58f86SHuazhong Tan hdev->roce_client); 2316e2cb1decSSalil Mehta if (ret) 231749dd8054SJian Shen goto clear_roce; 2318d9f28fc2SJian Shen 2319e2cb1decSSalil Mehta break; 2320e2cb1decSSalil Mehta case HNAE3_CLIENT_ROCE: 2321544a7bcdSLijun Ou if (hnae3_dev_roce_supported(hdev)) { 2322e2cb1decSSalil Mehta hdev->roce_client = client; 2323e2cb1decSSalil Mehta hdev->roce.client = client; 2324544a7bcdSLijun Ou } 2325e2cb1decSSalil Mehta 23261db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, client); 2327e2cb1decSSalil Mehta if (ret) 232849dd8054SJian Shen goto clear_roce; 2329e2cb1decSSalil Mehta 2330fa7a4bd5SJian Shen break; 2331fa7a4bd5SJian Shen default: 2332fa7a4bd5SJian Shen return -EINVAL; 2333e2cb1decSSalil Mehta } 2334e2cb1decSSalil Mehta 2335e2cb1decSSalil Mehta return 0; 233649dd8054SJian Shen 233749dd8054SJian Shen clear_nic: 233849dd8054SJian Shen hdev->nic_client = NULL; 233949dd8054SJian Shen hdev->nic.client = NULL; 234049dd8054SJian Shen return ret; 234149dd8054SJian Shen clear_roce: 234249dd8054SJian Shen hdev->roce_client = NULL; 234349dd8054SJian Shen hdev->roce.client = NULL; 234449dd8054SJian Shen return ret; 2345e2cb1decSSalil Mehta } 2346e2cb1decSSalil Mehta 2347e718a93fSPeng Li static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2348e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2349e2cb1decSSalil Mehta { 2350e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2351e718a93fSPeng Li 2352e2cb1decSSalil Mehta /* un-init roce, if it exists */ 235349dd8054SJian Shen if (hdev->roce_client) { 2354e2cb1decSSalil Mehta hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 235549dd8054SJian Shen hdev->roce_client = NULL; 235649dd8054SJian Shen hdev->roce.client = NULL; 235749dd8054SJian Shen } 2358e2cb1decSSalil Mehta 2359e2cb1decSSalil Mehta /* un-init nic/unic, if this was not called by roce client */ 236049dd8054SJian Shen if (client->ops->uninit_instance && hdev->nic_client && 236149dd8054SJian Shen client->type != HNAE3_CLIENT_ROCE) { 236225d1817cSHuazhong Tan clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 236325d1817cSHuazhong Tan 2364e2cb1decSSalil Mehta client->ops->uninit_instance(&hdev->nic, 0); 236549dd8054SJian Shen hdev->nic_client = NULL; 236649dd8054SJian Shen hdev->nic.client = NULL; 236749dd8054SJian Shen } 2368e2cb1decSSalil Mehta } 2369e2cb1decSSalil Mehta 2370e2cb1decSSalil Mehta static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2371e2cb1decSSalil Mehta { 2372e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2373e2cb1decSSalil Mehta struct hclgevf_hw *hw; 2374e2cb1decSSalil Mehta int ret; 2375e2cb1decSSalil Mehta 2376e2cb1decSSalil Mehta ret = pci_enable_device(pdev); 2377e2cb1decSSalil Mehta if (ret) { 2378e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed to enable PCI device\n"); 23793e249d3bSFuyun Liang return ret; 2380e2cb1decSSalil Mehta } 2381e2cb1decSSalil Mehta 2382e2cb1decSSalil Mehta ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2383e2cb1decSSalil Mehta if (ret) { 2384e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2385e2cb1decSSalil Mehta goto err_disable_device; 2386e2cb1decSSalil Mehta } 2387e2cb1decSSalil Mehta 2388e2cb1decSSalil Mehta ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2389e2cb1decSSalil Mehta if (ret) { 2390e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2391e2cb1decSSalil Mehta goto err_disable_device; 2392e2cb1decSSalil Mehta } 2393e2cb1decSSalil Mehta 2394e2cb1decSSalil Mehta pci_set_master(pdev); 2395e2cb1decSSalil Mehta hw = &hdev->hw; 2396e2cb1decSSalil Mehta hw->hdev = hdev; 23972e1ea493SPeng Li hw->io_base = pci_iomap(pdev, 2, 0); 2398e2cb1decSSalil Mehta if (!hw->io_base) { 2399e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't map configuration register space\n"); 2400e2cb1decSSalil Mehta ret = -ENOMEM; 2401e2cb1decSSalil Mehta goto err_clr_master; 2402e2cb1decSSalil Mehta } 2403e2cb1decSSalil Mehta 2404e2cb1decSSalil Mehta return 0; 2405e2cb1decSSalil Mehta 2406e2cb1decSSalil Mehta err_clr_master: 2407e2cb1decSSalil Mehta pci_clear_master(pdev); 2408e2cb1decSSalil Mehta pci_release_regions(pdev); 2409e2cb1decSSalil Mehta err_disable_device: 2410e2cb1decSSalil Mehta pci_disable_device(pdev); 24113e249d3bSFuyun Liang 2412e2cb1decSSalil Mehta return ret; 2413e2cb1decSSalil Mehta } 2414e2cb1decSSalil Mehta 2415e2cb1decSSalil Mehta static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2416e2cb1decSSalil Mehta { 2417e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2418e2cb1decSSalil Mehta 2419e2cb1decSSalil Mehta pci_iounmap(pdev, hdev->hw.io_base); 2420e2cb1decSSalil Mehta pci_clear_master(pdev); 2421e2cb1decSSalil Mehta pci_release_regions(pdev); 2422e2cb1decSSalil Mehta pci_disable_device(pdev); 2423e2cb1decSSalil Mehta } 2424e2cb1decSSalil Mehta 242507acf909SJian Shen static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 242607acf909SJian Shen { 242707acf909SJian Shen struct hclgevf_query_res_cmd *req; 242807acf909SJian Shen struct hclgevf_desc desc; 242907acf909SJian Shen int ret; 243007acf909SJian Shen 243107acf909SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 243207acf909SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 243307acf909SJian Shen if (ret) { 243407acf909SJian Shen dev_err(&hdev->pdev->dev, 243507acf909SJian Shen "query vf resource failed, ret = %d.\n", ret); 243607acf909SJian Shen return ret; 243707acf909SJian Shen } 243807acf909SJian Shen 243907acf909SJian Shen req = (struct hclgevf_query_res_cmd *)desc.data; 244007acf909SJian Shen 244107acf909SJian Shen if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) { 244207acf909SJian Shen hdev->roce_base_msix_offset = 244307acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 244407acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_M, 244507acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_S); 244607acf909SJian Shen hdev->num_roce_msix = 244707acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 244807acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 244907acf909SJian Shen 245007acf909SJian Shen /* VF should have NIC vectors and Roce vectors, NIC vectors 245107acf909SJian Shen * are queued before Roce vectors. The offset is fixed to 64. 245207acf909SJian Shen */ 245307acf909SJian Shen hdev->num_msi = hdev->num_roce_msix + 245407acf909SJian Shen hdev->roce_base_msix_offset; 245507acf909SJian Shen } else { 245607acf909SJian Shen hdev->num_msi = 245707acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 245807acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 245907acf909SJian Shen } 246007acf909SJian Shen 246107acf909SJian Shen return 0; 246207acf909SJian Shen } 246307acf909SJian Shen 2464862d969aSHuazhong Tan static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2465862d969aSHuazhong Tan { 2466862d969aSHuazhong Tan struct pci_dev *pdev = hdev->pdev; 2467862d969aSHuazhong Tan int ret = 0; 2468862d969aSHuazhong Tan 2469862d969aSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2470862d969aSHuazhong Tan test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2471862d969aSHuazhong Tan hclgevf_misc_irq_uninit(hdev); 2472862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2473862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2474862d969aSHuazhong Tan } 2475862d969aSHuazhong Tan 2476862d969aSHuazhong Tan if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2477862d969aSHuazhong Tan pci_set_master(pdev); 2478862d969aSHuazhong Tan ret = hclgevf_init_msi(hdev); 2479862d969aSHuazhong Tan if (ret) { 2480862d969aSHuazhong Tan dev_err(&pdev->dev, 2481862d969aSHuazhong Tan "failed(%d) to init MSI/MSI-X\n", ret); 2482862d969aSHuazhong Tan return ret; 2483862d969aSHuazhong Tan } 2484862d969aSHuazhong Tan 2485862d969aSHuazhong Tan ret = hclgevf_misc_irq_init(hdev); 2486862d969aSHuazhong Tan if (ret) { 2487862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2488862d969aSHuazhong Tan dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2489862d969aSHuazhong Tan ret); 2490862d969aSHuazhong Tan return ret; 2491862d969aSHuazhong Tan } 2492862d969aSHuazhong Tan 2493862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2494862d969aSHuazhong Tan } 2495862d969aSHuazhong Tan 2496862d969aSHuazhong Tan return ret; 2497862d969aSHuazhong Tan } 2498862d969aSHuazhong Tan 24999c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2500e2cb1decSSalil Mehta { 25017a01c897SSalil Mehta struct pci_dev *pdev = hdev->pdev; 2502e2cb1decSSalil Mehta int ret; 2503e2cb1decSSalil Mehta 2504862d969aSHuazhong Tan ret = hclgevf_pci_reset(hdev); 2505862d969aSHuazhong Tan if (ret) { 2506862d969aSHuazhong Tan dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2507862d969aSHuazhong Tan return ret; 2508862d969aSHuazhong Tan } 2509862d969aSHuazhong Tan 25109c6f7085SHuazhong Tan ret = hclgevf_cmd_init(hdev); 25119c6f7085SHuazhong Tan if (ret) { 25129c6f7085SHuazhong Tan dev_err(&pdev->dev, "cmd failed %d\n", ret); 25139c6f7085SHuazhong Tan return ret; 25147a01c897SSalil Mehta } 2515e2cb1decSSalil Mehta 25169c6f7085SHuazhong Tan ret = hclgevf_rss_init_hw(hdev); 25179c6f7085SHuazhong Tan if (ret) { 25189c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 25199c6f7085SHuazhong Tan "failed(%d) to initialize RSS\n", ret); 25209c6f7085SHuazhong Tan return ret; 25219c6f7085SHuazhong Tan } 25229c6f7085SHuazhong Tan 2523b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2524b26a6feaSPeng Li if (ret) 2525b26a6feaSPeng Li return ret; 2526b26a6feaSPeng Li 25279c6f7085SHuazhong Tan ret = hclgevf_init_vlan_config(hdev); 25289c6f7085SHuazhong Tan if (ret) { 25299c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 25309c6f7085SHuazhong Tan "failed(%d) to initialize VLAN config\n", ret); 25319c6f7085SHuazhong Tan return ret; 25329c6f7085SHuazhong Tan } 25339c6f7085SHuazhong Tan 25349c6f7085SHuazhong Tan dev_info(&hdev->pdev->dev, "Reset done\n"); 25359c6f7085SHuazhong Tan 25369c6f7085SHuazhong Tan return 0; 25379c6f7085SHuazhong Tan } 25389c6f7085SHuazhong Tan 25399c6f7085SHuazhong Tan static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 25409c6f7085SHuazhong Tan { 25419c6f7085SHuazhong Tan struct pci_dev *pdev = hdev->pdev; 25429c6f7085SHuazhong Tan int ret; 25439c6f7085SHuazhong Tan 2544e2cb1decSSalil Mehta ret = hclgevf_pci_init(hdev); 2545e2cb1decSSalil Mehta if (ret) { 2546e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI initialization failed\n"); 2547e2cb1decSSalil Mehta return ret; 2548e2cb1decSSalil Mehta } 2549e2cb1decSSalil Mehta 25508b0195a3SHuazhong Tan ret = hclgevf_cmd_queue_init(hdev); 25518b0195a3SHuazhong Tan if (ret) { 25528b0195a3SHuazhong Tan dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret); 25538b0195a3SHuazhong Tan goto err_cmd_queue_init; 25548b0195a3SHuazhong Tan } 25558b0195a3SHuazhong Tan 2556eddf0462SYunsheng Lin ret = hclgevf_cmd_init(hdev); 2557eddf0462SYunsheng Lin if (ret) 2558eddf0462SYunsheng Lin goto err_cmd_init; 2559eddf0462SYunsheng Lin 256007acf909SJian Shen /* Get vf resource */ 256107acf909SJian Shen ret = hclgevf_query_vf_resource(hdev); 256207acf909SJian Shen if (ret) { 256307acf909SJian Shen dev_err(&hdev->pdev->dev, 256407acf909SJian Shen "Query vf status error, ret = %d.\n", ret); 25658b0195a3SHuazhong Tan goto err_cmd_init; 256607acf909SJian Shen } 256707acf909SJian Shen 256807acf909SJian Shen ret = hclgevf_init_msi(hdev); 256907acf909SJian Shen if (ret) { 257007acf909SJian Shen dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 25718b0195a3SHuazhong Tan goto err_cmd_init; 257207acf909SJian Shen } 257307acf909SJian Shen 257407acf909SJian Shen hclgevf_state_init(hdev); 2575dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 257607acf909SJian Shen 2577e2cb1decSSalil Mehta ret = hclgevf_misc_irq_init(hdev); 2578e2cb1decSSalil Mehta if (ret) { 2579e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2580e2cb1decSSalil Mehta ret); 2581e2cb1decSSalil Mehta goto err_misc_irq_init; 2582e2cb1decSSalil Mehta } 2583e2cb1decSSalil Mehta 2584862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2585862d969aSHuazhong Tan 2586e2cb1decSSalil Mehta ret = hclgevf_configure(hdev); 2587e2cb1decSSalil Mehta if (ret) { 2588e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2589e2cb1decSSalil Mehta goto err_config; 2590e2cb1decSSalil Mehta } 2591e2cb1decSSalil Mehta 2592e2cb1decSSalil Mehta ret = hclgevf_alloc_tqps(hdev); 2593e2cb1decSSalil Mehta if (ret) { 2594e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2595e2cb1decSSalil Mehta goto err_config; 2596e2cb1decSSalil Mehta } 2597e2cb1decSSalil Mehta 2598e2cb1decSSalil Mehta ret = hclgevf_set_handle_info(hdev); 2599e2cb1decSSalil Mehta if (ret) { 2600e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 2601e2cb1decSSalil Mehta goto err_config; 2602e2cb1decSSalil Mehta } 2603e2cb1decSSalil Mehta 2604b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2605b26a6feaSPeng Li if (ret) 2606b26a6feaSPeng Li goto err_config; 2607b26a6feaSPeng Li 2608f01f5559SJian Shen /* vf is not allowed to enable unicast/multicast promisc mode. 2609f01f5559SJian Shen * For revision 0x20, default to disable broadcast promisc mode, 2610f01f5559SJian Shen * firmware makes sure broadcast packets can be accepted. 2611f01f5559SJian Shen * For revision 0x21, default to enable broadcast promisc mode. 2612f01f5559SJian Shen */ 2613f01f5559SJian Shen ret = hclgevf_set_promisc_mode(hdev, true); 2614f01f5559SJian Shen if (ret) 2615f01f5559SJian Shen goto err_config; 2616f01f5559SJian Shen 2617e2cb1decSSalil Mehta /* Initialize RSS for this VF */ 2618e2cb1decSSalil Mehta ret = hclgevf_rss_init_hw(hdev); 2619e2cb1decSSalil Mehta if (ret) { 2620e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2621e2cb1decSSalil Mehta "failed(%d) to initialize RSS\n", ret); 2622e2cb1decSSalil Mehta goto err_config; 2623e2cb1decSSalil Mehta } 2624e2cb1decSSalil Mehta 2625e2cb1decSSalil Mehta ret = hclgevf_init_vlan_config(hdev); 2626e2cb1decSSalil Mehta if (ret) { 2627e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2628e2cb1decSSalil Mehta "failed(%d) to initialize VLAN config\n", ret); 2629e2cb1decSSalil Mehta goto err_config; 2630e2cb1decSSalil Mehta } 2631e2cb1decSSalil Mehta 26320742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 2633e2cb1decSSalil Mehta pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME); 2634e2cb1decSSalil Mehta 2635e2cb1decSSalil Mehta return 0; 2636e2cb1decSSalil Mehta 2637e2cb1decSSalil Mehta err_config: 2638e2cb1decSSalil Mehta hclgevf_misc_irq_uninit(hdev); 2639e2cb1decSSalil Mehta err_misc_irq_init: 2640e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2641e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 264207acf909SJian Shen err_cmd_init: 26438b0195a3SHuazhong Tan hclgevf_cmd_uninit(hdev); 26448b0195a3SHuazhong Tan err_cmd_queue_init: 2645e2cb1decSSalil Mehta hclgevf_pci_uninit(hdev); 2646862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2647e2cb1decSSalil Mehta return ret; 2648e2cb1decSSalil Mehta } 2649e2cb1decSSalil Mehta 26507a01c897SSalil Mehta static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2651e2cb1decSSalil Mehta { 2652e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2653862d969aSHuazhong Tan 2654862d969aSHuazhong Tan if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2655eddf0462SYunsheng Lin hclgevf_misc_irq_uninit(hdev); 2656e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 26577a01c897SSalil Mehta } 26587a01c897SSalil Mehta 2659e3338205SHuazhong Tan hclgevf_pci_uninit(hdev); 2660862d969aSHuazhong Tan hclgevf_cmd_uninit(hdev); 2661862d969aSHuazhong Tan } 2662862d969aSHuazhong Tan 26637a01c897SSalil Mehta static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 26647a01c897SSalil Mehta { 26657a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 2666a6d818e3SYunsheng Lin struct hclgevf_dev *hdev; 26677a01c897SSalil Mehta int ret; 26687a01c897SSalil Mehta 26697a01c897SSalil Mehta ret = hclgevf_alloc_hdev(ae_dev); 26707a01c897SSalil Mehta if (ret) { 26717a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device allocation failed\n"); 26727a01c897SSalil Mehta return ret; 26737a01c897SSalil Mehta } 26747a01c897SSalil Mehta 26757a01c897SSalil Mehta ret = hclgevf_init_hdev(ae_dev->priv); 2676a6d818e3SYunsheng Lin if (ret) { 26777a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device initialization failed\n"); 26787a01c897SSalil Mehta return ret; 26797a01c897SSalil Mehta } 26807a01c897SSalil Mehta 2681a6d818e3SYunsheng Lin hdev = ae_dev->priv; 2682a6d818e3SYunsheng Lin timer_setup(&hdev->keep_alive_timer, hclgevf_keep_alive_timer, 0); 2683a6d818e3SYunsheng Lin INIT_WORK(&hdev->keep_alive_task, hclgevf_keep_alive_task); 2684a6d818e3SYunsheng Lin 2685a6d818e3SYunsheng Lin return 0; 2686a6d818e3SYunsheng Lin } 2687a6d818e3SYunsheng Lin 26887a01c897SSalil Mehta static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 26897a01c897SSalil Mehta { 26907a01c897SSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 26917a01c897SSalil Mehta 26927a01c897SSalil Mehta hclgevf_uninit_hdev(hdev); 2693e2cb1decSSalil Mehta ae_dev->priv = NULL; 2694e2cb1decSSalil Mehta } 2695e2cb1decSSalil Mehta 2696849e4607SPeng Li static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2697849e4607SPeng Li { 2698849e4607SPeng Li struct hnae3_handle *nic = &hdev->nic; 2699849e4607SPeng Li struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2700849e4607SPeng Li 27018be73621SHuazhong Tan return min_t(u32, hdev->rss_size_max, 27028be73621SHuazhong Tan hdev->num_tqps / kinfo->num_tc); 2703849e4607SPeng Li } 2704849e4607SPeng Li 2705849e4607SPeng Li /** 2706849e4607SPeng Li * hclgevf_get_channels - Get the current channels enabled and max supported. 2707849e4607SPeng Li * @handle: hardware information for network interface 2708849e4607SPeng Li * @ch: ethtool channels structure 2709849e4607SPeng Li * 2710849e4607SPeng Li * We don't support separate tx and rx queues as channels. The other count 2711849e4607SPeng Li * represents how many queues are being used for control. max_combined counts 2712849e4607SPeng Li * how many queue pairs we can support. They may not be mapped 1 to 1 with 2713849e4607SPeng Li * q_vectors since we support a lot more queue pairs than q_vectors. 2714849e4607SPeng Li **/ 2715849e4607SPeng Li static void hclgevf_get_channels(struct hnae3_handle *handle, 2716849e4607SPeng Li struct ethtool_channels *ch) 2717849e4607SPeng Li { 2718849e4607SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2719849e4607SPeng Li 2720849e4607SPeng Li ch->max_combined = hclgevf_get_max_channels(hdev); 2721849e4607SPeng Li ch->other_count = 0; 2722849e4607SPeng Li ch->max_other = 0; 27238be73621SHuazhong Tan ch->combined_count = handle->kinfo.rss_size; 2724849e4607SPeng Li } 2725849e4607SPeng Li 2726cc719218SPeng Li static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 27270d43bf45SHuazhong Tan u16 *alloc_tqps, u16 *max_rss_size) 2728cc719218SPeng Li { 2729cc719218SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2730cc719218SPeng Li 27310d43bf45SHuazhong Tan *alloc_tqps = hdev->num_tqps; 2732cc719218SPeng Li *max_rss_size = hdev->rss_size_max; 2733cc719218SPeng Li } 2734cc719218SPeng Li 2735175ec96bSFuyun Liang static int hclgevf_get_status(struct hnae3_handle *handle) 2736175ec96bSFuyun Liang { 2737175ec96bSFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2738175ec96bSFuyun Liang 2739175ec96bSFuyun Liang return hdev->hw.mac.link; 2740175ec96bSFuyun Liang } 2741175ec96bSFuyun Liang 27424a152de9SFuyun Liang static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 27434a152de9SFuyun Liang u8 *auto_neg, u32 *speed, 27444a152de9SFuyun Liang u8 *duplex) 27454a152de9SFuyun Liang { 27464a152de9SFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27474a152de9SFuyun Liang 27484a152de9SFuyun Liang if (speed) 27494a152de9SFuyun Liang *speed = hdev->hw.mac.speed; 27504a152de9SFuyun Liang if (duplex) 27514a152de9SFuyun Liang *duplex = hdev->hw.mac.duplex; 27524a152de9SFuyun Liang if (auto_neg) 27534a152de9SFuyun Liang *auto_neg = AUTONEG_DISABLE; 27544a152de9SFuyun Liang } 27554a152de9SFuyun Liang 27564a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 27574a152de9SFuyun Liang u8 duplex) 27584a152de9SFuyun Liang { 27594a152de9SFuyun Liang hdev->hw.mac.speed = speed; 27604a152de9SFuyun Liang hdev->hw.mac.duplex = duplex; 27614a152de9SFuyun Liang } 27624a152de9SFuyun Liang 27631731be4cSYonglong Liu static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 27645c9f6b39SPeng Li { 27655c9f6b39SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27665c9f6b39SPeng Li 27675c9f6b39SPeng Li return hclgevf_config_gro(hdev, enable); 27685c9f6b39SPeng Li } 27695c9f6b39SPeng Li 277088d10bd6SJian Shen static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 277188d10bd6SJian Shen u8 *module_type) 2772c136b884SPeng Li { 2773c136b884SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 277488d10bd6SJian Shen 2775c136b884SPeng Li if (media_type) 2776c136b884SPeng Li *media_type = hdev->hw.mac.media_type; 277788d10bd6SJian Shen 277888d10bd6SJian Shen if (module_type) 277988d10bd6SJian Shen *module_type = hdev->hw.mac.module_type; 2780c136b884SPeng Li } 2781c136b884SPeng Li 27824d60291bSHuazhong Tan static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 27834d60291bSHuazhong Tan { 27844d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27854d60291bSHuazhong Tan 2786aa5c4f17SHuazhong Tan return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 27874d60291bSHuazhong Tan } 27884d60291bSHuazhong Tan 27894d60291bSHuazhong Tan static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 27904d60291bSHuazhong Tan { 27914d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27924d60291bSHuazhong Tan 27934d60291bSHuazhong Tan return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 27944d60291bSHuazhong Tan } 27954d60291bSHuazhong Tan 27964d60291bSHuazhong Tan static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 27974d60291bSHuazhong Tan { 27984d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27994d60291bSHuazhong Tan 2800c88a6e7dSHuazhong Tan return hdev->rst_stats.hw_rst_done_cnt; 28014d60291bSHuazhong Tan } 28024d60291bSHuazhong Tan 28039194d18bSliuzhongzhu static void hclgevf_get_link_mode(struct hnae3_handle *handle, 28049194d18bSliuzhongzhu unsigned long *supported, 28059194d18bSliuzhongzhu unsigned long *advertising) 28069194d18bSliuzhongzhu { 28079194d18bSliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 28089194d18bSliuzhongzhu 28099194d18bSliuzhongzhu *supported = hdev->hw.mac.supported; 28109194d18bSliuzhongzhu *advertising = hdev->hw.mac.advertising; 28119194d18bSliuzhongzhu } 28129194d18bSliuzhongzhu 28131600c3e5SJian Shen #define MAX_SEPARATE_NUM 4 28141600c3e5SJian Shen #define SEPARATOR_VALUE 0xFFFFFFFF 28151600c3e5SJian Shen #define REG_NUM_PER_LINE 4 28161600c3e5SJian Shen #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 28171600c3e5SJian Shen 28181600c3e5SJian Shen static int hclgevf_get_regs_len(struct hnae3_handle *handle) 28191600c3e5SJian Shen { 28201600c3e5SJian Shen int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 28211600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 28221600c3e5SJian Shen 28231600c3e5SJian Shen cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 28241600c3e5SJian Shen common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 28251600c3e5SJian Shen ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 28261600c3e5SJian Shen tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 28271600c3e5SJian Shen 28281600c3e5SJian Shen return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 28291600c3e5SJian Shen tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 28301600c3e5SJian Shen } 28311600c3e5SJian Shen 28321600c3e5SJian Shen static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 28331600c3e5SJian Shen void *data) 28341600c3e5SJian Shen { 28351600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 28361600c3e5SJian Shen int i, j, reg_um, separator_num; 28371600c3e5SJian Shen u32 *reg = data; 28381600c3e5SJian Shen 28391600c3e5SJian Shen *version = hdev->fw_version; 28401600c3e5SJian Shen 28411600c3e5SJian Shen /* fetching per-VF registers values from VF PCIe register space */ 28421600c3e5SJian Shen reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 28431600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 28441600c3e5SJian Shen for (i = 0; i < reg_um; i++) 28451600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 28461600c3e5SJian Shen for (i = 0; i < separator_num; i++) 28471600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 28481600c3e5SJian Shen 28491600c3e5SJian Shen reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 28501600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 28511600c3e5SJian Shen for (i = 0; i < reg_um; i++) 28521600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 28531600c3e5SJian Shen for (i = 0; i < separator_num; i++) 28541600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 28551600c3e5SJian Shen 28561600c3e5SJian Shen reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 28571600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 28581600c3e5SJian Shen for (j = 0; j < hdev->num_tqps; j++) { 28591600c3e5SJian Shen for (i = 0; i < reg_um; i++) 28601600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 28611600c3e5SJian Shen ring_reg_addr_list[i] + 28621600c3e5SJian Shen 0x200 * j); 28631600c3e5SJian Shen for (i = 0; i < separator_num; i++) 28641600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 28651600c3e5SJian Shen } 28661600c3e5SJian Shen 28671600c3e5SJian Shen reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 28681600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 28691600c3e5SJian Shen for (j = 0; j < hdev->num_msi_used - 1; j++) { 28701600c3e5SJian Shen for (i = 0; i < reg_um; i++) 28711600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 28721600c3e5SJian Shen tqp_intr_reg_addr_list[i] + 28731600c3e5SJian Shen 4 * j); 28741600c3e5SJian Shen for (i = 0; i < separator_num; i++) 28751600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 28761600c3e5SJian Shen } 28771600c3e5SJian Shen } 28781600c3e5SJian Shen 287992f11ea1SJian Shen void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 288092f11ea1SJian Shen u8 *port_base_vlan_info, u8 data_size) 288192f11ea1SJian Shen { 288292f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 288392f11ea1SJian Shen 288492f11ea1SJian Shen rtnl_lock(); 288592f11ea1SJian Shen hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 288692f11ea1SJian Shen rtnl_unlock(); 288792f11ea1SJian Shen 288892f11ea1SJian Shen /* send msg to PF and wait update port based vlan info */ 288992f11ea1SJian Shen hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 289092f11ea1SJian Shen HCLGE_MBX_PORT_BASE_VLAN_CFG, 289192f11ea1SJian Shen port_base_vlan_info, data_size, 289292f11ea1SJian Shen false, NULL, 0); 289392f11ea1SJian Shen 289492f11ea1SJian Shen if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 289592f11ea1SJian Shen nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 289692f11ea1SJian Shen else 289792f11ea1SJian Shen nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 289892f11ea1SJian Shen 289992f11ea1SJian Shen rtnl_lock(); 290092f11ea1SJian Shen hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 290192f11ea1SJian Shen rtnl_unlock(); 290292f11ea1SJian Shen } 290392f11ea1SJian Shen 2904e2cb1decSSalil Mehta static const struct hnae3_ae_ops hclgevf_ops = { 2905e2cb1decSSalil Mehta .init_ae_dev = hclgevf_init_ae_dev, 2906e2cb1decSSalil Mehta .uninit_ae_dev = hclgevf_uninit_ae_dev, 29076ff3cf07SHuazhong Tan .flr_prepare = hclgevf_flr_prepare, 29086ff3cf07SHuazhong Tan .flr_done = hclgevf_flr_done, 2909e718a93fSPeng Li .init_client_instance = hclgevf_init_client_instance, 2910e718a93fSPeng Li .uninit_client_instance = hclgevf_uninit_client_instance, 2911e2cb1decSSalil Mehta .start = hclgevf_ae_start, 2912e2cb1decSSalil Mehta .stop = hclgevf_ae_stop, 2913a6d818e3SYunsheng Lin .client_start = hclgevf_client_start, 2914a6d818e3SYunsheng Lin .client_stop = hclgevf_client_stop, 2915e2cb1decSSalil Mehta .map_ring_to_vector = hclgevf_map_ring_to_vector, 2916e2cb1decSSalil Mehta .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 2917e2cb1decSSalil Mehta .get_vector = hclgevf_get_vector, 29180d3e6631SYunsheng Lin .put_vector = hclgevf_put_vector, 2919e2cb1decSSalil Mehta .reset_queue = hclgevf_reset_tqp, 2920e2cb1decSSalil Mehta .get_mac_addr = hclgevf_get_mac_addr, 2921e2cb1decSSalil Mehta .set_mac_addr = hclgevf_set_mac_addr, 2922e2cb1decSSalil Mehta .add_uc_addr = hclgevf_add_uc_addr, 2923e2cb1decSSalil Mehta .rm_uc_addr = hclgevf_rm_uc_addr, 2924e2cb1decSSalil Mehta .add_mc_addr = hclgevf_add_mc_addr, 2925e2cb1decSSalil Mehta .rm_mc_addr = hclgevf_rm_mc_addr, 2926e2cb1decSSalil Mehta .get_stats = hclgevf_get_stats, 2927e2cb1decSSalil Mehta .update_stats = hclgevf_update_stats, 2928e2cb1decSSalil Mehta .get_strings = hclgevf_get_strings, 2929e2cb1decSSalil Mehta .get_sset_count = hclgevf_get_sset_count, 2930e2cb1decSSalil Mehta .get_rss_key_size = hclgevf_get_rss_key_size, 2931e2cb1decSSalil Mehta .get_rss_indir_size = hclgevf_get_rss_indir_size, 2932e2cb1decSSalil Mehta .get_rss = hclgevf_get_rss, 2933e2cb1decSSalil Mehta .set_rss = hclgevf_set_rss, 2934d97b3072SJian Shen .get_rss_tuple = hclgevf_get_rss_tuple, 2935d97b3072SJian Shen .set_rss_tuple = hclgevf_set_rss_tuple, 2936e2cb1decSSalil Mehta .get_tc_size = hclgevf_get_tc_size, 2937e2cb1decSSalil Mehta .get_fw_version = hclgevf_get_fw_version, 2938e2cb1decSSalil Mehta .set_vlan_filter = hclgevf_set_vlan_filter, 2939b2641e2aSYunsheng Lin .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 29406d4c3981SSalil Mehta .reset_event = hclgevf_reset_event, 2941720bd583SHuazhong Tan .set_default_reset_request = hclgevf_set_def_reset_request, 2942849e4607SPeng Li .get_channels = hclgevf_get_channels, 2943cc719218SPeng Li .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 29441600c3e5SJian Shen .get_regs_len = hclgevf_get_regs_len, 29451600c3e5SJian Shen .get_regs = hclgevf_get_regs, 2946175ec96bSFuyun Liang .get_status = hclgevf_get_status, 29474a152de9SFuyun Liang .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 2948c136b884SPeng Li .get_media_type = hclgevf_get_media_type, 29494d60291bSHuazhong Tan .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 29504d60291bSHuazhong Tan .ae_dev_resetting = hclgevf_ae_dev_resetting, 29514d60291bSHuazhong Tan .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 29525c9f6b39SPeng Li .set_gro_en = hclgevf_gro_en, 2953818f1675SYunsheng Lin .set_mtu = hclgevf_set_mtu, 29540c29d191Sliuzhongzhu .get_global_queue_id = hclgevf_get_qid_global, 29558cdb992fSJian Shen .set_timer_task = hclgevf_set_timer_task, 29569194d18bSliuzhongzhu .get_link_mode = hclgevf_get_link_mode, 2957e2cb1decSSalil Mehta }; 2958e2cb1decSSalil Mehta 2959e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf = { 2960e2cb1decSSalil Mehta .ops = &hclgevf_ops, 2961e2cb1decSSalil Mehta .pdev_id_table = ae_algovf_pci_tbl, 2962e2cb1decSSalil Mehta }; 2963e2cb1decSSalil Mehta 2964e2cb1decSSalil Mehta static int hclgevf_init(void) 2965e2cb1decSSalil Mehta { 2966e2cb1decSSalil Mehta pr_info("%s is initializing\n", HCLGEVF_NAME); 2967e2cb1decSSalil Mehta 2968854cf33aSFuyun Liang hnae3_register_ae_algo(&ae_algovf); 2969854cf33aSFuyun Liang 2970854cf33aSFuyun Liang return 0; 2971e2cb1decSSalil Mehta } 2972e2cb1decSSalil Mehta 2973e2cb1decSSalil Mehta static void hclgevf_exit(void) 2974e2cb1decSSalil Mehta { 2975e2cb1decSSalil Mehta hnae3_unregister_ae_algo(&ae_algovf); 2976e2cb1decSSalil Mehta } 2977e2cb1decSSalil Mehta module_init(hclgevf_init); 2978e2cb1decSSalil Mehta module_exit(hclgevf_exit); 2979e2cb1decSSalil Mehta 2980e2cb1decSSalil Mehta MODULE_LICENSE("GPL"); 2981e2cb1decSSalil Mehta MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 2982e2cb1decSSalil Mehta MODULE_DESCRIPTION("HCLGEVF Driver"); 2983e2cb1decSSalil Mehta MODULE_VERSION(HCLGEVF_MOD_VERSION); 2984