1e2cb1decSSalil Mehta // SPDX-License-Identifier: GPL-2.0+ 2e2cb1decSSalil Mehta // Copyright (c) 2016-2017 Hisilicon Limited. 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #include <linux/etherdevice.h> 5aa5c4f17SHuazhong Tan #include <linux/iopoll.h> 66988eb2aSSalil Mehta #include <net/rtnetlink.h> 7e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 8e2cb1decSSalil Mehta #include "hclgevf_main.h" 9e2cb1decSSalil Mehta #include "hclge_mbx.h" 10e2cb1decSSalil Mehta #include "hnae3.h" 11e2cb1decSSalil Mehta 12e2cb1decSSalil Mehta #define HCLGEVF_NAME "hclgevf" 13e2cb1decSSalil Mehta 14bbe6540eSHuazhong Tan #define HCLGEVF_RESET_MAX_FAIL_CNT 5 15bbe6540eSHuazhong Tan 169c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 17e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf; 18e2cb1decSSalil Mehta 19e2cb1decSSalil Mehta static const struct pci_device_id ae_algovf_pci_tbl[] = { 20e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 21e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 22e2cb1decSSalil Mehta /* required last entry */ 23e2cb1decSSalil Mehta {0, } 24e2cb1decSSalil Mehta }; 25e2cb1decSSalil Mehta 26472d7eceSJian Shen static const u8 hclgevf_hash_key[] = { 27472d7eceSJian Shen 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 28472d7eceSJian Shen 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 29472d7eceSJian Shen 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 30472d7eceSJian Shen 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 31472d7eceSJian Shen 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 32472d7eceSJian Shen }; 33472d7eceSJian Shen 342f550a46SYunsheng Lin MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 352f550a46SYunsheng Lin 361600c3e5SJian Shen static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 371600c3e5SJian Shen HCLGEVF_CMDQ_TX_ADDR_H_REG, 381600c3e5SJian Shen HCLGEVF_CMDQ_TX_DEPTH_REG, 391600c3e5SJian Shen HCLGEVF_CMDQ_TX_TAIL_REG, 401600c3e5SJian Shen HCLGEVF_CMDQ_TX_HEAD_REG, 411600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_L_REG, 421600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_H_REG, 431600c3e5SJian Shen HCLGEVF_CMDQ_RX_DEPTH_REG, 441600c3e5SJian Shen HCLGEVF_CMDQ_RX_TAIL_REG, 451600c3e5SJian Shen HCLGEVF_CMDQ_RX_HEAD_REG, 461600c3e5SJian Shen HCLGEVF_VECTOR0_CMDQ_SRC_REG, 471600c3e5SJian Shen HCLGEVF_CMDQ_INTR_STS_REG, 481600c3e5SJian Shen HCLGEVF_CMDQ_INTR_EN_REG, 491600c3e5SJian Shen HCLGEVF_CMDQ_INTR_GEN_REG}; 501600c3e5SJian Shen 511600c3e5SJian Shen static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 521600c3e5SJian Shen HCLGEVF_RST_ING, 531600c3e5SJian Shen HCLGEVF_GRO_EN_REG}; 541600c3e5SJian Shen 551600c3e5SJian Shen static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 561600c3e5SJian Shen HCLGEVF_RING_RX_ADDR_H_REG, 571600c3e5SJian Shen HCLGEVF_RING_RX_BD_NUM_REG, 581600c3e5SJian Shen HCLGEVF_RING_RX_BD_LENGTH_REG, 591600c3e5SJian Shen HCLGEVF_RING_RX_MERGE_EN_REG, 601600c3e5SJian Shen HCLGEVF_RING_RX_TAIL_REG, 611600c3e5SJian Shen HCLGEVF_RING_RX_HEAD_REG, 621600c3e5SJian Shen HCLGEVF_RING_RX_FBD_NUM_REG, 631600c3e5SJian Shen HCLGEVF_RING_RX_OFFSET_REG, 641600c3e5SJian Shen HCLGEVF_RING_RX_FBD_OFFSET_REG, 651600c3e5SJian Shen HCLGEVF_RING_RX_STASH_REG, 661600c3e5SJian Shen HCLGEVF_RING_RX_BD_ERR_REG, 671600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_L_REG, 681600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_H_REG, 691600c3e5SJian Shen HCLGEVF_RING_TX_BD_NUM_REG, 701600c3e5SJian Shen HCLGEVF_RING_TX_PRIORITY_REG, 711600c3e5SJian Shen HCLGEVF_RING_TX_TC_REG, 721600c3e5SJian Shen HCLGEVF_RING_TX_MERGE_EN_REG, 731600c3e5SJian Shen HCLGEVF_RING_TX_TAIL_REG, 741600c3e5SJian Shen HCLGEVF_RING_TX_HEAD_REG, 751600c3e5SJian Shen HCLGEVF_RING_TX_FBD_NUM_REG, 761600c3e5SJian Shen HCLGEVF_RING_TX_OFFSET_REG, 771600c3e5SJian Shen HCLGEVF_RING_TX_EBD_NUM_REG, 781600c3e5SJian Shen HCLGEVF_RING_TX_EBD_OFFSET_REG, 791600c3e5SJian Shen HCLGEVF_RING_TX_BD_ERR_REG, 801600c3e5SJian Shen HCLGEVF_RING_EN_REG}; 811600c3e5SJian Shen 821600c3e5SJian Shen static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 831600c3e5SJian Shen HCLGEVF_TQP_INTR_GL0_REG, 841600c3e5SJian Shen HCLGEVF_TQP_INTR_GL1_REG, 851600c3e5SJian Shen HCLGEVF_TQP_INTR_GL2_REG, 861600c3e5SJian Shen HCLGEVF_TQP_INTR_RL_REG}; 871600c3e5SJian Shen 889b2f3477SWeihang Li static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 89e2cb1decSSalil Mehta { 90eed9535fSPeng Li if (!handle->client) 91eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, nic); 92eed9535fSPeng Li else if (handle->client->type == HNAE3_CLIENT_ROCE) 93eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, roce); 94eed9535fSPeng Li else 95e2cb1decSSalil Mehta return container_of(handle, struct hclgevf_dev, nic); 96e2cb1decSSalil Mehta } 97e2cb1decSSalil Mehta 98e2cb1decSSalil Mehta static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 99e2cb1decSSalil Mehta { 100b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 101e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 102e2cb1decSSalil Mehta struct hclgevf_desc desc; 103e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 104e2cb1decSSalil Mehta int status; 105e2cb1decSSalil Mehta int i; 106e2cb1decSSalil Mehta 107b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 108b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 109e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 110e2cb1decSSalil Mehta HCLGEVF_OPC_QUERY_RX_STATUS, 111e2cb1decSSalil Mehta true); 112e2cb1decSSalil Mehta 113e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 114e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 115e2cb1decSSalil Mehta if (status) { 116e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 117e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 118e2cb1decSSalil Mehta status, i); 119e2cb1decSSalil Mehta return status; 120e2cb1decSSalil Mehta } 121e2cb1decSSalil Mehta tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 122cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 123e2cb1decSSalil Mehta 124e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 125e2cb1decSSalil Mehta true); 126e2cb1decSSalil Mehta 127e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 128e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 129e2cb1decSSalil Mehta if (status) { 130e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 131e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 132e2cb1decSSalil Mehta status, i); 133e2cb1decSSalil Mehta return status; 134e2cb1decSSalil Mehta } 135e2cb1decSSalil Mehta tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 136cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 137e2cb1decSSalil Mehta } 138e2cb1decSSalil Mehta 139e2cb1decSSalil Mehta return 0; 140e2cb1decSSalil Mehta } 141e2cb1decSSalil Mehta 142e2cb1decSSalil Mehta static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 143e2cb1decSSalil Mehta { 144e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo = &handle->kinfo; 145e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 146e2cb1decSSalil Mehta u64 *buff = data; 147e2cb1decSSalil Mehta int i; 148e2cb1decSSalil Mehta 149b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 150b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 151e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 152e2cb1decSSalil Mehta } 153e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 154b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 155e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 156e2cb1decSSalil Mehta } 157e2cb1decSSalil Mehta 158e2cb1decSSalil Mehta return buff; 159e2cb1decSSalil Mehta } 160e2cb1decSSalil Mehta 161e2cb1decSSalil Mehta static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 162e2cb1decSSalil Mehta { 163b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 164e2cb1decSSalil Mehta 165b4f1d303SJian Shen return kinfo->num_tqps * 2; 166e2cb1decSSalil Mehta } 167e2cb1decSSalil Mehta 168e2cb1decSSalil Mehta static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 169e2cb1decSSalil Mehta { 170b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 171e2cb1decSSalil Mehta u8 *buff = data; 172e2cb1decSSalil Mehta int i = 0; 173e2cb1decSSalil Mehta 174b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 175b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 176e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1770c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 178e2cb1decSSalil Mehta tqp->index); 179e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 180e2cb1decSSalil Mehta } 181e2cb1decSSalil Mehta 182b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 183b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 184e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1850c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 186e2cb1decSSalil Mehta tqp->index); 187e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 188e2cb1decSSalil Mehta } 189e2cb1decSSalil Mehta 190e2cb1decSSalil Mehta return buff; 191e2cb1decSSalil Mehta } 192e2cb1decSSalil Mehta 193e2cb1decSSalil Mehta static void hclgevf_update_stats(struct hnae3_handle *handle, 194e2cb1decSSalil Mehta struct net_device_stats *net_stats) 195e2cb1decSSalil Mehta { 196e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 197e2cb1decSSalil Mehta int status; 198e2cb1decSSalil Mehta 199e2cb1decSSalil Mehta status = hclgevf_tqps_update_stats(handle); 200e2cb1decSSalil Mehta if (status) 201e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 202e2cb1decSSalil Mehta "VF update of TQPS stats fail, status = %d.\n", 203e2cb1decSSalil Mehta status); 204e2cb1decSSalil Mehta } 205e2cb1decSSalil Mehta 206e2cb1decSSalil Mehta static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 207e2cb1decSSalil Mehta { 208e2cb1decSSalil Mehta if (strset == ETH_SS_TEST) 209e2cb1decSSalil Mehta return -EOPNOTSUPP; 210e2cb1decSSalil Mehta else if (strset == ETH_SS_STATS) 211e2cb1decSSalil Mehta return hclgevf_tqps_get_sset_count(handle, strset); 212e2cb1decSSalil Mehta 213e2cb1decSSalil Mehta return 0; 214e2cb1decSSalil Mehta } 215e2cb1decSSalil Mehta 216e2cb1decSSalil Mehta static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 217e2cb1decSSalil Mehta u8 *data) 218e2cb1decSSalil Mehta { 219e2cb1decSSalil Mehta u8 *p = (char *)data; 220e2cb1decSSalil Mehta 221e2cb1decSSalil Mehta if (strset == ETH_SS_STATS) 222e2cb1decSSalil Mehta p = hclgevf_tqps_get_strings(handle, p); 223e2cb1decSSalil Mehta } 224e2cb1decSSalil Mehta 225e2cb1decSSalil Mehta static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 226e2cb1decSSalil Mehta { 227e2cb1decSSalil Mehta hclgevf_tqps_get_stats(handle, data); 228e2cb1decSSalil Mehta } 229e2cb1decSSalil Mehta 230e2cb1decSSalil Mehta static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 231e2cb1decSSalil Mehta { 232e2cb1decSSalil Mehta u8 resp_msg; 233e2cb1decSSalil Mehta int status; 234e2cb1decSSalil Mehta 235e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 23663cbf7a9SYufeng Mo true, &resp_msg, sizeof(resp_msg)); 237e2cb1decSSalil Mehta if (status) { 238e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 239e2cb1decSSalil Mehta "VF request to get TC info from PF failed %d", 240e2cb1decSSalil Mehta status); 241e2cb1decSSalil Mehta return status; 242e2cb1decSSalil Mehta } 243e2cb1decSSalil Mehta 244e2cb1decSSalil Mehta hdev->hw_tc_map = resp_msg; 245e2cb1decSSalil Mehta 246e2cb1decSSalil Mehta return 0; 247e2cb1decSSalil Mehta } 248e2cb1decSSalil Mehta 24992f11ea1SJian Shen static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 25092f11ea1SJian Shen { 25192f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 25292f11ea1SJian Shen u8 resp_msg; 25392f11ea1SJian Shen int ret; 25492f11ea1SJian Shen 25592f11ea1SJian Shen ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 25692f11ea1SJian Shen HCLGE_MBX_GET_PORT_BASE_VLAN_STATE, 25792f11ea1SJian Shen NULL, 0, true, &resp_msg, sizeof(u8)); 25892f11ea1SJian Shen if (ret) { 25992f11ea1SJian Shen dev_err(&hdev->pdev->dev, 26092f11ea1SJian Shen "VF request to get port based vlan state failed %d", 26192f11ea1SJian Shen ret); 26292f11ea1SJian Shen return ret; 26392f11ea1SJian Shen } 26492f11ea1SJian Shen 26592f11ea1SJian Shen nic->port_base_vlan_state = resp_msg; 26692f11ea1SJian Shen 26792f11ea1SJian Shen return 0; 26892f11ea1SJian Shen } 26992f11ea1SJian Shen 2706cee6fc3SJian Shen static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 271e2cb1decSSalil Mehta { 272c0425944SPeng Li #define HCLGEVF_TQPS_RSS_INFO_LEN 6 273e2cb1decSSalil Mehta u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 274e2cb1decSSalil Mehta int status; 275e2cb1decSSalil Mehta 276e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 277e2cb1decSSalil Mehta true, resp_msg, 278e2cb1decSSalil Mehta HCLGEVF_TQPS_RSS_INFO_LEN); 279e2cb1decSSalil Mehta if (status) { 280e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 281e2cb1decSSalil Mehta "VF request to get tqp info from PF failed %d", 282e2cb1decSSalil Mehta status); 283e2cb1decSSalil Mehta return status; 284e2cb1decSSalil Mehta } 285e2cb1decSSalil Mehta 286e2cb1decSSalil Mehta memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 287e2cb1decSSalil Mehta memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 288c0425944SPeng Li memcpy(&hdev->rx_buf_len, &resp_msg[4], sizeof(u16)); 289c0425944SPeng Li 290c0425944SPeng Li return 0; 291c0425944SPeng Li } 292c0425944SPeng Li 293c0425944SPeng Li static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 294c0425944SPeng Li { 295c0425944SPeng Li #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 296c0425944SPeng Li u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 297c0425944SPeng Li int ret; 298c0425944SPeng Li 299c0425944SPeng Li ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QDEPTH, 0, NULL, 0, 300c0425944SPeng Li true, resp_msg, 301c0425944SPeng Li HCLGEVF_TQPS_DEPTH_INFO_LEN); 302c0425944SPeng Li if (ret) { 303c0425944SPeng Li dev_err(&hdev->pdev->dev, 304c0425944SPeng Li "VF request to get tqp depth info from PF failed %d", 305c0425944SPeng Li ret); 306c0425944SPeng Li return ret; 307c0425944SPeng Li } 308c0425944SPeng Li 309c0425944SPeng Li memcpy(&hdev->num_tx_desc, &resp_msg[0], sizeof(u16)); 310c0425944SPeng Li memcpy(&hdev->num_rx_desc, &resp_msg[2], sizeof(u16)); 311e2cb1decSSalil Mehta 312e2cb1decSSalil Mehta return 0; 313e2cb1decSSalil Mehta } 314e2cb1decSSalil Mehta 3150c29d191Sliuzhongzhu static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 3160c29d191Sliuzhongzhu { 3170c29d191Sliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3180c29d191Sliuzhongzhu u8 msg_data[2], resp_data[2]; 3190c29d191Sliuzhongzhu u16 qid_in_pf = 0; 3200c29d191Sliuzhongzhu int ret; 3210c29d191Sliuzhongzhu 3220c29d191Sliuzhongzhu memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 3230c29d191Sliuzhongzhu 3240c29d191Sliuzhongzhu ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data, 32563cbf7a9SYufeng Mo sizeof(msg_data), true, resp_data, 32663cbf7a9SYufeng Mo sizeof(resp_data)); 3270c29d191Sliuzhongzhu if (!ret) 3280c29d191Sliuzhongzhu qid_in_pf = *(u16 *)resp_data; 3290c29d191Sliuzhongzhu 3300c29d191Sliuzhongzhu return qid_in_pf; 3310c29d191Sliuzhongzhu } 3320c29d191Sliuzhongzhu 3339c3e7130Sliuzhongzhu static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 3349c3e7130Sliuzhongzhu { 33588d10bd6SJian Shen u8 resp_msg[2]; 3369c3e7130Sliuzhongzhu int ret; 3379c3e7130Sliuzhongzhu 3389c3e7130Sliuzhongzhu ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_MEDIA_TYPE, 0, NULL, 0, 33988d10bd6SJian Shen true, resp_msg, sizeof(resp_msg)); 3409c3e7130Sliuzhongzhu if (ret) { 3419c3e7130Sliuzhongzhu dev_err(&hdev->pdev->dev, 3429c3e7130Sliuzhongzhu "VF request to get the pf port media type failed %d", 3439c3e7130Sliuzhongzhu ret); 3449c3e7130Sliuzhongzhu return ret; 3459c3e7130Sliuzhongzhu } 3469c3e7130Sliuzhongzhu 34788d10bd6SJian Shen hdev->hw.mac.media_type = resp_msg[0]; 34888d10bd6SJian Shen hdev->hw.mac.module_type = resp_msg[1]; 3499c3e7130Sliuzhongzhu 3509c3e7130Sliuzhongzhu return 0; 3519c3e7130Sliuzhongzhu } 3529c3e7130Sliuzhongzhu 353e2cb1decSSalil Mehta static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 354e2cb1decSSalil Mehta { 355e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 356e2cb1decSSalil Mehta int i; 357e2cb1decSSalil Mehta 358e2cb1decSSalil Mehta hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 359e2cb1decSSalil Mehta sizeof(struct hclgevf_tqp), GFP_KERNEL); 360e2cb1decSSalil Mehta if (!hdev->htqp) 361e2cb1decSSalil Mehta return -ENOMEM; 362e2cb1decSSalil Mehta 363e2cb1decSSalil Mehta tqp = hdev->htqp; 364e2cb1decSSalil Mehta 365e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 366e2cb1decSSalil Mehta tqp->dev = &hdev->pdev->dev; 367e2cb1decSSalil Mehta tqp->index = i; 368e2cb1decSSalil Mehta 369e2cb1decSSalil Mehta tqp->q.ae_algo = &ae_algovf; 370e2cb1decSSalil Mehta tqp->q.buf_size = hdev->rx_buf_len; 371c0425944SPeng Li tqp->q.tx_desc_num = hdev->num_tx_desc; 372c0425944SPeng Li tqp->q.rx_desc_num = hdev->num_rx_desc; 373e2cb1decSSalil Mehta tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 374e2cb1decSSalil Mehta i * HCLGEVF_TQP_REG_SIZE; 375e2cb1decSSalil Mehta 376e2cb1decSSalil Mehta tqp++; 377e2cb1decSSalil Mehta } 378e2cb1decSSalil Mehta 379e2cb1decSSalil Mehta return 0; 380e2cb1decSSalil Mehta } 381e2cb1decSSalil Mehta 382e2cb1decSSalil Mehta static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 383e2cb1decSSalil Mehta { 384e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 385e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo; 386e2cb1decSSalil Mehta u16 new_tqps = hdev->num_tqps; 387ebaf1908SWeihang Li unsigned int i; 388e2cb1decSSalil Mehta 389e2cb1decSSalil Mehta kinfo = &nic->kinfo; 390e2cb1decSSalil Mehta kinfo->num_tc = 0; 391c0425944SPeng Li kinfo->num_tx_desc = hdev->num_tx_desc; 392c0425944SPeng Li kinfo->num_rx_desc = hdev->num_rx_desc; 393e2cb1decSSalil Mehta kinfo->rx_buf_len = hdev->rx_buf_len; 394e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 395e2cb1decSSalil Mehta if (hdev->hw_tc_map & BIT(i)) 396e2cb1decSSalil Mehta kinfo->num_tc++; 397e2cb1decSSalil Mehta 398e2cb1decSSalil Mehta kinfo->rss_size 399e2cb1decSSalil Mehta = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 400e2cb1decSSalil Mehta new_tqps = kinfo->rss_size * kinfo->num_tc; 401e2cb1decSSalil Mehta kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 402e2cb1decSSalil Mehta 403e2cb1decSSalil Mehta kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 404e2cb1decSSalil Mehta sizeof(struct hnae3_queue *), GFP_KERNEL); 405e2cb1decSSalil Mehta if (!kinfo->tqp) 406e2cb1decSSalil Mehta return -ENOMEM; 407e2cb1decSSalil Mehta 408e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 409e2cb1decSSalil Mehta hdev->htqp[i].q.handle = &hdev->nic; 410e2cb1decSSalil Mehta hdev->htqp[i].q.tqp_index = i; 411e2cb1decSSalil Mehta kinfo->tqp[i] = &hdev->htqp[i].q; 412e2cb1decSSalil Mehta } 413e2cb1decSSalil Mehta 414e2cb1decSSalil Mehta return 0; 415e2cb1decSSalil Mehta } 416e2cb1decSSalil Mehta 417e2cb1decSSalil Mehta static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 418e2cb1decSSalil Mehta { 419e2cb1decSSalil Mehta int status; 420e2cb1decSSalil Mehta u8 resp_msg; 421e2cb1decSSalil Mehta 422e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 42363cbf7a9SYufeng Mo 0, false, &resp_msg, sizeof(resp_msg)); 424e2cb1decSSalil Mehta if (status) 425e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 426e2cb1decSSalil Mehta "VF failed to fetch link status(%d) from PF", status); 427e2cb1decSSalil Mehta } 428e2cb1decSSalil Mehta 429e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 430e2cb1decSSalil Mehta { 43145e92b7eSPeng Li struct hnae3_handle *rhandle = &hdev->roce; 432e2cb1decSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 43345e92b7eSPeng Li struct hnae3_client *rclient; 434e2cb1decSSalil Mehta struct hnae3_client *client; 435e2cb1decSSalil Mehta 436e2cb1decSSalil Mehta client = handle->client; 43745e92b7eSPeng Li rclient = hdev->roce_client; 438e2cb1decSSalil Mehta 439582d37bbSPeng Li link_state = 440582d37bbSPeng Li test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 441582d37bbSPeng Li 442e2cb1decSSalil Mehta if (link_state != hdev->hw.mac.link) { 443e2cb1decSSalil Mehta client->ops->link_status_change(handle, !!link_state); 44445e92b7eSPeng Li if (rclient && rclient->ops->link_status_change) 44545e92b7eSPeng Li rclient->ops->link_status_change(rhandle, !!link_state); 446e2cb1decSSalil Mehta hdev->hw.mac.link = link_state; 447e2cb1decSSalil Mehta } 448e2cb1decSSalil Mehta } 449e2cb1decSSalil Mehta 450538abaf3SYueHaibing static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 4519194d18bSliuzhongzhu { 4529194d18bSliuzhongzhu #define HCLGEVF_ADVERTISING 0 4539194d18bSliuzhongzhu #define HCLGEVF_SUPPORTED 1 4549194d18bSliuzhongzhu u8 send_msg; 4559194d18bSliuzhongzhu u8 resp_msg; 4569194d18bSliuzhongzhu 4579194d18bSliuzhongzhu send_msg = HCLGEVF_ADVERTISING; 45863cbf7a9SYufeng Mo hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 45963cbf7a9SYufeng Mo &send_msg, sizeof(send_msg), false, 46063cbf7a9SYufeng Mo &resp_msg, sizeof(resp_msg)); 4619194d18bSliuzhongzhu send_msg = HCLGEVF_SUPPORTED; 46263cbf7a9SYufeng Mo hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 46363cbf7a9SYufeng Mo &send_msg, sizeof(send_msg), false, 46463cbf7a9SYufeng Mo &resp_msg, sizeof(resp_msg)); 4659194d18bSliuzhongzhu } 4669194d18bSliuzhongzhu 467e2cb1decSSalil Mehta static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 468e2cb1decSSalil Mehta { 469e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 470e2cb1decSSalil Mehta int ret; 471e2cb1decSSalil Mehta 472e2cb1decSSalil Mehta nic->ae_algo = &ae_algovf; 473e2cb1decSSalil Mehta nic->pdev = hdev->pdev; 474e2cb1decSSalil Mehta nic->numa_node_mask = hdev->numa_node_mask; 475424eb834SSalil Mehta nic->flags |= HNAE3_SUPPORT_VF; 476e2cb1decSSalil Mehta 477e2cb1decSSalil Mehta ret = hclgevf_knic_setup(hdev); 478e2cb1decSSalil Mehta if (ret) 479e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 480e2cb1decSSalil Mehta ret); 481e2cb1decSSalil Mehta return ret; 482e2cb1decSSalil Mehta } 483e2cb1decSSalil Mehta 484e2cb1decSSalil Mehta static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 485e2cb1decSSalil Mehta { 48636cbbdf6SPeng Li if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 48736cbbdf6SPeng Li dev_warn(&hdev->pdev->dev, 48836cbbdf6SPeng Li "vector(vector_id %d) has been freed.\n", vector_id); 48936cbbdf6SPeng Li return; 49036cbbdf6SPeng Li } 49136cbbdf6SPeng Li 492e2cb1decSSalil Mehta hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 493e2cb1decSSalil Mehta hdev->num_msi_left += 1; 494e2cb1decSSalil Mehta hdev->num_msi_used -= 1; 495e2cb1decSSalil Mehta } 496e2cb1decSSalil Mehta 497e2cb1decSSalil Mehta static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 498e2cb1decSSalil Mehta struct hnae3_vector_info *vector_info) 499e2cb1decSSalil Mehta { 500e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 501e2cb1decSSalil Mehta struct hnae3_vector_info *vector = vector_info; 502e2cb1decSSalil Mehta int alloc = 0; 503e2cb1decSSalil Mehta int i, j; 504e2cb1decSSalil Mehta 505e2cb1decSSalil Mehta vector_num = min(hdev->num_msi_left, vector_num); 506e2cb1decSSalil Mehta 507e2cb1decSSalil Mehta for (j = 0; j < vector_num; j++) { 508e2cb1decSSalil Mehta for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 509e2cb1decSSalil Mehta if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 510e2cb1decSSalil Mehta vector->vector = pci_irq_vector(hdev->pdev, i); 511e2cb1decSSalil Mehta vector->io_addr = hdev->hw.io_base + 512e2cb1decSSalil Mehta HCLGEVF_VECTOR_REG_BASE + 513e2cb1decSSalil Mehta (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 514e2cb1decSSalil Mehta hdev->vector_status[i] = 0; 515e2cb1decSSalil Mehta hdev->vector_irq[i] = vector->vector; 516e2cb1decSSalil Mehta 517e2cb1decSSalil Mehta vector++; 518e2cb1decSSalil Mehta alloc++; 519e2cb1decSSalil Mehta 520e2cb1decSSalil Mehta break; 521e2cb1decSSalil Mehta } 522e2cb1decSSalil Mehta } 523e2cb1decSSalil Mehta } 524e2cb1decSSalil Mehta hdev->num_msi_left -= alloc; 525e2cb1decSSalil Mehta hdev->num_msi_used += alloc; 526e2cb1decSSalil Mehta 527e2cb1decSSalil Mehta return alloc; 528e2cb1decSSalil Mehta } 529e2cb1decSSalil Mehta 530e2cb1decSSalil Mehta static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 531e2cb1decSSalil Mehta { 532e2cb1decSSalil Mehta int i; 533e2cb1decSSalil Mehta 534e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 535e2cb1decSSalil Mehta if (vector == hdev->vector_irq[i]) 536e2cb1decSSalil Mehta return i; 537e2cb1decSSalil Mehta 538e2cb1decSSalil Mehta return -EINVAL; 539e2cb1decSSalil Mehta } 540e2cb1decSSalil Mehta 541374ad291SJian Shen static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 542374ad291SJian Shen const u8 hfunc, const u8 *key) 543374ad291SJian Shen { 544374ad291SJian Shen struct hclgevf_rss_config_cmd *req; 545ebaf1908SWeihang Li unsigned int key_offset = 0; 546374ad291SJian Shen struct hclgevf_desc desc; 5473caf772bSYufeng Mo int key_counts; 548374ad291SJian Shen int key_size; 549374ad291SJian Shen int ret; 550374ad291SJian Shen 5513caf772bSYufeng Mo key_counts = HCLGEVF_RSS_KEY_SIZE; 552374ad291SJian Shen req = (struct hclgevf_rss_config_cmd *)desc.data; 553374ad291SJian Shen 5543caf772bSYufeng Mo while (key_counts) { 555374ad291SJian Shen hclgevf_cmd_setup_basic_desc(&desc, 556374ad291SJian Shen HCLGEVF_OPC_RSS_GENERIC_CONFIG, 557374ad291SJian Shen false); 558374ad291SJian Shen 559374ad291SJian Shen req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 560374ad291SJian Shen req->hash_config |= 561374ad291SJian Shen (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 562374ad291SJian Shen 5633caf772bSYufeng Mo key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts); 564374ad291SJian Shen memcpy(req->hash_key, 565374ad291SJian Shen key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 566374ad291SJian Shen 5673caf772bSYufeng Mo key_counts -= key_size; 5683caf772bSYufeng Mo key_offset++; 569374ad291SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 570374ad291SJian Shen if (ret) { 571374ad291SJian Shen dev_err(&hdev->pdev->dev, 572374ad291SJian Shen "Configure RSS config fail, status = %d\n", 573374ad291SJian Shen ret); 574374ad291SJian Shen return ret; 575374ad291SJian Shen } 576374ad291SJian Shen } 577374ad291SJian Shen 578374ad291SJian Shen return 0; 579374ad291SJian Shen } 580374ad291SJian Shen 581e2cb1decSSalil Mehta static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 582e2cb1decSSalil Mehta { 583e2cb1decSSalil Mehta return HCLGEVF_RSS_KEY_SIZE; 584e2cb1decSSalil Mehta } 585e2cb1decSSalil Mehta 586e2cb1decSSalil Mehta static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 587e2cb1decSSalil Mehta { 588e2cb1decSSalil Mehta return HCLGEVF_RSS_IND_TBL_SIZE; 589e2cb1decSSalil Mehta } 590e2cb1decSSalil Mehta 591e2cb1decSSalil Mehta static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 592e2cb1decSSalil Mehta { 593e2cb1decSSalil Mehta const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 594e2cb1decSSalil Mehta struct hclgevf_rss_indirection_table_cmd *req; 595e2cb1decSSalil Mehta struct hclgevf_desc desc; 596e2cb1decSSalil Mehta int status; 597e2cb1decSSalil Mehta int i, j; 598e2cb1decSSalil Mehta 599e2cb1decSSalil Mehta req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 600e2cb1decSSalil Mehta 601e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 602e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 603e2cb1decSSalil Mehta false); 604e2cb1decSSalil Mehta req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 605e2cb1decSSalil Mehta req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 606e2cb1decSSalil Mehta for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 607e2cb1decSSalil Mehta req->rss_result[j] = 608e2cb1decSSalil Mehta indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 609e2cb1decSSalil Mehta 610e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 611e2cb1decSSalil Mehta if (status) { 612e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 613e2cb1decSSalil Mehta "VF failed(=%d) to set RSS indirection table\n", 614e2cb1decSSalil Mehta status); 615e2cb1decSSalil Mehta return status; 616e2cb1decSSalil Mehta } 617e2cb1decSSalil Mehta } 618e2cb1decSSalil Mehta 619e2cb1decSSalil Mehta return 0; 620e2cb1decSSalil Mehta } 621e2cb1decSSalil Mehta 622e2cb1decSSalil Mehta static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 623e2cb1decSSalil Mehta { 624e2cb1decSSalil Mehta struct hclgevf_rss_tc_mode_cmd *req; 625e2cb1decSSalil Mehta u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 626e2cb1decSSalil Mehta u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 627e2cb1decSSalil Mehta u16 tc_size[HCLGEVF_MAX_TC_NUM]; 628e2cb1decSSalil Mehta struct hclgevf_desc desc; 629e2cb1decSSalil Mehta u16 roundup_size; 630e2cb1decSSalil Mehta int status; 631ebaf1908SWeihang Li unsigned int i; 632e2cb1decSSalil Mehta 633e2cb1decSSalil Mehta req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 634e2cb1decSSalil Mehta 635e2cb1decSSalil Mehta roundup_size = roundup_pow_of_two(rss_size); 636e2cb1decSSalil Mehta roundup_size = ilog2(roundup_size); 637e2cb1decSSalil Mehta 638e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 639e2cb1decSSalil Mehta tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 640e2cb1decSSalil Mehta tc_size[i] = roundup_size; 641e2cb1decSSalil Mehta tc_offset[i] = rss_size * i; 642e2cb1decSSalil Mehta } 643e2cb1decSSalil Mehta 644e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 645e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 646e4e87715SPeng Li hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 647e2cb1decSSalil Mehta (tc_valid[i] & 0x1)); 648e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 649e2cb1decSSalil Mehta HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 650e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 651e2cb1decSSalil Mehta HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 652e2cb1decSSalil Mehta } 653e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 654e2cb1decSSalil Mehta if (status) 655e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 656e2cb1decSSalil Mehta "VF failed(=%d) to set rss tc mode\n", status); 657e2cb1decSSalil Mehta 658e2cb1decSSalil Mehta return status; 659e2cb1decSSalil Mehta } 660e2cb1decSSalil Mehta 661a638b1d8SJian Shen /* for revision 0x20, vf shared the same rss config with pf */ 662a638b1d8SJian Shen static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 663a638b1d8SJian Shen { 664a638b1d8SJian Shen #define HCLGEVF_RSS_MBX_RESP_LEN 8 665a638b1d8SJian Shen 666a638b1d8SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 667a638b1d8SJian Shen u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 668a638b1d8SJian Shen u16 msg_num, hash_key_index; 669a638b1d8SJian Shen u8 index; 670a638b1d8SJian Shen int ret; 671a638b1d8SJian Shen 672a638b1d8SJian Shen msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 673a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN; 674a638b1d8SJian Shen for (index = 0; index < msg_num; index++) { 675a638b1d8SJian Shen ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_RSS_KEY, 0, 676a638b1d8SJian Shen &index, sizeof(index), 677a638b1d8SJian Shen true, resp_msg, 678a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN); 679a638b1d8SJian Shen if (ret) { 680a638b1d8SJian Shen dev_err(&hdev->pdev->dev, 681a638b1d8SJian Shen "VF get rss hash key from PF failed, ret=%d", 682a638b1d8SJian Shen ret); 683a638b1d8SJian Shen return ret; 684a638b1d8SJian Shen } 685a638b1d8SJian Shen 686a638b1d8SJian Shen hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 687a638b1d8SJian Shen if (index == msg_num - 1) 688a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 689a638b1d8SJian Shen &resp_msg[0], 690a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE - hash_key_index); 691a638b1d8SJian Shen else 692a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 693a638b1d8SJian Shen &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 694a638b1d8SJian Shen } 695a638b1d8SJian Shen 696a638b1d8SJian Shen return 0; 697a638b1d8SJian Shen } 698a638b1d8SJian Shen 699e2cb1decSSalil Mehta static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 700e2cb1decSSalil Mehta u8 *hfunc) 701e2cb1decSSalil Mehta { 702e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 703e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 704a638b1d8SJian Shen int i, ret; 705e2cb1decSSalil Mehta 706374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 707374ad291SJian Shen /* Get hash algorithm */ 708374ad291SJian Shen if (hfunc) { 709374ad291SJian Shen switch (rss_cfg->hash_algo) { 710374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 711374ad291SJian Shen *hfunc = ETH_RSS_HASH_TOP; 712374ad291SJian Shen break; 713374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 714374ad291SJian Shen *hfunc = ETH_RSS_HASH_XOR; 715374ad291SJian Shen break; 716374ad291SJian Shen default: 717374ad291SJian Shen *hfunc = ETH_RSS_HASH_UNKNOWN; 718374ad291SJian Shen break; 719374ad291SJian Shen } 720374ad291SJian Shen } 721374ad291SJian Shen 722374ad291SJian Shen /* Get the RSS Key required by the user */ 723374ad291SJian Shen if (key) 724374ad291SJian Shen memcpy(key, rss_cfg->rss_hash_key, 725374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 726a638b1d8SJian Shen } else { 727a638b1d8SJian Shen if (hfunc) 728a638b1d8SJian Shen *hfunc = ETH_RSS_HASH_TOP; 729a638b1d8SJian Shen if (key) { 730a638b1d8SJian Shen ret = hclgevf_get_rss_hash_key(hdev); 731a638b1d8SJian Shen if (ret) 732a638b1d8SJian Shen return ret; 733a638b1d8SJian Shen memcpy(key, rss_cfg->rss_hash_key, 734a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE); 735a638b1d8SJian Shen } 736374ad291SJian Shen } 737374ad291SJian Shen 738e2cb1decSSalil Mehta if (indir) 739e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 740e2cb1decSSalil Mehta indir[i] = rss_cfg->rss_indirection_tbl[i]; 741e2cb1decSSalil Mehta 742374ad291SJian Shen return 0; 743e2cb1decSSalil Mehta } 744e2cb1decSSalil Mehta 745e2cb1decSSalil Mehta static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 746e2cb1decSSalil Mehta const u8 *key, const u8 hfunc) 747e2cb1decSSalil Mehta { 748e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 749e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 750374ad291SJian Shen int ret, i; 751374ad291SJian Shen 752374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 753374ad291SJian Shen /* Set the RSS Hash Key if specififed by the user */ 754374ad291SJian Shen if (key) { 755374ad291SJian Shen switch (hfunc) { 756374ad291SJian Shen case ETH_RSS_HASH_TOP: 757374ad291SJian Shen rss_cfg->hash_algo = 758374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 759374ad291SJian Shen break; 760374ad291SJian Shen case ETH_RSS_HASH_XOR: 761374ad291SJian Shen rss_cfg->hash_algo = 762374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_SIMPLE; 763374ad291SJian Shen break; 764374ad291SJian Shen case ETH_RSS_HASH_NO_CHANGE: 765374ad291SJian Shen break; 766374ad291SJian Shen default: 767374ad291SJian Shen return -EINVAL; 768374ad291SJian Shen } 769374ad291SJian Shen 770374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 771374ad291SJian Shen key); 772374ad291SJian Shen if (ret) 773374ad291SJian Shen return ret; 774374ad291SJian Shen 775374ad291SJian Shen /* Update the shadow RSS key with user specified qids */ 776374ad291SJian Shen memcpy(rss_cfg->rss_hash_key, key, 777374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 778374ad291SJian Shen } 779374ad291SJian Shen } 780e2cb1decSSalil Mehta 781e2cb1decSSalil Mehta /* update the shadow RSS table with user specified qids */ 782e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 783e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = indir[i]; 784e2cb1decSSalil Mehta 785e2cb1decSSalil Mehta /* update the hardware */ 786e2cb1decSSalil Mehta return hclgevf_set_rss_indir_table(hdev); 787e2cb1decSSalil Mehta } 788e2cb1decSSalil Mehta 789d97b3072SJian Shen static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 790d97b3072SJian Shen { 791d97b3072SJian Shen u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 792d97b3072SJian Shen 793d97b3072SJian Shen if (nfc->data & RXH_L4_B_2_3) 794d97b3072SJian Shen hash_sets |= HCLGEVF_D_PORT_BIT; 795d97b3072SJian Shen else 796d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_PORT_BIT; 797d97b3072SJian Shen 798d97b3072SJian Shen if (nfc->data & RXH_IP_SRC) 799d97b3072SJian Shen hash_sets |= HCLGEVF_S_IP_BIT; 800d97b3072SJian Shen else 801d97b3072SJian Shen hash_sets &= ~HCLGEVF_S_IP_BIT; 802d97b3072SJian Shen 803d97b3072SJian Shen if (nfc->data & RXH_IP_DST) 804d97b3072SJian Shen hash_sets |= HCLGEVF_D_IP_BIT; 805d97b3072SJian Shen else 806d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_IP_BIT; 807d97b3072SJian Shen 808d97b3072SJian Shen if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 809d97b3072SJian Shen hash_sets |= HCLGEVF_V_TAG_BIT; 810d97b3072SJian Shen 811d97b3072SJian Shen return hash_sets; 812d97b3072SJian Shen } 813d97b3072SJian Shen 814d97b3072SJian Shen static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 815d97b3072SJian Shen struct ethtool_rxnfc *nfc) 816d97b3072SJian Shen { 817d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 818d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 819d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 820d97b3072SJian Shen struct hclgevf_desc desc; 821d97b3072SJian Shen u8 tuple_sets; 822d97b3072SJian Shen int ret; 823d97b3072SJian Shen 824d97b3072SJian Shen if (handle->pdev->revision == 0x20) 825d97b3072SJian Shen return -EOPNOTSUPP; 826d97b3072SJian Shen 827d97b3072SJian Shen if (nfc->data & 828d97b3072SJian Shen ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 829d97b3072SJian Shen return -EINVAL; 830d97b3072SJian Shen 831d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 832d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 833d97b3072SJian Shen 834d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 835d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 836d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 837d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 838d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 839d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 840d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 841d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 842d97b3072SJian Shen 843d97b3072SJian Shen tuple_sets = hclgevf_get_rss_hash_bits(nfc); 844d97b3072SJian Shen switch (nfc->flow_type) { 845d97b3072SJian Shen case TCP_V4_FLOW: 846d97b3072SJian Shen req->ipv4_tcp_en = tuple_sets; 847d97b3072SJian Shen break; 848d97b3072SJian Shen case TCP_V6_FLOW: 849d97b3072SJian Shen req->ipv6_tcp_en = tuple_sets; 850d97b3072SJian Shen break; 851d97b3072SJian Shen case UDP_V4_FLOW: 852d97b3072SJian Shen req->ipv4_udp_en = tuple_sets; 853d97b3072SJian Shen break; 854d97b3072SJian Shen case UDP_V6_FLOW: 855d97b3072SJian Shen req->ipv6_udp_en = tuple_sets; 856d97b3072SJian Shen break; 857d97b3072SJian Shen case SCTP_V4_FLOW: 858d97b3072SJian Shen req->ipv4_sctp_en = tuple_sets; 859d97b3072SJian Shen break; 860d97b3072SJian Shen case SCTP_V6_FLOW: 861d97b3072SJian Shen if ((nfc->data & RXH_L4_B_0_1) || 862d97b3072SJian Shen (nfc->data & RXH_L4_B_2_3)) 863d97b3072SJian Shen return -EINVAL; 864d97b3072SJian Shen 865d97b3072SJian Shen req->ipv6_sctp_en = tuple_sets; 866d97b3072SJian Shen break; 867d97b3072SJian Shen case IPV4_FLOW: 868d97b3072SJian Shen req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 869d97b3072SJian Shen break; 870d97b3072SJian Shen case IPV6_FLOW: 871d97b3072SJian Shen req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 872d97b3072SJian Shen break; 873d97b3072SJian Shen default: 874d97b3072SJian Shen return -EINVAL; 875d97b3072SJian Shen } 876d97b3072SJian Shen 877d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 878d97b3072SJian Shen if (ret) { 879d97b3072SJian Shen dev_err(&hdev->pdev->dev, 880d97b3072SJian Shen "Set rss tuple fail, status = %d\n", ret); 881d97b3072SJian Shen return ret; 882d97b3072SJian Shen } 883d97b3072SJian Shen 884d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 885d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 886d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 887d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 888d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 889d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 890d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 891d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 892d97b3072SJian Shen return 0; 893d97b3072SJian Shen } 894d97b3072SJian Shen 895d97b3072SJian Shen static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 896d97b3072SJian Shen struct ethtool_rxnfc *nfc) 897d97b3072SJian Shen { 898d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 899d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 900d97b3072SJian Shen u8 tuple_sets; 901d97b3072SJian Shen 902d97b3072SJian Shen if (handle->pdev->revision == 0x20) 903d97b3072SJian Shen return -EOPNOTSUPP; 904d97b3072SJian Shen 905d97b3072SJian Shen nfc->data = 0; 906d97b3072SJian Shen 907d97b3072SJian Shen switch (nfc->flow_type) { 908d97b3072SJian Shen case TCP_V4_FLOW: 909d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 910d97b3072SJian Shen break; 911d97b3072SJian Shen case UDP_V4_FLOW: 912d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 913d97b3072SJian Shen break; 914d97b3072SJian Shen case TCP_V6_FLOW: 915d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 916d97b3072SJian Shen break; 917d97b3072SJian Shen case UDP_V6_FLOW: 918d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 919d97b3072SJian Shen break; 920d97b3072SJian Shen case SCTP_V4_FLOW: 921d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 922d97b3072SJian Shen break; 923d97b3072SJian Shen case SCTP_V6_FLOW: 924d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 925d97b3072SJian Shen break; 926d97b3072SJian Shen case IPV4_FLOW: 927d97b3072SJian Shen case IPV6_FLOW: 928d97b3072SJian Shen tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 929d97b3072SJian Shen break; 930d97b3072SJian Shen default: 931d97b3072SJian Shen return -EINVAL; 932d97b3072SJian Shen } 933d97b3072SJian Shen 934d97b3072SJian Shen if (!tuple_sets) 935d97b3072SJian Shen return 0; 936d97b3072SJian Shen 937d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_PORT_BIT) 938d97b3072SJian Shen nfc->data |= RXH_L4_B_2_3; 939d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_PORT_BIT) 940d97b3072SJian Shen nfc->data |= RXH_L4_B_0_1; 941d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_IP_BIT) 942d97b3072SJian Shen nfc->data |= RXH_IP_DST; 943d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_IP_BIT) 944d97b3072SJian Shen nfc->data |= RXH_IP_SRC; 945d97b3072SJian Shen 946d97b3072SJian Shen return 0; 947d97b3072SJian Shen } 948d97b3072SJian Shen 949d97b3072SJian Shen static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 950d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg) 951d97b3072SJian Shen { 952d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 953d97b3072SJian Shen struct hclgevf_desc desc; 954d97b3072SJian Shen int ret; 955d97b3072SJian Shen 956d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 957d97b3072SJian Shen 958d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 959d97b3072SJian Shen 960d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 961d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 962d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 963d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 964d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 965d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 966d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 967d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 968d97b3072SJian Shen 969d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 970d97b3072SJian Shen if (ret) 971d97b3072SJian Shen dev_err(&hdev->pdev->dev, 972d97b3072SJian Shen "Configure rss input fail, status = %d\n", ret); 973d97b3072SJian Shen return ret; 974d97b3072SJian Shen } 975d97b3072SJian Shen 976e2cb1decSSalil Mehta static int hclgevf_get_tc_size(struct hnae3_handle *handle) 977e2cb1decSSalil Mehta { 978e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 979e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 980e2cb1decSSalil Mehta 981e2cb1decSSalil Mehta return rss_cfg->rss_size; 982e2cb1decSSalil Mehta } 983e2cb1decSSalil Mehta 984e2cb1decSSalil Mehta static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 985b204bc74SPeng Li int vector_id, 986e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 987e2cb1decSSalil Mehta { 988e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 989e2cb1decSSalil Mehta struct hnae3_ring_chain_node *node; 990e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 991e2cb1decSSalil Mehta struct hclgevf_desc desc; 992b204bc74SPeng Li int i = 0; 993e2cb1decSSalil Mehta int status; 994e2cb1decSSalil Mehta u8 type; 995e2cb1decSSalil Mehta 996e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 997c09ba484SPeng Li type = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 998c09ba484SPeng Li HCLGE_MBX_UNMAP_RING_TO_VECTOR; 999e2cb1decSSalil Mehta 1000e2cb1decSSalil Mehta for (node = ring_chain; node; node = node->next) { 10015d02a58dSYunsheng Lin int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 10025d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 10035d02a58dSYunsheng Lin 10045d02a58dSYunsheng Lin if (i == 0) { 10055d02a58dSYunsheng Lin hclgevf_cmd_setup_basic_desc(&desc, 10065d02a58dSYunsheng Lin HCLGEVF_OPC_MBX_VF_TO_PF, 10075d02a58dSYunsheng Lin false); 10085d02a58dSYunsheng Lin req->msg[0] = type; 10095d02a58dSYunsheng Lin req->msg[1] = vector_id; 10105d02a58dSYunsheng Lin } 10115d02a58dSYunsheng Lin 10125d02a58dSYunsheng Lin req->msg[idx_offset] = 1013e4e87715SPeng Li hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 10145d02a58dSYunsheng Lin req->msg[idx_offset + 1] = node->tqp_index; 1015e4e87715SPeng Li req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 101679eee410SFuyun Liang HNAE3_RING_GL_IDX_M, 101779eee410SFuyun Liang HNAE3_RING_GL_IDX_S); 101879eee410SFuyun Liang 10195d02a58dSYunsheng Lin i++; 10205d02a58dSYunsheng Lin if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 10215d02a58dSYunsheng Lin HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 10225d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 10235d02a58dSYunsheng Lin !node->next) { 1024e2cb1decSSalil Mehta req->msg[2] = i; 1025e2cb1decSSalil Mehta 1026e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1027e2cb1decSSalil Mehta if (status) { 1028e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1029e2cb1decSSalil Mehta "Map TQP fail, status is %d.\n", 1030e2cb1decSSalil Mehta status); 1031e2cb1decSSalil Mehta return status; 1032e2cb1decSSalil Mehta } 1033e2cb1decSSalil Mehta i = 0; 1034e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 1035e2cb1decSSalil Mehta HCLGEVF_OPC_MBX_VF_TO_PF, 1036e2cb1decSSalil Mehta false); 1037e2cb1decSSalil Mehta req->msg[0] = type; 1038e2cb1decSSalil Mehta req->msg[1] = vector_id; 1039e2cb1decSSalil Mehta } 1040e2cb1decSSalil Mehta } 1041e2cb1decSSalil Mehta 1042e2cb1decSSalil Mehta return 0; 1043e2cb1decSSalil Mehta } 1044e2cb1decSSalil Mehta 1045e2cb1decSSalil Mehta static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1046e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1047e2cb1decSSalil Mehta { 1048b204bc74SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1049b204bc74SPeng Li int vector_id; 1050b204bc74SPeng Li 1051b204bc74SPeng Li vector_id = hclgevf_get_vector_index(hdev, vector); 1052b204bc74SPeng Li if (vector_id < 0) { 1053b204bc74SPeng Li dev_err(&handle->pdev->dev, 1054b204bc74SPeng Li "Get vector index fail. ret =%d\n", vector_id); 1055b204bc74SPeng Li return vector_id; 1056b204bc74SPeng Li } 1057b204bc74SPeng Li 1058b204bc74SPeng Li return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1059e2cb1decSSalil Mehta } 1060e2cb1decSSalil Mehta 1061e2cb1decSSalil Mehta static int hclgevf_unmap_ring_from_vector( 1062e2cb1decSSalil Mehta struct hnae3_handle *handle, 1063e2cb1decSSalil Mehta int vector, 1064e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1065e2cb1decSSalil Mehta { 1066e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1067e2cb1decSSalil Mehta int ret, vector_id; 1068e2cb1decSSalil Mehta 1069dea846e8SHuazhong Tan if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1070dea846e8SHuazhong Tan return 0; 1071dea846e8SHuazhong Tan 1072e2cb1decSSalil Mehta vector_id = hclgevf_get_vector_index(hdev, vector); 1073e2cb1decSSalil Mehta if (vector_id < 0) { 1074e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1075e2cb1decSSalil Mehta "Get vector index fail. ret =%d\n", vector_id); 1076e2cb1decSSalil Mehta return vector_id; 1077e2cb1decSSalil Mehta } 1078e2cb1decSSalil Mehta 1079b204bc74SPeng Li ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 10800d3e6631SYunsheng Lin if (ret) 1081e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1082e2cb1decSSalil Mehta "Unmap ring from vector fail. vector=%d, ret =%d\n", 1083e2cb1decSSalil Mehta vector_id, 1084e2cb1decSSalil Mehta ret); 10850d3e6631SYunsheng Lin 1086e2cb1decSSalil Mehta return ret; 1087e2cb1decSSalil Mehta } 1088e2cb1decSSalil Mehta 10890d3e6631SYunsheng Lin static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 10900d3e6631SYunsheng Lin { 10910d3e6631SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 109203718db9SYunsheng Lin int vector_id; 10930d3e6631SYunsheng Lin 109403718db9SYunsheng Lin vector_id = hclgevf_get_vector_index(hdev, vector); 109503718db9SYunsheng Lin if (vector_id < 0) { 109603718db9SYunsheng Lin dev_err(&handle->pdev->dev, 109703718db9SYunsheng Lin "hclgevf_put_vector get vector index fail. ret =%d\n", 109803718db9SYunsheng Lin vector_id); 109903718db9SYunsheng Lin return vector_id; 110003718db9SYunsheng Lin } 110103718db9SYunsheng Lin 110203718db9SYunsheng Lin hclgevf_free_vector(hdev, vector_id); 1103e2cb1decSSalil Mehta 1104e2cb1decSSalil Mehta return 0; 1105e2cb1decSSalil Mehta } 1106e2cb1decSSalil Mehta 11073b75c3dfSPeng Li static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1108e196ec75SJian Shen bool en_uc_pmc, bool en_mc_pmc, 1109f01f5559SJian Shen bool en_bc_pmc) 1110e2cb1decSSalil Mehta { 1111e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 1112e2cb1decSSalil Mehta struct hclgevf_desc desc; 1113f01f5559SJian Shen int ret; 1114e2cb1decSSalil Mehta 1115e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1116e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 1117e2cb1decSSalil Mehta req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 1118f01f5559SJian Shen req->msg[1] = en_bc_pmc ? 1 : 0; 1119e196ec75SJian Shen req->msg[2] = en_uc_pmc ? 1 : 0; 1120e196ec75SJian Shen req->msg[3] = en_mc_pmc ? 1 : 0; 1121e2cb1decSSalil Mehta 1122f01f5559SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1123f01f5559SJian Shen if (ret) 1124e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1125f01f5559SJian Shen "Set promisc mode fail, status is %d.\n", ret); 1126e2cb1decSSalil Mehta 1127f01f5559SJian Shen return ret; 1128e2cb1decSSalil Mehta } 1129e2cb1decSSalil Mehta 1130e196ec75SJian Shen static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 1131e196ec75SJian Shen bool en_mc_pmc) 1132e2cb1decSSalil Mehta { 1133e196ec75SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1134e196ec75SJian Shen struct pci_dev *pdev = hdev->pdev; 1135e196ec75SJian Shen bool en_bc_pmc; 1136e196ec75SJian Shen 1137e196ec75SJian Shen en_bc_pmc = pdev->revision != 0x20; 1138e196ec75SJian Shen 1139e196ec75SJian Shen return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc, 1140e196ec75SJian Shen en_bc_pmc); 1141e2cb1decSSalil Mehta } 1142e2cb1decSSalil Mehta 1143ebaf1908SWeihang Li static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, unsigned int tqp_id, 1144e2cb1decSSalil Mehta int stream_id, bool enable) 1145e2cb1decSSalil Mehta { 1146e2cb1decSSalil Mehta struct hclgevf_cfg_com_tqp_queue_cmd *req; 1147e2cb1decSSalil Mehta struct hclgevf_desc desc; 1148e2cb1decSSalil Mehta int status; 1149e2cb1decSSalil Mehta 1150e2cb1decSSalil Mehta req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1151e2cb1decSSalil Mehta 1152e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1153e2cb1decSSalil Mehta false); 1154e2cb1decSSalil Mehta req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1155e2cb1decSSalil Mehta req->stream_id = cpu_to_le16(stream_id); 1156ebaf1908SWeihang Li if (enable) 1157ebaf1908SWeihang Li req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 1158e2cb1decSSalil Mehta 1159e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1160e2cb1decSSalil Mehta if (status) 1161e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1162e2cb1decSSalil Mehta "TQP enable fail, status =%d.\n", status); 1163e2cb1decSSalil Mehta 1164e2cb1decSSalil Mehta return status; 1165e2cb1decSSalil Mehta } 1166e2cb1decSSalil Mehta 1167e2cb1decSSalil Mehta static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1168e2cb1decSSalil Mehta { 1169b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1170e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 1171e2cb1decSSalil Mehta int i; 1172e2cb1decSSalil Mehta 1173b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 1174b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1175e2cb1decSSalil Mehta memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1176e2cb1decSSalil Mehta } 1177e2cb1decSSalil Mehta } 1178e2cb1decSSalil Mehta 1179e2cb1decSSalil Mehta static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1180e2cb1decSSalil Mehta { 1181e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1182e2cb1decSSalil Mehta 1183e2cb1decSSalil Mehta ether_addr_copy(p, hdev->hw.mac.mac_addr); 1184e2cb1decSSalil Mehta } 1185e2cb1decSSalil Mehta 118659098055SFuyun Liang static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 118759098055SFuyun Liang bool is_first) 1188e2cb1decSSalil Mehta { 1189e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1190e2cb1decSSalil Mehta u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1191e2cb1decSSalil Mehta u8 *new_mac_addr = (u8 *)p; 1192e2cb1decSSalil Mehta u8 msg_data[ETH_ALEN * 2]; 119359098055SFuyun Liang u16 subcode; 1194e2cb1decSSalil Mehta int status; 1195e2cb1decSSalil Mehta 1196e2cb1decSSalil Mehta ether_addr_copy(msg_data, new_mac_addr); 1197e2cb1decSSalil Mehta ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 1198e2cb1decSSalil Mehta 119959098055SFuyun Liang subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 120059098055SFuyun Liang HCLGE_MBX_MAC_VLAN_UC_MODIFY; 120159098055SFuyun Liang 1202e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 120363cbf7a9SYufeng Mo subcode, msg_data, sizeof(msg_data), 12042097fdefSJian Shen true, NULL, 0); 1205e2cb1decSSalil Mehta if (!status) 1206e2cb1decSSalil Mehta ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1207e2cb1decSSalil Mehta 1208e2cb1decSSalil Mehta return status; 1209e2cb1decSSalil Mehta } 1210e2cb1decSSalil Mehta 1211e2cb1decSSalil Mehta static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1212e2cb1decSSalil Mehta const unsigned char *addr) 1213e2cb1decSSalil Mehta { 1214e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1215e2cb1decSSalil Mehta 1216e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1217e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_ADD, 1218e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1219e2cb1decSSalil Mehta } 1220e2cb1decSSalil Mehta 1221e2cb1decSSalil Mehta static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1222e2cb1decSSalil Mehta const unsigned char *addr) 1223e2cb1decSSalil Mehta { 1224e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1225e2cb1decSSalil Mehta 1226e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1227e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1228e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1229e2cb1decSSalil Mehta } 1230e2cb1decSSalil Mehta 1231e2cb1decSSalil Mehta static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1232e2cb1decSSalil Mehta const unsigned char *addr) 1233e2cb1decSSalil Mehta { 1234e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1235e2cb1decSSalil Mehta 1236e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1237e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_ADD, 1238e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1239e2cb1decSSalil Mehta } 1240e2cb1decSSalil Mehta 1241e2cb1decSSalil Mehta static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1242e2cb1decSSalil Mehta const unsigned char *addr) 1243e2cb1decSSalil Mehta { 1244e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1245e2cb1decSSalil Mehta 1246e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1247e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1248e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1249e2cb1decSSalil Mehta } 1250e2cb1decSSalil Mehta 1251e2cb1decSSalil Mehta static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1252e2cb1decSSalil Mehta __be16 proto, u16 vlan_id, 1253e2cb1decSSalil Mehta bool is_kill) 1254e2cb1decSSalil Mehta { 1255e2cb1decSSalil Mehta #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1256e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1257e2cb1decSSalil Mehta u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1258fe4144d4SJian Shen int ret; 1259e2cb1decSSalil Mehta 1260b37ce587SYufeng Mo if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1261e2cb1decSSalil Mehta return -EINVAL; 1262e2cb1decSSalil Mehta 1263e2cb1decSSalil Mehta if (proto != htons(ETH_P_8021Q)) 1264e2cb1decSSalil Mehta return -EPROTONOSUPPORT; 1265e2cb1decSSalil Mehta 1266fe4144d4SJian Shen /* When device is resetting, firmware is unable to handle 1267fe4144d4SJian Shen * mailbox. Just record the vlan id, and remove it after 1268fe4144d4SJian Shen * reset finished. 1269fe4144d4SJian Shen */ 1270fe4144d4SJian Shen if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) && is_kill) { 1271fe4144d4SJian Shen set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1272fe4144d4SJian Shen return -EBUSY; 1273fe4144d4SJian Shen } 1274fe4144d4SJian Shen 1275e2cb1decSSalil Mehta msg_data[0] = is_kill; 1276e2cb1decSSalil Mehta memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1277e2cb1decSSalil Mehta memcpy(&msg_data[3], &proto, sizeof(proto)); 1278fe4144d4SJian Shen ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1279e2cb1decSSalil Mehta HCLGE_MBX_VLAN_FILTER, msg_data, 128022044f95SJian Shen HCLGEVF_VLAN_MBX_MSG_LEN, true, NULL, 0); 1281fe4144d4SJian Shen 128246ee7350SGuojia Liao /* when remove hw vlan filter failed, record the vlan id, 1283fe4144d4SJian Shen * and try to remove it from hw later, to be consistence 1284fe4144d4SJian Shen * with stack. 1285fe4144d4SJian Shen */ 1286fe4144d4SJian Shen if (is_kill && ret) 1287fe4144d4SJian Shen set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1288fe4144d4SJian Shen 1289fe4144d4SJian Shen return ret; 1290fe4144d4SJian Shen } 1291fe4144d4SJian Shen 1292fe4144d4SJian Shen static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1293fe4144d4SJian Shen { 1294fe4144d4SJian Shen #define HCLGEVF_MAX_SYNC_COUNT 60 1295fe4144d4SJian Shen struct hnae3_handle *handle = &hdev->nic; 1296fe4144d4SJian Shen int ret, sync_cnt = 0; 1297fe4144d4SJian Shen u16 vlan_id; 1298fe4144d4SJian Shen 1299fe4144d4SJian Shen vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1300fe4144d4SJian Shen while (vlan_id != VLAN_N_VID) { 1301fe4144d4SJian Shen ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1302fe4144d4SJian Shen vlan_id, true); 1303fe4144d4SJian Shen if (ret) 1304fe4144d4SJian Shen return; 1305fe4144d4SJian Shen 1306fe4144d4SJian Shen clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1307fe4144d4SJian Shen sync_cnt++; 1308fe4144d4SJian Shen if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1309fe4144d4SJian Shen return; 1310fe4144d4SJian Shen 1311fe4144d4SJian Shen vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1312fe4144d4SJian Shen } 1313e2cb1decSSalil Mehta } 1314e2cb1decSSalil Mehta 1315b2641e2aSYunsheng Lin static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1316b2641e2aSYunsheng Lin { 1317b2641e2aSYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1318b2641e2aSYunsheng Lin u8 msg_data; 1319b2641e2aSYunsheng Lin 1320b2641e2aSYunsheng Lin msg_data = enable ? 1 : 0; 1321b2641e2aSYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1322b2641e2aSYunsheng Lin HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1323b2641e2aSYunsheng Lin 1, false, NULL, 0); 1324b2641e2aSYunsheng Lin } 1325b2641e2aSYunsheng Lin 13267fa6be4fSHuazhong Tan static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1327e2cb1decSSalil Mehta { 1328e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1329e2cb1decSSalil Mehta u8 msg_data[2]; 13301a426f8bSPeng Li int ret; 1331e2cb1decSSalil Mehta 133263cbf7a9SYufeng Mo memcpy(msg_data, &queue_id, sizeof(queue_id)); 1333e2cb1decSSalil Mehta 13341a426f8bSPeng Li /* disable vf queue before send queue reset msg to PF */ 13351a426f8bSPeng Li ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 13361a426f8bSPeng Li if (ret) 13377fa6be4fSHuazhong Tan return ret; 13381a426f8bSPeng Li 13397fa6be4fSHuazhong Tan return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 134063cbf7a9SYufeng Mo sizeof(msg_data), true, NULL, 0); 1341e2cb1decSSalil Mehta } 1342e2cb1decSSalil Mehta 1343818f1675SYunsheng Lin static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1344818f1675SYunsheng Lin { 1345818f1675SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1346818f1675SYunsheng Lin 1347818f1675SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu, 1348818f1675SYunsheng Lin sizeof(new_mtu), true, NULL, 0); 1349818f1675SYunsheng Lin } 1350818f1675SYunsheng Lin 13516988eb2aSSalil Mehta static int hclgevf_notify_client(struct hclgevf_dev *hdev, 13526988eb2aSSalil Mehta enum hnae3_reset_notify_type type) 13536988eb2aSSalil Mehta { 13546988eb2aSSalil Mehta struct hnae3_client *client = hdev->nic_client; 13556988eb2aSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 13566a5f6fa3SHuazhong Tan int ret; 13576988eb2aSSalil Mehta 135825d1817cSHuazhong Tan if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 135925d1817cSHuazhong Tan !client) 136025d1817cSHuazhong Tan return 0; 136125d1817cSHuazhong Tan 13626988eb2aSSalil Mehta if (!client->ops->reset_notify) 13636988eb2aSSalil Mehta return -EOPNOTSUPP; 13646988eb2aSSalil Mehta 13656a5f6fa3SHuazhong Tan ret = client->ops->reset_notify(handle, type); 13666a5f6fa3SHuazhong Tan if (ret) 13676a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 13686a5f6fa3SHuazhong Tan type, ret); 13696a5f6fa3SHuazhong Tan 13706a5f6fa3SHuazhong Tan return ret; 13716988eb2aSSalil Mehta } 13726988eb2aSSalil Mehta 13736ff3cf07SHuazhong Tan static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 13746ff3cf07SHuazhong Tan { 13756ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 13766ff3cf07SHuazhong Tan 13776ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DONE, &hdev->flr_state); 13786ff3cf07SHuazhong Tan } 13796ff3cf07SHuazhong Tan 13806ff3cf07SHuazhong Tan static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev, 13816ff3cf07SHuazhong Tan unsigned long delay_us, 13826ff3cf07SHuazhong Tan unsigned long wait_cnt) 13836ff3cf07SHuazhong Tan { 13846ff3cf07SHuazhong Tan unsigned long cnt = 0; 13856ff3cf07SHuazhong Tan 13866ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) && 13876ff3cf07SHuazhong Tan cnt++ < wait_cnt) 13886ff3cf07SHuazhong Tan usleep_range(delay_us, delay_us * 2); 13896ff3cf07SHuazhong Tan 13906ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) { 13916ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 13926ff3cf07SHuazhong Tan "flr wait timeout\n"); 13936ff3cf07SHuazhong Tan return -ETIMEDOUT; 13946ff3cf07SHuazhong Tan } 13956ff3cf07SHuazhong Tan 13966ff3cf07SHuazhong Tan return 0; 13976ff3cf07SHuazhong Tan } 13986ff3cf07SHuazhong Tan 13996988eb2aSSalil Mehta static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 14006988eb2aSSalil Mehta { 1401aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_US 20000 1402aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_CNT 2000 1403aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1404aa5c4f17SHuazhong Tan (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1405aa5c4f17SHuazhong Tan 1406aa5c4f17SHuazhong Tan u32 val; 1407aa5c4f17SHuazhong Tan int ret; 14086988eb2aSSalil Mehta 14096ff3cf07SHuazhong Tan if (hdev->reset_type == HNAE3_FLR_RESET) 14106ff3cf07SHuazhong Tan return hclgevf_flr_poll_timeout(hdev, 14116ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_US, 14126ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_CNT); 141372e2fb07SHuazhong Tan else if (hdev->reset_type == HNAE3_VF_RESET) 141472e2fb07SHuazhong Tan ret = readl_poll_timeout(hdev->hw.io_base + 141572e2fb07SHuazhong Tan HCLGEVF_VF_RST_ING, val, 141672e2fb07SHuazhong Tan !(val & HCLGEVF_VF_RST_ING_BIT), 141772e2fb07SHuazhong Tan HCLGEVF_RESET_WAIT_US, 141872e2fb07SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 141972e2fb07SHuazhong Tan else 142072e2fb07SHuazhong Tan ret = readl_poll_timeout(hdev->hw.io_base + 142172e2fb07SHuazhong Tan HCLGEVF_RST_ING, val, 1422aa5c4f17SHuazhong Tan !(val & HCLGEVF_RST_ING_BITS), 1423aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_US, 1424aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 14256988eb2aSSalil Mehta 14266988eb2aSSalil Mehta /* hardware completion status should be available by this time */ 1427aa5c4f17SHuazhong Tan if (ret) { 1428aa5c4f17SHuazhong Tan dev_err(&hdev->pdev->dev, 14296988eb2aSSalil Mehta "could'nt get reset done status from h/w, timeout!\n"); 1430aa5c4f17SHuazhong Tan return ret; 14316988eb2aSSalil Mehta } 14326988eb2aSSalil Mehta 14336988eb2aSSalil Mehta /* we will wait a bit more to let reset of the stack to complete. This 14346988eb2aSSalil Mehta * might happen in case reset assertion was made by PF. Yes, this also 14356988eb2aSSalil Mehta * means we might end up waiting bit more even for VF reset. 14366988eb2aSSalil Mehta */ 14376988eb2aSSalil Mehta msleep(5000); 14386988eb2aSSalil Mehta 14396988eb2aSSalil Mehta return 0; 14406988eb2aSSalil Mehta } 14416988eb2aSSalil Mehta 14426b428b4fSHuazhong Tan static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable) 14436b428b4fSHuazhong Tan { 14446b428b4fSHuazhong Tan u32 reg_val; 14456b428b4fSHuazhong Tan 14466b428b4fSHuazhong Tan reg_val = hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG); 14476b428b4fSHuazhong Tan if (enable) 14486b428b4fSHuazhong Tan reg_val |= HCLGEVF_NIC_SW_RST_RDY; 14496b428b4fSHuazhong Tan else 14506b428b4fSHuazhong Tan reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; 14516b428b4fSHuazhong Tan 14526b428b4fSHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 14536b428b4fSHuazhong Tan reg_val); 14546b428b4fSHuazhong Tan } 14556b428b4fSHuazhong Tan 14566988eb2aSSalil Mehta static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 14576988eb2aSSalil Mehta { 14587a01c897SSalil Mehta int ret; 14597a01c897SSalil Mehta 14606988eb2aSSalil Mehta /* uninitialize the nic client */ 14616a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 14626a5f6fa3SHuazhong Tan if (ret) 14636a5f6fa3SHuazhong Tan return ret; 14646988eb2aSSalil Mehta 14657a01c897SSalil Mehta /* re-initialize the hclge device */ 14669c6f7085SHuazhong Tan ret = hclgevf_reset_hdev(hdev); 14677a01c897SSalil Mehta if (ret) { 14687a01c897SSalil Mehta dev_err(&hdev->pdev->dev, 14697a01c897SSalil Mehta "hclge device re-init failed, VF is disabled!\n"); 14707a01c897SSalil Mehta return ret; 14717a01c897SSalil Mehta } 14726988eb2aSSalil Mehta 14736988eb2aSSalil Mehta /* bring up the nic client again */ 14746a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 14756a5f6fa3SHuazhong Tan if (ret) 14766a5f6fa3SHuazhong Tan return ret; 14776988eb2aSSalil Mehta 14786b428b4fSHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT); 14796b428b4fSHuazhong Tan if (ret) 14806b428b4fSHuazhong Tan return ret; 14816b428b4fSHuazhong Tan 14826b428b4fSHuazhong Tan /* clear handshake status with IMP */ 14836b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, false); 14846b428b4fSHuazhong Tan 14856b428b4fSHuazhong Tan return 0; 14866988eb2aSSalil Mehta } 14876988eb2aSSalil Mehta 1488dea846e8SHuazhong Tan static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1489dea846e8SHuazhong Tan { 1490ada13ee3SHuazhong Tan #define HCLGEVF_RESET_SYNC_TIME 100 1491ada13ee3SHuazhong Tan 1492dea846e8SHuazhong Tan int ret = 0; 1493dea846e8SHuazhong Tan 1494dea846e8SHuazhong Tan switch (hdev->reset_type) { 1495dea846e8SHuazhong Tan case HNAE3_VF_FUNC_RESET: 1496dea846e8SHuazhong Tan ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1497dea846e8SHuazhong Tan 0, true, NULL, sizeof(u8)); 1498c88a6e7dSHuazhong Tan hdev->rst_stats.vf_func_rst_cnt++; 1499dea846e8SHuazhong Tan break; 15006ff3cf07SHuazhong Tan case HNAE3_FLR_RESET: 15016ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1502c88a6e7dSHuazhong Tan hdev->rst_stats.flr_rst_cnt++; 15036ff3cf07SHuazhong Tan break; 1504dea846e8SHuazhong Tan default: 1505dea846e8SHuazhong Tan break; 1506dea846e8SHuazhong Tan } 1507dea846e8SHuazhong Tan 1508ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1509ada13ee3SHuazhong Tan /* inform hardware that preparatory work is done */ 1510ada13ee3SHuazhong Tan msleep(HCLGEVF_RESET_SYNC_TIME); 15116b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, true); 1512dea846e8SHuazhong Tan dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1513dea846e8SHuazhong Tan hdev->reset_type, ret); 1514dea846e8SHuazhong Tan 1515dea846e8SHuazhong Tan return ret; 1516dea846e8SHuazhong Tan } 1517dea846e8SHuazhong Tan 1518bbe6540eSHuazhong Tan static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1519bbe6540eSHuazhong Tan { 15206b428b4fSHuazhong Tan /* recover handshake status with IMP when reset fail */ 15216b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, true); 1522bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt++; 1523bbe6540eSHuazhong Tan dev_err(&hdev->pdev->dev, "failed to reset VF(%d)\n", 1524bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt); 1525bbe6540eSHuazhong Tan 1526bbe6540eSHuazhong Tan if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1527bbe6540eSHuazhong Tan set_bit(hdev->reset_type, &hdev->reset_pending); 1528bbe6540eSHuazhong Tan 1529bbe6540eSHuazhong Tan if (hclgevf_is_reset_pending(hdev)) { 1530bbe6540eSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1531bbe6540eSHuazhong Tan hclgevf_reset_task_schedule(hdev); 1532bbe6540eSHuazhong Tan } 1533bbe6540eSHuazhong Tan } 1534bbe6540eSHuazhong Tan 15356988eb2aSSalil Mehta static int hclgevf_reset(struct hclgevf_dev *hdev) 15366988eb2aSSalil Mehta { 1537dea846e8SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 15386988eb2aSSalil Mehta int ret; 15396988eb2aSSalil Mehta 1540dea846e8SHuazhong Tan /* Initialize ae_dev reset status as well, in case enet layer wants to 1541dea846e8SHuazhong Tan * know if device is undergoing reset 1542dea846e8SHuazhong Tan */ 1543dea846e8SHuazhong Tan ae_dev->reset_type = hdev->reset_type; 1544c88a6e7dSHuazhong Tan hdev->rst_stats.rst_cnt++; 15456988eb2aSSalil Mehta rtnl_lock(); 15466988eb2aSSalil Mehta 15476988eb2aSSalil Mehta /* bring down the nic to stop any ongoing TX/RX */ 15486a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 15496a5f6fa3SHuazhong Tan if (ret) 15506a5f6fa3SHuazhong Tan goto err_reset_lock; 15516988eb2aSSalil Mehta 155229118ab9SHuazhong Tan rtnl_unlock(); 155329118ab9SHuazhong Tan 15546a5f6fa3SHuazhong Tan ret = hclgevf_reset_prepare_wait(hdev); 15556a5f6fa3SHuazhong Tan if (ret) 15566a5f6fa3SHuazhong Tan goto err_reset; 1557dea846e8SHuazhong Tan 15586988eb2aSSalil Mehta /* check if VF could successfully fetch the hardware reset completion 15596988eb2aSSalil Mehta * status from the hardware 15606988eb2aSSalil Mehta */ 15616988eb2aSSalil Mehta ret = hclgevf_reset_wait(hdev); 15626988eb2aSSalil Mehta if (ret) { 15636988eb2aSSalil Mehta /* can't do much in this situation, will disable VF */ 15646988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, 15656988eb2aSSalil Mehta "VF failed(=%d) to fetch H/W reset completion status\n", 15666988eb2aSSalil Mehta ret); 15676a5f6fa3SHuazhong Tan goto err_reset; 15686988eb2aSSalil Mehta } 15696988eb2aSSalil Mehta 1570c88a6e7dSHuazhong Tan hdev->rst_stats.hw_rst_done_cnt++; 1571c88a6e7dSHuazhong Tan 157229118ab9SHuazhong Tan rtnl_lock(); 157329118ab9SHuazhong Tan 15746988eb2aSSalil Mehta /* now, re-initialize the nic client and ae device */ 15756988eb2aSSalil Mehta ret = hclgevf_reset_stack(hdev); 15766a5f6fa3SHuazhong Tan if (ret) { 15776988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 15786a5f6fa3SHuazhong Tan goto err_reset_lock; 15796a5f6fa3SHuazhong Tan } 15806988eb2aSSalil Mehta 15816988eb2aSSalil Mehta /* bring up the nic to enable TX/RX again */ 15826a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 15836a5f6fa3SHuazhong Tan if (ret) 15846a5f6fa3SHuazhong Tan goto err_reset_lock; 15856988eb2aSSalil Mehta 15866988eb2aSSalil Mehta rtnl_unlock(); 15876988eb2aSSalil Mehta 1588b644a8d4SHuazhong Tan hdev->last_reset_time = jiffies; 1589b644a8d4SHuazhong Tan ae_dev->reset_type = HNAE3_NONE_RESET; 1590c88a6e7dSHuazhong Tan hdev->rst_stats.rst_done_cnt++; 1591bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt = 0; 1592b644a8d4SHuazhong Tan 15936988eb2aSSalil Mehta return ret; 15946a5f6fa3SHuazhong Tan err_reset_lock: 15956a5f6fa3SHuazhong Tan rtnl_unlock(); 15966a5f6fa3SHuazhong Tan err_reset: 1597bbe6540eSHuazhong Tan hclgevf_reset_err_handle(hdev); 15986a5f6fa3SHuazhong Tan 15996a5f6fa3SHuazhong Tan return ret; 16006988eb2aSSalil Mehta } 16016988eb2aSSalil Mehta 1602720bd583SHuazhong Tan static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1603720bd583SHuazhong Tan unsigned long *addr) 1604720bd583SHuazhong Tan { 1605720bd583SHuazhong Tan enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1606720bd583SHuazhong Tan 1607dea846e8SHuazhong Tan /* return the highest priority reset level amongst all */ 1608b90fcc5bSHuazhong Tan if (test_bit(HNAE3_VF_RESET, addr)) { 1609b90fcc5bSHuazhong Tan rst_level = HNAE3_VF_RESET; 1610b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_RESET, addr); 1611b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1612b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1613b90fcc5bSHuazhong Tan } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1614dea846e8SHuazhong Tan rst_level = HNAE3_VF_FULL_RESET; 1615dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FULL_RESET, addr); 1616dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1617aa5c4f17SHuazhong Tan } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1618aa5c4f17SHuazhong Tan rst_level = HNAE3_VF_PF_FUNC_RESET; 1619aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1620aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1621dea846e8SHuazhong Tan } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1622dea846e8SHuazhong Tan rst_level = HNAE3_VF_FUNC_RESET; 1623dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 16246ff3cf07SHuazhong Tan } else if (test_bit(HNAE3_FLR_RESET, addr)) { 16256ff3cf07SHuazhong Tan rst_level = HNAE3_FLR_RESET; 16266ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_RESET, addr); 1627720bd583SHuazhong Tan } 1628720bd583SHuazhong Tan 1629720bd583SHuazhong Tan return rst_level; 1630720bd583SHuazhong Tan } 1631720bd583SHuazhong Tan 16326ae4e733SShiju Jose static void hclgevf_reset_event(struct pci_dev *pdev, 16336ae4e733SShiju Jose struct hnae3_handle *handle) 16346d4c3981SSalil Mehta { 16356ff3cf07SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 16366ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 16376d4c3981SSalil Mehta 16386d4c3981SSalil Mehta dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 16396d4c3981SSalil Mehta 16406ff3cf07SHuazhong Tan if (hdev->default_reset_request) 16410742ed7cSHuazhong Tan hdev->reset_level = 1642720bd583SHuazhong Tan hclgevf_get_reset_level(hdev, 1643720bd583SHuazhong Tan &hdev->default_reset_request); 1644720bd583SHuazhong Tan else 1645dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 16466d4c3981SSalil Mehta 1647436667d2SSalil Mehta /* reset of this VF requested */ 1648436667d2SSalil Mehta set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1649436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 16506d4c3981SSalil Mehta 16510742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 16526d4c3981SSalil Mehta } 16536d4c3981SSalil Mehta 1654720bd583SHuazhong Tan static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1655720bd583SHuazhong Tan enum hnae3_reset_type rst_type) 1656720bd583SHuazhong Tan { 1657720bd583SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1658720bd583SHuazhong Tan 1659720bd583SHuazhong Tan set_bit(rst_type, &hdev->default_reset_request); 1660720bd583SHuazhong Tan } 1661720bd583SHuazhong Tan 16626ff3cf07SHuazhong Tan static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 16636ff3cf07SHuazhong Tan { 16646ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_MS 100 16656ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_CNT 50 16666ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 16676ff3cf07SHuazhong Tan int cnt = 0; 16686ff3cf07SHuazhong Tan 16696ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 16706ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DONE, &hdev->flr_state); 16716ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request); 16726ff3cf07SHuazhong Tan hclgevf_reset_event(hdev->pdev, NULL); 16736ff3cf07SHuazhong Tan 16746ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) && 16756ff3cf07SHuazhong Tan cnt++ < HCLGEVF_FLR_WAIT_CNT) 16766ff3cf07SHuazhong Tan msleep(HCLGEVF_FLR_WAIT_MS); 16776ff3cf07SHuazhong Tan 16786ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state)) 16796ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 16806ff3cf07SHuazhong Tan "flr wait down timeout: %d\n", cnt); 16816ff3cf07SHuazhong Tan } 16826ff3cf07SHuazhong Tan 1683e2cb1decSSalil Mehta static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1684e2cb1decSSalil Mehta { 1685e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1686e2cb1decSSalil Mehta 1687e2cb1decSSalil Mehta return hdev->fw_version; 1688e2cb1decSSalil Mehta } 1689e2cb1decSSalil Mehta 1690e2cb1decSSalil Mehta static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1691e2cb1decSSalil Mehta { 1692e2cb1decSSalil Mehta struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1693e2cb1decSSalil Mehta 1694e2cb1decSSalil Mehta vector->vector_irq = pci_irq_vector(hdev->pdev, 1695e2cb1decSSalil Mehta HCLGEVF_MISC_VECTOR_NUM); 1696e2cb1decSSalil Mehta vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1697e2cb1decSSalil Mehta /* vector status always valid for Vector 0 */ 1698e2cb1decSSalil Mehta hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1699e2cb1decSSalil Mehta hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1700e2cb1decSSalil Mehta 1701e2cb1decSSalil Mehta hdev->num_msi_left -= 1; 1702e2cb1decSSalil Mehta hdev->num_msi_used += 1; 1703e2cb1decSSalil Mehta } 1704e2cb1decSSalil Mehta 170535a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 170635a1e503SSalil Mehta { 1707acfc3d55SHuazhong Tan if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) && 1708acfc3d55SHuazhong Tan !test_bit(HCLGEVF_STATE_REMOVING, &hdev->state)) { 170935a1e503SSalil Mehta set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 171035a1e503SSalil Mehta schedule_work(&hdev->rst_service_task); 171135a1e503SSalil Mehta } 171235a1e503SSalil Mehta } 171335a1e503SSalil Mehta 171407a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1715e2cb1decSSalil Mehta { 171607a0556aSSalil Mehta if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) && 171707a0556aSSalil Mehta !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) { 171807a0556aSSalil Mehta set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1719e2cb1decSSalil Mehta schedule_work(&hdev->mbx_service_task); 1720e2cb1decSSalil Mehta } 172107a0556aSSalil Mehta } 1722e2cb1decSSalil Mehta 1723e2cb1decSSalil Mehta static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 1724e2cb1decSSalil Mehta { 1725e2cb1decSSalil Mehta if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 1726e2cb1decSSalil Mehta !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 1727e2cb1decSSalil Mehta schedule_work(&hdev->service_task); 1728e2cb1decSSalil Mehta } 1729e2cb1decSSalil Mehta 1730436667d2SSalil Mehta static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev) 1731436667d2SSalil Mehta { 173207a0556aSSalil Mehta /* if we have any pending mailbox event then schedule the mbx task */ 173307a0556aSSalil Mehta if (hdev->mbx_event_pending) 173407a0556aSSalil Mehta hclgevf_mbx_task_schedule(hdev); 173507a0556aSSalil Mehta 1736436667d2SSalil Mehta if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state)) 1737436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 1738436667d2SSalil Mehta } 1739436667d2SSalil Mehta 1740e2cb1decSSalil Mehta static void hclgevf_service_timer(struct timer_list *t) 1741e2cb1decSSalil Mehta { 1742e2cb1decSSalil Mehta struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 1743e2cb1decSSalil Mehta 1744b37ce587SYufeng Mo mod_timer(&hdev->service_timer, jiffies + 1745b37ce587SYufeng Mo HCLGEVF_GENERAL_TASK_INTERVAL * HZ); 1746e2cb1decSSalil Mehta 1747db01afebSliuzhongzhu hdev->stats_timer++; 1748e2cb1decSSalil Mehta hclgevf_task_schedule(hdev); 1749e2cb1decSSalil Mehta } 1750e2cb1decSSalil Mehta 175135a1e503SSalil Mehta static void hclgevf_reset_service_task(struct work_struct *work) 175235a1e503SSalil Mehta { 175335a1e503SSalil Mehta struct hclgevf_dev *hdev = 175435a1e503SSalil Mehta container_of(work, struct hclgevf_dev, rst_service_task); 1755a8dedb65SSalil Mehta int ret; 175635a1e503SSalil Mehta 175735a1e503SSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 175835a1e503SSalil Mehta return; 175935a1e503SSalil Mehta 176035a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 176135a1e503SSalil Mehta 1762436667d2SSalil Mehta if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1763436667d2SSalil Mehta &hdev->reset_state)) { 1764436667d2SSalil Mehta /* PF has initmated that it is about to reset the hardware. 17659b2f3477SWeihang Li * We now have to poll & check if hardware has actually 17669b2f3477SWeihang Li * completed the reset sequence. On hardware reset completion, 17679b2f3477SWeihang Li * VF needs to reset the client and ae device. 176835a1e503SSalil Mehta */ 1769436667d2SSalil Mehta hdev->reset_attempts = 0; 1770436667d2SSalil Mehta 1771dea846e8SHuazhong Tan hdev->last_reset_time = jiffies; 1772dea846e8SHuazhong Tan while ((hdev->reset_type = 1773dea846e8SHuazhong Tan hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 1774dea846e8SHuazhong Tan != HNAE3_NONE_RESET) { 17756988eb2aSSalil Mehta ret = hclgevf_reset(hdev); 17766988eb2aSSalil Mehta if (ret) 1777dea846e8SHuazhong Tan dev_err(&hdev->pdev->dev, 1778dea846e8SHuazhong Tan "VF stack reset failed %d.\n", ret); 1779dea846e8SHuazhong Tan } 1780436667d2SSalil Mehta } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1781436667d2SSalil Mehta &hdev->reset_state)) { 1782436667d2SSalil Mehta /* we could be here when either of below happens: 17839b2f3477SWeihang Li * 1. reset was initiated due to watchdog timeout caused by 1784436667d2SSalil Mehta * a. IMP was earlier reset and our TX got choked down and 1785436667d2SSalil Mehta * which resulted in watchdog reacting and inducing VF 1786436667d2SSalil Mehta * reset. This also means our cmdq would be unreliable. 1787436667d2SSalil Mehta * b. problem in TX due to other lower layer(example link 1788436667d2SSalil Mehta * layer not functioning properly etc.) 1789436667d2SSalil Mehta * 2. VF reset might have been initiated due to some config 1790436667d2SSalil Mehta * change. 1791436667d2SSalil Mehta * 1792436667d2SSalil Mehta * NOTE: Theres no clear way to detect above cases than to react 1793436667d2SSalil Mehta * to the response of PF for this reset request. PF will ack the 1794436667d2SSalil Mehta * 1b and 2. cases but we will not get any intimation about 1a 1795436667d2SSalil Mehta * from PF as cmdq would be in unreliable state i.e. mailbox 1796436667d2SSalil Mehta * communication between PF and VF would be broken. 179746ee7350SGuojia Liao * 179846ee7350SGuojia Liao * if we are never geting into pending state it means either: 1799436667d2SSalil Mehta * 1. PF is not receiving our request which could be due to IMP 1800436667d2SSalil Mehta * reset 1801436667d2SSalil Mehta * 2. PF is screwed 1802436667d2SSalil Mehta * We cannot do much for 2. but to check first we can try reset 1803436667d2SSalil Mehta * our PCIe + stack and see if it alleviates the problem. 1804436667d2SSalil Mehta */ 1805436667d2SSalil Mehta if (hdev->reset_attempts > 3) { 1806436667d2SSalil Mehta /* prepare for full reset of stack + pcie interface */ 1807dea846e8SHuazhong Tan set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1808436667d2SSalil Mehta 1809436667d2SSalil Mehta /* "defer" schedule the reset task again */ 1810436667d2SSalil Mehta set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1811436667d2SSalil Mehta } else { 1812436667d2SSalil Mehta hdev->reset_attempts++; 1813436667d2SSalil Mehta 1814dea846e8SHuazhong Tan set_bit(hdev->reset_level, &hdev->reset_pending); 1815dea846e8SHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1816436667d2SSalil Mehta } 1817dea846e8SHuazhong Tan hclgevf_reset_task_schedule(hdev); 1818436667d2SSalil Mehta } 181935a1e503SSalil Mehta 182035a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 182135a1e503SSalil Mehta } 182235a1e503SSalil Mehta 1823e2cb1decSSalil Mehta static void hclgevf_mailbox_service_task(struct work_struct *work) 1824e2cb1decSSalil Mehta { 1825e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1826e2cb1decSSalil Mehta 1827e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 1828e2cb1decSSalil Mehta 1829e2cb1decSSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1830e2cb1decSSalil Mehta return; 1831e2cb1decSSalil Mehta 1832e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1833e2cb1decSSalil Mehta 183407a0556aSSalil Mehta hclgevf_mbx_async_handler(hdev); 1835e2cb1decSSalil Mehta 1836e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1837e2cb1decSSalil Mehta } 1838e2cb1decSSalil Mehta 1839a6d818e3SYunsheng Lin static void hclgevf_keep_alive_timer(struct timer_list *t) 1840a6d818e3SYunsheng Lin { 1841a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = from_timer(hdev, t, keep_alive_timer); 1842a6d818e3SYunsheng Lin 1843a6d818e3SYunsheng Lin schedule_work(&hdev->keep_alive_task); 1844b37ce587SYufeng Mo mod_timer(&hdev->keep_alive_timer, jiffies + 1845b37ce587SYufeng Mo HCLGEVF_KEEP_ALIVE_TASK_INTERVAL * HZ); 1846a6d818e3SYunsheng Lin } 1847a6d818e3SYunsheng Lin 1848a6d818e3SYunsheng Lin static void hclgevf_keep_alive_task(struct work_struct *work) 1849a6d818e3SYunsheng Lin { 1850a6d818e3SYunsheng Lin struct hclgevf_dev *hdev; 1851a6d818e3SYunsheng Lin u8 respmsg; 1852a6d818e3SYunsheng Lin int ret; 1853a6d818e3SYunsheng Lin 1854a6d818e3SYunsheng Lin hdev = container_of(work, struct hclgevf_dev, keep_alive_task); 1855c59a85c0SJian Shen 18561416d333SHuazhong Tan if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 1857c59a85c0SJian Shen return; 1858c59a85c0SJian Shen 1859a6d818e3SYunsheng Lin ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL, 186063cbf7a9SYufeng Mo 0, false, &respmsg, sizeof(respmsg)); 1861a6d818e3SYunsheng Lin if (ret) 1862a6d818e3SYunsheng Lin dev_err(&hdev->pdev->dev, 1863a6d818e3SYunsheng Lin "VF sends keep alive cmd failed(=%d)\n", ret); 1864a6d818e3SYunsheng Lin } 1865a6d818e3SYunsheng Lin 1866e2cb1decSSalil Mehta static void hclgevf_service_task(struct work_struct *work) 1867e2cb1decSSalil Mehta { 1868db01afebSliuzhongzhu struct hnae3_handle *handle; 1869e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1870e2cb1decSSalil Mehta 1871e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, service_task); 1872db01afebSliuzhongzhu handle = &hdev->nic; 1873db01afebSliuzhongzhu 1874db01afebSliuzhongzhu if (hdev->stats_timer >= HCLGEVF_STATS_TIMER_INTERVAL) { 1875db01afebSliuzhongzhu hclgevf_tqps_update_stats(handle); 1876db01afebSliuzhongzhu hdev->stats_timer = 0; 1877db01afebSliuzhongzhu } 1878e2cb1decSSalil Mehta 1879e2cb1decSSalil Mehta /* request the link status from the PF. PF would be able to tell VF 1880e2cb1decSSalil Mehta * about such updates in future so we might remove this later 1881e2cb1decSSalil Mehta */ 1882e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1883e2cb1decSSalil Mehta 18849194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 18859194d18bSliuzhongzhu 1886fe4144d4SJian Shen hclgevf_sync_vlan_filter(hdev); 1887fe4144d4SJian Shen 1888436667d2SSalil Mehta hclgevf_deferred_task_schedule(hdev); 1889436667d2SSalil Mehta 1890e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1891e2cb1decSSalil Mehta } 1892e2cb1decSSalil Mehta 1893e2cb1decSSalil Mehta static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1894e2cb1decSSalil Mehta { 1895e2cb1decSSalil Mehta hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1896e2cb1decSSalil Mehta } 1897e2cb1decSSalil Mehta 1898b90fcc5bSHuazhong Tan static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1899b90fcc5bSHuazhong Tan u32 *clearval) 1900e2cb1decSSalil Mehta { 190113050921SHuazhong Tan u32 val, cmdq_stat_reg, rst_ing_reg; 1902e2cb1decSSalil Mehta 1903e2cb1decSSalil Mehta /* fetch the events from their corresponding regs */ 190413050921SHuazhong Tan cmdq_stat_reg = hclgevf_read_dev(&hdev->hw, 190513050921SHuazhong Tan HCLGEVF_VECTOR0_CMDQ_STAT_REG); 1906e2cb1decSSalil Mehta 190713050921SHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 1908b90fcc5bSHuazhong Tan rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1909b90fcc5bSHuazhong Tan dev_info(&hdev->pdev->dev, 1910b90fcc5bSHuazhong Tan "receive reset interrupt 0x%x!\n", rst_ing_reg); 1911b90fcc5bSHuazhong Tan set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1912b90fcc5bSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1913ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 191413050921SHuazhong Tan *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B); 1915c88a6e7dSHuazhong Tan hdev->rst_stats.vf_rst_cnt++; 191672e2fb07SHuazhong Tan /* set up VF hardware reset status, its PF will clear 191772e2fb07SHuazhong Tan * this status when PF has initialized done. 191872e2fb07SHuazhong Tan */ 191972e2fb07SHuazhong Tan val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING); 192072e2fb07SHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING, 192172e2fb07SHuazhong Tan val | HCLGEVF_VF_RST_ING_BIT); 1922b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_RST; 1923b90fcc5bSHuazhong Tan } 1924b90fcc5bSHuazhong Tan 1925e2cb1decSSalil Mehta /* check for vector0 mailbox(=CMDQ RX) event source */ 192613050921SHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 192713050921SHuazhong Tan /* for revision 0x21, clearing interrupt is writing bit 0 192813050921SHuazhong Tan * to the clear register, writing bit 1 means to keep the 192913050921SHuazhong Tan * old value. 193013050921SHuazhong Tan * for revision 0x20, the clear register is a read & write 193113050921SHuazhong Tan * register, so we should just write 0 to the bit we are 193213050921SHuazhong Tan * handling, and keep other bits as cmdq_stat_reg. 193313050921SHuazhong Tan */ 193413050921SHuazhong Tan if (hdev->pdev->revision >= 0x21) 193513050921SHuazhong Tan *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 193613050921SHuazhong Tan else 193713050921SHuazhong Tan *clearval = cmdq_stat_reg & 193813050921SHuazhong Tan ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 193913050921SHuazhong Tan 1940b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_MBX; 1941e2cb1decSSalil Mehta } 1942e2cb1decSSalil Mehta 1943e2cb1decSSalil Mehta dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 1944e2cb1decSSalil Mehta 1945b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_OTHER; 1946e2cb1decSSalil Mehta } 1947e2cb1decSSalil Mehta 1948e2cb1decSSalil Mehta static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1949e2cb1decSSalil Mehta { 1950e2cb1decSSalil Mehta writel(en ? 1 : 0, vector->addr); 1951e2cb1decSSalil Mehta } 1952e2cb1decSSalil Mehta 1953e2cb1decSSalil Mehta static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1954e2cb1decSSalil Mehta { 1955b90fcc5bSHuazhong Tan enum hclgevf_evt_cause event_cause; 1956e2cb1decSSalil Mehta struct hclgevf_dev *hdev = data; 1957e2cb1decSSalil Mehta u32 clearval; 1958e2cb1decSSalil Mehta 1959e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 1960b90fcc5bSHuazhong Tan event_cause = hclgevf_check_evt_cause(hdev, &clearval); 1961e2cb1decSSalil Mehta 1962b90fcc5bSHuazhong Tan switch (event_cause) { 1963b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_RST: 1964b90fcc5bSHuazhong Tan hclgevf_reset_task_schedule(hdev); 1965b90fcc5bSHuazhong Tan break; 1966b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_MBX: 196707a0556aSSalil Mehta hclgevf_mbx_handler(hdev); 1968b90fcc5bSHuazhong Tan break; 1969b90fcc5bSHuazhong Tan default: 1970b90fcc5bSHuazhong Tan break; 1971b90fcc5bSHuazhong Tan } 1972e2cb1decSSalil Mehta 1973b90fcc5bSHuazhong Tan if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 1974e2cb1decSSalil Mehta hclgevf_clear_event_cause(hdev, clearval); 1975e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 1976b90fcc5bSHuazhong Tan } 1977e2cb1decSSalil Mehta 1978e2cb1decSSalil Mehta return IRQ_HANDLED; 1979e2cb1decSSalil Mehta } 1980e2cb1decSSalil Mehta 1981e2cb1decSSalil Mehta static int hclgevf_configure(struct hclgevf_dev *hdev) 1982e2cb1decSSalil Mehta { 1983e2cb1decSSalil Mehta int ret; 1984e2cb1decSSalil Mehta 198592f11ea1SJian Shen /* get current port based vlan state from PF */ 198692f11ea1SJian Shen ret = hclgevf_get_port_base_vlan_filter_state(hdev); 198792f11ea1SJian Shen if (ret) 198892f11ea1SJian Shen return ret; 198992f11ea1SJian Shen 1990e2cb1decSSalil Mehta /* get queue configuration from PF */ 19916cee6fc3SJian Shen ret = hclgevf_get_queue_info(hdev); 1992e2cb1decSSalil Mehta if (ret) 1993e2cb1decSSalil Mehta return ret; 1994c0425944SPeng Li 1995c0425944SPeng Li /* get queue depth info from PF */ 1996c0425944SPeng Li ret = hclgevf_get_queue_depth(hdev); 1997c0425944SPeng Li if (ret) 1998c0425944SPeng Li return ret; 1999c0425944SPeng Li 20009c3e7130Sliuzhongzhu ret = hclgevf_get_pf_media_type(hdev); 20019c3e7130Sliuzhongzhu if (ret) 20029c3e7130Sliuzhongzhu return ret; 20039c3e7130Sliuzhongzhu 2004e2cb1decSSalil Mehta /* get tc configuration from PF */ 2005e2cb1decSSalil Mehta return hclgevf_get_tc_info(hdev); 2006e2cb1decSSalil Mehta } 2007e2cb1decSSalil Mehta 20087a01c897SSalil Mehta static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 20097a01c897SSalil Mehta { 20107a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 20111154bb26SPeng Li struct hclgevf_dev *hdev; 20127a01c897SSalil Mehta 20137a01c897SSalil Mehta hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 20147a01c897SSalil Mehta if (!hdev) 20157a01c897SSalil Mehta return -ENOMEM; 20167a01c897SSalil Mehta 20177a01c897SSalil Mehta hdev->pdev = pdev; 20187a01c897SSalil Mehta hdev->ae_dev = ae_dev; 20197a01c897SSalil Mehta ae_dev->priv = hdev; 20207a01c897SSalil Mehta 20217a01c897SSalil Mehta return 0; 20227a01c897SSalil Mehta } 20237a01c897SSalil Mehta 2024e2cb1decSSalil Mehta static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 2025e2cb1decSSalil Mehta { 2026e2cb1decSSalil Mehta struct hnae3_handle *roce = &hdev->roce; 2027e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 2028e2cb1decSSalil Mehta 202907acf909SJian Shen roce->rinfo.num_vectors = hdev->num_roce_msix; 2030e2cb1decSSalil Mehta 2031e2cb1decSSalil Mehta if (hdev->num_msi_left < roce->rinfo.num_vectors || 2032e2cb1decSSalil Mehta hdev->num_msi_left == 0) 2033e2cb1decSSalil Mehta return -EINVAL; 2034e2cb1decSSalil Mehta 203507acf909SJian Shen roce->rinfo.base_vector = hdev->roce_base_vector; 2036e2cb1decSSalil Mehta 2037e2cb1decSSalil Mehta roce->rinfo.netdev = nic->kinfo.netdev; 2038e2cb1decSSalil Mehta roce->rinfo.roce_io_base = hdev->hw.io_base; 2039e2cb1decSSalil Mehta 2040e2cb1decSSalil Mehta roce->pdev = nic->pdev; 2041e2cb1decSSalil Mehta roce->ae_algo = nic->ae_algo; 2042e2cb1decSSalil Mehta roce->numa_node_mask = nic->numa_node_mask; 2043e2cb1decSSalil Mehta 2044e2cb1decSSalil Mehta return 0; 2045e2cb1decSSalil Mehta } 2046e2cb1decSSalil Mehta 2047b26a6feaSPeng Li static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 2048b26a6feaSPeng Li { 2049b26a6feaSPeng Li struct hclgevf_cfg_gro_status_cmd *req; 2050b26a6feaSPeng Li struct hclgevf_desc desc; 2051b26a6feaSPeng Li int ret; 2052b26a6feaSPeng Li 2053b26a6feaSPeng Li if (!hnae3_dev_gro_supported(hdev)) 2054b26a6feaSPeng Li return 0; 2055b26a6feaSPeng Li 2056b26a6feaSPeng Li hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 2057b26a6feaSPeng Li false); 2058b26a6feaSPeng Li req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2059b26a6feaSPeng Li 2060b26a6feaSPeng Li req->gro_en = cpu_to_le16(en ? 1 : 0); 2061b26a6feaSPeng Li 2062b26a6feaSPeng Li ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2063b26a6feaSPeng Li if (ret) 2064b26a6feaSPeng Li dev_err(&hdev->pdev->dev, 2065b26a6feaSPeng Li "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2066b26a6feaSPeng Li 2067b26a6feaSPeng Li return ret; 2068b26a6feaSPeng Li } 2069b26a6feaSPeng Li 2070e2cb1decSSalil Mehta static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2071e2cb1decSSalil Mehta { 2072e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 20734093d1a2SGuangbin Huang int ret; 20744093d1a2SGuangbin Huang u32 i; 2075e2cb1decSSalil Mehta 20764093d1a2SGuangbin Huang rss_cfg->rss_size = hdev->nic.kinfo.rss_size; 2077e2cb1decSSalil Mehta 2078374ad291SJian Shen if (hdev->pdev->revision >= 0x21) { 2079472d7eceSJian Shen rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 2080472d7eceSJian Shen memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 2081374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 2082374ad291SJian Shen 2083374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 2084374ad291SJian Shen rss_cfg->rss_hash_key); 2085374ad291SJian Shen if (ret) 2086374ad291SJian Shen return ret; 2087d97b3072SJian Shen 2088d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = 2089d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2090d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = 2091d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2092d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = 2093d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2094d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = 2095d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2096d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = 2097d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2098d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = 2099d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2100d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = 2101d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2102d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = 2103d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2104d97b3072SJian Shen 2105d97b3072SJian Shen ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 2106d97b3072SJian Shen if (ret) 2107d97b3072SJian Shen return ret; 2108d97b3072SJian Shen 2109374ad291SJian Shen } 2110374ad291SJian Shen 21119b2f3477SWeihang Li /* Initialize RSS indirect table */ 2112e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 21134093d1a2SGuangbin Huang rss_cfg->rss_indirection_tbl[i] = i % rss_cfg->rss_size; 2114e2cb1decSSalil Mehta 2115e2cb1decSSalil Mehta ret = hclgevf_set_rss_indir_table(hdev); 2116e2cb1decSSalil Mehta if (ret) 2117e2cb1decSSalil Mehta return ret; 2118e2cb1decSSalil Mehta 21194093d1a2SGuangbin Huang return hclgevf_set_rss_tc_mode(hdev, rss_cfg->rss_size); 2120e2cb1decSSalil Mehta } 2121e2cb1decSSalil Mehta 2122e2cb1decSSalil Mehta static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2123e2cb1decSSalil Mehta { 2124e2cb1decSSalil Mehta return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2125e2cb1decSSalil Mehta false); 2126e2cb1decSSalil Mehta } 2127e2cb1decSSalil Mehta 21288cdb992fSJian Shen static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 21298cdb992fSJian Shen { 21308cdb992fSJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 21318cdb992fSJian Shen 21328cdb992fSJian Shen if (enable) { 21338cdb992fSJian Shen mod_timer(&hdev->service_timer, jiffies + HZ); 21348cdb992fSJian Shen } else { 21358cdb992fSJian Shen del_timer_sync(&hdev->service_timer); 21368cdb992fSJian Shen cancel_work_sync(&hdev->service_task); 21378cdb992fSJian Shen clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 21388cdb992fSJian Shen } 21398cdb992fSJian Shen } 21408cdb992fSJian Shen 2141e2cb1decSSalil Mehta static int hclgevf_ae_start(struct hnae3_handle *handle) 2142e2cb1decSSalil Mehta { 2143e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2144e2cb1decSSalil Mehta 2145e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 2146e2cb1decSSalil Mehta 2147e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 2148e2cb1decSSalil Mehta 21499194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 21509194d18bSliuzhongzhu 2151e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2152e2cb1decSSalil Mehta 2153e2cb1decSSalil Mehta return 0; 2154e2cb1decSSalil Mehta } 2155e2cb1decSSalil Mehta 2156e2cb1decSSalil Mehta static void hclgevf_ae_stop(struct hnae3_handle *handle) 2157e2cb1decSSalil Mehta { 2158e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 215939cfbc9cSHuazhong Tan int i; 2160e2cb1decSSalil Mehta 21612f7e4896SFuyun Liang set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 21622f7e4896SFuyun Liang 2163146e92c1SHuazhong Tan if (hdev->reset_type != HNAE3_VF_RESET) 216439cfbc9cSHuazhong Tan for (i = 0; i < handle->kinfo.num_tqps; i++) 2165146e92c1SHuazhong Tan if (hclgevf_reset_tqp(handle, i)) 2166146e92c1SHuazhong Tan break; 216739cfbc9cSHuazhong Tan 2168e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 21698cc6c1f7SFuyun Liang hclgevf_update_link_status(hdev, 0); 2170e2cb1decSSalil Mehta } 2171e2cb1decSSalil Mehta 2172a6d818e3SYunsheng Lin static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2173a6d818e3SYunsheng Lin { 2174a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2175a6d818e3SYunsheng Lin u8 msg_data; 2176a6d818e3SYunsheng Lin 2177a6d818e3SYunsheng Lin msg_data = alive ? 1 : 0; 2178a6d818e3SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE, 2179a6d818e3SYunsheng Lin 0, &msg_data, 1, false, NULL, 0); 2180a6d818e3SYunsheng Lin } 2181a6d818e3SYunsheng Lin 2182a6d818e3SYunsheng Lin static int hclgevf_client_start(struct hnae3_handle *handle) 2183a6d818e3SYunsheng Lin { 2184a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2185e233516eSHuazhong Tan int ret; 2186e233516eSHuazhong Tan 2187e233516eSHuazhong Tan ret = hclgevf_set_alive(handle, true); 2188e233516eSHuazhong Tan if (ret) 2189e233516eSHuazhong Tan return ret; 2190a6d818e3SYunsheng Lin 2191b37ce587SYufeng Mo mod_timer(&hdev->keep_alive_timer, jiffies + 2192b37ce587SYufeng Mo HCLGEVF_KEEP_ALIVE_TASK_INTERVAL * HZ); 2193e233516eSHuazhong Tan 2194e233516eSHuazhong Tan return 0; 2195a6d818e3SYunsheng Lin } 2196a6d818e3SYunsheng Lin 2197a6d818e3SYunsheng Lin static void hclgevf_client_stop(struct hnae3_handle *handle) 2198a6d818e3SYunsheng Lin { 2199a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2200a6d818e3SYunsheng Lin int ret; 2201a6d818e3SYunsheng Lin 2202a6d818e3SYunsheng Lin ret = hclgevf_set_alive(handle, false); 2203a6d818e3SYunsheng Lin if (ret) 2204a6d818e3SYunsheng Lin dev_warn(&hdev->pdev->dev, 2205a6d818e3SYunsheng Lin "%s failed %d\n", __func__, ret); 2206a6d818e3SYunsheng Lin 2207a6d818e3SYunsheng Lin del_timer_sync(&hdev->keep_alive_timer); 2208a6d818e3SYunsheng Lin cancel_work_sync(&hdev->keep_alive_task); 2209a6d818e3SYunsheng Lin } 2210a6d818e3SYunsheng Lin 2211e2cb1decSSalil Mehta static void hclgevf_state_init(struct hclgevf_dev *hdev) 2212e2cb1decSSalil Mehta { 2213e2cb1decSSalil Mehta /* setup tasks for the MBX */ 2214e2cb1decSSalil Mehta INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 2215e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2216e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2217e2cb1decSSalil Mehta 2218e2cb1decSSalil Mehta /* setup tasks for service timer */ 2219e2cb1decSSalil Mehta timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 2220e2cb1decSSalil Mehta 2221e2cb1decSSalil Mehta INIT_WORK(&hdev->service_task, hclgevf_service_task); 2222e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2223e2cb1decSSalil Mehta 222435a1e503SSalil Mehta INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task); 222535a1e503SSalil Mehta 2226e2cb1decSSalil Mehta mutex_init(&hdev->mbx_resp.mbx_mutex); 2227e2cb1decSSalil Mehta 2228e2cb1decSSalil Mehta /* bring the device down */ 2229e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2230e2cb1decSSalil Mehta } 2231e2cb1decSSalil Mehta 2232e2cb1decSSalil Mehta static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2233e2cb1decSSalil Mehta { 2234e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2235acfc3d55SHuazhong Tan set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2236e2cb1decSSalil Mehta 2237e233516eSHuazhong Tan if (hdev->keep_alive_timer.function) 2238e233516eSHuazhong Tan del_timer_sync(&hdev->keep_alive_timer); 2239e233516eSHuazhong Tan if (hdev->keep_alive_task.func) 2240e233516eSHuazhong Tan cancel_work_sync(&hdev->keep_alive_task); 2241e2cb1decSSalil Mehta if (hdev->service_timer.function) 2242e2cb1decSSalil Mehta del_timer_sync(&hdev->service_timer); 2243e2cb1decSSalil Mehta if (hdev->service_task.func) 2244e2cb1decSSalil Mehta cancel_work_sync(&hdev->service_task); 2245e2cb1decSSalil Mehta if (hdev->mbx_service_task.func) 2246e2cb1decSSalil Mehta cancel_work_sync(&hdev->mbx_service_task); 224735a1e503SSalil Mehta if (hdev->rst_service_task.func) 224835a1e503SSalil Mehta cancel_work_sync(&hdev->rst_service_task); 2249e2cb1decSSalil Mehta 2250e2cb1decSSalil Mehta mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2251e2cb1decSSalil Mehta } 2252e2cb1decSSalil Mehta 2253e2cb1decSSalil Mehta static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2254e2cb1decSSalil Mehta { 2255e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2256e2cb1decSSalil Mehta int vectors; 2257e2cb1decSSalil Mehta int i; 2258e2cb1decSSalil Mehta 225907acf909SJian Shen if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) 226007acf909SJian Shen vectors = pci_alloc_irq_vectors(pdev, 226107acf909SJian Shen hdev->roce_base_msix_offset + 1, 226207acf909SJian Shen hdev->num_msi, 226307acf909SJian Shen PCI_IRQ_MSIX); 226407acf909SJian Shen else 2265e2cb1decSSalil Mehta vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 2266e2cb1decSSalil Mehta PCI_IRQ_MSI | PCI_IRQ_MSIX); 226707acf909SJian Shen 2268e2cb1decSSalil Mehta if (vectors < 0) { 2269e2cb1decSSalil Mehta dev_err(&pdev->dev, 2270e2cb1decSSalil Mehta "failed(%d) to allocate MSI/MSI-X vectors\n", 2271e2cb1decSSalil Mehta vectors); 2272e2cb1decSSalil Mehta return vectors; 2273e2cb1decSSalil Mehta } 2274e2cb1decSSalil Mehta if (vectors < hdev->num_msi) 2275e2cb1decSSalil Mehta dev_warn(&hdev->pdev->dev, 2276e2cb1decSSalil Mehta "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2277e2cb1decSSalil Mehta hdev->num_msi, vectors); 2278e2cb1decSSalil Mehta 2279e2cb1decSSalil Mehta hdev->num_msi = vectors; 2280e2cb1decSSalil Mehta hdev->num_msi_left = vectors; 2281e2cb1decSSalil Mehta hdev->base_msi_vector = pdev->irq; 228207acf909SJian Shen hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2283e2cb1decSSalil Mehta 2284e2cb1decSSalil Mehta hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2285e2cb1decSSalil Mehta sizeof(u16), GFP_KERNEL); 2286e2cb1decSSalil Mehta if (!hdev->vector_status) { 2287e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2288e2cb1decSSalil Mehta return -ENOMEM; 2289e2cb1decSSalil Mehta } 2290e2cb1decSSalil Mehta 2291e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 2292e2cb1decSSalil Mehta hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2293e2cb1decSSalil Mehta 2294e2cb1decSSalil Mehta hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2295e2cb1decSSalil Mehta sizeof(int), GFP_KERNEL); 2296e2cb1decSSalil Mehta if (!hdev->vector_irq) { 2297862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2298e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2299e2cb1decSSalil Mehta return -ENOMEM; 2300e2cb1decSSalil Mehta } 2301e2cb1decSSalil Mehta 2302e2cb1decSSalil Mehta return 0; 2303e2cb1decSSalil Mehta } 2304e2cb1decSSalil Mehta 2305e2cb1decSSalil Mehta static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2306e2cb1decSSalil Mehta { 2307e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2308e2cb1decSSalil Mehta 2309862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2310862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_irq); 2311e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2312e2cb1decSSalil Mehta } 2313e2cb1decSSalil Mehta 2314e2cb1decSSalil Mehta static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2315e2cb1decSSalil Mehta { 2316cdd332acSGuojia Liao int ret; 2317e2cb1decSSalil Mehta 2318e2cb1decSSalil Mehta hclgevf_get_misc_vector(hdev); 2319e2cb1decSSalil Mehta 2320e2cb1decSSalil Mehta ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2321e2cb1decSSalil Mehta 0, "hclgevf_cmd", hdev); 2322e2cb1decSSalil Mehta if (ret) { 2323e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2324e2cb1decSSalil Mehta hdev->misc_vector.vector_irq); 2325e2cb1decSSalil Mehta return ret; 2326e2cb1decSSalil Mehta } 2327e2cb1decSSalil Mehta 23281819e409SXi Wang hclgevf_clear_event_cause(hdev, 0); 23291819e409SXi Wang 2330e2cb1decSSalil Mehta /* enable misc. vector(vector 0) */ 2331e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2332e2cb1decSSalil Mehta 2333e2cb1decSSalil Mehta return ret; 2334e2cb1decSSalil Mehta } 2335e2cb1decSSalil Mehta 2336e2cb1decSSalil Mehta static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2337e2cb1decSSalil Mehta { 2338e2cb1decSSalil Mehta /* disable misc vector(vector 0) */ 2339e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 23401819e409SXi Wang synchronize_irq(hdev->misc_vector.vector_irq); 2341e2cb1decSSalil Mehta free_irq(hdev->misc_vector.vector_irq, hdev); 2342e2cb1decSSalil Mehta hclgevf_free_vector(hdev, 0); 2343e2cb1decSSalil Mehta } 2344e2cb1decSSalil Mehta 2345bb87be87SYonglong Liu static void hclgevf_info_show(struct hclgevf_dev *hdev) 2346bb87be87SYonglong Liu { 2347bb87be87SYonglong Liu struct device *dev = &hdev->pdev->dev; 2348bb87be87SYonglong Liu 2349bb87be87SYonglong Liu dev_info(dev, "VF info begin:\n"); 2350bb87be87SYonglong Liu 2351bb87be87SYonglong Liu dev_info(dev, "Task queue pairs numbers: %d\n", hdev->num_tqps); 2352bb87be87SYonglong Liu dev_info(dev, "Desc num per TX queue: %d\n", hdev->num_tx_desc); 2353bb87be87SYonglong Liu dev_info(dev, "Desc num per RX queue: %d\n", hdev->num_rx_desc); 2354bb87be87SYonglong Liu dev_info(dev, "Numbers of vports: %d\n", hdev->num_alloc_vport); 2355bb87be87SYonglong Liu dev_info(dev, "HW tc map: %d\n", hdev->hw_tc_map); 2356bb87be87SYonglong Liu dev_info(dev, "PF media type of this VF: %d\n", 2357bb87be87SYonglong Liu hdev->hw.mac.media_type); 2358bb87be87SYonglong Liu 2359bb87be87SYonglong Liu dev_info(dev, "VF info end.\n"); 2360bb87be87SYonglong Liu } 2361bb87be87SYonglong Liu 23621db58f86SHuazhong Tan static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 23631db58f86SHuazhong Tan struct hnae3_client *client) 23641db58f86SHuazhong Tan { 23651db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 23661db58f86SHuazhong Tan int ret; 23671db58f86SHuazhong Tan 23681db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->nic); 23691db58f86SHuazhong Tan if (ret) 23701db58f86SHuazhong Tan return ret; 23711db58f86SHuazhong Tan 23721db58f86SHuazhong Tan set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 23731db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 23741db58f86SHuazhong Tan 23751db58f86SHuazhong Tan if (netif_msg_drv(&hdev->nic)) 23761db58f86SHuazhong Tan hclgevf_info_show(hdev); 23771db58f86SHuazhong Tan 23781db58f86SHuazhong Tan return 0; 23791db58f86SHuazhong Tan } 23801db58f86SHuazhong Tan 23811db58f86SHuazhong Tan static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 23821db58f86SHuazhong Tan struct hnae3_client *client) 23831db58f86SHuazhong Tan { 23841db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 23851db58f86SHuazhong Tan int ret; 23861db58f86SHuazhong Tan 23871db58f86SHuazhong Tan if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 23881db58f86SHuazhong Tan !hdev->nic_client) 23891db58f86SHuazhong Tan return 0; 23901db58f86SHuazhong Tan 23911db58f86SHuazhong Tan ret = hclgevf_init_roce_base_info(hdev); 23921db58f86SHuazhong Tan if (ret) 23931db58f86SHuazhong Tan return ret; 23941db58f86SHuazhong Tan 23951db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->roce); 23961db58f86SHuazhong Tan if (ret) 23971db58f86SHuazhong Tan return ret; 23981db58f86SHuazhong Tan 23991db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 24001db58f86SHuazhong Tan 24011db58f86SHuazhong Tan return 0; 24021db58f86SHuazhong Tan } 24031db58f86SHuazhong Tan 2404e718a93fSPeng Li static int hclgevf_init_client_instance(struct hnae3_client *client, 2405e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2406e2cb1decSSalil Mehta { 2407e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2408e2cb1decSSalil Mehta int ret; 2409e2cb1decSSalil Mehta 2410e2cb1decSSalil Mehta switch (client->type) { 2411e2cb1decSSalil Mehta case HNAE3_CLIENT_KNIC: 2412e2cb1decSSalil Mehta hdev->nic_client = client; 2413e2cb1decSSalil Mehta hdev->nic.client = client; 2414e2cb1decSSalil Mehta 24151db58f86SHuazhong Tan ret = hclgevf_init_nic_client_instance(ae_dev, client); 2416e2cb1decSSalil Mehta if (ret) 241749dd8054SJian Shen goto clear_nic; 2418e2cb1decSSalil Mehta 24191db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, 24201db58f86SHuazhong Tan hdev->roce_client); 2421e2cb1decSSalil Mehta if (ret) 242249dd8054SJian Shen goto clear_roce; 2423d9f28fc2SJian Shen 2424e2cb1decSSalil Mehta break; 2425e2cb1decSSalil Mehta case HNAE3_CLIENT_ROCE: 2426544a7bcdSLijun Ou if (hnae3_dev_roce_supported(hdev)) { 2427e2cb1decSSalil Mehta hdev->roce_client = client; 2428e2cb1decSSalil Mehta hdev->roce.client = client; 2429544a7bcdSLijun Ou } 2430e2cb1decSSalil Mehta 24311db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, client); 2432e2cb1decSSalil Mehta if (ret) 243349dd8054SJian Shen goto clear_roce; 2434e2cb1decSSalil Mehta 2435fa7a4bd5SJian Shen break; 2436fa7a4bd5SJian Shen default: 2437fa7a4bd5SJian Shen return -EINVAL; 2438e2cb1decSSalil Mehta } 2439e2cb1decSSalil Mehta 2440e2cb1decSSalil Mehta return 0; 244149dd8054SJian Shen 244249dd8054SJian Shen clear_nic: 244349dd8054SJian Shen hdev->nic_client = NULL; 244449dd8054SJian Shen hdev->nic.client = NULL; 244549dd8054SJian Shen return ret; 244649dd8054SJian Shen clear_roce: 244749dd8054SJian Shen hdev->roce_client = NULL; 244849dd8054SJian Shen hdev->roce.client = NULL; 244949dd8054SJian Shen return ret; 2450e2cb1decSSalil Mehta } 2451e2cb1decSSalil Mehta 2452e718a93fSPeng Li static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2453e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2454e2cb1decSSalil Mehta { 2455e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2456e718a93fSPeng Li 2457e2cb1decSSalil Mehta /* un-init roce, if it exists */ 245849dd8054SJian Shen if (hdev->roce_client) { 2459e2cb1decSSalil Mehta hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 246049dd8054SJian Shen hdev->roce_client = NULL; 246149dd8054SJian Shen hdev->roce.client = NULL; 246249dd8054SJian Shen } 2463e2cb1decSSalil Mehta 2464e2cb1decSSalil Mehta /* un-init nic/unic, if this was not called by roce client */ 246549dd8054SJian Shen if (client->ops->uninit_instance && hdev->nic_client && 246649dd8054SJian Shen client->type != HNAE3_CLIENT_ROCE) { 246725d1817cSHuazhong Tan clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 246825d1817cSHuazhong Tan 2469e2cb1decSSalil Mehta client->ops->uninit_instance(&hdev->nic, 0); 247049dd8054SJian Shen hdev->nic_client = NULL; 247149dd8054SJian Shen hdev->nic.client = NULL; 247249dd8054SJian Shen } 2473e2cb1decSSalil Mehta } 2474e2cb1decSSalil Mehta 2475e2cb1decSSalil Mehta static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2476e2cb1decSSalil Mehta { 2477e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2478e2cb1decSSalil Mehta struct hclgevf_hw *hw; 2479e2cb1decSSalil Mehta int ret; 2480e2cb1decSSalil Mehta 2481e2cb1decSSalil Mehta ret = pci_enable_device(pdev); 2482e2cb1decSSalil Mehta if (ret) { 2483e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed to enable PCI device\n"); 24843e249d3bSFuyun Liang return ret; 2485e2cb1decSSalil Mehta } 2486e2cb1decSSalil Mehta 2487e2cb1decSSalil Mehta ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2488e2cb1decSSalil Mehta if (ret) { 2489e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2490e2cb1decSSalil Mehta goto err_disable_device; 2491e2cb1decSSalil Mehta } 2492e2cb1decSSalil Mehta 2493e2cb1decSSalil Mehta ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2494e2cb1decSSalil Mehta if (ret) { 2495e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2496e2cb1decSSalil Mehta goto err_disable_device; 2497e2cb1decSSalil Mehta } 2498e2cb1decSSalil Mehta 2499e2cb1decSSalil Mehta pci_set_master(pdev); 2500e2cb1decSSalil Mehta hw = &hdev->hw; 2501e2cb1decSSalil Mehta hw->hdev = hdev; 25022e1ea493SPeng Li hw->io_base = pci_iomap(pdev, 2, 0); 2503e2cb1decSSalil Mehta if (!hw->io_base) { 2504e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't map configuration register space\n"); 2505e2cb1decSSalil Mehta ret = -ENOMEM; 2506e2cb1decSSalil Mehta goto err_clr_master; 2507e2cb1decSSalil Mehta } 2508e2cb1decSSalil Mehta 2509e2cb1decSSalil Mehta return 0; 2510e2cb1decSSalil Mehta 2511e2cb1decSSalil Mehta err_clr_master: 2512e2cb1decSSalil Mehta pci_clear_master(pdev); 2513e2cb1decSSalil Mehta pci_release_regions(pdev); 2514e2cb1decSSalil Mehta err_disable_device: 2515e2cb1decSSalil Mehta pci_disable_device(pdev); 25163e249d3bSFuyun Liang 2517e2cb1decSSalil Mehta return ret; 2518e2cb1decSSalil Mehta } 2519e2cb1decSSalil Mehta 2520e2cb1decSSalil Mehta static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2521e2cb1decSSalil Mehta { 2522e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2523e2cb1decSSalil Mehta 2524e2cb1decSSalil Mehta pci_iounmap(pdev, hdev->hw.io_base); 2525e2cb1decSSalil Mehta pci_clear_master(pdev); 2526e2cb1decSSalil Mehta pci_release_regions(pdev); 2527e2cb1decSSalil Mehta pci_disable_device(pdev); 2528e2cb1decSSalil Mehta } 2529e2cb1decSSalil Mehta 253007acf909SJian Shen static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 253107acf909SJian Shen { 253207acf909SJian Shen struct hclgevf_query_res_cmd *req; 253307acf909SJian Shen struct hclgevf_desc desc; 253407acf909SJian Shen int ret; 253507acf909SJian Shen 253607acf909SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 253707acf909SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 253807acf909SJian Shen if (ret) { 253907acf909SJian Shen dev_err(&hdev->pdev->dev, 254007acf909SJian Shen "query vf resource failed, ret = %d.\n", ret); 254107acf909SJian Shen return ret; 254207acf909SJian Shen } 254307acf909SJian Shen 254407acf909SJian Shen req = (struct hclgevf_query_res_cmd *)desc.data; 254507acf909SJian Shen 254607acf909SJian Shen if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) { 254707acf909SJian Shen hdev->roce_base_msix_offset = 254807acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 254907acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_M, 255007acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_S); 255107acf909SJian Shen hdev->num_roce_msix = 255207acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 255307acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 255407acf909SJian Shen 255507acf909SJian Shen /* VF should have NIC vectors and Roce vectors, NIC vectors 255607acf909SJian Shen * are queued before Roce vectors. The offset is fixed to 64. 255707acf909SJian Shen */ 255807acf909SJian Shen hdev->num_msi = hdev->num_roce_msix + 255907acf909SJian Shen hdev->roce_base_msix_offset; 256007acf909SJian Shen } else { 256107acf909SJian Shen hdev->num_msi = 256207acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 256307acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 256407acf909SJian Shen } 256507acf909SJian Shen 256607acf909SJian Shen return 0; 256707acf909SJian Shen } 256807acf909SJian Shen 2569862d969aSHuazhong Tan static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2570862d969aSHuazhong Tan { 2571862d969aSHuazhong Tan struct pci_dev *pdev = hdev->pdev; 2572862d969aSHuazhong Tan int ret = 0; 2573862d969aSHuazhong Tan 2574862d969aSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2575862d969aSHuazhong Tan test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2576862d969aSHuazhong Tan hclgevf_misc_irq_uninit(hdev); 2577862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2578862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2579862d969aSHuazhong Tan } 2580862d969aSHuazhong Tan 2581862d969aSHuazhong Tan if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2582862d969aSHuazhong Tan pci_set_master(pdev); 2583862d969aSHuazhong Tan ret = hclgevf_init_msi(hdev); 2584862d969aSHuazhong Tan if (ret) { 2585862d969aSHuazhong Tan dev_err(&pdev->dev, 2586862d969aSHuazhong Tan "failed(%d) to init MSI/MSI-X\n", ret); 2587862d969aSHuazhong Tan return ret; 2588862d969aSHuazhong Tan } 2589862d969aSHuazhong Tan 2590862d969aSHuazhong Tan ret = hclgevf_misc_irq_init(hdev); 2591862d969aSHuazhong Tan if (ret) { 2592862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2593862d969aSHuazhong Tan dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2594862d969aSHuazhong Tan ret); 2595862d969aSHuazhong Tan return ret; 2596862d969aSHuazhong Tan } 2597862d969aSHuazhong Tan 2598862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2599862d969aSHuazhong Tan } 2600862d969aSHuazhong Tan 2601862d969aSHuazhong Tan return ret; 2602862d969aSHuazhong Tan } 2603862d969aSHuazhong Tan 26049c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2605e2cb1decSSalil Mehta { 26067a01c897SSalil Mehta struct pci_dev *pdev = hdev->pdev; 2607e2cb1decSSalil Mehta int ret; 2608e2cb1decSSalil Mehta 2609862d969aSHuazhong Tan ret = hclgevf_pci_reset(hdev); 2610862d969aSHuazhong Tan if (ret) { 2611862d969aSHuazhong Tan dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2612862d969aSHuazhong Tan return ret; 2613862d969aSHuazhong Tan } 2614862d969aSHuazhong Tan 26159c6f7085SHuazhong Tan ret = hclgevf_cmd_init(hdev); 26169c6f7085SHuazhong Tan if (ret) { 26179c6f7085SHuazhong Tan dev_err(&pdev->dev, "cmd failed %d\n", ret); 26189c6f7085SHuazhong Tan return ret; 26197a01c897SSalil Mehta } 2620e2cb1decSSalil Mehta 26219c6f7085SHuazhong Tan ret = hclgevf_rss_init_hw(hdev); 26229c6f7085SHuazhong Tan if (ret) { 26239c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 26249c6f7085SHuazhong Tan "failed(%d) to initialize RSS\n", ret); 26259c6f7085SHuazhong Tan return ret; 26269c6f7085SHuazhong Tan } 26279c6f7085SHuazhong Tan 2628b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2629b26a6feaSPeng Li if (ret) 2630b26a6feaSPeng Li return ret; 2631b26a6feaSPeng Li 26329c6f7085SHuazhong Tan ret = hclgevf_init_vlan_config(hdev); 26339c6f7085SHuazhong Tan if (ret) { 26349c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 26359c6f7085SHuazhong Tan "failed(%d) to initialize VLAN config\n", ret); 26369c6f7085SHuazhong Tan return ret; 26379c6f7085SHuazhong Tan } 26389c6f7085SHuazhong Tan 26399c6f7085SHuazhong Tan dev_info(&hdev->pdev->dev, "Reset done\n"); 26409c6f7085SHuazhong Tan 26419c6f7085SHuazhong Tan return 0; 26429c6f7085SHuazhong Tan } 26439c6f7085SHuazhong Tan 26449c6f7085SHuazhong Tan static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 26459c6f7085SHuazhong Tan { 26469c6f7085SHuazhong Tan struct pci_dev *pdev = hdev->pdev; 26479c6f7085SHuazhong Tan int ret; 26489c6f7085SHuazhong Tan 2649e2cb1decSSalil Mehta ret = hclgevf_pci_init(hdev); 2650e2cb1decSSalil Mehta if (ret) { 2651e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI initialization failed\n"); 2652e2cb1decSSalil Mehta return ret; 2653e2cb1decSSalil Mehta } 2654e2cb1decSSalil Mehta 26558b0195a3SHuazhong Tan ret = hclgevf_cmd_queue_init(hdev); 26568b0195a3SHuazhong Tan if (ret) { 26578b0195a3SHuazhong Tan dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret); 26588b0195a3SHuazhong Tan goto err_cmd_queue_init; 26598b0195a3SHuazhong Tan } 26608b0195a3SHuazhong Tan 2661eddf0462SYunsheng Lin ret = hclgevf_cmd_init(hdev); 2662eddf0462SYunsheng Lin if (ret) 2663eddf0462SYunsheng Lin goto err_cmd_init; 2664eddf0462SYunsheng Lin 266507acf909SJian Shen /* Get vf resource */ 266607acf909SJian Shen ret = hclgevf_query_vf_resource(hdev); 266707acf909SJian Shen if (ret) { 266807acf909SJian Shen dev_err(&hdev->pdev->dev, 266907acf909SJian Shen "Query vf status error, ret = %d.\n", ret); 26708b0195a3SHuazhong Tan goto err_cmd_init; 267107acf909SJian Shen } 267207acf909SJian Shen 267307acf909SJian Shen ret = hclgevf_init_msi(hdev); 267407acf909SJian Shen if (ret) { 267507acf909SJian Shen dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 26768b0195a3SHuazhong Tan goto err_cmd_init; 267707acf909SJian Shen } 267807acf909SJian Shen 267907acf909SJian Shen hclgevf_state_init(hdev); 2680dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 268107acf909SJian Shen 2682e2cb1decSSalil Mehta ret = hclgevf_misc_irq_init(hdev); 2683e2cb1decSSalil Mehta if (ret) { 2684e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2685e2cb1decSSalil Mehta ret); 2686e2cb1decSSalil Mehta goto err_misc_irq_init; 2687e2cb1decSSalil Mehta } 2688e2cb1decSSalil Mehta 2689862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2690862d969aSHuazhong Tan 2691e2cb1decSSalil Mehta ret = hclgevf_configure(hdev); 2692e2cb1decSSalil Mehta if (ret) { 2693e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2694e2cb1decSSalil Mehta goto err_config; 2695e2cb1decSSalil Mehta } 2696e2cb1decSSalil Mehta 2697e2cb1decSSalil Mehta ret = hclgevf_alloc_tqps(hdev); 2698e2cb1decSSalil Mehta if (ret) { 2699e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2700e2cb1decSSalil Mehta goto err_config; 2701e2cb1decSSalil Mehta } 2702e2cb1decSSalil Mehta 2703e2cb1decSSalil Mehta ret = hclgevf_set_handle_info(hdev); 2704e2cb1decSSalil Mehta if (ret) { 2705e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 2706e2cb1decSSalil Mehta goto err_config; 2707e2cb1decSSalil Mehta } 2708e2cb1decSSalil Mehta 2709b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2710b26a6feaSPeng Li if (ret) 2711b26a6feaSPeng Li goto err_config; 2712b26a6feaSPeng Li 2713e2cb1decSSalil Mehta /* Initialize RSS for this VF */ 2714e2cb1decSSalil Mehta ret = hclgevf_rss_init_hw(hdev); 2715e2cb1decSSalil Mehta if (ret) { 2716e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2717e2cb1decSSalil Mehta "failed(%d) to initialize RSS\n", ret); 2718e2cb1decSSalil Mehta goto err_config; 2719e2cb1decSSalil Mehta } 2720e2cb1decSSalil Mehta 2721e2cb1decSSalil Mehta ret = hclgevf_init_vlan_config(hdev); 2722e2cb1decSSalil Mehta if (ret) { 2723e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2724e2cb1decSSalil Mehta "failed(%d) to initialize VLAN config\n", ret); 2725e2cb1decSSalil Mehta goto err_config; 2726e2cb1decSSalil Mehta } 2727e2cb1decSSalil Mehta 27280742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 272908d80a4cSHuazhong Tan dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 273008d80a4cSHuazhong Tan HCLGEVF_DRIVER_NAME); 2731e2cb1decSSalil Mehta 2732e2cb1decSSalil Mehta return 0; 2733e2cb1decSSalil Mehta 2734e2cb1decSSalil Mehta err_config: 2735e2cb1decSSalil Mehta hclgevf_misc_irq_uninit(hdev); 2736e2cb1decSSalil Mehta err_misc_irq_init: 2737e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2738e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 273907acf909SJian Shen err_cmd_init: 27408b0195a3SHuazhong Tan hclgevf_cmd_uninit(hdev); 27418b0195a3SHuazhong Tan err_cmd_queue_init: 2742e2cb1decSSalil Mehta hclgevf_pci_uninit(hdev); 2743862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2744e2cb1decSSalil Mehta return ret; 2745e2cb1decSSalil Mehta } 2746e2cb1decSSalil Mehta 27477a01c897SSalil Mehta static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2748e2cb1decSSalil Mehta { 2749e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2750862d969aSHuazhong Tan 2751862d969aSHuazhong Tan if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2752eddf0462SYunsheng Lin hclgevf_misc_irq_uninit(hdev); 2753e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 27547a01c897SSalil Mehta } 27557a01c897SSalil Mehta 2756e3338205SHuazhong Tan hclgevf_pci_uninit(hdev); 2757862d969aSHuazhong Tan hclgevf_cmd_uninit(hdev); 2758862d969aSHuazhong Tan } 2759862d969aSHuazhong Tan 27607a01c897SSalil Mehta static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 27617a01c897SSalil Mehta { 27627a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 2763a6d818e3SYunsheng Lin struct hclgevf_dev *hdev; 27647a01c897SSalil Mehta int ret; 27657a01c897SSalil Mehta 27667a01c897SSalil Mehta ret = hclgevf_alloc_hdev(ae_dev); 27677a01c897SSalil Mehta if (ret) { 27687a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device allocation failed\n"); 27697a01c897SSalil Mehta return ret; 27707a01c897SSalil Mehta } 27717a01c897SSalil Mehta 27727a01c897SSalil Mehta ret = hclgevf_init_hdev(ae_dev->priv); 2773a6d818e3SYunsheng Lin if (ret) { 27747a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device initialization failed\n"); 27757a01c897SSalil Mehta return ret; 27767a01c897SSalil Mehta } 27777a01c897SSalil Mehta 2778a6d818e3SYunsheng Lin hdev = ae_dev->priv; 2779a6d818e3SYunsheng Lin timer_setup(&hdev->keep_alive_timer, hclgevf_keep_alive_timer, 0); 2780a6d818e3SYunsheng Lin INIT_WORK(&hdev->keep_alive_task, hclgevf_keep_alive_task); 2781a6d818e3SYunsheng Lin 2782a6d818e3SYunsheng Lin return 0; 2783a6d818e3SYunsheng Lin } 2784a6d818e3SYunsheng Lin 27857a01c897SSalil Mehta static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 27867a01c897SSalil Mehta { 27877a01c897SSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 27887a01c897SSalil Mehta 27897a01c897SSalil Mehta hclgevf_uninit_hdev(hdev); 2790e2cb1decSSalil Mehta ae_dev->priv = NULL; 2791e2cb1decSSalil Mehta } 2792e2cb1decSSalil Mehta 2793849e4607SPeng Li static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2794849e4607SPeng Li { 2795849e4607SPeng Li struct hnae3_handle *nic = &hdev->nic; 2796849e4607SPeng Li struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2797849e4607SPeng Li 27988be73621SHuazhong Tan return min_t(u32, hdev->rss_size_max, 27998be73621SHuazhong Tan hdev->num_tqps / kinfo->num_tc); 2800849e4607SPeng Li } 2801849e4607SPeng Li 2802849e4607SPeng Li /** 2803849e4607SPeng Li * hclgevf_get_channels - Get the current channels enabled and max supported. 2804849e4607SPeng Li * @handle: hardware information for network interface 2805849e4607SPeng Li * @ch: ethtool channels structure 2806849e4607SPeng Li * 2807849e4607SPeng Li * We don't support separate tx and rx queues as channels. The other count 2808849e4607SPeng Li * represents how many queues are being used for control. max_combined counts 2809849e4607SPeng Li * how many queue pairs we can support. They may not be mapped 1 to 1 with 2810849e4607SPeng Li * q_vectors since we support a lot more queue pairs than q_vectors. 2811849e4607SPeng Li **/ 2812849e4607SPeng Li static void hclgevf_get_channels(struct hnae3_handle *handle, 2813849e4607SPeng Li struct ethtool_channels *ch) 2814849e4607SPeng Li { 2815849e4607SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2816849e4607SPeng Li 2817849e4607SPeng Li ch->max_combined = hclgevf_get_max_channels(hdev); 2818849e4607SPeng Li ch->other_count = 0; 2819849e4607SPeng Li ch->max_other = 0; 28208be73621SHuazhong Tan ch->combined_count = handle->kinfo.rss_size; 2821849e4607SPeng Li } 2822849e4607SPeng Li 2823cc719218SPeng Li static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 28240d43bf45SHuazhong Tan u16 *alloc_tqps, u16 *max_rss_size) 2825cc719218SPeng Li { 2826cc719218SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2827cc719218SPeng Li 28280d43bf45SHuazhong Tan *alloc_tqps = hdev->num_tqps; 2829cc719218SPeng Li *max_rss_size = hdev->rss_size_max; 2830cc719218SPeng Li } 2831cc719218SPeng Li 28324093d1a2SGuangbin Huang static void hclgevf_update_rss_size(struct hnae3_handle *handle, 28334093d1a2SGuangbin Huang u32 new_tqps_num) 28344093d1a2SGuangbin Huang { 28354093d1a2SGuangbin Huang struct hnae3_knic_private_info *kinfo = &handle->kinfo; 28364093d1a2SGuangbin Huang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 28374093d1a2SGuangbin Huang u16 max_rss_size; 28384093d1a2SGuangbin Huang 28394093d1a2SGuangbin Huang kinfo->req_rss_size = new_tqps_num; 28404093d1a2SGuangbin Huang 28414093d1a2SGuangbin Huang max_rss_size = min_t(u16, hdev->rss_size_max, 28424093d1a2SGuangbin Huang hdev->num_tqps / kinfo->num_tc); 28434093d1a2SGuangbin Huang 28444093d1a2SGuangbin Huang /* Use the user's configuration when it is not larger than 28454093d1a2SGuangbin Huang * max_rss_size, otherwise, use the maximum specification value. 28464093d1a2SGuangbin Huang */ 28474093d1a2SGuangbin Huang if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 28484093d1a2SGuangbin Huang kinfo->req_rss_size <= max_rss_size) 28494093d1a2SGuangbin Huang kinfo->rss_size = kinfo->req_rss_size; 28504093d1a2SGuangbin Huang else if (kinfo->rss_size > max_rss_size || 28514093d1a2SGuangbin Huang (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) 28524093d1a2SGuangbin Huang kinfo->rss_size = max_rss_size; 28534093d1a2SGuangbin Huang 28544093d1a2SGuangbin Huang kinfo->num_tqps = kinfo->num_tc * kinfo->rss_size; 28554093d1a2SGuangbin Huang } 28564093d1a2SGuangbin Huang 28574093d1a2SGuangbin Huang static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 28584093d1a2SGuangbin Huang bool rxfh_configured) 28594093d1a2SGuangbin Huang { 28604093d1a2SGuangbin Huang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 28614093d1a2SGuangbin Huang struct hnae3_knic_private_info *kinfo = &handle->kinfo; 28624093d1a2SGuangbin Huang u16 cur_rss_size = kinfo->rss_size; 28634093d1a2SGuangbin Huang u16 cur_tqps = kinfo->num_tqps; 28644093d1a2SGuangbin Huang u32 *rss_indir; 28654093d1a2SGuangbin Huang unsigned int i; 28664093d1a2SGuangbin Huang int ret; 28674093d1a2SGuangbin Huang 28684093d1a2SGuangbin Huang hclgevf_update_rss_size(handle, new_tqps_num); 28694093d1a2SGuangbin Huang 28704093d1a2SGuangbin Huang ret = hclgevf_set_rss_tc_mode(hdev, kinfo->rss_size); 28714093d1a2SGuangbin Huang if (ret) 28724093d1a2SGuangbin Huang return ret; 28734093d1a2SGuangbin Huang 28744093d1a2SGuangbin Huang /* RSS indirection table has been configuared by user */ 28754093d1a2SGuangbin Huang if (rxfh_configured) 28764093d1a2SGuangbin Huang goto out; 28774093d1a2SGuangbin Huang 28784093d1a2SGuangbin Huang /* Reinitializes the rss indirect table according to the new RSS size */ 28794093d1a2SGuangbin Huang rss_indir = kcalloc(HCLGEVF_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL); 28804093d1a2SGuangbin Huang if (!rss_indir) 28814093d1a2SGuangbin Huang return -ENOMEM; 28824093d1a2SGuangbin Huang 28834093d1a2SGuangbin Huang for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 28844093d1a2SGuangbin Huang rss_indir[i] = i % kinfo->rss_size; 28854093d1a2SGuangbin Huang 28864093d1a2SGuangbin Huang ret = hclgevf_set_rss(handle, rss_indir, NULL, 0); 28874093d1a2SGuangbin Huang if (ret) 28884093d1a2SGuangbin Huang dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 28894093d1a2SGuangbin Huang ret); 28904093d1a2SGuangbin Huang 28914093d1a2SGuangbin Huang kfree(rss_indir); 28924093d1a2SGuangbin Huang 28934093d1a2SGuangbin Huang out: 28944093d1a2SGuangbin Huang if (!ret) 28954093d1a2SGuangbin Huang dev_info(&hdev->pdev->dev, 28964093d1a2SGuangbin Huang "Channels changed, rss_size from %u to %u, tqps from %u to %u", 28974093d1a2SGuangbin Huang cur_rss_size, kinfo->rss_size, 28984093d1a2SGuangbin Huang cur_tqps, kinfo->rss_size * kinfo->num_tc); 28994093d1a2SGuangbin Huang 29004093d1a2SGuangbin Huang return ret; 29014093d1a2SGuangbin Huang } 29024093d1a2SGuangbin Huang 2903175ec96bSFuyun Liang static int hclgevf_get_status(struct hnae3_handle *handle) 2904175ec96bSFuyun Liang { 2905175ec96bSFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2906175ec96bSFuyun Liang 2907175ec96bSFuyun Liang return hdev->hw.mac.link; 2908175ec96bSFuyun Liang } 2909175ec96bSFuyun Liang 29104a152de9SFuyun Liang static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 29114a152de9SFuyun Liang u8 *auto_neg, u32 *speed, 29124a152de9SFuyun Liang u8 *duplex) 29134a152de9SFuyun Liang { 29144a152de9SFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 29154a152de9SFuyun Liang 29164a152de9SFuyun Liang if (speed) 29174a152de9SFuyun Liang *speed = hdev->hw.mac.speed; 29184a152de9SFuyun Liang if (duplex) 29194a152de9SFuyun Liang *duplex = hdev->hw.mac.duplex; 29204a152de9SFuyun Liang if (auto_neg) 29214a152de9SFuyun Liang *auto_neg = AUTONEG_DISABLE; 29224a152de9SFuyun Liang } 29234a152de9SFuyun Liang 29244a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 29254a152de9SFuyun Liang u8 duplex) 29264a152de9SFuyun Liang { 29274a152de9SFuyun Liang hdev->hw.mac.speed = speed; 29284a152de9SFuyun Liang hdev->hw.mac.duplex = duplex; 29294a152de9SFuyun Liang } 29304a152de9SFuyun Liang 29311731be4cSYonglong Liu static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 29325c9f6b39SPeng Li { 29335c9f6b39SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 29345c9f6b39SPeng Li 29355c9f6b39SPeng Li return hclgevf_config_gro(hdev, enable); 29365c9f6b39SPeng Li } 29375c9f6b39SPeng Li 293888d10bd6SJian Shen static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 293988d10bd6SJian Shen u8 *module_type) 2940c136b884SPeng Li { 2941c136b884SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 294288d10bd6SJian Shen 2943c136b884SPeng Li if (media_type) 2944c136b884SPeng Li *media_type = hdev->hw.mac.media_type; 294588d10bd6SJian Shen 294688d10bd6SJian Shen if (module_type) 294788d10bd6SJian Shen *module_type = hdev->hw.mac.module_type; 2948c136b884SPeng Li } 2949c136b884SPeng Li 29504d60291bSHuazhong Tan static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 29514d60291bSHuazhong Tan { 29524d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 29534d60291bSHuazhong Tan 2954aa5c4f17SHuazhong Tan return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 29554d60291bSHuazhong Tan } 29564d60291bSHuazhong Tan 29574d60291bSHuazhong Tan static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 29584d60291bSHuazhong Tan { 29594d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 29604d60291bSHuazhong Tan 29614d60291bSHuazhong Tan return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 29624d60291bSHuazhong Tan } 29634d60291bSHuazhong Tan 29644d60291bSHuazhong Tan static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 29654d60291bSHuazhong Tan { 29664d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 29674d60291bSHuazhong Tan 2968c88a6e7dSHuazhong Tan return hdev->rst_stats.hw_rst_done_cnt; 29694d60291bSHuazhong Tan } 29704d60291bSHuazhong Tan 29719194d18bSliuzhongzhu static void hclgevf_get_link_mode(struct hnae3_handle *handle, 29729194d18bSliuzhongzhu unsigned long *supported, 29739194d18bSliuzhongzhu unsigned long *advertising) 29749194d18bSliuzhongzhu { 29759194d18bSliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 29769194d18bSliuzhongzhu 29779194d18bSliuzhongzhu *supported = hdev->hw.mac.supported; 29789194d18bSliuzhongzhu *advertising = hdev->hw.mac.advertising; 29799194d18bSliuzhongzhu } 29809194d18bSliuzhongzhu 29811600c3e5SJian Shen #define MAX_SEPARATE_NUM 4 29821600c3e5SJian Shen #define SEPARATOR_VALUE 0xFFFFFFFF 29831600c3e5SJian Shen #define REG_NUM_PER_LINE 4 29841600c3e5SJian Shen #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 29851600c3e5SJian Shen 29861600c3e5SJian Shen static int hclgevf_get_regs_len(struct hnae3_handle *handle) 29871600c3e5SJian Shen { 29881600c3e5SJian Shen int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 29891600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 29901600c3e5SJian Shen 29911600c3e5SJian Shen cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 29921600c3e5SJian Shen common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 29931600c3e5SJian Shen ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 29941600c3e5SJian Shen tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 29951600c3e5SJian Shen 29961600c3e5SJian Shen return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 29971600c3e5SJian Shen tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 29981600c3e5SJian Shen } 29991600c3e5SJian Shen 30001600c3e5SJian Shen static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 30011600c3e5SJian Shen void *data) 30021600c3e5SJian Shen { 30031600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 30041600c3e5SJian Shen int i, j, reg_um, separator_num; 30051600c3e5SJian Shen u32 *reg = data; 30061600c3e5SJian Shen 30071600c3e5SJian Shen *version = hdev->fw_version; 30081600c3e5SJian Shen 30091600c3e5SJian Shen /* fetching per-VF registers values from VF PCIe register space */ 30101600c3e5SJian Shen reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 30111600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 30121600c3e5SJian Shen for (i = 0; i < reg_um; i++) 30131600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 30141600c3e5SJian Shen for (i = 0; i < separator_num; i++) 30151600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 30161600c3e5SJian Shen 30171600c3e5SJian Shen reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 30181600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 30191600c3e5SJian Shen for (i = 0; i < reg_um; i++) 30201600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 30211600c3e5SJian Shen for (i = 0; i < separator_num; i++) 30221600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 30231600c3e5SJian Shen 30241600c3e5SJian Shen reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 30251600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 30261600c3e5SJian Shen for (j = 0; j < hdev->num_tqps; j++) { 30271600c3e5SJian Shen for (i = 0; i < reg_um; i++) 30281600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 30291600c3e5SJian Shen ring_reg_addr_list[i] + 30301600c3e5SJian Shen 0x200 * j); 30311600c3e5SJian Shen for (i = 0; i < separator_num; i++) 30321600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 30331600c3e5SJian Shen } 30341600c3e5SJian Shen 30351600c3e5SJian Shen reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 30361600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 30371600c3e5SJian Shen for (j = 0; j < hdev->num_msi_used - 1; j++) { 30381600c3e5SJian Shen for (i = 0; i < reg_um; i++) 30391600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 30401600c3e5SJian Shen tqp_intr_reg_addr_list[i] + 30411600c3e5SJian Shen 4 * j); 30421600c3e5SJian Shen for (i = 0; i < separator_num; i++) 30431600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 30441600c3e5SJian Shen } 30451600c3e5SJian Shen } 30461600c3e5SJian Shen 304792f11ea1SJian Shen void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 304892f11ea1SJian Shen u8 *port_base_vlan_info, u8 data_size) 304992f11ea1SJian Shen { 305092f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 305192f11ea1SJian Shen 305292f11ea1SJian Shen rtnl_lock(); 305392f11ea1SJian Shen hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 305492f11ea1SJian Shen rtnl_unlock(); 305592f11ea1SJian Shen 305692f11ea1SJian Shen /* send msg to PF and wait update port based vlan info */ 305792f11ea1SJian Shen hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 305892f11ea1SJian Shen HCLGE_MBX_PORT_BASE_VLAN_CFG, 305992f11ea1SJian Shen port_base_vlan_info, data_size, 306092f11ea1SJian Shen false, NULL, 0); 306192f11ea1SJian Shen 306292f11ea1SJian Shen if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 306392f11ea1SJian Shen nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 306492f11ea1SJian Shen else 306592f11ea1SJian Shen nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 306692f11ea1SJian Shen 306792f11ea1SJian Shen rtnl_lock(); 306892f11ea1SJian Shen hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 306992f11ea1SJian Shen rtnl_unlock(); 307092f11ea1SJian Shen } 307192f11ea1SJian Shen 3072e2cb1decSSalil Mehta static const struct hnae3_ae_ops hclgevf_ops = { 3073e2cb1decSSalil Mehta .init_ae_dev = hclgevf_init_ae_dev, 3074e2cb1decSSalil Mehta .uninit_ae_dev = hclgevf_uninit_ae_dev, 30756ff3cf07SHuazhong Tan .flr_prepare = hclgevf_flr_prepare, 30766ff3cf07SHuazhong Tan .flr_done = hclgevf_flr_done, 3077e718a93fSPeng Li .init_client_instance = hclgevf_init_client_instance, 3078e718a93fSPeng Li .uninit_client_instance = hclgevf_uninit_client_instance, 3079e2cb1decSSalil Mehta .start = hclgevf_ae_start, 3080e2cb1decSSalil Mehta .stop = hclgevf_ae_stop, 3081a6d818e3SYunsheng Lin .client_start = hclgevf_client_start, 3082a6d818e3SYunsheng Lin .client_stop = hclgevf_client_stop, 3083e2cb1decSSalil Mehta .map_ring_to_vector = hclgevf_map_ring_to_vector, 3084e2cb1decSSalil Mehta .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 3085e2cb1decSSalil Mehta .get_vector = hclgevf_get_vector, 30860d3e6631SYunsheng Lin .put_vector = hclgevf_put_vector, 3087e2cb1decSSalil Mehta .reset_queue = hclgevf_reset_tqp, 3088e2cb1decSSalil Mehta .get_mac_addr = hclgevf_get_mac_addr, 3089e2cb1decSSalil Mehta .set_mac_addr = hclgevf_set_mac_addr, 3090e2cb1decSSalil Mehta .add_uc_addr = hclgevf_add_uc_addr, 3091e2cb1decSSalil Mehta .rm_uc_addr = hclgevf_rm_uc_addr, 3092e2cb1decSSalil Mehta .add_mc_addr = hclgevf_add_mc_addr, 3093e2cb1decSSalil Mehta .rm_mc_addr = hclgevf_rm_mc_addr, 3094e2cb1decSSalil Mehta .get_stats = hclgevf_get_stats, 3095e2cb1decSSalil Mehta .update_stats = hclgevf_update_stats, 3096e2cb1decSSalil Mehta .get_strings = hclgevf_get_strings, 3097e2cb1decSSalil Mehta .get_sset_count = hclgevf_get_sset_count, 3098e2cb1decSSalil Mehta .get_rss_key_size = hclgevf_get_rss_key_size, 3099e2cb1decSSalil Mehta .get_rss_indir_size = hclgevf_get_rss_indir_size, 3100e2cb1decSSalil Mehta .get_rss = hclgevf_get_rss, 3101e2cb1decSSalil Mehta .set_rss = hclgevf_set_rss, 3102d97b3072SJian Shen .get_rss_tuple = hclgevf_get_rss_tuple, 3103d97b3072SJian Shen .set_rss_tuple = hclgevf_set_rss_tuple, 3104e2cb1decSSalil Mehta .get_tc_size = hclgevf_get_tc_size, 3105e2cb1decSSalil Mehta .get_fw_version = hclgevf_get_fw_version, 3106e2cb1decSSalil Mehta .set_vlan_filter = hclgevf_set_vlan_filter, 3107b2641e2aSYunsheng Lin .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 31086d4c3981SSalil Mehta .reset_event = hclgevf_reset_event, 3109720bd583SHuazhong Tan .set_default_reset_request = hclgevf_set_def_reset_request, 31104093d1a2SGuangbin Huang .set_channels = hclgevf_set_channels, 3111849e4607SPeng Li .get_channels = hclgevf_get_channels, 3112cc719218SPeng Li .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 31131600c3e5SJian Shen .get_regs_len = hclgevf_get_regs_len, 31141600c3e5SJian Shen .get_regs = hclgevf_get_regs, 3115175ec96bSFuyun Liang .get_status = hclgevf_get_status, 31164a152de9SFuyun Liang .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3117c136b884SPeng Li .get_media_type = hclgevf_get_media_type, 31184d60291bSHuazhong Tan .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 31194d60291bSHuazhong Tan .ae_dev_resetting = hclgevf_ae_dev_resetting, 31204d60291bSHuazhong Tan .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 31215c9f6b39SPeng Li .set_gro_en = hclgevf_gro_en, 3122818f1675SYunsheng Lin .set_mtu = hclgevf_set_mtu, 31230c29d191Sliuzhongzhu .get_global_queue_id = hclgevf_get_qid_global, 31248cdb992fSJian Shen .set_timer_task = hclgevf_set_timer_task, 31259194d18bSliuzhongzhu .get_link_mode = hclgevf_get_link_mode, 3126e196ec75SJian Shen .set_promisc_mode = hclgevf_set_promisc_mode, 3127e2cb1decSSalil Mehta }; 3128e2cb1decSSalil Mehta 3129e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf = { 3130e2cb1decSSalil Mehta .ops = &hclgevf_ops, 3131e2cb1decSSalil Mehta .pdev_id_table = ae_algovf_pci_tbl, 3132e2cb1decSSalil Mehta }; 3133e2cb1decSSalil Mehta 3134e2cb1decSSalil Mehta static int hclgevf_init(void) 3135e2cb1decSSalil Mehta { 3136e2cb1decSSalil Mehta pr_info("%s is initializing\n", HCLGEVF_NAME); 3137e2cb1decSSalil Mehta 3138854cf33aSFuyun Liang hnae3_register_ae_algo(&ae_algovf); 3139854cf33aSFuyun Liang 3140854cf33aSFuyun Liang return 0; 3141e2cb1decSSalil Mehta } 3142e2cb1decSSalil Mehta 3143e2cb1decSSalil Mehta static void hclgevf_exit(void) 3144e2cb1decSSalil Mehta { 3145e2cb1decSSalil Mehta hnae3_unregister_ae_algo(&ae_algovf); 3146e2cb1decSSalil Mehta } 3147e2cb1decSSalil Mehta module_init(hclgevf_init); 3148e2cb1decSSalil Mehta module_exit(hclgevf_exit); 3149e2cb1decSSalil Mehta 3150e2cb1decSSalil Mehta MODULE_LICENSE("GPL"); 3151e2cb1decSSalil Mehta MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3152e2cb1decSSalil Mehta MODULE_DESCRIPTION("HCLGEVF Driver"); 3153e2cb1decSSalil Mehta MODULE_VERSION(HCLGEVF_MOD_VERSION); 3154