1e2cb1decSSalil Mehta // SPDX-License-Identifier: GPL-2.0+ 2e2cb1decSSalil Mehta // Copyright (c) 2016-2017 Hisilicon Limited. 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #include <linux/etherdevice.h> 5aa5c4f17SHuazhong Tan #include <linux/iopoll.h> 66988eb2aSSalil Mehta #include <net/rtnetlink.h> 7e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 8e2cb1decSSalil Mehta #include "hclgevf_main.h" 9e2cb1decSSalil Mehta #include "hclge_mbx.h" 10e2cb1decSSalil Mehta #include "hnae3.h" 11e2cb1decSSalil Mehta 12e2cb1decSSalil Mehta #define HCLGEVF_NAME "hclgevf" 13e2cb1decSSalil Mehta 14bbe6540eSHuazhong Tan #define HCLGEVF_RESET_MAX_FAIL_CNT 5 15bbe6540eSHuazhong Tan 169c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 17e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf; 18e2cb1decSSalil Mehta 190ea68902SYunsheng Lin static struct workqueue_struct *hclgevf_wq; 200ea68902SYunsheng Lin 21e2cb1decSSalil Mehta static const struct pci_device_id ae_algovf_pci_tbl[] = { 22e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 23e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 24e2cb1decSSalil Mehta /* required last entry */ 25e2cb1decSSalil Mehta {0, } 26e2cb1decSSalil Mehta }; 27e2cb1decSSalil Mehta 28472d7eceSJian Shen static const u8 hclgevf_hash_key[] = { 29472d7eceSJian Shen 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 30472d7eceSJian Shen 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 31472d7eceSJian Shen 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 32472d7eceSJian Shen 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 33472d7eceSJian Shen 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 34472d7eceSJian Shen }; 35472d7eceSJian Shen 362f550a46SYunsheng Lin MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 372f550a46SYunsheng Lin 381600c3e5SJian Shen static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 391600c3e5SJian Shen HCLGEVF_CMDQ_TX_ADDR_H_REG, 401600c3e5SJian Shen HCLGEVF_CMDQ_TX_DEPTH_REG, 411600c3e5SJian Shen HCLGEVF_CMDQ_TX_TAIL_REG, 421600c3e5SJian Shen HCLGEVF_CMDQ_TX_HEAD_REG, 431600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_L_REG, 441600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_H_REG, 451600c3e5SJian Shen HCLGEVF_CMDQ_RX_DEPTH_REG, 461600c3e5SJian Shen HCLGEVF_CMDQ_RX_TAIL_REG, 471600c3e5SJian Shen HCLGEVF_CMDQ_RX_HEAD_REG, 481600c3e5SJian Shen HCLGEVF_VECTOR0_CMDQ_SRC_REG, 491600c3e5SJian Shen HCLGEVF_CMDQ_INTR_STS_REG, 501600c3e5SJian Shen HCLGEVF_CMDQ_INTR_EN_REG, 511600c3e5SJian Shen HCLGEVF_CMDQ_INTR_GEN_REG}; 521600c3e5SJian Shen 531600c3e5SJian Shen static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 541600c3e5SJian Shen HCLGEVF_RST_ING, 551600c3e5SJian Shen HCLGEVF_GRO_EN_REG}; 561600c3e5SJian Shen 571600c3e5SJian Shen static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 581600c3e5SJian Shen HCLGEVF_RING_RX_ADDR_H_REG, 591600c3e5SJian Shen HCLGEVF_RING_RX_BD_NUM_REG, 601600c3e5SJian Shen HCLGEVF_RING_RX_BD_LENGTH_REG, 611600c3e5SJian Shen HCLGEVF_RING_RX_MERGE_EN_REG, 621600c3e5SJian Shen HCLGEVF_RING_RX_TAIL_REG, 631600c3e5SJian Shen HCLGEVF_RING_RX_HEAD_REG, 641600c3e5SJian Shen HCLGEVF_RING_RX_FBD_NUM_REG, 651600c3e5SJian Shen HCLGEVF_RING_RX_OFFSET_REG, 661600c3e5SJian Shen HCLGEVF_RING_RX_FBD_OFFSET_REG, 671600c3e5SJian Shen HCLGEVF_RING_RX_STASH_REG, 681600c3e5SJian Shen HCLGEVF_RING_RX_BD_ERR_REG, 691600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_L_REG, 701600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_H_REG, 711600c3e5SJian Shen HCLGEVF_RING_TX_BD_NUM_REG, 721600c3e5SJian Shen HCLGEVF_RING_TX_PRIORITY_REG, 731600c3e5SJian Shen HCLGEVF_RING_TX_TC_REG, 741600c3e5SJian Shen HCLGEVF_RING_TX_MERGE_EN_REG, 751600c3e5SJian Shen HCLGEVF_RING_TX_TAIL_REG, 761600c3e5SJian Shen HCLGEVF_RING_TX_HEAD_REG, 771600c3e5SJian Shen HCLGEVF_RING_TX_FBD_NUM_REG, 781600c3e5SJian Shen HCLGEVF_RING_TX_OFFSET_REG, 791600c3e5SJian Shen HCLGEVF_RING_TX_EBD_NUM_REG, 801600c3e5SJian Shen HCLGEVF_RING_TX_EBD_OFFSET_REG, 811600c3e5SJian Shen HCLGEVF_RING_TX_BD_ERR_REG, 821600c3e5SJian Shen HCLGEVF_RING_EN_REG}; 831600c3e5SJian Shen 841600c3e5SJian Shen static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 851600c3e5SJian Shen HCLGEVF_TQP_INTR_GL0_REG, 861600c3e5SJian Shen HCLGEVF_TQP_INTR_GL1_REG, 871600c3e5SJian Shen HCLGEVF_TQP_INTR_GL2_REG, 881600c3e5SJian Shen HCLGEVF_TQP_INTR_RL_REG}; 891600c3e5SJian Shen 909b2f3477SWeihang Li static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 91e2cb1decSSalil Mehta { 92eed9535fSPeng Li if (!handle->client) 93eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, nic); 94eed9535fSPeng Li else if (handle->client->type == HNAE3_CLIENT_ROCE) 95eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, roce); 96eed9535fSPeng Li else 97e2cb1decSSalil Mehta return container_of(handle, struct hclgevf_dev, nic); 98e2cb1decSSalil Mehta } 99e2cb1decSSalil Mehta 100e2cb1decSSalil Mehta static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 101e2cb1decSSalil Mehta { 102b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 103e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 104e2cb1decSSalil Mehta struct hclgevf_desc desc; 105e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 106e2cb1decSSalil Mehta int status; 107e2cb1decSSalil Mehta int i; 108e2cb1decSSalil Mehta 109b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 110b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 111e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 112e2cb1decSSalil Mehta HCLGEVF_OPC_QUERY_RX_STATUS, 113e2cb1decSSalil Mehta true); 114e2cb1decSSalil Mehta 115e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 116e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 117e2cb1decSSalil Mehta if (status) { 118e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 119e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 120e2cb1decSSalil Mehta status, i); 121e2cb1decSSalil Mehta return status; 122e2cb1decSSalil Mehta } 123e2cb1decSSalil Mehta tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 124cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 125e2cb1decSSalil Mehta 126e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 127e2cb1decSSalil Mehta true); 128e2cb1decSSalil Mehta 129e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 130e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 131e2cb1decSSalil Mehta if (status) { 132e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 133e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 134e2cb1decSSalil Mehta status, i); 135e2cb1decSSalil Mehta return status; 136e2cb1decSSalil Mehta } 137e2cb1decSSalil Mehta tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 138cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 139e2cb1decSSalil Mehta } 140e2cb1decSSalil Mehta 141e2cb1decSSalil Mehta return 0; 142e2cb1decSSalil Mehta } 143e2cb1decSSalil Mehta 144e2cb1decSSalil Mehta static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 145e2cb1decSSalil Mehta { 146e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo = &handle->kinfo; 147e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 148e2cb1decSSalil Mehta u64 *buff = data; 149e2cb1decSSalil Mehta int i; 150e2cb1decSSalil Mehta 151b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 152b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 153e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 154e2cb1decSSalil Mehta } 155e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 156b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 157e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 158e2cb1decSSalil Mehta } 159e2cb1decSSalil Mehta 160e2cb1decSSalil Mehta return buff; 161e2cb1decSSalil Mehta } 162e2cb1decSSalil Mehta 163e2cb1decSSalil Mehta static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 164e2cb1decSSalil Mehta { 165b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 166e2cb1decSSalil Mehta 167b4f1d303SJian Shen return kinfo->num_tqps * 2; 168e2cb1decSSalil Mehta } 169e2cb1decSSalil Mehta 170e2cb1decSSalil Mehta static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 171e2cb1decSSalil Mehta { 172b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 173e2cb1decSSalil Mehta u8 *buff = data; 174e2cb1decSSalil Mehta int i = 0; 175e2cb1decSSalil Mehta 176b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 177b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 178e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1790c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 180e2cb1decSSalil Mehta tqp->index); 181e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 182e2cb1decSSalil Mehta } 183e2cb1decSSalil Mehta 184b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 185b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 186e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1870c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 188e2cb1decSSalil Mehta tqp->index); 189e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 190e2cb1decSSalil Mehta } 191e2cb1decSSalil Mehta 192e2cb1decSSalil Mehta return buff; 193e2cb1decSSalil Mehta } 194e2cb1decSSalil Mehta 195e2cb1decSSalil Mehta static void hclgevf_update_stats(struct hnae3_handle *handle, 196e2cb1decSSalil Mehta struct net_device_stats *net_stats) 197e2cb1decSSalil Mehta { 198e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 199e2cb1decSSalil Mehta int status; 200e2cb1decSSalil Mehta 201e2cb1decSSalil Mehta status = hclgevf_tqps_update_stats(handle); 202e2cb1decSSalil Mehta if (status) 203e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 204e2cb1decSSalil Mehta "VF update of TQPS stats fail, status = %d.\n", 205e2cb1decSSalil Mehta status); 206e2cb1decSSalil Mehta } 207e2cb1decSSalil Mehta 208e2cb1decSSalil Mehta static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 209e2cb1decSSalil Mehta { 210e2cb1decSSalil Mehta if (strset == ETH_SS_TEST) 211e2cb1decSSalil Mehta return -EOPNOTSUPP; 212e2cb1decSSalil Mehta else if (strset == ETH_SS_STATS) 213e2cb1decSSalil Mehta return hclgevf_tqps_get_sset_count(handle, strset); 214e2cb1decSSalil Mehta 215e2cb1decSSalil Mehta return 0; 216e2cb1decSSalil Mehta } 217e2cb1decSSalil Mehta 218e2cb1decSSalil Mehta static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 219e2cb1decSSalil Mehta u8 *data) 220e2cb1decSSalil Mehta { 221e2cb1decSSalil Mehta u8 *p = (char *)data; 222e2cb1decSSalil Mehta 223e2cb1decSSalil Mehta if (strset == ETH_SS_STATS) 224e2cb1decSSalil Mehta p = hclgevf_tqps_get_strings(handle, p); 225e2cb1decSSalil Mehta } 226e2cb1decSSalil Mehta 227e2cb1decSSalil Mehta static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 228e2cb1decSSalil Mehta { 229e2cb1decSSalil Mehta hclgevf_tqps_get_stats(handle, data); 230e2cb1decSSalil Mehta } 231e2cb1decSSalil Mehta 232d3410018SYufeng Mo static void hclgevf_build_send_msg(struct hclge_vf_to_pf_msg *msg, u8 code, 233d3410018SYufeng Mo u8 subcode) 234d3410018SYufeng Mo { 235d3410018SYufeng Mo if (msg) { 236d3410018SYufeng Mo memset(msg, 0, sizeof(struct hclge_vf_to_pf_msg)); 237d3410018SYufeng Mo msg->code = code; 238d3410018SYufeng Mo msg->subcode = subcode; 239d3410018SYufeng Mo } 240d3410018SYufeng Mo } 241d3410018SYufeng Mo 242e2cb1decSSalil Mehta static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 243e2cb1decSSalil Mehta { 244d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 245e2cb1decSSalil Mehta u8 resp_msg; 246e2cb1decSSalil Mehta int status; 247e2cb1decSSalil Mehta 248d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_TCINFO, 0); 249d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg, 250d3410018SYufeng Mo sizeof(resp_msg)); 251e2cb1decSSalil Mehta if (status) { 252e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 253e2cb1decSSalil Mehta "VF request to get TC info from PF failed %d", 254e2cb1decSSalil Mehta status); 255e2cb1decSSalil Mehta return status; 256e2cb1decSSalil Mehta } 257e2cb1decSSalil Mehta 258e2cb1decSSalil Mehta hdev->hw_tc_map = resp_msg; 259e2cb1decSSalil Mehta 260e2cb1decSSalil Mehta return 0; 261e2cb1decSSalil Mehta } 262e2cb1decSSalil Mehta 26392f11ea1SJian Shen static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 26492f11ea1SJian Shen { 26592f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 266d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 26792f11ea1SJian Shen u8 resp_msg; 26892f11ea1SJian Shen int ret; 26992f11ea1SJian Shen 270d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 271d3410018SYufeng Mo HCLGE_MBX_GET_PORT_BASE_VLAN_STATE); 272d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg, 273d3410018SYufeng Mo sizeof(u8)); 27492f11ea1SJian Shen if (ret) { 27592f11ea1SJian Shen dev_err(&hdev->pdev->dev, 27692f11ea1SJian Shen "VF request to get port based vlan state failed %d", 27792f11ea1SJian Shen ret); 27892f11ea1SJian Shen return ret; 27992f11ea1SJian Shen } 28092f11ea1SJian Shen 28192f11ea1SJian Shen nic->port_base_vlan_state = resp_msg; 28292f11ea1SJian Shen 28392f11ea1SJian Shen return 0; 28492f11ea1SJian Shen } 28592f11ea1SJian Shen 2866cee6fc3SJian Shen static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 287e2cb1decSSalil Mehta { 288c0425944SPeng Li #define HCLGEVF_TQPS_RSS_INFO_LEN 6 289d3410018SYufeng Mo #define HCLGEVF_TQPS_ALLOC_OFFSET 0 290d3410018SYufeng Mo #define HCLGEVF_TQPS_RSS_SIZE_OFFSET 2 291d3410018SYufeng Mo #define HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET 4 292d3410018SYufeng Mo 293e2cb1decSSalil Mehta u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 294d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 295e2cb1decSSalil Mehta int status; 296e2cb1decSSalil Mehta 297d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QINFO, 0); 298d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 299e2cb1decSSalil Mehta HCLGEVF_TQPS_RSS_INFO_LEN); 300e2cb1decSSalil Mehta if (status) { 301e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 302e2cb1decSSalil Mehta "VF request to get tqp info from PF failed %d", 303e2cb1decSSalil Mehta status); 304e2cb1decSSalil Mehta return status; 305e2cb1decSSalil Mehta } 306e2cb1decSSalil Mehta 307d3410018SYufeng Mo memcpy(&hdev->num_tqps, &resp_msg[HCLGEVF_TQPS_ALLOC_OFFSET], 308d3410018SYufeng Mo sizeof(u16)); 309d3410018SYufeng Mo memcpy(&hdev->rss_size_max, &resp_msg[HCLGEVF_TQPS_RSS_SIZE_OFFSET], 310d3410018SYufeng Mo sizeof(u16)); 311d3410018SYufeng Mo memcpy(&hdev->rx_buf_len, &resp_msg[HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET], 312d3410018SYufeng Mo sizeof(u16)); 313c0425944SPeng Li 314c0425944SPeng Li return 0; 315c0425944SPeng Li } 316c0425944SPeng Li 317c0425944SPeng Li static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 318c0425944SPeng Li { 319c0425944SPeng Li #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 320d3410018SYufeng Mo #define HCLGEVF_TQPS_NUM_TX_DESC_OFFSET 0 321d3410018SYufeng Mo #define HCLGEVF_TQPS_NUM_RX_DESC_OFFSET 2 322d3410018SYufeng Mo 323c0425944SPeng Li u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 324d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 325c0425944SPeng Li int ret; 326c0425944SPeng Li 327d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QDEPTH, 0); 328d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 329c0425944SPeng Li HCLGEVF_TQPS_DEPTH_INFO_LEN); 330c0425944SPeng Li if (ret) { 331c0425944SPeng Li dev_err(&hdev->pdev->dev, 332c0425944SPeng Li "VF request to get tqp depth info from PF failed %d", 333c0425944SPeng Li ret); 334c0425944SPeng Li return ret; 335c0425944SPeng Li } 336c0425944SPeng Li 337d3410018SYufeng Mo memcpy(&hdev->num_tx_desc, &resp_msg[HCLGEVF_TQPS_NUM_TX_DESC_OFFSET], 338d3410018SYufeng Mo sizeof(u16)); 339d3410018SYufeng Mo memcpy(&hdev->num_rx_desc, &resp_msg[HCLGEVF_TQPS_NUM_RX_DESC_OFFSET], 340d3410018SYufeng Mo sizeof(u16)); 341e2cb1decSSalil Mehta 342e2cb1decSSalil Mehta return 0; 343e2cb1decSSalil Mehta } 344e2cb1decSSalil Mehta 3450c29d191Sliuzhongzhu static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 3460c29d191Sliuzhongzhu { 3470c29d191Sliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 348d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 3490c29d191Sliuzhongzhu u16 qid_in_pf = 0; 350d3410018SYufeng Mo u8 resp_data[2]; 3510c29d191Sliuzhongzhu int ret; 3520c29d191Sliuzhongzhu 353d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QID_IN_PF, 0); 354d3410018SYufeng Mo memcpy(send_msg.data, &queue_id, sizeof(queue_id)); 355d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_data, 35663cbf7a9SYufeng Mo sizeof(resp_data)); 3570c29d191Sliuzhongzhu if (!ret) 3580c29d191Sliuzhongzhu qid_in_pf = *(u16 *)resp_data; 3590c29d191Sliuzhongzhu 3600c29d191Sliuzhongzhu return qid_in_pf; 3610c29d191Sliuzhongzhu } 3620c29d191Sliuzhongzhu 3639c3e7130Sliuzhongzhu static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 3649c3e7130Sliuzhongzhu { 365d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 36688d10bd6SJian Shen u8 resp_msg[2]; 3679c3e7130Sliuzhongzhu int ret; 3689c3e7130Sliuzhongzhu 369d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MEDIA_TYPE, 0); 370d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 371d3410018SYufeng Mo sizeof(resp_msg)); 3729c3e7130Sliuzhongzhu if (ret) { 3739c3e7130Sliuzhongzhu dev_err(&hdev->pdev->dev, 3749c3e7130Sliuzhongzhu "VF request to get the pf port media type failed %d", 3759c3e7130Sliuzhongzhu ret); 3769c3e7130Sliuzhongzhu return ret; 3779c3e7130Sliuzhongzhu } 3789c3e7130Sliuzhongzhu 37988d10bd6SJian Shen hdev->hw.mac.media_type = resp_msg[0]; 38088d10bd6SJian Shen hdev->hw.mac.module_type = resp_msg[1]; 3819c3e7130Sliuzhongzhu 3829c3e7130Sliuzhongzhu return 0; 3839c3e7130Sliuzhongzhu } 3849c3e7130Sliuzhongzhu 385e2cb1decSSalil Mehta static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 386e2cb1decSSalil Mehta { 387e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 388e2cb1decSSalil Mehta int i; 389e2cb1decSSalil Mehta 390e2cb1decSSalil Mehta hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 391e2cb1decSSalil Mehta sizeof(struct hclgevf_tqp), GFP_KERNEL); 392e2cb1decSSalil Mehta if (!hdev->htqp) 393e2cb1decSSalil Mehta return -ENOMEM; 394e2cb1decSSalil Mehta 395e2cb1decSSalil Mehta tqp = hdev->htqp; 396e2cb1decSSalil Mehta 397e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 398e2cb1decSSalil Mehta tqp->dev = &hdev->pdev->dev; 399e2cb1decSSalil Mehta tqp->index = i; 400e2cb1decSSalil Mehta 401e2cb1decSSalil Mehta tqp->q.ae_algo = &ae_algovf; 402e2cb1decSSalil Mehta tqp->q.buf_size = hdev->rx_buf_len; 403c0425944SPeng Li tqp->q.tx_desc_num = hdev->num_tx_desc; 404c0425944SPeng Li tqp->q.rx_desc_num = hdev->num_rx_desc; 405e2cb1decSSalil Mehta tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 406e2cb1decSSalil Mehta i * HCLGEVF_TQP_REG_SIZE; 407e2cb1decSSalil Mehta 408e2cb1decSSalil Mehta tqp++; 409e2cb1decSSalil Mehta } 410e2cb1decSSalil Mehta 411e2cb1decSSalil Mehta return 0; 412e2cb1decSSalil Mehta } 413e2cb1decSSalil Mehta 414e2cb1decSSalil Mehta static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 415e2cb1decSSalil Mehta { 416e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 417e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo; 418e2cb1decSSalil Mehta u16 new_tqps = hdev->num_tqps; 419ebaf1908SWeihang Li unsigned int i; 420e2cb1decSSalil Mehta 421e2cb1decSSalil Mehta kinfo = &nic->kinfo; 422e2cb1decSSalil Mehta kinfo->num_tc = 0; 423c0425944SPeng Li kinfo->num_tx_desc = hdev->num_tx_desc; 424c0425944SPeng Li kinfo->num_rx_desc = hdev->num_rx_desc; 425e2cb1decSSalil Mehta kinfo->rx_buf_len = hdev->rx_buf_len; 426e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 427e2cb1decSSalil Mehta if (hdev->hw_tc_map & BIT(i)) 428e2cb1decSSalil Mehta kinfo->num_tc++; 429e2cb1decSSalil Mehta 430e2cb1decSSalil Mehta kinfo->rss_size 431e2cb1decSSalil Mehta = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 432e2cb1decSSalil Mehta new_tqps = kinfo->rss_size * kinfo->num_tc; 433e2cb1decSSalil Mehta kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 434e2cb1decSSalil Mehta 435e2cb1decSSalil Mehta kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 436e2cb1decSSalil Mehta sizeof(struct hnae3_queue *), GFP_KERNEL); 437e2cb1decSSalil Mehta if (!kinfo->tqp) 438e2cb1decSSalil Mehta return -ENOMEM; 439e2cb1decSSalil Mehta 440e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 441e2cb1decSSalil Mehta hdev->htqp[i].q.handle = &hdev->nic; 442e2cb1decSSalil Mehta hdev->htqp[i].q.tqp_index = i; 443e2cb1decSSalil Mehta kinfo->tqp[i] = &hdev->htqp[i].q; 444e2cb1decSSalil Mehta } 445e2cb1decSSalil Mehta 446580a05f9SYonglong Liu /* after init the max rss_size and tqps, adjust the default tqp numbers 447580a05f9SYonglong Liu * and rss size with the actual vector numbers 448580a05f9SYonglong Liu */ 449580a05f9SYonglong Liu kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps); 450580a05f9SYonglong Liu kinfo->rss_size = min_t(u16, kinfo->num_tqps / kinfo->num_tc, 451580a05f9SYonglong Liu kinfo->rss_size); 452580a05f9SYonglong Liu 453e2cb1decSSalil Mehta return 0; 454e2cb1decSSalil Mehta } 455e2cb1decSSalil Mehta 456e2cb1decSSalil Mehta static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 457e2cb1decSSalil Mehta { 458d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 459e2cb1decSSalil Mehta int status; 460e2cb1decSSalil Mehta 461d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_STATUS, 0); 462d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 463e2cb1decSSalil Mehta if (status) 464e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 465e2cb1decSSalil Mehta "VF failed to fetch link status(%d) from PF", status); 466e2cb1decSSalil Mehta } 467e2cb1decSSalil Mehta 468e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 469e2cb1decSSalil Mehta { 47045e92b7eSPeng Li struct hnae3_handle *rhandle = &hdev->roce; 471e2cb1decSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 47245e92b7eSPeng Li struct hnae3_client *rclient; 473e2cb1decSSalil Mehta struct hnae3_client *client; 474e2cb1decSSalil Mehta 475ff200099SYunsheng Lin if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state)) 476ff200099SYunsheng Lin return; 477ff200099SYunsheng Lin 478e2cb1decSSalil Mehta client = handle->client; 47945e92b7eSPeng Li rclient = hdev->roce_client; 480e2cb1decSSalil Mehta 481582d37bbSPeng Li link_state = 482582d37bbSPeng Li test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 483582d37bbSPeng Li 484e2cb1decSSalil Mehta if (link_state != hdev->hw.mac.link) { 485e2cb1decSSalil Mehta client->ops->link_status_change(handle, !!link_state); 48645e92b7eSPeng Li if (rclient && rclient->ops->link_status_change) 48745e92b7eSPeng Li rclient->ops->link_status_change(rhandle, !!link_state); 488e2cb1decSSalil Mehta hdev->hw.mac.link = link_state; 489e2cb1decSSalil Mehta } 490ff200099SYunsheng Lin 491ff200099SYunsheng Lin clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state); 492e2cb1decSSalil Mehta } 493e2cb1decSSalil Mehta 494538abaf3SYueHaibing static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 4959194d18bSliuzhongzhu { 4969194d18bSliuzhongzhu #define HCLGEVF_ADVERTISING 0 4979194d18bSliuzhongzhu #define HCLGEVF_SUPPORTED 1 4989194d18bSliuzhongzhu 499d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 500d3410018SYufeng Mo 501d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_MODE, 0); 502d3410018SYufeng Mo send_msg.data[0] = HCLGEVF_ADVERTISING; 503d3410018SYufeng Mo hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 504d3410018SYufeng Mo send_msg.data[0] = HCLGEVF_SUPPORTED; 505d3410018SYufeng Mo hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 5069194d18bSliuzhongzhu } 5079194d18bSliuzhongzhu 508e2cb1decSSalil Mehta static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 509e2cb1decSSalil Mehta { 510e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 511e2cb1decSSalil Mehta int ret; 512e2cb1decSSalil Mehta 513e2cb1decSSalil Mehta nic->ae_algo = &ae_algovf; 514e2cb1decSSalil Mehta nic->pdev = hdev->pdev; 515e2cb1decSSalil Mehta nic->numa_node_mask = hdev->numa_node_mask; 516424eb834SSalil Mehta nic->flags |= HNAE3_SUPPORT_VF; 517e2cb1decSSalil Mehta 518e2cb1decSSalil Mehta ret = hclgevf_knic_setup(hdev); 519e2cb1decSSalil Mehta if (ret) 520e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 521e2cb1decSSalil Mehta ret); 522e2cb1decSSalil Mehta return ret; 523e2cb1decSSalil Mehta } 524e2cb1decSSalil Mehta 525e2cb1decSSalil Mehta static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 526e2cb1decSSalil Mehta { 52736cbbdf6SPeng Li if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 52836cbbdf6SPeng Li dev_warn(&hdev->pdev->dev, 52936cbbdf6SPeng Li "vector(vector_id %d) has been freed.\n", vector_id); 53036cbbdf6SPeng Li return; 53136cbbdf6SPeng Li } 53236cbbdf6SPeng Li 533e2cb1decSSalil Mehta hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 534e2cb1decSSalil Mehta hdev->num_msi_left += 1; 535e2cb1decSSalil Mehta hdev->num_msi_used -= 1; 536e2cb1decSSalil Mehta } 537e2cb1decSSalil Mehta 538e2cb1decSSalil Mehta static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 539e2cb1decSSalil Mehta struct hnae3_vector_info *vector_info) 540e2cb1decSSalil Mehta { 541e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 542e2cb1decSSalil Mehta struct hnae3_vector_info *vector = vector_info; 543e2cb1decSSalil Mehta int alloc = 0; 544e2cb1decSSalil Mehta int i, j; 545e2cb1decSSalil Mehta 546580a05f9SYonglong Liu vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num); 547e2cb1decSSalil Mehta vector_num = min(hdev->num_msi_left, vector_num); 548e2cb1decSSalil Mehta 549e2cb1decSSalil Mehta for (j = 0; j < vector_num; j++) { 550e2cb1decSSalil Mehta for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 551e2cb1decSSalil Mehta if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 552e2cb1decSSalil Mehta vector->vector = pci_irq_vector(hdev->pdev, i); 553e2cb1decSSalil Mehta vector->io_addr = hdev->hw.io_base + 554e2cb1decSSalil Mehta HCLGEVF_VECTOR_REG_BASE + 555e2cb1decSSalil Mehta (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 556e2cb1decSSalil Mehta hdev->vector_status[i] = 0; 557e2cb1decSSalil Mehta hdev->vector_irq[i] = vector->vector; 558e2cb1decSSalil Mehta 559e2cb1decSSalil Mehta vector++; 560e2cb1decSSalil Mehta alloc++; 561e2cb1decSSalil Mehta 562e2cb1decSSalil Mehta break; 563e2cb1decSSalil Mehta } 564e2cb1decSSalil Mehta } 565e2cb1decSSalil Mehta } 566e2cb1decSSalil Mehta hdev->num_msi_left -= alloc; 567e2cb1decSSalil Mehta hdev->num_msi_used += alloc; 568e2cb1decSSalil Mehta 569e2cb1decSSalil Mehta return alloc; 570e2cb1decSSalil Mehta } 571e2cb1decSSalil Mehta 572e2cb1decSSalil Mehta static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 573e2cb1decSSalil Mehta { 574e2cb1decSSalil Mehta int i; 575e2cb1decSSalil Mehta 576e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 577e2cb1decSSalil Mehta if (vector == hdev->vector_irq[i]) 578e2cb1decSSalil Mehta return i; 579e2cb1decSSalil Mehta 580e2cb1decSSalil Mehta return -EINVAL; 581e2cb1decSSalil Mehta } 582e2cb1decSSalil Mehta 583374ad291SJian Shen static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 584374ad291SJian Shen const u8 hfunc, const u8 *key) 585374ad291SJian Shen { 586374ad291SJian Shen struct hclgevf_rss_config_cmd *req; 587ebaf1908SWeihang Li unsigned int key_offset = 0; 588374ad291SJian Shen struct hclgevf_desc desc; 5893caf772bSYufeng Mo int key_counts; 590374ad291SJian Shen int key_size; 591374ad291SJian Shen int ret; 592374ad291SJian Shen 5933caf772bSYufeng Mo key_counts = HCLGEVF_RSS_KEY_SIZE; 594374ad291SJian Shen req = (struct hclgevf_rss_config_cmd *)desc.data; 595374ad291SJian Shen 5963caf772bSYufeng Mo while (key_counts) { 597374ad291SJian Shen hclgevf_cmd_setup_basic_desc(&desc, 598374ad291SJian Shen HCLGEVF_OPC_RSS_GENERIC_CONFIG, 599374ad291SJian Shen false); 600374ad291SJian Shen 601374ad291SJian Shen req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 602374ad291SJian Shen req->hash_config |= 603374ad291SJian Shen (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 604374ad291SJian Shen 6053caf772bSYufeng Mo key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts); 606374ad291SJian Shen memcpy(req->hash_key, 607374ad291SJian Shen key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 608374ad291SJian Shen 6093caf772bSYufeng Mo key_counts -= key_size; 6103caf772bSYufeng Mo key_offset++; 611374ad291SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 612374ad291SJian Shen if (ret) { 613374ad291SJian Shen dev_err(&hdev->pdev->dev, 614374ad291SJian Shen "Configure RSS config fail, status = %d\n", 615374ad291SJian Shen ret); 616374ad291SJian Shen return ret; 617374ad291SJian Shen } 618374ad291SJian Shen } 619374ad291SJian Shen 620374ad291SJian Shen return 0; 621374ad291SJian Shen } 622374ad291SJian Shen 623e2cb1decSSalil Mehta static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 624e2cb1decSSalil Mehta { 625e2cb1decSSalil Mehta return HCLGEVF_RSS_KEY_SIZE; 626e2cb1decSSalil Mehta } 627e2cb1decSSalil Mehta 628e2cb1decSSalil Mehta static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 629e2cb1decSSalil Mehta { 630e2cb1decSSalil Mehta return HCLGEVF_RSS_IND_TBL_SIZE; 631e2cb1decSSalil Mehta } 632e2cb1decSSalil Mehta 633e2cb1decSSalil Mehta static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 634e2cb1decSSalil Mehta { 635e2cb1decSSalil Mehta const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 636e2cb1decSSalil Mehta struct hclgevf_rss_indirection_table_cmd *req; 637e2cb1decSSalil Mehta struct hclgevf_desc desc; 638e2cb1decSSalil Mehta int status; 639e2cb1decSSalil Mehta int i, j; 640e2cb1decSSalil Mehta 641e2cb1decSSalil Mehta req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 642e2cb1decSSalil Mehta 643e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 644e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 645e2cb1decSSalil Mehta false); 646e2cb1decSSalil Mehta req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 647e2cb1decSSalil Mehta req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 648e2cb1decSSalil Mehta for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 649e2cb1decSSalil Mehta req->rss_result[j] = 650e2cb1decSSalil Mehta indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 651e2cb1decSSalil Mehta 652e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 653e2cb1decSSalil Mehta if (status) { 654e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 655e2cb1decSSalil Mehta "VF failed(=%d) to set RSS indirection table\n", 656e2cb1decSSalil Mehta status); 657e2cb1decSSalil Mehta return status; 658e2cb1decSSalil Mehta } 659e2cb1decSSalil Mehta } 660e2cb1decSSalil Mehta 661e2cb1decSSalil Mehta return 0; 662e2cb1decSSalil Mehta } 663e2cb1decSSalil Mehta 664e2cb1decSSalil Mehta static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 665e2cb1decSSalil Mehta { 666e2cb1decSSalil Mehta struct hclgevf_rss_tc_mode_cmd *req; 667e2cb1decSSalil Mehta u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 668e2cb1decSSalil Mehta u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 669e2cb1decSSalil Mehta u16 tc_size[HCLGEVF_MAX_TC_NUM]; 670e2cb1decSSalil Mehta struct hclgevf_desc desc; 671e2cb1decSSalil Mehta u16 roundup_size; 672e2cb1decSSalil Mehta int status; 673ebaf1908SWeihang Li unsigned int i; 674e2cb1decSSalil Mehta 675e2cb1decSSalil Mehta req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 676e2cb1decSSalil Mehta 677e2cb1decSSalil Mehta roundup_size = roundup_pow_of_two(rss_size); 678e2cb1decSSalil Mehta roundup_size = ilog2(roundup_size); 679e2cb1decSSalil Mehta 680e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 681e2cb1decSSalil Mehta tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 682e2cb1decSSalil Mehta tc_size[i] = roundup_size; 683e2cb1decSSalil Mehta tc_offset[i] = rss_size * i; 684e2cb1decSSalil Mehta } 685e2cb1decSSalil Mehta 686e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 687e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 688e4e87715SPeng Li hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 689e2cb1decSSalil Mehta (tc_valid[i] & 0x1)); 690e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 691e2cb1decSSalil Mehta HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 692e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 693e2cb1decSSalil Mehta HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 694e2cb1decSSalil Mehta } 695e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 696e2cb1decSSalil Mehta if (status) 697e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 698e2cb1decSSalil Mehta "VF failed(=%d) to set rss tc mode\n", status); 699e2cb1decSSalil Mehta 700e2cb1decSSalil Mehta return status; 701e2cb1decSSalil Mehta } 702e2cb1decSSalil Mehta 703a638b1d8SJian Shen /* for revision 0x20, vf shared the same rss config with pf */ 704a638b1d8SJian Shen static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 705a638b1d8SJian Shen { 706a638b1d8SJian Shen #define HCLGEVF_RSS_MBX_RESP_LEN 8 707a638b1d8SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 708a638b1d8SJian Shen u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 709d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 710a638b1d8SJian Shen u16 msg_num, hash_key_index; 711a638b1d8SJian Shen u8 index; 712a638b1d8SJian Shen int ret; 713a638b1d8SJian Shen 714d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_RSS_KEY, 0); 715a638b1d8SJian Shen msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 716a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN; 717a638b1d8SJian Shen for (index = 0; index < msg_num; index++) { 718d3410018SYufeng Mo send_msg.data[0] = index; 719d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 720a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN); 721a638b1d8SJian Shen if (ret) { 722a638b1d8SJian Shen dev_err(&hdev->pdev->dev, 723a638b1d8SJian Shen "VF get rss hash key from PF failed, ret=%d", 724a638b1d8SJian Shen ret); 725a638b1d8SJian Shen return ret; 726a638b1d8SJian Shen } 727a638b1d8SJian Shen 728a638b1d8SJian Shen hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 729a638b1d8SJian Shen if (index == msg_num - 1) 730a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 731a638b1d8SJian Shen &resp_msg[0], 732a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE - hash_key_index); 733a638b1d8SJian Shen else 734a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 735a638b1d8SJian Shen &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 736a638b1d8SJian Shen } 737a638b1d8SJian Shen 738a638b1d8SJian Shen return 0; 739a638b1d8SJian Shen } 740a638b1d8SJian Shen 741e2cb1decSSalil Mehta static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 742e2cb1decSSalil Mehta u8 *hfunc) 743e2cb1decSSalil Mehta { 744e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 745e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 746a638b1d8SJian Shen int i, ret; 747e2cb1decSSalil Mehta 748374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 749374ad291SJian Shen /* Get hash algorithm */ 750374ad291SJian Shen if (hfunc) { 751374ad291SJian Shen switch (rss_cfg->hash_algo) { 752374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 753374ad291SJian Shen *hfunc = ETH_RSS_HASH_TOP; 754374ad291SJian Shen break; 755374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 756374ad291SJian Shen *hfunc = ETH_RSS_HASH_XOR; 757374ad291SJian Shen break; 758374ad291SJian Shen default: 759374ad291SJian Shen *hfunc = ETH_RSS_HASH_UNKNOWN; 760374ad291SJian Shen break; 761374ad291SJian Shen } 762374ad291SJian Shen } 763374ad291SJian Shen 764374ad291SJian Shen /* Get the RSS Key required by the user */ 765374ad291SJian Shen if (key) 766374ad291SJian Shen memcpy(key, rss_cfg->rss_hash_key, 767374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 768a638b1d8SJian Shen } else { 769a638b1d8SJian Shen if (hfunc) 770a638b1d8SJian Shen *hfunc = ETH_RSS_HASH_TOP; 771a638b1d8SJian Shen if (key) { 772a638b1d8SJian Shen ret = hclgevf_get_rss_hash_key(hdev); 773a638b1d8SJian Shen if (ret) 774a638b1d8SJian Shen return ret; 775a638b1d8SJian Shen memcpy(key, rss_cfg->rss_hash_key, 776a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE); 777a638b1d8SJian Shen } 778374ad291SJian Shen } 779374ad291SJian Shen 780e2cb1decSSalil Mehta if (indir) 781e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 782e2cb1decSSalil Mehta indir[i] = rss_cfg->rss_indirection_tbl[i]; 783e2cb1decSSalil Mehta 784374ad291SJian Shen return 0; 785e2cb1decSSalil Mehta } 786e2cb1decSSalil Mehta 787e2cb1decSSalil Mehta static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 788e2cb1decSSalil Mehta const u8 *key, const u8 hfunc) 789e2cb1decSSalil Mehta { 790e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 791e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 792374ad291SJian Shen int ret, i; 793374ad291SJian Shen 794374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 795374ad291SJian Shen /* Set the RSS Hash Key if specififed by the user */ 796374ad291SJian Shen if (key) { 797374ad291SJian Shen switch (hfunc) { 798374ad291SJian Shen case ETH_RSS_HASH_TOP: 799374ad291SJian Shen rss_cfg->hash_algo = 800374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 801374ad291SJian Shen break; 802374ad291SJian Shen case ETH_RSS_HASH_XOR: 803374ad291SJian Shen rss_cfg->hash_algo = 804374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_SIMPLE; 805374ad291SJian Shen break; 806374ad291SJian Shen case ETH_RSS_HASH_NO_CHANGE: 807374ad291SJian Shen break; 808374ad291SJian Shen default: 809374ad291SJian Shen return -EINVAL; 810374ad291SJian Shen } 811374ad291SJian Shen 812374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 813374ad291SJian Shen key); 814374ad291SJian Shen if (ret) 815374ad291SJian Shen return ret; 816374ad291SJian Shen 817374ad291SJian Shen /* Update the shadow RSS key with user specified qids */ 818374ad291SJian Shen memcpy(rss_cfg->rss_hash_key, key, 819374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 820374ad291SJian Shen } 821374ad291SJian Shen } 822e2cb1decSSalil Mehta 823e2cb1decSSalil Mehta /* update the shadow RSS table with user specified qids */ 824e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 825e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = indir[i]; 826e2cb1decSSalil Mehta 827e2cb1decSSalil Mehta /* update the hardware */ 828e2cb1decSSalil Mehta return hclgevf_set_rss_indir_table(hdev); 829e2cb1decSSalil Mehta } 830e2cb1decSSalil Mehta 831d97b3072SJian Shen static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 832d97b3072SJian Shen { 833d97b3072SJian Shen u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 834d97b3072SJian Shen 835d97b3072SJian Shen if (nfc->data & RXH_L4_B_2_3) 836d97b3072SJian Shen hash_sets |= HCLGEVF_D_PORT_BIT; 837d97b3072SJian Shen else 838d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_PORT_BIT; 839d97b3072SJian Shen 840d97b3072SJian Shen if (nfc->data & RXH_IP_SRC) 841d97b3072SJian Shen hash_sets |= HCLGEVF_S_IP_BIT; 842d97b3072SJian Shen else 843d97b3072SJian Shen hash_sets &= ~HCLGEVF_S_IP_BIT; 844d97b3072SJian Shen 845d97b3072SJian Shen if (nfc->data & RXH_IP_DST) 846d97b3072SJian Shen hash_sets |= HCLGEVF_D_IP_BIT; 847d97b3072SJian Shen else 848d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_IP_BIT; 849d97b3072SJian Shen 850d97b3072SJian Shen if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 851d97b3072SJian Shen hash_sets |= HCLGEVF_V_TAG_BIT; 852d97b3072SJian Shen 853d97b3072SJian Shen return hash_sets; 854d97b3072SJian Shen } 855d97b3072SJian Shen 856d97b3072SJian Shen static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 857d97b3072SJian Shen struct ethtool_rxnfc *nfc) 858d97b3072SJian Shen { 859d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 860d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 861d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 862d97b3072SJian Shen struct hclgevf_desc desc; 863d97b3072SJian Shen u8 tuple_sets; 864d97b3072SJian Shen int ret; 865d97b3072SJian Shen 866d97b3072SJian Shen if (handle->pdev->revision == 0x20) 867d97b3072SJian Shen return -EOPNOTSUPP; 868d97b3072SJian Shen 869d97b3072SJian Shen if (nfc->data & 870d97b3072SJian Shen ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 871d97b3072SJian Shen return -EINVAL; 872d97b3072SJian Shen 873d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 874d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 875d97b3072SJian Shen 876d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 877d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 878d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 879d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 880d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 881d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 882d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 883d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 884d97b3072SJian Shen 885d97b3072SJian Shen tuple_sets = hclgevf_get_rss_hash_bits(nfc); 886d97b3072SJian Shen switch (nfc->flow_type) { 887d97b3072SJian Shen case TCP_V4_FLOW: 888d97b3072SJian Shen req->ipv4_tcp_en = tuple_sets; 889d97b3072SJian Shen break; 890d97b3072SJian Shen case TCP_V6_FLOW: 891d97b3072SJian Shen req->ipv6_tcp_en = tuple_sets; 892d97b3072SJian Shen break; 893d97b3072SJian Shen case UDP_V4_FLOW: 894d97b3072SJian Shen req->ipv4_udp_en = tuple_sets; 895d97b3072SJian Shen break; 896d97b3072SJian Shen case UDP_V6_FLOW: 897d97b3072SJian Shen req->ipv6_udp_en = tuple_sets; 898d97b3072SJian Shen break; 899d97b3072SJian Shen case SCTP_V4_FLOW: 900d97b3072SJian Shen req->ipv4_sctp_en = tuple_sets; 901d97b3072SJian Shen break; 902d97b3072SJian Shen case SCTP_V6_FLOW: 903d97b3072SJian Shen if ((nfc->data & RXH_L4_B_0_1) || 904d97b3072SJian Shen (nfc->data & RXH_L4_B_2_3)) 905d97b3072SJian Shen return -EINVAL; 906d97b3072SJian Shen 907d97b3072SJian Shen req->ipv6_sctp_en = tuple_sets; 908d97b3072SJian Shen break; 909d97b3072SJian Shen case IPV4_FLOW: 910d97b3072SJian Shen req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 911d97b3072SJian Shen break; 912d97b3072SJian Shen case IPV6_FLOW: 913d97b3072SJian Shen req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 914d97b3072SJian Shen break; 915d97b3072SJian Shen default: 916d97b3072SJian Shen return -EINVAL; 917d97b3072SJian Shen } 918d97b3072SJian Shen 919d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 920d97b3072SJian Shen if (ret) { 921d97b3072SJian Shen dev_err(&hdev->pdev->dev, 922d97b3072SJian Shen "Set rss tuple fail, status = %d\n", ret); 923d97b3072SJian Shen return ret; 924d97b3072SJian Shen } 925d97b3072SJian Shen 926d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 927d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 928d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 929d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 930d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 931d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 932d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 933d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 934d97b3072SJian Shen return 0; 935d97b3072SJian Shen } 936d97b3072SJian Shen 937d97b3072SJian Shen static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 938d97b3072SJian Shen struct ethtool_rxnfc *nfc) 939d97b3072SJian Shen { 940d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 941d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 942d97b3072SJian Shen u8 tuple_sets; 943d97b3072SJian Shen 944d97b3072SJian Shen if (handle->pdev->revision == 0x20) 945d97b3072SJian Shen return -EOPNOTSUPP; 946d97b3072SJian Shen 947d97b3072SJian Shen nfc->data = 0; 948d97b3072SJian Shen 949d97b3072SJian Shen switch (nfc->flow_type) { 950d97b3072SJian Shen case TCP_V4_FLOW: 951d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 952d97b3072SJian Shen break; 953d97b3072SJian Shen case UDP_V4_FLOW: 954d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 955d97b3072SJian Shen break; 956d97b3072SJian Shen case TCP_V6_FLOW: 957d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 958d97b3072SJian Shen break; 959d97b3072SJian Shen case UDP_V6_FLOW: 960d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 961d97b3072SJian Shen break; 962d97b3072SJian Shen case SCTP_V4_FLOW: 963d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 964d97b3072SJian Shen break; 965d97b3072SJian Shen case SCTP_V6_FLOW: 966d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 967d97b3072SJian Shen break; 968d97b3072SJian Shen case IPV4_FLOW: 969d97b3072SJian Shen case IPV6_FLOW: 970d97b3072SJian Shen tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 971d97b3072SJian Shen break; 972d97b3072SJian Shen default: 973d97b3072SJian Shen return -EINVAL; 974d97b3072SJian Shen } 975d97b3072SJian Shen 976d97b3072SJian Shen if (!tuple_sets) 977d97b3072SJian Shen return 0; 978d97b3072SJian Shen 979d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_PORT_BIT) 980d97b3072SJian Shen nfc->data |= RXH_L4_B_2_3; 981d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_PORT_BIT) 982d97b3072SJian Shen nfc->data |= RXH_L4_B_0_1; 983d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_IP_BIT) 984d97b3072SJian Shen nfc->data |= RXH_IP_DST; 985d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_IP_BIT) 986d97b3072SJian Shen nfc->data |= RXH_IP_SRC; 987d97b3072SJian Shen 988d97b3072SJian Shen return 0; 989d97b3072SJian Shen } 990d97b3072SJian Shen 991d97b3072SJian Shen static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 992d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg) 993d97b3072SJian Shen { 994d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 995d97b3072SJian Shen struct hclgevf_desc desc; 996d97b3072SJian Shen int ret; 997d97b3072SJian Shen 998d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 999d97b3072SJian Shen 1000d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 1001d97b3072SJian Shen 1002d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 1003d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 1004d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 1005d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 1006d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 1007d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 1008d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 1009d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 1010d97b3072SJian Shen 1011d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1012d97b3072SJian Shen if (ret) 1013d97b3072SJian Shen dev_err(&hdev->pdev->dev, 1014d97b3072SJian Shen "Configure rss input fail, status = %d\n", ret); 1015d97b3072SJian Shen return ret; 1016d97b3072SJian Shen } 1017d97b3072SJian Shen 1018e2cb1decSSalil Mehta static int hclgevf_get_tc_size(struct hnae3_handle *handle) 1019e2cb1decSSalil Mehta { 1020e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1021e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1022e2cb1decSSalil Mehta 1023e2cb1decSSalil Mehta return rss_cfg->rss_size; 1024e2cb1decSSalil Mehta } 1025e2cb1decSSalil Mehta 1026e2cb1decSSalil Mehta static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 1027b204bc74SPeng Li int vector_id, 1028e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1029e2cb1decSSalil Mehta { 1030e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1031d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1032e2cb1decSSalil Mehta struct hnae3_ring_chain_node *node; 1033e2cb1decSSalil Mehta int status; 1034d3410018SYufeng Mo int i = 0; 1035e2cb1decSSalil Mehta 1036d3410018SYufeng Mo memset(&send_msg, 0, sizeof(send_msg)); 1037d3410018SYufeng Mo send_msg.code = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 1038c09ba484SPeng Li HCLGE_MBX_UNMAP_RING_TO_VECTOR; 1039d3410018SYufeng Mo send_msg.vector_id = vector_id; 1040e2cb1decSSalil Mehta 1041e2cb1decSSalil Mehta for (node = ring_chain; node; node = node->next) { 1042d3410018SYufeng Mo send_msg.param[i].ring_type = 1043e4e87715SPeng Li hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 1044d3410018SYufeng Mo 1045d3410018SYufeng Mo send_msg.param[i].tqp_index = node->tqp_index; 1046d3410018SYufeng Mo send_msg.param[i].int_gl_index = 1047d3410018SYufeng Mo hnae3_get_field(node->int_gl_idx, 104879eee410SFuyun Liang HNAE3_RING_GL_IDX_M, 104979eee410SFuyun Liang HNAE3_RING_GL_IDX_S); 105079eee410SFuyun Liang 10515d02a58dSYunsheng Lin i++; 1052d3410018SYufeng Mo if (i == HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM || !node->next) { 1053d3410018SYufeng Mo send_msg.ring_num = i; 1054e2cb1decSSalil Mehta 1055d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, false, 1056d3410018SYufeng Mo NULL, 0); 1057e2cb1decSSalil Mehta if (status) { 1058e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1059e2cb1decSSalil Mehta "Map TQP fail, status is %d.\n", 1060e2cb1decSSalil Mehta status); 1061e2cb1decSSalil Mehta return status; 1062e2cb1decSSalil Mehta } 1063e2cb1decSSalil Mehta i = 0; 1064e2cb1decSSalil Mehta } 1065e2cb1decSSalil Mehta } 1066e2cb1decSSalil Mehta 1067e2cb1decSSalil Mehta return 0; 1068e2cb1decSSalil Mehta } 1069e2cb1decSSalil Mehta 1070e2cb1decSSalil Mehta static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1071e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1072e2cb1decSSalil Mehta { 1073b204bc74SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1074b204bc74SPeng Li int vector_id; 1075b204bc74SPeng Li 1076b204bc74SPeng Li vector_id = hclgevf_get_vector_index(hdev, vector); 1077b204bc74SPeng Li if (vector_id < 0) { 1078b204bc74SPeng Li dev_err(&handle->pdev->dev, 1079b204bc74SPeng Li "Get vector index fail. ret =%d\n", vector_id); 1080b204bc74SPeng Li return vector_id; 1081b204bc74SPeng Li } 1082b204bc74SPeng Li 1083b204bc74SPeng Li return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1084e2cb1decSSalil Mehta } 1085e2cb1decSSalil Mehta 1086e2cb1decSSalil Mehta static int hclgevf_unmap_ring_from_vector( 1087e2cb1decSSalil Mehta struct hnae3_handle *handle, 1088e2cb1decSSalil Mehta int vector, 1089e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1090e2cb1decSSalil Mehta { 1091e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1092e2cb1decSSalil Mehta int ret, vector_id; 1093e2cb1decSSalil Mehta 1094dea846e8SHuazhong Tan if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1095dea846e8SHuazhong Tan return 0; 1096dea846e8SHuazhong Tan 1097e2cb1decSSalil Mehta vector_id = hclgevf_get_vector_index(hdev, vector); 1098e2cb1decSSalil Mehta if (vector_id < 0) { 1099e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1100e2cb1decSSalil Mehta "Get vector index fail. ret =%d\n", vector_id); 1101e2cb1decSSalil Mehta return vector_id; 1102e2cb1decSSalil Mehta } 1103e2cb1decSSalil Mehta 1104b204bc74SPeng Li ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 11050d3e6631SYunsheng Lin if (ret) 1106e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1107e2cb1decSSalil Mehta "Unmap ring from vector fail. vector=%d, ret =%d\n", 1108e2cb1decSSalil Mehta vector_id, 1109e2cb1decSSalil Mehta ret); 11100d3e6631SYunsheng Lin 1111e2cb1decSSalil Mehta return ret; 1112e2cb1decSSalil Mehta } 1113e2cb1decSSalil Mehta 11140d3e6631SYunsheng Lin static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 11150d3e6631SYunsheng Lin { 11160d3e6631SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 111703718db9SYunsheng Lin int vector_id; 11180d3e6631SYunsheng Lin 111903718db9SYunsheng Lin vector_id = hclgevf_get_vector_index(hdev, vector); 112003718db9SYunsheng Lin if (vector_id < 0) { 112103718db9SYunsheng Lin dev_err(&handle->pdev->dev, 112203718db9SYunsheng Lin "hclgevf_put_vector get vector index fail. ret =%d\n", 112303718db9SYunsheng Lin vector_id); 112403718db9SYunsheng Lin return vector_id; 112503718db9SYunsheng Lin } 112603718db9SYunsheng Lin 112703718db9SYunsheng Lin hclgevf_free_vector(hdev, vector_id); 1128e2cb1decSSalil Mehta 1129e2cb1decSSalil Mehta return 0; 1130e2cb1decSSalil Mehta } 1131e2cb1decSSalil Mehta 11323b75c3dfSPeng Li static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1133e196ec75SJian Shen bool en_uc_pmc, bool en_mc_pmc, 1134f01f5559SJian Shen bool en_bc_pmc) 1135e2cb1decSSalil Mehta { 1136d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1137f01f5559SJian Shen int ret; 1138e2cb1decSSalil Mehta 1139d3410018SYufeng Mo memset(&send_msg, 0, sizeof(send_msg)); 1140d3410018SYufeng Mo send_msg.code = HCLGE_MBX_SET_PROMISC_MODE; 1141d3410018SYufeng Mo send_msg.en_bc = en_bc_pmc ? 1 : 0; 1142d3410018SYufeng Mo send_msg.en_uc = en_uc_pmc ? 1 : 0; 1143d3410018SYufeng Mo send_msg.en_mc = en_mc_pmc ? 1 : 0; 1144e2cb1decSSalil Mehta 1145d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1146d3410018SYufeng Mo 1147f01f5559SJian Shen if (ret) 1148e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1149f01f5559SJian Shen "Set promisc mode fail, status is %d.\n", ret); 1150e2cb1decSSalil Mehta 1151f01f5559SJian Shen return ret; 1152e2cb1decSSalil Mehta } 1153e2cb1decSSalil Mehta 1154e196ec75SJian Shen static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 1155e196ec75SJian Shen bool en_mc_pmc) 1156e2cb1decSSalil Mehta { 1157e196ec75SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1158e196ec75SJian Shen struct pci_dev *pdev = hdev->pdev; 1159e196ec75SJian Shen bool en_bc_pmc; 1160e196ec75SJian Shen 1161e196ec75SJian Shen en_bc_pmc = pdev->revision != 0x20; 1162e196ec75SJian Shen 1163e196ec75SJian Shen return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc, 1164e196ec75SJian Shen en_bc_pmc); 1165e2cb1decSSalil Mehta } 1166e2cb1decSSalil Mehta 1167ebaf1908SWeihang Li static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, unsigned int tqp_id, 1168e2cb1decSSalil Mehta int stream_id, bool enable) 1169e2cb1decSSalil Mehta { 1170e2cb1decSSalil Mehta struct hclgevf_cfg_com_tqp_queue_cmd *req; 1171e2cb1decSSalil Mehta struct hclgevf_desc desc; 1172e2cb1decSSalil Mehta int status; 1173e2cb1decSSalil Mehta 1174e2cb1decSSalil Mehta req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1175e2cb1decSSalil Mehta 1176e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1177e2cb1decSSalil Mehta false); 1178e2cb1decSSalil Mehta req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1179e2cb1decSSalil Mehta req->stream_id = cpu_to_le16(stream_id); 1180ebaf1908SWeihang Li if (enable) 1181ebaf1908SWeihang Li req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 1182e2cb1decSSalil Mehta 1183e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1184e2cb1decSSalil Mehta if (status) 1185e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1186e2cb1decSSalil Mehta "TQP enable fail, status =%d.\n", status); 1187e2cb1decSSalil Mehta 1188e2cb1decSSalil Mehta return status; 1189e2cb1decSSalil Mehta } 1190e2cb1decSSalil Mehta 1191e2cb1decSSalil Mehta static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1192e2cb1decSSalil Mehta { 1193b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1194e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 1195e2cb1decSSalil Mehta int i; 1196e2cb1decSSalil Mehta 1197b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 1198b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1199e2cb1decSSalil Mehta memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1200e2cb1decSSalil Mehta } 1201e2cb1decSSalil Mehta } 1202e2cb1decSSalil Mehta 12038e6de441SHuazhong Tan static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p) 12048e6de441SHuazhong Tan { 1205d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 12068e6de441SHuazhong Tan u8 host_mac[ETH_ALEN]; 12078e6de441SHuazhong Tan int status; 12088e6de441SHuazhong Tan 1209d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MAC_ADDR, 0); 1210d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, true, host_mac, 1211d3410018SYufeng Mo ETH_ALEN); 12128e6de441SHuazhong Tan if (status) { 12138e6de441SHuazhong Tan dev_err(&hdev->pdev->dev, 12148e6de441SHuazhong Tan "fail to get VF MAC from host %d", status); 12158e6de441SHuazhong Tan return status; 12168e6de441SHuazhong Tan } 12178e6de441SHuazhong Tan 12188e6de441SHuazhong Tan ether_addr_copy(p, host_mac); 12198e6de441SHuazhong Tan 12208e6de441SHuazhong Tan return 0; 12218e6de441SHuazhong Tan } 12228e6de441SHuazhong Tan 1223e2cb1decSSalil Mehta static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1224e2cb1decSSalil Mehta { 1225e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 12268e6de441SHuazhong Tan u8 host_mac_addr[ETH_ALEN]; 1227e2cb1decSSalil Mehta 12288e6de441SHuazhong Tan if (hclgevf_get_host_mac_addr(hdev, host_mac_addr)) 12298e6de441SHuazhong Tan return; 12308e6de441SHuazhong Tan 12318e6de441SHuazhong Tan hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr); 12328e6de441SHuazhong Tan if (hdev->has_pf_mac) 12338e6de441SHuazhong Tan ether_addr_copy(p, host_mac_addr); 12348e6de441SHuazhong Tan else 1235e2cb1decSSalil Mehta ether_addr_copy(p, hdev->hw.mac.mac_addr); 1236e2cb1decSSalil Mehta } 1237e2cb1decSSalil Mehta 123859098055SFuyun Liang static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 123959098055SFuyun Liang bool is_first) 1240e2cb1decSSalil Mehta { 1241e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1242e2cb1decSSalil Mehta u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1243d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1244e2cb1decSSalil Mehta u8 *new_mac_addr = (u8 *)p; 1245e2cb1decSSalil Mehta int status; 1246e2cb1decSSalil Mehta 1247d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 0); 1248d3410018SYufeng Mo send_msg.subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 124959098055SFuyun Liang HCLGE_MBX_MAC_VLAN_UC_MODIFY; 1250d3410018SYufeng Mo ether_addr_copy(send_msg.data, new_mac_addr); 1251d3410018SYufeng Mo ether_addr_copy(&send_msg.data[ETH_ALEN], old_mac_addr); 1252d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1253e2cb1decSSalil Mehta if (!status) 1254e2cb1decSSalil Mehta ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1255e2cb1decSSalil Mehta 1256e2cb1decSSalil Mehta return status; 1257e2cb1decSSalil Mehta } 1258e2cb1decSSalil Mehta 1259e2cb1decSSalil Mehta static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1260e2cb1decSSalil Mehta const unsigned char *addr) 1261e2cb1decSSalil Mehta { 1262e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1263d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1264e2cb1decSSalil Mehta 1265d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 1266d3410018SYufeng Mo HCLGE_MBX_MAC_VLAN_UC_ADD); 1267d3410018SYufeng Mo ether_addr_copy(send_msg.data, addr); 1268d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1269e2cb1decSSalil Mehta } 1270e2cb1decSSalil Mehta 1271e2cb1decSSalil Mehta static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1272e2cb1decSSalil Mehta const unsigned char *addr) 1273e2cb1decSSalil Mehta { 1274e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1275d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1276e2cb1decSSalil Mehta 1277d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 1278d3410018SYufeng Mo HCLGE_MBX_MAC_VLAN_UC_REMOVE); 1279d3410018SYufeng Mo ether_addr_copy(send_msg.data, addr); 1280d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1281e2cb1decSSalil Mehta } 1282e2cb1decSSalil Mehta 1283e2cb1decSSalil Mehta static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1284e2cb1decSSalil Mehta const unsigned char *addr) 1285e2cb1decSSalil Mehta { 1286e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1287d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1288e2cb1decSSalil Mehta 1289d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MULTICAST, 1290d3410018SYufeng Mo HCLGE_MBX_MAC_VLAN_MC_ADD); 1291d3410018SYufeng Mo ether_addr_copy(send_msg.data, addr); 1292d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1293e2cb1decSSalil Mehta } 1294e2cb1decSSalil Mehta 1295e2cb1decSSalil Mehta static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1296e2cb1decSSalil Mehta const unsigned char *addr) 1297e2cb1decSSalil Mehta { 1298e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1299d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1300e2cb1decSSalil Mehta 1301d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MULTICAST, 1302d3410018SYufeng Mo HCLGE_MBX_MAC_VLAN_MC_REMOVE); 1303d3410018SYufeng Mo ether_addr_copy(send_msg.data, addr); 1304d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1305e2cb1decSSalil Mehta } 1306e2cb1decSSalil Mehta 1307e2cb1decSSalil Mehta static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1308e2cb1decSSalil Mehta __be16 proto, u16 vlan_id, 1309e2cb1decSSalil Mehta bool is_kill) 1310e2cb1decSSalil Mehta { 1311d3410018SYufeng Mo #define HCLGEVF_VLAN_MBX_IS_KILL_OFFSET 0 1312d3410018SYufeng Mo #define HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET 1 1313d3410018SYufeng Mo #define HCLGEVF_VLAN_MBX_PROTO_OFFSET 3 1314d3410018SYufeng Mo 1315e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1316d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1317fe4144d4SJian Shen int ret; 1318e2cb1decSSalil Mehta 1319b37ce587SYufeng Mo if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1320e2cb1decSSalil Mehta return -EINVAL; 1321e2cb1decSSalil Mehta 1322e2cb1decSSalil Mehta if (proto != htons(ETH_P_8021Q)) 1323e2cb1decSSalil Mehta return -EPROTONOSUPPORT; 1324e2cb1decSSalil Mehta 1325fe4144d4SJian Shen /* When device is resetting, firmware is unable to handle 1326fe4144d4SJian Shen * mailbox. Just record the vlan id, and remove it after 1327fe4144d4SJian Shen * reset finished. 1328fe4144d4SJian Shen */ 1329fe4144d4SJian Shen if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) && is_kill) { 1330fe4144d4SJian Shen set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1331fe4144d4SJian Shen return -EBUSY; 1332fe4144d4SJian Shen } 1333fe4144d4SJian Shen 1334d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1335d3410018SYufeng Mo HCLGE_MBX_VLAN_FILTER); 1336d3410018SYufeng Mo send_msg.data[HCLGEVF_VLAN_MBX_IS_KILL_OFFSET] = is_kill; 1337d3410018SYufeng Mo memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET], &vlan_id, 1338d3410018SYufeng Mo sizeof(vlan_id)); 1339d3410018SYufeng Mo memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_PROTO_OFFSET], &proto, 1340d3410018SYufeng Mo sizeof(proto)); 134146ee7350SGuojia Liao /* when remove hw vlan filter failed, record the vlan id, 1342fe4144d4SJian Shen * and try to remove it from hw later, to be consistence 1343fe4144d4SJian Shen * with stack. 1344fe4144d4SJian Shen */ 1345d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1346fe4144d4SJian Shen if (is_kill && ret) 1347fe4144d4SJian Shen set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1348fe4144d4SJian Shen 1349fe4144d4SJian Shen return ret; 1350fe4144d4SJian Shen } 1351fe4144d4SJian Shen 1352fe4144d4SJian Shen static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1353fe4144d4SJian Shen { 1354fe4144d4SJian Shen #define HCLGEVF_MAX_SYNC_COUNT 60 1355fe4144d4SJian Shen struct hnae3_handle *handle = &hdev->nic; 1356fe4144d4SJian Shen int ret, sync_cnt = 0; 1357fe4144d4SJian Shen u16 vlan_id; 1358fe4144d4SJian Shen 1359fe4144d4SJian Shen vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1360fe4144d4SJian Shen while (vlan_id != VLAN_N_VID) { 1361fe4144d4SJian Shen ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1362fe4144d4SJian Shen vlan_id, true); 1363fe4144d4SJian Shen if (ret) 1364fe4144d4SJian Shen return; 1365fe4144d4SJian Shen 1366fe4144d4SJian Shen clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1367fe4144d4SJian Shen sync_cnt++; 1368fe4144d4SJian Shen if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1369fe4144d4SJian Shen return; 1370fe4144d4SJian Shen 1371fe4144d4SJian Shen vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1372fe4144d4SJian Shen } 1373e2cb1decSSalil Mehta } 1374e2cb1decSSalil Mehta 1375b2641e2aSYunsheng Lin static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1376b2641e2aSYunsheng Lin { 1377b2641e2aSYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1378d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1379b2641e2aSYunsheng Lin 1380d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1381d3410018SYufeng Mo HCLGE_MBX_VLAN_RX_OFF_CFG); 1382d3410018SYufeng Mo send_msg.data[0] = enable ? 1 : 0; 1383d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1384b2641e2aSYunsheng Lin } 1385b2641e2aSYunsheng Lin 13867fa6be4fSHuazhong Tan static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1387e2cb1decSSalil Mehta { 1388e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1389d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 13901a426f8bSPeng Li int ret; 1391e2cb1decSSalil Mehta 13921a426f8bSPeng Li /* disable vf queue before send queue reset msg to PF */ 13931a426f8bSPeng Li ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 13941a426f8bSPeng Li if (ret) 13957fa6be4fSHuazhong Tan return ret; 13961a426f8bSPeng Li 1397d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 1398d3410018SYufeng Mo memcpy(send_msg.data, &queue_id, sizeof(queue_id)); 1399d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1400e2cb1decSSalil Mehta } 1401e2cb1decSSalil Mehta 1402818f1675SYunsheng Lin static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1403818f1675SYunsheng Lin { 1404818f1675SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1405d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1406818f1675SYunsheng Lin 1407d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MTU, 0); 1408d3410018SYufeng Mo memcpy(send_msg.data, &new_mtu, sizeof(new_mtu)); 1409d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1410818f1675SYunsheng Lin } 1411818f1675SYunsheng Lin 14126988eb2aSSalil Mehta static int hclgevf_notify_client(struct hclgevf_dev *hdev, 14136988eb2aSSalil Mehta enum hnae3_reset_notify_type type) 14146988eb2aSSalil Mehta { 14156988eb2aSSalil Mehta struct hnae3_client *client = hdev->nic_client; 14166988eb2aSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 14176a5f6fa3SHuazhong Tan int ret; 14186988eb2aSSalil Mehta 141925d1817cSHuazhong Tan if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 142025d1817cSHuazhong Tan !client) 142125d1817cSHuazhong Tan return 0; 142225d1817cSHuazhong Tan 14236988eb2aSSalil Mehta if (!client->ops->reset_notify) 14246988eb2aSSalil Mehta return -EOPNOTSUPP; 14256988eb2aSSalil Mehta 14266a5f6fa3SHuazhong Tan ret = client->ops->reset_notify(handle, type); 14276a5f6fa3SHuazhong Tan if (ret) 14286a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 14296a5f6fa3SHuazhong Tan type, ret); 14306a5f6fa3SHuazhong Tan 14316a5f6fa3SHuazhong Tan return ret; 14326988eb2aSSalil Mehta } 14336988eb2aSSalil Mehta 14346988eb2aSSalil Mehta static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 14356988eb2aSSalil Mehta { 1436aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_US 20000 1437aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_CNT 2000 1438aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1439aa5c4f17SHuazhong Tan (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1440aa5c4f17SHuazhong Tan 1441aa5c4f17SHuazhong Tan u32 val; 1442aa5c4f17SHuazhong Tan int ret; 14436988eb2aSSalil Mehta 1444f28368bbSHuazhong Tan if (hdev->reset_type == HNAE3_VF_RESET) 144572e2fb07SHuazhong Tan ret = readl_poll_timeout(hdev->hw.io_base + 144672e2fb07SHuazhong Tan HCLGEVF_VF_RST_ING, val, 144772e2fb07SHuazhong Tan !(val & HCLGEVF_VF_RST_ING_BIT), 144872e2fb07SHuazhong Tan HCLGEVF_RESET_WAIT_US, 144972e2fb07SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 145072e2fb07SHuazhong Tan else 145172e2fb07SHuazhong Tan ret = readl_poll_timeout(hdev->hw.io_base + 145272e2fb07SHuazhong Tan HCLGEVF_RST_ING, val, 1453aa5c4f17SHuazhong Tan !(val & HCLGEVF_RST_ING_BITS), 1454aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_US, 1455aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 14566988eb2aSSalil Mehta 14576988eb2aSSalil Mehta /* hardware completion status should be available by this time */ 1458aa5c4f17SHuazhong Tan if (ret) { 1459aa5c4f17SHuazhong Tan dev_err(&hdev->pdev->dev, 14606988eb2aSSalil Mehta "could'nt get reset done status from h/w, timeout!\n"); 1461aa5c4f17SHuazhong Tan return ret; 14626988eb2aSSalil Mehta } 14636988eb2aSSalil Mehta 14646988eb2aSSalil Mehta /* we will wait a bit more to let reset of the stack to complete. This 14656988eb2aSSalil Mehta * might happen in case reset assertion was made by PF. Yes, this also 14666988eb2aSSalil Mehta * means we might end up waiting bit more even for VF reset. 14676988eb2aSSalil Mehta */ 14686988eb2aSSalil Mehta msleep(5000); 14696988eb2aSSalil Mehta 14706988eb2aSSalil Mehta return 0; 14716988eb2aSSalil Mehta } 14726988eb2aSSalil Mehta 14736b428b4fSHuazhong Tan static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable) 14746b428b4fSHuazhong Tan { 14756b428b4fSHuazhong Tan u32 reg_val; 14766b428b4fSHuazhong Tan 14776b428b4fSHuazhong Tan reg_val = hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG); 14786b428b4fSHuazhong Tan if (enable) 14796b428b4fSHuazhong Tan reg_val |= HCLGEVF_NIC_SW_RST_RDY; 14806b428b4fSHuazhong Tan else 14816b428b4fSHuazhong Tan reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; 14826b428b4fSHuazhong Tan 14836b428b4fSHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 14846b428b4fSHuazhong Tan reg_val); 14856b428b4fSHuazhong Tan } 14866b428b4fSHuazhong Tan 14876988eb2aSSalil Mehta static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 14886988eb2aSSalil Mehta { 14897a01c897SSalil Mehta int ret; 14907a01c897SSalil Mehta 14916988eb2aSSalil Mehta /* uninitialize the nic client */ 14926a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 14936a5f6fa3SHuazhong Tan if (ret) 14946a5f6fa3SHuazhong Tan return ret; 14956988eb2aSSalil Mehta 14967a01c897SSalil Mehta /* re-initialize the hclge device */ 14979c6f7085SHuazhong Tan ret = hclgevf_reset_hdev(hdev); 14987a01c897SSalil Mehta if (ret) { 14997a01c897SSalil Mehta dev_err(&hdev->pdev->dev, 15007a01c897SSalil Mehta "hclge device re-init failed, VF is disabled!\n"); 15017a01c897SSalil Mehta return ret; 15027a01c897SSalil Mehta } 15036988eb2aSSalil Mehta 15046988eb2aSSalil Mehta /* bring up the nic client again */ 15056a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 15066a5f6fa3SHuazhong Tan if (ret) 15076a5f6fa3SHuazhong Tan return ret; 15086988eb2aSSalil Mehta 15096b428b4fSHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT); 15106b428b4fSHuazhong Tan if (ret) 15116b428b4fSHuazhong Tan return ret; 15126b428b4fSHuazhong Tan 15136b428b4fSHuazhong Tan /* clear handshake status with IMP */ 15146b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, false); 15156b428b4fSHuazhong Tan 15161cc9bc6eSHuazhong Tan /* bring up the nic to enable TX/RX again */ 15171cc9bc6eSHuazhong Tan return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 15186988eb2aSSalil Mehta } 15196988eb2aSSalil Mehta 1520dea846e8SHuazhong Tan static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1521dea846e8SHuazhong Tan { 1522ada13ee3SHuazhong Tan #define HCLGEVF_RESET_SYNC_TIME 100 1523ada13ee3SHuazhong Tan 1524d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1525dea846e8SHuazhong Tan int ret = 0; 1526dea846e8SHuazhong Tan 1527f28368bbSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FUNC_RESET) { 1528d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_RESET, 0); 1529d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1530c88a6e7dSHuazhong Tan hdev->rst_stats.vf_func_rst_cnt++; 1531dea846e8SHuazhong Tan } 1532dea846e8SHuazhong Tan 1533ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1534ada13ee3SHuazhong Tan /* inform hardware that preparatory work is done */ 1535ada13ee3SHuazhong Tan msleep(HCLGEVF_RESET_SYNC_TIME); 15366b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, true); 1537dea846e8SHuazhong Tan dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1538dea846e8SHuazhong Tan hdev->reset_type, ret); 1539dea846e8SHuazhong Tan 1540dea846e8SHuazhong Tan return ret; 1541dea846e8SHuazhong Tan } 1542dea846e8SHuazhong Tan 15433d77d0cbSHuazhong Tan static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev) 15443d77d0cbSHuazhong Tan { 15453d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "VF function reset count: %u\n", 15463d77d0cbSHuazhong Tan hdev->rst_stats.vf_func_rst_cnt); 15473d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "FLR reset count: %u\n", 15483d77d0cbSHuazhong Tan hdev->rst_stats.flr_rst_cnt); 15493d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "VF reset count: %u\n", 15503d77d0cbSHuazhong Tan hdev->rst_stats.vf_rst_cnt); 15513d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "reset done count: %u\n", 15523d77d0cbSHuazhong Tan hdev->rst_stats.rst_done_cnt); 15533d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "HW reset done count: %u\n", 15543d77d0cbSHuazhong Tan hdev->rst_stats.hw_rst_done_cnt); 15553d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "reset count: %u\n", 15563d77d0cbSHuazhong Tan hdev->rst_stats.rst_cnt); 15573d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "reset fail count: %u\n", 15583d77d0cbSHuazhong Tan hdev->rst_stats.rst_fail_cnt); 15593d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n", 15603d77d0cbSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE)); 15613d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n", 15623d77d0cbSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_STAT_REG)); 15633d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n", 15643d77d0cbSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_CMDQ_TX_DEPTH_REG)); 15653d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n", 15663d77d0cbSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING)); 15673d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state); 15683d77d0cbSHuazhong Tan } 15693d77d0cbSHuazhong Tan 1570bbe6540eSHuazhong Tan static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1571bbe6540eSHuazhong Tan { 15726b428b4fSHuazhong Tan /* recover handshake status with IMP when reset fail */ 15736b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, true); 1574bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt++; 1575adcf738bSGuojia Liao dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n", 1576bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt); 1577bbe6540eSHuazhong Tan 1578bbe6540eSHuazhong Tan if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1579bbe6540eSHuazhong Tan set_bit(hdev->reset_type, &hdev->reset_pending); 1580bbe6540eSHuazhong Tan 1581bbe6540eSHuazhong Tan if (hclgevf_is_reset_pending(hdev)) { 1582bbe6540eSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1583bbe6540eSHuazhong Tan hclgevf_reset_task_schedule(hdev); 15843d77d0cbSHuazhong Tan } else { 1585d5432455SGuojia Liao set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 15863d77d0cbSHuazhong Tan hclgevf_dump_rst_info(hdev); 1587bbe6540eSHuazhong Tan } 1588bbe6540eSHuazhong Tan } 1589bbe6540eSHuazhong Tan 15901cc9bc6eSHuazhong Tan static int hclgevf_reset_prepare(struct hclgevf_dev *hdev) 15916988eb2aSSalil Mehta { 1592dea846e8SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 15936988eb2aSSalil Mehta int ret; 15946988eb2aSSalil Mehta 1595dea846e8SHuazhong Tan /* Initialize ae_dev reset status as well, in case enet layer wants to 1596dea846e8SHuazhong Tan * know if device is undergoing reset 1597dea846e8SHuazhong Tan */ 1598dea846e8SHuazhong Tan ae_dev->reset_type = hdev->reset_type; 1599c88a6e7dSHuazhong Tan hdev->rst_stats.rst_cnt++; 16006988eb2aSSalil Mehta 16011cc9bc6eSHuazhong Tan rtnl_lock(); 16026988eb2aSSalil Mehta /* bring down the nic to stop any ongoing TX/RX */ 16036a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 160429118ab9SHuazhong Tan rtnl_unlock(); 16056a5f6fa3SHuazhong Tan if (ret) 16061cc9bc6eSHuazhong Tan return ret; 1607dea846e8SHuazhong Tan 16081cc9bc6eSHuazhong Tan return hclgevf_reset_prepare_wait(hdev); 16096988eb2aSSalil Mehta } 16106988eb2aSSalil Mehta 16111cc9bc6eSHuazhong Tan static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev) 16121cc9bc6eSHuazhong Tan { 16131cc9bc6eSHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 16141cc9bc6eSHuazhong Tan int ret; 16151cc9bc6eSHuazhong Tan 1616c88a6e7dSHuazhong Tan hdev->rst_stats.hw_rst_done_cnt++; 1617c88a6e7dSHuazhong Tan 161829118ab9SHuazhong Tan rtnl_lock(); 16196988eb2aSSalil Mehta /* now, re-initialize the nic client and ae device */ 16206988eb2aSSalil Mehta ret = hclgevf_reset_stack(hdev); 16211cc9bc6eSHuazhong Tan rtnl_unlock(); 16226a5f6fa3SHuazhong Tan if (ret) { 16236988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 16241cc9bc6eSHuazhong Tan return ret; 16256a5f6fa3SHuazhong Tan } 16266988eb2aSSalil Mehta 1627b644a8d4SHuazhong Tan hdev->last_reset_time = jiffies; 1628b644a8d4SHuazhong Tan ae_dev->reset_type = HNAE3_NONE_RESET; 1629c88a6e7dSHuazhong Tan hdev->rst_stats.rst_done_cnt++; 1630bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt = 0; 1631d5432455SGuojia Liao clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1632b644a8d4SHuazhong Tan 16331cc9bc6eSHuazhong Tan return 0; 16341cc9bc6eSHuazhong Tan } 16351cc9bc6eSHuazhong Tan 16361cc9bc6eSHuazhong Tan static void hclgevf_reset(struct hclgevf_dev *hdev) 16371cc9bc6eSHuazhong Tan { 16381cc9bc6eSHuazhong Tan if (hclgevf_reset_prepare(hdev)) 16391cc9bc6eSHuazhong Tan goto err_reset; 16401cc9bc6eSHuazhong Tan 16411cc9bc6eSHuazhong Tan /* check if VF could successfully fetch the hardware reset completion 16421cc9bc6eSHuazhong Tan * status from the hardware 16431cc9bc6eSHuazhong Tan */ 16441cc9bc6eSHuazhong Tan if (hclgevf_reset_wait(hdev)) { 16451cc9bc6eSHuazhong Tan /* can't do much in this situation, will disable VF */ 16461cc9bc6eSHuazhong Tan dev_err(&hdev->pdev->dev, 16471cc9bc6eSHuazhong Tan "failed to fetch H/W reset completion status\n"); 16481cc9bc6eSHuazhong Tan goto err_reset; 16491cc9bc6eSHuazhong Tan } 16501cc9bc6eSHuazhong Tan 16511cc9bc6eSHuazhong Tan if (hclgevf_reset_rebuild(hdev)) 16521cc9bc6eSHuazhong Tan goto err_reset; 16531cc9bc6eSHuazhong Tan 16541cc9bc6eSHuazhong Tan return; 16551cc9bc6eSHuazhong Tan 16566a5f6fa3SHuazhong Tan err_reset: 1657bbe6540eSHuazhong Tan hclgevf_reset_err_handle(hdev); 16586988eb2aSSalil Mehta } 16596988eb2aSSalil Mehta 1660720bd583SHuazhong Tan static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1661720bd583SHuazhong Tan unsigned long *addr) 1662720bd583SHuazhong Tan { 1663720bd583SHuazhong Tan enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1664720bd583SHuazhong Tan 1665dea846e8SHuazhong Tan /* return the highest priority reset level amongst all */ 1666b90fcc5bSHuazhong Tan if (test_bit(HNAE3_VF_RESET, addr)) { 1667b90fcc5bSHuazhong Tan rst_level = HNAE3_VF_RESET; 1668b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_RESET, addr); 1669b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1670b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1671b90fcc5bSHuazhong Tan } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1672dea846e8SHuazhong Tan rst_level = HNAE3_VF_FULL_RESET; 1673dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FULL_RESET, addr); 1674dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1675aa5c4f17SHuazhong Tan } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1676aa5c4f17SHuazhong Tan rst_level = HNAE3_VF_PF_FUNC_RESET; 1677aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1678aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1679dea846e8SHuazhong Tan } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1680dea846e8SHuazhong Tan rst_level = HNAE3_VF_FUNC_RESET; 1681dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 16826ff3cf07SHuazhong Tan } else if (test_bit(HNAE3_FLR_RESET, addr)) { 16836ff3cf07SHuazhong Tan rst_level = HNAE3_FLR_RESET; 16846ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_RESET, addr); 1685720bd583SHuazhong Tan } 1686720bd583SHuazhong Tan 1687720bd583SHuazhong Tan return rst_level; 1688720bd583SHuazhong Tan } 1689720bd583SHuazhong Tan 16906ae4e733SShiju Jose static void hclgevf_reset_event(struct pci_dev *pdev, 16916ae4e733SShiju Jose struct hnae3_handle *handle) 16926d4c3981SSalil Mehta { 16936ff3cf07SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 16946ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 16956d4c3981SSalil Mehta 16966d4c3981SSalil Mehta dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 16976d4c3981SSalil Mehta 16986ff3cf07SHuazhong Tan if (hdev->default_reset_request) 16990742ed7cSHuazhong Tan hdev->reset_level = 1700720bd583SHuazhong Tan hclgevf_get_reset_level(hdev, 1701720bd583SHuazhong Tan &hdev->default_reset_request); 1702720bd583SHuazhong Tan else 1703dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 17046d4c3981SSalil Mehta 1705436667d2SSalil Mehta /* reset of this VF requested */ 1706436667d2SSalil Mehta set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1707436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 17086d4c3981SSalil Mehta 17090742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 17106d4c3981SSalil Mehta } 17116d4c3981SSalil Mehta 1712720bd583SHuazhong Tan static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1713720bd583SHuazhong Tan enum hnae3_reset_type rst_type) 1714720bd583SHuazhong Tan { 1715720bd583SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1716720bd583SHuazhong Tan 1717720bd583SHuazhong Tan set_bit(rst_type, &hdev->default_reset_request); 1718720bd583SHuazhong Tan } 1719720bd583SHuazhong Tan 1720f28368bbSHuazhong Tan static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1721f28368bbSHuazhong Tan { 1722f28368bbSHuazhong Tan writel(en ? 1 : 0, vector->addr); 1723f28368bbSHuazhong Tan } 1724f28368bbSHuazhong Tan 17256ff3cf07SHuazhong Tan static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 17266ff3cf07SHuazhong Tan { 1727f28368bbSHuazhong Tan #define HCLGEVF_FLR_RETRY_WAIT_MS 500 1728f28368bbSHuazhong Tan #define HCLGEVF_FLR_RETRY_CNT 5 1729f28368bbSHuazhong Tan 17306ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1731f28368bbSHuazhong Tan int retry_cnt = 0; 1732f28368bbSHuazhong Tan int ret; 17336ff3cf07SHuazhong Tan 1734f28368bbSHuazhong Tan retry: 1735f28368bbSHuazhong Tan down(&hdev->reset_sem); 1736f28368bbSHuazhong Tan set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1737f28368bbSHuazhong Tan hdev->reset_type = HNAE3_FLR_RESET; 1738f28368bbSHuazhong Tan ret = hclgevf_reset_prepare(hdev); 1739f28368bbSHuazhong Tan if (ret) { 1740f28368bbSHuazhong Tan dev_err(&hdev->pdev->dev, "fail to prepare FLR, ret=%d\n", 1741f28368bbSHuazhong Tan ret); 1742f28368bbSHuazhong Tan if (hdev->reset_pending || 1743f28368bbSHuazhong Tan retry_cnt++ < HCLGEVF_FLR_RETRY_CNT) { 17446ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 1745f28368bbSHuazhong Tan "reset_pending:0x%lx, retry_cnt:%d\n", 1746f28368bbSHuazhong Tan hdev->reset_pending, retry_cnt); 1747f28368bbSHuazhong Tan clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1748f28368bbSHuazhong Tan up(&hdev->reset_sem); 1749f28368bbSHuazhong Tan msleep(HCLGEVF_FLR_RETRY_WAIT_MS); 1750f28368bbSHuazhong Tan goto retry; 1751f28368bbSHuazhong Tan } 1752f28368bbSHuazhong Tan } 1753f28368bbSHuazhong Tan 1754f28368bbSHuazhong Tan /* disable misc vector before FLR done */ 1755f28368bbSHuazhong Tan hclgevf_enable_vector(&hdev->misc_vector, false); 1756f28368bbSHuazhong Tan hdev->rst_stats.flr_rst_cnt++; 1757f28368bbSHuazhong Tan } 1758f28368bbSHuazhong Tan 1759f28368bbSHuazhong Tan static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 1760f28368bbSHuazhong Tan { 1761f28368bbSHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1762f28368bbSHuazhong Tan int ret; 1763f28368bbSHuazhong Tan 1764f28368bbSHuazhong Tan hclgevf_enable_vector(&hdev->misc_vector, true); 1765f28368bbSHuazhong Tan 1766f28368bbSHuazhong Tan ret = hclgevf_reset_rebuild(hdev); 1767f28368bbSHuazhong Tan if (ret) 1768f28368bbSHuazhong Tan dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", 1769f28368bbSHuazhong Tan ret); 1770f28368bbSHuazhong Tan 1771f28368bbSHuazhong Tan hdev->reset_type = HNAE3_NONE_RESET; 1772f28368bbSHuazhong Tan clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1773f28368bbSHuazhong Tan up(&hdev->reset_sem); 17746ff3cf07SHuazhong Tan } 17756ff3cf07SHuazhong Tan 1776e2cb1decSSalil Mehta static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1777e2cb1decSSalil Mehta { 1778e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1779e2cb1decSSalil Mehta 1780e2cb1decSSalil Mehta return hdev->fw_version; 1781e2cb1decSSalil Mehta } 1782e2cb1decSSalil Mehta 1783e2cb1decSSalil Mehta static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1784e2cb1decSSalil Mehta { 1785e2cb1decSSalil Mehta struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1786e2cb1decSSalil Mehta 1787e2cb1decSSalil Mehta vector->vector_irq = pci_irq_vector(hdev->pdev, 1788e2cb1decSSalil Mehta HCLGEVF_MISC_VECTOR_NUM); 1789e2cb1decSSalil Mehta vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1790e2cb1decSSalil Mehta /* vector status always valid for Vector 0 */ 1791e2cb1decSSalil Mehta hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1792e2cb1decSSalil Mehta hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1793e2cb1decSSalil Mehta 1794e2cb1decSSalil Mehta hdev->num_msi_left -= 1; 1795e2cb1decSSalil Mehta hdev->num_msi_used += 1; 1796e2cb1decSSalil Mehta } 1797e2cb1decSSalil Mehta 179835a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 179935a1e503SSalil Mehta { 1800ff200099SYunsheng Lin if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1801ff200099SYunsheng Lin !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, 1802ff200099SYunsheng Lin &hdev->state)) 18030ea68902SYunsheng Lin mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 180435a1e503SSalil Mehta } 180535a1e503SSalil Mehta 180607a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1807e2cb1decSSalil Mehta { 1808ff200099SYunsheng Lin if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1809ff200099SYunsheng Lin !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, 1810ff200099SYunsheng Lin &hdev->state)) 18110ea68902SYunsheng Lin mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 181207a0556aSSalil Mehta } 1813e2cb1decSSalil Mehta 1814ff200099SYunsheng Lin static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 1815ff200099SYunsheng Lin unsigned long delay) 1816e2cb1decSSalil Mehta { 1817d5432455SGuojia Liao if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1818d5432455SGuojia Liao !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 18190ea68902SYunsheng Lin mod_delayed_work(hclgevf_wq, &hdev->service_task, delay); 1820e2cb1decSSalil Mehta } 1821e2cb1decSSalil Mehta 1822ff200099SYunsheng Lin static void hclgevf_reset_service_task(struct hclgevf_dev *hdev) 182335a1e503SSalil Mehta { 1824d6ad7c53SGuojia Liao #define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3 1825d6ad7c53SGuojia Liao 1826ff200099SYunsheng Lin if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state)) 1827ff200099SYunsheng Lin return; 1828ff200099SYunsheng Lin 1829f28368bbSHuazhong Tan down(&hdev->reset_sem); 1830f28368bbSHuazhong Tan set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 183135a1e503SSalil Mehta 1832436667d2SSalil Mehta if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1833436667d2SSalil Mehta &hdev->reset_state)) { 1834436667d2SSalil Mehta /* PF has initmated that it is about to reset the hardware. 18359b2f3477SWeihang Li * We now have to poll & check if hardware has actually 18369b2f3477SWeihang Li * completed the reset sequence. On hardware reset completion, 18379b2f3477SWeihang Li * VF needs to reset the client and ae device. 183835a1e503SSalil Mehta */ 1839436667d2SSalil Mehta hdev->reset_attempts = 0; 1840436667d2SSalil Mehta 1841dea846e8SHuazhong Tan hdev->last_reset_time = jiffies; 1842dea846e8SHuazhong Tan while ((hdev->reset_type = 1843dea846e8SHuazhong Tan hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 18441cc9bc6eSHuazhong Tan != HNAE3_NONE_RESET) 18451cc9bc6eSHuazhong Tan hclgevf_reset(hdev); 1846436667d2SSalil Mehta } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1847436667d2SSalil Mehta &hdev->reset_state)) { 1848436667d2SSalil Mehta /* we could be here when either of below happens: 18499b2f3477SWeihang Li * 1. reset was initiated due to watchdog timeout caused by 1850436667d2SSalil Mehta * a. IMP was earlier reset and our TX got choked down and 1851436667d2SSalil Mehta * which resulted in watchdog reacting and inducing VF 1852436667d2SSalil Mehta * reset. This also means our cmdq would be unreliable. 1853436667d2SSalil Mehta * b. problem in TX due to other lower layer(example link 1854436667d2SSalil Mehta * layer not functioning properly etc.) 1855436667d2SSalil Mehta * 2. VF reset might have been initiated due to some config 1856436667d2SSalil Mehta * change. 1857436667d2SSalil Mehta * 1858436667d2SSalil Mehta * NOTE: Theres no clear way to detect above cases than to react 1859436667d2SSalil Mehta * to the response of PF for this reset request. PF will ack the 1860436667d2SSalil Mehta * 1b and 2. cases but we will not get any intimation about 1a 1861436667d2SSalil Mehta * from PF as cmdq would be in unreliable state i.e. mailbox 1862436667d2SSalil Mehta * communication between PF and VF would be broken. 186346ee7350SGuojia Liao * 186446ee7350SGuojia Liao * if we are never geting into pending state it means either: 1865436667d2SSalil Mehta * 1. PF is not receiving our request which could be due to IMP 1866436667d2SSalil Mehta * reset 1867436667d2SSalil Mehta * 2. PF is screwed 1868436667d2SSalil Mehta * We cannot do much for 2. but to check first we can try reset 1869436667d2SSalil Mehta * our PCIe + stack and see if it alleviates the problem. 1870436667d2SSalil Mehta */ 1871d6ad7c53SGuojia Liao if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) { 1872436667d2SSalil Mehta /* prepare for full reset of stack + pcie interface */ 1873dea846e8SHuazhong Tan set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1874436667d2SSalil Mehta 1875436667d2SSalil Mehta /* "defer" schedule the reset task again */ 1876436667d2SSalil Mehta set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1877436667d2SSalil Mehta } else { 1878436667d2SSalil Mehta hdev->reset_attempts++; 1879436667d2SSalil Mehta 1880dea846e8SHuazhong Tan set_bit(hdev->reset_level, &hdev->reset_pending); 1881dea846e8SHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1882436667d2SSalil Mehta } 1883dea846e8SHuazhong Tan hclgevf_reset_task_schedule(hdev); 1884436667d2SSalil Mehta } 188535a1e503SSalil Mehta 1886afb6afdbSHuazhong Tan hdev->reset_type = HNAE3_NONE_RESET; 188735a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1888f28368bbSHuazhong Tan up(&hdev->reset_sem); 188935a1e503SSalil Mehta } 189035a1e503SSalil Mehta 1891ff200099SYunsheng Lin static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev) 1892e2cb1decSSalil Mehta { 1893ff200099SYunsheng Lin if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state)) 1894ff200099SYunsheng Lin return; 1895e2cb1decSSalil Mehta 1896e2cb1decSSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1897e2cb1decSSalil Mehta return; 1898e2cb1decSSalil Mehta 189907a0556aSSalil Mehta hclgevf_mbx_async_handler(hdev); 1900e2cb1decSSalil Mehta 1901e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1902e2cb1decSSalil Mehta } 1903e2cb1decSSalil Mehta 1904ff200099SYunsheng Lin static void hclgevf_keep_alive(struct hclgevf_dev *hdev) 1905a6d818e3SYunsheng Lin { 1906d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1907a6d818e3SYunsheng Lin int ret; 1908a6d818e3SYunsheng Lin 19091416d333SHuazhong Tan if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 1910c59a85c0SJian Shen return; 1911c59a85c0SJian Shen 1912d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_KEEP_ALIVE, 0); 1913d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1914a6d818e3SYunsheng Lin if (ret) 1915a6d818e3SYunsheng Lin dev_err(&hdev->pdev->dev, 1916a6d818e3SYunsheng Lin "VF sends keep alive cmd failed(=%d)\n", ret); 1917a6d818e3SYunsheng Lin } 1918a6d818e3SYunsheng Lin 1919ff200099SYunsheng Lin static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev) 1920e2cb1decSSalil Mehta { 1921ff200099SYunsheng Lin unsigned long delta = round_jiffies_relative(HZ); 1922ff200099SYunsheng Lin struct hnae3_handle *handle = &hdev->nic; 1923e2cb1decSSalil Mehta 1924ff200099SYunsheng Lin if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 1925ff200099SYunsheng Lin delta = jiffies - hdev->last_serv_processed; 1926db01afebSliuzhongzhu 1927ff200099SYunsheng Lin if (delta < round_jiffies_relative(HZ)) { 1928ff200099SYunsheng Lin delta = round_jiffies_relative(HZ) - delta; 1929ff200099SYunsheng Lin goto out; 1930db01afebSliuzhongzhu } 1931ff200099SYunsheng Lin } 1932ff200099SYunsheng Lin 1933ff200099SYunsheng Lin hdev->serv_processed_cnt++; 1934ff200099SYunsheng Lin if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL)) 1935ff200099SYunsheng Lin hclgevf_keep_alive(hdev); 1936ff200099SYunsheng Lin 1937ff200099SYunsheng Lin if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) { 1938ff200099SYunsheng Lin hdev->last_serv_processed = jiffies; 1939ff200099SYunsheng Lin goto out; 1940ff200099SYunsheng Lin } 1941ff200099SYunsheng Lin 1942ff200099SYunsheng Lin if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL)) 1943ff200099SYunsheng Lin hclgevf_tqps_update_stats(handle); 1944e2cb1decSSalil Mehta 1945e2cb1decSSalil Mehta /* request the link status from the PF. PF would be able to tell VF 1946e2cb1decSSalil Mehta * about such updates in future so we might remove this later 1947e2cb1decSSalil Mehta */ 1948e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1949e2cb1decSSalil Mehta 19509194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 19519194d18bSliuzhongzhu 1952fe4144d4SJian Shen hclgevf_sync_vlan_filter(hdev); 1953fe4144d4SJian Shen 1954ff200099SYunsheng Lin hdev->last_serv_processed = jiffies; 1955436667d2SSalil Mehta 1956ff200099SYunsheng Lin out: 1957ff200099SYunsheng Lin hclgevf_task_schedule(hdev, delta); 1958ff200099SYunsheng Lin } 1959b3c3fe8eSYunsheng Lin 1960ff200099SYunsheng Lin static void hclgevf_service_task(struct work_struct *work) 1961ff200099SYunsheng Lin { 1962ff200099SYunsheng Lin struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev, 1963ff200099SYunsheng Lin service_task.work); 1964ff200099SYunsheng Lin 1965ff200099SYunsheng Lin hclgevf_reset_service_task(hdev); 1966ff200099SYunsheng Lin hclgevf_mailbox_service_task(hdev); 1967ff200099SYunsheng Lin hclgevf_periodic_service_task(hdev); 1968ff200099SYunsheng Lin 1969ff200099SYunsheng Lin /* Handle reset and mbx again in case periodical task delays the 1970ff200099SYunsheng Lin * handling by calling hclgevf_task_schedule() in 1971ff200099SYunsheng Lin * hclgevf_periodic_service_task() 1972ff200099SYunsheng Lin */ 1973ff200099SYunsheng Lin hclgevf_reset_service_task(hdev); 1974ff200099SYunsheng Lin hclgevf_mailbox_service_task(hdev); 1975e2cb1decSSalil Mehta } 1976e2cb1decSSalil Mehta 1977e2cb1decSSalil Mehta static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1978e2cb1decSSalil Mehta { 1979e2cb1decSSalil Mehta hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1980e2cb1decSSalil Mehta } 1981e2cb1decSSalil Mehta 1982b90fcc5bSHuazhong Tan static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1983b90fcc5bSHuazhong Tan u32 *clearval) 1984e2cb1decSSalil Mehta { 198513050921SHuazhong Tan u32 val, cmdq_stat_reg, rst_ing_reg; 1986e2cb1decSSalil Mehta 1987e2cb1decSSalil Mehta /* fetch the events from their corresponding regs */ 198813050921SHuazhong Tan cmdq_stat_reg = hclgevf_read_dev(&hdev->hw, 198913050921SHuazhong Tan HCLGEVF_VECTOR0_CMDQ_STAT_REG); 1990e2cb1decSSalil Mehta 199113050921SHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 1992b90fcc5bSHuazhong Tan rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1993b90fcc5bSHuazhong Tan dev_info(&hdev->pdev->dev, 1994b90fcc5bSHuazhong Tan "receive reset interrupt 0x%x!\n", rst_ing_reg); 1995b90fcc5bSHuazhong Tan set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1996b90fcc5bSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1997ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 199813050921SHuazhong Tan *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B); 1999c88a6e7dSHuazhong Tan hdev->rst_stats.vf_rst_cnt++; 200072e2fb07SHuazhong Tan /* set up VF hardware reset status, its PF will clear 200172e2fb07SHuazhong Tan * this status when PF has initialized done. 200272e2fb07SHuazhong Tan */ 200372e2fb07SHuazhong Tan val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING); 200472e2fb07SHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING, 200572e2fb07SHuazhong Tan val | HCLGEVF_VF_RST_ING_BIT); 2006b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_RST; 2007b90fcc5bSHuazhong Tan } 2008b90fcc5bSHuazhong Tan 2009e2cb1decSSalil Mehta /* check for vector0 mailbox(=CMDQ RX) event source */ 201013050921SHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 201113050921SHuazhong Tan /* for revision 0x21, clearing interrupt is writing bit 0 201213050921SHuazhong Tan * to the clear register, writing bit 1 means to keep the 201313050921SHuazhong Tan * old value. 201413050921SHuazhong Tan * for revision 0x20, the clear register is a read & write 201513050921SHuazhong Tan * register, so we should just write 0 to the bit we are 201613050921SHuazhong Tan * handling, and keep other bits as cmdq_stat_reg. 201713050921SHuazhong Tan */ 201813050921SHuazhong Tan if (hdev->pdev->revision >= 0x21) 201913050921SHuazhong Tan *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 202013050921SHuazhong Tan else 202113050921SHuazhong Tan *clearval = cmdq_stat_reg & 202213050921SHuazhong Tan ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 202313050921SHuazhong Tan 2024b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_MBX; 2025e2cb1decSSalil Mehta } 2026e2cb1decSSalil Mehta 2027e45afb39SHuazhong Tan /* print other vector0 event source */ 2028e45afb39SHuazhong Tan dev_info(&hdev->pdev->dev, 2029e45afb39SHuazhong Tan "vector 0 interrupt from unknown source, cmdq_src = %#x\n", 2030e45afb39SHuazhong Tan cmdq_stat_reg); 2031e2cb1decSSalil Mehta 2032b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_OTHER; 2033e2cb1decSSalil Mehta } 2034e2cb1decSSalil Mehta 2035e2cb1decSSalil Mehta static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 2036e2cb1decSSalil Mehta { 2037b90fcc5bSHuazhong Tan enum hclgevf_evt_cause event_cause; 2038e2cb1decSSalil Mehta struct hclgevf_dev *hdev = data; 2039e2cb1decSSalil Mehta u32 clearval; 2040e2cb1decSSalil Mehta 2041e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 2042b90fcc5bSHuazhong Tan event_cause = hclgevf_check_evt_cause(hdev, &clearval); 2043e2cb1decSSalil Mehta 2044b90fcc5bSHuazhong Tan switch (event_cause) { 2045b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_RST: 2046b90fcc5bSHuazhong Tan hclgevf_reset_task_schedule(hdev); 2047b90fcc5bSHuazhong Tan break; 2048b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_MBX: 204907a0556aSSalil Mehta hclgevf_mbx_handler(hdev); 2050b90fcc5bSHuazhong Tan break; 2051b90fcc5bSHuazhong Tan default: 2052b90fcc5bSHuazhong Tan break; 2053b90fcc5bSHuazhong Tan } 2054e2cb1decSSalil Mehta 2055b90fcc5bSHuazhong Tan if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 2056e2cb1decSSalil Mehta hclgevf_clear_event_cause(hdev, clearval); 2057e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2058b90fcc5bSHuazhong Tan } 2059e2cb1decSSalil Mehta 2060e2cb1decSSalil Mehta return IRQ_HANDLED; 2061e2cb1decSSalil Mehta } 2062e2cb1decSSalil Mehta 2063e2cb1decSSalil Mehta static int hclgevf_configure(struct hclgevf_dev *hdev) 2064e2cb1decSSalil Mehta { 2065e2cb1decSSalil Mehta int ret; 2066e2cb1decSSalil Mehta 206792f11ea1SJian Shen /* get current port based vlan state from PF */ 206892f11ea1SJian Shen ret = hclgevf_get_port_base_vlan_filter_state(hdev); 206992f11ea1SJian Shen if (ret) 207092f11ea1SJian Shen return ret; 207192f11ea1SJian Shen 2072e2cb1decSSalil Mehta /* get queue configuration from PF */ 20736cee6fc3SJian Shen ret = hclgevf_get_queue_info(hdev); 2074e2cb1decSSalil Mehta if (ret) 2075e2cb1decSSalil Mehta return ret; 2076c0425944SPeng Li 2077c0425944SPeng Li /* get queue depth info from PF */ 2078c0425944SPeng Li ret = hclgevf_get_queue_depth(hdev); 2079c0425944SPeng Li if (ret) 2080c0425944SPeng Li return ret; 2081c0425944SPeng Li 20829c3e7130Sliuzhongzhu ret = hclgevf_get_pf_media_type(hdev); 20839c3e7130Sliuzhongzhu if (ret) 20849c3e7130Sliuzhongzhu return ret; 20859c3e7130Sliuzhongzhu 2086e2cb1decSSalil Mehta /* get tc configuration from PF */ 2087e2cb1decSSalil Mehta return hclgevf_get_tc_info(hdev); 2088e2cb1decSSalil Mehta } 2089e2cb1decSSalil Mehta 20907a01c897SSalil Mehta static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 20917a01c897SSalil Mehta { 20927a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 20931154bb26SPeng Li struct hclgevf_dev *hdev; 20947a01c897SSalil Mehta 20957a01c897SSalil Mehta hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 20967a01c897SSalil Mehta if (!hdev) 20977a01c897SSalil Mehta return -ENOMEM; 20987a01c897SSalil Mehta 20997a01c897SSalil Mehta hdev->pdev = pdev; 21007a01c897SSalil Mehta hdev->ae_dev = ae_dev; 21017a01c897SSalil Mehta ae_dev->priv = hdev; 21027a01c897SSalil Mehta 21037a01c897SSalil Mehta return 0; 21047a01c897SSalil Mehta } 21057a01c897SSalil Mehta 2106e2cb1decSSalil Mehta static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 2107e2cb1decSSalil Mehta { 2108e2cb1decSSalil Mehta struct hnae3_handle *roce = &hdev->roce; 2109e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 2110e2cb1decSSalil Mehta 211107acf909SJian Shen roce->rinfo.num_vectors = hdev->num_roce_msix; 2112e2cb1decSSalil Mehta 2113e2cb1decSSalil Mehta if (hdev->num_msi_left < roce->rinfo.num_vectors || 2114e2cb1decSSalil Mehta hdev->num_msi_left == 0) 2115e2cb1decSSalil Mehta return -EINVAL; 2116e2cb1decSSalil Mehta 211707acf909SJian Shen roce->rinfo.base_vector = hdev->roce_base_vector; 2118e2cb1decSSalil Mehta 2119e2cb1decSSalil Mehta roce->rinfo.netdev = nic->kinfo.netdev; 2120e2cb1decSSalil Mehta roce->rinfo.roce_io_base = hdev->hw.io_base; 2121e2cb1decSSalil Mehta 2122e2cb1decSSalil Mehta roce->pdev = nic->pdev; 2123e2cb1decSSalil Mehta roce->ae_algo = nic->ae_algo; 2124e2cb1decSSalil Mehta roce->numa_node_mask = nic->numa_node_mask; 2125e2cb1decSSalil Mehta 2126e2cb1decSSalil Mehta return 0; 2127e2cb1decSSalil Mehta } 2128e2cb1decSSalil Mehta 2129b26a6feaSPeng Li static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 2130b26a6feaSPeng Li { 2131b26a6feaSPeng Li struct hclgevf_cfg_gro_status_cmd *req; 2132b26a6feaSPeng Li struct hclgevf_desc desc; 2133b26a6feaSPeng Li int ret; 2134b26a6feaSPeng Li 2135b26a6feaSPeng Li if (!hnae3_dev_gro_supported(hdev)) 2136b26a6feaSPeng Li return 0; 2137b26a6feaSPeng Li 2138b26a6feaSPeng Li hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 2139b26a6feaSPeng Li false); 2140b26a6feaSPeng Li req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2141b26a6feaSPeng Li 2142b26a6feaSPeng Li req->gro_en = cpu_to_le16(en ? 1 : 0); 2143b26a6feaSPeng Li 2144b26a6feaSPeng Li ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2145b26a6feaSPeng Li if (ret) 2146b26a6feaSPeng Li dev_err(&hdev->pdev->dev, 2147b26a6feaSPeng Li "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2148b26a6feaSPeng Li 2149b26a6feaSPeng Li return ret; 2150b26a6feaSPeng Li } 2151b26a6feaSPeng Li 2152e2cb1decSSalil Mehta static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2153e2cb1decSSalil Mehta { 2154e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 21554093d1a2SGuangbin Huang int ret; 21564093d1a2SGuangbin Huang u32 i; 2157e2cb1decSSalil Mehta 21584093d1a2SGuangbin Huang rss_cfg->rss_size = hdev->nic.kinfo.rss_size; 2159e2cb1decSSalil Mehta 2160374ad291SJian Shen if (hdev->pdev->revision >= 0x21) { 2161472d7eceSJian Shen rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 2162472d7eceSJian Shen memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 2163374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 2164374ad291SJian Shen 2165374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 2166374ad291SJian Shen rss_cfg->rss_hash_key); 2167374ad291SJian Shen if (ret) 2168374ad291SJian Shen return ret; 2169d97b3072SJian Shen 2170d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = 2171d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2172d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = 2173d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2174d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = 2175d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2176d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = 2177d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2178d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = 2179d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2180d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = 2181d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2182d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = 2183d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2184d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = 2185d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2186d97b3072SJian Shen 2187d97b3072SJian Shen ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 2188d97b3072SJian Shen if (ret) 2189d97b3072SJian Shen return ret; 2190374ad291SJian Shen } 2191374ad291SJian Shen 21929b2f3477SWeihang Li /* Initialize RSS indirect table */ 2193e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 21944093d1a2SGuangbin Huang rss_cfg->rss_indirection_tbl[i] = i % rss_cfg->rss_size; 2195e2cb1decSSalil Mehta 2196e2cb1decSSalil Mehta ret = hclgevf_set_rss_indir_table(hdev); 2197e2cb1decSSalil Mehta if (ret) 2198e2cb1decSSalil Mehta return ret; 2199e2cb1decSSalil Mehta 22004093d1a2SGuangbin Huang return hclgevf_set_rss_tc_mode(hdev, rss_cfg->rss_size); 2201e2cb1decSSalil Mehta } 2202e2cb1decSSalil Mehta 2203e2cb1decSSalil Mehta static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2204e2cb1decSSalil Mehta { 2205e2cb1decSSalil Mehta return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2206e2cb1decSSalil Mehta false); 2207e2cb1decSSalil Mehta } 2208e2cb1decSSalil Mehta 2209ff200099SYunsheng Lin static void hclgevf_flush_link_update(struct hclgevf_dev *hdev) 2210ff200099SYunsheng Lin { 2211ff200099SYunsheng Lin #define HCLGEVF_FLUSH_LINK_TIMEOUT 100000 2212ff200099SYunsheng Lin 2213ff200099SYunsheng Lin unsigned long last = hdev->serv_processed_cnt; 2214ff200099SYunsheng Lin int i = 0; 2215ff200099SYunsheng Lin 2216ff200099SYunsheng Lin while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) && 2217ff200099SYunsheng Lin i++ < HCLGEVF_FLUSH_LINK_TIMEOUT && 2218ff200099SYunsheng Lin last == hdev->serv_processed_cnt) 2219ff200099SYunsheng Lin usleep_range(1, 1); 2220ff200099SYunsheng Lin } 2221ff200099SYunsheng Lin 22228cdb992fSJian Shen static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 22238cdb992fSJian Shen { 22248cdb992fSJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 22258cdb992fSJian Shen 22268cdb992fSJian Shen if (enable) { 2227ff200099SYunsheng Lin hclgevf_task_schedule(hdev, 0); 22288cdb992fSJian Shen } else { 2229b3c3fe8eSYunsheng Lin set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2230ff200099SYunsheng Lin 2231ff200099SYunsheng Lin /* flush memory to make sure DOWN is seen by service task */ 2232ff200099SYunsheng Lin smp_mb__before_atomic(); 2233ff200099SYunsheng Lin hclgevf_flush_link_update(hdev); 22348cdb992fSJian Shen } 22358cdb992fSJian Shen } 22368cdb992fSJian Shen 2237e2cb1decSSalil Mehta static int hclgevf_ae_start(struct hnae3_handle *handle) 2238e2cb1decSSalil Mehta { 2239e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2240e2cb1decSSalil Mehta 2241e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 2242e2cb1decSSalil Mehta 2243e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 2244e2cb1decSSalil Mehta 22459194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 22469194d18bSliuzhongzhu 2247e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2248e2cb1decSSalil Mehta 2249e2cb1decSSalil Mehta return 0; 2250e2cb1decSSalil Mehta } 2251e2cb1decSSalil Mehta 2252e2cb1decSSalil Mehta static void hclgevf_ae_stop(struct hnae3_handle *handle) 2253e2cb1decSSalil Mehta { 2254e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 225539cfbc9cSHuazhong Tan int i; 2256e2cb1decSSalil Mehta 22572f7e4896SFuyun Liang set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 22582f7e4896SFuyun Liang 2259146e92c1SHuazhong Tan if (hdev->reset_type != HNAE3_VF_RESET) 226039cfbc9cSHuazhong Tan for (i = 0; i < handle->kinfo.num_tqps; i++) 2261146e92c1SHuazhong Tan if (hclgevf_reset_tqp(handle, i)) 2262146e92c1SHuazhong Tan break; 226339cfbc9cSHuazhong Tan 2264e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 22658cc6c1f7SFuyun Liang hclgevf_update_link_status(hdev, 0); 2266e2cb1decSSalil Mehta } 2267e2cb1decSSalil Mehta 2268a6d818e3SYunsheng Lin static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2269a6d818e3SYunsheng Lin { 2270d3410018SYufeng Mo #define HCLGEVF_STATE_ALIVE 1 2271d3410018SYufeng Mo #define HCLGEVF_STATE_NOT_ALIVE 0 2272a6d818e3SYunsheng Lin 2273d3410018SYufeng Mo struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2274d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 2275d3410018SYufeng Mo 2276d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_ALIVE, 0); 2277d3410018SYufeng Mo send_msg.data[0] = alive ? HCLGEVF_STATE_ALIVE : 2278d3410018SYufeng Mo HCLGEVF_STATE_NOT_ALIVE; 2279d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2280a6d818e3SYunsheng Lin } 2281a6d818e3SYunsheng Lin 2282a6d818e3SYunsheng Lin static int hclgevf_client_start(struct hnae3_handle *handle) 2283a6d818e3SYunsheng Lin { 2284e233516eSHuazhong Tan int ret; 2285e233516eSHuazhong Tan 2286e233516eSHuazhong Tan ret = hclgevf_set_alive(handle, true); 2287e233516eSHuazhong Tan if (ret) 2288e233516eSHuazhong Tan return ret; 2289a6d818e3SYunsheng Lin 2290e233516eSHuazhong Tan return 0; 2291a6d818e3SYunsheng Lin } 2292a6d818e3SYunsheng Lin 2293a6d818e3SYunsheng Lin static void hclgevf_client_stop(struct hnae3_handle *handle) 2294a6d818e3SYunsheng Lin { 2295a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2296a6d818e3SYunsheng Lin int ret; 2297a6d818e3SYunsheng Lin 2298a6d818e3SYunsheng Lin ret = hclgevf_set_alive(handle, false); 2299a6d818e3SYunsheng Lin if (ret) 2300a6d818e3SYunsheng Lin dev_warn(&hdev->pdev->dev, 2301a6d818e3SYunsheng Lin "%s failed %d\n", __func__, ret); 2302a6d818e3SYunsheng Lin } 2303a6d818e3SYunsheng Lin 2304e2cb1decSSalil Mehta static void hclgevf_state_init(struct hclgevf_dev *hdev) 2305e2cb1decSSalil Mehta { 2306e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2307e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2308d5432455SGuojia Liao clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 2309e2cb1decSSalil Mehta 2310b3c3fe8eSYunsheng Lin INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task); 231135a1e503SSalil Mehta 2312e2cb1decSSalil Mehta mutex_init(&hdev->mbx_resp.mbx_mutex); 2313f28368bbSHuazhong Tan sema_init(&hdev->reset_sem, 1); 2314e2cb1decSSalil Mehta 2315e2cb1decSSalil Mehta /* bring the device down */ 2316e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2317e2cb1decSSalil Mehta } 2318e2cb1decSSalil Mehta 2319e2cb1decSSalil Mehta static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2320e2cb1decSSalil Mehta { 2321e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2322acfc3d55SHuazhong Tan set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2323e2cb1decSSalil Mehta 2324b3c3fe8eSYunsheng Lin if (hdev->service_task.work.func) 2325b3c3fe8eSYunsheng Lin cancel_delayed_work_sync(&hdev->service_task); 2326e2cb1decSSalil Mehta 2327e2cb1decSSalil Mehta mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2328e2cb1decSSalil Mehta } 2329e2cb1decSSalil Mehta 2330e2cb1decSSalil Mehta static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2331e2cb1decSSalil Mehta { 2332e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2333e2cb1decSSalil Mehta int vectors; 2334e2cb1decSSalil Mehta int i; 2335e2cb1decSSalil Mehta 2336580a05f9SYonglong Liu if (hnae3_dev_roce_supported(hdev)) 233707acf909SJian Shen vectors = pci_alloc_irq_vectors(pdev, 233807acf909SJian Shen hdev->roce_base_msix_offset + 1, 233907acf909SJian Shen hdev->num_msi, 234007acf909SJian Shen PCI_IRQ_MSIX); 234107acf909SJian Shen else 2342580a05f9SYonglong Liu vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2343580a05f9SYonglong Liu hdev->num_msi, 2344e2cb1decSSalil Mehta PCI_IRQ_MSI | PCI_IRQ_MSIX); 234507acf909SJian Shen 2346e2cb1decSSalil Mehta if (vectors < 0) { 2347e2cb1decSSalil Mehta dev_err(&pdev->dev, 2348e2cb1decSSalil Mehta "failed(%d) to allocate MSI/MSI-X vectors\n", 2349e2cb1decSSalil Mehta vectors); 2350e2cb1decSSalil Mehta return vectors; 2351e2cb1decSSalil Mehta } 2352e2cb1decSSalil Mehta if (vectors < hdev->num_msi) 2353e2cb1decSSalil Mehta dev_warn(&hdev->pdev->dev, 2354adcf738bSGuojia Liao "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2355e2cb1decSSalil Mehta hdev->num_msi, vectors); 2356e2cb1decSSalil Mehta 2357e2cb1decSSalil Mehta hdev->num_msi = vectors; 2358e2cb1decSSalil Mehta hdev->num_msi_left = vectors; 2359580a05f9SYonglong Liu 2360e2cb1decSSalil Mehta hdev->base_msi_vector = pdev->irq; 236107acf909SJian Shen hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2362e2cb1decSSalil Mehta 2363e2cb1decSSalil Mehta hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2364e2cb1decSSalil Mehta sizeof(u16), GFP_KERNEL); 2365e2cb1decSSalil Mehta if (!hdev->vector_status) { 2366e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2367e2cb1decSSalil Mehta return -ENOMEM; 2368e2cb1decSSalil Mehta } 2369e2cb1decSSalil Mehta 2370e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 2371e2cb1decSSalil Mehta hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2372e2cb1decSSalil Mehta 2373e2cb1decSSalil Mehta hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2374e2cb1decSSalil Mehta sizeof(int), GFP_KERNEL); 2375e2cb1decSSalil Mehta if (!hdev->vector_irq) { 2376862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2377e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2378e2cb1decSSalil Mehta return -ENOMEM; 2379e2cb1decSSalil Mehta } 2380e2cb1decSSalil Mehta 2381e2cb1decSSalil Mehta return 0; 2382e2cb1decSSalil Mehta } 2383e2cb1decSSalil Mehta 2384e2cb1decSSalil Mehta static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2385e2cb1decSSalil Mehta { 2386e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2387e2cb1decSSalil Mehta 2388862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2389862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_irq); 2390e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2391e2cb1decSSalil Mehta } 2392e2cb1decSSalil Mehta 2393e2cb1decSSalil Mehta static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2394e2cb1decSSalil Mehta { 2395cdd332acSGuojia Liao int ret; 2396e2cb1decSSalil Mehta 2397e2cb1decSSalil Mehta hclgevf_get_misc_vector(hdev); 2398e2cb1decSSalil Mehta 2399f97c4d82SYonglong Liu snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 2400f97c4d82SYonglong Liu HCLGEVF_NAME, pci_name(hdev->pdev)); 2401e2cb1decSSalil Mehta ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2402f97c4d82SYonglong Liu 0, hdev->misc_vector.name, hdev); 2403e2cb1decSSalil Mehta if (ret) { 2404e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2405e2cb1decSSalil Mehta hdev->misc_vector.vector_irq); 2406e2cb1decSSalil Mehta return ret; 2407e2cb1decSSalil Mehta } 2408e2cb1decSSalil Mehta 24091819e409SXi Wang hclgevf_clear_event_cause(hdev, 0); 24101819e409SXi Wang 2411e2cb1decSSalil Mehta /* enable misc. vector(vector 0) */ 2412e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2413e2cb1decSSalil Mehta 2414e2cb1decSSalil Mehta return ret; 2415e2cb1decSSalil Mehta } 2416e2cb1decSSalil Mehta 2417e2cb1decSSalil Mehta static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2418e2cb1decSSalil Mehta { 2419e2cb1decSSalil Mehta /* disable misc vector(vector 0) */ 2420e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 24211819e409SXi Wang synchronize_irq(hdev->misc_vector.vector_irq); 2422e2cb1decSSalil Mehta free_irq(hdev->misc_vector.vector_irq, hdev); 2423e2cb1decSSalil Mehta hclgevf_free_vector(hdev, 0); 2424e2cb1decSSalil Mehta } 2425e2cb1decSSalil Mehta 2426bb87be87SYonglong Liu static void hclgevf_info_show(struct hclgevf_dev *hdev) 2427bb87be87SYonglong Liu { 2428bb87be87SYonglong Liu struct device *dev = &hdev->pdev->dev; 2429bb87be87SYonglong Liu 2430bb87be87SYonglong Liu dev_info(dev, "VF info begin:\n"); 2431bb87be87SYonglong Liu 2432adcf738bSGuojia Liao dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 2433adcf738bSGuojia Liao dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 2434adcf738bSGuojia Liao dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 2435adcf738bSGuojia Liao dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 2436adcf738bSGuojia Liao dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 2437adcf738bSGuojia Liao dev_info(dev, "PF media type of this VF: %u\n", 2438bb87be87SYonglong Liu hdev->hw.mac.media_type); 2439bb87be87SYonglong Liu 2440bb87be87SYonglong Liu dev_info(dev, "VF info end.\n"); 2441bb87be87SYonglong Liu } 2442bb87be87SYonglong Liu 24431db58f86SHuazhong Tan static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 24441db58f86SHuazhong Tan struct hnae3_client *client) 24451db58f86SHuazhong Tan { 24461db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 24471db58f86SHuazhong Tan int ret; 24481db58f86SHuazhong Tan 24491db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->nic); 24501db58f86SHuazhong Tan if (ret) 24511db58f86SHuazhong Tan return ret; 24521db58f86SHuazhong Tan 24531db58f86SHuazhong Tan set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 24541db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 24551db58f86SHuazhong Tan 24561db58f86SHuazhong Tan if (netif_msg_drv(&hdev->nic)) 24571db58f86SHuazhong Tan hclgevf_info_show(hdev); 24581db58f86SHuazhong Tan 24591db58f86SHuazhong Tan return 0; 24601db58f86SHuazhong Tan } 24611db58f86SHuazhong Tan 24621db58f86SHuazhong Tan static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 24631db58f86SHuazhong Tan struct hnae3_client *client) 24641db58f86SHuazhong Tan { 24651db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 24661db58f86SHuazhong Tan int ret; 24671db58f86SHuazhong Tan 24681db58f86SHuazhong Tan if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 24691db58f86SHuazhong Tan !hdev->nic_client) 24701db58f86SHuazhong Tan return 0; 24711db58f86SHuazhong Tan 24721db58f86SHuazhong Tan ret = hclgevf_init_roce_base_info(hdev); 24731db58f86SHuazhong Tan if (ret) 24741db58f86SHuazhong Tan return ret; 24751db58f86SHuazhong Tan 24761db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->roce); 24771db58f86SHuazhong Tan if (ret) 24781db58f86SHuazhong Tan return ret; 24791db58f86SHuazhong Tan 24801db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 24811db58f86SHuazhong Tan 24821db58f86SHuazhong Tan return 0; 24831db58f86SHuazhong Tan } 24841db58f86SHuazhong Tan 2485e718a93fSPeng Li static int hclgevf_init_client_instance(struct hnae3_client *client, 2486e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2487e2cb1decSSalil Mehta { 2488e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2489e2cb1decSSalil Mehta int ret; 2490e2cb1decSSalil Mehta 2491e2cb1decSSalil Mehta switch (client->type) { 2492e2cb1decSSalil Mehta case HNAE3_CLIENT_KNIC: 2493e2cb1decSSalil Mehta hdev->nic_client = client; 2494e2cb1decSSalil Mehta hdev->nic.client = client; 2495e2cb1decSSalil Mehta 24961db58f86SHuazhong Tan ret = hclgevf_init_nic_client_instance(ae_dev, client); 2497e2cb1decSSalil Mehta if (ret) 249849dd8054SJian Shen goto clear_nic; 2499e2cb1decSSalil Mehta 25001db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, 25011db58f86SHuazhong Tan hdev->roce_client); 2502e2cb1decSSalil Mehta if (ret) 250349dd8054SJian Shen goto clear_roce; 2504d9f28fc2SJian Shen 2505e2cb1decSSalil Mehta break; 2506e2cb1decSSalil Mehta case HNAE3_CLIENT_ROCE: 2507544a7bcdSLijun Ou if (hnae3_dev_roce_supported(hdev)) { 2508e2cb1decSSalil Mehta hdev->roce_client = client; 2509e2cb1decSSalil Mehta hdev->roce.client = client; 2510544a7bcdSLijun Ou } 2511e2cb1decSSalil Mehta 25121db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, client); 2513e2cb1decSSalil Mehta if (ret) 251449dd8054SJian Shen goto clear_roce; 2515e2cb1decSSalil Mehta 2516fa7a4bd5SJian Shen break; 2517fa7a4bd5SJian Shen default: 2518fa7a4bd5SJian Shen return -EINVAL; 2519e2cb1decSSalil Mehta } 2520e2cb1decSSalil Mehta 2521e2cb1decSSalil Mehta return 0; 252249dd8054SJian Shen 252349dd8054SJian Shen clear_nic: 252449dd8054SJian Shen hdev->nic_client = NULL; 252549dd8054SJian Shen hdev->nic.client = NULL; 252649dd8054SJian Shen return ret; 252749dd8054SJian Shen clear_roce: 252849dd8054SJian Shen hdev->roce_client = NULL; 252949dd8054SJian Shen hdev->roce.client = NULL; 253049dd8054SJian Shen return ret; 2531e2cb1decSSalil Mehta } 2532e2cb1decSSalil Mehta 2533e718a93fSPeng Li static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2534e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2535e2cb1decSSalil Mehta { 2536e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2537e718a93fSPeng Li 2538e2cb1decSSalil Mehta /* un-init roce, if it exists */ 253949dd8054SJian Shen if (hdev->roce_client) { 2540e2cb1decSSalil Mehta hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 254149dd8054SJian Shen hdev->roce_client = NULL; 254249dd8054SJian Shen hdev->roce.client = NULL; 254349dd8054SJian Shen } 2544e2cb1decSSalil Mehta 2545e2cb1decSSalil Mehta /* un-init nic/unic, if this was not called by roce client */ 254649dd8054SJian Shen if (client->ops->uninit_instance && hdev->nic_client && 254749dd8054SJian Shen client->type != HNAE3_CLIENT_ROCE) { 254825d1817cSHuazhong Tan clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 254925d1817cSHuazhong Tan 2550e2cb1decSSalil Mehta client->ops->uninit_instance(&hdev->nic, 0); 255149dd8054SJian Shen hdev->nic_client = NULL; 255249dd8054SJian Shen hdev->nic.client = NULL; 255349dd8054SJian Shen } 2554e2cb1decSSalil Mehta } 2555e2cb1decSSalil Mehta 2556e2cb1decSSalil Mehta static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2557e2cb1decSSalil Mehta { 2558e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2559e2cb1decSSalil Mehta struct hclgevf_hw *hw; 2560e2cb1decSSalil Mehta int ret; 2561e2cb1decSSalil Mehta 2562e2cb1decSSalil Mehta ret = pci_enable_device(pdev); 2563e2cb1decSSalil Mehta if (ret) { 2564e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed to enable PCI device\n"); 25653e249d3bSFuyun Liang return ret; 2566e2cb1decSSalil Mehta } 2567e2cb1decSSalil Mehta 2568e2cb1decSSalil Mehta ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2569e2cb1decSSalil Mehta if (ret) { 2570e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2571e2cb1decSSalil Mehta goto err_disable_device; 2572e2cb1decSSalil Mehta } 2573e2cb1decSSalil Mehta 2574e2cb1decSSalil Mehta ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2575e2cb1decSSalil Mehta if (ret) { 2576e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2577e2cb1decSSalil Mehta goto err_disable_device; 2578e2cb1decSSalil Mehta } 2579e2cb1decSSalil Mehta 2580e2cb1decSSalil Mehta pci_set_master(pdev); 2581e2cb1decSSalil Mehta hw = &hdev->hw; 2582e2cb1decSSalil Mehta hw->hdev = hdev; 25832e1ea493SPeng Li hw->io_base = pci_iomap(pdev, 2, 0); 2584e2cb1decSSalil Mehta if (!hw->io_base) { 2585e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't map configuration register space\n"); 2586e2cb1decSSalil Mehta ret = -ENOMEM; 2587e2cb1decSSalil Mehta goto err_clr_master; 2588e2cb1decSSalil Mehta } 2589e2cb1decSSalil Mehta 2590e2cb1decSSalil Mehta return 0; 2591e2cb1decSSalil Mehta 2592e2cb1decSSalil Mehta err_clr_master: 2593e2cb1decSSalil Mehta pci_clear_master(pdev); 2594e2cb1decSSalil Mehta pci_release_regions(pdev); 2595e2cb1decSSalil Mehta err_disable_device: 2596e2cb1decSSalil Mehta pci_disable_device(pdev); 25973e249d3bSFuyun Liang 2598e2cb1decSSalil Mehta return ret; 2599e2cb1decSSalil Mehta } 2600e2cb1decSSalil Mehta 2601e2cb1decSSalil Mehta static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2602e2cb1decSSalil Mehta { 2603e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2604e2cb1decSSalil Mehta 2605e2cb1decSSalil Mehta pci_iounmap(pdev, hdev->hw.io_base); 2606e2cb1decSSalil Mehta pci_clear_master(pdev); 2607e2cb1decSSalil Mehta pci_release_regions(pdev); 2608e2cb1decSSalil Mehta pci_disable_device(pdev); 2609e2cb1decSSalil Mehta } 2610e2cb1decSSalil Mehta 261107acf909SJian Shen static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 261207acf909SJian Shen { 261307acf909SJian Shen struct hclgevf_query_res_cmd *req; 261407acf909SJian Shen struct hclgevf_desc desc; 261507acf909SJian Shen int ret; 261607acf909SJian Shen 261707acf909SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 261807acf909SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 261907acf909SJian Shen if (ret) { 262007acf909SJian Shen dev_err(&hdev->pdev->dev, 262107acf909SJian Shen "query vf resource failed, ret = %d.\n", ret); 262207acf909SJian Shen return ret; 262307acf909SJian Shen } 262407acf909SJian Shen 262507acf909SJian Shen req = (struct hclgevf_query_res_cmd *)desc.data; 262607acf909SJian Shen 2627580a05f9SYonglong Liu if (hnae3_dev_roce_supported(hdev)) { 262807acf909SJian Shen hdev->roce_base_msix_offset = 262960df7e91SHuazhong Tan hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee), 263007acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_M, 263107acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_S); 263207acf909SJian Shen hdev->num_roce_msix = 263360df7e91SHuazhong Tan hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 263407acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 263507acf909SJian Shen 2636580a05f9SYonglong Liu /* nic's msix numbers is always equals to the roce's. */ 2637580a05f9SYonglong Liu hdev->num_nic_msix = hdev->num_roce_msix; 2638580a05f9SYonglong Liu 263907acf909SJian Shen /* VF should have NIC vectors and Roce vectors, NIC vectors 264007acf909SJian Shen * are queued before Roce vectors. The offset is fixed to 64. 264107acf909SJian Shen */ 264207acf909SJian Shen hdev->num_msi = hdev->num_roce_msix + 264307acf909SJian Shen hdev->roce_base_msix_offset; 264407acf909SJian Shen } else { 264507acf909SJian Shen hdev->num_msi = 264660df7e91SHuazhong Tan hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 264707acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2648580a05f9SYonglong Liu 2649580a05f9SYonglong Liu hdev->num_nic_msix = hdev->num_msi; 2650580a05f9SYonglong Liu } 2651580a05f9SYonglong Liu 2652580a05f9SYonglong Liu if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) { 2653580a05f9SYonglong Liu dev_err(&hdev->pdev->dev, 2654580a05f9SYonglong Liu "Just %u msi resources, not enough for vf(min:2).\n", 2655580a05f9SYonglong Liu hdev->num_nic_msix); 2656580a05f9SYonglong Liu return -EINVAL; 265707acf909SJian Shen } 265807acf909SJian Shen 265907acf909SJian Shen return 0; 266007acf909SJian Shen } 266107acf909SJian Shen 2662862d969aSHuazhong Tan static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2663862d969aSHuazhong Tan { 2664862d969aSHuazhong Tan struct pci_dev *pdev = hdev->pdev; 2665862d969aSHuazhong Tan int ret = 0; 2666862d969aSHuazhong Tan 2667862d969aSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2668862d969aSHuazhong Tan test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2669862d969aSHuazhong Tan hclgevf_misc_irq_uninit(hdev); 2670862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2671862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2672862d969aSHuazhong Tan } 2673862d969aSHuazhong Tan 2674862d969aSHuazhong Tan if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2675862d969aSHuazhong Tan pci_set_master(pdev); 2676862d969aSHuazhong Tan ret = hclgevf_init_msi(hdev); 2677862d969aSHuazhong Tan if (ret) { 2678862d969aSHuazhong Tan dev_err(&pdev->dev, 2679862d969aSHuazhong Tan "failed(%d) to init MSI/MSI-X\n", ret); 2680862d969aSHuazhong Tan return ret; 2681862d969aSHuazhong Tan } 2682862d969aSHuazhong Tan 2683862d969aSHuazhong Tan ret = hclgevf_misc_irq_init(hdev); 2684862d969aSHuazhong Tan if (ret) { 2685862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2686862d969aSHuazhong Tan dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2687862d969aSHuazhong Tan ret); 2688862d969aSHuazhong Tan return ret; 2689862d969aSHuazhong Tan } 2690862d969aSHuazhong Tan 2691862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2692862d969aSHuazhong Tan } 2693862d969aSHuazhong Tan 2694862d969aSHuazhong Tan return ret; 2695862d969aSHuazhong Tan } 2696862d969aSHuazhong Tan 26979c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2698e2cb1decSSalil Mehta { 26997a01c897SSalil Mehta struct pci_dev *pdev = hdev->pdev; 2700e2cb1decSSalil Mehta int ret; 2701e2cb1decSSalil Mehta 2702862d969aSHuazhong Tan ret = hclgevf_pci_reset(hdev); 2703862d969aSHuazhong Tan if (ret) { 2704862d969aSHuazhong Tan dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2705862d969aSHuazhong Tan return ret; 2706862d969aSHuazhong Tan } 2707862d969aSHuazhong Tan 27089c6f7085SHuazhong Tan ret = hclgevf_cmd_init(hdev); 27099c6f7085SHuazhong Tan if (ret) { 27109c6f7085SHuazhong Tan dev_err(&pdev->dev, "cmd failed %d\n", ret); 27119c6f7085SHuazhong Tan return ret; 27127a01c897SSalil Mehta } 2713e2cb1decSSalil Mehta 27149c6f7085SHuazhong Tan ret = hclgevf_rss_init_hw(hdev); 27159c6f7085SHuazhong Tan if (ret) { 27169c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 27179c6f7085SHuazhong Tan "failed(%d) to initialize RSS\n", ret); 27189c6f7085SHuazhong Tan return ret; 27199c6f7085SHuazhong Tan } 27209c6f7085SHuazhong Tan 2721b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2722b26a6feaSPeng Li if (ret) 2723b26a6feaSPeng Li return ret; 2724b26a6feaSPeng Li 27259c6f7085SHuazhong Tan ret = hclgevf_init_vlan_config(hdev); 27269c6f7085SHuazhong Tan if (ret) { 27279c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 27289c6f7085SHuazhong Tan "failed(%d) to initialize VLAN config\n", ret); 27299c6f7085SHuazhong Tan return ret; 27309c6f7085SHuazhong Tan } 27319c6f7085SHuazhong Tan 27329c6f7085SHuazhong Tan dev_info(&hdev->pdev->dev, "Reset done\n"); 27339c6f7085SHuazhong Tan 27349c6f7085SHuazhong Tan return 0; 27359c6f7085SHuazhong Tan } 27369c6f7085SHuazhong Tan 27379c6f7085SHuazhong Tan static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 27389c6f7085SHuazhong Tan { 27399c6f7085SHuazhong Tan struct pci_dev *pdev = hdev->pdev; 27409c6f7085SHuazhong Tan int ret; 27419c6f7085SHuazhong Tan 2742e2cb1decSSalil Mehta ret = hclgevf_pci_init(hdev); 274360df7e91SHuazhong Tan if (ret) 2744e2cb1decSSalil Mehta return ret; 2745e2cb1decSSalil Mehta 27468b0195a3SHuazhong Tan ret = hclgevf_cmd_queue_init(hdev); 274760df7e91SHuazhong Tan if (ret) 27488b0195a3SHuazhong Tan goto err_cmd_queue_init; 27498b0195a3SHuazhong Tan 2750eddf0462SYunsheng Lin ret = hclgevf_cmd_init(hdev); 2751eddf0462SYunsheng Lin if (ret) 2752eddf0462SYunsheng Lin goto err_cmd_init; 2753eddf0462SYunsheng Lin 275407acf909SJian Shen /* Get vf resource */ 275507acf909SJian Shen ret = hclgevf_query_vf_resource(hdev); 275660df7e91SHuazhong Tan if (ret) 27578b0195a3SHuazhong Tan goto err_cmd_init; 275807acf909SJian Shen 275907acf909SJian Shen ret = hclgevf_init_msi(hdev); 276007acf909SJian Shen if (ret) { 276107acf909SJian Shen dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 27628b0195a3SHuazhong Tan goto err_cmd_init; 276307acf909SJian Shen } 276407acf909SJian Shen 276507acf909SJian Shen hclgevf_state_init(hdev); 2766dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 2767afb6afdbSHuazhong Tan hdev->reset_type = HNAE3_NONE_RESET; 276807acf909SJian Shen 2769e2cb1decSSalil Mehta ret = hclgevf_misc_irq_init(hdev); 277060df7e91SHuazhong Tan if (ret) 2771e2cb1decSSalil Mehta goto err_misc_irq_init; 2772e2cb1decSSalil Mehta 2773862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2774862d969aSHuazhong Tan 2775e2cb1decSSalil Mehta ret = hclgevf_configure(hdev); 2776e2cb1decSSalil Mehta if (ret) { 2777e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2778e2cb1decSSalil Mehta goto err_config; 2779e2cb1decSSalil Mehta } 2780e2cb1decSSalil Mehta 2781e2cb1decSSalil Mehta ret = hclgevf_alloc_tqps(hdev); 2782e2cb1decSSalil Mehta if (ret) { 2783e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2784e2cb1decSSalil Mehta goto err_config; 2785e2cb1decSSalil Mehta } 2786e2cb1decSSalil Mehta 2787e2cb1decSSalil Mehta ret = hclgevf_set_handle_info(hdev); 278860df7e91SHuazhong Tan if (ret) 2789e2cb1decSSalil Mehta goto err_config; 2790e2cb1decSSalil Mehta 2791b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2792b26a6feaSPeng Li if (ret) 2793b26a6feaSPeng Li goto err_config; 2794b26a6feaSPeng Li 2795e2cb1decSSalil Mehta /* Initialize RSS for this VF */ 2796e2cb1decSSalil Mehta ret = hclgevf_rss_init_hw(hdev); 2797e2cb1decSSalil Mehta if (ret) { 2798e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2799e2cb1decSSalil Mehta "failed(%d) to initialize RSS\n", ret); 2800e2cb1decSSalil Mehta goto err_config; 2801e2cb1decSSalil Mehta } 2802e2cb1decSSalil Mehta 2803e2cb1decSSalil Mehta ret = hclgevf_init_vlan_config(hdev); 2804e2cb1decSSalil Mehta if (ret) { 2805e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2806e2cb1decSSalil Mehta "failed(%d) to initialize VLAN config\n", ret); 2807e2cb1decSSalil Mehta goto err_config; 2808e2cb1decSSalil Mehta } 2809e2cb1decSSalil Mehta 28100742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 281108d80a4cSHuazhong Tan dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 281208d80a4cSHuazhong Tan HCLGEVF_DRIVER_NAME); 2813e2cb1decSSalil Mehta 2814ff200099SYunsheng Lin hclgevf_task_schedule(hdev, round_jiffies_relative(HZ)); 2815ff200099SYunsheng Lin 2816e2cb1decSSalil Mehta return 0; 2817e2cb1decSSalil Mehta 2818e2cb1decSSalil Mehta err_config: 2819e2cb1decSSalil Mehta hclgevf_misc_irq_uninit(hdev); 2820e2cb1decSSalil Mehta err_misc_irq_init: 2821e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2822e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 282307acf909SJian Shen err_cmd_init: 28248b0195a3SHuazhong Tan hclgevf_cmd_uninit(hdev); 28258b0195a3SHuazhong Tan err_cmd_queue_init: 2826e2cb1decSSalil Mehta hclgevf_pci_uninit(hdev); 2827862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2828e2cb1decSSalil Mehta return ret; 2829e2cb1decSSalil Mehta } 2830e2cb1decSSalil Mehta 28317a01c897SSalil Mehta static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2832e2cb1decSSalil Mehta { 2833d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 2834d3410018SYufeng Mo 2835e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2836862d969aSHuazhong Tan 2837d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_VF_UNINIT, 0); 2838d3410018SYufeng Mo hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 283923b4201dSJian Shen 2840862d969aSHuazhong Tan if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2841eddf0462SYunsheng Lin hclgevf_misc_irq_uninit(hdev); 2842e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 28437a01c897SSalil Mehta } 28447a01c897SSalil Mehta 2845e3338205SHuazhong Tan hclgevf_pci_uninit(hdev); 2846862d969aSHuazhong Tan hclgevf_cmd_uninit(hdev); 2847862d969aSHuazhong Tan } 2848862d969aSHuazhong Tan 28497a01c897SSalil Mehta static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 28507a01c897SSalil Mehta { 28517a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 28527a01c897SSalil Mehta int ret; 28537a01c897SSalil Mehta 28547a01c897SSalil Mehta ret = hclgevf_alloc_hdev(ae_dev); 28557a01c897SSalil Mehta if (ret) { 28567a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device allocation failed\n"); 28577a01c897SSalil Mehta return ret; 28587a01c897SSalil Mehta } 28597a01c897SSalil Mehta 28607a01c897SSalil Mehta ret = hclgevf_init_hdev(ae_dev->priv); 2861a6d818e3SYunsheng Lin if (ret) { 28627a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device initialization failed\n"); 28637a01c897SSalil Mehta return ret; 28647a01c897SSalil Mehta } 28657a01c897SSalil Mehta 2866a6d818e3SYunsheng Lin return 0; 2867a6d818e3SYunsheng Lin } 2868a6d818e3SYunsheng Lin 28697a01c897SSalil Mehta static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 28707a01c897SSalil Mehta { 28717a01c897SSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 28727a01c897SSalil Mehta 28737a01c897SSalil Mehta hclgevf_uninit_hdev(hdev); 2874e2cb1decSSalil Mehta ae_dev->priv = NULL; 2875e2cb1decSSalil Mehta } 2876e2cb1decSSalil Mehta 2877849e4607SPeng Li static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2878849e4607SPeng Li { 2879849e4607SPeng Li struct hnae3_handle *nic = &hdev->nic; 2880849e4607SPeng Li struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2881849e4607SPeng Li 28828be73621SHuazhong Tan return min_t(u32, hdev->rss_size_max, 28838be73621SHuazhong Tan hdev->num_tqps / kinfo->num_tc); 2884849e4607SPeng Li } 2885849e4607SPeng Li 2886849e4607SPeng Li /** 2887849e4607SPeng Li * hclgevf_get_channels - Get the current channels enabled and max supported. 2888849e4607SPeng Li * @handle: hardware information for network interface 2889849e4607SPeng Li * @ch: ethtool channels structure 2890849e4607SPeng Li * 2891849e4607SPeng Li * We don't support separate tx and rx queues as channels. The other count 2892849e4607SPeng Li * represents how many queues are being used for control. max_combined counts 2893849e4607SPeng Li * how many queue pairs we can support. They may not be mapped 1 to 1 with 2894849e4607SPeng Li * q_vectors since we support a lot more queue pairs than q_vectors. 2895849e4607SPeng Li **/ 2896849e4607SPeng Li static void hclgevf_get_channels(struct hnae3_handle *handle, 2897849e4607SPeng Li struct ethtool_channels *ch) 2898849e4607SPeng Li { 2899849e4607SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2900849e4607SPeng Li 2901849e4607SPeng Li ch->max_combined = hclgevf_get_max_channels(hdev); 2902849e4607SPeng Li ch->other_count = 0; 2903849e4607SPeng Li ch->max_other = 0; 29048be73621SHuazhong Tan ch->combined_count = handle->kinfo.rss_size; 2905849e4607SPeng Li } 2906849e4607SPeng Li 2907cc719218SPeng Li static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 29080d43bf45SHuazhong Tan u16 *alloc_tqps, u16 *max_rss_size) 2909cc719218SPeng Li { 2910cc719218SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2911cc719218SPeng Li 29120d43bf45SHuazhong Tan *alloc_tqps = hdev->num_tqps; 2913cc719218SPeng Li *max_rss_size = hdev->rss_size_max; 2914cc719218SPeng Li } 2915cc719218SPeng Li 29164093d1a2SGuangbin Huang static void hclgevf_update_rss_size(struct hnae3_handle *handle, 29174093d1a2SGuangbin Huang u32 new_tqps_num) 29184093d1a2SGuangbin Huang { 29194093d1a2SGuangbin Huang struct hnae3_knic_private_info *kinfo = &handle->kinfo; 29204093d1a2SGuangbin Huang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 29214093d1a2SGuangbin Huang u16 max_rss_size; 29224093d1a2SGuangbin Huang 29234093d1a2SGuangbin Huang kinfo->req_rss_size = new_tqps_num; 29244093d1a2SGuangbin Huang 29254093d1a2SGuangbin Huang max_rss_size = min_t(u16, hdev->rss_size_max, 29264093d1a2SGuangbin Huang hdev->num_tqps / kinfo->num_tc); 29274093d1a2SGuangbin Huang 29284093d1a2SGuangbin Huang /* Use the user's configuration when it is not larger than 29294093d1a2SGuangbin Huang * max_rss_size, otherwise, use the maximum specification value. 29304093d1a2SGuangbin Huang */ 29314093d1a2SGuangbin Huang if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 29324093d1a2SGuangbin Huang kinfo->req_rss_size <= max_rss_size) 29334093d1a2SGuangbin Huang kinfo->rss_size = kinfo->req_rss_size; 29344093d1a2SGuangbin Huang else if (kinfo->rss_size > max_rss_size || 29354093d1a2SGuangbin Huang (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) 29364093d1a2SGuangbin Huang kinfo->rss_size = max_rss_size; 29374093d1a2SGuangbin Huang 29384093d1a2SGuangbin Huang kinfo->num_tqps = kinfo->num_tc * kinfo->rss_size; 29394093d1a2SGuangbin Huang } 29404093d1a2SGuangbin Huang 29414093d1a2SGuangbin Huang static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 29424093d1a2SGuangbin Huang bool rxfh_configured) 29434093d1a2SGuangbin Huang { 29444093d1a2SGuangbin Huang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 29454093d1a2SGuangbin Huang struct hnae3_knic_private_info *kinfo = &handle->kinfo; 29464093d1a2SGuangbin Huang u16 cur_rss_size = kinfo->rss_size; 29474093d1a2SGuangbin Huang u16 cur_tqps = kinfo->num_tqps; 29484093d1a2SGuangbin Huang u32 *rss_indir; 29494093d1a2SGuangbin Huang unsigned int i; 29504093d1a2SGuangbin Huang int ret; 29514093d1a2SGuangbin Huang 29524093d1a2SGuangbin Huang hclgevf_update_rss_size(handle, new_tqps_num); 29534093d1a2SGuangbin Huang 29544093d1a2SGuangbin Huang ret = hclgevf_set_rss_tc_mode(hdev, kinfo->rss_size); 29554093d1a2SGuangbin Huang if (ret) 29564093d1a2SGuangbin Huang return ret; 29574093d1a2SGuangbin Huang 29584093d1a2SGuangbin Huang /* RSS indirection table has been configuared by user */ 29594093d1a2SGuangbin Huang if (rxfh_configured) 29604093d1a2SGuangbin Huang goto out; 29614093d1a2SGuangbin Huang 29624093d1a2SGuangbin Huang /* Reinitializes the rss indirect table according to the new RSS size */ 29634093d1a2SGuangbin Huang rss_indir = kcalloc(HCLGEVF_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL); 29644093d1a2SGuangbin Huang if (!rss_indir) 29654093d1a2SGuangbin Huang return -ENOMEM; 29664093d1a2SGuangbin Huang 29674093d1a2SGuangbin Huang for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 29684093d1a2SGuangbin Huang rss_indir[i] = i % kinfo->rss_size; 29694093d1a2SGuangbin Huang 29704093d1a2SGuangbin Huang ret = hclgevf_set_rss(handle, rss_indir, NULL, 0); 29714093d1a2SGuangbin Huang if (ret) 29724093d1a2SGuangbin Huang dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 29734093d1a2SGuangbin Huang ret); 29744093d1a2SGuangbin Huang 29754093d1a2SGuangbin Huang kfree(rss_indir); 29764093d1a2SGuangbin Huang 29774093d1a2SGuangbin Huang out: 29784093d1a2SGuangbin Huang if (!ret) 29794093d1a2SGuangbin Huang dev_info(&hdev->pdev->dev, 29804093d1a2SGuangbin Huang "Channels changed, rss_size from %u to %u, tqps from %u to %u", 29814093d1a2SGuangbin Huang cur_rss_size, kinfo->rss_size, 29824093d1a2SGuangbin Huang cur_tqps, kinfo->rss_size * kinfo->num_tc); 29834093d1a2SGuangbin Huang 29844093d1a2SGuangbin Huang return ret; 29854093d1a2SGuangbin Huang } 29864093d1a2SGuangbin Huang 2987175ec96bSFuyun Liang static int hclgevf_get_status(struct hnae3_handle *handle) 2988175ec96bSFuyun Liang { 2989175ec96bSFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2990175ec96bSFuyun Liang 2991175ec96bSFuyun Liang return hdev->hw.mac.link; 2992175ec96bSFuyun Liang } 2993175ec96bSFuyun Liang 29944a152de9SFuyun Liang static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 29954a152de9SFuyun Liang u8 *auto_neg, u32 *speed, 29964a152de9SFuyun Liang u8 *duplex) 29974a152de9SFuyun Liang { 29984a152de9SFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 29994a152de9SFuyun Liang 30004a152de9SFuyun Liang if (speed) 30014a152de9SFuyun Liang *speed = hdev->hw.mac.speed; 30024a152de9SFuyun Liang if (duplex) 30034a152de9SFuyun Liang *duplex = hdev->hw.mac.duplex; 30044a152de9SFuyun Liang if (auto_neg) 30054a152de9SFuyun Liang *auto_neg = AUTONEG_DISABLE; 30064a152de9SFuyun Liang } 30074a152de9SFuyun Liang 30084a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 30094a152de9SFuyun Liang u8 duplex) 30104a152de9SFuyun Liang { 30114a152de9SFuyun Liang hdev->hw.mac.speed = speed; 30124a152de9SFuyun Liang hdev->hw.mac.duplex = duplex; 30134a152de9SFuyun Liang } 30144a152de9SFuyun Liang 30151731be4cSYonglong Liu static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 30165c9f6b39SPeng Li { 30175c9f6b39SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 30185c9f6b39SPeng Li 30195c9f6b39SPeng Li return hclgevf_config_gro(hdev, enable); 30205c9f6b39SPeng Li } 30215c9f6b39SPeng Li 302288d10bd6SJian Shen static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 302388d10bd6SJian Shen u8 *module_type) 3024c136b884SPeng Li { 3025c136b884SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 302688d10bd6SJian Shen 3027c136b884SPeng Li if (media_type) 3028c136b884SPeng Li *media_type = hdev->hw.mac.media_type; 302988d10bd6SJian Shen 303088d10bd6SJian Shen if (module_type) 303188d10bd6SJian Shen *module_type = hdev->hw.mac.module_type; 3032c136b884SPeng Li } 3033c136b884SPeng Li 30344d60291bSHuazhong Tan static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 30354d60291bSHuazhong Tan { 30364d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 30374d60291bSHuazhong Tan 3038aa5c4f17SHuazhong Tan return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 30394d60291bSHuazhong Tan } 30404d60291bSHuazhong Tan 30414d60291bSHuazhong Tan static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 30424d60291bSHuazhong Tan { 30434d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 30444d60291bSHuazhong Tan 30454d60291bSHuazhong Tan return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 30464d60291bSHuazhong Tan } 30474d60291bSHuazhong Tan 30484d60291bSHuazhong Tan static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 30494d60291bSHuazhong Tan { 30504d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 30514d60291bSHuazhong Tan 3052c88a6e7dSHuazhong Tan return hdev->rst_stats.hw_rst_done_cnt; 30534d60291bSHuazhong Tan } 30544d60291bSHuazhong Tan 30559194d18bSliuzhongzhu static void hclgevf_get_link_mode(struct hnae3_handle *handle, 30569194d18bSliuzhongzhu unsigned long *supported, 30579194d18bSliuzhongzhu unsigned long *advertising) 30589194d18bSliuzhongzhu { 30599194d18bSliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 30609194d18bSliuzhongzhu 30619194d18bSliuzhongzhu *supported = hdev->hw.mac.supported; 30629194d18bSliuzhongzhu *advertising = hdev->hw.mac.advertising; 30639194d18bSliuzhongzhu } 30649194d18bSliuzhongzhu 30651600c3e5SJian Shen #define MAX_SEPARATE_NUM 4 30661600c3e5SJian Shen #define SEPARATOR_VALUE 0xFFFFFFFF 30671600c3e5SJian Shen #define REG_NUM_PER_LINE 4 30681600c3e5SJian Shen #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 30691600c3e5SJian Shen 30701600c3e5SJian Shen static int hclgevf_get_regs_len(struct hnae3_handle *handle) 30711600c3e5SJian Shen { 30721600c3e5SJian Shen int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 30731600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 30741600c3e5SJian Shen 30751600c3e5SJian Shen cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 30761600c3e5SJian Shen common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 30771600c3e5SJian Shen ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 30781600c3e5SJian Shen tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 30791600c3e5SJian Shen 30801600c3e5SJian Shen return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 30811600c3e5SJian Shen tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 30821600c3e5SJian Shen } 30831600c3e5SJian Shen 30841600c3e5SJian Shen static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 30851600c3e5SJian Shen void *data) 30861600c3e5SJian Shen { 30871600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 30881600c3e5SJian Shen int i, j, reg_um, separator_num; 30891600c3e5SJian Shen u32 *reg = data; 30901600c3e5SJian Shen 30911600c3e5SJian Shen *version = hdev->fw_version; 30921600c3e5SJian Shen 30931600c3e5SJian Shen /* fetching per-VF registers values from VF PCIe register space */ 30941600c3e5SJian Shen reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 30951600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 30961600c3e5SJian Shen for (i = 0; i < reg_um; i++) 30971600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 30981600c3e5SJian Shen for (i = 0; i < separator_num; i++) 30991600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 31001600c3e5SJian Shen 31011600c3e5SJian Shen reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 31021600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 31031600c3e5SJian Shen for (i = 0; i < reg_um; i++) 31041600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 31051600c3e5SJian Shen for (i = 0; i < separator_num; i++) 31061600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 31071600c3e5SJian Shen 31081600c3e5SJian Shen reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 31091600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 31101600c3e5SJian Shen for (j = 0; j < hdev->num_tqps; j++) { 31111600c3e5SJian Shen for (i = 0; i < reg_um; i++) 31121600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 31131600c3e5SJian Shen ring_reg_addr_list[i] + 31141600c3e5SJian Shen 0x200 * j); 31151600c3e5SJian Shen for (i = 0; i < separator_num; i++) 31161600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 31171600c3e5SJian Shen } 31181600c3e5SJian Shen 31191600c3e5SJian Shen reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 31201600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 31211600c3e5SJian Shen for (j = 0; j < hdev->num_msi_used - 1; j++) { 31221600c3e5SJian Shen for (i = 0; i < reg_um; i++) 31231600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 31241600c3e5SJian Shen tqp_intr_reg_addr_list[i] + 31251600c3e5SJian Shen 4 * j); 31261600c3e5SJian Shen for (i = 0; i < separator_num; i++) 31271600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 31281600c3e5SJian Shen } 31291600c3e5SJian Shen } 31301600c3e5SJian Shen 313192f11ea1SJian Shen void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 313292f11ea1SJian Shen u8 *port_base_vlan_info, u8 data_size) 313392f11ea1SJian Shen { 313492f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 3135d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 313692f11ea1SJian Shen 313792f11ea1SJian Shen rtnl_lock(); 313892f11ea1SJian Shen hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 313992f11ea1SJian Shen rtnl_unlock(); 314092f11ea1SJian Shen 314192f11ea1SJian Shen /* send msg to PF and wait update port based vlan info */ 3142d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 3143d3410018SYufeng Mo HCLGE_MBX_PORT_BASE_VLAN_CFG); 3144d3410018SYufeng Mo memcpy(send_msg.data, port_base_vlan_info, data_size); 3145d3410018SYufeng Mo hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 314692f11ea1SJian Shen 314792f11ea1SJian Shen if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 314892f11ea1SJian Shen nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 314992f11ea1SJian Shen else 315092f11ea1SJian Shen nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 315192f11ea1SJian Shen 315292f11ea1SJian Shen rtnl_lock(); 315392f11ea1SJian Shen hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 315492f11ea1SJian Shen rtnl_unlock(); 315592f11ea1SJian Shen } 315692f11ea1SJian Shen 3157e2cb1decSSalil Mehta static const struct hnae3_ae_ops hclgevf_ops = { 3158e2cb1decSSalil Mehta .init_ae_dev = hclgevf_init_ae_dev, 3159e2cb1decSSalil Mehta .uninit_ae_dev = hclgevf_uninit_ae_dev, 31606ff3cf07SHuazhong Tan .flr_prepare = hclgevf_flr_prepare, 31616ff3cf07SHuazhong Tan .flr_done = hclgevf_flr_done, 3162e718a93fSPeng Li .init_client_instance = hclgevf_init_client_instance, 3163e718a93fSPeng Li .uninit_client_instance = hclgevf_uninit_client_instance, 3164e2cb1decSSalil Mehta .start = hclgevf_ae_start, 3165e2cb1decSSalil Mehta .stop = hclgevf_ae_stop, 3166a6d818e3SYunsheng Lin .client_start = hclgevf_client_start, 3167a6d818e3SYunsheng Lin .client_stop = hclgevf_client_stop, 3168e2cb1decSSalil Mehta .map_ring_to_vector = hclgevf_map_ring_to_vector, 3169e2cb1decSSalil Mehta .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 3170e2cb1decSSalil Mehta .get_vector = hclgevf_get_vector, 31710d3e6631SYunsheng Lin .put_vector = hclgevf_put_vector, 3172e2cb1decSSalil Mehta .reset_queue = hclgevf_reset_tqp, 3173e2cb1decSSalil Mehta .get_mac_addr = hclgevf_get_mac_addr, 3174e2cb1decSSalil Mehta .set_mac_addr = hclgevf_set_mac_addr, 3175e2cb1decSSalil Mehta .add_uc_addr = hclgevf_add_uc_addr, 3176e2cb1decSSalil Mehta .rm_uc_addr = hclgevf_rm_uc_addr, 3177e2cb1decSSalil Mehta .add_mc_addr = hclgevf_add_mc_addr, 3178e2cb1decSSalil Mehta .rm_mc_addr = hclgevf_rm_mc_addr, 3179e2cb1decSSalil Mehta .get_stats = hclgevf_get_stats, 3180e2cb1decSSalil Mehta .update_stats = hclgevf_update_stats, 3181e2cb1decSSalil Mehta .get_strings = hclgevf_get_strings, 3182e2cb1decSSalil Mehta .get_sset_count = hclgevf_get_sset_count, 3183e2cb1decSSalil Mehta .get_rss_key_size = hclgevf_get_rss_key_size, 3184e2cb1decSSalil Mehta .get_rss_indir_size = hclgevf_get_rss_indir_size, 3185e2cb1decSSalil Mehta .get_rss = hclgevf_get_rss, 3186e2cb1decSSalil Mehta .set_rss = hclgevf_set_rss, 3187d97b3072SJian Shen .get_rss_tuple = hclgevf_get_rss_tuple, 3188d97b3072SJian Shen .set_rss_tuple = hclgevf_set_rss_tuple, 3189e2cb1decSSalil Mehta .get_tc_size = hclgevf_get_tc_size, 3190e2cb1decSSalil Mehta .get_fw_version = hclgevf_get_fw_version, 3191e2cb1decSSalil Mehta .set_vlan_filter = hclgevf_set_vlan_filter, 3192b2641e2aSYunsheng Lin .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 31936d4c3981SSalil Mehta .reset_event = hclgevf_reset_event, 3194720bd583SHuazhong Tan .set_default_reset_request = hclgevf_set_def_reset_request, 31954093d1a2SGuangbin Huang .set_channels = hclgevf_set_channels, 3196849e4607SPeng Li .get_channels = hclgevf_get_channels, 3197cc719218SPeng Li .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 31981600c3e5SJian Shen .get_regs_len = hclgevf_get_regs_len, 31991600c3e5SJian Shen .get_regs = hclgevf_get_regs, 3200175ec96bSFuyun Liang .get_status = hclgevf_get_status, 32014a152de9SFuyun Liang .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3202c136b884SPeng Li .get_media_type = hclgevf_get_media_type, 32034d60291bSHuazhong Tan .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 32044d60291bSHuazhong Tan .ae_dev_resetting = hclgevf_ae_dev_resetting, 32054d60291bSHuazhong Tan .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 32065c9f6b39SPeng Li .set_gro_en = hclgevf_gro_en, 3207818f1675SYunsheng Lin .set_mtu = hclgevf_set_mtu, 32080c29d191Sliuzhongzhu .get_global_queue_id = hclgevf_get_qid_global, 32098cdb992fSJian Shen .set_timer_task = hclgevf_set_timer_task, 32109194d18bSliuzhongzhu .get_link_mode = hclgevf_get_link_mode, 3211e196ec75SJian Shen .set_promisc_mode = hclgevf_set_promisc_mode, 3212e2cb1decSSalil Mehta }; 3213e2cb1decSSalil Mehta 3214e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf = { 3215e2cb1decSSalil Mehta .ops = &hclgevf_ops, 3216e2cb1decSSalil Mehta .pdev_id_table = ae_algovf_pci_tbl, 3217e2cb1decSSalil Mehta }; 3218e2cb1decSSalil Mehta 3219e2cb1decSSalil Mehta static int hclgevf_init(void) 3220e2cb1decSSalil Mehta { 3221e2cb1decSSalil Mehta pr_info("%s is initializing\n", HCLGEVF_NAME); 3222e2cb1decSSalil Mehta 32230ea68902SYunsheng Lin hclgevf_wq = alloc_workqueue("%s", WQ_MEM_RECLAIM, 0, HCLGEVF_NAME); 32240ea68902SYunsheng Lin if (!hclgevf_wq) { 32250ea68902SYunsheng Lin pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME); 32260ea68902SYunsheng Lin return -ENOMEM; 32270ea68902SYunsheng Lin } 32280ea68902SYunsheng Lin 3229854cf33aSFuyun Liang hnae3_register_ae_algo(&ae_algovf); 3230854cf33aSFuyun Liang 3231854cf33aSFuyun Liang return 0; 3232e2cb1decSSalil Mehta } 3233e2cb1decSSalil Mehta 3234e2cb1decSSalil Mehta static void hclgevf_exit(void) 3235e2cb1decSSalil Mehta { 3236e2cb1decSSalil Mehta hnae3_unregister_ae_algo(&ae_algovf); 32370ea68902SYunsheng Lin destroy_workqueue(hclgevf_wq); 3238e2cb1decSSalil Mehta } 3239e2cb1decSSalil Mehta module_init(hclgevf_init); 3240e2cb1decSSalil Mehta module_exit(hclgevf_exit); 3241e2cb1decSSalil Mehta 3242e2cb1decSSalil Mehta MODULE_LICENSE("GPL"); 3243e2cb1decSSalil Mehta MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3244e2cb1decSSalil Mehta MODULE_DESCRIPTION("HCLGEVF Driver"); 3245e2cb1decSSalil Mehta MODULE_VERSION(HCLGEVF_MOD_VERSION); 3246