1e2cb1decSSalil Mehta // SPDX-License-Identifier: GPL-2.0+ 2e2cb1decSSalil Mehta // Copyright (c) 2016-2017 Hisilicon Limited. 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #include <linux/etherdevice.h> 5aa5c4f17SHuazhong Tan #include <linux/iopoll.h> 66988eb2aSSalil Mehta #include <net/rtnetlink.h> 7e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 8e2cb1decSSalil Mehta #include "hclgevf_main.h" 9e2cb1decSSalil Mehta #include "hclge_mbx.h" 10e2cb1decSSalil Mehta #include "hnae3.h" 11*cd624299SYufeng Mo #include "hclgevf_devlink.h" 12e2cb1decSSalil Mehta 13e2cb1decSSalil Mehta #define HCLGEVF_NAME "hclgevf" 14e2cb1decSSalil Mehta 15bbe6540eSHuazhong Tan #define HCLGEVF_RESET_MAX_FAIL_CNT 5 16bbe6540eSHuazhong Tan 179c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 185e7414cdSJian Shen static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 195e7414cdSJian Shen unsigned long delay); 205e7414cdSJian Shen 21e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf; 22e2cb1decSSalil Mehta 230ea68902SYunsheng Lin static struct workqueue_struct *hclgevf_wq; 240ea68902SYunsheng Lin 25e2cb1decSSalil Mehta static const struct pci_device_id ae_algovf_pci_tbl[] = { 26c155e22bSGuangbin Huang {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0}, 27c155e22bSGuangbin Huang {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 28c155e22bSGuangbin Huang HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 29e2cb1decSSalil Mehta /* required last entry */ 30e2cb1decSSalil Mehta {0, } 31e2cb1decSSalil Mehta }; 32e2cb1decSSalil Mehta 33472d7eceSJian Shen static const u8 hclgevf_hash_key[] = { 34472d7eceSJian Shen 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 35472d7eceSJian Shen 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 36472d7eceSJian Shen 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 37472d7eceSJian Shen 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 38472d7eceSJian Shen 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 39472d7eceSJian Shen }; 40472d7eceSJian Shen 412f550a46SYunsheng Lin MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 422f550a46SYunsheng Lin 431600c3e5SJian Shen static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 441600c3e5SJian Shen HCLGEVF_CMDQ_TX_ADDR_H_REG, 451600c3e5SJian Shen HCLGEVF_CMDQ_TX_DEPTH_REG, 461600c3e5SJian Shen HCLGEVF_CMDQ_TX_TAIL_REG, 471600c3e5SJian Shen HCLGEVF_CMDQ_TX_HEAD_REG, 481600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_L_REG, 491600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_H_REG, 501600c3e5SJian Shen HCLGEVF_CMDQ_RX_DEPTH_REG, 511600c3e5SJian Shen HCLGEVF_CMDQ_RX_TAIL_REG, 521600c3e5SJian Shen HCLGEVF_CMDQ_RX_HEAD_REG, 531600c3e5SJian Shen HCLGEVF_VECTOR0_CMDQ_SRC_REG, 549cee2e8dSHuazhong Tan HCLGEVF_VECTOR0_CMDQ_STATE_REG, 551600c3e5SJian Shen HCLGEVF_CMDQ_INTR_EN_REG, 561600c3e5SJian Shen HCLGEVF_CMDQ_INTR_GEN_REG}; 571600c3e5SJian Shen 581600c3e5SJian Shen static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 591600c3e5SJian Shen HCLGEVF_RST_ING, 601600c3e5SJian Shen HCLGEVF_GRO_EN_REG}; 611600c3e5SJian Shen 621600c3e5SJian Shen static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 631600c3e5SJian Shen HCLGEVF_RING_RX_ADDR_H_REG, 641600c3e5SJian Shen HCLGEVF_RING_RX_BD_NUM_REG, 651600c3e5SJian Shen HCLGEVF_RING_RX_BD_LENGTH_REG, 661600c3e5SJian Shen HCLGEVF_RING_RX_MERGE_EN_REG, 671600c3e5SJian Shen HCLGEVF_RING_RX_TAIL_REG, 681600c3e5SJian Shen HCLGEVF_RING_RX_HEAD_REG, 691600c3e5SJian Shen HCLGEVF_RING_RX_FBD_NUM_REG, 701600c3e5SJian Shen HCLGEVF_RING_RX_OFFSET_REG, 711600c3e5SJian Shen HCLGEVF_RING_RX_FBD_OFFSET_REG, 721600c3e5SJian Shen HCLGEVF_RING_RX_STASH_REG, 731600c3e5SJian Shen HCLGEVF_RING_RX_BD_ERR_REG, 741600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_L_REG, 751600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_H_REG, 761600c3e5SJian Shen HCLGEVF_RING_TX_BD_NUM_REG, 771600c3e5SJian Shen HCLGEVF_RING_TX_PRIORITY_REG, 781600c3e5SJian Shen HCLGEVF_RING_TX_TC_REG, 791600c3e5SJian Shen HCLGEVF_RING_TX_MERGE_EN_REG, 801600c3e5SJian Shen HCLGEVF_RING_TX_TAIL_REG, 811600c3e5SJian Shen HCLGEVF_RING_TX_HEAD_REG, 821600c3e5SJian Shen HCLGEVF_RING_TX_FBD_NUM_REG, 831600c3e5SJian Shen HCLGEVF_RING_TX_OFFSET_REG, 841600c3e5SJian Shen HCLGEVF_RING_TX_EBD_NUM_REG, 851600c3e5SJian Shen HCLGEVF_RING_TX_EBD_OFFSET_REG, 861600c3e5SJian Shen HCLGEVF_RING_TX_BD_ERR_REG, 871600c3e5SJian Shen HCLGEVF_RING_EN_REG}; 881600c3e5SJian Shen 891600c3e5SJian Shen static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 901600c3e5SJian Shen HCLGEVF_TQP_INTR_GL0_REG, 911600c3e5SJian Shen HCLGEVF_TQP_INTR_GL1_REG, 921600c3e5SJian Shen HCLGEVF_TQP_INTR_GL2_REG, 931600c3e5SJian Shen HCLGEVF_TQP_INTR_RL_REG}; 941600c3e5SJian Shen 959b2f3477SWeihang Li static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 96e2cb1decSSalil Mehta { 97eed9535fSPeng Li if (!handle->client) 98eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, nic); 99eed9535fSPeng Li else if (handle->client->type == HNAE3_CLIENT_ROCE) 100eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, roce); 101eed9535fSPeng Li else 102e2cb1decSSalil Mehta return container_of(handle, struct hclgevf_dev, nic); 103e2cb1decSSalil Mehta } 104e2cb1decSSalil Mehta 105e2cb1decSSalil Mehta static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 106e2cb1decSSalil Mehta { 107b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 108e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 109e2cb1decSSalil Mehta struct hclgevf_desc desc; 110e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 111e2cb1decSSalil Mehta int status; 112e2cb1decSSalil Mehta int i; 113e2cb1decSSalil Mehta 114b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 115b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 116e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 117e2cb1decSSalil Mehta HCLGEVF_OPC_QUERY_RX_STATUS, 118e2cb1decSSalil Mehta true); 119e2cb1decSSalil Mehta 120e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 121e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 122e2cb1decSSalil Mehta if (status) { 123e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 124e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 125e2cb1decSSalil Mehta status, i); 126e2cb1decSSalil Mehta return status; 127e2cb1decSSalil Mehta } 128e2cb1decSSalil Mehta tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 129cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 130e2cb1decSSalil Mehta 131e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 132e2cb1decSSalil Mehta true); 133e2cb1decSSalil Mehta 134e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 135e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 136e2cb1decSSalil Mehta if (status) { 137e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 138e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 139e2cb1decSSalil Mehta status, i); 140e2cb1decSSalil Mehta return status; 141e2cb1decSSalil Mehta } 142e2cb1decSSalil Mehta tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 143cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 144e2cb1decSSalil Mehta } 145e2cb1decSSalil Mehta 146e2cb1decSSalil Mehta return 0; 147e2cb1decSSalil Mehta } 148e2cb1decSSalil Mehta 149e2cb1decSSalil Mehta static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 150e2cb1decSSalil Mehta { 151e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo = &handle->kinfo; 152e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 153e2cb1decSSalil Mehta u64 *buff = data; 154e2cb1decSSalil Mehta int i; 155e2cb1decSSalil Mehta 156b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 157b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 158e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 159e2cb1decSSalil Mehta } 160e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 161b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 162e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 163e2cb1decSSalil Mehta } 164e2cb1decSSalil Mehta 165e2cb1decSSalil Mehta return buff; 166e2cb1decSSalil Mehta } 167e2cb1decSSalil Mehta 168e2cb1decSSalil Mehta static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 169e2cb1decSSalil Mehta { 170b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 171e2cb1decSSalil Mehta 172b4f1d303SJian Shen return kinfo->num_tqps * 2; 173e2cb1decSSalil Mehta } 174e2cb1decSSalil Mehta 175e2cb1decSSalil Mehta static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 176e2cb1decSSalil Mehta { 177b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 178e2cb1decSSalil Mehta u8 *buff = data; 1799d8d5a36SYufeng Mo int i; 180e2cb1decSSalil Mehta 181b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 182b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 183e2cb1decSSalil Mehta struct hclgevf_tqp, q); 184c5aaf176SJiaran Zhang snprintf(buff, ETH_GSTRING_LEN, "txq%u_pktnum_rcd", 185e2cb1decSSalil Mehta tqp->index); 186e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 187e2cb1decSSalil Mehta } 188e2cb1decSSalil Mehta 189b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 190b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 191e2cb1decSSalil Mehta struct hclgevf_tqp, q); 192c5aaf176SJiaran Zhang snprintf(buff, ETH_GSTRING_LEN, "rxq%u_pktnum_rcd", 193e2cb1decSSalil Mehta tqp->index); 194e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 195e2cb1decSSalil Mehta } 196e2cb1decSSalil Mehta 197e2cb1decSSalil Mehta return buff; 198e2cb1decSSalil Mehta } 199e2cb1decSSalil Mehta 200e2cb1decSSalil Mehta static void hclgevf_update_stats(struct hnae3_handle *handle, 201e2cb1decSSalil Mehta struct net_device_stats *net_stats) 202e2cb1decSSalil Mehta { 203e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 204e2cb1decSSalil Mehta int status; 205e2cb1decSSalil Mehta 206e2cb1decSSalil Mehta status = hclgevf_tqps_update_stats(handle); 207e2cb1decSSalil Mehta if (status) 208e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 209e2cb1decSSalil Mehta "VF update of TQPS stats fail, status = %d.\n", 210e2cb1decSSalil Mehta status); 211e2cb1decSSalil Mehta } 212e2cb1decSSalil Mehta 213e2cb1decSSalil Mehta static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 214e2cb1decSSalil Mehta { 215e2cb1decSSalil Mehta if (strset == ETH_SS_TEST) 216e2cb1decSSalil Mehta return -EOPNOTSUPP; 217e2cb1decSSalil Mehta else if (strset == ETH_SS_STATS) 218e2cb1decSSalil Mehta return hclgevf_tqps_get_sset_count(handle, strset); 219e2cb1decSSalil Mehta 220e2cb1decSSalil Mehta return 0; 221e2cb1decSSalil Mehta } 222e2cb1decSSalil Mehta 223e2cb1decSSalil Mehta static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 224e2cb1decSSalil Mehta u8 *data) 225e2cb1decSSalil Mehta { 226e2cb1decSSalil Mehta u8 *p = (char *)data; 227e2cb1decSSalil Mehta 228e2cb1decSSalil Mehta if (strset == ETH_SS_STATS) 229e2cb1decSSalil Mehta p = hclgevf_tqps_get_strings(handle, p); 230e2cb1decSSalil Mehta } 231e2cb1decSSalil Mehta 232e2cb1decSSalil Mehta static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 233e2cb1decSSalil Mehta { 234e2cb1decSSalil Mehta hclgevf_tqps_get_stats(handle, data); 235e2cb1decSSalil Mehta } 236e2cb1decSSalil Mehta 237d3410018SYufeng Mo static void hclgevf_build_send_msg(struct hclge_vf_to_pf_msg *msg, u8 code, 238d3410018SYufeng Mo u8 subcode) 239d3410018SYufeng Mo { 240d3410018SYufeng Mo if (msg) { 241d3410018SYufeng Mo memset(msg, 0, sizeof(struct hclge_vf_to_pf_msg)); 242d3410018SYufeng Mo msg->code = code; 243d3410018SYufeng Mo msg->subcode = subcode; 244d3410018SYufeng Mo } 245d3410018SYufeng Mo } 246d3410018SYufeng Mo 24732e6d104SJian Shen static int hclgevf_get_basic_info(struct hclgevf_dev *hdev) 248e2cb1decSSalil Mehta { 24932e6d104SJian Shen struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 25032e6d104SJian Shen u8 resp_msg[HCLGE_MBX_MAX_RESP_DATA_SIZE]; 25132e6d104SJian Shen struct hclge_basic_info *basic_info; 252d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 25332e6d104SJian Shen unsigned long caps; 254e2cb1decSSalil Mehta int status; 255e2cb1decSSalil Mehta 25632e6d104SJian Shen hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_BASIC_INFO, 0); 25732e6d104SJian Shen status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 258d3410018SYufeng Mo sizeof(resp_msg)); 259e2cb1decSSalil Mehta if (status) { 260e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 26132e6d104SJian Shen "failed to get basic info from pf, ret = %d", status); 262e2cb1decSSalil Mehta return status; 263e2cb1decSSalil Mehta } 264e2cb1decSSalil Mehta 26532e6d104SJian Shen basic_info = (struct hclge_basic_info *)resp_msg; 26632e6d104SJian Shen 26732e6d104SJian Shen hdev->hw_tc_map = basic_info->hw_tc_map; 26832e6d104SJian Shen hdev->mbx_api_version = basic_info->mbx_api_version; 26932e6d104SJian Shen caps = basic_info->pf_caps; 27032e6d104SJian Shen if (test_bit(HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B, &caps)) 27132e6d104SJian Shen set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps); 272e2cb1decSSalil Mehta 273e2cb1decSSalil Mehta return 0; 274e2cb1decSSalil Mehta } 275e2cb1decSSalil Mehta 27692f11ea1SJian Shen static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 27792f11ea1SJian Shen { 27892f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 279d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 28092f11ea1SJian Shen u8 resp_msg; 28192f11ea1SJian Shen int ret; 28292f11ea1SJian Shen 283d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 284d3410018SYufeng Mo HCLGE_MBX_GET_PORT_BASE_VLAN_STATE); 285d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg, 286d3410018SYufeng Mo sizeof(u8)); 28792f11ea1SJian Shen if (ret) { 28892f11ea1SJian Shen dev_err(&hdev->pdev->dev, 28992f11ea1SJian Shen "VF request to get port based vlan state failed %d", 29092f11ea1SJian Shen ret); 29192f11ea1SJian Shen return ret; 29292f11ea1SJian Shen } 29392f11ea1SJian Shen 29492f11ea1SJian Shen nic->port_base_vlan_state = resp_msg; 29592f11ea1SJian Shen 29692f11ea1SJian Shen return 0; 29792f11ea1SJian Shen } 29892f11ea1SJian Shen 2996cee6fc3SJian Shen static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 300e2cb1decSSalil Mehta { 301c0425944SPeng Li #define HCLGEVF_TQPS_RSS_INFO_LEN 6 302d3410018SYufeng Mo #define HCLGEVF_TQPS_ALLOC_OFFSET 0 303d3410018SYufeng Mo #define HCLGEVF_TQPS_RSS_SIZE_OFFSET 2 304d3410018SYufeng Mo #define HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET 4 305d3410018SYufeng Mo 306e2cb1decSSalil Mehta u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 307d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 308e2cb1decSSalil Mehta int status; 309e2cb1decSSalil Mehta 310d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QINFO, 0); 311d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 312e2cb1decSSalil Mehta HCLGEVF_TQPS_RSS_INFO_LEN); 313e2cb1decSSalil Mehta if (status) { 314e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 315e2cb1decSSalil Mehta "VF request to get tqp info from PF failed %d", 316e2cb1decSSalil Mehta status); 317e2cb1decSSalil Mehta return status; 318e2cb1decSSalil Mehta } 319e2cb1decSSalil Mehta 320d3410018SYufeng Mo memcpy(&hdev->num_tqps, &resp_msg[HCLGEVF_TQPS_ALLOC_OFFSET], 321d3410018SYufeng Mo sizeof(u16)); 322d3410018SYufeng Mo memcpy(&hdev->rss_size_max, &resp_msg[HCLGEVF_TQPS_RSS_SIZE_OFFSET], 323d3410018SYufeng Mo sizeof(u16)); 324d3410018SYufeng Mo memcpy(&hdev->rx_buf_len, &resp_msg[HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET], 325d3410018SYufeng Mo sizeof(u16)); 326c0425944SPeng Li 327c0425944SPeng Li return 0; 328c0425944SPeng Li } 329c0425944SPeng Li 330c0425944SPeng Li static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 331c0425944SPeng Li { 332c0425944SPeng Li #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 333d3410018SYufeng Mo #define HCLGEVF_TQPS_NUM_TX_DESC_OFFSET 0 334d3410018SYufeng Mo #define HCLGEVF_TQPS_NUM_RX_DESC_OFFSET 2 335d3410018SYufeng Mo 336c0425944SPeng Li u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 337d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 338c0425944SPeng Li int ret; 339c0425944SPeng Li 340d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QDEPTH, 0); 341d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 342c0425944SPeng Li HCLGEVF_TQPS_DEPTH_INFO_LEN); 343c0425944SPeng Li if (ret) { 344c0425944SPeng Li dev_err(&hdev->pdev->dev, 345c0425944SPeng Li "VF request to get tqp depth info from PF failed %d", 346c0425944SPeng Li ret); 347c0425944SPeng Li return ret; 348c0425944SPeng Li } 349c0425944SPeng Li 350d3410018SYufeng Mo memcpy(&hdev->num_tx_desc, &resp_msg[HCLGEVF_TQPS_NUM_TX_DESC_OFFSET], 351d3410018SYufeng Mo sizeof(u16)); 352d3410018SYufeng Mo memcpy(&hdev->num_rx_desc, &resp_msg[HCLGEVF_TQPS_NUM_RX_DESC_OFFSET], 353d3410018SYufeng Mo sizeof(u16)); 354e2cb1decSSalil Mehta 355e2cb1decSSalil Mehta return 0; 356e2cb1decSSalil Mehta } 357e2cb1decSSalil Mehta 3580c29d191Sliuzhongzhu static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 3590c29d191Sliuzhongzhu { 3600c29d191Sliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 361d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 3620c29d191Sliuzhongzhu u16 qid_in_pf = 0; 363d3410018SYufeng Mo u8 resp_data[2]; 3640c29d191Sliuzhongzhu int ret; 3650c29d191Sliuzhongzhu 366d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QID_IN_PF, 0); 367d3410018SYufeng Mo memcpy(send_msg.data, &queue_id, sizeof(queue_id)); 368d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_data, 36963cbf7a9SYufeng Mo sizeof(resp_data)); 3700c29d191Sliuzhongzhu if (!ret) 3710c29d191Sliuzhongzhu qid_in_pf = *(u16 *)resp_data; 3720c29d191Sliuzhongzhu 3730c29d191Sliuzhongzhu return qid_in_pf; 3740c29d191Sliuzhongzhu } 3750c29d191Sliuzhongzhu 3769c3e7130Sliuzhongzhu static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 3779c3e7130Sliuzhongzhu { 378d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 37988d10bd6SJian Shen u8 resp_msg[2]; 3809c3e7130Sliuzhongzhu int ret; 3819c3e7130Sliuzhongzhu 382d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MEDIA_TYPE, 0); 383d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 384d3410018SYufeng Mo sizeof(resp_msg)); 3859c3e7130Sliuzhongzhu if (ret) { 3869c3e7130Sliuzhongzhu dev_err(&hdev->pdev->dev, 3879c3e7130Sliuzhongzhu "VF request to get the pf port media type failed %d", 3889c3e7130Sliuzhongzhu ret); 3899c3e7130Sliuzhongzhu return ret; 3909c3e7130Sliuzhongzhu } 3919c3e7130Sliuzhongzhu 39288d10bd6SJian Shen hdev->hw.mac.media_type = resp_msg[0]; 39388d10bd6SJian Shen hdev->hw.mac.module_type = resp_msg[1]; 3949c3e7130Sliuzhongzhu 3959c3e7130Sliuzhongzhu return 0; 3969c3e7130Sliuzhongzhu } 3979c3e7130Sliuzhongzhu 398e2cb1decSSalil Mehta static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 399e2cb1decSSalil Mehta { 400e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 401e2cb1decSSalil Mehta int i; 402e2cb1decSSalil Mehta 403e2cb1decSSalil Mehta hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 404e2cb1decSSalil Mehta sizeof(struct hclgevf_tqp), GFP_KERNEL); 405e2cb1decSSalil Mehta if (!hdev->htqp) 406e2cb1decSSalil Mehta return -ENOMEM; 407e2cb1decSSalil Mehta 408e2cb1decSSalil Mehta tqp = hdev->htqp; 409e2cb1decSSalil Mehta 410e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 411e2cb1decSSalil Mehta tqp->dev = &hdev->pdev->dev; 412e2cb1decSSalil Mehta tqp->index = i; 413e2cb1decSSalil Mehta 414e2cb1decSSalil Mehta tqp->q.ae_algo = &ae_algovf; 415e2cb1decSSalil Mehta tqp->q.buf_size = hdev->rx_buf_len; 416c0425944SPeng Li tqp->q.tx_desc_num = hdev->num_tx_desc; 417c0425944SPeng Li tqp->q.rx_desc_num = hdev->num_rx_desc; 4189a5ef4aaSYonglong Liu 4199a5ef4aaSYonglong Liu /* need an extended offset to configure queues >= 4209a5ef4aaSYonglong Liu * HCLGEVF_TQP_MAX_SIZE_DEV_V2. 4219a5ef4aaSYonglong Liu */ 4229a5ef4aaSYonglong Liu if (i < HCLGEVF_TQP_MAX_SIZE_DEV_V2) 4239a5ef4aaSYonglong Liu tqp->q.io_base = hdev->hw.io_base + 4249a5ef4aaSYonglong Liu HCLGEVF_TQP_REG_OFFSET + 425e2cb1decSSalil Mehta i * HCLGEVF_TQP_REG_SIZE; 4269a5ef4aaSYonglong Liu else 4279a5ef4aaSYonglong Liu tqp->q.io_base = hdev->hw.io_base + 4289a5ef4aaSYonglong Liu HCLGEVF_TQP_REG_OFFSET + 4299a5ef4aaSYonglong Liu HCLGEVF_TQP_EXT_REG_OFFSET + 4309a5ef4aaSYonglong Liu (i - HCLGEVF_TQP_MAX_SIZE_DEV_V2) * 4319a5ef4aaSYonglong Liu HCLGEVF_TQP_REG_SIZE; 432e2cb1decSSalil Mehta 433e2cb1decSSalil Mehta tqp++; 434e2cb1decSSalil Mehta } 435e2cb1decSSalil Mehta 436e2cb1decSSalil Mehta return 0; 437e2cb1decSSalil Mehta } 438e2cb1decSSalil Mehta 439e2cb1decSSalil Mehta static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 440e2cb1decSSalil Mehta { 441e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 442e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo; 443e2cb1decSSalil Mehta u16 new_tqps = hdev->num_tqps; 444ebaf1908SWeihang Li unsigned int i; 44535244430SJian Shen u8 num_tc = 0; 446e2cb1decSSalil Mehta 447e2cb1decSSalil Mehta kinfo = &nic->kinfo; 448c0425944SPeng Li kinfo->num_tx_desc = hdev->num_tx_desc; 449c0425944SPeng Li kinfo->num_rx_desc = hdev->num_rx_desc; 450e2cb1decSSalil Mehta kinfo->rx_buf_len = hdev->rx_buf_len; 451e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 452e2cb1decSSalil Mehta if (hdev->hw_tc_map & BIT(i)) 45335244430SJian Shen num_tc++; 454e2cb1decSSalil Mehta 45535244430SJian Shen num_tc = num_tc ? num_tc : 1; 45635244430SJian Shen kinfo->tc_info.num_tc = num_tc; 45735244430SJian Shen kinfo->rss_size = min_t(u16, hdev->rss_size_max, new_tqps / num_tc); 45835244430SJian Shen new_tqps = kinfo->rss_size * num_tc; 459e2cb1decSSalil Mehta kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 460e2cb1decSSalil Mehta 461e2cb1decSSalil Mehta kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 462e2cb1decSSalil Mehta sizeof(struct hnae3_queue *), GFP_KERNEL); 463e2cb1decSSalil Mehta if (!kinfo->tqp) 464e2cb1decSSalil Mehta return -ENOMEM; 465e2cb1decSSalil Mehta 466e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 467e2cb1decSSalil Mehta hdev->htqp[i].q.handle = &hdev->nic; 468e2cb1decSSalil Mehta hdev->htqp[i].q.tqp_index = i; 469e2cb1decSSalil Mehta kinfo->tqp[i] = &hdev->htqp[i].q; 470e2cb1decSSalil Mehta } 471e2cb1decSSalil Mehta 472580a05f9SYonglong Liu /* after init the max rss_size and tqps, adjust the default tqp numbers 473580a05f9SYonglong Liu * and rss size with the actual vector numbers 474580a05f9SYonglong Liu */ 475580a05f9SYonglong Liu kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps); 47635244430SJian Shen kinfo->rss_size = min_t(u16, kinfo->num_tqps / num_tc, 477580a05f9SYonglong Liu kinfo->rss_size); 478580a05f9SYonglong Liu 479e2cb1decSSalil Mehta return 0; 480e2cb1decSSalil Mehta } 481e2cb1decSSalil Mehta 482e2cb1decSSalil Mehta static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 483e2cb1decSSalil Mehta { 484d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 485e2cb1decSSalil Mehta int status; 486e2cb1decSSalil Mehta 487d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_STATUS, 0); 488d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 489e2cb1decSSalil Mehta if (status) 490e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 491e2cb1decSSalil Mehta "VF failed to fetch link status(%d) from PF", status); 492e2cb1decSSalil Mehta } 493e2cb1decSSalil Mehta 494e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 495e2cb1decSSalil Mehta { 49645e92b7eSPeng Li struct hnae3_handle *rhandle = &hdev->roce; 497e2cb1decSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 49845e92b7eSPeng Li struct hnae3_client *rclient; 499e2cb1decSSalil Mehta struct hnae3_client *client; 500e2cb1decSSalil Mehta 501ff200099SYunsheng Lin if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state)) 502ff200099SYunsheng Lin return; 503ff200099SYunsheng Lin 504e2cb1decSSalil Mehta client = handle->client; 50545e92b7eSPeng Li rclient = hdev->roce_client; 506e2cb1decSSalil Mehta 507582d37bbSPeng Li link_state = 508582d37bbSPeng Li test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 509e2cb1decSSalil Mehta if (link_state != hdev->hw.mac.link) { 510e2cb1decSSalil Mehta client->ops->link_status_change(handle, !!link_state); 51145e92b7eSPeng Li if (rclient && rclient->ops->link_status_change) 51245e92b7eSPeng Li rclient->ops->link_status_change(rhandle, !!link_state); 513e2cb1decSSalil Mehta hdev->hw.mac.link = link_state; 514e2cb1decSSalil Mehta } 515ff200099SYunsheng Lin 516ff200099SYunsheng Lin clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state); 517e2cb1decSSalil Mehta } 518e2cb1decSSalil Mehta 519538abaf3SYueHaibing static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 5209194d18bSliuzhongzhu { 5219194d18bSliuzhongzhu #define HCLGEVF_ADVERTISING 0 5229194d18bSliuzhongzhu #define HCLGEVF_SUPPORTED 1 5239194d18bSliuzhongzhu 524d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 525d3410018SYufeng Mo 526d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_MODE, 0); 527d3410018SYufeng Mo send_msg.data[0] = HCLGEVF_ADVERTISING; 528d3410018SYufeng Mo hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 529d3410018SYufeng Mo send_msg.data[0] = HCLGEVF_SUPPORTED; 530d3410018SYufeng Mo hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 5319194d18bSliuzhongzhu } 5329194d18bSliuzhongzhu 533e2cb1decSSalil Mehta static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 534e2cb1decSSalil Mehta { 535e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 536e2cb1decSSalil Mehta int ret; 537e2cb1decSSalil Mehta 538e2cb1decSSalil Mehta nic->ae_algo = &ae_algovf; 539e2cb1decSSalil Mehta nic->pdev = hdev->pdev; 540e2cb1decSSalil Mehta nic->numa_node_mask = hdev->numa_node_mask; 541424eb834SSalil Mehta nic->flags |= HNAE3_SUPPORT_VF; 542e2cb1decSSalil Mehta 543e2cb1decSSalil Mehta ret = hclgevf_knic_setup(hdev); 544e2cb1decSSalil Mehta if (ret) 545e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 546e2cb1decSSalil Mehta ret); 547e2cb1decSSalil Mehta return ret; 548e2cb1decSSalil Mehta } 549e2cb1decSSalil Mehta 550e2cb1decSSalil Mehta static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 551e2cb1decSSalil Mehta { 55236cbbdf6SPeng Li if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 55336cbbdf6SPeng Li dev_warn(&hdev->pdev->dev, 55436cbbdf6SPeng Li "vector(vector_id %d) has been freed.\n", vector_id); 55536cbbdf6SPeng Li return; 55636cbbdf6SPeng Li } 55736cbbdf6SPeng Li 558e2cb1decSSalil Mehta hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 559e2cb1decSSalil Mehta hdev->num_msi_left += 1; 560e2cb1decSSalil Mehta hdev->num_msi_used -= 1; 561e2cb1decSSalil Mehta } 562e2cb1decSSalil Mehta 563e2cb1decSSalil Mehta static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 564e2cb1decSSalil Mehta struct hnae3_vector_info *vector_info) 565e2cb1decSSalil Mehta { 566e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 567e2cb1decSSalil Mehta struct hnae3_vector_info *vector = vector_info; 568e2cb1decSSalil Mehta int alloc = 0; 569e2cb1decSSalil Mehta int i, j; 570e2cb1decSSalil Mehta 571580a05f9SYonglong Liu vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num); 572e2cb1decSSalil Mehta vector_num = min(hdev->num_msi_left, vector_num); 573e2cb1decSSalil Mehta 574e2cb1decSSalil Mehta for (j = 0; j < vector_num; j++) { 575e2cb1decSSalil Mehta for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 576e2cb1decSSalil Mehta if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 577e2cb1decSSalil Mehta vector->vector = pci_irq_vector(hdev->pdev, i); 578e2cb1decSSalil Mehta vector->io_addr = hdev->hw.io_base + 579e2cb1decSSalil Mehta HCLGEVF_VECTOR_REG_BASE + 580e2cb1decSSalil Mehta (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 581e2cb1decSSalil Mehta hdev->vector_status[i] = 0; 582e2cb1decSSalil Mehta hdev->vector_irq[i] = vector->vector; 583e2cb1decSSalil Mehta 584e2cb1decSSalil Mehta vector++; 585e2cb1decSSalil Mehta alloc++; 586e2cb1decSSalil Mehta 587e2cb1decSSalil Mehta break; 588e2cb1decSSalil Mehta } 589e2cb1decSSalil Mehta } 590e2cb1decSSalil Mehta } 591e2cb1decSSalil Mehta hdev->num_msi_left -= alloc; 592e2cb1decSSalil Mehta hdev->num_msi_used += alloc; 593e2cb1decSSalil Mehta 594e2cb1decSSalil Mehta return alloc; 595e2cb1decSSalil Mehta } 596e2cb1decSSalil Mehta 597e2cb1decSSalil Mehta static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 598e2cb1decSSalil Mehta { 599e2cb1decSSalil Mehta int i; 600e2cb1decSSalil Mehta 601e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 602e2cb1decSSalil Mehta if (vector == hdev->vector_irq[i]) 603e2cb1decSSalil Mehta return i; 604e2cb1decSSalil Mehta 605e2cb1decSSalil Mehta return -EINVAL; 606e2cb1decSSalil Mehta } 607e2cb1decSSalil Mehta 608374ad291SJian Shen static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 609374ad291SJian Shen const u8 hfunc, const u8 *key) 610374ad291SJian Shen { 611374ad291SJian Shen struct hclgevf_rss_config_cmd *req; 612ebaf1908SWeihang Li unsigned int key_offset = 0; 613374ad291SJian Shen struct hclgevf_desc desc; 6143caf772bSYufeng Mo int key_counts; 615374ad291SJian Shen int key_size; 616374ad291SJian Shen int ret; 617374ad291SJian Shen 6183caf772bSYufeng Mo key_counts = HCLGEVF_RSS_KEY_SIZE; 619374ad291SJian Shen req = (struct hclgevf_rss_config_cmd *)desc.data; 620374ad291SJian Shen 6213caf772bSYufeng Mo while (key_counts) { 622374ad291SJian Shen hclgevf_cmd_setup_basic_desc(&desc, 623374ad291SJian Shen HCLGEVF_OPC_RSS_GENERIC_CONFIG, 624374ad291SJian Shen false); 625374ad291SJian Shen 626374ad291SJian Shen req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 627374ad291SJian Shen req->hash_config |= 628374ad291SJian Shen (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 629374ad291SJian Shen 6303caf772bSYufeng Mo key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts); 631374ad291SJian Shen memcpy(req->hash_key, 632374ad291SJian Shen key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 633374ad291SJian Shen 6343caf772bSYufeng Mo key_counts -= key_size; 6353caf772bSYufeng Mo key_offset++; 636374ad291SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 637374ad291SJian Shen if (ret) { 638374ad291SJian Shen dev_err(&hdev->pdev->dev, 639374ad291SJian Shen "Configure RSS config fail, status = %d\n", 640374ad291SJian Shen ret); 641374ad291SJian Shen return ret; 642374ad291SJian Shen } 643374ad291SJian Shen } 644374ad291SJian Shen 645374ad291SJian Shen return 0; 646374ad291SJian Shen } 647374ad291SJian Shen 648e2cb1decSSalil Mehta static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 649e2cb1decSSalil Mehta { 650e2cb1decSSalil Mehta return HCLGEVF_RSS_KEY_SIZE; 651e2cb1decSSalil Mehta } 652e2cb1decSSalil Mehta 653e2cb1decSSalil Mehta static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 654e2cb1decSSalil Mehta { 655e2cb1decSSalil Mehta const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 656e2cb1decSSalil Mehta struct hclgevf_rss_indirection_table_cmd *req; 657e2cb1decSSalil Mehta struct hclgevf_desc desc; 65887ce161eSGuangbin Huang int rss_cfg_tbl_num; 659e2cb1decSSalil Mehta int status; 660e2cb1decSSalil Mehta int i, j; 661e2cb1decSSalil Mehta 662e2cb1decSSalil Mehta req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 66387ce161eSGuangbin Huang rss_cfg_tbl_num = hdev->ae_dev->dev_specs.rss_ind_tbl_size / 66487ce161eSGuangbin Huang HCLGEVF_RSS_CFG_TBL_SIZE; 665e2cb1decSSalil Mehta 66687ce161eSGuangbin Huang for (i = 0; i < rss_cfg_tbl_num; i++) { 667e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 668e2cb1decSSalil Mehta false); 66955ff3ed5SJian Shen req->start_table_index = 67055ff3ed5SJian Shen cpu_to_le16(i * HCLGEVF_RSS_CFG_TBL_SIZE); 67155ff3ed5SJian Shen req->rss_set_bitmap = cpu_to_le16(HCLGEVF_RSS_SET_BITMAP_MSK); 672e2cb1decSSalil Mehta for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 673e2cb1decSSalil Mehta req->rss_result[j] = 674e2cb1decSSalil Mehta indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 675e2cb1decSSalil Mehta 676e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 677e2cb1decSSalil Mehta if (status) { 678e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 679e2cb1decSSalil Mehta "VF failed(=%d) to set RSS indirection table\n", 680e2cb1decSSalil Mehta status); 681e2cb1decSSalil Mehta return status; 682e2cb1decSSalil Mehta } 683e2cb1decSSalil Mehta } 684e2cb1decSSalil Mehta 685e2cb1decSSalil Mehta return 0; 686e2cb1decSSalil Mehta } 687e2cb1decSSalil Mehta 688e2cb1decSSalil Mehta static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 689e2cb1decSSalil Mehta { 690e2cb1decSSalil Mehta struct hclgevf_rss_tc_mode_cmd *req; 691e2cb1decSSalil Mehta u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 692e2cb1decSSalil Mehta u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 693e2cb1decSSalil Mehta u16 tc_size[HCLGEVF_MAX_TC_NUM]; 694e2cb1decSSalil Mehta struct hclgevf_desc desc; 695e2cb1decSSalil Mehta u16 roundup_size; 696ebaf1908SWeihang Li unsigned int i; 6972adb8187SHuazhong Tan int status; 698e2cb1decSSalil Mehta 699e2cb1decSSalil Mehta req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 700e2cb1decSSalil Mehta 701e2cb1decSSalil Mehta roundup_size = roundup_pow_of_two(rss_size); 702e2cb1decSSalil Mehta roundup_size = ilog2(roundup_size); 703e2cb1decSSalil Mehta 704e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 705e2cb1decSSalil Mehta tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 706e2cb1decSSalil Mehta tc_size[i] = roundup_size; 707e2cb1decSSalil Mehta tc_offset[i] = rss_size * i; 708e2cb1decSSalil Mehta } 709e2cb1decSSalil Mehta 710e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 711e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 71255ff3ed5SJian Shen u16 mode = 0; 71355ff3ed5SJian Shen 71455ff3ed5SJian Shen hnae3_set_bit(mode, HCLGEVF_RSS_TC_VALID_B, 715e2cb1decSSalil Mehta (tc_valid[i] & 0x1)); 71655ff3ed5SJian Shen hnae3_set_field(mode, HCLGEVF_RSS_TC_SIZE_M, 717e2cb1decSSalil Mehta HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 71833a8f764SGuojia Liao hnae3_set_bit(mode, HCLGEVF_RSS_TC_SIZE_MSB_B, 71933a8f764SGuojia Liao tc_size[i] >> HCLGEVF_RSS_TC_SIZE_MSB_OFFSET & 72033a8f764SGuojia Liao 0x1); 72155ff3ed5SJian Shen hnae3_set_field(mode, HCLGEVF_RSS_TC_OFFSET_M, 722e2cb1decSSalil Mehta HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 72355ff3ed5SJian Shen 72455ff3ed5SJian Shen req->rss_tc_mode[i] = cpu_to_le16(mode); 725e2cb1decSSalil Mehta } 726e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 727e2cb1decSSalil Mehta if (status) 728e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 729e2cb1decSSalil Mehta "VF failed(=%d) to set rss tc mode\n", status); 730e2cb1decSSalil Mehta 731e2cb1decSSalil Mehta return status; 732e2cb1decSSalil Mehta } 733e2cb1decSSalil Mehta 734a638b1d8SJian Shen /* for revision 0x20, vf shared the same rss config with pf */ 735a638b1d8SJian Shen static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 736a638b1d8SJian Shen { 737a638b1d8SJian Shen #define HCLGEVF_RSS_MBX_RESP_LEN 8 738a638b1d8SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 739a638b1d8SJian Shen u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 740d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 741a638b1d8SJian Shen u16 msg_num, hash_key_index; 742a638b1d8SJian Shen u8 index; 743a638b1d8SJian Shen int ret; 744a638b1d8SJian Shen 745d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_RSS_KEY, 0); 746a638b1d8SJian Shen msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 747a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN; 748a638b1d8SJian Shen for (index = 0; index < msg_num; index++) { 749d3410018SYufeng Mo send_msg.data[0] = index; 750d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 751a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN); 752a638b1d8SJian Shen if (ret) { 753a638b1d8SJian Shen dev_err(&hdev->pdev->dev, 754a638b1d8SJian Shen "VF get rss hash key from PF failed, ret=%d", 755a638b1d8SJian Shen ret); 756a638b1d8SJian Shen return ret; 757a638b1d8SJian Shen } 758a638b1d8SJian Shen 759a638b1d8SJian Shen hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 760a638b1d8SJian Shen if (index == msg_num - 1) 761a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 762a638b1d8SJian Shen &resp_msg[0], 763a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE - hash_key_index); 764a638b1d8SJian Shen else 765a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 766a638b1d8SJian Shen &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 767a638b1d8SJian Shen } 768a638b1d8SJian Shen 769a638b1d8SJian Shen return 0; 770a638b1d8SJian Shen } 771a638b1d8SJian Shen 772e2cb1decSSalil Mehta static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 773e2cb1decSSalil Mehta u8 *hfunc) 774e2cb1decSSalil Mehta { 775e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 776e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 777a638b1d8SJian Shen int i, ret; 778e2cb1decSSalil Mehta 779295ba232SGuangbin Huang if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 780374ad291SJian Shen /* Get hash algorithm */ 781374ad291SJian Shen if (hfunc) { 782374ad291SJian Shen switch (rss_cfg->hash_algo) { 783374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 784374ad291SJian Shen *hfunc = ETH_RSS_HASH_TOP; 785374ad291SJian Shen break; 786374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 787374ad291SJian Shen *hfunc = ETH_RSS_HASH_XOR; 788374ad291SJian Shen break; 789374ad291SJian Shen default: 790374ad291SJian Shen *hfunc = ETH_RSS_HASH_UNKNOWN; 791374ad291SJian Shen break; 792374ad291SJian Shen } 793374ad291SJian Shen } 794374ad291SJian Shen 795374ad291SJian Shen /* Get the RSS Key required by the user */ 796374ad291SJian Shen if (key) 797374ad291SJian Shen memcpy(key, rss_cfg->rss_hash_key, 798374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 799a638b1d8SJian Shen } else { 800a638b1d8SJian Shen if (hfunc) 801a638b1d8SJian Shen *hfunc = ETH_RSS_HASH_TOP; 802a638b1d8SJian Shen if (key) { 803a638b1d8SJian Shen ret = hclgevf_get_rss_hash_key(hdev); 804a638b1d8SJian Shen if (ret) 805a638b1d8SJian Shen return ret; 806a638b1d8SJian Shen memcpy(key, rss_cfg->rss_hash_key, 807a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE); 808a638b1d8SJian Shen } 809374ad291SJian Shen } 810374ad291SJian Shen 811e2cb1decSSalil Mehta if (indir) 81287ce161eSGuangbin Huang for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 813e2cb1decSSalil Mehta indir[i] = rss_cfg->rss_indirection_tbl[i]; 814e2cb1decSSalil Mehta 815374ad291SJian Shen return 0; 816e2cb1decSSalil Mehta } 817e2cb1decSSalil Mehta 818e2cb1decSSalil Mehta static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 819e2cb1decSSalil Mehta const u8 *key, const u8 hfunc) 820e2cb1decSSalil Mehta { 821e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 822e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 823374ad291SJian Shen int ret, i; 824374ad291SJian Shen 825295ba232SGuangbin Huang if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 826374ad291SJian Shen /* Set the RSS Hash Key if specififed by the user */ 827374ad291SJian Shen if (key) { 828374ad291SJian Shen switch (hfunc) { 829374ad291SJian Shen case ETH_RSS_HASH_TOP: 830374ad291SJian Shen rss_cfg->hash_algo = 831374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 832374ad291SJian Shen break; 833374ad291SJian Shen case ETH_RSS_HASH_XOR: 834374ad291SJian Shen rss_cfg->hash_algo = 835374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_SIMPLE; 836374ad291SJian Shen break; 837374ad291SJian Shen case ETH_RSS_HASH_NO_CHANGE: 838374ad291SJian Shen break; 839374ad291SJian Shen default: 840374ad291SJian Shen return -EINVAL; 841374ad291SJian Shen } 842374ad291SJian Shen 843374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 844374ad291SJian Shen key); 845374ad291SJian Shen if (ret) 846374ad291SJian Shen return ret; 847374ad291SJian Shen 848374ad291SJian Shen /* Update the shadow RSS key with user specified qids */ 849374ad291SJian Shen memcpy(rss_cfg->rss_hash_key, key, 850374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 851374ad291SJian Shen } 852374ad291SJian Shen } 853e2cb1decSSalil Mehta 854e2cb1decSSalil Mehta /* update the shadow RSS table with user specified qids */ 85587ce161eSGuangbin Huang for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 856e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = indir[i]; 857e2cb1decSSalil Mehta 858e2cb1decSSalil Mehta /* update the hardware */ 859e2cb1decSSalil Mehta return hclgevf_set_rss_indir_table(hdev); 860e2cb1decSSalil Mehta } 861e2cb1decSSalil Mehta 862d97b3072SJian Shen static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 863d97b3072SJian Shen { 864d97b3072SJian Shen u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 865d97b3072SJian Shen 866d97b3072SJian Shen if (nfc->data & RXH_L4_B_2_3) 867d97b3072SJian Shen hash_sets |= HCLGEVF_D_PORT_BIT; 868d97b3072SJian Shen else 869d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_PORT_BIT; 870d97b3072SJian Shen 871d97b3072SJian Shen if (nfc->data & RXH_IP_SRC) 872d97b3072SJian Shen hash_sets |= HCLGEVF_S_IP_BIT; 873d97b3072SJian Shen else 874d97b3072SJian Shen hash_sets &= ~HCLGEVF_S_IP_BIT; 875d97b3072SJian Shen 876d97b3072SJian Shen if (nfc->data & RXH_IP_DST) 877d97b3072SJian Shen hash_sets |= HCLGEVF_D_IP_BIT; 878d97b3072SJian Shen else 879d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_IP_BIT; 880d97b3072SJian Shen 881d97b3072SJian Shen if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 882d97b3072SJian Shen hash_sets |= HCLGEVF_V_TAG_BIT; 883d97b3072SJian Shen 884d97b3072SJian Shen return hash_sets; 885d97b3072SJian Shen } 886d97b3072SJian Shen 8875fd0e7b4SHuazhong Tan static int hclgevf_init_rss_tuple_cmd(struct hnae3_handle *handle, 8885fd0e7b4SHuazhong Tan struct ethtool_rxnfc *nfc, 8895fd0e7b4SHuazhong Tan struct hclgevf_rss_input_tuple_cmd *req) 890d97b3072SJian Shen { 891d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 892d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 893d97b3072SJian Shen u8 tuple_sets; 894d97b3072SJian Shen 895d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 896d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 897d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 898d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 899d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 900d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 901d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 902d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 903d97b3072SJian Shen 904d97b3072SJian Shen tuple_sets = hclgevf_get_rss_hash_bits(nfc); 905d97b3072SJian Shen switch (nfc->flow_type) { 906d97b3072SJian Shen case TCP_V4_FLOW: 907d97b3072SJian Shen req->ipv4_tcp_en = tuple_sets; 908d97b3072SJian Shen break; 909d97b3072SJian Shen case TCP_V6_FLOW: 910d97b3072SJian Shen req->ipv6_tcp_en = tuple_sets; 911d97b3072SJian Shen break; 912d97b3072SJian Shen case UDP_V4_FLOW: 913d97b3072SJian Shen req->ipv4_udp_en = tuple_sets; 914d97b3072SJian Shen break; 915d97b3072SJian Shen case UDP_V6_FLOW: 916d97b3072SJian Shen req->ipv6_udp_en = tuple_sets; 917d97b3072SJian Shen break; 918d97b3072SJian Shen case SCTP_V4_FLOW: 919d97b3072SJian Shen req->ipv4_sctp_en = tuple_sets; 920d97b3072SJian Shen break; 921d97b3072SJian Shen case SCTP_V6_FLOW: 922ab6e32d2SJian Shen if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 && 923ab6e32d2SJian Shen (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3))) 924d97b3072SJian Shen return -EINVAL; 925d97b3072SJian Shen 926d97b3072SJian Shen req->ipv6_sctp_en = tuple_sets; 927d97b3072SJian Shen break; 928d97b3072SJian Shen case IPV4_FLOW: 929d97b3072SJian Shen req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 930d97b3072SJian Shen break; 931d97b3072SJian Shen case IPV6_FLOW: 932d97b3072SJian Shen req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 933d97b3072SJian Shen break; 934d97b3072SJian Shen default: 935d97b3072SJian Shen return -EINVAL; 936d97b3072SJian Shen } 937d97b3072SJian Shen 9385fd0e7b4SHuazhong Tan return 0; 9395fd0e7b4SHuazhong Tan } 9405fd0e7b4SHuazhong Tan 9415fd0e7b4SHuazhong Tan static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 9425fd0e7b4SHuazhong Tan struct ethtool_rxnfc *nfc) 9435fd0e7b4SHuazhong Tan { 9445fd0e7b4SHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 9455fd0e7b4SHuazhong Tan struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 9465fd0e7b4SHuazhong Tan struct hclgevf_rss_input_tuple_cmd *req; 9475fd0e7b4SHuazhong Tan struct hclgevf_desc desc; 9485fd0e7b4SHuazhong Tan int ret; 9495fd0e7b4SHuazhong Tan 9505fd0e7b4SHuazhong Tan if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9515fd0e7b4SHuazhong Tan return -EOPNOTSUPP; 9525fd0e7b4SHuazhong Tan 9535fd0e7b4SHuazhong Tan if (nfc->data & 9545fd0e7b4SHuazhong Tan ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 9555fd0e7b4SHuazhong Tan return -EINVAL; 9565fd0e7b4SHuazhong Tan 9575fd0e7b4SHuazhong Tan req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 9585fd0e7b4SHuazhong Tan hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 9595fd0e7b4SHuazhong Tan 9605fd0e7b4SHuazhong Tan ret = hclgevf_init_rss_tuple_cmd(handle, nfc, req); 9615fd0e7b4SHuazhong Tan if (ret) { 9625fd0e7b4SHuazhong Tan dev_err(&hdev->pdev->dev, 9635fd0e7b4SHuazhong Tan "failed to init rss tuple cmd, ret = %d\n", ret); 9645fd0e7b4SHuazhong Tan return ret; 9655fd0e7b4SHuazhong Tan } 9665fd0e7b4SHuazhong Tan 967d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 968d97b3072SJian Shen if (ret) { 969d97b3072SJian Shen dev_err(&hdev->pdev->dev, 970d97b3072SJian Shen "Set rss tuple fail, status = %d\n", ret); 971d97b3072SJian Shen return ret; 972d97b3072SJian Shen } 973d97b3072SJian Shen 974d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 975d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 976d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 977d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 978d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 979d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 980d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 981d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 982d97b3072SJian Shen return 0; 983d97b3072SJian Shen } 984d97b3072SJian Shen 98573f7767eSJian Shen static int hclgevf_get_rss_tuple_by_flow_type(struct hclgevf_dev *hdev, 98673f7767eSJian Shen int flow_type, u8 *tuple_sets) 98773f7767eSJian Shen { 98873f7767eSJian Shen switch (flow_type) { 98973f7767eSJian Shen case TCP_V4_FLOW: 99073f7767eSJian Shen *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_tcp_en; 99173f7767eSJian Shen break; 99273f7767eSJian Shen case UDP_V4_FLOW: 99373f7767eSJian Shen *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_udp_en; 99473f7767eSJian Shen break; 99573f7767eSJian Shen case TCP_V6_FLOW: 99673f7767eSJian Shen *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_tcp_en; 99773f7767eSJian Shen break; 99873f7767eSJian Shen case UDP_V6_FLOW: 99973f7767eSJian Shen *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_udp_en; 100073f7767eSJian Shen break; 100173f7767eSJian Shen case SCTP_V4_FLOW: 100273f7767eSJian Shen *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_sctp_en; 100373f7767eSJian Shen break; 100473f7767eSJian Shen case SCTP_V6_FLOW: 100573f7767eSJian Shen *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_sctp_en; 100673f7767eSJian Shen break; 100773f7767eSJian Shen case IPV4_FLOW: 100873f7767eSJian Shen case IPV6_FLOW: 100973f7767eSJian Shen *tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 101073f7767eSJian Shen break; 101173f7767eSJian Shen default: 101273f7767eSJian Shen return -EINVAL; 101373f7767eSJian Shen } 101473f7767eSJian Shen 101573f7767eSJian Shen return 0; 101673f7767eSJian Shen } 101773f7767eSJian Shen 101873f7767eSJian Shen static u64 hclgevf_convert_rss_tuple(u8 tuple_sets) 101973f7767eSJian Shen { 102073f7767eSJian Shen u64 tuple_data = 0; 102173f7767eSJian Shen 102273f7767eSJian Shen if (tuple_sets & HCLGEVF_D_PORT_BIT) 102373f7767eSJian Shen tuple_data |= RXH_L4_B_2_3; 102473f7767eSJian Shen if (tuple_sets & HCLGEVF_S_PORT_BIT) 102573f7767eSJian Shen tuple_data |= RXH_L4_B_0_1; 102673f7767eSJian Shen if (tuple_sets & HCLGEVF_D_IP_BIT) 102773f7767eSJian Shen tuple_data |= RXH_IP_DST; 102873f7767eSJian Shen if (tuple_sets & HCLGEVF_S_IP_BIT) 102973f7767eSJian Shen tuple_data |= RXH_IP_SRC; 103073f7767eSJian Shen 103173f7767eSJian Shen return tuple_data; 103273f7767eSJian Shen } 103373f7767eSJian Shen 1034d97b3072SJian Shen static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 1035d97b3072SJian Shen struct ethtool_rxnfc *nfc) 1036d97b3072SJian Shen { 1037d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1038d97b3072SJian Shen u8 tuple_sets; 103973f7767eSJian Shen int ret; 1040d97b3072SJian Shen 1041295ba232SGuangbin Huang if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 1042d97b3072SJian Shen return -EOPNOTSUPP; 1043d97b3072SJian Shen 1044d97b3072SJian Shen nfc->data = 0; 1045d97b3072SJian Shen 104673f7767eSJian Shen ret = hclgevf_get_rss_tuple_by_flow_type(hdev, nfc->flow_type, 104773f7767eSJian Shen &tuple_sets); 104873f7767eSJian Shen if (ret || !tuple_sets) 104973f7767eSJian Shen return ret; 1050d97b3072SJian Shen 105173f7767eSJian Shen nfc->data = hclgevf_convert_rss_tuple(tuple_sets); 1052d97b3072SJian Shen 1053d97b3072SJian Shen return 0; 1054d97b3072SJian Shen } 1055d97b3072SJian Shen 1056d97b3072SJian Shen static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 1057d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg) 1058d97b3072SJian Shen { 1059d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 1060d97b3072SJian Shen struct hclgevf_desc desc; 1061d97b3072SJian Shen int ret; 1062d97b3072SJian Shen 1063d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 1064d97b3072SJian Shen 1065d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 1066d97b3072SJian Shen 1067d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 1068d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 1069d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 1070d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 1071d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 1072d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 1073d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 1074d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 1075d97b3072SJian Shen 1076d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1077d97b3072SJian Shen if (ret) 1078d97b3072SJian Shen dev_err(&hdev->pdev->dev, 1079d97b3072SJian Shen "Configure rss input fail, status = %d\n", ret); 1080d97b3072SJian Shen return ret; 1081d97b3072SJian Shen } 1082d97b3072SJian Shen 1083e2cb1decSSalil Mehta static int hclgevf_get_tc_size(struct hnae3_handle *handle) 1084e2cb1decSSalil Mehta { 1085e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1086e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1087e2cb1decSSalil Mehta 1088e2cb1decSSalil Mehta return rss_cfg->rss_size; 1089e2cb1decSSalil Mehta } 1090e2cb1decSSalil Mehta 1091e2cb1decSSalil Mehta static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 1092b204bc74SPeng Li int vector_id, 1093e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1094e2cb1decSSalil Mehta { 1095e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1096d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1097e2cb1decSSalil Mehta struct hnae3_ring_chain_node *node; 1098e2cb1decSSalil Mehta int status; 1099d3410018SYufeng Mo int i = 0; 1100e2cb1decSSalil Mehta 1101d3410018SYufeng Mo memset(&send_msg, 0, sizeof(send_msg)); 1102d3410018SYufeng Mo send_msg.code = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 1103c09ba484SPeng Li HCLGE_MBX_UNMAP_RING_TO_VECTOR; 1104d3410018SYufeng Mo send_msg.vector_id = vector_id; 1105e2cb1decSSalil Mehta 1106e2cb1decSSalil Mehta for (node = ring_chain; node; node = node->next) { 1107d3410018SYufeng Mo send_msg.param[i].ring_type = 1108e4e87715SPeng Li hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 1109d3410018SYufeng Mo 1110d3410018SYufeng Mo send_msg.param[i].tqp_index = node->tqp_index; 1111d3410018SYufeng Mo send_msg.param[i].int_gl_index = 1112d3410018SYufeng Mo hnae3_get_field(node->int_gl_idx, 111379eee410SFuyun Liang HNAE3_RING_GL_IDX_M, 111479eee410SFuyun Liang HNAE3_RING_GL_IDX_S); 111579eee410SFuyun Liang 11165d02a58dSYunsheng Lin i++; 1117d3410018SYufeng Mo if (i == HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM || !node->next) { 1118d3410018SYufeng Mo send_msg.ring_num = i; 1119e2cb1decSSalil Mehta 1120d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, false, 1121d3410018SYufeng Mo NULL, 0); 1122e2cb1decSSalil Mehta if (status) { 1123e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1124e2cb1decSSalil Mehta "Map TQP fail, status is %d.\n", 1125e2cb1decSSalil Mehta status); 1126e2cb1decSSalil Mehta return status; 1127e2cb1decSSalil Mehta } 1128e2cb1decSSalil Mehta i = 0; 1129e2cb1decSSalil Mehta } 1130e2cb1decSSalil Mehta } 1131e2cb1decSSalil Mehta 1132e2cb1decSSalil Mehta return 0; 1133e2cb1decSSalil Mehta } 1134e2cb1decSSalil Mehta 1135e2cb1decSSalil Mehta static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1136e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1137e2cb1decSSalil Mehta { 1138b204bc74SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1139b204bc74SPeng Li int vector_id; 1140b204bc74SPeng Li 1141b204bc74SPeng Li vector_id = hclgevf_get_vector_index(hdev, vector); 1142b204bc74SPeng Li if (vector_id < 0) { 1143b204bc74SPeng Li dev_err(&handle->pdev->dev, 1144b204bc74SPeng Li "Get vector index fail. ret =%d\n", vector_id); 1145b204bc74SPeng Li return vector_id; 1146b204bc74SPeng Li } 1147b204bc74SPeng Li 1148b204bc74SPeng Li return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1149e2cb1decSSalil Mehta } 1150e2cb1decSSalil Mehta 1151e2cb1decSSalil Mehta static int hclgevf_unmap_ring_from_vector( 1152e2cb1decSSalil Mehta struct hnae3_handle *handle, 1153e2cb1decSSalil Mehta int vector, 1154e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1155e2cb1decSSalil Mehta { 1156e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1157e2cb1decSSalil Mehta int ret, vector_id; 1158e2cb1decSSalil Mehta 1159dea846e8SHuazhong Tan if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1160dea846e8SHuazhong Tan return 0; 1161dea846e8SHuazhong Tan 1162e2cb1decSSalil Mehta vector_id = hclgevf_get_vector_index(hdev, vector); 1163e2cb1decSSalil Mehta if (vector_id < 0) { 1164e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1165e2cb1decSSalil Mehta "Get vector index fail. ret =%d\n", vector_id); 1166e2cb1decSSalil Mehta return vector_id; 1167e2cb1decSSalil Mehta } 1168e2cb1decSSalil Mehta 1169b204bc74SPeng Li ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 11700d3e6631SYunsheng Lin if (ret) 1171e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1172e2cb1decSSalil Mehta "Unmap ring from vector fail. vector=%d, ret =%d\n", 1173e2cb1decSSalil Mehta vector_id, 1174e2cb1decSSalil Mehta ret); 11750d3e6631SYunsheng Lin 1176e2cb1decSSalil Mehta return ret; 1177e2cb1decSSalil Mehta } 1178e2cb1decSSalil Mehta 11790d3e6631SYunsheng Lin static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 11800d3e6631SYunsheng Lin { 11810d3e6631SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 118203718db9SYunsheng Lin int vector_id; 11830d3e6631SYunsheng Lin 118403718db9SYunsheng Lin vector_id = hclgevf_get_vector_index(hdev, vector); 118503718db9SYunsheng Lin if (vector_id < 0) { 118603718db9SYunsheng Lin dev_err(&handle->pdev->dev, 118703718db9SYunsheng Lin "hclgevf_put_vector get vector index fail. ret =%d\n", 118803718db9SYunsheng Lin vector_id); 118903718db9SYunsheng Lin return vector_id; 119003718db9SYunsheng Lin } 119103718db9SYunsheng Lin 119203718db9SYunsheng Lin hclgevf_free_vector(hdev, vector_id); 1193e2cb1decSSalil Mehta 1194e2cb1decSSalil Mehta return 0; 1195e2cb1decSSalil Mehta } 1196e2cb1decSSalil Mehta 11973b75c3dfSPeng Li static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1198e196ec75SJian Shen bool en_uc_pmc, bool en_mc_pmc, 1199f01f5559SJian Shen bool en_bc_pmc) 1200e2cb1decSSalil Mehta { 12015e7414cdSJian Shen struct hnae3_handle *handle = &hdev->nic; 1202d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1203f01f5559SJian Shen int ret; 1204e2cb1decSSalil Mehta 1205d3410018SYufeng Mo memset(&send_msg, 0, sizeof(send_msg)); 1206d3410018SYufeng Mo send_msg.code = HCLGE_MBX_SET_PROMISC_MODE; 1207d3410018SYufeng Mo send_msg.en_bc = en_bc_pmc ? 1 : 0; 1208d3410018SYufeng Mo send_msg.en_uc = en_uc_pmc ? 1 : 0; 1209d3410018SYufeng Mo send_msg.en_mc = en_mc_pmc ? 1 : 0; 12105e7414cdSJian Shen send_msg.en_limit_promisc = test_bit(HNAE3_PFLAG_LIMIT_PROMISC, 12115e7414cdSJian Shen &handle->priv_flags) ? 1 : 0; 1212e2cb1decSSalil Mehta 1213d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1214f01f5559SJian Shen if (ret) 1215e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1216f01f5559SJian Shen "Set promisc mode fail, status is %d.\n", ret); 1217e2cb1decSSalil Mehta 1218f01f5559SJian Shen return ret; 1219e2cb1decSSalil Mehta } 1220e2cb1decSSalil Mehta 1221e196ec75SJian Shen static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 1222e196ec75SJian Shen bool en_mc_pmc) 1223e2cb1decSSalil Mehta { 1224e196ec75SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1225e196ec75SJian Shen bool en_bc_pmc; 1226e196ec75SJian Shen 1227295ba232SGuangbin Huang en_bc_pmc = hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2; 1228e196ec75SJian Shen 1229e196ec75SJian Shen return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc, 1230e196ec75SJian Shen en_bc_pmc); 1231e2cb1decSSalil Mehta } 1232e2cb1decSSalil Mehta 1233c631c696SJian Shen static void hclgevf_request_update_promisc_mode(struct hnae3_handle *handle) 1234c631c696SJian Shen { 1235c631c696SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1236c631c696SJian Shen 1237c631c696SJian Shen set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 12385e7414cdSJian Shen hclgevf_task_schedule(hdev, 0); 1239c631c696SJian Shen } 1240c631c696SJian Shen 1241c631c696SJian Shen static void hclgevf_sync_promisc_mode(struct hclgevf_dev *hdev) 1242c631c696SJian Shen { 1243c631c696SJian Shen struct hnae3_handle *handle = &hdev->nic; 1244c631c696SJian Shen bool en_uc_pmc = handle->netdev_flags & HNAE3_UPE; 1245c631c696SJian Shen bool en_mc_pmc = handle->netdev_flags & HNAE3_MPE; 1246c631c696SJian Shen int ret; 1247c631c696SJian Shen 1248c631c696SJian Shen if (test_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state)) { 1249c631c696SJian Shen ret = hclgevf_set_promisc_mode(handle, en_uc_pmc, en_mc_pmc); 1250c631c696SJian Shen if (!ret) 1251c631c696SJian Shen clear_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 1252c631c696SJian Shen } 1253c631c696SJian Shen } 1254c631c696SJian Shen 12558fa86551SYufeng Mo static int hclgevf_tqp_enable_cmd_send(struct hclgevf_dev *hdev, u16 tqp_id, 12568fa86551SYufeng Mo u16 stream_id, bool enable) 1257e2cb1decSSalil Mehta { 1258e2cb1decSSalil Mehta struct hclgevf_cfg_com_tqp_queue_cmd *req; 1259e2cb1decSSalil Mehta struct hclgevf_desc desc; 1260e2cb1decSSalil Mehta 1261e2cb1decSSalil Mehta req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1262e2cb1decSSalil Mehta 1263e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1264e2cb1decSSalil Mehta false); 1265e2cb1decSSalil Mehta req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1266e2cb1decSSalil Mehta req->stream_id = cpu_to_le16(stream_id); 1267ebaf1908SWeihang Li if (enable) 1268ebaf1908SWeihang Li req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 1269e2cb1decSSalil Mehta 12708fa86551SYufeng Mo return hclgevf_cmd_send(&hdev->hw, &desc, 1); 12718fa86551SYufeng Mo } 1272e2cb1decSSalil Mehta 12738fa86551SYufeng Mo static int hclgevf_tqp_enable(struct hnae3_handle *handle, bool enable) 12748fa86551SYufeng Mo { 12758fa86551SYufeng Mo struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 12768fa86551SYufeng Mo int ret; 12778fa86551SYufeng Mo u16 i; 12788fa86551SYufeng Mo 12798fa86551SYufeng Mo for (i = 0; i < handle->kinfo.num_tqps; i++) { 12808fa86551SYufeng Mo ret = hclgevf_tqp_enable_cmd_send(hdev, i, 0, enable); 12818fa86551SYufeng Mo if (ret) 12828fa86551SYufeng Mo return ret; 12838fa86551SYufeng Mo } 12848fa86551SYufeng Mo 12858fa86551SYufeng Mo return 0; 1286e2cb1decSSalil Mehta } 1287e2cb1decSSalil Mehta 1288e2cb1decSSalil Mehta static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1289e2cb1decSSalil Mehta { 1290b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1291e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 1292e2cb1decSSalil Mehta int i; 1293e2cb1decSSalil Mehta 1294b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 1295b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1296e2cb1decSSalil Mehta memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1297e2cb1decSSalil Mehta } 1298e2cb1decSSalil Mehta } 1299e2cb1decSSalil Mehta 13008e6de441SHuazhong Tan static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p) 13018e6de441SHuazhong Tan { 1302d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 13038e6de441SHuazhong Tan u8 host_mac[ETH_ALEN]; 13048e6de441SHuazhong Tan int status; 13058e6de441SHuazhong Tan 1306d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MAC_ADDR, 0); 1307d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, true, host_mac, 1308d3410018SYufeng Mo ETH_ALEN); 13098e6de441SHuazhong Tan if (status) { 13108e6de441SHuazhong Tan dev_err(&hdev->pdev->dev, 13118e6de441SHuazhong Tan "fail to get VF MAC from host %d", status); 13128e6de441SHuazhong Tan return status; 13138e6de441SHuazhong Tan } 13148e6de441SHuazhong Tan 13158e6de441SHuazhong Tan ether_addr_copy(p, host_mac); 13168e6de441SHuazhong Tan 13178e6de441SHuazhong Tan return 0; 13188e6de441SHuazhong Tan } 13198e6de441SHuazhong Tan 1320e2cb1decSSalil Mehta static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1321e2cb1decSSalil Mehta { 1322e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 13238e6de441SHuazhong Tan u8 host_mac_addr[ETH_ALEN]; 1324e2cb1decSSalil Mehta 13258e6de441SHuazhong Tan if (hclgevf_get_host_mac_addr(hdev, host_mac_addr)) 13268e6de441SHuazhong Tan return; 13278e6de441SHuazhong Tan 13288e6de441SHuazhong Tan hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr); 13298e6de441SHuazhong Tan if (hdev->has_pf_mac) 13308e6de441SHuazhong Tan ether_addr_copy(p, host_mac_addr); 13318e6de441SHuazhong Tan else 1332e2cb1decSSalil Mehta ether_addr_copy(p, hdev->hw.mac.mac_addr); 1333e2cb1decSSalil Mehta } 1334e2cb1decSSalil Mehta 133559098055SFuyun Liang static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 133659098055SFuyun Liang bool is_first) 1337e2cb1decSSalil Mehta { 1338e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1339e2cb1decSSalil Mehta u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1340d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1341e2cb1decSSalil Mehta u8 *new_mac_addr = (u8 *)p; 1342e2cb1decSSalil Mehta int status; 1343e2cb1decSSalil Mehta 1344d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 0); 1345ee4bcd3bSJian Shen send_msg.subcode = HCLGE_MBX_MAC_VLAN_UC_MODIFY; 1346d3410018SYufeng Mo ether_addr_copy(send_msg.data, new_mac_addr); 1347ee4bcd3bSJian Shen if (is_first && !hdev->has_pf_mac) 1348ee4bcd3bSJian Shen eth_zero_addr(&send_msg.data[ETH_ALEN]); 1349ee4bcd3bSJian Shen else 1350d3410018SYufeng Mo ether_addr_copy(&send_msg.data[ETH_ALEN], old_mac_addr); 1351d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1352e2cb1decSSalil Mehta if (!status) 1353e2cb1decSSalil Mehta ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1354e2cb1decSSalil Mehta 1355e2cb1decSSalil Mehta return status; 1356e2cb1decSSalil Mehta } 1357e2cb1decSSalil Mehta 1358ee4bcd3bSJian Shen static struct hclgevf_mac_addr_node * 1359ee4bcd3bSJian Shen hclgevf_find_mac_node(struct list_head *list, const u8 *mac_addr) 1360ee4bcd3bSJian Shen { 1361ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp; 1362ee4bcd3bSJian Shen 1363ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, list, node) 1364ee4bcd3bSJian Shen if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 1365ee4bcd3bSJian Shen return mac_node; 1366ee4bcd3bSJian Shen 1367ee4bcd3bSJian Shen return NULL; 1368ee4bcd3bSJian Shen } 1369ee4bcd3bSJian Shen 1370ee4bcd3bSJian Shen static void hclgevf_update_mac_node(struct hclgevf_mac_addr_node *mac_node, 1371ee4bcd3bSJian Shen enum HCLGEVF_MAC_NODE_STATE state) 1372ee4bcd3bSJian Shen { 1373ee4bcd3bSJian Shen switch (state) { 1374ee4bcd3bSJian Shen /* from set_rx_mode or tmp_add_list */ 1375ee4bcd3bSJian Shen case HCLGEVF_MAC_TO_ADD: 1376ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_DEL) 1377ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_ACTIVE; 1378ee4bcd3bSJian Shen break; 1379ee4bcd3bSJian Shen /* only from set_rx_mode */ 1380ee4bcd3bSJian Shen case HCLGEVF_MAC_TO_DEL: 1381ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1382ee4bcd3bSJian Shen list_del(&mac_node->node); 1383ee4bcd3bSJian Shen kfree(mac_node); 1384ee4bcd3bSJian Shen } else { 1385ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_TO_DEL; 1386ee4bcd3bSJian Shen } 1387ee4bcd3bSJian Shen break; 1388ee4bcd3bSJian Shen /* only from tmp_add_list, the mac_node->state won't be 1389ee4bcd3bSJian Shen * HCLGEVF_MAC_ACTIVE 1390ee4bcd3bSJian Shen */ 1391ee4bcd3bSJian Shen case HCLGEVF_MAC_ACTIVE: 1392ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1393ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_ACTIVE; 1394ee4bcd3bSJian Shen break; 1395ee4bcd3bSJian Shen } 1396ee4bcd3bSJian Shen } 1397ee4bcd3bSJian Shen 1398ee4bcd3bSJian Shen static int hclgevf_update_mac_list(struct hnae3_handle *handle, 1399ee4bcd3bSJian Shen enum HCLGEVF_MAC_NODE_STATE state, 1400ee4bcd3bSJian Shen enum HCLGEVF_MAC_ADDR_TYPE mac_type, 1401e2cb1decSSalil Mehta const unsigned char *addr) 1402e2cb1decSSalil Mehta { 1403e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1404ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node; 1405ee4bcd3bSJian Shen struct list_head *list; 1406e2cb1decSSalil Mehta 1407ee4bcd3bSJian Shen list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1408ee4bcd3bSJian Shen &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1409ee4bcd3bSJian Shen 1410ee4bcd3bSJian Shen spin_lock_bh(&hdev->mac_table.mac_list_lock); 1411ee4bcd3bSJian Shen 1412ee4bcd3bSJian Shen /* if the mac addr is already in the mac list, no need to add a new 1413ee4bcd3bSJian Shen * one into it, just check the mac addr state, convert it to a new 1414ee4bcd3bSJian Shen * new state, or just remove it, or do nothing. 1415ee4bcd3bSJian Shen */ 1416ee4bcd3bSJian Shen mac_node = hclgevf_find_mac_node(list, addr); 1417ee4bcd3bSJian Shen if (mac_node) { 1418ee4bcd3bSJian Shen hclgevf_update_mac_node(mac_node, state); 1419ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1420ee4bcd3bSJian Shen return 0; 1421ee4bcd3bSJian Shen } 1422ee4bcd3bSJian Shen /* if this address is never added, unnecessary to delete */ 1423ee4bcd3bSJian Shen if (state == HCLGEVF_MAC_TO_DEL) { 1424ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1425ee4bcd3bSJian Shen return -ENOENT; 1426ee4bcd3bSJian Shen } 1427ee4bcd3bSJian Shen 1428ee4bcd3bSJian Shen mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 1429ee4bcd3bSJian Shen if (!mac_node) { 1430ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1431ee4bcd3bSJian Shen return -ENOMEM; 1432ee4bcd3bSJian Shen } 1433ee4bcd3bSJian Shen 1434ee4bcd3bSJian Shen mac_node->state = state; 1435ee4bcd3bSJian Shen ether_addr_copy(mac_node->mac_addr, addr); 1436ee4bcd3bSJian Shen list_add_tail(&mac_node->node, list); 1437ee4bcd3bSJian Shen 1438ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1439ee4bcd3bSJian Shen return 0; 1440ee4bcd3bSJian Shen } 1441ee4bcd3bSJian Shen 1442ee4bcd3bSJian Shen static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1443ee4bcd3bSJian Shen const unsigned char *addr) 1444ee4bcd3bSJian Shen { 1445ee4bcd3bSJian Shen return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1446ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_UC, addr); 1447e2cb1decSSalil Mehta } 1448e2cb1decSSalil Mehta 1449e2cb1decSSalil Mehta static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1450e2cb1decSSalil Mehta const unsigned char *addr) 1451e2cb1decSSalil Mehta { 1452ee4bcd3bSJian Shen return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1453ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_UC, addr); 1454e2cb1decSSalil Mehta } 1455e2cb1decSSalil Mehta 1456e2cb1decSSalil Mehta static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1457e2cb1decSSalil Mehta const unsigned char *addr) 1458e2cb1decSSalil Mehta { 1459ee4bcd3bSJian Shen return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1460ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_MC, addr); 1461e2cb1decSSalil Mehta } 1462e2cb1decSSalil Mehta 1463e2cb1decSSalil Mehta static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1464e2cb1decSSalil Mehta const unsigned char *addr) 1465e2cb1decSSalil Mehta { 1466ee4bcd3bSJian Shen return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1467ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_MC, addr); 1468ee4bcd3bSJian Shen } 1469e2cb1decSSalil Mehta 1470ee4bcd3bSJian Shen static int hclgevf_add_del_mac_addr(struct hclgevf_dev *hdev, 1471ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, 1472ee4bcd3bSJian Shen enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1473ee4bcd3bSJian Shen { 1474ee4bcd3bSJian Shen struct hclge_vf_to_pf_msg send_msg; 1475ee4bcd3bSJian Shen u8 code, subcode; 1476ee4bcd3bSJian Shen 1477ee4bcd3bSJian Shen if (mac_type == HCLGEVF_MAC_ADDR_UC) { 1478ee4bcd3bSJian Shen code = HCLGE_MBX_SET_UNICAST; 1479ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1480ee4bcd3bSJian Shen subcode = HCLGE_MBX_MAC_VLAN_UC_ADD; 1481ee4bcd3bSJian Shen else 1482ee4bcd3bSJian Shen subcode = HCLGE_MBX_MAC_VLAN_UC_REMOVE; 1483ee4bcd3bSJian Shen } else { 1484ee4bcd3bSJian Shen code = HCLGE_MBX_SET_MULTICAST; 1485ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1486ee4bcd3bSJian Shen subcode = HCLGE_MBX_MAC_VLAN_MC_ADD; 1487ee4bcd3bSJian Shen else 1488ee4bcd3bSJian Shen subcode = HCLGE_MBX_MAC_VLAN_MC_REMOVE; 1489ee4bcd3bSJian Shen } 1490ee4bcd3bSJian Shen 1491ee4bcd3bSJian Shen hclgevf_build_send_msg(&send_msg, code, subcode); 1492ee4bcd3bSJian Shen ether_addr_copy(send_msg.data, mac_node->mac_addr); 1493d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1494e2cb1decSSalil Mehta } 1495e2cb1decSSalil Mehta 1496ee4bcd3bSJian Shen static void hclgevf_config_mac_list(struct hclgevf_dev *hdev, 1497ee4bcd3bSJian Shen struct list_head *list, 1498ee4bcd3bSJian Shen enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1499ee4bcd3bSJian Shen { 1500ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp; 1501ee4bcd3bSJian Shen int ret; 1502ee4bcd3bSJian Shen 1503ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, list, node) { 1504ee4bcd3bSJian Shen ret = hclgevf_add_del_mac_addr(hdev, mac_node, mac_type); 1505ee4bcd3bSJian Shen if (ret) { 1506ee4bcd3bSJian Shen dev_err(&hdev->pdev->dev, 1507ee4bcd3bSJian Shen "failed to configure mac %pM, state = %d, ret = %d\n", 1508ee4bcd3bSJian Shen mac_node->mac_addr, mac_node->state, ret); 1509ee4bcd3bSJian Shen return; 1510ee4bcd3bSJian Shen } 1511ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1512ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_ACTIVE; 1513ee4bcd3bSJian Shen } else { 1514ee4bcd3bSJian Shen list_del(&mac_node->node); 1515ee4bcd3bSJian Shen kfree(mac_node); 1516ee4bcd3bSJian Shen } 1517ee4bcd3bSJian Shen } 1518ee4bcd3bSJian Shen } 1519ee4bcd3bSJian Shen 1520ee4bcd3bSJian Shen static void hclgevf_sync_from_add_list(struct list_head *add_list, 1521ee4bcd3bSJian Shen struct list_head *mac_list) 1522ee4bcd3bSJian Shen { 1523ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1524ee4bcd3bSJian Shen 1525ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, add_list, node) { 1526ee4bcd3bSJian Shen /* if the mac address from tmp_add_list is not in the 1527ee4bcd3bSJian Shen * uc/mc_mac_list, it means have received a TO_DEL request 1528ee4bcd3bSJian Shen * during the time window of sending mac config request to PF 1529ee4bcd3bSJian Shen * If mac_node state is ACTIVE, then change its state to TO_DEL, 1530ee4bcd3bSJian Shen * then it will be removed at next time. If is TO_ADD, it means 1531ee4bcd3bSJian Shen * send TO_ADD request failed, so just remove the mac node. 1532ee4bcd3bSJian Shen */ 1533ee4bcd3bSJian Shen new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1534ee4bcd3bSJian Shen if (new_node) { 1535ee4bcd3bSJian Shen hclgevf_update_mac_node(new_node, mac_node->state); 1536ee4bcd3bSJian Shen list_del(&mac_node->node); 1537ee4bcd3bSJian Shen kfree(mac_node); 1538ee4bcd3bSJian Shen } else if (mac_node->state == HCLGEVF_MAC_ACTIVE) { 1539ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_TO_DEL; 154049768ce9SBaokun Li list_move_tail(&mac_node->node, mac_list); 1541ee4bcd3bSJian Shen } else { 1542ee4bcd3bSJian Shen list_del(&mac_node->node); 1543ee4bcd3bSJian Shen kfree(mac_node); 1544ee4bcd3bSJian Shen } 1545ee4bcd3bSJian Shen } 1546ee4bcd3bSJian Shen } 1547ee4bcd3bSJian Shen 1548ee4bcd3bSJian Shen static void hclgevf_sync_from_del_list(struct list_head *del_list, 1549ee4bcd3bSJian Shen struct list_head *mac_list) 1550ee4bcd3bSJian Shen { 1551ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1552ee4bcd3bSJian Shen 1553ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, del_list, node) { 1554ee4bcd3bSJian Shen new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1555ee4bcd3bSJian Shen if (new_node) { 1556ee4bcd3bSJian Shen /* If the mac addr is exist in the mac list, it means 1557ee4bcd3bSJian Shen * received a new request TO_ADD during the time window 1558ee4bcd3bSJian Shen * of sending mac addr configurrequest to PF, so just 1559ee4bcd3bSJian Shen * change the mac state to ACTIVE. 1560ee4bcd3bSJian Shen */ 1561ee4bcd3bSJian Shen new_node->state = HCLGEVF_MAC_ACTIVE; 1562ee4bcd3bSJian Shen list_del(&mac_node->node); 1563ee4bcd3bSJian Shen kfree(mac_node); 1564ee4bcd3bSJian Shen } else { 156549768ce9SBaokun Li list_move_tail(&mac_node->node, mac_list); 1566ee4bcd3bSJian Shen } 1567ee4bcd3bSJian Shen } 1568ee4bcd3bSJian Shen } 1569ee4bcd3bSJian Shen 1570ee4bcd3bSJian Shen static void hclgevf_clear_list(struct list_head *list) 1571ee4bcd3bSJian Shen { 1572ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp; 1573ee4bcd3bSJian Shen 1574ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, list, node) { 1575ee4bcd3bSJian Shen list_del(&mac_node->node); 1576ee4bcd3bSJian Shen kfree(mac_node); 1577ee4bcd3bSJian Shen } 1578ee4bcd3bSJian Shen } 1579ee4bcd3bSJian Shen 1580ee4bcd3bSJian Shen static void hclgevf_sync_mac_list(struct hclgevf_dev *hdev, 1581ee4bcd3bSJian Shen enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1582ee4bcd3bSJian Shen { 1583ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1584ee4bcd3bSJian Shen struct list_head tmp_add_list, tmp_del_list; 1585ee4bcd3bSJian Shen struct list_head *list; 1586ee4bcd3bSJian Shen 1587ee4bcd3bSJian Shen INIT_LIST_HEAD(&tmp_add_list); 1588ee4bcd3bSJian Shen INIT_LIST_HEAD(&tmp_del_list); 1589ee4bcd3bSJian Shen 1590ee4bcd3bSJian Shen /* move the mac addr to the tmp_add_list and tmp_del_list, then 1591ee4bcd3bSJian Shen * we can add/delete these mac addr outside the spin lock 1592ee4bcd3bSJian Shen */ 1593ee4bcd3bSJian Shen list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1594ee4bcd3bSJian Shen &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1595ee4bcd3bSJian Shen 1596ee4bcd3bSJian Shen spin_lock_bh(&hdev->mac_table.mac_list_lock); 1597ee4bcd3bSJian Shen 1598ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, list, node) { 1599ee4bcd3bSJian Shen switch (mac_node->state) { 1600ee4bcd3bSJian Shen case HCLGEVF_MAC_TO_DEL: 160149768ce9SBaokun Li list_move_tail(&mac_node->node, &tmp_del_list); 1602ee4bcd3bSJian Shen break; 1603ee4bcd3bSJian Shen case HCLGEVF_MAC_TO_ADD: 1604ee4bcd3bSJian Shen new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 1605ee4bcd3bSJian Shen if (!new_node) 1606ee4bcd3bSJian Shen goto stop_traverse; 1607ee4bcd3bSJian Shen 1608ee4bcd3bSJian Shen ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 1609ee4bcd3bSJian Shen new_node->state = mac_node->state; 1610ee4bcd3bSJian Shen list_add_tail(&new_node->node, &tmp_add_list); 1611ee4bcd3bSJian Shen break; 1612ee4bcd3bSJian Shen default: 1613ee4bcd3bSJian Shen break; 1614ee4bcd3bSJian Shen } 1615ee4bcd3bSJian Shen } 1616ee4bcd3bSJian Shen 1617ee4bcd3bSJian Shen stop_traverse: 1618ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1619ee4bcd3bSJian Shen 1620ee4bcd3bSJian Shen /* delete first, in order to get max mac table space for adding */ 1621ee4bcd3bSJian Shen hclgevf_config_mac_list(hdev, &tmp_del_list, mac_type); 1622ee4bcd3bSJian Shen hclgevf_config_mac_list(hdev, &tmp_add_list, mac_type); 1623ee4bcd3bSJian Shen 1624ee4bcd3bSJian Shen /* if some mac addresses were added/deleted fail, move back to the 1625ee4bcd3bSJian Shen * mac_list, and retry at next time. 1626ee4bcd3bSJian Shen */ 1627ee4bcd3bSJian Shen spin_lock_bh(&hdev->mac_table.mac_list_lock); 1628ee4bcd3bSJian Shen 1629ee4bcd3bSJian Shen hclgevf_sync_from_del_list(&tmp_del_list, list); 1630ee4bcd3bSJian Shen hclgevf_sync_from_add_list(&tmp_add_list, list); 1631ee4bcd3bSJian Shen 1632ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1633ee4bcd3bSJian Shen } 1634ee4bcd3bSJian Shen 1635ee4bcd3bSJian Shen static void hclgevf_sync_mac_table(struct hclgevf_dev *hdev) 1636ee4bcd3bSJian Shen { 1637ee4bcd3bSJian Shen hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_UC); 1638ee4bcd3bSJian Shen hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_MC); 1639ee4bcd3bSJian Shen } 1640ee4bcd3bSJian Shen 1641ee4bcd3bSJian Shen static void hclgevf_uninit_mac_list(struct hclgevf_dev *hdev) 1642ee4bcd3bSJian Shen { 1643ee4bcd3bSJian Shen spin_lock_bh(&hdev->mac_table.mac_list_lock); 1644ee4bcd3bSJian Shen 1645ee4bcd3bSJian Shen hclgevf_clear_list(&hdev->mac_table.uc_mac_list); 1646ee4bcd3bSJian Shen hclgevf_clear_list(&hdev->mac_table.mc_mac_list); 1647ee4bcd3bSJian Shen 1648ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1649ee4bcd3bSJian Shen } 1650ee4bcd3bSJian Shen 1651fa6a262aSJian Shen static int hclgevf_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 1652fa6a262aSJian Shen { 1653fa6a262aSJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1654fa6a262aSJian Shen struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 1655fa6a262aSJian Shen struct hclge_vf_to_pf_msg send_msg; 1656fa6a262aSJian Shen 1657fa6a262aSJian Shen if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 1658fa6a262aSJian Shen return -EOPNOTSUPP; 1659fa6a262aSJian Shen 1660fa6a262aSJian Shen hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1661fa6a262aSJian Shen HCLGE_MBX_ENABLE_VLAN_FILTER); 1662fa6a262aSJian Shen send_msg.data[0] = enable ? 1 : 0; 1663fa6a262aSJian Shen 1664fa6a262aSJian Shen return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1665fa6a262aSJian Shen } 1666fa6a262aSJian Shen 1667e2cb1decSSalil Mehta static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1668e2cb1decSSalil Mehta __be16 proto, u16 vlan_id, 1669e2cb1decSSalil Mehta bool is_kill) 1670e2cb1decSSalil Mehta { 1671d3410018SYufeng Mo #define HCLGEVF_VLAN_MBX_IS_KILL_OFFSET 0 1672d3410018SYufeng Mo #define HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET 1 1673d3410018SYufeng Mo #define HCLGEVF_VLAN_MBX_PROTO_OFFSET 3 1674d3410018SYufeng Mo 1675e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1676d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1677fe4144d4SJian Shen int ret; 1678e2cb1decSSalil Mehta 1679b37ce587SYufeng Mo if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1680e2cb1decSSalil Mehta return -EINVAL; 1681e2cb1decSSalil Mehta 1682e2cb1decSSalil Mehta if (proto != htons(ETH_P_8021Q)) 1683e2cb1decSSalil Mehta return -EPROTONOSUPPORT; 1684e2cb1decSSalil Mehta 1685b7b5d25bSGuojia Liao /* When device is resetting or reset failed, firmware is unable to 1686b7b5d25bSGuojia Liao * handle mailbox. Just record the vlan id, and remove it after 1687fe4144d4SJian Shen * reset finished. 1688fe4144d4SJian Shen */ 1689b7b5d25bSGuojia Liao if ((test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 1690b7b5d25bSGuojia Liao test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) && is_kill) { 1691fe4144d4SJian Shen set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1692fe4144d4SJian Shen return -EBUSY; 1693fe4144d4SJian Shen } 1694fe4144d4SJian Shen 1695d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1696d3410018SYufeng Mo HCLGE_MBX_VLAN_FILTER); 1697d3410018SYufeng Mo send_msg.data[HCLGEVF_VLAN_MBX_IS_KILL_OFFSET] = is_kill; 1698d3410018SYufeng Mo memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET], &vlan_id, 1699d3410018SYufeng Mo sizeof(vlan_id)); 1700d3410018SYufeng Mo memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_PROTO_OFFSET], &proto, 1701d3410018SYufeng Mo sizeof(proto)); 170246ee7350SGuojia Liao /* when remove hw vlan filter failed, record the vlan id, 1703fe4144d4SJian Shen * and try to remove it from hw later, to be consistence 1704fe4144d4SJian Shen * with stack. 1705fe4144d4SJian Shen */ 1706d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1707fe4144d4SJian Shen if (is_kill && ret) 1708fe4144d4SJian Shen set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1709fe4144d4SJian Shen 1710fe4144d4SJian Shen return ret; 1711fe4144d4SJian Shen } 1712fe4144d4SJian Shen 1713fe4144d4SJian Shen static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1714fe4144d4SJian Shen { 1715fe4144d4SJian Shen #define HCLGEVF_MAX_SYNC_COUNT 60 1716fe4144d4SJian Shen struct hnae3_handle *handle = &hdev->nic; 1717fe4144d4SJian Shen int ret, sync_cnt = 0; 1718fe4144d4SJian Shen u16 vlan_id; 1719fe4144d4SJian Shen 1720fe4144d4SJian Shen vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1721fe4144d4SJian Shen while (vlan_id != VLAN_N_VID) { 1722fe4144d4SJian Shen ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1723fe4144d4SJian Shen vlan_id, true); 1724fe4144d4SJian Shen if (ret) 1725fe4144d4SJian Shen return; 1726fe4144d4SJian Shen 1727fe4144d4SJian Shen clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1728fe4144d4SJian Shen sync_cnt++; 1729fe4144d4SJian Shen if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1730fe4144d4SJian Shen return; 1731fe4144d4SJian Shen 1732fe4144d4SJian Shen vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1733fe4144d4SJian Shen } 1734e2cb1decSSalil Mehta } 1735e2cb1decSSalil Mehta 1736b2641e2aSYunsheng Lin static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1737b2641e2aSYunsheng Lin { 1738b2641e2aSYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1739d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1740b2641e2aSYunsheng Lin 1741d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1742d3410018SYufeng Mo HCLGE_MBX_VLAN_RX_OFF_CFG); 1743d3410018SYufeng Mo send_msg.data[0] = enable ? 1 : 0; 1744d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1745b2641e2aSYunsheng Lin } 1746b2641e2aSYunsheng Lin 17478fa86551SYufeng Mo static int hclgevf_reset_tqp(struct hnae3_handle *handle) 1748e2cb1decSSalil Mehta { 17498fa86551SYufeng Mo #define HCLGEVF_RESET_ALL_QUEUE_DONE 1U 1750e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1751d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 17528fa86551SYufeng Mo u8 return_status = 0; 17531a426f8bSPeng Li int ret; 17548fa86551SYufeng Mo u16 i; 1755e2cb1decSSalil Mehta 17561a426f8bSPeng Li /* disable vf queue before send queue reset msg to PF */ 17578fa86551SYufeng Mo ret = hclgevf_tqp_enable(handle, false); 17588fa86551SYufeng Mo if (ret) { 17598fa86551SYufeng Mo dev_err(&hdev->pdev->dev, "failed to disable tqp, ret = %d\n", 17608fa86551SYufeng Mo ret); 17617fa6be4fSHuazhong Tan return ret; 17628fa86551SYufeng Mo } 17631a426f8bSPeng Li 1764d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 17658fa86551SYufeng Mo 17668fa86551SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &return_status, 17678fa86551SYufeng Mo sizeof(return_status)); 17688fa86551SYufeng Mo if (ret || return_status == HCLGEVF_RESET_ALL_QUEUE_DONE) 17698fa86551SYufeng Mo return ret; 17708fa86551SYufeng Mo 17718fa86551SYufeng Mo for (i = 1; i < handle->kinfo.num_tqps; i++) { 17728fa86551SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 17738fa86551SYufeng Mo memcpy(send_msg.data, &i, sizeof(i)); 17748fa86551SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 17758fa86551SYufeng Mo if (ret) 17768fa86551SYufeng Mo return ret; 17778fa86551SYufeng Mo } 17788fa86551SYufeng Mo 17798fa86551SYufeng Mo return 0; 1780e2cb1decSSalil Mehta } 1781e2cb1decSSalil Mehta 1782818f1675SYunsheng Lin static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1783818f1675SYunsheng Lin { 1784818f1675SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1785d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1786818f1675SYunsheng Lin 1787d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MTU, 0); 1788d3410018SYufeng Mo memcpy(send_msg.data, &new_mtu, sizeof(new_mtu)); 1789d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1790818f1675SYunsheng Lin } 1791818f1675SYunsheng Lin 17926988eb2aSSalil Mehta static int hclgevf_notify_client(struct hclgevf_dev *hdev, 17936988eb2aSSalil Mehta enum hnae3_reset_notify_type type) 17946988eb2aSSalil Mehta { 17956988eb2aSSalil Mehta struct hnae3_client *client = hdev->nic_client; 17966988eb2aSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 17976a5f6fa3SHuazhong Tan int ret; 17986988eb2aSSalil Mehta 179925d1817cSHuazhong Tan if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 180025d1817cSHuazhong Tan !client) 180125d1817cSHuazhong Tan return 0; 180225d1817cSHuazhong Tan 18036988eb2aSSalil Mehta if (!client->ops->reset_notify) 18046988eb2aSSalil Mehta return -EOPNOTSUPP; 18056988eb2aSSalil Mehta 18066a5f6fa3SHuazhong Tan ret = client->ops->reset_notify(handle, type); 18076a5f6fa3SHuazhong Tan if (ret) 18086a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 18096a5f6fa3SHuazhong Tan type, ret); 18106a5f6fa3SHuazhong Tan 18116a5f6fa3SHuazhong Tan return ret; 18126988eb2aSSalil Mehta } 18136988eb2aSSalil Mehta 1814fe735c84SHuazhong Tan static int hclgevf_notify_roce_client(struct hclgevf_dev *hdev, 1815fe735c84SHuazhong Tan enum hnae3_reset_notify_type type) 1816fe735c84SHuazhong Tan { 1817fe735c84SHuazhong Tan struct hnae3_client *client = hdev->roce_client; 1818fe735c84SHuazhong Tan struct hnae3_handle *handle = &hdev->roce; 1819fe735c84SHuazhong Tan int ret; 1820fe735c84SHuazhong Tan 1821fe735c84SHuazhong Tan if (!test_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state) || !client) 1822fe735c84SHuazhong Tan return 0; 1823fe735c84SHuazhong Tan 1824fe735c84SHuazhong Tan if (!client->ops->reset_notify) 1825fe735c84SHuazhong Tan return -EOPNOTSUPP; 1826fe735c84SHuazhong Tan 1827fe735c84SHuazhong Tan ret = client->ops->reset_notify(handle, type); 1828fe735c84SHuazhong Tan if (ret) 1829fe735c84SHuazhong Tan dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 1830fe735c84SHuazhong Tan type, ret); 1831fe735c84SHuazhong Tan return ret; 1832fe735c84SHuazhong Tan } 1833fe735c84SHuazhong Tan 18346988eb2aSSalil Mehta static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 18356988eb2aSSalil Mehta { 1836aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_US 20000 1837aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_CNT 2000 1838aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1839aa5c4f17SHuazhong Tan (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1840aa5c4f17SHuazhong Tan 1841aa5c4f17SHuazhong Tan u32 val; 1842aa5c4f17SHuazhong Tan int ret; 18436988eb2aSSalil Mehta 1844f28368bbSHuazhong Tan if (hdev->reset_type == HNAE3_VF_RESET) 184572e2fb07SHuazhong Tan ret = readl_poll_timeout(hdev->hw.io_base + 184672e2fb07SHuazhong Tan HCLGEVF_VF_RST_ING, val, 184772e2fb07SHuazhong Tan !(val & HCLGEVF_VF_RST_ING_BIT), 184872e2fb07SHuazhong Tan HCLGEVF_RESET_WAIT_US, 184972e2fb07SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 185072e2fb07SHuazhong Tan else 185172e2fb07SHuazhong Tan ret = readl_poll_timeout(hdev->hw.io_base + 185272e2fb07SHuazhong Tan HCLGEVF_RST_ING, val, 1853aa5c4f17SHuazhong Tan !(val & HCLGEVF_RST_ING_BITS), 1854aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_US, 1855aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 18566988eb2aSSalil Mehta 18576988eb2aSSalil Mehta /* hardware completion status should be available by this time */ 1858aa5c4f17SHuazhong Tan if (ret) { 1859aa5c4f17SHuazhong Tan dev_err(&hdev->pdev->dev, 18608912fd6aSColin Ian King "couldn't get reset done status from h/w, timeout!\n"); 1861aa5c4f17SHuazhong Tan return ret; 18626988eb2aSSalil Mehta } 18636988eb2aSSalil Mehta 18646988eb2aSSalil Mehta /* we will wait a bit more to let reset of the stack to complete. This 18656988eb2aSSalil Mehta * might happen in case reset assertion was made by PF. Yes, this also 18666988eb2aSSalil Mehta * means we might end up waiting bit more even for VF reset. 18676988eb2aSSalil Mehta */ 18686988eb2aSSalil Mehta msleep(5000); 18696988eb2aSSalil Mehta 18706988eb2aSSalil Mehta return 0; 18716988eb2aSSalil Mehta } 18726988eb2aSSalil Mehta 18736b428b4fSHuazhong Tan static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable) 18746b428b4fSHuazhong Tan { 18756b428b4fSHuazhong Tan u32 reg_val; 18766b428b4fSHuazhong Tan 18776b428b4fSHuazhong Tan reg_val = hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG); 18786b428b4fSHuazhong Tan if (enable) 18796b428b4fSHuazhong Tan reg_val |= HCLGEVF_NIC_SW_RST_RDY; 18806b428b4fSHuazhong Tan else 18816b428b4fSHuazhong Tan reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; 18826b428b4fSHuazhong Tan 18836b428b4fSHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 18846b428b4fSHuazhong Tan reg_val); 18856b428b4fSHuazhong Tan } 18866b428b4fSHuazhong Tan 18876988eb2aSSalil Mehta static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 18886988eb2aSSalil Mehta { 18897a01c897SSalil Mehta int ret; 18907a01c897SSalil Mehta 18916988eb2aSSalil Mehta /* uninitialize the nic client */ 18926a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 18936a5f6fa3SHuazhong Tan if (ret) 18946a5f6fa3SHuazhong Tan return ret; 18956988eb2aSSalil Mehta 18967a01c897SSalil Mehta /* re-initialize the hclge device */ 18979c6f7085SHuazhong Tan ret = hclgevf_reset_hdev(hdev); 18987a01c897SSalil Mehta if (ret) { 18997a01c897SSalil Mehta dev_err(&hdev->pdev->dev, 19007a01c897SSalil Mehta "hclge device re-init failed, VF is disabled!\n"); 19017a01c897SSalil Mehta return ret; 19027a01c897SSalil Mehta } 19036988eb2aSSalil Mehta 19046988eb2aSSalil Mehta /* bring up the nic client again */ 19056a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 19066a5f6fa3SHuazhong Tan if (ret) 19076a5f6fa3SHuazhong Tan return ret; 19086988eb2aSSalil Mehta 19096b428b4fSHuazhong Tan /* clear handshake status with IMP */ 19106b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, false); 19116b428b4fSHuazhong Tan 19121cc9bc6eSHuazhong Tan /* bring up the nic to enable TX/RX again */ 19131cc9bc6eSHuazhong Tan return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 19146988eb2aSSalil Mehta } 19156988eb2aSSalil Mehta 1916dea846e8SHuazhong Tan static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1917dea846e8SHuazhong Tan { 1918ada13ee3SHuazhong Tan #define HCLGEVF_RESET_SYNC_TIME 100 1919ada13ee3SHuazhong Tan 1920f28368bbSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FUNC_RESET) { 1921d41884eeSHuazhong Tan struct hclge_vf_to_pf_msg send_msg; 1922d41884eeSHuazhong Tan int ret; 1923d41884eeSHuazhong Tan 1924d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_RESET, 0); 1925d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1926cddd5648SHuazhong Tan if (ret) { 1927cddd5648SHuazhong Tan dev_err(&hdev->pdev->dev, 1928cddd5648SHuazhong Tan "failed to assert VF reset, ret = %d\n", ret); 1929cddd5648SHuazhong Tan return ret; 1930cddd5648SHuazhong Tan } 1931c88a6e7dSHuazhong Tan hdev->rst_stats.vf_func_rst_cnt++; 1932dea846e8SHuazhong Tan } 1933dea846e8SHuazhong Tan 1934ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1935ada13ee3SHuazhong Tan /* inform hardware that preparatory work is done */ 1936ada13ee3SHuazhong Tan msleep(HCLGEVF_RESET_SYNC_TIME); 19376b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, true); 1938d41884eeSHuazhong Tan dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done\n", 1939d41884eeSHuazhong Tan hdev->reset_type); 1940dea846e8SHuazhong Tan 1941d41884eeSHuazhong Tan return 0; 1942dea846e8SHuazhong Tan } 1943dea846e8SHuazhong Tan 19443d77d0cbSHuazhong Tan static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev) 19453d77d0cbSHuazhong Tan { 19463d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "VF function reset count: %u\n", 19473d77d0cbSHuazhong Tan hdev->rst_stats.vf_func_rst_cnt); 19483d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "FLR reset count: %u\n", 19493d77d0cbSHuazhong Tan hdev->rst_stats.flr_rst_cnt); 19503d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "VF reset count: %u\n", 19513d77d0cbSHuazhong Tan hdev->rst_stats.vf_rst_cnt); 19523d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "reset done count: %u\n", 19533d77d0cbSHuazhong Tan hdev->rst_stats.rst_done_cnt); 19543d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "HW reset done count: %u\n", 19553d77d0cbSHuazhong Tan hdev->rst_stats.hw_rst_done_cnt); 19563d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "reset count: %u\n", 19573d77d0cbSHuazhong Tan hdev->rst_stats.rst_cnt); 19583d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "reset fail count: %u\n", 19593d77d0cbSHuazhong Tan hdev->rst_stats.rst_fail_cnt); 19603d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n", 19613d77d0cbSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE)); 19623d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n", 19639cee2e8dSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_STATE_REG)); 19643d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n", 19653d77d0cbSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_CMDQ_TX_DEPTH_REG)); 19663d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n", 19673d77d0cbSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING)); 19683d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state); 19693d77d0cbSHuazhong Tan } 19703d77d0cbSHuazhong Tan 1971bbe6540eSHuazhong Tan static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1972bbe6540eSHuazhong Tan { 19736b428b4fSHuazhong Tan /* recover handshake status with IMP when reset fail */ 19746b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, true); 1975bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt++; 1976adcf738bSGuojia Liao dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n", 1977bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt); 1978bbe6540eSHuazhong Tan 1979bbe6540eSHuazhong Tan if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1980bbe6540eSHuazhong Tan set_bit(hdev->reset_type, &hdev->reset_pending); 1981bbe6540eSHuazhong Tan 1982bbe6540eSHuazhong Tan if (hclgevf_is_reset_pending(hdev)) { 1983bbe6540eSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1984bbe6540eSHuazhong Tan hclgevf_reset_task_schedule(hdev); 19853d77d0cbSHuazhong Tan } else { 1986d5432455SGuojia Liao set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 19873d77d0cbSHuazhong Tan hclgevf_dump_rst_info(hdev); 1988bbe6540eSHuazhong Tan } 1989bbe6540eSHuazhong Tan } 1990bbe6540eSHuazhong Tan 19911cc9bc6eSHuazhong Tan static int hclgevf_reset_prepare(struct hclgevf_dev *hdev) 19926988eb2aSSalil Mehta { 19936988eb2aSSalil Mehta int ret; 19946988eb2aSSalil Mehta 1995c88a6e7dSHuazhong Tan hdev->rst_stats.rst_cnt++; 19966988eb2aSSalil Mehta 1997fe735c84SHuazhong Tan /* perform reset of the stack & ae device for a client */ 1998fe735c84SHuazhong Tan ret = hclgevf_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 1999fe735c84SHuazhong Tan if (ret) 2000fe735c84SHuazhong Tan return ret; 2001fe735c84SHuazhong Tan 20021cc9bc6eSHuazhong Tan rtnl_lock(); 20036988eb2aSSalil Mehta /* bring down the nic to stop any ongoing TX/RX */ 20046a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 200529118ab9SHuazhong Tan rtnl_unlock(); 20066a5f6fa3SHuazhong Tan if (ret) 20071cc9bc6eSHuazhong Tan return ret; 2008dea846e8SHuazhong Tan 20091cc9bc6eSHuazhong Tan return hclgevf_reset_prepare_wait(hdev); 20106988eb2aSSalil Mehta } 20116988eb2aSSalil Mehta 20121cc9bc6eSHuazhong Tan static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev) 20131cc9bc6eSHuazhong Tan { 20141cc9bc6eSHuazhong Tan int ret; 20151cc9bc6eSHuazhong Tan 2016c88a6e7dSHuazhong Tan hdev->rst_stats.hw_rst_done_cnt++; 2017fe735c84SHuazhong Tan ret = hclgevf_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 2018fe735c84SHuazhong Tan if (ret) 2019fe735c84SHuazhong Tan return ret; 2020c88a6e7dSHuazhong Tan 202129118ab9SHuazhong Tan rtnl_lock(); 20226988eb2aSSalil Mehta /* now, re-initialize the nic client and ae device */ 20236988eb2aSSalil Mehta ret = hclgevf_reset_stack(hdev); 20241cc9bc6eSHuazhong Tan rtnl_unlock(); 20256a5f6fa3SHuazhong Tan if (ret) { 20266988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 20271cc9bc6eSHuazhong Tan return ret; 20286a5f6fa3SHuazhong Tan } 20296988eb2aSSalil Mehta 2030fe735c84SHuazhong Tan ret = hclgevf_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 2031fe735c84SHuazhong Tan /* ignore RoCE notify error if it fails HCLGEVF_RESET_MAX_FAIL_CNT - 1 2032fe735c84SHuazhong Tan * times 2033fe735c84SHuazhong Tan */ 2034fe735c84SHuazhong Tan if (ret && 2035fe735c84SHuazhong Tan hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT - 1) 2036fe735c84SHuazhong Tan return ret; 2037fe735c84SHuazhong Tan 2038fe735c84SHuazhong Tan ret = hclgevf_notify_roce_client(hdev, HNAE3_UP_CLIENT); 2039fe735c84SHuazhong Tan if (ret) 2040fe735c84SHuazhong Tan return ret; 2041fe735c84SHuazhong Tan 2042b644a8d4SHuazhong Tan hdev->last_reset_time = jiffies; 2043c88a6e7dSHuazhong Tan hdev->rst_stats.rst_done_cnt++; 2044bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt = 0; 2045d5432455SGuojia Liao clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 2046b644a8d4SHuazhong Tan 20471cc9bc6eSHuazhong Tan return 0; 20481cc9bc6eSHuazhong Tan } 20491cc9bc6eSHuazhong Tan 20501cc9bc6eSHuazhong Tan static void hclgevf_reset(struct hclgevf_dev *hdev) 20511cc9bc6eSHuazhong Tan { 20521cc9bc6eSHuazhong Tan if (hclgevf_reset_prepare(hdev)) 20531cc9bc6eSHuazhong Tan goto err_reset; 20541cc9bc6eSHuazhong Tan 20551cc9bc6eSHuazhong Tan /* check if VF could successfully fetch the hardware reset completion 20561cc9bc6eSHuazhong Tan * status from the hardware 20571cc9bc6eSHuazhong Tan */ 20581cc9bc6eSHuazhong Tan if (hclgevf_reset_wait(hdev)) { 20591cc9bc6eSHuazhong Tan /* can't do much in this situation, will disable VF */ 20601cc9bc6eSHuazhong Tan dev_err(&hdev->pdev->dev, 20611cc9bc6eSHuazhong Tan "failed to fetch H/W reset completion status\n"); 20621cc9bc6eSHuazhong Tan goto err_reset; 20631cc9bc6eSHuazhong Tan } 20641cc9bc6eSHuazhong Tan 20651cc9bc6eSHuazhong Tan if (hclgevf_reset_rebuild(hdev)) 20661cc9bc6eSHuazhong Tan goto err_reset; 20671cc9bc6eSHuazhong Tan 20681cc9bc6eSHuazhong Tan return; 20691cc9bc6eSHuazhong Tan 20706a5f6fa3SHuazhong Tan err_reset: 2071bbe6540eSHuazhong Tan hclgevf_reset_err_handle(hdev); 20726988eb2aSSalil Mehta } 20736988eb2aSSalil Mehta 2074720bd583SHuazhong Tan static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 2075720bd583SHuazhong Tan unsigned long *addr) 2076720bd583SHuazhong Tan { 2077720bd583SHuazhong Tan enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 2078720bd583SHuazhong Tan 2079dea846e8SHuazhong Tan /* return the highest priority reset level amongst all */ 2080b90fcc5bSHuazhong Tan if (test_bit(HNAE3_VF_RESET, addr)) { 2081b90fcc5bSHuazhong Tan rst_level = HNAE3_VF_RESET; 2082b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_RESET, addr); 2083b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 2084b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 2085b90fcc5bSHuazhong Tan } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 2086dea846e8SHuazhong Tan rst_level = HNAE3_VF_FULL_RESET; 2087dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FULL_RESET, addr); 2088dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 2089aa5c4f17SHuazhong Tan } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 2090aa5c4f17SHuazhong Tan rst_level = HNAE3_VF_PF_FUNC_RESET; 2091aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 2092aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 2093dea846e8SHuazhong Tan } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 2094dea846e8SHuazhong Tan rst_level = HNAE3_VF_FUNC_RESET; 2095dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 20966ff3cf07SHuazhong Tan } else if (test_bit(HNAE3_FLR_RESET, addr)) { 20976ff3cf07SHuazhong Tan rst_level = HNAE3_FLR_RESET; 20986ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_RESET, addr); 2099720bd583SHuazhong Tan } 2100720bd583SHuazhong Tan 2101720bd583SHuazhong Tan return rst_level; 2102720bd583SHuazhong Tan } 2103720bd583SHuazhong Tan 21046ae4e733SShiju Jose static void hclgevf_reset_event(struct pci_dev *pdev, 21056ae4e733SShiju Jose struct hnae3_handle *handle) 21066d4c3981SSalil Mehta { 21076ff3cf07SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 21086ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 21096d4c3981SSalil Mehta 21106d4c3981SSalil Mehta dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 21116d4c3981SSalil Mehta 21126ff3cf07SHuazhong Tan if (hdev->default_reset_request) 21130742ed7cSHuazhong Tan hdev->reset_level = 2114720bd583SHuazhong Tan hclgevf_get_reset_level(hdev, 2115720bd583SHuazhong Tan &hdev->default_reset_request); 2116720bd583SHuazhong Tan else 2117dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 21186d4c3981SSalil Mehta 2119436667d2SSalil Mehta /* reset of this VF requested */ 2120436667d2SSalil Mehta set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 2121436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 21226d4c3981SSalil Mehta 21230742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 21246d4c3981SSalil Mehta } 21256d4c3981SSalil Mehta 2126720bd583SHuazhong Tan static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 2127720bd583SHuazhong Tan enum hnae3_reset_type rst_type) 2128720bd583SHuazhong Tan { 2129720bd583SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 2130720bd583SHuazhong Tan 2131720bd583SHuazhong Tan set_bit(rst_type, &hdev->default_reset_request); 2132720bd583SHuazhong Tan } 2133720bd583SHuazhong Tan 2134f28368bbSHuazhong Tan static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 2135f28368bbSHuazhong Tan { 2136f28368bbSHuazhong Tan writel(en ? 1 : 0, vector->addr); 2137f28368bbSHuazhong Tan } 2138f28368bbSHuazhong Tan 2139bb1890d5SJiaran Zhang static void hclgevf_reset_prepare_general(struct hnae3_ae_dev *ae_dev, 2140bb1890d5SJiaran Zhang enum hnae3_reset_type rst_type) 21416ff3cf07SHuazhong Tan { 2142bb1890d5SJiaran Zhang #define HCLGEVF_RESET_RETRY_WAIT_MS 500 2143bb1890d5SJiaran Zhang #define HCLGEVF_RESET_RETRY_CNT 5 2144f28368bbSHuazhong Tan 21456ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 2146f28368bbSHuazhong Tan int retry_cnt = 0; 2147f28368bbSHuazhong Tan int ret; 21486ff3cf07SHuazhong Tan 2149f28368bbSHuazhong Tan retry: 2150f28368bbSHuazhong Tan down(&hdev->reset_sem); 2151f28368bbSHuazhong Tan set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2152bb1890d5SJiaran Zhang hdev->reset_type = rst_type; 2153f28368bbSHuazhong Tan ret = hclgevf_reset_prepare(hdev); 2154f28368bbSHuazhong Tan if (ret) { 2155bb1890d5SJiaran Zhang dev_err(&hdev->pdev->dev, "fail to prepare to reset, ret=%d\n", 2156f28368bbSHuazhong Tan ret); 2157f28368bbSHuazhong Tan if (hdev->reset_pending || 2158bb1890d5SJiaran Zhang retry_cnt++ < HCLGEVF_RESET_RETRY_CNT) { 21596ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 2160f28368bbSHuazhong Tan "reset_pending:0x%lx, retry_cnt:%d\n", 2161f28368bbSHuazhong Tan hdev->reset_pending, retry_cnt); 2162f28368bbSHuazhong Tan clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2163f28368bbSHuazhong Tan up(&hdev->reset_sem); 2164bb1890d5SJiaran Zhang msleep(HCLGEVF_RESET_RETRY_WAIT_MS); 2165f28368bbSHuazhong Tan goto retry; 2166f28368bbSHuazhong Tan } 2167f28368bbSHuazhong Tan } 2168f28368bbSHuazhong Tan 2169bb1890d5SJiaran Zhang /* disable misc vector before reset done */ 2170f28368bbSHuazhong Tan hclgevf_enable_vector(&hdev->misc_vector, false); 2171bb1890d5SJiaran Zhang 2172bb1890d5SJiaran Zhang if (hdev->reset_type == HNAE3_FLR_RESET) 2173f28368bbSHuazhong Tan hdev->rst_stats.flr_rst_cnt++; 2174f28368bbSHuazhong Tan } 2175f28368bbSHuazhong Tan 2176bb1890d5SJiaran Zhang static void hclgevf_reset_done(struct hnae3_ae_dev *ae_dev) 2177f28368bbSHuazhong Tan { 2178f28368bbSHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 2179f28368bbSHuazhong Tan int ret; 2180f28368bbSHuazhong Tan 2181f28368bbSHuazhong Tan hclgevf_enable_vector(&hdev->misc_vector, true); 2182f28368bbSHuazhong Tan 2183f28368bbSHuazhong Tan ret = hclgevf_reset_rebuild(hdev); 2184f28368bbSHuazhong Tan if (ret) 2185f28368bbSHuazhong Tan dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", 2186f28368bbSHuazhong Tan ret); 2187f28368bbSHuazhong Tan 2188f28368bbSHuazhong Tan hdev->reset_type = HNAE3_NONE_RESET; 2189f28368bbSHuazhong Tan clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2190f28368bbSHuazhong Tan up(&hdev->reset_sem); 21916ff3cf07SHuazhong Tan } 21926ff3cf07SHuazhong Tan 2193e2cb1decSSalil Mehta static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 2194e2cb1decSSalil Mehta { 2195e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2196e2cb1decSSalil Mehta 2197e2cb1decSSalil Mehta return hdev->fw_version; 2198e2cb1decSSalil Mehta } 2199e2cb1decSSalil Mehta 2200e2cb1decSSalil Mehta static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 2201e2cb1decSSalil Mehta { 2202e2cb1decSSalil Mehta struct hclgevf_misc_vector *vector = &hdev->misc_vector; 2203e2cb1decSSalil Mehta 2204e2cb1decSSalil Mehta vector->vector_irq = pci_irq_vector(hdev->pdev, 2205e2cb1decSSalil Mehta HCLGEVF_MISC_VECTOR_NUM); 2206e2cb1decSSalil Mehta vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 2207e2cb1decSSalil Mehta /* vector status always valid for Vector 0 */ 2208e2cb1decSSalil Mehta hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 2209e2cb1decSSalil Mehta hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 2210e2cb1decSSalil Mehta 2211e2cb1decSSalil Mehta hdev->num_msi_left -= 1; 2212e2cb1decSSalil Mehta hdev->num_msi_used += 1; 2213e2cb1decSSalil Mehta } 2214e2cb1decSSalil Mehta 221535a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 221635a1e503SSalil Mehta { 2217ff200099SYunsheng Lin if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2218ff200099SYunsheng Lin !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, 2219ff200099SYunsheng Lin &hdev->state)) 22200ea68902SYunsheng Lin mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 222135a1e503SSalil Mehta } 222235a1e503SSalil Mehta 222307a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 2224e2cb1decSSalil Mehta { 2225ff200099SYunsheng Lin if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2226ff200099SYunsheng Lin !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, 2227ff200099SYunsheng Lin &hdev->state)) 22280ea68902SYunsheng Lin mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 222907a0556aSSalil Mehta } 2230e2cb1decSSalil Mehta 2231ff200099SYunsheng Lin static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 2232ff200099SYunsheng Lin unsigned long delay) 2233e2cb1decSSalil Mehta { 2234d5432455SGuojia Liao if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2235d5432455SGuojia Liao !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 22360ea68902SYunsheng Lin mod_delayed_work(hclgevf_wq, &hdev->service_task, delay); 2237e2cb1decSSalil Mehta } 2238e2cb1decSSalil Mehta 2239ff200099SYunsheng Lin static void hclgevf_reset_service_task(struct hclgevf_dev *hdev) 224035a1e503SSalil Mehta { 2241d6ad7c53SGuojia Liao #define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3 2242d6ad7c53SGuojia Liao 2243ff200099SYunsheng Lin if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state)) 2244ff200099SYunsheng Lin return; 2245ff200099SYunsheng Lin 2246f28368bbSHuazhong Tan down(&hdev->reset_sem); 2247f28368bbSHuazhong Tan set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 224835a1e503SSalil Mehta 2249436667d2SSalil Mehta if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 2250436667d2SSalil Mehta &hdev->reset_state)) { 2251cd7e963dSSalil Mehta /* PF has intimated that it is about to reset the hardware. 22529b2f3477SWeihang Li * We now have to poll & check if hardware has actually 22539b2f3477SWeihang Li * completed the reset sequence. On hardware reset completion, 22549b2f3477SWeihang Li * VF needs to reset the client and ae device. 225535a1e503SSalil Mehta */ 2256436667d2SSalil Mehta hdev->reset_attempts = 0; 2257436667d2SSalil Mehta 2258dea846e8SHuazhong Tan hdev->last_reset_time = jiffies; 2259dea846e8SHuazhong Tan while ((hdev->reset_type = 2260dea846e8SHuazhong Tan hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 22611cc9bc6eSHuazhong Tan != HNAE3_NONE_RESET) 22621cc9bc6eSHuazhong Tan hclgevf_reset(hdev); 2263436667d2SSalil Mehta } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 2264436667d2SSalil Mehta &hdev->reset_state)) { 2265436667d2SSalil Mehta /* we could be here when either of below happens: 22669b2f3477SWeihang Li * 1. reset was initiated due to watchdog timeout caused by 2267436667d2SSalil Mehta * a. IMP was earlier reset and our TX got choked down and 2268436667d2SSalil Mehta * which resulted in watchdog reacting and inducing VF 2269436667d2SSalil Mehta * reset. This also means our cmdq would be unreliable. 2270436667d2SSalil Mehta * b. problem in TX due to other lower layer(example link 2271436667d2SSalil Mehta * layer not functioning properly etc.) 2272436667d2SSalil Mehta * 2. VF reset might have been initiated due to some config 2273436667d2SSalil Mehta * change. 2274436667d2SSalil Mehta * 2275436667d2SSalil Mehta * NOTE: Theres no clear way to detect above cases than to react 2276436667d2SSalil Mehta * to the response of PF for this reset request. PF will ack the 2277436667d2SSalil Mehta * 1b and 2. cases but we will not get any intimation about 1a 2278436667d2SSalil Mehta * from PF as cmdq would be in unreliable state i.e. mailbox 2279436667d2SSalil Mehta * communication between PF and VF would be broken. 228046ee7350SGuojia Liao * 228146ee7350SGuojia Liao * if we are never geting into pending state it means either: 2282436667d2SSalil Mehta * 1. PF is not receiving our request which could be due to IMP 2283436667d2SSalil Mehta * reset 2284436667d2SSalil Mehta * 2. PF is screwed 2285436667d2SSalil Mehta * We cannot do much for 2. but to check first we can try reset 2286436667d2SSalil Mehta * our PCIe + stack and see if it alleviates the problem. 2287436667d2SSalil Mehta */ 2288d6ad7c53SGuojia Liao if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) { 2289436667d2SSalil Mehta /* prepare for full reset of stack + pcie interface */ 2290dea846e8SHuazhong Tan set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 2291436667d2SSalil Mehta 2292436667d2SSalil Mehta /* "defer" schedule the reset task again */ 2293436667d2SSalil Mehta set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2294436667d2SSalil Mehta } else { 2295436667d2SSalil Mehta hdev->reset_attempts++; 2296436667d2SSalil Mehta 2297dea846e8SHuazhong Tan set_bit(hdev->reset_level, &hdev->reset_pending); 2298dea846e8SHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2299436667d2SSalil Mehta } 2300dea846e8SHuazhong Tan hclgevf_reset_task_schedule(hdev); 2301436667d2SSalil Mehta } 230235a1e503SSalil Mehta 2303afb6afdbSHuazhong Tan hdev->reset_type = HNAE3_NONE_RESET; 230435a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2305f28368bbSHuazhong Tan up(&hdev->reset_sem); 230635a1e503SSalil Mehta } 230735a1e503SSalil Mehta 2308ff200099SYunsheng Lin static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev) 2309e2cb1decSSalil Mehta { 2310ff200099SYunsheng Lin if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state)) 2311ff200099SYunsheng Lin return; 2312e2cb1decSSalil Mehta 2313e2cb1decSSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 2314e2cb1decSSalil Mehta return; 2315e2cb1decSSalil Mehta 231607a0556aSSalil Mehta hclgevf_mbx_async_handler(hdev); 2317e2cb1decSSalil Mehta 2318e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2319e2cb1decSSalil Mehta } 2320e2cb1decSSalil Mehta 2321ff200099SYunsheng Lin static void hclgevf_keep_alive(struct hclgevf_dev *hdev) 2322a6d818e3SYunsheng Lin { 2323d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 2324a6d818e3SYunsheng Lin int ret; 2325a6d818e3SYunsheng Lin 23261416d333SHuazhong Tan if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 2327c59a85c0SJian Shen return; 2328c59a85c0SJian Shen 2329d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_KEEP_ALIVE, 0); 2330d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2331a6d818e3SYunsheng Lin if (ret) 2332a6d818e3SYunsheng Lin dev_err(&hdev->pdev->dev, 2333a6d818e3SYunsheng Lin "VF sends keep alive cmd failed(=%d)\n", ret); 2334a6d818e3SYunsheng Lin } 2335a6d818e3SYunsheng Lin 2336ff200099SYunsheng Lin static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev) 2337e2cb1decSSalil Mehta { 2338ff200099SYunsheng Lin unsigned long delta = round_jiffies_relative(HZ); 2339ff200099SYunsheng Lin struct hnae3_handle *handle = &hdev->nic; 2340e2cb1decSSalil Mehta 2341e6394363SGuangbin Huang if (test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 2342e6394363SGuangbin Huang return; 2343e6394363SGuangbin Huang 2344ff200099SYunsheng Lin if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 2345ff200099SYunsheng Lin delta = jiffies - hdev->last_serv_processed; 2346db01afebSliuzhongzhu 2347ff200099SYunsheng Lin if (delta < round_jiffies_relative(HZ)) { 2348ff200099SYunsheng Lin delta = round_jiffies_relative(HZ) - delta; 2349ff200099SYunsheng Lin goto out; 2350db01afebSliuzhongzhu } 2351ff200099SYunsheng Lin } 2352ff200099SYunsheng Lin 2353ff200099SYunsheng Lin hdev->serv_processed_cnt++; 2354ff200099SYunsheng Lin if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL)) 2355ff200099SYunsheng Lin hclgevf_keep_alive(hdev); 2356ff200099SYunsheng Lin 2357ff200099SYunsheng Lin if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) { 2358ff200099SYunsheng Lin hdev->last_serv_processed = jiffies; 2359ff200099SYunsheng Lin goto out; 2360ff200099SYunsheng Lin } 2361ff200099SYunsheng Lin 2362ff200099SYunsheng Lin if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL)) 2363ff200099SYunsheng Lin hclgevf_tqps_update_stats(handle); 2364e2cb1decSSalil Mehta 236501305e16SGuangbin Huang /* VF does not need to request link status when this bit is set, because 236601305e16SGuangbin Huang * PF will push its link status to VFs when link status changed. 2367e2cb1decSSalil Mehta */ 236801305e16SGuangbin Huang if (!test_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state)) 2369e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 2370e2cb1decSSalil Mehta 23719194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 23729194d18bSliuzhongzhu 2373fe4144d4SJian Shen hclgevf_sync_vlan_filter(hdev); 2374fe4144d4SJian Shen 2375ee4bcd3bSJian Shen hclgevf_sync_mac_table(hdev); 2376ee4bcd3bSJian Shen 2377c631c696SJian Shen hclgevf_sync_promisc_mode(hdev); 2378c631c696SJian Shen 2379ff200099SYunsheng Lin hdev->last_serv_processed = jiffies; 2380436667d2SSalil Mehta 2381ff200099SYunsheng Lin out: 2382ff200099SYunsheng Lin hclgevf_task_schedule(hdev, delta); 2383ff200099SYunsheng Lin } 2384b3c3fe8eSYunsheng Lin 2385ff200099SYunsheng Lin static void hclgevf_service_task(struct work_struct *work) 2386ff200099SYunsheng Lin { 2387ff200099SYunsheng Lin struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev, 2388ff200099SYunsheng Lin service_task.work); 2389ff200099SYunsheng Lin 2390ff200099SYunsheng Lin hclgevf_reset_service_task(hdev); 2391ff200099SYunsheng Lin hclgevf_mailbox_service_task(hdev); 2392ff200099SYunsheng Lin hclgevf_periodic_service_task(hdev); 2393ff200099SYunsheng Lin 2394ff200099SYunsheng Lin /* Handle reset and mbx again in case periodical task delays the 2395ff200099SYunsheng Lin * handling by calling hclgevf_task_schedule() in 2396ff200099SYunsheng Lin * hclgevf_periodic_service_task() 2397ff200099SYunsheng Lin */ 2398ff200099SYunsheng Lin hclgevf_reset_service_task(hdev); 2399ff200099SYunsheng Lin hclgevf_mailbox_service_task(hdev); 2400e2cb1decSSalil Mehta } 2401e2cb1decSSalil Mehta 2402e2cb1decSSalil Mehta static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 2403e2cb1decSSalil Mehta { 2404e2cb1decSSalil Mehta hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 2405e2cb1decSSalil Mehta } 2406e2cb1decSSalil Mehta 2407b90fcc5bSHuazhong Tan static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 2408b90fcc5bSHuazhong Tan u32 *clearval) 2409e2cb1decSSalil Mehta { 241013050921SHuazhong Tan u32 val, cmdq_stat_reg, rst_ing_reg; 2411e2cb1decSSalil Mehta 2412e2cb1decSSalil Mehta /* fetch the events from their corresponding regs */ 241313050921SHuazhong Tan cmdq_stat_reg = hclgevf_read_dev(&hdev->hw, 24149cee2e8dSHuazhong Tan HCLGEVF_VECTOR0_CMDQ_STATE_REG); 241513050921SHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 2416b90fcc5bSHuazhong Tan rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 2417b90fcc5bSHuazhong Tan dev_info(&hdev->pdev->dev, 2418b90fcc5bSHuazhong Tan "receive reset interrupt 0x%x!\n", rst_ing_reg); 2419b90fcc5bSHuazhong Tan set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 2420b90fcc5bSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2421ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 242213050921SHuazhong Tan *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B); 2423c88a6e7dSHuazhong Tan hdev->rst_stats.vf_rst_cnt++; 242472e2fb07SHuazhong Tan /* set up VF hardware reset status, its PF will clear 242572e2fb07SHuazhong Tan * this status when PF has initialized done. 242672e2fb07SHuazhong Tan */ 242772e2fb07SHuazhong Tan val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING); 242872e2fb07SHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING, 242972e2fb07SHuazhong Tan val | HCLGEVF_VF_RST_ING_BIT); 2430b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_RST; 2431b90fcc5bSHuazhong Tan } 2432b90fcc5bSHuazhong Tan 2433e2cb1decSSalil Mehta /* check for vector0 mailbox(=CMDQ RX) event source */ 243413050921SHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 243513050921SHuazhong Tan /* for revision 0x21, clearing interrupt is writing bit 0 243613050921SHuazhong Tan * to the clear register, writing bit 1 means to keep the 243713050921SHuazhong Tan * old value. 243813050921SHuazhong Tan * for revision 0x20, the clear register is a read & write 243913050921SHuazhong Tan * register, so we should just write 0 to the bit we are 244013050921SHuazhong Tan * handling, and keep other bits as cmdq_stat_reg. 244113050921SHuazhong Tan */ 2442295ba232SGuangbin Huang if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) 244313050921SHuazhong Tan *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 244413050921SHuazhong Tan else 244513050921SHuazhong Tan *clearval = cmdq_stat_reg & 244613050921SHuazhong Tan ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 244713050921SHuazhong Tan 2448b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_MBX; 2449e2cb1decSSalil Mehta } 2450e2cb1decSSalil Mehta 2451e45afb39SHuazhong Tan /* print other vector0 event source */ 2452e45afb39SHuazhong Tan dev_info(&hdev->pdev->dev, 2453e45afb39SHuazhong Tan "vector 0 interrupt from unknown source, cmdq_src = %#x\n", 2454e45afb39SHuazhong Tan cmdq_stat_reg); 2455e2cb1decSSalil Mehta 2456b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_OTHER; 2457e2cb1decSSalil Mehta } 2458e2cb1decSSalil Mehta 2459e2cb1decSSalil Mehta static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 2460e2cb1decSSalil Mehta { 2461b90fcc5bSHuazhong Tan enum hclgevf_evt_cause event_cause; 2462e2cb1decSSalil Mehta struct hclgevf_dev *hdev = data; 2463e2cb1decSSalil Mehta u32 clearval; 2464e2cb1decSSalil Mehta 2465e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 2466b90fcc5bSHuazhong Tan event_cause = hclgevf_check_evt_cause(hdev, &clearval); 2467e2cb1decSSalil Mehta 2468b90fcc5bSHuazhong Tan switch (event_cause) { 2469b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_RST: 2470b90fcc5bSHuazhong Tan hclgevf_reset_task_schedule(hdev); 2471b90fcc5bSHuazhong Tan break; 2472b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_MBX: 247307a0556aSSalil Mehta hclgevf_mbx_handler(hdev); 2474b90fcc5bSHuazhong Tan break; 2475b90fcc5bSHuazhong Tan default: 2476b90fcc5bSHuazhong Tan break; 2477b90fcc5bSHuazhong Tan } 2478e2cb1decSSalil Mehta 2479b90fcc5bSHuazhong Tan if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 2480e2cb1decSSalil Mehta hclgevf_clear_event_cause(hdev, clearval); 2481e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2482b90fcc5bSHuazhong Tan } 2483e2cb1decSSalil Mehta 2484e2cb1decSSalil Mehta return IRQ_HANDLED; 2485e2cb1decSSalil Mehta } 2486e2cb1decSSalil Mehta 2487e2cb1decSSalil Mehta static int hclgevf_configure(struct hclgevf_dev *hdev) 2488e2cb1decSSalil Mehta { 2489e2cb1decSSalil Mehta int ret; 2490e2cb1decSSalil Mehta 249132e6d104SJian Shen ret = hclgevf_get_basic_info(hdev); 249232e6d104SJian Shen if (ret) 249332e6d104SJian Shen return ret; 249432e6d104SJian Shen 249592f11ea1SJian Shen /* get current port based vlan state from PF */ 249692f11ea1SJian Shen ret = hclgevf_get_port_base_vlan_filter_state(hdev); 249792f11ea1SJian Shen if (ret) 249892f11ea1SJian Shen return ret; 249992f11ea1SJian Shen 2500e2cb1decSSalil Mehta /* get queue configuration from PF */ 25016cee6fc3SJian Shen ret = hclgevf_get_queue_info(hdev); 2502e2cb1decSSalil Mehta if (ret) 2503e2cb1decSSalil Mehta return ret; 2504c0425944SPeng Li 2505c0425944SPeng Li /* get queue depth info from PF */ 2506c0425944SPeng Li ret = hclgevf_get_queue_depth(hdev); 2507c0425944SPeng Li if (ret) 2508c0425944SPeng Li return ret; 2509c0425944SPeng Li 251032e6d104SJian Shen return hclgevf_get_pf_media_type(hdev); 2511e2cb1decSSalil Mehta } 2512e2cb1decSSalil Mehta 25137a01c897SSalil Mehta static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 25147a01c897SSalil Mehta { 25157a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 25161154bb26SPeng Li struct hclgevf_dev *hdev; 25177a01c897SSalil Mehta 25187a01c897SSalil Mehta hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 25197a01c897SSalil Mehta if (!hdev) 25207a01c897SSalil Mehta return -ENOMEM; 25217a01c897SSalil Mehta 25227a01c897SSalil Mehta hdev->pdev = pdev; 25237a01c897SSalil Mehta hdev->ae_dev = ae_dev; 25247a01c897SSalil Mehta ae_dev->priv = hdev; 25257a01c897SSalil Mehta 25267a01c897SSalil Mehta return 0; 25277a01c897SSalil Mehta } 25287a01c897SSalil Mehta 2529e2cb1decSSalil Mehta static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 2530e2cb1decSSalil Mehta { 2531e2cb1decSSalil Mehta struct hnae3_handle *roce = &hdev->roce; 2532e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 2533e2cb1decSSalil Mehta 253407acf909SJian Shen roce->rinfo.num_vectors = hdev->num_roce_msix; 2535e2cb1decSSalil Mehta 2536e2cb1decSSalil Mehta if (hdev->num_msi_left < roce->rinfo.num_vectors || 2537e2cb1decSSalil Mehta hdev->num_msi_left == 0) 2538e2cb1decSSalil Mehta return -EINVAL; 2539e2cb1decSSalil Mehta 254007acf909SJian Shen roce->rinfo.base_vector = hdev->roce_base_vector; 2541e2cb1decSSalil Mehta 2542e2cb1decSSalil Mehta roce->rinfo.netdev = nic->kinfo.netdev; 2543e2cb1decSSalil Mehta roce->rinfo.roce_io_base = hdev->hw.io_base; 254430ae7f8aSHuazhong Tan roce->rinfo.roce_mem_base = hdev->hw.mem_base; 2545e2cb1decSSalil Mehta 2546e2cb1decSSalil Mehta roce->pdev = nic->pdev; 2547e2cb1decSSalil Mehta roce->ae_algo = nic->ae_algo; 2548e2cb1decSSalil Mehta roce->numa_node_mask = nic->numa_node_mask; 2549e2cb1decSSalil Mehta 2550e2cb1decSSalil Mehta return 0; 2551e2cb1decSSalil Mehta } 2552e2cb1decSSalil Mehta 2553b26a6feaSPeng Li static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 2554b26a6feaSPeng Li { 2555b26a6feaSPeng Li struct hclgevf_cfg_gro_status_cmd *req; 2556b26a6feaSPeng Li struct hclgevf_desc desc; 2557b26a6feaSPeng Li int ret; 2558b26a6feaSPeng Li 2559b26a6feaSPeng Li if (!hnae3_dev_gro_supported(hdev)) 2560b26a6feaSPeng Li return 0; 2561b26a6feaSPeng Li 2562b26a6feaSPeng Li hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 2563b26a6feaSPeng Li false); 2564b26a6feaSPeng Li req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2565b26a6feaSPeng Li 2566fb9e44d6SHuazhong Tan req->gro_en = en ? 1 : 0; 2567b26a6feaSPeng Li 2568b26a6feaSPeng Li ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2569b26a6feaSPeng Li if (ret) 2570b26a6feaSPeng Li dev_err(&hdev->pdev->dev, 2571b26a6feaSPeng Li "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2572b26a6feaSPeng Li 2573b26a6feaSPeng Li return ret; 2574b26a6feaSPeng Li } 2575b26a6feaSPeng Li 257687ce161eSGuangbin Huang static int hclgevf_rss_init_cfg(struct hclgevf_dev *hdev) 2577e2cb1decSSalil Mehta { 257887ce161eSGuangbin Huang u16 rss_ind_tbl_size = hdev->ae_dev->dev_specs.rss_ind_tbl_size; 2579e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2580944de484SGuojia Liao struct hclgevf_rss_tuple_cfg *tuple_sets; 25814093d1a2SGuangbin Huang u32 i; 2582e2cb1decSSalil Mehta 2583944de484SGuojia Liao rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 25844093d1a2SGuangbin Huang rss_cfg->rss_size = hdev->nic.kinfo.rss_size; 2585944de484SGuojia Liao tuple_sets = &rss_cfg->rss_tuple_sets; 2586295ba232SGuangbin Huang if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 258787ce161eSGuangbin Huang u8 *rss_ind_tbl; 258887ce161eSGuangbin Huang 2589472d7eceSJian Shen rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 259087ce161eSGuangbin Huang 259187ce161eSGuangbin Huang rss_ind_tbl = devm_kcalloc(&hdev->pdev->dev, rss_ind_tbl_size, 259287ce161eSGuangbin Huang sizeof(*rss_ind_tbl), GFP_KERNEL); 259387ce161eSGuangbin Huang if (!rss_ind_tbl) 259487ce161eSGuangbin Huang return -ENOMEM; 259587ce161eSGuangbin Huang 259687ce161eSGuangbin Huang rss_cfg->rss_indirection_tbl = rss_ind_tbl; 2597472d7eceSJian Shen memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 2598374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 2599374ad291SJian Shen 2600944de484SGuojia Liao tuple_sets->ipv4_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2601944de484SGuojia Liao tuple_sets->ipv4_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2602944de484SGuojia Liao tuple_sets->ipv4_sctp_en = HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2603944de484SGuojia Liao tuple_sets->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2604944de484SGuojia Liao tuple_sets->ipv6_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2605944de484SGuojia Liao tuple_sets->ipv6_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2606ab6e32d2SJian Shen tuple_sets->ipv6_sctp_en = 2607ab6e32d2SJian Shen hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 ? 2608ab6e32d2SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP_NO_PORT : 2609ab6e32d2SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2610944de484SGuojia Liao tuple_sets->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2611374ad291SJian Shen } 2612374ad291SJian Shen 26139b2f3477SWeihang Li /* Initialize RSS indirect table */ 261487ce161eSGuangbin Huang for (i = 0; i < rss_ind_tbl_size; i++) 26154093d1a2SGuangbin Huang rss_cfg->rss_indirection_tbl[i] = i % rss_cfg->rss_size; 261687ce161eSGuangbin Huang 261787ce161eSGuangbin Huang return 0; 2618944de484SGuojia Liao } 2619944de484SGuojia Liao 2620944de484SGuojia Liao static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2621944de484SGuojia Liao { 2622944de484SGuojia Liao struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2623944de484SGuojia Liao int ret; 2624944de484SGuojia Liao 2625295ba232SGuangbin Huang if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 2626944de484SGuojia Liao ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 2627944de484SGuojia Liao rss_cfg->rss_hash_key); 2628944de484SGuojia Liao if (ret) 2629944de484SGuojia Liao return ret; 2630944de484SGuojia Liao 2631944de484SGuojia Liao ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 2632944de484SGuojia Liao if (ret) 2633944de484SGuojia Liao return ret; 2634944de484SGuojia Liao } 2635e2cb1decSSalil Mehta 2636e2cb1decSSalil Mehta ret = hclgevf_set_rss_indir_table(hdev); 2637e2cb1decSSalil Mehta if (ret) 2638e2cb1decSSalil Mehta return ret; 2639e2cb1decSSalil Mehta 26404093d1a2SGuangbin Huang return hclgevf_set_rss_tc_mode(hdev, rss_cfg->rss_size); 2641e2cb1decSSalil Mehta } 2642e2cb1decSSalil Mehta 2643e2cb1decSSalil Mehta static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2644e2cb1decSSalil Mehta { 2645bbfd4506SJian Shen struct hnae3_handle *nic = &hdev->nic; 2646bbfd4506SJian Shen int ret; 2647bbfd4506SJian Shen 2648bbfd4506SJian Shen ret = hclgevf_en_hw_strip_rxvtag(nic, true); 2649bbfd4506SJian Shen if (ret) { 2650bbfd4506SJian Shen dev_err(&hdev->pdev->dev, 2651bbfd4506SJian Shen "failed to enable rx vlan offload, ret = %d\n", ret); 2652bbfd4506SJian Shen return ret; 2653bbfd4506SJian Shen } 2654bbfd4506SJian Shen 2655e2cb1decSSalil Mehta return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2656e2cb1decSSalil Mehta false); 2657e2cb1decSSalil Mehta } 2658e2cb1decSSalil Mehta 2659ff200099SYunsheng Lin static void hclgevf_flush_link_update(struct hclgevf_dev *hdev) 2660ff200099SYunsheng Lin { 2661ff200099SYunsheng Lin #define HCLGEVF_FLUSH_LINK_TIMEOUT 100000 2662ff200099SYunsheng Lin 2663ff200099SYunsheng Lin unsigned long last = hdev->serv_processed_cnt; 2664ff200099SYunsheng Lin int i = 0; 2665ff200099SYunsheng Lin 2666ff200099SYunsheng Lin while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) && 2667ff200099SYunsheng Lin i++ < HCLGEVF_FLUSH_LINK_TIMEOUT && 2668ff200099SYunsheng Lin last == hdev->serv_processed_cnt) 2669ff200099SYunsheng Lin usleep_range(1, 1); 2670ff200099SYunsheng Lin } 2671ff200099SYunsheng Lin 26728cdb992fSJian Shen static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 26738cdb992fSJian Shen { 26748cdb992fSJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 26758cdb992fSJian Shen 26768cdb992fSJian Shen if (enable) { 2677ff200099SYunsheng Lin hclgevf_task_schedule(hdev, 0); 26788cdb992fSJian Shen } else { 2679b3c3fe8eSYunsheng Lin set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2680ff200099SYunsheng Lin 2681ff200099SYunsheng Lin /* flush memory to make sure DOWN is seen by service task */ 2682ff200099SYunsheng Lin smp_mb__before_atomic(); 2683ff200099SYunsheng Lin hclgevf_flush_link_update(hdev); 26848cdb992fSJian Shen } 26858cdb992fSJian Shen } 26868cdb992fSJian Shen 2687e2cb1decSSalil Mehta static int hclgevf_ae_start(struct hnae3_handle *handle) 2688e2cb1decSSalil Mehta { 2689e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2690e2cb1decSSalil Mehta 2691ed7bedd2SGuangbin Huang clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 269201305e16SGuangbin Huang clear_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state); 2693ed7bedd2SGuangbin Huang 2694e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 2695e2cb1decSSalil Mehta 2696e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 2697e2cb1decSSalil Mehta 26989194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 26999194d18bSliuzhongzhu 2700e2cb1decSSalil Mehta return 0; 2701e2cb1decSSalil Mehta } 2702e2cb1decSSalil Mehta 2703e2cb1decSSalil Mehta static void hclgevf_ae_stop(struct hnae3_handle *handle) 2704e2cb1decSSalil Mehta { 2705e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2706e2cb1decSSalil Mehta 27072f7e4896SFuyun Liang set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 27082f7e4896SFuyun Liang 2709146e92c1SHuazhong Tan if (hdev->reset_type != HNAE3_VF_RESET) 27108fa86551SYufeng Mo hclgevf_reset_tqp(handle); 271139cfbc9cSHuazhong Tan 2712e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 27138cc6c1f7SFuyun Liang hclgevf_update_link_status(hdev, 0); 2714e2cb1decSSalil Mehta } 2715e2cb1decSSalil Mehta 2716a6d818e3SYunsheng Lin static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2717a6d818e3SYunsheng Lin { 2718d3410018SYufeng Mo #define HCLGEVF_STATE_ALIVE 1 2719d3410018SYufeng Mo #define HCLGEVF_STATE_NOT_ALIVE 0 2720a6d818e3SYunsheng Lin 2721d3410018SYufeng Mo struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2722d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 2723d3410018SYufeng Mo 2724d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_ALIVE, 0); 2725d3410018SYufeng Mo send_msg.data[0] = alive ? HCLGEVF_STATE_ALIVE : 2726d3410018SYufeng Mo HCLGEVF_STATE_NOT_ALIVE; 2727d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2728a6d818e3SYunsheng Lin } 2729a6d818e3SYunsheng Lin 2730a6d818e3SYunsheng Lin static int hclgevf_client_start(struct hnae3_handle *handle) 2731a6d818e3SYunsheng Lin { 2732f621df96SQinglang Miao return hclgevf_set_alive(handle, true); 2733a6d818e3SYunsheng Lin } 2734a6d818e3SYunsheng Lin 2735a6d818e3SYunsheng Lin static void hclgevf_client_stop(struct hnae3_handle *handle) 2736a6d818e3SYunsheng Lin { 2737a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2738a6d818e3SYunsheng Lin int ret; 2739a6d818e3SYunsheng Lin 2740a6d818e3SYunsheng Lin ret = hclgevf_set_alive(handle, false); 2741a6d818e3SYunsheng Lin if (ret) 2742a6d818e3SYunsheng Lin dev_warn(&hdev->pdev->dev, 2743a6d818e3SYunsheng Lin "%s failed %d\n", __func__, ret); 2744a6d818e3SYunsheng Lin } 2745a6d818e3SYunsheng Lin 2746e2cb1decSSalil Mehta static void hclgevf_state_init(struct hclgevf_dev *hdev) 2747e2cb1decSSalil Mehta { 2748e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2749e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2750d5432455SGuojia Liao clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 2751e2cb1decSSalil Mehta 2752b3c3fe8eSYunsheng Lin INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task); 275335a1e503SSalil Mehta 2754e2cb1decSSalil Mehta mutex_init(&hdev->mbx_resp.mbx_mutex); 2755f28368bbSHuazhong Tan sema_init(&hdev->reset_sem, 1); 2756e2cb1decSSalil Mehta 2757ee4bcd3bSJian Shen spin_lock_init(&hdev->mac_table.mac_list_lock); 2758ee4bcd3bSJian Shen INIT_LIST_HEAD(&hdev->mac_table.uc_mac_list); 2759ee4bcd3bSJian Shen INIT_LIST_HEAD(&hdev->mac_table.mc_mac_list); 2760ee4bcd3bSJian Shen 2761e2cb1decSSalil Mehta /* bring the device down */ 2762e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2763e2cb1decSSalil Mehta } 2764e2cb1decSSalil Mehta 2765e2cb1decSSalil Mehta static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2766e2cb1decSSalil Mehta { 2767e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2768acfc3d55SHuazhong Tan set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2769e2cb1decSSalil Mehta 2770b3c3fe8eSYunsheng Lin if (hdev->service_task.work.func) 2771b3c3fe8eSYunsheng Lin cancel_delayed_work_sync(&hdev->service_task); 2772e2cb1decSSalil Mehta 2773e2cb1decSSalil Mehta mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2774e2cb1decSSalil Mehta } 2775e2cb1decSSalil Mehta 2776e2cb1decSSalil Mehta static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2777e2cb1decSSalil Mehta { 2778e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2779e2cb1decSSalil Mehta int vectors; 2780e2cb1decSSalil Mehta int i; 2781e2cb1decSSalil Mehta 2782580a05f9SYonglong Liu if (hnae3_dev_roce_supported(hdev)) 278307acf909SJian Shen vectors = pci_alloc_irq_vectors(pdev, 278407acf909SJian Shen hdev->roce_base_msix_offset + 1, 278507acf909SJian Shen hdev->num_msi, 278607acf909SJian Shen PCI_IRQ_MSIX); 278707acf909SJian Shen else 2788580a05f9SYonglong Liu vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2789580a05f9SYonglong Liu hdev->num_msi, 2790e2cb1decSSalil Mehta PCI_IRQ_MSI | PCI_IRQ_MSIX); 279107acf909SJian Shen 2792e2cb1decSSalil Mehta if (vectors < 0) { 2793e2cb1decSSalil Mehta dev_err(&pdev->dev, 2794e2cb1decSSalil Mehta "failed(%d) to allocate MSI/MSI-X vectors\n", 2795e2cb1decSSalil Mehta vectors); 2796e2cb1decSSalil Mehta return vectors; 2797e2cb1decSSalil Mehta } 2798e2cb1decSSalil Mehta if (vectors < hdev->num_msi) 2799e2cb1decSSalil Mehta dev_warn(&hdev->pdev->dev, 2800adcf738bSGuojia Liao "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2801e2cb1decSSalil Mehta hdev->num_msi, vectors); 2802e2cb1decSSalil Mehta 2803e2cb1decSSalil Mehta hdev->num_msi = vectors; 2804e2cb1decSSalil Mehta hdev->num_msi_left = vectors; 2805580a05f9SYonglong Liu 2806e2cb1decSSalil Mehta hdev->base_msi_vector = pdev->irq; 280707acf909SJian Shen hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2808e2cb1decSSalil Mehta 2809e2cb1decSSalil Mehta hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2810e2cb1decSSalil Mehta sizeof(u16), GFP_KERNEL); 2811e2cb1decSSalil Mehta if (!hdev->vector_status) { 2812e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2813e2cb1decSSalil Mehta return -ENOMEM; 2814e2cb1decSSalil Mehta } 2815e2cb1decSSalil Mehta 2816e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 2817e2cb1decSSalil Mehta hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2818e2cb1decSSalil Mehta 2819e2cb1decSSalil Mehta hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2820e2cb1decSSalil Mehta sizeof(int), GFP_KERNEL); 2821e2cb1decSSalil Mehta if (!hdev->vector_irq) { 2822862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2823e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2824e2cb1decSSalil Mehta return -ENOMEM; 2825e2cb1decSSalil Mehta } 2826e2cb1decSSalil Mehta 2827e2cb1decSSalil Mehta return 0; 2828e2cb1decSSalil Mehta } 2829e2cb1decSSalil Mehta 2830e2cb1decSSalil Mehta static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2831e2cb1decSSalil Mehta { 2832e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2833e2cb1decSSalil Mehta 2834862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2835862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_irq); 2836e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2837e2cb1decSSalil Mehta } 2838e2cb1decSSalil Mehta 2839e2cb1decSSalil Mehta static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2840e2cb1decSSalil Mehta { 2841cdd332acSGuojia Liao int ret; 2842e2cb1decSSalil Mehta 2843e2cb1decSSalil Mehta hclgevf_get_misc_vector(hdev); 2844e2cb1decSSalil Mehta 2845f97c4d82SYonglong Liu snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 2846f97c4d82SYonglong Liu HCLGEVF_NAME, pci_name(hdev->pdev)); 2847e2cb1decSSalil Mehta ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2848f97c4d82SYonglong Liu 0, hdev->misc_vector.name, hdev); 2849e2cb1decSSalil Mehta if (ret) { 2850e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2851e2cb1decSSalil Mehta hdev->misc_vector.vector_irq); 2852e2cb1decSSalil Mehta return ret; 2853e2cb1decSSalil Mehta } 2854e2cb1decSSalil Mehta 28551819e409SXi Wang hclgevf_clear_event_cause(hdev, 0); 28561819e409SXi Wang 2857e2cb1decSSalil Mehta /* enable misc. vector(vector 0) */ 2858e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2859e2cb1decSSalil Mehta 2860e2cb1decSSalil Mehta return ret; 2861e2cb1decSSalil Mehta } 2862e2cb1decSSalil Mehta 2863e2cb1decSSalil Mehta static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2864e2cb1decSSalil Mehta { 2865e2cb1decSSalil Mehta /* disable misc vector(vector 0) */ 2866e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 28671819e409SXi Wang synchronize_irq(hdev->misc_vector.vector_irq); 2868e2cb1decSSalil Mehta free_irq(hdev->misc_vector.vector_irq, hdev); 2869e2cb1decSSalil Mehta hclgevf_free_vector(hdev, 0); 2870e2cb1decSSalil Mehta } 2871e2cb1decSSalil Mehta 2872bb87be87SYonglong Liu static void hclgevf_info_show(struct hclgevf_dev *hdev) 2873bb87be87SYonglong Liu { 2874bb87be87SYonglong Liu struct device *dev = &hdev->pdev->dev; 2875bb87be87SYonglong Liu 2876bb87be87SYonglong Liu dev_info(dev, "VF info begin:\n"); 2877bb87be87SYonglong Liu 2878adcf738bSGuojia Liao dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 2879adcf738bSGuojia Liao dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 2880adcf738bSGuojia Liao dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 2881adcf738bSGuojia Liao dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 2882adcf738bSGuojia Liao dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 2883adcf738bSGuojia Liao dev_info(dev, "PF media type of this VF: %u\n", 2884bb87be87SYonglong Liu hdev->hw.mac.media_type); 2885bb87be87SYonglong Liu 2886bb87be87SYonglong Liu dev_info(dev, "VF info end.\n"); 2887bb87be87SYonglong Liu } 2888bb87be87SYonglong Liu 28891db58f86SHuazhong Tan static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 28901db58f86SHuazhong Tan struct hnae3_client *client) 28911db58f86SHuazhong Tan { 28921db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 28934cd5beaaSGuangbin Huang int rst_cnt = hdev->rst_stats.rst_cnt; 28941db58f86SHuazhong Tan int ret; 28951db58f86SHuazhong Tan 28961db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->nic); 28971db58f86SHuazhong Tan if (ret) 28981db58f86SHuazhong Tan return ret; 28991db58f86SHuazhong Tan 29001db58f86SHuazhong Tan set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 29014cd5beaaSGuangbin Huang if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 29024cd5beaaSGuangbin Huang rst_cnt != hdev->rst_stats.rst_cnt) { 29034cd5beaaSGuangbin Huang clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 29044cd5beaaSGuangbin Huang 29054cd5beaaSGuangbin Huang client->ops->uninit_instance(&hdev->nic, 0); 29064cd5beaaSGuangbin Huang return -EBUSY; 29074cd5beaaSGuangbin Huang } 29084cd5beaaSGuangbin Huang 29091db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 29101db58f86SHuazhong Tan 29111db58f86SHuazhong Tan if (netif_msg_drv(&hdev->nic)) 29121db58f86SHuazhong Tan hclgevf_info_show(hdev); 29131db58f86SHuazhong Tan 29141db58f86SHuazhong Tan return 0; 29151db58f86SHuazhong Tan } 29161db58f86SHuazhong Tan 29171db58f86SHuazhong Tan static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 29181db58f86SHuazhong Tan struct hnae3_client *client) 29191db58f86SHuazhong Tan { 29201db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 29211db58f86SHuazhong Tan int ret; 29221db58f86SHuazhong Tan 29231db58f86SHuazhong Tan if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 29241db58f86SHuazhong Tan !hdev->nic_client) 29251db58f86SHuazhong Tan return 0; 29261db58f86SHuazhong Tan 29271db58f86SHuazhong Tan ret = hclgevf_init_roce_base_info(hdev); 29281db58f86SHuazhong Tan if (ret) 29291db58f86SHuazhong Tan return ret; 29301db58f86SHuazhong Tan 29311db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->roce); 29321db58f86SHuazhong Tan if (ret) 29331db58f86SHuazhong Tan return ret; 29341db58f86SHuazhong Tan 2935fe735c84SHuazhong Tan set_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 29361db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 29371db58f86SHuazhong Tan 29381db58f86SHuazhong Tan return 0; 29391db58f86SHuazhong Tan } 29401db58f86SHuazhong Tan 2941e718a93fSPeng Li static int hclgevf_init_client_instance(struct hnae3_client *client, 2942e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2943e2cb1decSSalil Mehta { 2944e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2945e2cb1decSSalil Mehta int ret; 2946e2cb1decSSalil Mehta 2947e2cb1decSSalil Mehta switch (client->type) { 2948e2cb1decSSalil Mehta case HNAE3_CLIENT_KNIC: 2949e2cb1decSSalil Mehta hdev->nic_client = client; 2950e2cb1decSSalil Mehta hdev->nic.client = client; 2951e2cb1decSSalil Mehta 29521db58f86SHuazhong Tan ret = hclgevf_init_nic_client_instance(ae_dev, client); 2953e2cb1decSSalil Mehta if (ret) 295449dd8054SJian Shen goto clear_nic; 2955e2cb1decSSalil Mehta 29561db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, 29571db58f86SHuazhong Tan hdev->roce_client); 2958e2cb1decSSalil Mehta if (ret) 295949dd8054SJian Shen goto clear_roce; 2960d9f28fc2SJian Shen 2961e2cb1decSSalil Mehta break; 2962e2cb1decSSalil Mehta case HNAE3_CLIENT_ROCE: 2963544a7bcdSLijun Ou if (hnae3_dev_roce_supported(hdev)) { 2964e2cb1decSSalil Mehta hdev->roce_client = client; 2965e2cb1decSSalil Mehta hdev->roce.client = client; 2966544a7bcdSLijun Ou } 2967e2cb1decSSalil Mehta 29681db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, client); 2969e2cb1decSSalil Mehta if (ret) 297049dd8054SJian Shen goto clear_roce; 2971e2cb1decSSalil Mehta 2972fa7a4bd5SJian Shen break; 2973fa7a4bd5SJian Shen default: 2974fa7a4bd5SJian Shen return -EINVAL; 2975e2cb1decSSalil Mehta } 2976e2cb1decSSalil Mehta 2977e2cb1decSSalil Mehta return 0; 297849dd8054SJian Shen 297949dd8054SJian Shen clear_nic: 298049dd8054SJian Shen hdev->nic_client = NULL; 298149dd8054SJian Shen hdev->nic.client = NULL; 298249dd8054SJian Shen return ret; 298349dd8054SJian Shen clear_roce: 298449dd8054SJian Shen hdev->roce_client = NULL; 298549dd8054SJian Shen hdev->roce.client = NULL; 298649dd8054SJian Shen return ret; 2987e2cb1decSSalil Mehta } 2988e2cb1decSSalil Mehta 2989e718a93fSPeng Li static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2990e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2991e2cb1decSSalil Mehta { 2992e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2993e718a93fSPeng Li 2994e2cb1decSSalil Mehta /* un-init roce, if it exists */ 299549dd8054SJian Shen if (hdev->roce_client) { 2996fe735c84SHuazhong Tan clear_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 2997e2cb1decSSalil Mehta hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 299849dd8054SJian Shen hdev->roce_client = NULL; 299949dd8054SJian Shen hdev->roce.client = NULL; 300049dd8054SJian Shen } 3001e2cb1decSSalil Mehta 3002e2cb1decSSalil Mehta /* un-init nic/unic, if this was not called by roce client */ 300349dd8054SJian Shen if (client->ops->uninit_instance && hdev->nic_client && 300449dd8054SJian Shen client->type != HNAE3_CLIENT_ROCE) { 300525d1817cSHuazhong Tan clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 300625d1817cSHuazhong Tan 3007e2cb1decSSalil Mehta client->ops->uninit_instance(&hdev->nic, 0); 300849dd8054SJian Shen hdev->nic_client = NULL; 300949dd8054SJian Shen hdev->nic.client = NULL; 301049dd8054SJian Shen } 3011e2cb1decSSalil Mehta } 3012e2cb1decSSalil Mehta 301330ae7f8aSHuazhong Tan static int hclgevf_dev_mem_map(struct hclgevf_dev *hdev) 301430ae7f8aSHuazhong Tan { 301530ae7f8aSHuazhong Tan #define HCLGEVF_MEM_BAR 4 301630ae7f8aSHuazhong Tan 301730ae7f8aSHuazhong Tan struct pci_dev *pdev = hdev->pdev; 301830ae7f8aSHuazhong Tan struct hclgevf_hw *hw = &hdev->hw; 301930ae7f8aSHuazhong Tan 302030ae7f8aSHuazhong Tan /* for device does not have device memory, return directly */ 302130ae7f8aSHuazhong Tan if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGEVF_MEM_BAR))) 302230ae7f8aSHuazhong Tan return 0; 302330ae7f8aSHuazhong Tan 302430ae7f8aSHuazhong Tan hw->mem_base = devm_ioremap_wc(&pdev->dev, 302530ae7f8aSHuazhong Tan pci_resource_start(pdev, 302630ae7f8aSHuazhong Tan HCLGEVF_MEM_BAR), 302730ae7f8aSHuazhong Tan pci_resource_len(pdev, HCLGEVF_MEM_BAR)); 302830ae7f8aSHuazhong Tan if (!hw->mem_base) { 3029be419fcaSColin Ian King dev_err(&pdev->dev, "failed to map device memory\n"); 303030ae7f8aSHuazhong Tan return -EFAULT; 303130ae7f8aSHuazhong Tan } 303230ae7f8aSHuazhong Tan 303330ae7f8aSHuazhong Tan return 0; 303430ae7f8aSHuazhong Tan } 303530ae7f8aSHuazhong Tan 3036e2cb1decSSalil Mehta static int hclgevf_pci_init(struct hclgevf_dev *hdev) 3037e2cb1decSSalil Mehta { 3038e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 3039e2cb1decSSalil Mehta struct hclgevf_hw *hw; 3040e2cb1decSSalil Mehta int ret; 3041e2cb1decSSalil Mehta 3042e2cb1decSSalil Mehta ret = pci_enable_device(pdev); 3043e2cb1decSSalil Mehta if (ret) { 3044e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed to enable PCI device\n"); 30453e249d3bSFuyun Liang return ret; 3046e2cb1decSSalil Mehta } 3047e2cb1decSSalil Mehta 3048e2cb1decSSalil Mehta ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3049e2cb1decSSalil Mehta if (ret) { 3050e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 3051e2cb1decSSalil Mehta goto err_disable_device; 3052e2cb1decSSalil Mehta } 3053e2cb1decSSalil Mehta 3054e2cb1decSSalil Mehta ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 3055e2cb1decSSalil Mehta if (ret) { 3056e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 3057e2cb1decSSalil Mehta goto err_disable_device; 3058e2cb1decSSalil Mehta } 3059e2cb1decSSalil Mehta 3060e2cb1decSSalil Mehta pci_set_master(pdev); 3061e2cb1decSSalil Mehta hw = &hdev->hw; 3062e2cb1decSSalil Mehta hw->hdev = hdev; 30632e1ea493SPeng Li hw->io_base = pci_iomap(pdev, 2, 0); 3064e2cb1decSSalil Mehta if (!hw->io_base) { 3065e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't map configuration register space\n"); 3066e2cb1decSSalil Mehta ret = -ENOMEM; 3067e2cb1decSSalil Mehta goto err_clr_master; 3068e2cb1decSSalil Mehta } 3069e2cb1decSSalil Mehta 307030ae7f8aSHuazhong Tan ret = hclgevf_dev_mem_map(hdev); 307130ae7f8aSHuazhong Tan if (ret) 307230ae7f8aSHuazhong Tan goto err_unmap_io_base; 307330ae7f8aSHuazhong Tan 3074e2cb1decSSalil Mehta return 0; 3075e2cb1decSSalil Mehta 307630ae7f8aSHuazhong Tan err_unmap_io_base: 307730ae7f8aSHuazhong Tan pci_iounmap(pdev, hdev->hw.io_base); 3078e2cb1decSSalil Mehta err_clr_master: 3079e2cb1decSSalil Mehta pci_clear_master(pdev); 3080e2cb1decSSalil Mehta pci_release_regions(pdev); 3081e2cb1decSSalil Mehta err_disable_device: 3082e2cb1decSSalil Mehta pci_disable_device(pdev); 30833e249d3bSFuyun Liang 3084e2cb1decSSalil Mehta return ret; 3085e2cb1decSSalil Mehta } 3086e2cb1decSSalil Mehta 3087e2cb1decSSalil Mehta static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 3088e2cb1decSSalil Mehta { 3089e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 3090e2cb1decSSalil Mehta 309130ae7f8aSHuazhong Tan if (hdev->hw.mem_base) 309230ae7f8aSHuazhong Tan devm_iounmap(&pdev->dev, hdev->hw.mem_base); 309330ae7f8aSHuazhong Tan 3094e2cb1decSSalil Mehta pci_iounmap(pdev, hdev->hw.io_base); 3095e2cb1decSSalil Mehta pci_clear_master(pdev); 3096e2cb1decSSalil Mehta pci_release_regions(pdev); 3097e2cb1decSSalil Mehta pci_disable_device(pdev); 3098e2cb1decSSalil Mehta } 3099e2cb1decSSalil Mehta 310007acf909SJian Shen static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 310107acf909SJian Shen { 310207acf909SJian Shen struct hclgevf_query_res_cmd *req; 310307acf909SJian Shen struct hclgevf_desc desc; 310407acf909SJian Shen int ret; 310507acf909SJian Shen 310607acf909SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 310707acf909SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 310807acf909SJian Shen if (ret) { 310907acf909SJian Shen dev_err(&hdev->pdev->dev, 311007acf909SJian Shen "query vf resource failed, ret = %d.\n", ret); 311107acf909SJian Shen return ret; 311207acf909SJian Shen } 311307acf909SJian Shen 311407acf909SJian Shen req = (struct hclgevf_query_res_cmd *)desc.data; 311507acf909SJian Shen 3116580a05f9SYonglong Liu if (hnae3_dev_roce_supported(hdev)) { 311707acf909SJian Shen hdev->roce_base_msix_offset = 311860df7e91SHuazhong Tan hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee), 311907acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_M, 312007acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_S); 312107acf909SJian Shen hdev->num_roce_msix = 312260df7e91SHuazhong Tan hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 312307acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 312407acf909SJian Shen 3125580a05f9SYonglong Liu /* nic's msix numbers is always equals to the roce's. */ 3126580a05f9SYonglong Liu hdev->num_nic_msix = hdev->num_roce_msix; 3127580a05f9SYonglong Liu 312807acf909SJian Shen /* VF should have NIC vectors and Roce vectors, NIC vectors 312907acf909SJian Shen * are queued before Roce vectors. The offset is fixed to 64. 313007acf909SJian Shen */ 313107acf909SJian Shen hdev->num_msi = hdev->num_roce_msix + 313207acf909SJian Shen hdev->roce_base_msix_offset; 313307acf909SJian Shen } else { 313407acf909SJian Shen hdev->num_msi = 313560df7e91SHuazhong Tan hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 313607acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 3137580a05f9SYonglong Liu 3138580a05f9SYonglong Liu hdev->num_nic_msix = hdev->num_msi; 3139580a05f9SYonglong Liu } 3140580a05f9SYonglong Liu 3141580a05f9SYonglong Liu if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) { 3142580a05f9SYonglong Liu dev_err(&hdev->pdev->dev, 3143580a05f9SYonglong Liu "Just %u msi resources, not enough for vf(min:2).\n", 3144580a05f9SYonglong Liu hdev->num_nic_msix); 3145580a05f9SYonglong Liu return -EINVAL; 314607acf909SJian Shen } 314707acf909SJian Shen 314807acf909SJian Shen return 0; 314907acf909SJian Shen } 315007acf909SJian Shen 3151af2aedc5SGuangbin Huang static void hclgevf_set_default_dev_specs(struct hclgevf_dev *hdev) 3152af2aedc5SGuangbin Huang { 3153af2aedc5SGuangbin Huang #define HCLGEVF_MAX_NON_TSO_BD_NUM 8U 3154af2aedc5SGuangbin Huang 3155af2aedc5SGuangbin Huang struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 3156af2aedc5SGuangbin Huang 3157af2aedc5SGuangbin Huang ae_dev->dev_specs.max_non_tso_bd_num = 3158af2aedc5SGuangbin Huang HCLGEVF_MAX_NON_TSO_BD_NUM; 3159af2aedc5SGuangbin Huang ae_dev->dev_specs.rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 3160af2aedc5SGuangbin Huang ae_dev->dev_specs.rss_key_size = HCLGEVF_RSS_KEY_SIZE; 3161ab16b49cSHuazhong Tan ae_dev->dev_specs.max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 3162e070c8b9SYufeng Mo ae_dev->dev_specs.max_frm_size = HCLGEVF_MAC_MAX_FRAME; 3163af2aedc5SGuangbin Huang } 3164af2aedc5SGuangbin Huang 3165af2aedc5SGuangbin Huang static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev, 3166af2aedc5SGuangbin Huang struct hclgevf_desc *desc) 3167af2aedc5SGuangbin Huang { 3168af2aedc5SGuangbin Huang struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 3169af2aedc5SGuangbin Huang struct hclgevf_dev_specs_0_cmd *req0; 3170ab16b49cSHuazhong Tan struct hclgevf_dev_specs_1_cmd *req1; 3171af2aedc5SGuangbin Huang 3172af2aedc5SGuangbin Huang req0 = (struct hclgevf_dev_specs_0_cmd *)desc[0].data; 3173ab16b49cSHuazhong Tan req1 = (struct hclgevf_dev_specs_1_cmd *)desc[1].data; 3174af2aedc5SGuangbin Huang 3175af2aedc5SGuangbin Huang ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 3176af2aedc5SGuangbin Huang ae_dev->dev_specs.rss_ind_tbl_size = 3177af2aedc5SGuangbin Huang le16_to_cpu(req0->rss_ind_tbl_size); 317891bfae25SHuazhong Tan ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 3179af2aedc5SGuangbin Huang ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 3180ab16b49cSHuazhong Tan ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 3181e070c8b9SYufeng Mo ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 3182af2aedc5SGuangbin Huang } 3183af2aedc5SGuangbin Huang 318413297028SGuangbin Huang static void hclgevf_check_dev_specs(struct hclgevf_dev *hdev) 318513297028SGuangbin Huang { 318613297028SGuangbin Huang struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 318713297028SGuangbin Huang 318813297028SGuangbin Huang if (!dev_specs->max_non_tso_bd_num) 318913297028SGuangbin Huang dev_specs->max_non_tso_bd_num = HCLGEVF_MAX_NON_TSO_BD_NUM; 319013297028SGuangbin Huang if (!dev_specs->rss_ind_tbl_size) 319113297028SGuangbin Huang dev_specs->rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 319213297028SGuangbin Huang if (!dev_specs->rss_key_size) 319313297028SGuangbin Huang dev_specs->rss_key_size = HCLGEVF_RSS_KEY_SIZE; 3194ab16b49cSHuazhong Tan if (!dev_specs->max_int_gl) 3195ab16b49cSHuazhong Tan dev_specs->max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 3196e070c8b9SYufeng Mo if (!dev_specs->max_frm_size) 3197e070c8b9SYufeng Mo dev_specs->max_frm_size = HCLGEVF_MAC_MAX_FRAME; 319813297028SGuangbin Huang } 319913297028SGuangbin Huang 3200af2aedc5SGuangbin Huang static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev) 3201af2aedc5SGuangbin Huang { 3202af2aedc5SGuangbin Huang struct hclgevf_desc desc[HCLGEVF_QUERY_DEV_SPECS_BD_NUM]; 3203af2aedc5SGuangbin Huang int ret; 3204af2aedc5SGuangbin Huang int i; 3205af2aedc5SGuangbin Huang 3206af2aedc5SGuangbin Huang /* set default specifications as devices lower than version V3 do not 3207af2aedc5SGuangbin Huang * support querying specifications from firmware. 3208af2aedc5SGuangbin Huang */ 3209af2aedc5SGuangbin Huang if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 3210af2aedc5SGuangbin Huang hclgevf_set_default_dev_specs(hdev); 3211af2aedc5SGuangbin Huang return 0; 3212af2aedc5SGuangbin Huang } 3213af2aedc5SGuangbin Huang 3214af2aedc5SGuangbin Huang for (i = 0; i < HCLGEVF_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 3215af2aedc5SGuangbin Huang hclgevf_cmd_setup_basic_desc(&desc[i], 3216af2aedc5SGuangbin Huang HCLGEVF_OPC_QUERY_DEV_SPECS, true); 3217af2aedc5SGuangbin Huang desc[i].flag |= cpu_to_le16(HCLGEVF_CMD_FLAG_NEXT); 3218af2aedc5SGuangbin Huang } 3219af2aedc5SGuangbin Huang hclgevf_cmd_setup_basic_desc(&desc[i], HCLGEVF_OPC_QUERY_DEV_SPECS, 3220af2aedc5SGuangbin Huang true); 3221af2aedc5SGuangbin Huang 3222af2aedc5SGuangbin Huang ret = hclgevf_cmd_send(&hdev->hw, desc, HCLGEVF_QUERY_DEV_SPECS_BD_NUM); 3223af2aedc5SGuangbin Huang if (ret) 3224af2aedc5SGuangbin Huang return ret; 3225af2aedc5SGuangbin Huang 3226af2aedc5SGuangbin Huang hclgevf_parse_dev_specs(hdev, desc); 322713297028SGuangbin Huang hclgevf_check_dev_specs(hdev); 3228af2aedc5SGuangbin Huang 3229af2aedc5SGuangbin Huang return 0; 3230af2aedc5SGuangbin Huang } 3231af2aedc5SGuangbin Huang 3232862d969aSHuazhong Tan static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 3233862d969aSHuazhong Tan { 3234862d969aSHuazhong Tan struct pci_dev *pdev = hdev->pdev; 3235862d969aSHuazhong Tan int ret = 0; 3236862d969aSHuazhong Tan 3237862d969aSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FULL_RESET && 3238862d969aSHuazhong Tan test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3239862d969aSHuazhong Tan hclgevf_misc_irq_uninit(hdev); 3240862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 3241862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3242862d969aSHuazhong Tan } 3243862d969aSHuazhong Tan 3244862d969aSHuazhong Tan if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3245862d969aSHuazhong Tan pci_set_master(pdev); 3246862d969aSHuazhong Tan ret = hclgevf_init_msi(hdev); 3247862d969aSHuazhong Tan if (ret) { 3248862d969aSHuazhong Tan dev_err(&pdev->dev, 3249862d969aSHuazhong Tan "failed(%d) to init MSI/MSI-X\n", ret); 3250862d969aSHuazhong Tan return ret; 3251862d969aSHuazhong Tan } 3252862d969aSHuazhong Tan 3253862d969aSHuazhong Tan ret = hclgevf_misc_irq_init(hdev); 3254862d969aSHuazhong Tan if (ret) { 3255862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 3256862d969aSHuazhong Tan dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 3257862d969aSHuazhong Tan ret); 3258862d969aSHuazhong Tan return ret; 3259862d969aSHuazhong Tan } 3260862d969aSHuazhong Tan 3261862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3262862d969aSHuazhong Tan } 3263862d969aSHuazhong Tan 3264862d969aSHuazhong Tan return ret; 3265862d969aSHuazhong Tan } 3266862d969aSHuazhong Tan 3267039ba863SJian Shen static int hclgevf_clear_vport_list(struct hclgevf_dev *hdev) 3268039ba863SJian Shen { 3269039ba863SJian Shen struct hclge_vf_to_pf_msg send_msg; 3270039ba863SJian Shen 3271039ba863SJian Shen hclgevf_build_send_msg(&send_msg, HCLGE_MBX_HANDLE_VF_TBL, 3272039ba863SJian Shen HCLGE_MBX_VPORT_LIST_CLEAR); 3273039ba863SJian Shen return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3274039ba863SJian Shen } 3275039ba863SJian Shen 327679664077SHuazhong Tan static void hclgevf_init_rxd_adv_layout(struct hclgevf_dev *hdev) 327779664077SHuazhong Tan { 327879664077SHuazhong Tan if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 327979664077SHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 1); 328079664077SHuazhong Tan } 328179664077SHuazhong Tan 328279664077SHuazhong Tan static void hclgevf_uninit_rxd_adv_layout(struct hclgevf_dev *hdev) 328379664077SHuazhong Tan { 328479664077SHuazhong Tan if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 328579664077SHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 0); 328679664077SHuazhong Tan } 328779664077SHuazhong Tan 32889c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 3289e2cb1decSSalil Mehta { 32907a01c897SSalil Mehta struct pci_dev *pdev = hdev->pdev; 3291e2cb1decSSalil Mehta int ret; 3292e2cb1decSSalil Mehta 3293862d969aSHuazhong Tan ret = hclgevf_pci_reset(hdev); 3294862d969aSHuazhong Tan if (ret) { 3295862d969aSHuazhong Tan dev_err(&pdev->dev, "pci reset failed %d\n", ret); 3296862d969aSHuazhong Tan return ret; 3297862d969aSHuazhong Tan } 3298862d969aSHuazhong Tan 32999c6f7085SHuazhong Tan ret = hclgevf_cmd_init(hdev); 33009c6f7085SHuazhong Tan if (ret) { 33019c6f7085SHuazhong Tan dev_err(&pdev->dev, "cmd failed %d\n", ret); 33029c6f7085SHuazhong Tan return ret; 33037a01c897SSalil Mehta } 3304e2cb1decSSalil Mehta 33059c6f7085SHuazhong Tan ret = hclgevf_rss_init_hw(hdev); 33069c6f7085SHuazhong Tan if (ret) { 33079c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 33089c6f7085SHuazhong Tan "failed(%d) to initialize RSS\n", ret); 33099c6f7085SHuazhong Tan return ret; 33109c6f7085SHuazhong Tan } 33119c6f7085SHuazhong Tan 3312b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 3313b26a6feaSPeng Li if (ret) 3314b26a6feaSPeng Li return ret; 3315b26a6feaSPeng Li 33169c6f7085SHuazhong Tan ret = hclgevf_init_vlan_config(hdev); 33179c6f7085SHuazhong Tan if (ret) { 33189c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 33199c6f7085SHuazhong Tan "failed(%d) to initialize VLAN config\n", ret); 33209c6f7085SHuazhong Tan return ret; 33219c6f7085SHuazhong Tan } 33229c6f7085SHuazhong Tan 3323c631c696SJian Shen set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 3324c631c696SJian Shen 332579664077SHuazhong Tan hclgevf_init_rxd_adv_layout(hdev); 332679664077SHuazhong Tan 33279c6f7085SHuazhong Tan dev_info(&hdev->pdev->dev, "Reset done\n"); 33289c6f7085SHuazhong Tan 33299c6f7085SHuazhong Tan return 0; 33309c6f7085SHuazhong Tan } 33319c6f7085SHuazhong Tan 33329c6f7085SHuazhong Tan static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 33339c6f7085SHuazhong Tan { 33349c6f7085SHuazhong Tan struct pci_dev *pdev = hdev->pdev; 33359c6f7085SHuazhong Tan int ret; 33369c6f7085SHuazhong Tan 3337e2cb1decSSalil Mehta ret = hclgevf_pci_init(hdev); 333860df7e91SHuazhong Tan if (ret) 3339e2cb1decSSalil Mehta return ret; 3340e2cb1decSSalil Mehta 3341*cd624299SYufeng Mo ret = hclgevf_devlink_init(hdev); 3342*cd624299SYufeng Mo if (ret) 3343*cd624299SYufeng Mo goto err_devlink_init; 3344*cd624299SYufeng Mo 33458b0195a3SHuazhong Tan ret = hclgevf_cmd_queue_init(hdev); 334660df7e91SHuazhong Tan if (ret) 33478b0195a3SHuazhong Tan goto err_cmd_queue_init; 33488b0195a3SHuazhong Tan 3349eddf0462SYunsheng Lin ret = hclgevf_cmd_init(hdev); 3350eddf0462SYunsheng Lin if (ret) 3351eddf0462SYunsheng Lin goto err_cmd_init; 3352eddf0462SYunsheng Lin 335307acf909SJian Shen /* Get vf resource */ 335407acf909SJian Shen ret = hclgevf_query_vf_resource(hdev); 335560df7e91SHuazhong Tan if (ret) 33568b0195a3SHuazhong Tan goto err_cmd_init; 335707acf909SJian Shen 3358af2aedc5SGuangbin Huang ret = hclgevf_query_dev_specs(hdev); 3359af2aedc5SGuangbin Huang if (ret) { 3360af2aedc5SGuangbin Huang dev_err(&pdev->dev, 3361af2aedc5SGuangbin Huang "failed to query dev specifications, ret = %d\n", ret); 3362af2aedc5SGuangbin Huang goto err_cmd_init; 3363af2aedc5SGuangbin Huang } 3364af2aedc5SGuangbin Huang 336507acf909SJian Shen ret = hclgevf_init_msi(hdev); 336607acf909SJian Shen if (ret) { 336707acf909SJian Shen dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 33688b0195a3SHuazhong Tan goto err_cmd_init; 336907acf909SJian Shen } 337007acf909SJian Shen 337107acf909SJian Shen hclgevf_state_init(hdev); 3372dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 3373afb6afdbSHuazhong Tan hdev->reset_type = HNAE3_NONE_RESET; 337407acf909SJian Shen 3375e2cb1decSSalil Mehta ret = hclgevf_misc_irq_init(hdev); 337660df7e91SHuazhong Tan if (ret) 3377e2cb1decSSalil Mehta goto err_misc_irq_init; 3378e2cb1decSSalil Mehta 3379862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3380862d969aSHuazhong Tan 3381e2cb1decSSalil Mehta ret = hclgevf_configure(hdev); 3382e2cb1decSSalil Mehta if (ret) { 3383e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 3384e2cb1decSSalil Mehta goto err_config; 3385e2cb1decSSalil Mehta } 3386e2cb1decSSalil Mehta 3387e2cb1decSSalil Mehta ret = hclgevf_alloc_tqps(hdev); 3388e2cb1decSSalil Mehta if (ret) { 3389e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 3390e2cb1decSSalil Mehta goto err_config; 3391e2cb1decSSalil Mehta } 3392e2cb1decSSalil Mehta 3393e2cb1decSSalil Mehta ret = hclgevf_set_handle_info(hdev); 339460df7e91SHuazhong Tan if (ret) 3395e2cb1decSSalil Mehta goto err_config; 3396e2cb1decSSalil Mehta 3397b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 3398b26a6feaSPeng Li if (ret) 3399b26a6feaSPeng Li goto err_config; 3400b26a6feaSPeng Li 3401e2cb1decSSalil Mehta /* Initialize RSS for this VF */ 340287ce161eSGuangbin Huang ret = hclgevf_rss_init_cfg(hdev); 340387ce161eSGuangbin Huang if (ret) { 340487ce161eSGuangbin Huang dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 340587ce161eSGuangbin Huang goto err_config; 340687ce161eSGuangbin Huang } 340787ce161eSGuangbin Huang 3408e2cb1decSSalil Mehta ret = hclgevf_rss_init_hw(hdev); 3409e2cb1decSSalil Mehta if (ret) { 3410e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 3411e2cb1decSSalil Mehta "failed(%d) to initialize RSS\n", ret); 3412e2cb1decSSalil Mehta goto err_config; 3413e2cb1decSSalil Mehta } 3414e2cb1decSSalil Mehta 3415039ba863SJian Shen /* ensure vf tbl list as empty before init*/ 3416039ba863SJian Shen ret = hclgevf_clear_vport_list(hdev); 3417039ba863SJian Shen if (ret) { 3418039ba863SJian Shen dev_err(&pdev->dev, 3419039ba863SJian Shen "failed to clear tbl list configuration, ret = %d.\n", 3420039ba863SJian Shen ret); 3421039ba863SJian Shen goto err_config; 3422039ba863SJian Shen } 3423039ba863SJian Shen 3424e2cb1decSSalil Mehta ret = hclgevf_init_vlan_config(hdev); 3425e2cb1decSSalil Mehta if (ret) { 3426e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 3427e2cb1decSSalil Mehta "failed(%d) to initialize VLAN config\n", ret); 3428e2cb1decSSalil Mehta goto err_config; 3429e2cb1decSSalil Mehta } 3430e2cb1decSSalil Mehta 343179664077SHuazhong Tan hclgevf_init_rxd_adv_layout(hdev); 343279664077SHuazhong Tan 34330742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 343408d80a4cSHuazhong Tan dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 343508d80a4cSHuazhong Tan HCLGEVF_DRIVER_NAME); 3436e2cb1decSSalil Mehta 3437ff200099SYunsheng Lin hclgevf_task_schedule(hdev, round_jiffies_relative(HZ)); 3438ff200099SYunsheng Lin 3439e2cb1decSSalil Mehta return 0; 3440e2cb1decSSalil Mehta 3441e2cb1decSSalil Mehta err_config: 3442e2cb1decSSalil Mehta hclgevf_misc_irq_uninit(hdev); 3443e2cb1decSSalil Mehta err_misc_irq_init: 3444e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 3445e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 344607acf909SJian Shen err_cmd_init: 34478b0195a3SHuazhong Tan hclgevf_cmd_uninit(hdev); 34488b0195a3SHuazhong Tan err_cmd_queue_init: 3449*cd624299SYufeng Mo hclgevf_devlink_uninit(hdev); 3450*cd624299SYufeng Mo err_devlink_init: 3451e2cb1decSSalil Mehta hclgevf_pci_uninit(hdev); 3452862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3453e2cb1decSSalil Mehta return ret; 3454e2cb1decSSalil Mehta } 3455e2cb1decSSalil Mehta 34567a01c897SSalil Mehta static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 3457e2cb1decSSalil Mehta { 3458d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 3459d3410018SYufeng Mo 3460e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 346179664077SHuazhong Tan hclgevf_uninit_rxd_adv_layout(hdev); 3462862d969aSHuazhong Tan 3463d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_VF_UNINIT, 0); 3464d3410018SYufeng Mo hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 346523b4201dSJian Shen 3466862d969aSHuazhong Tan if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3467eddf0462SYunsheng Lin hclgevf_misc_irq_uninit(hdev); 3468e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 34697a01c897SSalil Mehta } 34707a01c897SSalil Mehta 3471862d969aSHuazhong Tan hclgevf_cmd_uninit(hdev); 3472*cd624299SYufeng Mo hclgevf_devlink_uninit(hdev); 3473e3364c5fSZenghui Yu hclgevf_pci_uninit(hdev); 3474ee4bcd3bSJian Shen hclgevf_uninit_mac_list(hdev); 3475862d969aSHuazhong Tan } 3476862d969aSHuazhong Tan 34777a01c897SSalil Mehta static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 34787a01c897SSalil Mehta { 34797a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 34807a01c897SSalil Mehta int ret; 34817a01c897SSalil Mehta 34827a01c897SSalil Mehta ret = hclgevf_alloc_hdev(ae_dev); 34837a01c897SSalil Mehta if (ret) { 34847a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device allocation failed\n"); 34857a01c897SSalil Mehta return ret; 34867a01c897SSalil Mehta } 34877a01c897SSalil Mehta 34887a01c897SSalil Mehta ret = hclgevf_init_hdev(ae_dev->priv); 3489a6d818e3SYunsheng Lin if (ret) { 34907a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device initialization failed\n"); 34917a01c897SSalil Mehta return ret; 34927a01c897SSalil Mehta } 34937a01c897SSalil Mehta 3494a6d818e3SYunsheng Lin return 0; 3495a6d818e3SYunsheng Lin } 3496a6d818e3SYunsheng Lin 34977a01c897SSalil Mehta static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 34987a01c897SSalil Mehta { 34997a01c897SSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 35007a01c897SSalil Mehta 35017a01c897SSalil Mehta hclgevf_uninit_hdev(hdev); 3502e2cb1decSSalil Mehta ae_dev->priv = NULL; 3503e2cb1decSSalil Mehta } 3504e2cb1decSSalil Mehta 3505849e4607SPeng Li static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 3506849e4607SPeng Li { 3507849e4607SPeng Li struct hnae3_handle *nic = &hdev->nic; 3508849e4607SPeng Li struct hnae3_knic_private_info *kinfo = &nic->kinfo; 3509849e4607SPeng Li 35108be73621SHuazhong Tan return min_t(u32, hdev->rss_size_max, 351135244430SJian Shen hdev->num_tqps / kinfo->tc_info.num_tc); 3512849e4607SPeng Li } 3513849e4607SPeng Li 3514849e4607SPeng Li /** 3515849e4607SPeng Li * hclgevf_get_channels - Get the current channels enabled and max supported. 3516849e4607SPeng Li * @handle: hardware information for network interface 3517849e4607SPeng Li * @ch: ethtool channels structure 3518849e4607SPeng Li * 3519849e4607SPeng Li * We don't support separate tx and rx queues as channels. The other count 3520849e4607SPeng Li * represents how many queues are being used for control. max_combined counts 3521849e4607SPeng Li * how many queue pairs we can support. They may not be mapped 1 to 1 with 3522849e4607SPeng Li * q_vectors since we support a lot more queue pairs than q_vectors. 3523849e4607SPeng Li **/ 3524849e4607SPeng Li static void hclgevf_get_channels(struct hnae3_handle *handle, 3525849e4607SPeng Li struct ethtool_channels *ch) 3526849e4607SPeng Li { 3527849e4607SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3528849e4607SPeng Li 3529849e4607SPeng Li ch->max_combined = hclgevf_get_max_channels(hdev); 3530849e4607SPeng Li ch->other_count = 0; 3531849e4607SPeng Li ch->max_other = 0; 35328be73621SHuazhong Tan ch->combined_count = handle->kinfo.rss_size; 3533849e4607SPeng Li } 3534849e4607SPeng Li 3535cc719218SPeng Li static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 35360d43bf45SHuazhong Tan u16 *alloc_tqps, u16 *max_rss_size) 3537cc719218SPeng Li { 3538cc719218SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3539cc719218SPeng Li 35400d43bf45SHuazhong Tan *alloc_tqps = hdev->num_tqps; 3541cc719218SPeng Li *max_rss_size = hdev->rss_size_max; 3542cc719218SPeng Li } 3543cc719218SPeng Li 35444093d1a2SGuangbin Huang static void hclgevf_update_rss_size(struct hnae3_handle *handle, 35454093d1a2SGuangbin Huang u32 new_tqps_num) 35464093d1a2SGuangbin Huang { 35474093d1a2SGuangbin Huang struct hnae3_knic_private_info *kinfo = &handle->kinfo; 35484093d1a2SGuangbin Huang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 35494093d1a2SGuangbin Huang u16 max_rss_size; 35504093d1a2SGuangbin Huang 35514093d1a2SGuangbin Huang kinfo->req_rss_size = new_tqps_num; 35524093d1a2SGuangbin Huang 35534093d1a2SGuangbin Huang max_rss_size = min_t(u16, hdev->rss_size_max, 355435244430SJian Shen hdev->num_tqps / kinfo->tc_info.num_tc); 35554093d1a2SGuangbin Huang 35564093d1a2SGuangbin Huang /* Use the user's configuration when it is not larger than 35574093d1a2SGuangbin Huang * max_rss_size, otherwise, use the maximum specification value. 35584093d1a2SGuangbin Huang */ 35594093d1a2SGuangbin Huang if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 35604093d1a2SGuangbin Huang kinfo->req_rss_size <= max_rss_size) 35614093d1a2SGuangbin Huang kinfo->rss_size = kinfo->req_rss_size; 35624093d1a2SGuangbin Huang else if (kinfo->rss_size > max_rss_size || 35634093d1a2SGuangbin Huang (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) 35644093d1a2SGuangbin Huang kinfo->rss_size = max_rss_size; 35654093d1a2SGuangbin Huang 356635244430SJian Shen kinfo->num_tqps = kinfo->tc_info.num_tc * kinfo->rss_size; 35674093d1a2SGuangbin Huang } 35684093d1a2SGuangbin Huang 35694093d1a2SGuangbin Huang static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 35704093d1a2SGuangbin Huang bool rxfh_configured) 35714093d1a2SGuangbin Huang { 35724093d1a2SGuangbin Huang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 35734093d1a2SGuangbin Huang struct hnae3_knic_private_info *kinfo = &handle->kinfo; 35744093d1a2SGuangbin Huang u16 cur_rss_size = kinfo->rss_size; 35754093d1a2SGuangbin Huang u16 cur_tqps = kinfo->num_tqps; 35764093d1a2SGuangbin Huang u32 *rss_indir; 35774093d1a2SGuangbin Huang unsigned int i; 35784093d1a2SGuangbin Huang int ret; 35794093d1a2SGuangbin Huang 35804093d1a2SGuangbin Huang hclgevf_update_rss_size(handle, new_tqps_num); 35814093d1a2SGuangbin Huang 35824093d1a2SGuangbin Huang ret = hclgevf_set_rss_tc_mode(hdev, kinfo->rss_size); 35834093d1a2SGuangbin Huang if (ret) 35844093d1a2SGuangbin Huang return ret; 35854093d1a2SGuangbin Huang 3586cd7e963dSSalil Mehta /* RSS indirection table has been configured by user */ 35874093d1a2SGuangbin Huang if (rxfh_configured) 35884093d1a2SGuangbin Huang goto out; 35894093d1a2SGuangbin Huang 35904093d1a2SGuangbin Huang /* Reinitializes the rss indirect table according to the new RSS size */ 359187ce161eSGuangbin Huang rss_indir = kcalloc(hdev->ae_dev->dev_specs.rss_ind_tbl_size, 359287ce161eSGuangbin Huang sizeof(u32), GFP_KERNEL); 35934093d1a2SGuangbin Huang if (!rss_indir) 35944093d1a2SGuangbin Huang return -ENOMEM; 35954093d1a2SGuangbin Huang 359687ce161eSGuangbin Huang for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 35974093d1a2SGuangbin Huang rss_indir[i] = i % kinfo->rss_size; 35984093d1a2SGuangbin Huang 3599944de484SGuojia Liao hdev->rss_cfg.rss_size = kinfo->rss_size; 3600944de484SGuojia Liao 36014093d1a2SGuangbin Huang ret = hclgevf_set_rss(handle, rss_indir, NULL, 0); 36024093d1a2SGuangbin Huang if (ret) 36034093d1a2SGuangbin Huang dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 36044093d1a2SGuangbin Huang ret); 36054093d1a2SGuangbin Huang 36064093d1a2SGuangbin Huang kfree(rss_indir); 36074093d1a2SGuangbin Huang 36084093d1a2SGuangbin Huang out: 36094093d1a2SGuangbin Huang if (!ret) 36104093d1a2SGuangbin Huang dev_info(&hdev->pdev->dev, 36114093d1a2SGuangbin Huang "Channels changed, rss_size from %u to %u, tqps from %u to %u", 36124093d1a2SGuangbin Huang cur_rss_size, kinfo->rss_size, 361335244430SJian Shen cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 36144093d1a2SGuangbin Huang 36154093d1a2SGuangbin Huang return ret; 36164093d1a2SGuangbin Huang } 36174093d1a2SGuangbin Huang 3618175ec96bSFuyun Liang static int hclgevf_get_status(struct hnae3_handle *handle) 3619175ec96bSFuyun Liang { 3620175ec96bSFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3621175ec96bSFuyun Liang 3622175ec96bSFuyun Liang return hdev->hw.mac.link; 3623175ec96bSFuyun Liang } 3624175ec96bSFuyun Liang 36254a152de9SFuyun Liang static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 36264a152de9SFuyun Liang u8 *auto_neg, u32 *speed, 36274a152de9SFuyun Liang u8 *duplex) 36284a152de9SFuyun Liang { 36294a152de9SFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 36304a152de9SFuyun Liang 36314a152de9SFuyun Liang if (speed) 36324a152de9SFuyun Liang *speed = hdev->hw.mac.speed; 36334a152de9SFuyun Liang if (duplex) 36344a152de9SFuyun Liang *duplex = hdev->hw.mac.duplex; 36354a152de9SFuyun Liang if (auto_neg) 36364a152de9SFuyun Liang *auto_neg = AUTONEG_DISABLE; 36374a152de9SFuyun Liang } 36384a152de9SFuyun Liang 36394a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 36404a152de9SFuyun Liang u8 duplex) 36414a152de9SFuyun Liang { 36424a152de9SFuyun Liang hdev->hw.mac.speed = speed; 36434a152de9SFuyun Liang hdev->hw.mac.duplex = duplex; 36444a152de9SFuyun Liang } 36454a152de9SFuyun Liang 36461731be4cSYonglong Liu static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 36475c9f6b39SPeng Li { 36485c9f6b39SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 36495c9f6b39SPeng Li 36505c9f6b39SPeng Li return hclgevf_config_gro(hdev, enable); 36515c9f6b39SPeng Li } 36525c9f6b39SPeng Li 365388d10bd6SJian Shen static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 365488d10bd6SJian Shen u8 *module_type) 3655c136b884SPeng Li { 3656c136b884SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 365788d10bd6SJian Shen 3658c136b884SPeng Li if (media_type) 3659c136b884SPeng Li *media_type = hdev->hw.mac.media_type; 366088d10bd6SJian Shen 366188d10bd6SJian Shen if (module_type) 366288d10bd6SJian Shen *module_type = hdev->hw.mac.module_type; 3663c136b884SPeng Li } 3664c136b884SPeng Li 36654d60291bSHuazhong Tan static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 36664d60291bSHuazhong Tan { 36674d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 36684d60291bSHuazhong Tan 3669aa5c4f17SHuazhong Tan return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 36704d60291bSHuazhong Tan } 36714d60291bSHuazhong Tan 3672fe735c84SHuazhong Tan static bool hclgevf_get_cmdq_stat(struct hnae3_handle *handle) 3673fe735c84SHuazhong Tan { 3674fe735c84SHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3675fe735c84SHuazhong Tan 3676fe735c84SHuazhong Tan return test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 3677fe735c84SHuazhong Tan } 3678fe735c84SHuazhong Tan 36794d60291bSHuazhong Tan static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 36804d60291bSHuazhong Tan { 36814d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 36824d60291bSHuazhong Tan 36834d60291bSHuazhong Tan return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 36844d60291bSHuazhong Tan } 36854d60291bSHuazhong Tan 36864d60291bSHuazhong Tan static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 36874d60291bSHuazhong Tan { 36884d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 36894d60291bSHuazhong Tan 3690c88a6e7dSHuazhong Tan return hdev->rst_stats.hw_rst_done_cnt; 36914d60291bSHuazhong Tan } 36924d60291bSHuazhong Tan 36939194d18bSliuzhongzhu static void hclgevf_get_link_mode(struct hnae3_handle *handle, 36949194d18bSliuzhongzhu unsigned long *supported, 36959194d18bSliuzhongzhu unsigned long *advertising) 36969194d18bSliuzhongzhu { 36979194d18bSliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 36989194d18bSliuzhongzhu 36999194d18bSliuzhongzhu *supported = hdev->hw.mac.supported; 37009194d18bSliuzhongzhu *advertising = hdev->hw.mac.advertising; 37019194d18bSliuzhongzhu } 37029194d18bSliuzhongzhu 37031600c3e5SJian Shen #define MAX_SEPARATE_NUM 4 3704e407efddSHuazhong Tan #define SEPARATOR_VALUE 0xFDFCFBFA 37051600c3e5SJian Shen #define REG_NUM_PER_LINE 4 37061600c3e5SJian Shen #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 37071600c3e5SJian Shen 37081600c3e5SJian Shen static int hclgevf_get_regs_len(struct hnae3_handle *handle) 37091600c3e5SJian Shen { 37101600c3e5SJian Shen int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 37111600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 37121600c3e5SJian Shen 37131600c3e5SJian Shen cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 37141600c3e5SJian Shen common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 37151600c3e5SJian Shen ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 37161600c3e5SJian Shen tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 37171600c3e5SJian Shen 37181600c3e5SJian Shen return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 37191600c3e5SJian Shen tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 37201600c3e5SJian Shen } 37211600c3e5SJian Shen 37221600c3e5SJian Shen static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 37231600c3e5SJian Shen void *data) 37241600c3e5SJian Shen { 37251600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 37261600c3e5SJian Shen int i, j, reg_um, separator_num; 37271600c3e5SJian Shen u32 *reg = data; 37281600c3e5SJian Shen 37291600c3e5SJian Shen *version = hdev->fw_version; 37301600c3e5SJian Shen 37311600c3e5SJian Shen /* fetching per-VF registers values from VF PCIe register space */ 37321600c3e5SJian Shen reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 37331600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 37341600c3e5SJian Shen for (i = 0; i < reg_um; i++) 37351600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 37361600c3e5SJian Shen for (i = 0; i < separator_num; i++) 37371600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 37381600c3e5SJian Shen 37391600c3e5SJian Shen reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 37401600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 37411600c3e5SJian Shen for (i = 0; i < reg_um; i++) 37421600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 37431600c3e5SJian Shen for (i = 0; i < separator_num; i++) 37441600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 37451600c3e5SJian Shen 37461600c3e5SJian Shen reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 37471600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 37481600c3e5SJian Shen for (j = 0; j < hdev->num_tqps; j++) { 37491600c3e5SJian Shen for (i = 0; i < reg_um; i++) 37501600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 37511600c3e5SJian Shen ring_reg_addr_list[i] + 37521600c3e5SJian Shen 0x200 * j); 37531600c3e5SJian Shen for (i = 0; i < separator_num; i++) 37541600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 37551600c3e5SJian Shen } 37561600c3e5SJian Shen 37571600c3e5SJian Shen reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 37581600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 37591600c3e5SJian Shen for (j = 0; j < hdev->num_msi_used - 1; j++) { 37601600c3e5SJian Shen for (i = 0; i < reg_um; i++) 37611600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 37621600c3e5SJian Shen tqp_intr_reg_addr_list[i] + 37631600c3e5SJian Shen 4 * j); 37641600c3e5SJian Shen for (i = 0; i < separator_num; i++) 37651600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 37661600c3e5SJian Shen } 37671600c3e5SJian Shen } 37681600c3e5SJian Shen 376992f11ea1SJian Shen void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 377092f11ea1SJian Shen u8 *port_base_vlan_info, u8 data_size) 377192f11ea1SJian Shen { 377292f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 3773d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 3774a6f7bfdcSJian Shen int ret; 377592f11ea1SJian Shen 377692f11ea1SJian Shen rtnl_lock(); 3777a6f7bfdcSJian Shen 3778b7b5d25bSGuojia Liao if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 3779b7b5d25bSGuojia Liao test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) { 3780a6f7bfdcSJian Shen dev_warn(&hdev->pdev->dev, 3781a6f7bfdcSJian Shen "is resetting when updating port based vlan info\n"); 378292f11ea1SJian Shen rtnl_unlock(); 3783a6f7bfdcSJian Shen return; 3784a6f7bfdcSJian Shen } 3785a6f7bfdcSJian Shen 3786a6f7bfdcSJian Shen ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 3787a6f7bfdcSJian Shen if (ret) { 3788a6f7bfdcSJian Shen rtnl_unlock(); 3789a6f7bfdcSJian Shen return; 3790a6f7bfdcSJian Shen } 379192f11ea1SJian Shen 379292f11ea1SJian Shen /* send msg to PF and wait update port based vlan info */ 3793d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 3794d3410018SYufeng Mo HCLGE_MBX_PORT_BASE_VLAN_CFG); 3795d3410018SYufeng Mo memcpy(send_msg.data, port_base_vlan_info, data_size); 3796a6f7bfdcSJian Shen ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3797a6f7bfdcSJian Shen if (!ret) { 379892f11ea1SJian Shen if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 3799a6f7bfdcSJian Shen nic->port_base_vlan_state = state; 380092f11ea1SJian Shen else 380192f11ea1SJian Shen nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 3802a6f7bfdcSJian Shen } 380392f11ea1SJian Shen 380492f11ea1SJian Shen hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 380592f11ea1SJian Shen rtnl_unlock(); 380692f11ea1SJian Shen } 380792f11ea1SJian Shen 3808e2cb1decSSalil Mehta static const struct hnae3_ae_ops hclgevf_ops = { 3809e2cb1decSSalil Mehta .init_ae_dev = hclgevf_init_ae_dev, 3810e2cb1decSSalil Mehta .uninit_ae_dev = hclgevf_uninit_ae_dev, 3811bb1890d5SJiaran Zhang .reset_prepare = hclgevf_reset_prepare_general, 3812bb1890d5SJiaran Zhang .reset_done = hclgevf_reset_done, 3813e718a93fSPeng Li .init_client_instance = hclgevf_init_client_instance, 3814e718a93fSPeng Li .uninit_client_instance = hclgevf_uninit_client_instance, 3815e2cb1decSSalil Mehta .start = hclgevf_ae_start, 3816e2cb1decSSalil Mehta .stop = hclgevf_ae_stop, 3817a6d818e3SYunsheng Lin .client_start = hclgevf_client_start, 3818a6d818e3SYunsheng Lin .client_stop = hclgevf_client_stop, 3819e2cb1decSSalil Mehta .map_ring_to_vector = hclgevf_map_ring_to_vector, 3820e2cb1decSSalil Mehta .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 3821e2cb1decSSalil Mehta .get_vector = hclgevf_get_vector, 38220d3e6631SYunsheng Lin .put_vector = hclgevf_put_vector, 3823e2cb1decSSalil Mehta .reset_queue = hclgevf_reset_tqp, 3824e2cb1decSSalil Mehta .get_mac_addr = hclgevf_get_mac_addr, 3825e2cb1decSSalil Mehta .set_mac_addr = hclgevf_set_mac_addr, 3826e2cb1decSSalil Mehta .add_uc_addr = hclgevf_add_uc_addr, 3827e2cb1decSSalil Mehta .rm_uc_addr = hclgevf_rm_uc_addr, 3828e2cb1decSSalil Mehta .add_mc_addr = hclgevf_add_mc_addr, 3829e2cb1decSSalil Mehta .rm_mc_addr = hclgevf_rm_mc_addr, 3830e2cb1decSSalil Mehta .get_stats = hclgevf_get_stats, 3831e2cb1decSSalil Mehta .update_stats = hclgevf_update_stats, 3832e2cb1decSSalil Mehta .get_strings = hclgevf_get_strings, 3833e2cb1decSSalil Mehta .get_sset_count = hclgevf_get_sset_count, 3834e2cb1decSSalil Mehta .get_rss_key_size = hclgevf_get_rss_key_size, 3835e2cb1decSSalil Mehta .get_rss = hclgevf_get_rss, 3836e2cb1decSSalil Mehta .set_rss = hclgevf_set_rss, 3837d97b3072SJian Shen .get_rss_tuple = hclgevf_get_rss_tuple, 3838d97b3072SJian Shen .set_rss_tuple = hclgevf_set_rss_tuple, 3839e2cb1decSSalil Mehta .get_tc_size = hclgevf_get_tc_size, 3840e2cb1decSSalil Mehta .get_fw_version = hclgevf_get_fw_version, 3841e2cb1decSSalil Mehta .set_vlan_filter = hclgevf_set_vlan_filter, 3842fa6a262aSJian Shen .enable_vlan_filter = hclgevf_enable_vlan_filter, 3843b2641e2aSYunsheng Lin .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 38446d4c3981SSalil Mehta .reset_event = hclgevf_reset_event, 3845720bd583SHuazhong Tan .set_default_reset_request = hclgevf_set_def_reset_request, 38464093d1a2SGuangbin Huang .set_channels = hclgevf_set_channels, 3847849e4607SPeng Li .get_channels = hclgevf_get_channels, 3848cc719218SPeng Li .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 38491600c3e5SJian Shen .get_regs_len = hclgevf_get_regs_len, 38501600c3e5SJian Shen .get_regs = hclgevf_get_regs, 3851175ec96bSFuyun Liang .get_status = hclgevf_get_status, 38524a152de9SFuyun Liang .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3853c136b884SPeng Li .get_media_type = hclgevf_get_media_type, 38544d60291bSHuazhong Tan .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 38554d60291bSHuazhong Tan .ae_dev_resetting = hclgevf_ae_dev_resetting, 38564d60291bSHuazhong Tan .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 38575c9f6b39SPeng Li .set_gro_en = hclgevf_gro_en, 3858818f1675SYunsheng Lin .set_mtu = hclgevf_set_mtu, 38590c29d191Sliuzhongzhu .get_global_queue_id = hclgevf_get_qid_global, 38608cdb992fSJian Shen .set_timer_task = hclgevf_set_timer_task, 38619194d18bSliuzhongzhu .get_link_mode = hclgevf_get_link_mode, 3862e196ec75SJian Shen .set_promisc_mode = hclgevf_set_promisc_mode, 3863c631c696SJian Shen .request_update_promisc_mode = hclgevf_request_update_promisc_mode, 3864fe735c84SHuazhong Tan .get_cmdq_stat = hclgevf_get_cmdq_stat, 3865e2cb1decSSalil Mehta }; 3866e2cb1decSSalil Mehta 3867e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf = { 3868e2cb1decSSalil Mehta .ops = &hclgevf_ops, 3869e2cb1decSSalil Mehta .pdev_id_table = ae_algovf_pci_tbl, 3870e2cb1decSSalil Mehta }; 3871e2cb1decSSalil Mehta 3872e2cb1decSSalil Mehta static int hclgevf_init(void) 3873e2cb1decSSalil Mehta { 3874e2cb1decSSalil Mehta pr_info("%s is initializing\n", HCLGEVF_NAME); 3875e2cb1decSSalil Mehta 387616deaef2SYunsheng Lin hclgevf_wq = alloc_workqueue("%s", 0, 0, HCLGEVF_NAME); 38770ea68902SYunsheng Lin if (!hclgevf_wq) { 38780ea68902SYunsheng Lin pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME); 38790ea68902SYunsheng Lin return -ENOMEM; 38800ea68902SYunsheng Lin } 38810ea68902SYunsheng Lin 3882854cf33aSFuyun Liang hnae3_register_ae_algo(&ae_algovf); 3883854cf33aSFuyun Liang 3884854cf33aSFuyun Liang return 0; 3885e2cb1decSSalil Mehta } 3886e2cb1decSSalil Mehta 3887e2cb1decSSalil Mehta static void hclgevf_exit(void) 3888e2cb1decSSalil Mehta { 3889e2cb1decSSalil Mehta hnae3_unregister_ae_algo(&ae_algovf); 38900ea68902SYunsheng Lin destroy_workqueue(hclgevf_wq); 3891e2cb1decSSalil Mehta } 3892e2cb1decSSalil Mehta module_init(hclgevf_init); 3893e2cb1decSSalil Mehta module_exit(hclgevf_exit); 3894e2cb1decSSalil Mehta 3895e2cb1decSSalil Mehta MODULE_LICENSE("GPL"); 3896e2cb1decSSalil Mehta MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3897e2cb1decSSalil Mehta MODULE_DESCRIPTION("HCLGEVF Driver"); 3898e2cb1decSSalil Mehta MODULE_VERSION(HCLGEVF_MOD_VERSION); 3899