1e2cb1decSSalil Mehta // SPDX-License-Identifier: GPL-2.0+ 2e2cb1decSSalil Mehta // Copyright (c) 2016-2017 Hisilicon Limited. 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #include <linux/etherdevice.h> 5aa5c4f17SHuazhong Tan #include <linux/iopoll.h> 66988eb2aSSalil Mehta #include <net/rtnetlink.h> 7e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 8e2cb1decSSalil Mehta #include "hclgevf_main.h" 9e2cb1decSSalil Mehta #include "hclge_mbx.h" 10e2cb1decSSalil Mehta #include "hnae3.h" 11e2cb1decSSalil Mehta 12e2cb1decSSalil Mehta #define HCLGEVF_NAME "hclgevf" 13e2cb1decSSalil Mehta 14bbe6540eSHuazhong Tan #define HCLGEVF_RESET_MAX_FAIL_CNT 5 15bbe6540eSHuazhong Tan 169c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 17e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf; 18e2cb1decSSalil Mehta 190ea68902SYunsheng Lin static struct workqueue_struct *hclgevf_wq; 200ea68902SYunsheng Lin 21e2cb1decSSalil Mehta static const struct pci_device_id ae_algovf_pci_tbl[] = { 22c155e22bSGuangbin Huang {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0}, 23c155e22bSGuangbin Huang {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 24c155e22bSGuangbin Huang HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 25e2cb1decSSalil Mehta /* required last entry */ 26e2cb1decSSalil Mehta {0, } 27e2cb1decSSalil Mehta }; 28e2cb1decSSalil Mehta 29472d7eceSJian Shen static const u8 hclgevf_hash_key[] = { 30472d7eceSJian Shen 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 31472d7eceSJian Shen 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 32472d7eceSJian Shen 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 33472d7eceSJian Shen 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 34472d7eceSJian Shen 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 35472d7eceSJian Shen }; 36472d7eceSJian Shen 372f550a46SYunsheng Lin MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 382f550a46SYunsheng Lin 391600c3e5SJian Shen static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 401600c3e5SJian Shen HCLGEVF_CMDQ_TX_ADDR_H_REG, 411600c3e5SJian Shen HCLGEVF_CMDQ_TX_DEPTH_REG, 421600c3e5SJian Shen HCLGEVF_CMDQ_TX_TAIL_REG, 431600c3e5SJian Shen HCLGEVF_CMDQ_TX_HEAD_REG, 441600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_L_REG, 451600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_H_REG, 461600c3e5SJian Shen HCLGEVF_CMDQ_RX_DEPTH_REG, 471600c3e5SJian Shen HCLGEVF_CMDQ_RX_TAIL_REG, 481600c3e5SJian Shen HCLGEVF_CMDQ_RX_HEAD_REG, 491600c3e5SJian Shen HCLGEVF_VECTOR0_CMDQ_SRC_REG, 509cee2e8dSHuazhong Tan HCLGEVF_VECTOR0_CMDQ_STATE_REG, 511600c3e5SJian Shen HCLGEVF_CMDQ_INTR_EN_REG, 521600c3e5SJian Shen HCLGEVF_CMDQ_INTR_GEN_REG}; 531600c3e5SJian Shen 541600c3e5SJian Shen static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 551600c3e5SJian Shen HCLGEVF_RST_ING, 561600c3e5SJian Shen HCLGEVF_GRO_EN_REG}; 571600c3e5SJian Shen 581600c3e5SJian Shen static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 591600c3e5SJian Shen HCLGEVF_RING_RX_ADDR_H_REG, 601600c3e5SJian Shen HCLGEVF_RING_RX_BD_NUM_REG, 611600c3e5SJian Shen HCLGEVF_RING_RX_BD_LENGTH_REG, 621600c3e5SJian Shen HCLGEVF_RING_RX_MERGE_EN_REG, 631600c3e5SJian Shen HCLGEVF_RING_RX_TAIL_REG, 641600c3e5SJian Shen HCLGEVF_RING_RX_HEAD_REG, 651600c3e5SJian Shen HCLGEVF_RING_RX_FBD_NUM_REG, 661600c3e5SJian Shen HCLGEVF_RING_RX_OFFSET_REG, 671600c3e5SJian Shen HCLGEVF_RING_RX_FBD_OFFSET_REG, 681600c3e5SJian Shen HCLGEVF_RING_RX_STASH_REG, 691600c3e5SJian Shen HCLGEVF_RING_RX_BD_ERR_REG, 701600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_L_REG, 711600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_H_REG, 721600c3e5SJian Shen HCLGEVF_RING_TX_BD_NUM_REG, 731600c3e5SJian Shen HCLGEVF_RING_TX_PRIORITY_REG, 741600c3e5SJian Shen HCLGEVF_RING_TX_TC_REG, 751600c3e5SJian Shen HCLGEVF_RING_TX_MERGE_EN_REG, 761600c3e5SJian Shen HCLGEVF_RING_TX_TAIL_REG, 771600c3e5SJian Shen HCLGEVF_RING_TX_HEAD_REG, 781600c3e5SJian Shen HCLGEVF_RING_TX_FBD_NUM_REG, 791600c3e5SJian Shen HCLGEVF_RING_TX_OFFSET_REG, 801600c3e5SJian Shen HCLGEVF_RING_TX_EBD_NUM_REG, 811600c3e5SJian Shen HCLGEVF_RING_TX_EBD_OFFSET_REG, 821600c3e5SJian Shen HCLGEVF_RING_TX_BD_ERR_REG, 831600c3e5SJian Shen HCLGEVF_RING_EN_REG}; 841600c3e5SJian Shen 851600c3e5SJian Shen static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 861600c3e5SJian Shen HCLGEVF_TQP_INTR_GL0_REG, 871600c3e5SJian Shen HCLGEVF_TQP_INTR_GL1_REG, 881600c3e5SJian Shen HCLGEVF_TQP_INTR_GL2_REG, 891600c3e5SJian Shen HCLGEVF_TQP_INTR_RL_REG}; 901600c3e5SJian Shen 919b2f3477SWeihang Li static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 92e2cb1decSSalil Mehta { 93eed9535fSPeng Li if (!handle->client) 94eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, nic); 95eed9535fSPeng Li else if (handle->client->type == HNAE3_CLIENT_ROCE) 96eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, roce); 97eed9535fSPeng Li else 98e2cb1decSSalil Mehta return container_of(handle, struct hclgevf_dev, nic); 99e2cb1decSSalil Mehta } 100e2cb1decSSalil Mehta 101e2cb1decSSalil Mehta static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 102e2cb1decSSalil Mehta { 103b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 104e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 105e2cb1decSSalil Mehta struct hclgevf_desc desc; 106e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 107e2cb1decSSalil Mehta int status; 108e2cb1decSSalil Mehta int i; 109e2cb1decSSalil Mehta 110b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 111b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 112e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 113e2cb1decSSalil Mehta HCLGEVF_OPC_QUERY_RX_STATUS, 114e2cb1decSSalil Mehta true); 115e2cb1decSSalil Mehta 116e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 117e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 118e2cb1decSSalil Mehta if (status) { 119e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 120e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 121e2cb1decSSalil Mehta status, i); 122e2cb1decSSalil Mehta return status; 123e2cb1decSSalil Mehta } 124e2cb1decSSalil Mehta tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 125cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 126e2cb1decSSalil Mehta 127e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 128e2cb1decSSalil Mehta true); 129e2cb1decSSalil Mehta 130e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 131e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 132e2cb1decSSalil Mehta if (status) { 133e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 134e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 135e2cb1decSSalil Mehta status, i); 136e2cb1decSSalil Mehta return status; 137e2cb1decSSalil Mehta } 138e2cb1decSSalil Mehta tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 139cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 140e2cb1decSSalil Mehta } 141e2cb1decSSalil Mehta 142e2cb1decSSalil Mehta return 0; 143e2cb1decSSalil Mehta } 144e2cb1decSSalil Mehta 145e2cb1decSSalil Mehta static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 146e2cb1decSSalil Mehta { 147e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo = &handle->kinfo; 148e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 149e2cb1decSSalil Mehta u64 *buff = data; 150e2cb1decSSalil Mehta int i; 151e2cb1decSSalil Mehta 152b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 153b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 154e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 155e2cb1decSSalil Mehta } 156e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 157b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 158e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 159e2cb1decSSalil Mehta } 160e2cb1decSSalil Mehta 161e2cb1decSSalil Mehta return buff; 162e2cb1decSSalil Mehta } 163e2cb1decSSalil Mehta 164e2cb1decSSalil Mehta static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 165e2cb1decSSalil Mehta { 166b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 167e2cb1decSSalil Mehta 168b4f1d303SJian Shen return kinfo->num_tqps * 2; 169e2cb1decSSalil Mehta } 170e2cb1decSSalil Mehta 171e2cb1decSSalil Mehta static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 172e2cb1decSSalil Mehta { 173b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 174e2cb1decSSalil Mehta u8 *buff = data; 1759d8d5a36SYufeng Mo int i; 176e2cb1decSSalil Mehta 177b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 178b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 179e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1800c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 181e2cb1decSSalil Mehta tqp->index); 182e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 183e2cb1decSSalil Mehta } 184e2cb1decSSalil Mehta 185b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 186b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 187e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1880c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 189e2cb1decSSalil Mehta tqp->index); 190e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 191e2cb1decSSalil Mehta } 192e2cb1decSSalil Mehta 193e2cb1decSSalil Mehta return buff; 194e2cb1decSSalil Mehta } 195e2cb1decSSalil Mehta 196e2cb1decSSalil Mehta static void hclgevf_update_stats(struct hnae3_handle *handle, 197e2cb1decSSalil Mehta struct net_device_stats *net_stats) 198e2cb1decSSalil Mehta { 199e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 200e2cb1decSSalil Mehta int status; 201e2cb1decSSalil Mehta 202e2cb1decSSalil Mehta status = hclgevf_tqps_update_stats(handle); 203e2cb1decSSalil Mehta if (status) 204e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 205e2cb1decSSalil Mehta "VF update of TQPS stats fail, status = %d.\n", 206e2cb1decSSalil Mehta status); 207e2cb1decSSalil Mehta } 208e2cb1decSSalil Mehta 209e2cb1decSSalil Mehta static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 210e2cb1decSSalil Mehta { 211e2cb1decSSalil Mehta if (strset == ETH_SS_TEST) 212e2cb1decSSalil Mehta return -EOPNOTSUPP; 213e2cb1decSSalil Mehta else if (strset == ETH_SS_STATS) 214e2cb1decSSalil Mehta return hclgevf_tqps_get_sset_count(handle, strset); 215e2cb1decSSalil Mehta 216e2cb1decSSalil Mehta return 0; 217e2cb1decSSalil Mehta } 218e2cb1decSSalil Mehta 219e2cb1decSSalil Mehta static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 220e2cb1decSSalil Mehta u8 *data) 221e2cb1decSSalil Mehta { 222e2cb1decSSalil Mehta u8 *p = (char *)data; 223e2cb1decSSalil Mehta 224e2cb1decSSalil Mehta if (strset == ETH_SS_STATS) 225e2cb1decSSalil Mehta p = hclgevf_tqps_get_strings(handle, p); 226e2cb1decSSalil Mehta } 227e2cb1decSSalil Mehta 228e2cb1decSSalil Mehta static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 229e2cb1decSSalil Mehta { 230e2cb1decSSalil Mehta hclgevf_tqps_get_stats(handle, data); 231e2cb1decSSalil Mehta } 232e2cb1decSSalil Mehta 233d3410018SYufeng Mo static void hclgevf_build_send_msg(struct hclge_vf_to_pf_msg *msg, u8 code, 234d3410018SYufeng Mo u8 subcode) 235d3410018SYufeng Mo { 236d3410018SYufeng Mo if (msg) { 237d3410018SYufeng Mo memset(msg, 0, sizeof(struct hclge_vf_to_pf_msg)); 238d3410018SYufeng Mo msg->code = code; 239d3410018SYufeng Mo msg->subcode = subcode; 240d3410018SYufeng Mo } 241d3410018SYufeng Mo } 242d3410018SYufeng Mo 243e2cb1decSSalil Mehta static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 244e2cb1decSSalil Mehta { 245d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 246e2cb1decSSalil Mehta u8 resp_msg; 247e2cb1decSSalil Mehta int status; 248e2cb1decSSalil Mehta 249d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_TCINFO, 0); 250d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg, 251d3410018SYufeng Mo sizeof(resp_msg)); 252e2cb1decSSalil Mehta if (status) { 253e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 254e2cb1decSSalil Mehta "VF request to get TC info from PF failed %d", 255e2cb1decSSalil Mehta status); 256e2cb1decSSalil Mehta return status; 257e2cb1decSSalil Mehta } 258e2cb1decSSalil Mehta 259e2cb1decSSalil Mehta hdev->hw_tc_map = resp_msg; 260e2cb1decSSalil Mehta 261e2cb1decSSalil Mehta return 0; 262e2cb1decSSalil Mehta } 263e2cb1decSSalil Mehta 26492f11ea1SJian Shen static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 26592f11ea1SJian Shen { 26692f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 267d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 26892f11ea1SJian Shen u8 resp_msg; 26992f11ea1SJian Shen int ret; 27092f11ea1SJian Shen 271d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 272d3410018SYufeng Mo HCLGE_MBX_GET_PORT_BASE_VLAN_STATE); 273d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg, 274d3410018SYufeng Mo sizeof(u8)); 27592f11ea1SJian Shen if (ret) { 27692f11ea1SJian Shen dev_err(&hdev->pdev->dev, 27792f11ea1SJian Shen "VF request to get port based vlan state failed %d", 27892f11ea1SJian Shen ret); 27992f11ea1SJian Shen return ret; 28092f11ea1SJian Shen } 28192f11ea1SJian Shen 28292f11ea1SJian Shen nic->port_base_vlan_state = resp_msg; 28392f11ea1SJian Shen 28492f11ea1SJian Shen return 0; 28592f11ea1SJian Shen } 28692f11ea1SJian Shen 2876cee6fc3SJian Shen static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 288e2cb1decSSalil Mehta { 289c0425944SPeng Li #define HCLGEVF_TQPS_RSS_INFO_LEN 6 290d3410018SYufeng Mo #define HCLGEVF_TQPS_ALLOC_OFFSET 0 291d3410018SYufeng Mo #define HCLGEVF_TQPS_RSS_SIZE_OFFSET 2 292d3410018SYufeng Mo #define HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET 4 293d3410018SYufeng Mo 294e2cb1decSSalil Mehta u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 295d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 296e2cb1decSSalil Mehta int status; 297e2cb1decSSalil Mehta 298d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QINFO, 0); 299d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 300e2cb1decSSalil Mehta HCLGEVF_TQPS_RSS_INFO_LEN); 301e2cb1decSSalil Mehta if (status) { 302e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 303e2cb1decSSalil Mehta "VF request to get tqp info from PF failed %d", 304e2cb1decSSalil Mehta status); 305e2cb1decSSalil Mehta return status; 306e2cb1decSSalil Mehta } 307e2cb1decSSalil Mehta 308d3410018SYufeng Mo memcpy(&hdev->num_tqps, &resp_msg[HCLGEVF_TQPS_ALLOC_OFFSET], 309d3410018SYufeng Mo sizeof(u16)); 310d3410018SYufeng Mo memcpy(&hdev->rss_size_max, &resp_msg[HCLGEVF_TQPS_RSS_SIZE_OFFSET], 311d3410018SYufeng Mo sizeof(u16)); 312d3410018SYufeng Mo memcpy(&hdev->rx_buf_len, &resp_msg[HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET], 313d3410018SYufeng Mo sizeof(u16)); 314c0425944SPeng Li 315c0425944SPeng Li return 0; 316c0425944SPeng Li } 317c0425944SPeng Li 318c0425944SPeng Li static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 319c0425944SPeng Li { 320c0425944SPeng Li #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 321d3410018SYufeng Mo #define HCLGEVF_TQPS_NUM_TX_DESC_OFFSET 0 322d3410018SYufeng Mo #define HCLGEVF_TQPS_NUM_RX_DESC_OFFSET 2 323d3410018SYufeng Mo 324c0425944SPeng Li u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 325d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 326c0425944SPeng Li int ret; 327c0425944SPeng Li 328d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QDEPTH, 0); 329d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 330c0425944SPeng Li HCLGEVF_TQPS_DEPTH_INFO_LEN); 331c0425944SPeng Li if (ret) { 332c0425944SPeng Li dev_err(&hdev->pdev->dev, 333c0425944SPeng Li "VF request to get tqp depth info from PF failed %d", 334c0425944SPeng Li ret); 335c0425944SPeng Li return ret; 336c0425944SPeng Li } 337c0425944SPeng Li 338d3410018SYufeng Mo memcpy(&hdev->num_tx_desc, &resp_msg[HCLGEVF_TQPS_NUM_TX_DESC_OFFSET], 339d3410018SYufeng Mo sizeof(u16)); 340d3410018SYufeng Mo memcpy(&hdev->num_rx_desc, &resp_msg[HCLGEVF_TQPS_NUM_RX_DESC_OFFSET], 341d3410018SYufeng Mo sizeof(u16)); 342e2cb1decSSalil Mehta 343e2cb1decSSalil Mehta return 0; 344e2cb1decSSalil Mehta } 345e2cb1decSSalil Mehta 3460c29d191Sliuzhongzhu static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 3470c29d191Sliuzhongzhu { 3480c29d191Sliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 349d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 3500c29d191Sliuzhongzhu u16 qid_in_pf = 0; 351d3410018SYufeng Mo u8 resp_data[2]; 3520c29d191Sliuzhongzhu int ret; 3530c29d191Sliuzhongzhu 354d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QID_IN_PF, 0); 355d3410018SYufeng Mo memcpy(send_msg.data, &queue_id, sizeof(queue_id)); 356d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_data, 35763cbf7a9SYufeng Mo sizeof(resp_data)); 3580c29d191Sliuzhongzhu if (!ret) 3590c29d191Sliuzhongzhu qid_in_pf = *(u16 *)resp_data; 3600c29d191Sliuzhongzhu 3610c29d191Sliuzhongzhu return qid_in_pf; 3620c29d191Sliuzhongzhu } 3630c29d191Sliuzhongzhu 3649c3e7130Sliuzhongzhu static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 3659c3e7130Sliuzhongzhu { 366d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 36788d10bd6SJian Shen u8 resp_msg[2]; 3689c3e7130Sliuzhongzhu int ret; 3699c3e7130Sliuzhongzhu 370d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MEDIA_TYPE, 0); 371d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 372d3410018SYufeng Mo sizeof(resp_msg)); 3739c3e7130Sliuzhongzhu if (ret) { 3749c3e7130Sliuzhongzhu dev_err(&hdev->pdev->dev, 3759c3e7130Sliuzhongzhu "VF request to get the pf port media type failed %d", 3769c3e7130Sliuzhongzhu ret); 3779c3e7130Sliuzhongzhu return ret; 3789c3e7130Sliuzhongzhu } 3799c3e7130Sliuzhongzhu 38088d10bd6SJian Shen hdev->hw.mac.media_type = resp_msg[0]; 38188d10bd6SJian Shen hdev->hw.mac.module_type = resp_msg[1]; 3829c3e7130Sliuzhongzhu 3839c3e7130Sliuzhongzhu return 0; 3849c3e7130Sliuzhongzhu } 3859c3e7130Sliuzhongzhu 386e2cb1decSSalil Mehta static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 387e2cb1decSSalil Mehta { 388e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 389e2cb1decSSalil Mehta int i; 390e2cb1decSSalil Mehta 391e2cb1decSSalil Mehta hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 392e2cb1decSSalil Mehta sizeof(struct hclgevf_tqp), GFP_KERNEL); 393e2cb1decSSalil Mehta if (!hdev->htqp) 394e2cb1decSSalil Mehta return -ENOMEM; 395e2cb1decSSalil Mehta 396e2cb1decSSalil Mehta tqp = hdev->htqp; 397e2cb1decSSalil Mehta 398e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 399e2cb1decSSalil Mehta tqp->dev = &hdev->pdev->dev; 400e2cb1decSSalil Mehta tqp->index = i; 401e2cb1decSSalil Mehta 402e2cb1decSSalil Mehta tqp->q.ae_algo = &ae_algovf; 403e2cb1decSSalil Mehta tqp->q.buf_size = hdev->rx_buf_len; 404c0425944SPeng Li tqp->q.tx_desc_num = hdev->num_tx_desc; 405c0425944SPeng Li tqp->q.rx_desc_num = hdev->num_rx_desc; 406e2cb1decSSalil Mehta tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 407e2cb1decSSalil Mehta i * HCLGEVF_TQP_REG_SIZE; 408e2cb1decSSalil Mehta 409e2cb1decSSalil Mehta tqp++; 410e2cb1decSSalil Mehta } 411e2cb1decSSalil Mehta 412e2cb1decSSalil Mehta return 0; 413e2cb1decSSalil Mehta } 414e2cb1decSSalil Mehta 415e2cb1decSSalil Mehta static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 416e2cb1decSSalil Mehta { 417e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 418e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo; 419e2cb1decSSalil Mehta u16 new_tqps = hdev->num_tqps; 420ebaf1908SWeihang Li unsigned int i; 421e2cb1decSSalil Mehta 422e2cb1decSSalil Mehta kinfo = &nic->kinfo; 423e2cb1decSSalil Mehta kinfo->num_tc = 0; 424c0425944SPeng Li kinfo->num_tx_desc = hdev->num_tx_desc; 425c0425944SPeng Li kinfo->num_rx_desc = hdev->num_rx_desc; 426e2cb1decSSalil Mehta kinfo->rx_buf_len = hdev->rx_buf_len; 427e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 428e2cb1decSSalil Mehta if (hdev->hw_tc_map & BIT(i)) 429e2cb1decSSalil Mehta kinfo->num_tc++; 430e2cb1decSSalil Mehta 431e2cb1decSSalil Mehta kinfo->rss_size 432e2cb1decSSalil Mehta = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 433e2cb1decSSalil Mehta new_tqps = kinfo->rss_size * kinfo->num_tc; 434e2cb1decSSalil Mehta kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 435e2cb1decSSalil Mehta 436e2cb1decSSalil Mehta kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 437e2cb1decSSalil Mehta sizeof(struct hnae3_queue *), GFP_KERNEL); 438e2cb1decSSalil Mehta if (!kinfo->tqp) 439e2cb1decSSalil Mehta return -ENOMEM; 440e2cb1decSSalil Mehta 441e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 442e2cb1decSSalil Mehta hdev->htqp[i].q.handle = &hdev->nic; 443e2cb1decSSalil Mehta hdev->htqp[i].q.tqp_index = i; 444e2cb1decSSalil Mehta kinfo->tqp[i] = &hdev->htqp[i].q; 445e2cb1decSSalil Mehta } 446e2cb1decSSalil Mehta 447580a05f9SYonglong Liu /* after init the max rss_size and tqps, adjust the default tqp numbers 448580a05f9SYonglong Liu * and rss size with the actual vector numbers 449580a05f9SYonglong Liu */ 450580a05f9SYonglong Liu kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps); 451580a05f9SYonglong Liu kinfo->rss_size = min_t(u16, kinfo->num_tqps / kinfo->num_tc, 452580a05f9SYonglong Liu kinfo->rss_size); 453580a05f9SYonglong Liu 454e2cb1decSSalil Mehta return 0; 455e2cb1decSSalil Mehta } 456e2cb1decSSalil Mehta 457e2cb1decSSalil Mehta static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 458e2cb1decSSalil Mehta { 459d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 460e2cb1decSSalil Mehta int status; 461e2cb1decSSalil Mehta 462d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_STATUS, 0); 463d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 464e2cb1decSSalil Mehta if (status) 465e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 466e2cb1decSSalil Mehta "VF failed to fetch link status(%d) from PF", status); 467e2cb1decSSalil Mehta } 468e2cb1decSSalil Mehta 469e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 470e2cb1decSSalil Mehta { 47145e92b7eSPeng Li struct hnae3_handle *rhandle = &hdev->roce; 472e2cb1decSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 47345e92b7eSPeng Li struct hnae3_client *rclient; 474e2cb1decSSalil Mehta struct hnae3_client *client; 475e2cb1decSSalil Mehta 476ff200099SYunsheng Lin if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state)) 477ff200099SYunsheng Lin return; 478ff200099SYunsheng Lin 479e2cb1decSSalil Mehta client = handle->client; 48045e92b7eSPeng Li rclient = hdev->roce_client; 481e2cb1decSSalil Mehta 482582d37bbSPeng Li link_state = 483582d37bbSPeng Li test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 484582d37bbSPeng Li 485e2cb1decSSalil Mehta if (link_state != hdev->hw.mac.link) { 486e2cb1decSSalil Mehta client->ops->link_status_change(handle, !!link_state); 48745e92b7eSPeng Li if (rclient && rclient->ops->link_status_change) 48845e92b7eSPeng Li rclient->ops->link_status_change(rhandle, !!link_state); 489e2cb1decSSalil Mehta hdev->hw.mac.link = link_state; 490e2cb1decSSalil Mehta } 491ff200099SYunsheng Lin 492ff200099SYunsheng Lin clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state); 493e2cb1decSSalil Mehta } 494e2cb1decSSalil Mehta 495538abaf3SYueHaibing static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 4969194d18bSliuzhongzhu { 4979194d18bSliuzhongzhu #define HCLGEVF_ADVERTISING 0 4989194d18bSliuzhongzhu #define HCLGEVF_SUPPORTED 1 4999194d18bSliuzhongzhu 500d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 501d3410018SYufeng Mo 502d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_MODE, 0); 503d3410018SYufeng Mo send_msg.data[0] = HCLGEVF_ADVERTISING; 504d3410018SYufeng Mo hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 505d3410018SYufeng Mo send_msg.data[0] = HCLGEVF_SUPPORTED; 506d3410018SYufeng Mo hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 5079194d18bSliuzhongzhu } 5089194d18bSliuzhongzhu 509e2cb1decSSalil Mehta static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 510e2cb1decSSalil Mehta { 511e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 512e2cb1decSSalil Mehta int ret; 513e2cb1decSSalil Mehta 514e2cb1decSSalil Mehta nic->ae_algo = &ae_algovf; 515e2cb1decSSalil Mehta nic->pdev = hdev->pdev; 516e2cb1decSSalil Mehta nic->numa_node_mask = hdev->numa_node_mask; 517424eb834SSalil Mehta nic->flags |= HNAE3_SUPPORT_VF; 518e2cb1decSSalil Mehta 519e2cb1decSSalil Mehta ret = hclgevf_knic_setup(hdev); 520e2cb1decSSalil Mehta if (ret) 521e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 522e2cb1decSSalil Mehta ret); 523e2cb1decSSalil Mehta return ret; 524e2cb1decSSalil Mehta } 525e2cb1decSSalil Mehta 526e2cb1decSSalil Mehta static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 527e2cb1decSSalil Mehta { 52836cbbdf6SPeng Li if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 52936cbbdf6SPeng Li dev_warn(&hdev->pdev->dev, 53036cbbdf6SPeng Li "vector(vector_id %d) has been freed.\n", vector_id); 53136cbbdf6SPeng Li return; 53236cbbdf6SPeng Li } 53336cbbdf6SPeng Li 534e2cb1decSSalil Mehta hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 535e2cb1decSSalil Mehta hdev->num_msi_left += 1; 536e2cb1decSSalil Mehta hdev->num_msi_used -= 1; 537e2cb1decSSalil Mehta } 538e2cb1decSSalil Mehta 539e2cb1decSSalil Mehta static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 540e2cb1decSSalil Mehta struct hnae3_vector_info *vector_info) 541e2cb1decSSalil Mehta { 542e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 543e2cb1decSSalil Mehta struct hnae3_vector_info *vector = vector_info; 544e2cb1decSSalil Mehta int alloc = 0; 545e2cb1decSSalil Mehta int i, j; 546e2cb1decSSalil Mehta 547580a05f9SYonglong Liu vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num); 548e2cb1decSSalil Mehta vector_num = min(hdev->num_msi_left, vector_num); 549e2cb1decSSalil Mehta 550e2cb1decSSalil Mehta for (j = 0; j < vector_num; j++) { 551e2cb1decSSalil Mehta for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 552e2cb1decSSalil Mehta if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 553e2cb1decSSalil Mehta vector->vector = pci_irq_vector(hdev->pdev, i); 554e2cb1decSSalil Mehta vector->io_addr = hdev->hw.io_base + 555e2cb1decSSalil Mehta HCLGEVF_VECTOR_REG_BASE + 556e2cb1decSSalil Mehta (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 557e2cb1decSSalil Mehta hdev->vector_status[i] = 0; 558e2cb1decSSalil Mehta hdev->vector_irq[i] = vector->vector; 559e2cb1decSSalil Mehta 560e2cb1decSSalil Mehta vector++; 561e2cb1decSSalil Mehta alloc++; 562e2cb1decSSalil Mehta 563e2cb1decSSalil Mehta break; 564e2cb1decSSalil Mehta } 565e2cb1decSSalil Mehta } 566e2cb1decSSalil Mehta } 567e2cb1decSSalil Mehta hdev->num_msi_left -= alloc; 568e2cb1decSSalil Mehta hdev->num_msi_used += alloc; 569e2cb1decSSalil Mehta 570e2cb1decSSalil Mehta return alloc; 571e2cb1decSSalil Mehta } 572e2cb1decSSalil Mehta 573e2cb1decSSalil Mehta static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 574e2cb1decSSalil Mehta { 575e2cb1decSSalil Mehta int i; 576e2cb1decSSalil Mehta 577e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 578e2cb1decSSalil Mehta if (vector == hdev->vector_irq[i]) 579e2cb1decSSalil Mehta return i; 580e2cb1decSSalil Mehta 581e2cb1decSSalil Mehta return -EINVAL; 582e2cb1decSSalil Mehta } 583e2cb1decSSalil Mehta 584374ad291SJian Shen static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 585374ad291SJian Shen const u8 hfunc, const u8 *key) 586374ad291SJian Shen { 587374ad291SJian Shen struct hclgevf_rss_config_cmd *req; 588ebaf1908SWeihang Li unsigned int key_offset = 0; 589374ad291SJian Shen struct hclgevf_desc desc; 5903caf772bSYufeng Mo int key_counts; 591374ad291SJian Shen int key_size; 592374ad291SJian Shen int ret; 593374ad291SJian Shen 5943caf772bSYufeng Mo key_counts = HCLGEVF_RSS_KEY_SIZE; 595374ad291SJian Shen req = (struct hclgevf_rss_config_cmd *)desc.data; 596374ad291SJian Shen 5973caf772bSYufeng Mo while (key_counts) { 598374ad291SJian Shen hclgevf_cmd_setup_basic_desc(&desc, 599374ad291SJian Shen HCLGEVF_OPC_RSS_GENERIC_CONFIG, 600374ad291SJian Shen false); 601374ad291SJian Shen 602374ad291SJian Shen req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 603374ad291SJian Shen req->hash_config |= 604374ad291SJian Shen (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 605374ad291SJian Shen 6063caf772bSYufeng Mo key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts); 607374ad291SJian Shen memcpy(req->hash_key, 608374ad291SJian Shen key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 609374ad291SJian Shen 6103caf772bSYufeng Mo key_counts -= key_size; 6113caf772bSYufeng Mo key_offset++; 612374ad291SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 613374ad291SJian Shen if (ret) { 614374ad291SJian Shen dev_err(&hdev->pdev->dev, 615374ad291SJian Shen "Configure RSS config fail, status = %d\n", 616374ad291SJian Shen ret); 617374ad291SJian Shen return ret; 618374ad291SJian Shen } 619374ad291SJian Shen } 620374ad291SJian Shen 621374ad291SJian Shen return 0; 622374ad291SJian Shen } 623374ad291SJian Shen 624e2cb1decSSalil Mehta static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 625e2cb1decSSalil Mehta { 626e2cb1decSSalil Mehta return HCLGEVF_RSS_KEY_SIZE; 627e2cb1decSSalil Mehta } 628e2cb1decSSalil Mehta 629e2cb1decSSalil Mehta static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 630e2cb1decSSalil Mehta { 631e2cb1decSSalil Mehta return HCLGEVF_RSS_IND_TBL_SIZE; 632e2cb1decSSalil Mehta } 633e2cb1decSSalil Mehta 634e2cb1decSSalil Mehta static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 635e2cb1decSSalil Mehta { 636e2cb1decSSalil Mehta const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 637e2cb1decSSalil Mehta struct hclgevf_rss_indirection_table_cmd *req; 638e2cb1decSSalil Mehta struct hclgevf_desc desc; 639e2cb1decSSalil Mehta int status; 640e2cb1decSSalil Mehta int i, j; 641e2cb1decSSalil Mehta 642e2cb1decSSalil Mehta req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 643e2cb1decSSalil Mehta 644e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 645e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 646e2cb1decSSalil Mehta false); 647e2cb1decSSalil Mehta req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 648e2cb1decSSalil Mehta req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 649e2cb1decSSalil Mehta for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 650e2cb1decSSalil Mehta req->rss_result[j] = 651e2cb1decSSalil Mehta indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 652e2cb1decSSalil Mehta 653e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 654e2cb1decSSalil Mehta if (status) { 655e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 656e2cb1decSSalil Mehta "VF failed(=%d) to set RSS indirection table\n", 657e2cb1decSSalil Mehta status); 658e2cb1decSSalil Mehta return status; 659e2cb1decSSalil Mehta } 660e2cb1decSSalil Mehta } 661e2cb1decSSalil Mehta 662e2cb1decSSalil Mehta return 0; 663e2cb1decSSalil Mehta } 664e2cb1decSSalil Mehta 665e2cb1decSSalil Mehta static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 666e2cb1decSSalil Mehta { 667e2cb1decSSalil Mehta struct hclgevf_rss_tc_mode_cmd *req; 668e2cb1decSSalil Mehta u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 669e2cb1decSSalil Mehta u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 670e2cb1decSSalil Mehta u16 tc_size[HCLGEVF_MAX_TC_NUM]; 671e2cb1decSSalil Mehta struct hclgevf_desc desc; 672e2cb1decSSalil Mehta u16 roundup_size; 673ebaf1908SWeihang Li unsigned int i; 6742adb8187SHuazhong Tan int status; 675e2cb1decSSalil Mehta 676e2cb1decSSalil Mehta req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 677e2cb1decSSalil Mehta 678e2cb1decSSalil Mehta roundup_size = roundup_pow_of_two(rss_size); 679e2cb1decSSalil Mehta roundup_size = ilog2(roundup_size); 680e2cb1decSSalil Mehta 681e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 682e2cb1decSSalil Mehta tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 683e2cb1decSSalil Mehta tc_size[i] = roundup_size; 684e2cb1decSSalil Mehta tc_offset[i] = rss_size * i; 685e2cb1decSSalil Mehta } 686e2cb1decSSalil Mehta 687e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 688e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 689e4e87715SPeng Li hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 690e2cb1decSSalil Mehta (tc_valid[i] & 0x1)); 691e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 692e2cb1decSSalil Mehta HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 693e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 694e2cb1decSSalil Mehta HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 695e2cb1decSSalil Mehta } 696e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 697e2cb1decSSalil Mehta if (status) 698e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 699e2cb1decSSalil Mehta "VF failed(=%d) to set rss tc mode\n", status); 700e2cb1decSSalil Mehta 701e2cb1decSSalil Mehta return status; 702e2cb1decSSalil Mehta } 703e2cb1decSSalil Mehta 704a638b1d8SJian Shen /* for revision 0x20, vf shared the same rss config with pf */ 705a638b1d8SJian Shen static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 706a638b1d8SJian Shen { 707a638b1d8SJian Shen #define HCLGEVF_RSS_MBX_RESP_LEN 8 708a638b1d8SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 709a638b1d8SJian Shen u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 710d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 711a638b1d8SJian Shen u16 msg_num, hash_key_index; 712a638b1d8SJian Shen u8 index; 713a638b1d8SJian Shen int ret; 714a638b1d8SJian Shen 715d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_RSS_KEY, 0); 716a638b1d8SJian Shen msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 717a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN; 718a638b1d8SJian Shen for (index = 0; index < msg_num; index++) { 719d3410018SYufeng Mo send_msg.data[0] = index; 720d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 721a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN); 722a638b1d8SJian Shen if (ret) { 723a638b1d8SJian Shen dev_err(&hdev->pdev->dev, 724a638b1d8SJian Shen "VF get rss hash key from PF failed, ret=%d", 725a638b1d8SJian Shen ret); 726a638b1d8SJian Shen return ret; 727a638b1d8SJian Shen } 728a638b1d8SJian Shen 729a638b1d8SJian Shen hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 730a638b1d8SJian Shen if (index == msg_num - 1) 731a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 732a638b1d8SJian Shen &resp_msg[0], 733a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE - hash_key_index); 734a638b1d8SJian Shen else 735a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 736a638b1d8SJian Shen &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 737a638b1d8SJian Shen } 738a638b1d8SJian Shen 739a638b1d8SJian Shen return 0; 740a638b1d8SJian Shen } 741a638b1d8SJian Shen 742e2cb1decSSalil Mehta static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 743e2cb1decSSalil Mehta u8 *hfunc) 744e2cb1decSSalil Mehta { 745e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 746e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 747a638b1d8SJian Shen int i, ret; 748e2cb1decSSalil Mehta 749374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 750374ad291SJian Shen /* Get hash algorithm */ 751374ad291SJian Shen if (hfunc) { 752374ad291SJian Shen switch (rss_cfg->hash_algo) { 753374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 754374ad291SJian Shen *hfunc = ETH_RSS_HASH_TOP; 755374ad291SJian Shen break; 756374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 757374ad291SJian Shen *hfunc = ETH_RSS_HASH_XOR; 758374ad291SJian Shen break; 759374ad291SJian Shen default: 760374ad291SJian Shen *hfunc = ETH_RSS_HASH_UNKNOWN; 761374ad291SJian Shen break; 762374ad291SJian Shen } 763374ad291SJian Shen } 764374ad291SJian Shen 765374ad291SJian Shen /* Get the RSS Key required by the user */ 766374ad291SJian Shen if (key) 767374ad291SJian Shen memcpy(key, rss_cfg->rss_hash_key, 768374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 769a638b1d8SJian Shen } else { 770a638b1d8SJian Shen if (hfunc) 771a638b1d8SJian Shen *hfunc = ETH_RSS_HASH_TOP; 772a638b1d8SJian Shen if (key) { 773a638b1d8SJian Shen ret = hclgevf_get_rss_hash_key(hdev); 774a638b1d8SJian Shen if (ret) 775a638b1d8SJian Shen return ret; 776a638b1d8SJian Shen memcpy(key, rss_cfg->rss_hash_key, 777a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE); 778a638b1d8SJian Shen } 779374ad291SJian Shen } 780374ad291SJian Shen 781e2cb1decSSalil Mehta if (indir) 782e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 783e2cb1decSSalil Mehta indir[i] = rss_cfg->rss_indirection_tbl[i]; 784e2cb1decSSalil Mehta 785374ad291SJian Shen return 0; 786e2cb1decSSalil Mehta } 787e2cb1decSSalil Mehta 788e2cb1decSSalil Mehta static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 789e2cb1decSSalil Mehta const u8 *key, const u8 hfunc) 790e2cb1decSSalil Mehta { 791e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 792e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 793374ad291SJian Shen int ret, i; 794374ad291SJian Shen 795374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 796374ad291SJian Shen /* Set the RSS Hash Key if specififed by the user */ 797374ad291SJian Shen if (key) { 798374ad291SJian Shen switch (hfunc) { 799374ad291SJian Shen case ETH_RSS_HASH_TOP: 800374ad291SJian Shen rss_cfg->hash_algo = 801374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 802374ad291SJian Shen break; 803374ad291SJian Shen case ETH_RSS_HASH_XOR: 804374ad291SJian Shen rss_cfg->hash_algo = 805374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_SIMPLE; 806374ad291SJian Shen break; 807374ad291SJian Shen case ETH_RSS_HASH_NO_CHANGE: 808374ad291SJian Shen break; 809374ad291SJian Shen default: 810374ad291SJian Shen return -EINVAL; 811374ad291SJian Shen } 812374ad291SJian Shen 813374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 814374ad291SJian Shen key); 815374ad291SJian Shen if (ret) 816374ad291SJian Shen return ret; 817374ad291SJian Shen 818374ad291SJian Shen /* Update the shadow RSS key with user specified qids */ 819374ad291SJian Shen memcpy(rss_cfg->rss_hash_key, key, 820374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 821374ad291SJian Shen } 822374ad291SJian Shen } 823e2cb1decSSalil Mehta 824e2cb1decSSalil Mehta /* update the shadow RSS table with user specified qids */ 825e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 826e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = indir[i]; 827e2cb1decSSalil Mehta 828e2cb1decSSalil Mehta /* update the hardware */ 829e2cb1decSSalil Mehta return hclgevf_set_rss_indir_table(hdev); 830e2cb1decSSalil Mehta } 831e2cb1decSSalil Mehta 832d97b3072SJian Shen static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 833d97b3072SJian Shen { 834d97b3072SJian Shen u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 835d97b3072SJian Shen 836d97b3072SJian Shen if (nfc->data & RXH_L4_B_2_3) 837d97b3072SJian Shen hash_sets |= HCLGEVF_D_PORT_BIT; 838d97b3072SJian Shen else 839d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_PORT_BIT; 840d97b3072SJian Shen 841d97b3072SJian Shen if (nfc->data & RXH_IP_SRC) 842d97b3072SJian Shen hash_sets |= HCLGEVF_S_IP_BIT; 843d97b3072SJian Shen else 844d97b3072SJian Shen hash_sets &= ~HCLGEVF_S_IP_BIT; 845d97b3072SJian Shen 846d97b3072SJian Shen if (nfc->data & RXH_IP_DST) 847d97b3072SJian Shen hash_sets |= HCLGEVF_D_IP_BIT; 848d97b3072SJian Shen else 849d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_IP_BIT; 850d97b3072SJian Shen 851d97b3072SJian Shen if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 852d97b3072SJian Shen hash_sets |= HCLGEVF_V_TAG_BIT; 853d97b3072SJian Shen 854d97b3072SJian Shen return hash_sets; 855d97b3072SJian Shen } 856d97b3072SJian Shen 857d97b3072SJian Shen static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 858d97b3072SJian Shen struct ethtool_rxnfc *nfc) 859d97b3072SJian Shen { 860d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 861d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 862d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 863d97b3072SJian Shen struct hclgevf_desc desc; 864d97b3072SJian Shen u8 tuple_sets; 865d97b3072SJian Shen int ret; 866d97b3072SJian Shen 867d97b3072SJian Shen if (handle->pdev->revision == 0x20) 868d97b3072SJian Shen return -EOPNOTSUPP; 869d97b3072SJian Shen 870d97b3072SJian Shen if (nfc->data & 871d97b3072SJian Shen ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 872d97b3072SJian Shen return -EINVAL; 873d97b3072SJian Shen 874d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 875d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 876d97b3072SJian Shen 877d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 878d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 879d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 880d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 881d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 882d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 883d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 884d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 885d97b3072SJian Shen 886d97b3072SJian Shen tuple_sets = hclgevf_get_rss_hash_bits(nfc); 887d97b3072SJian Shen switch (nfc->flow_type) { 888d97b3072SJian Shen case TCP_V4_FLOW: 889d97b3072SJian Shen req->ipv4_tcp_en = tuple_sets; 890d97b3072SJian Shen break; 891d97b3072SJian Shen case TCP_V6_FLOW: 892d97b3072SJian Shen req->ipv6_tcp_en = tuple_sets; 893d97b3072SJian Shen break; 894d97b3072SJian Shen case UDP_V4_FLOW: 895d97b3072SJian Shen req->ipv4_udp_en = tuple_sets; 896d97b3072SJian Shen break; 897d97b3072SJian Shen case UDP_V6_FLOW: 898d97b3072SJian Shen req->ipv6_udp_en = tuple_sets; 899d97b3072SJian Shen break; 900d97b3072SJian Shen case SCTP_V4_FLOW: 901d97b3072SJian Shen req->ipv4_sctp_en = tuple_sets; 902d97b3072SJian Shen break; 903d97b3072SJian Shen case SCTP_V6_FLOW: 904d97b3072SJian Shen if ((nfc->data & RXH_L4_B_0_1) || 905d97b3072SJian Shen (nfc->data & RXH_L4_B_2_3)) 906d97b3072SJian Shen return -EINVAL; 907d97b3072SJian Shen 908d97b3072SJian Shen req->ipv6_sctp_en = tuple_sets; 909d97b3072SJian Shen break; 910d97b3072SJian Shen case IPV4_FLOW: 911d97b3072SJian Shen req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 912d97b3072SJian Shen break; 913d97b3072SJian Shen case IPV6_FLOW: 914d97b3072SJian Shen req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 915d97b3072SJian Shen break; 916d97b3072SJian Shen default: 917d97b3072SJian Shen return -EINVAL; 918d97b3072SJian Shen } 919d97b3072SJian Shen 920d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 921d97b3072SJian Shen if (ret) { 922d97b3072SJian Shen dev_err(&hdev->pdev->dev, 923d97b3072SJian Shen "Set rss tuple fail, status = %d\n", ret); 924d97b3072SJian Shen return ret; 925d97b3072SJian Shen } 926d97b3072SJian Shen 927d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 928d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 929d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 930d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 931d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 932d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 933d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 934d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 935d97b3072SJian Shen return 0; 936d97b3072SJian Shen } 937d97b3072SJian Shen 938d97b3072SJian Shen static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 939d97b3072SJian Shen struct ethtool_rxnfc *nfc) 940d97b3072SJian Shen { 941d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 942d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 943d97b3072SJian Shen u8 tuple_sets; 944d97b3072SJian Shen 945d97b3072SJian Shen if (handle->pdev->revision == 0x20) 946d97b3072SJian Shen return -EOPNOTSUPP; 947d97b3072SJian Shen 948d97b3072SJian Shen nfc->data = 0; 949d97b3072SJian Shen 950d97b3072SJian Shen switch (nfc->flow_type) { 951d97b3072SJian Shen case TCP_V4_FLOW: 952d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 953d97b3072SJian Shen break; 954d97b3072SJian Shen case UDP_V4_FLOW: 955d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 956d97b3072SJian Shen break; 957d97b3072SJian Shen case TCP_V6_FLOW: 958d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 959d97b3072SJian Shen break; 960d97b3072SJian Shen case UDP_V6_FLOW: 961d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 962d97b3072SJian Shen break; 963d97b3072SJian Shen case SCTP_V4_FLOW: 964d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 965d97b3072SJian Shen break; 966d97b3072SJian Shen case SCTP_V6_FLOW: 967d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 968d97b3072SJian Shen break; 969d97b3072SJian Shen case IPV4_FLOW: 970d97b3072SJian Shen case IPV6_FLOW: 971d97b3072SJian Shen tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 972d97b3072SJian Shen break; 973d97b3072SJian Shen default: 974d97b3072SJian Shen return -EINVAL; 975d97b3072SJian Shen } 976d97b3072SJian Shen 977d97b3072SJian Shen if (!tuple_sets) 978d97b3072SJian Shen return 0; 979d97b3072SJian Shen 980d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_PORT_BIT) 981d97b3072SJian Shen nfc->data |= RXH_L4_B_2_3; 982d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_PORT_BIT) 983d97b3072SJian Shen nfc->data |= RXH_L4_B_0_1; 984d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_IP_BIT) 985d97b3072SJian Shen nfc->data |= RXH_IP_DST; 986d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_IP_BIT) 987d97b3072SJian Shen nfc->data |= RXH_IP_SRC; 988d97b3072SJian Shen 989d97b3072SJian Shen return 0; 990d97b3072SJian Shen } 991d97b3072SJian Shen 992d97b3072SJian Shen static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 993d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg) 994d97b3072SJian Shen { 995d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 996d97b3072SJian Shen struct hclgevf_desc desc; 997d97b3072SJian Shen int ret; 998d97b3072SJian Shen 999d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 1000d97b3072SJian Shen 1001d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 1002d97b3072SJian Shen 1003d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 1004d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 1005d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 1006d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 1007d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 1008d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 1009d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 1010d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 1011d97b3072SJian Shen 1012d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1013d97b3072SJian Shen if (ret) 1014d97b3072SJian Shen dev_err(&hdev->pdev->dev, 1015d97b3072SJian Shen "Configure rss input fail, status = %d\n", ret); 1016d97b3072SJian Shen return ret; 1017d97b3072SJian Shen } 1018d97b3072SJian Shen 1019e2cb1decSSalil Mehta static int hclgevf_get_tc_size(struct hnae3_handle *handle) 1020e2cb1decSSalil Mehta { 1021e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1022e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1023e2cb1decSSalil Mehta 1024e2cb1decSSalil Mehta return rss_cfg->rss_size; 1025e2cb1decSSalil Mehta } 1026e2cb1decSSalil Mehta 1027e2cb1decSSalil Mehta static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 1028b204bc74SPeng Li int vector_id, 1029e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1030e2cb1decSSalil Mehta { 1031e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1032d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1033e2cb1decSSalil Mehta struct hnae3_ring_chain_node *node; 1034e2cb1decSSalil Mehta int status; 1035d3410018SYufeng Mo int i = 0; 1036e2cb1decSSalil Mehta 1037d3410018SYufeng Mo memset(&send_msg, 0, sizeof(send_msg)); 1038d3410018SYufeng Mo send_msg.code = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 1039c09ba484SPeng Li HCLGE_MBX_UNMAP_RING_TO_VECTOR; 1040d3410018SYufeng Mo send_msg.vector_id = vector_id; 1041e2cb1decSSalil Mehta 1042e2cb1decSSalil Mehta for (node = ring_chain; node; node = node->next) { 1043d3410018SYufeng Mo send_msg.param[i].ring_type = 1044e4e87715SPeng Li hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 1045d3410018SYufeng Mo 1046d3410018SYufeng Mo send_msg.param[i].tqp_index = node->tqp_index; 1047d3410018SYufeng Mo send_msg.param[i].int_gl_index = 1048d3410018SYufeng Mo hnae3_get_field(node->int_gl_idx, 104979eee410SFuyun Liang HNAE3_RING_GL_IDX_M, 105079eee410SFuyun Liang HNAE3_RING_GL_IDX_S); 105179eee410SFuyun Liang 10525d02a58dSYunsheng Lin i++; 1053d3410018SYufeng Mo if (i == HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM || !node->next) { 1054d3410018SYufeng Mo send_msg.ring_num = i; 1055e2cb1decSSalil Mehta 1056d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, false, 1057d3410018SYufeng Mo NULL, 0); 1058e2cb1decSSalil Mehta if (status) { 1059e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1060e2cb1decSSalil Mehta "Map TQP fail, status is %d.\n", 1061e2cb1decSSalil Mehta status); 1062e2cb1decSSalil Mehta return status; 1063e2cb1decSSalil Mehta } 1064e2cb1decSSalil Mehta i = 0; 1065e2cb1decSSalil Mehta } 1066e2cb1decSSalil Mehta } 1067e2cb1decSSalil Mehta 1068e2cb1decSSalil Mehta return 0; 1069e2cb1decSSalil Mehta } 1070e2cb1decSSalil Mehta 1071e2cb1decSSalil Mehta static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1072e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1073e2cb1decSSalil Mehta { 1074b204bc74SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1075b204bc74SPeng Li int vector_id; 1076b204bc74SPeng Li 1077b204bc74SPeng Li vector_id = hclgevf_get_vector_index(hdev, vector); 1078b204bc74SPeng Li if (vector_id < 0) { 1079b204bc74SPeng Li dev_err(&handle->pdev->dev, 1080b204bc74SPeng Li "Get vector index fail. ret =%d\n", vector_id); 1081b204bc74SPeng Li return vector_id; 1082b204bc74SPeng Li } 1083b204bc74SPeng Li 1084b204bc74SPeng Li return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1085e2cb1decSSalil Mehta } 1086e2cb1decSSalil Mehta 1087e2cb1decSSalil Mehta static int hclgevf_unmap_ring_from_vector( 1088e2cb1decSSalil Mehta struct hnae3_handle *handle, 1089e2cb1decSSalil Mehta int vector, 1090e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1091e2cb1decSSalil Mehta { 1092e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1093e2cb1decSSalil Mehta int ret, vector_id; 1094e2cb1decSSalil Mehta 1095dea846e8SHuazhong Tan if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1096dea846e8SHuazhong Tan return 0; 1097dea846e8SHuazhong Tan 1098e2cb1decSSalil Mehta vector_id = hclgevf_get_vector_index(hdev, vector); 1099e2cb1decSSalil Mehta if (vector_id < 0) { 1100e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1101e2cb1decSSalil Mehta "Get vector index fail. ret =%d\n", vector_id); 1102e2cb1decSSalil Mehta return vector_id; 1103e2cb1decSSalil Mehta } 1104e2cb1decSSalil Mehta 1105b204bc74SPeng Li ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 11060d3e6631SYunsheng Lin if (ret) 1107e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1108e2cb1decSSalil Mehta "Unmap ring from vector fail. vector=%d, ret =%d\n", 1109e2cb1decSSalil Mehta vector_id, 1110e2cb1decSSalil Mehta ret); 11110d3e6631SYunsheng Lin 1112e2cb1decSSalil Mehta return ret; 1113e2cb1decSSalil Mehta } 1114e2cb1decSSalil Mehta 11150d3e6631SYunsheng Lin static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 11160d3e6631SYunsheng Lin { 11170d3e6631SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 111803718db9SYunsheng Lin int vector_id; 11190d3e6631SYunsheng Lin 112003718db9SYunsheng Lin vector_id = hclgevf_get_vector_index(hdev, vector); 112103718db9SYunsheng Lin if (vector_id < 0) { 112203718db9SYunsheng Lin dev_err(&handle->pdev->dev, 112303718db9SYunsheng Lin "hclgevf_put_vector get vector index fail. ret =%d\n", 112403718db9SYunsheng Lin vector_id); 112503718db9SYunsheng Lin return vector_id; 112603718db9SYunsheng Lin } 112703718db9SYunsheng Lin 112803718db9SYunsheng Lin hclgevf_free_vector(hdev, vector_id); 1129e2cb1decSSalil Mehta 1130e2cb1decSSalil Mehta return 0; 1131e2cb1decSSalil Mehta } 1132e2cb1decSSalil Mehta 11333b75c3dfSPeng Li static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1134e196ec75SJian Shen bool en_uc_pmc, bool en_mc_pmc, 1135f01f5559SJian Shen bool en_bc_pmc) 1136e2cb1decSSalil Mehta { 1137d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1138f01f5559SJian Shen int ret; 1139e2cb1decSSalil Mehta 1140d3410018SYufeng Mo memset(&send_msg, 0, sizeof(send_msg)); 1141d3410018SYufeng Mo send_msg.code = HCLGE_MBX_SET_PROMISC_MODE; 1142d3410018SYufeng Mo send_msg.en_bc = en_bc_pmc ? 1 : 0; 1143d3410018SYufeng Mo send_msg.en_uc = en_uc_pmc ? 1 : 0; 1144d3410018SYufeng Mo send_msg.en_mc = en_mc_pmc ? 1 : 0; 1145e2cb1decSSalil Mehta 1146d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1147f01f5559SJian Shen if (ret) 1148e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1149f01f5559SJian Shen "Set promisc mode fail, status is %d.\n", ret); 1150e2cb1decSSalil Mehta 1151f01f5559SJian Shen return ret; 1152e2cb1decSSalil Mehta } 1153e2cb1decSSalil Mehta 1154e196ec75SJian Shen static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 1155e196ec75SJian Shen bool en_mc_pmc) 1156e2cb1decSSalil Mehta { 1157e196ec75SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1158e196ec75SJian Shen struct pci_dev *pdev = hdev->pdev; 1159e196ec75SJian Shen bool en_bc_pmc; 1160e196ec75SJian Shen 1161e196ec75SJian Shen en_bc_pmc = pdev->revision != 0x20; 1162e196ec75SJian Shen 1163e196ec75SJian Shen return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc, 1164e196ec75SJian Shen en_bc_pmc); 1165e2cb1decSSalil Mehta } 1166e2cb1decSSalil Mehta 1167c631c696SJian Shen static void hclgevf_request_update_promisc_mode(struct hnae3_handle *handle) 1168c631c696SJian Shen { 1169c631c696SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1170c631c696SJian Shen 1171c631c696SJian Shen set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 1172c631c696SJian Shen } 1173c631c696SJian Shen 1174c631c696SJian Shen static void hclgevf_sync_promisc_mode(struct hclgevf_dev *hdev) 1175c631c696SJian Shen { 1176c631c696SJian Shen struct hnae3_handle *handle = &hdev->nic; 1177c631c696SJian Shen bool en_uc_pmc = handle->netdev_flags & HNAE3_UPE; 1178c631c696SJian Shen bool en_mc_pmc = handle->netdev_flags & HNAE3_MPE; 1179c631c696SJian Shen int ret; 1180c631c696SJian Shen 1181c631c696SJian Shen if (test_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state)) { 1182c631c696SJian Shen ret = hclgevf_set_promisc_mode(handle, en_uc_pmc, en_mc_pmc); 1183c631c696SJian Shen if (!ret) 1184c631c696SJian Shen clear_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 1185c631c696SJian Shen } 1186c631c696SJian Shen } 1187c631c696SJian Shen 1188ebaf1908SWeihang Li static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, unsigned int tqp_id, 1189e2cb1decSSalil Mehta int stream_id, bool enable) 1190e2cb1decSSalil Mehta { 1191e2cb1decSSalil Mehta struct hclgevf_cfg_com_tqp_queue_cmd *req; 1192e2cb1decSSalil Mehta struct hclgevf_desc desc; 1193e2cb1decSSalil Mehta int status; 1194e2cb1decSSalil Mehta 1195e2cb1decSSalil Mehta req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1196e2cb1decSSalil Mehta 1197e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1198e2cb1decSSalil Mehta false); 1199e2cb1decSSalil Mehta req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1200e2cb1decSSalil Mehta req->stream_id = cpu_to_le16(stream_id); 1201ebaf1908SWeihang Li if (enable) 1202ebaf1908SWeihang Li req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 1203e2cb1decSSalil Mehta 1204e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1205e2cb1decSSalil Mehta if (status) 1206e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1207e2cb1decSSalil Mehta "TQP enable fail, status =%d.\n", status); 1208e2cb1decSSalil Mehta 1209e2cb1decSSalil Mehta return status; 1210e2cb1decSSalil Mehta } 1211e2cb1decSSalil Mehta 1212e2cb1decSSalil Mehta static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1213e2cb1decSSalil Mehta { 1214b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1215e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 1216e2cb1decSSalil Mehta int i; 1217e2cb1decSSalil Mehta 1218b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 1219b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1220e2cb1decSSalil Mehta memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1221e2cb1decSSalil Mehta } 1222e2cb1decSSalil Mehta } 1223e2cb1decSSalil Mehta 12248e6de441SHuazhong Tan static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p) 12258e6de441SHuazhong Tan { 1226d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 12278e6de441SHuazhong Tan u8 host_mac[ETH_ALEN]; 12288e6de441SHuazhong Tan int status; 12298e6de441SHuazhong Tan 1230d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MAC_ADDR, 0); 1231d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, true, host_mac, 1232d3410018SYufeng Mo ETH_ALEN); 12338e6de441SHuazhong Tan if (status) { 12348e6de441SHuazhong Tan dev_err(&hdev->pdev->dev, 12358e6de441SHuazhong Tan "fail to get VF MAC from host %d", status); 12368e6de441SHuazhong Tan return status; 12378e6de441SHuazhong Tan } 12388e6de441SHuazhong Tan 12398e6de441SHuazhong Tan ether_addr_copy(p, host_mac); 12408e6de441SHuazhong Tan 12418e6de441SHuazhong Tan return 0; 12428e6de441SHuazhong Tan } 12438e6de441SHuazhong Tan 1244e2cb1decSSalil Mehta static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1245e2cb1decSSalil Mehta { 1246e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 12478e6de441SHuazhong Tan u8 host_mac_addr[ETH_ALEN]; 1248e2cb1decSSalil Mehta 12498e6de441SHuazhong Tan if (hclgevf_get_host_mac_addr(hdev, host_mac_addr)) 12508e6de441SHuazhong Tan return; 12518e6de441SHuazhong Tan 12528e6de441SHuazhong Tan hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr); 12538e6de441SHuazhong Tan if (hdev->has_pf_mac) 12548e6de441SHuazhong Tan ether_addr_copy(p, host_mac_addr); 12558e6de441SHuazhong Tan else 1256e2cb1decSSalil Mehta ether_addr_copy(p, hdev->hw.mac.mac_addr); 1257e2cb1decSSalil Mehta } 1258e2cb1decSSalil Mehta 125959098055SFuyun Liang static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 126059098055SFuyun Liang bool is_first) 1261e2cb1decSSalil Mehta { 1262e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1263e2cb1decSSalil Mehta u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1264d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1265e2cb1decSSalil Mehta u8 *new_mac_addr = (u8 *)p; 1266e2cb1decSSalil Mehta int status; 1267e2cb1decSSalil Mehta 1268d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 0); 1269ee4bcd3bSJian Shen send_msg.subcode = HCLGE_MBX_MAC_VLAN_UC_MODIFY; 1270d3410018SYufeng Mo ether_addr_copy(send_msg.data, new_mac_addr); 1271ee4bcd3bSJian Shen if (is_first && !hdev->has_pf_mac) 1272ee4bcd3bSJian Shen eth_zero_addr(&send_msg.data[ETH_ALEN]); 1273ee4bcd3bSJian Shen else 1274d3410018SYufeng Mo ether_addr_copy(&send_msg.data[ETH_ALEN], old_mac_addr); 1275d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1276e2cb1decSSalil Mehta if (!status) 1277e2cb1decSSalil Mehta ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1278e2cb1decSSalil Mehta 1279e2cb1decSSalil Mehta return status; 1280e2cb1decSSalil Mehta } 1281e2cb1decSSalil Mehta 1282ee4bcd3bSJian Shen static struct hclgevf_mac_addr_node * 1283ee4bcd3bSJian Shen hclgevf_find_mac_node(struct list_head *list, const u8 *mac_addr) 1284ee4bcd3bSJian Shen { 1285ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp; 1286ee4bcd3bSJian Shen 1287ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, list, node) 1288ee4bcd3bSJian Shen if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 1289ee4bcd3bSJian Shen return mac_node; 1290ee4bcd3bSJian Shen 1291ee4bcd3bSJian Shen return NULL; 1292ee4bcd3bSJian Shen } 1293ee4bcd3bSJian Shen 1294ee4bcd3bSJian Shen static void hclgevf_update_mac_node(struct hclgevf_mac_addr_node *mac_node, 1295ee4bcd3bSJian Shen enum HCLGEVF_MAC_NODE_STATE state) 1296ee4bcd3bSJian Shen { 1297ee4bcd3bSJian Shen switch (state) { 1298ee4bcd3bSJian Shen /* from set_rx_mode or tmp_add_list */ 1299ee4bcd3bSJian Shen case HCLGEVF_MAC_TO_ADD: 1300ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_DEL) 1301ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_ACTIVE; 1302ee4bcd3bSJian Shen break; 1303ee4bcd3bSJian Shen /* only from set_rx_mode */ 1304ee4bcd3bSJian Shen case HCLGEVF_MAC_TO_DEL: 1305ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1306ee4bcd3bSJian Shen list_del(&mac_node->node); 1307ee4bcd3bSJian Shen kfree(mac_node); 1308ee4bcd3bSJian Shen } else { 1309ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_TO_DEL; 1310ee4bcd3bSJian Shen } 1311ee4bcd3bSJian Shen break; 1312ee4bcd3bSJian Shen /* only from tmp_add_list, the mac_node->state won't be 1313ee4bcd3bSJian Shen * HCLGEVF_MAC_ACTIVE 1314ee4bcd3bSJian Shen */ 1315ee4bcd3bSJian Shen case HCLGEVF_MAC_ACTIVE: 1316ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1317ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_ACTIVE; 1318ee4bcd3bSJian Shen break; 1319ee4bcd3bSJian Shen } 1320ee4bcd3bSJian Shen } 1321ee4bcd3bSJian Shen 1322ee4bcd3bSJian Shen static int hclgevf_update_mac_list(struct hnae3_handle *handle, 1323ee4bcd3bSJian Shen enum HCLGEVF_MAC_NODE_STATE state, 1324ee4bcd3bSJian Shen enum HCLGEVF_MAC_ADDR_TYPE mac_type, 1325e2cb1decSSalil Mehta const unsigned char *addr) 1326e2cb1decSSalil Mehta { 1327e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1328ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node; 1329ee4bcd3bSJian Shen struct list_head *list; 1330e2cb1decSSalil Mehta 1331ee4bcd3bSJian Shen list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1332ee4bcd3bSJian Shen &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1333ee4bcd3bSJian Shen 1334ee4bcd3bSJian Shen spin_lock_bh(&hdev->mac_table.mac_list_lock); 1335ee4bcd3bSJian Shen 1336ee4bcd3bSJian Shen /* if the mac addr is already in the mac list, no need to add a new 1337ee4bcd3bSJian Shen * one into it, just check the mac addr state, convert it to a new 1338ee4bcd3bSJian Shen * new state, or just remove it, or do nothing. 1339ee4bcd3bSJian Shen */ 1340ee4bcd3bSJian Shen mac_node = hclgevf_find_mac_node(list, addr); 1341ee4bcd3bSJian Shen if (mac_node) { 1342ee4bcd3bSJian Shen hclgevf_update_mac_node(mac_node, state); 1343ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1344ee4bcd3bSJian Shen return 0; 1345ee4bcd3bSJian Shen } 1346ee4bcd3bSJian Shen /* if this address is never added, unnecessary to delete */ 1347ee4bcd3bSJian Shen if (state == HCLGEVF_MAC_TO_DEL) { 1348ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1349ee4bcd3bSJian Shen return -ENOENT; 1350ee4bcd3bSJian Shen } 1351ee4bcd3bSJian Shen 1352ee4bcd3bSJian Shen mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 1353ee4bcd3bSJian Shen if (!mac_node) { 1354ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1355ee4bcd3bSJian Shen return -ENOMEM; 1356ee4bcd3bSJian Shen } 1357ee4bcd3bSJian Shen 1358ee4bcd3bSJian Shen mac_node->state = state; 1359ee4bcd3bSJian Shen ether_addr_copy(mac_node->mac_addr, addr); 1360ee4bcd3bSJian Shen list_add_tail(&mac_node->node, list); 1361ee4bcd3bSJian Shen 1362ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1363ee4bcd3bSJian Shen return 0; 1364ee4bcd3bSJian Shen } 1365ee4bcd3bSJian Shen 1366ee4bcd3bSJian Shen static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1367ee4bcd3bSJian Shen const unsigned char *addr) 1368ee4bcd3bSJian Shen { 1369ee4bcd3bSJian Shen return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1370ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_UC, addr); 1371e2cb1decSSalil Mehta } 1372e2cb1decSSalil Mehta 1373e2cb1decSSalil Mehta static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1374e2cb1decSSalil Mehta const unsigned char *addr) 1375e2cb1decSSalil Mehta { 1376ee4bcd3bSJian Shen return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1377ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_UC, addr); 1378e2cb1decSSalil Mehta } 1379e2cb1decSSalil Mehta 1380e2cb1decSSalil Mehta static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1381e2cb1decSSalil Mehta const unsigned char *addr) 1382e2cb1decSSalil Mehta { 1383ee4bcd3bSJian Shen return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1384ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_MC, addr); 1385e2cb1decSSalil Mehta } 1386e2cb1decSSalil Mehta 1387e2cb1decSSalil Mehta static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1388e2cb1decSSalil Mehta const unsigned char *addr) 1389e2cb1decSSalil Mehta { 1390ee4bcd3bSJian Shen return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1391ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_MC, addr); 1392ee4bcd3bSJian Shen } 1393e2cb1decSSalil Mehta 1394ee4bcd3bSJian Shen static int hclgevf_add_del_mac_addr(struct hclgevf_dev *hdev, 1395ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, 1396ee4bcd3bSJian Shen enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1397ee4bcd3bSJian Shen { 1398ee4bcd3bSJian Shen struct hclge_vf_to_pf_msg send_msg; 1399ee4bcd3bSJian Shen u8 code, subcode; 1400ee4bcd3bSJian Shen 1401ee4bcd3bSJian Shen if (mac_type == HCLGEVF_MAC_ADDR_UC) { 1402ee4bcd3bSJian Shen code = HCLGE_MBX_SET_UNICAST; 1403ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1404ee4bcd3bSJian Shen subcode = HCLGE_MBX_MAC_VLAN_UC_ADD; 1405ee4bcd3bSJian Shen else 1406ee4bcd3bSJian Shen subcode = HCLGE_MBX_MAC_VLAN_UC_REMOVE; 1407ee4bcd3bSJian Shen } else { 1408ee4bcd3bSJian Shen code = HCLGE_MBX_SET_MULTICAST; 1409ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1410ee4bcd3bSJian Shen subcode = HCLGE_MBX_MAC_VLAN_MC_ADD; 1411ee4bcd3bSJian Shen else 1412ee4bcd3bSJian Shen subcode = HCLGE_MBX_MAC_VLAN_MC_REMOVE; 1413ee4bcd3bSJian Shen } 1414ee4bcd3bSJian Shen 1415ee4bcd3bSJian Shen hclgevf_build_send_msg(&send_msg, code, subcode); 1416ee4bcd3bSJian Shen ether_addr_copy(send_msg.data, mac_node->mac_addr); 1417d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1418e2cb1decSSalil Mehta } 1419e2cb1decSSalil Mehta 1420ee4bcd3bSJian Shen static void hclgevf_config_mac_list(struct hclgevf_dev *hdev, 1421ee4bcd3bSJian Shen struct list_head *list, 1422ee4bcd3bSJian Shen enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1423ee4bcd3bSJian Shen { 1424ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp; 1425ee4bcd3bSJian Shen int ret; 1426ee4bcd3bSJian Shen 1427ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, list, node) { 1428ee4bcd3bSJian Shen ret = hclgevf_add_del_mac_addr(hdev, mac_node, mac_type); 1429ee4bcd3bSJian Shen if (ret) { 1430ee4bcd3bSJian Shen dev_err(&hdev->pdev->dev, 1431ee4bcd3bSJian Shen "failed to configure mac %pM, state = %d, ret = %d\n", 1432ee4bcd3bSJian Shen mac_node->mac_addr, mac_node->state, ret); 1433ee4bcd3bSJian Shen return; 1434ee4bcd3bSJian Shen } 1435ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1436ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_ACTIVE; 1437ee4bcd3bSJian Shen } else { 1438ee4bcd3bSJian Shen list_del(&mac_node->node); 1439ee4bcd3bSJian Shen kfree(mac_node); 1440ee4bcd3bSJian Shen } 1441ee4bcd3bSJian Shen } 1442ee4bcd3bSJian Shen } 1443ee4bcd3bSJian Shen 1444ee4bcd3bSJian Shen static void hclgevf_sync_from_add_list(struct list_head *add_list, 1445ee4bcd3bSJian Shen struct list_head *mac_list) 1446ee4bcd3bSJian Shen { 1447ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1448ee4bcd3bSJian Shen 1449ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, add_list, node) { 1450ee4bcd3bSJian Shen /* if the mac address from tmp_add_list is not in the 1451ee4bcd3bSJian Shen * uc/mc_mac_list, it means have received a TO_DEL request 1452ee4bcd3bSJian Shen * during the time window of sending mac config request to PF 1453ee4bcd3bSJian Shen * If mac_node state is ACTIVE, then change its state to TO_DEL, 1454ee4bcd3bSJian Shen * then it will be removed at next time. If is TO_ADD, it means 1455ee4bcd3bSJian Shen * send TO_ADD request failed, so just remove the mac node. 1456ee4bcd3bSJian Shen */ 1457ee4bcd3bSJian Shen new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1458ee4bcd3bSJian Shen if (new_node) { 1459ee4bcd3bSJian Shen hclgevf_update_mac_node(new_node, mac_node->state); 1460ee4bcd3bSJian Shen list_del(&mac_node->node); 1461ee4bcd3bSJian Shen kfree(mac_node); 1462ee4bcd3bSJian Shen } else if (mac_node->state == HCLGEVF_MAC_ACTIVE) { 1463ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_TO_DEL; 1464ee4bcd3bSJian Shen list_del(&mac_node->node); 1465ee4bcd3bSJian Shen list_add_tail(&mac_node->node, mac_list); 1466ee4bcd3bSJian Shen } else { 1467ee4bcd3bSJian Shen list_del(&mac_node->node); 1468ee4bcd3bSJian Shen kfree(mac_node); 1469ee4bcd3bSJian Shen } 1470ee4bcd3bSJian Shen } 1471ee4bcd3bSJian Shen } 1472ee4bcd3bSJian Shen 1473ee4bcd3bSJian Shen static void hclgevf_sync_from_del_list(struct list_head *del_list, 1474ee4bcd3bSJian Shen struct list_head *mac_list) 1475ee4bcd3bSJian Shen { 1476ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1477ee4bcd3bSJian Shen 1478ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, del_list, node) { 1479ee4bcd3bSJian Shen new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1480ee4bcd3bSJian Shen if (new_node) { 1481ee4bcd3bSJian Shen /* If the mac addr is exist in the mac list, it means 1482ee4bcd3bSJian Shen * received a new request TO_ADD during the time window 1483ee4bcd3bSJian Shen * of sending mac addr configurrequest to PF, so just 1484ee4bcd3bSJian Shen * change the mac state to ACTIVE. 1485ee4bcd3bSJian Shen */ 1486ee4bcd3bSJian Shen new_node->state = HCLGEVF_MAC_ACTIVE; 1487ee4bcd3bSJian Shen list_del(&mac_node->node); 1488ee4bcd3bSJian Shen kfree(mac_node); 1489ee4bcd3bSJian Shen } else { 1490ee4bcd3bSJian Shen list_del(&mac_node->node); 1491ee4bcd3bSJian Shen list_add_tail(&mac_node->node, mac_list); 1492ee4bcd3bSJian Shen } 1493ee4bcd3bSJian Shen } 1494ee4bcd3bSJian Shen } 1495ee4bcd3bSJian Shen 1496ee4bcd3bSJian Shen static void hclgevf_clear_list(struct list_head *list) 1497ee4bcd3bSJian Shen { 1498ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp; 1499ee4bcd3bSJian Shen 1500ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, list, node) { 1501ee4bcd3bSJian Shen list_del(&mac_node->node); 1502ee4bcd3bSJian Shen kfree(mac_node); 1503ee4bcd3bSJian Shen } 1504ee4bcd3bSJian Shen } 1505ee4bcd3bSJian Shen 1506ee4bcd3bSJian Shen static void hclgevf_sync_mac_list(struct hclgevf_dev *hdev, 1507ee4bcd3bSJian Shen enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1508ee4bcd3bSJian Shen { 1509ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1510ee4bcd3bSJian Shen struct list_head tmp_add_list, tmp_del_list; 1511ee4bcd3bSJian Shen struct list_head *list; 1512ee4bcd3bSJian Shen 1513ee4bcd3bSJian Shen INIT_LIST_HEAD(&tmp_add_list); 1514ee4bcd3bSJian Shen INIT_LIST_HEAD(&tmp_del_list); 1515ee4bcd3bSJian Shen 1516ee4bcd3bSJian Shen /* move the mac addr to the tmp_add_list and tmp_del_list, then 1517ee4bcd3bSJian Shen * we can add/delete these mac addr outside the spin lock 1518ee4bcd3bSJian Shen */ 1519ee4bcd3bSJian Shen list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1520ee4bcd3bSJian Shen &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1521ee4bcd3bSJian Shen 1522ee4bcd3bSJian Shen spin_lock_bh(&hdev->mac_table.mac_list_lock); 1523ee4bcd3bSJian Shen 1524ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, list, node) { 1525ee4bcd3bSJian Shen switch (mac_node->state) { 1526ee4bcd3bSJian Shen case HCLGEVF_MAC_TO_DEL: 1527ee4bcd3bSJian Shen list_del(&mac_node->node); 1528ee4bcd3bSJian Shen list_add_tail(&mac_node->node, &tmp_del_list); 1529ee4bcd3bSJian Shen break; 1530ee4bcd3bSJian Shen case HCLGEVF_MAC_TO_ADD: 1531ee4bcd3bSJian Shen new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 1532ee4bcd3bSJian Shen if (!new_node) 1533ee4bcd3bSJian Shen goto stop_traverse; 1534ee4bcd3bSJian Shen 1535ee4bcd3bSJian Shen ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 1536ee4bcd3bSJian Shen new_node->state = mac_node->state; 1537ee4bcd3bSJian Shen list_add_tail(&new_node->node, &tmp_add_list); 1538ee4bcd3bSJian Shen break; 1539ee4bcd3bSJian Shen default: 1540ee4bcd3bSJian Shen break; 1541ee4bcd3bSJian Shen } 1542ee4bcd3bSJian Shen } 1543ee4bcd3bSJian Shen 1544ee4bcd3bSJian Shen stop_traverse: 1545ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1546ee4bcd3bSJian Shen 1547ee4bcd3bSJian Shen /* delete first, in order to get max mac table space for adding */ 1548ee4bcd3bSJian Shen hclgevf_config_mac_list(hdev, &tmp_del_list, mac_type); 1549ee4bcd3bSJian Shen hclgevf_config_mac_list(hdev, &tmp_add_list, mac_type); 1550ee4bcd3bSJian Shen 1551ee4bcd3bSJian Shen /* if some mac addresses were added/deleted fail, move back to the 1552ee4bcd3bSJian Shen * mac_list, and retry at next time. 1553ee4bcd3bSJian Shen */ 1554ee4bcd3bSJian Shen spin_lock_bh(&hdev->mac_table.mac_list_lock); 1555ee4bcd3bSJian Shen 1556ee4bcd3bSJian Shen hclgevf_sync_from_del_list(&tmp_del_list, list); 1557ee4bcd3bSJian Shen hclgevf_sync_from_add_list(&tmp_add_list, list); 1558ee4bcd3bSJian Shen 1559ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1560ee4bcd3bSJian Shen } 1561ee4bcd3bSJian Shen 1562ee4bcd3bSJian Shen static void hclgevf_sync_mac_table(struct hclgevf_dev *hdev) 1563ee4bcd3bSJian Shen { 1564ee4bcd3bSJian Shen hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_UC); 1565ee4bcd3bSJian Shen hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_MC); 1566ee4bcd3bSJian Shen } 1567ee4bcd3bSJian Shen 1568ee4bcd3bSJian Shen static void hclgevf_uninit_mac_list(struct hclgevf_dev *hdev) 1569ee4bcd3bSJian Shen { 1570ee4bcd3bSJian Shen spin_lock_bh(&hdev->mac_table.mac_list_lock); 1571ee4bcd3bSJian Shen 1572ee4bcd3bSJian Shen hclgevf_clear_list(&hdev->mac_table.uc_mac_list); 1573ee4bcd3bSJian Shen hclgevf_clear_list(&hdev->mac_table.mc_mac_list); 1574ee4bcd3bSJian Shen 1575ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1576ee4bcd3bSJian Shen } 1577ee4bcd3bSJian Shen 1578e2cb1decSSalil Mehta static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1579e2cb1decSSalil Mehta __be16 proto, u16 vlan_id, 1580e2cb1decSSalil Mehta bool is_kill) 1581e2cb1decSSalil Mehta { 1582d3410018SYufeng Mo #define HCLGEVF_VLAN_MBX_IS_KILL_OFFSET 0 1583d3410018SYufeng Mo #define HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET 1 1584d3410018SYufeng Mo #define HCLGEVF_VLAN_MBX_PROTO_OFFSET 3 1585d3410018SYufeng Mo 1586e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1587d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1588fe4144d4SJian Shen int ret; 1589e2cb1decSSalil Mehta 1590b37ce587SYufeng Mo if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1591e2cb1decSSalil Mehta return -EINVAL; 1592e2cb1decSSalil Mehta 1593e2cb1decSSalil Mehta if (proto != htons(ETH_P_8021Q)) 1594e2cb1decSSalil Mehta return -EPROTONOSUPPORT; 1595e2cb1decSSalil Mehta 1596b7b5d25bSGuojia Liao /* When device is resetting or reset failed, firmware is unable to 1597b7b5d25bSGuojia Liao * handle mailbox. Just record the vlan id, and remove it after 1598fe4144d4SJian Shen * reset finished. 1599fe4144d4SJian Shen */ 1600b7b5d25bSGuojia Liao if ((test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 1601b7b5d25bSGuojia Liao test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) && is_kill) { 1602fe4144d4SJian Shen set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1603fe4144d4SJian Shen return -EBUSY; 1604fe4144d4SJian Shen } 1605fe4144d4SJian Shen 1606d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1607d3410018SYufeng Mo HCLGE_MBX_VLAN_FILTER); 1608d3410018SYufeng Mo send_msg.data[HCLGEVF_VLAN_MBX_IS_KILL_OFFSET] = is_kill; 1609d3410018SYufeng Mo memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET], &vlan_id, 1610d3410018SYufeng Mo sizeof(vlan_id)); 1611d3410018SYufeng Mo memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_PROTO_OFFSET], &proto, 1612d3410018SYufeng Mo sizeof(proto)); 161346ee7350SGuojia Liao /* when remove hw vlan filter failed, record the vlan id, 1614fe4144d4SJian Shen * and try to remove it from hw later, to be consistence 1615fe4144d4SJian Shen * with stack. 1616fe4144d4SJian Shen */ 1617d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1618fe4144d4SJian Shen if (is_kill && ret) 1619fe4144d4SJian Shen set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1620fe4144d4SJian Shen 1621fe4144d4SJian Shen return ret; 1622fe4144d4SJian Shen } 1623fe4144d4SJian Shen 1624fe4144d4SJian Shen static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1625fe4144d4SJian Shen { 1626fe4144d4SJian Shen #define HCLGEVF_MAX_SYNC_COUNT 60 1627fe4144d4SJian Shen struct hnae3_handle *handle = &hdev->nic; 1628fe4144d4SJian Shen int ret, sync_cnt = 0; 1629fe4144d4SJian Shen u16 vlan_id; 1630fe4144d4SJian Shen 1631fe4144d4SJian Shen vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1632fe4144d4SJian Shen while (vlan_id != VLAN_N_VID) { 1633fe4144d4SJian Shen ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1634fe4144d4SJian Shen vlan_id, true); 1635fe4144d4SJian Shen if (ret) 1636fe4144d4SJian Shen return; 1637fe4144d4SJian Shen 1638fe4144d4SJian Shen clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1639fe4144d4SJian Shen sync_cnt++; 1640fe4144d4SJian Shen if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1641fe4144d4SJian Shen return; 1642fe4144d4SJian Shen 1643fe4144d4SJian Shen vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1644fe4144d4SJian Shen } 1645e2cb1decSSalil Mehta } 1646e2cb1decSSalil Mehta 1647b2641e2aSYunsheng Lin static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1648b2641e2aSYunsheng Lin { 1649b2641e2aSYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1650d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1651b2641e2aSYunsheng Lin 1652d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1653d3410018SYufeng Mo HCLGE_MBX_VLAN_RX_OFF_CFG); 1654d3410018SYufeng Mo send_msg.data[0] = enable ? 1 : 0; 1655d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1656b2641e2aSYunsheng Lin } 1657b2641e2aSYunsheng Lin 16587fa6be4fSHuazhong Tan static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1659e2cb1decSSalil Mehta { 1660e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1661d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 16621a426f8bSPeng Li int ret; 1663e2cb1decSSalil Mehta 16641a426f8bSPeng Li /* disable vf queue before send queue reset msg to PF */ 16651a426f8bSPeng Li ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 16661a426f8bSPeng Li if (ret) 16677fa6be4fSHuazhong Tan return ret; 16681a426f8bSPeng Li 1669d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 1670d3410018SYufeng Mo memcpy(send_msg.data, &queue_id, sizeof(queue_id)); 1671d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1672e2cb1decSSalil Mehta } 1673e2cb1decSSalil Mehta 1674818f1675SYunsheng Lin static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1675818f1675SYunsheng Lin { 1676818f1675SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1677d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1678818f1675SYunsheng Lin 1679d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MTU, 0); 1680d3410018SYufeng Mo memcpy(send_msg.data, &new_mtu, sizeof(new_mtu)); 1681d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1682818f1675SYunsheng Lin } 1683818f1675SYunsheng Lin 16846988eb2aSSalil Mehta static int hclgevf_notify_client(struct hclgevf_dev *hdev, 16856988eb2aSSalil Mehta enum hnae3_reset_notify_type type) 16866988eb2aSSalil Mehta { 16876988eb2aSSalil Mehta struct hnae3_client *client = hdev->nic_client; 16886988eb2aSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 16896a5f6fa3SHuazhong Tan int ret; 16906988eb2aSSalil Mehta 169125d1817cSHuazhong Tan if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 169225d1817cSHuazhong Tan !client) 169325d1817cSHuazhong Tan return 0; 169425d1817cSHuazhong Tan 16956988eb2aSSalil Mehta if (!client->ops->reset_notify) 16966988eb2aSSalil Mehta return -EOPNOTSUPP; 16976988eb2aSSalil Mehta 16986a5f6fa3SHuazhong Tan ret = client->ops->reset_notify(handle, type); 16996a5f6fa3SHuazhong Tan if (ret) 17006a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 17016a5f6fa3SHuazhong Tan type, ret); 17026a5f6fa3SHuazhong Tan 17036a5f6fa3SHuazhong Tan return ret; 17046988eb2aSSalil Mehta } 17056988eb2aSSalil Mehta 17066988eb2aSSalil Mehta static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 17076988eb2aSSalil Mehta { 1708aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_US 20000 1709aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_CNT 2000 1710aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1711aa5c4f17SHuazhong Tan (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1712aa5c4f17SHuazhong Tan 1713aa5c4f17SHuazhong Tan u32 val; 1714aa5c4f17SHuazhong Tan int ret; 17156988eb2aSSalil Mehta 1716f28368bbSHuazhong Tan if (hdev->reset_type == HNAE3_VF_RESET) 171772e2fb07SHuazhong Tan ret = readl_poll_timeout(hdev->hw.io_base + 171872e2fb07SHuazhong Tan HCLGEVF_VF_RST_ING, val, 171972e2fb07SHuazhong Tan !(val & HCLGEVF_VF_RST_ING_BIT), 172072e2fb07SHuazhong Tan HCLGEVF_RESET_WAIT_US, 172172e2fb07SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 172272e2fb07SHuazhong Tan else 172372e2fb07SHuazhong Tan ret = readl_poll_timeout(hdev->hw.io_base + 172472e2fb07SHuazhong Tan HCLGEVF_RST_ING, val, 1725aa5c4f17SHuazhong Tan !(val & HCLGEVF_RST_ING_BITS), 1726aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_US, 1727aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 17286988eb2aSSalil Mehta 17296988eb2aSSalil Mehta /* hardware completion status should be available by this time */ 1730aa5c4f17SHuazhong Tan if (ret) { 1731aa5c4f17SHuazhong Tan dev_err(&hdev->pdev->dev, 17328912fd6aSColin Ian King "couldn't get reset done status from h/w, timeout!\n"); 1733aa5c4f17SHuazhong Tan return ret; 17346988eb2aSSalil Mehta } 17356988eb2aSSalil Mehta 17366988eb2aSSalil Mehta /* we will wait a bit more to let reset of the stack to complete. This 17376988eb2aSSalil Mehta * might happen in case reset assertion was made by PF. Yes, this also 17386988eb2aSSalil Mehta * means we might end up waiting bit more even for VF reset. 17396988eb2aSSalil Mehta */ 17406988eb2aSSalil Mehta msleep(5000); 17416988eb2aSSalil Mehta 17426988eb2aSSalil Mehta return 0; 17436988eb2aSSalil Mehta } 17446988eb2aSSalil Mehta 17456b428b4fSHuazhong Tan static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable) 17466b428b4fSHuazhong Tan { 17476b428b4fSHuazhong Tan u32 reg_val; 17486b428b4fSHuazhong Tan 17496b428b4fSHuazhong Tan reg_val = hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG); 17506b428b4fSHuazhong Tan if (enable) 17516b428b4fSHuazhong Tan reg_val |= HCLGEVF_NIC_SW_RST_RDY; 17526b428b4fSHuazhong Tan else 17536b428b4fSHuazhong Tan reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; 17546b428b4fSHuazhong Tan 17556b428b4fSHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 17566b428b4fSHuazhong Tan reg_val); 17576b428b4fSHuazhong Tan } 17586b428b4fSHuazhong Tan 17596988eb2aSSalil Mehta static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 17606988eb2aSSalil Mehta { 17617a01c897SSalil Mehta int ret; 17627a01c897SSalil Mehta 17636988eb2aSSalil Mehta /* uninitialize the nic client */ 17646a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 17656a5f6fa3SHuazhong Tan if (ret) 17666a5f6fa3SHuazhong Tan return ret; 17676988eb2aSSalil Mehta 17687a01c897SSalil Mehta /* re-initialize the hclge device */ 17699c6f7085SHuazhong Tan ret = hclgevf_reset_hdev(hdev); 17707a01c897SSalil Mehta if (ret) { 17717a01c897SSalil Mehta dev_err(&hdev->pdev->dev, 17727a01c897SSalil Mehta "hclge device re-init failed, VF is disabled!\n"); 17737a01c897SSalil Mehta return ret; 17747a01c897SSalil Mehta } 17756988eb2aSSalil Mehta 17766988eb2aSSalil Mehta /* bring up the nic client again */ 17776a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 17786a5f6fa3SHuazhong Tan if (ret) 17796a5f6fa3SHuazhong Tan return ret; 17806988eb2aSSalil Mehta 17816b428b4fSHuazhong Tan /* clear handshake status with IMP */ 17826b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, false); 17836b428b4fSHuazhong Tan 17841cc9bc6eSHuazhong Tan /* bring up the nic to enable TX/RX again */ 17851cc9bc6eSHuazhong Tan return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 17866988eb2aSSalil Mehta } 17876988eb2aSSalil Mehta 1788dea846e8SHuazhong Tan static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1789dea846e8SHuazhong Tan { 1790ada13ee3SHuazhong Tan #define HCLGEVF_RESET_SYNC_TIME 100 1791ada13ee3SHuazhong Tan 1792f28368bbSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FUNC_RESET) { 1793d41884eeSHuazhong Tan struct hclge_vf_to_pf_msg send_msg; 1794d41884eeSHuazhong Tan int ret; 1795d41884eeSHuazhong Tan 1796d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_RESET, 0); 1797d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1798cddd5648SHuazhong Tan if (ret) { 1799cddd5648SHuazhong Tan dev_err(&hdev->pdev->dev, 1800cddd5648SHuazhong Tan "failed to assert VF reset, ret = %d\n", ret); 1801cddd5648SHuazhong Tan return ret; 1802cddd5648SHuazhong Tan } 1803c88a6e7dSHuazhong Tan hdev->rst_stats.vf_func_rst_cnt++; 1804dea846e8SHuazhong Tan } 1805dea846e8SHuazhong Tan 1806ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1807ada13ee3SHuazhong Tan /* inform hardware that preparatory work is done */ 1808ada13ee3SHuazhong Tan msleep(HCLGEVF_RESET_SYNC_TIME); 18096b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, true); 1810d41884eeSHuazhong Tan dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done\n", 1811d41884eeSHuazhong Tan hdev->reset_type); 1812dea846e8SHuazhong Tan 1813d41884eeSHuazhong Tan return 0; 1814dea846e8SHuazhong Tan } 1815dea846e8SHuazhong Tan 18163d77d0cbSHuazhong Tan static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev) 18173d77d0cbSHuazhong Tan { 18183d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "VF function reset count: %u\n", 18193d77d0cbSHuazhong Tan hdev->rst_stats.vf_func_rst_cnt); 18203d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "FLR reset count: %u\n", 18213d77d0cbSHuazhong Tan hdev->rst_stats.flr_rst_cnt); 18223d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "VF reset count: %u\n", 18233d77d0cbSHuazhong Tan hdev->rst_stats.vf_rst_cnt); 18243d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "reset done count: %u\n", 18253d77d0cbSHuazhong Tan hdev->rst_stats.rst_done_cnt); 18263d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "HW reset done count: %u\n", 18273d77d0cbSHuazhong Tan hdev->rst_stats.hw_rst_done_cnt); 18283d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "reset count: %u\n", 18293d77d0cbSHuazhong Tan hdev->rst_stats.rst_cnt); 18303d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "reset fail count: %u\n", 18313d77d0cbSHuazhong Tan hdev->rst_stats.rst_fail_cnt); 18323d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n", 18333d77d0cbSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE)); 18343d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n", 18359cee2e8dSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_STATE_REG)); 18363d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n", 18373d77d0cbSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_CMDQ_TX_DEPTH_REG)); 18383d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n", 18393d77d0cbSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING)); 18403d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state); 18413d77d0cbSHuazhong Tan } 18423d77d0cbSHuazhong Tan 1843bbe6540eSHuazhong Tan static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1844bbe6540eSHuazhong Tan { 18456b428b4fSHuazhong Tan /* recover handshake status with IMP when reset fail */ 18466b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, true); 1847bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt++; 1848adcf738bSGuojia Liao dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n", 1849bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt); 1850bbe6540eSHuazhong Tan 1851bbe6540eSHuazhong Tan if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1852bbe6540eSHuazhong Tan set_bit(hdev->reset_type, &hdev->reset_pending); 1853bbe6540eSHuazhong Tan 1854bbe6540eSHuazhong Tan if (hclgevf_is_reset_pending(hdev)) { 1855bbe6540eSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1856bbe6540eSHuazhong Tan hclgevf_reset_task_schedule(hdev); 18573d77d0cbSHuazhong Tan } else { 1858d5432455SGuojia Liao set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 18593d77d0cbSHuazhong Tan hclgevf_dump_rst_info(hdev); 1860bbe6540eSHuazhong Tan } 1861bbe6540eSHuazhong Tan } 1862bbe6540eSHuazhong Tan 18631cc9bc6eSHuazhong Tan static int hclgevf_reset_prepare(struct hclgevf_dev *hdev) 18646988eb2aSSalil Mehta { 18656988eb2aSSalil Mehta int ret; 18666988eb2aSSalil Mehta 1867c88a6e7dSHuazhong Tan hdev->rst_stats.rst_cnt++; 18686988eb2aSSalil Mehta 18691cc9bc6eSHuazhong Tan rtnl_lock(); 18706988eb2aSSalil Mehta /* bring down the nic to stop any ongoing TX/RX */ 18716a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 187229118ab9SHuazhong Tan rtnl_unlock(); 18736a5f6fa3SHuazhong Tan if (ret) 18741cc9bc6eSHuazhong Tan return ret; 1875dea846e8SHuazhong Tan 18761cc9bc6eSHuazhong Tan return hclgevf_reset_prepare_wait(hdev); 18776988eb2aSSalil Mehta } 18786988eb2aSSalil Mehta 18791cc9bc6eSHuazhong Tan static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev) 18801cc9bc6eSHuazhong Tan { 18811cc9bc6eSHuazhong Tan int ret; 18821cc9bc6eSHuazhong Tan 1883c88a6e7dSHuazhong Tan hdev->rst_stats.hw_rst_done_cnt++; 1884c88a6e7dSHuazhong Tan 188529118ab9SHuazhong Tan rtnl_lock(); 18866988eb2aSSalil Mehta /* now, re-initialize the nic client and ae device */ 18876988eb2aSSalil Mehta ret = hclgevf_reset_stack(hdev); 18881cc9bc6eSHuazhong Tan rtnl_unlock(); 18896a5f6fa3SHuazhong Tan if (ret) { 18906988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 18911cc9bc6eSHuazhong Tan return ret; 18926a5f6fa3SHuazhong Tan } 18936988eb2aSSalil Mehta 1894b644a8d4SHuazhong Tan hdev->last_reset_time = jiffies; 1895c88a6e7dSHuazhong Tan hdev->rst_stats.rst_done_cnt++; 1896bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt = 0; 1897d5432455SGuojia Liao clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1898b644a8d4SHuazhong Tan 18991cc9bc6eSHuazhong Tan return 0; 19001cc9bc6eSHuazhong Tan } 19011cc9bc6eSHuazhong Tan 19021cc9bc6eSHuazhong Tan static void hclgevf_reset(struct hclgevf_dev *hdev) 19031cc9bc6eSHuazhong Tan { 19041cc9bc6eSHuazhong Tan if (hclgevf_reset_prepare(hdev)) 19051cc9bc6eSHuazhong Tan goto err_reset; 19061cc9bc6eSHuazhong Tan 19071cc9bc6eSHuazhong Tan /* check if VF could successfully fetch the hardware reset completion 19081cc9bc6eSHuazhong Tan * status from the hardware 19091cc9bc6eSHuazhong Tan */ 19101cc9bc6eSHuazhong Tan if (hclgevf_reset_wait(hdev)) { 19111cc9bc6eSHuazhong Tan /* can't do much in this situation, will disable VF */ 19121cc9bc6eSHuazhong Tan dev_err(&hdev->pdev->dev, 19131cc9bc6eSHuazhong Tan "failed to fetch H/W reset completion status\n"); 19141cc9bc6eSHuazhong Tan goto err_reset; 19151cc9bc6eSHuazhong Tan } 19161cc9bc6eSHuazhong Tan 19171cc9bc6eSHuazhong Tan if (hclgevf_reset_rebuild(hdev)) 19181cc9bc6eSHuazhong Tan goto err_reset; 19191cc9bc6eSHuazhong Tan 19201cc9bc6eSHuazhong Tan return; 19211cc9bc6eSHuazhong Tan 19226a5f6fa3SHuazhong Tan err_reset: 1923bbe6540eSHuazhong Tan hclgevf_reset_err_handle(hdev); 19246988eb2aSSalil Mehta } 19256988eb2aSSalil Mehta 1926720bd583SHuazhong Tan static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1927720bd583SHuazhong Tan unsigned long *addr) 1928720bd583SHuazhong Tan { 1929720bd583SHuazhong Tan enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1930720bd583SHuazhong Tan 1931dea846e8SHuazhong Tan /* return the highest priority reset level amongst all */ 1932b90fcc5bSHuazhong Tan if (test_bit(HNAE3_VF_RESET, addr)) { 1933b90fcc5bSHuazhong Tan rst_level = HNAE3_VF_RESET; 1934b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_RESET, addr); 1935b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1936b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1937b90fcc5bSHuazhong Tan } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1938dea846e8SHuazhong Tan rst_level = HNAE3_VF_FULL_RESET; 1939dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FULL_RESET, addr); 1940dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1941aa5c4f17SHuazhong Tan } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1942aa5c4f17SHuazhong Tan rst_level = HNAE3_VF_PF_FUNC_RESET; 1943aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1944aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1945dea846e8SHuazhong Tan } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1946dea846e8SHuazhong Tan rst_level = HNAE3_VF_FUNC_RESET; 1947dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 19486ff3cf07SHuazhong Tan } else if (test_bit(HNAE3_FLR_RESET, addr)) { 19496ff3cf07SHuazhong Tan rst_level = HNAE3_FLR_RESET; 19506ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_RESET, addr); 1951720bd583SHuazhong Tan } 1952720bd583SHuazhong Tan 1953720bd583SHuazhong Tan return rst_level; 1954720bd583SHuazhong Tan } 1955720bd583SHuazhong Tan 19566ae4e733SShiju Jose static void hclgevf_reset_event(struct pci_dev *pdev, 19576ae4e733SShiju Jose struct hnae3_handle *handle) 19586d4c3981SSalil Mehta { 19596ff3cf07SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 19606ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 19616d4c3981SSalil Mehta 19626d4c3981SSalil Mehta dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 19636d4c3981SSalil Mehta 19646ff3cf07SHuazhong Tan if (hdev->default_reset_request) 19650742ed7cSHuazhong Tan hdev->reset_level = 1966720bd583SHuazhong Tan hclgevf_get_reset_level(hdev, 1967720bd583SHuazhong Tan &hdev->default_reset_request); 1968720bd583SHuazhong Tan else 1969dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 19706d4c3981SSalil Mehta 1971436667d2SSalil Mehta /* reset of this VF requested */ 1972436667d2SSalil Mehta set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1973436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 19746d4c3981SSalil Mehta 19750742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 19766d4c3981SSalil Mehta } 19776d4c3981SSalil Mehta 1978720bd583SHuazhong Tan static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1979720bd583SHuazhong Tan enum hnae3_reset_type rst_type) 1980720bd583SHuazhong Tan { 1981720bd583SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1982720bd583SHuazhong Tan 1983720bd583SHuazhong Tan set_bit(rst_type, &hdev->default_reset_request); 1984720bd583SHuazhong Tan } 1985720bd583SHuazhong Tan 1986f28368bbSHuazhong Tan static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1987f28368bbSHuazhong Tan { 1988f28368bbSHuazhong Tan writel(en ? 1 : 0, vector->addr); 1989f28368bbSHuazhong Tan } 1990f28368bbSHuazhong Tan 19916ff3cf07SHuazhong Tan static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 19926ff3cf07SHuazhong Tan { 1993f28368bbSHuazhong Tan #define HCLGEVF_FLR_RETRY_WAIT_MS 500 1994f28368bbSHuazhong Tan #define HCLGEVF_FLR_RETRY_CNT 5 1995f28368bbSHuazhong Tan 19966ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1997f28368bbSHuazhong Tan int retry_cnt = 0; 1998f28368bbSHuazhong Tan int ret; 19996ff3cf07SHuazhong Tan 2000f28368bbSHuazhong Tan retry: 2001f28368bbSHuazhong Tan down(&hdev->reset_sem); 2002f28368bbSHuazhong Tan set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2003f28368bbSHuazhong Tan hdev->reset_type = HNAE3_FLR_RESET; 2004f28368bbSHuazhong Tan ret = hclgevf_reset_prepare(hdev); 2005f28368bbSHuazhong Tan if (ret) { 2006f28368bbSHuazhong Tan dev_err(&hdev->pdev->dev, "fail to prepare FLR, ret=%d\n", 2007f28368bbSHuazhong Tan ret); 2008f28368bbSHuazhong Tan if (hdev->reset_pending || 2009f28368bbSHuazhong Tan retry_cnt++ < HCLGEVF_FLR_RETRY_CNT) { 20106ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 2011f28368bbSHuazhong Tan "reset_pending:0x%lx, retry_cnt:%d\n", 2012f28368bbSHuazhong Tan hdev->reset_pending, retry_cnt); 2013f28368bbSHuazhong Tan clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2014f28368bbSHuazhong Tan up(&hdev->reset_sem); 2015f28368bbSHuazhong Tan msleep(HCLGEVF_FLR_RETRY_WAIT_MS); 2016f28368bbSHuazhong Tan goto retry; 2017f28368bbSHuazhong Tan } 2018f28368bbSHuazhong Tan } 2019f28368bbSHuazhong Tan 2020f28368bbSHuazhong Tan /* disable misc vector before FLR done */ 2021f28368bbSHuazhong Tan hclgevf_enable_vector(&hdev->misc_vector, false); 2022f28368bbSHuazhong Tan hdev->rst_stats.flr_rst_cnt++; 2023f28368bbSHuazhong Tan } 2024f28368bbSHuazhong Tan 2025f28368bbSHuazhong Tan static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 2026f28368bbSHuazhong Tan { 2027f28368bbSHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 2028f28368bbSHuazhong Tan int ret; 2029f28368bbSHuazhong Tan 2030f28368bbSHuazhong Tan hclgevf_enable_vector(&hdev->misc_vector, true); 2031f28368bbSHuazhong Tan 2032f28368bbSHuazhong Tan ret = hclgevf_reset_rebuild(hdev); 2033f28368bbSHuazhong Tan if (ret) 2034f28368bbSHuazhong Tan dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", 2035f28368bbSHuazhong Tan ret); 2036f28368bbSHuazhong Tan 2037f28368bbSHuazhong Tan hdev->reset_type = HNAE3_NONE_RESET; 2038f28368bbSHuazhong Tan clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2039f28368bbSHuazhong Tan up(&hdev->reset_sem); 20406ff3cf07SHuazhong Tan } 20416ff3cf07SHuazhong Tan 2042e2cb1decSSalil Mehta static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 2043e2cb1decSSalil Mehta { 2044e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2045e2cb1decSSalil Mehta 2046e2cb1decSSalil Mehta return hdev->fw_version; 2047e2cb1decSSalil Mehta } 2048e2cb1decSSalil Mehta 2049e2cb1decSSalil Mehta static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 2050e2cb1decSSalil Mehta { 2051e2cb1decSSalil Mehta struct hclgevf_misc_vector *vector = &hdev->misc_vector; 2052e2cb1decSSalil Mehta 2053e2cb1decSSalil Mehta vector->vector_irq = pci_irq_vector(hdev->pdev, 2054e2cb1decSSalil Mehta HCLGEVF_MISC_VECTOR_NUM); 2055e2cb1decSSalil Mehta vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 2056e2cb1decSSalil Mehta /* vector status always valid for Vector 0 */ 2057e2cb1decSSalil Mehta hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 2058e2cb1decSSalil Mehta hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 2059e2cb1decSSalil Mehta 2060e2cb1decSSalil Mehta hdev->num_msi_left -= 1; 2061e2cb1decSSalil Mehta hdev->num_msi_used += 1; 2062e2cb1decSSalil Mehta } 2063e2cb1decSSalil Mehta 206435a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 206535a1e503SSalil Mehta { 2066ff200099SYunsheng Lin if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2067ff200099SYunsheng Lin !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, 2068ff200099SYunsheng Lin &hdev->state)) 20690ea68902SYunsheng Lin mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 207035a1e503SSalil Mehta } 207135a1e503SSalil Mehta 207207a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 2073e2cb1decSSalil Mehta { 2074ff200099SYunsheng Lin if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2075ff200099SYunsheng Lin !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, 2076ff200099SYunsheng Lin &hdev->state)) 20770ea68902SYunsheng Lin mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 207807a0556aSSalil Mehta } 2079e2cb1decSSalil Mehta 2080ff200099SYunsheng Lin static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 2081ff200099SYunsheng Lin unsigned long delay) 2082e2cb1decSSalil Mehta { 2083d5432455SGuojia Liao if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2084d5432455SGuojia Liao !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 20850ea68902SYunsheng Lin mod_delayed_work(hclgevf_wq, &hdev->service_task, delay); 2086e2cb1decSSalil Mehta } 2087e2cb1decSSalil Mehta 2088ff200099SYunsheng Lin static void hclgevf_reset_service_task(struct hclgevf_dev *hdev) 208935a1e503SSalil Mehta { 2090d6ad7c53SGuojia Liao #define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3 2091d6ad7c53SGuojia Liao 2092ff200099SYunsheng Lin if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state)) 2093ff200099SYunsheng Lin return; 2094ff200099SYunsheng Lin 2095f28368bbSHuazhong Tan down(&hdev->reset_sem); 2096f28368bbSHuazhong Tan set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 209735a1e503SSalil Mehta 2098436667d2SSalil Mehta if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 2099436667d2SSalil Mehta &hdev->reset_state)) { 2100436667d2SSalil Mehta /* PF has initmated that it is about to reset the hardware. 21019b2f3477SWeihang Li * We now have to poll & check if hardware has actually 21029b2f3477SWeihang Li * completed the reset sequence. On hardware reset completion, 21039b2f3477SWeihang Li * VF needs to reset the client and ae device. 210435a1e503SSalil Mehta */ 2105436667d2SSalil Mehta hdev->reset_attempts = 0; 2106436667d2SSalil Mehta 2107dea846e8SHuazhong Tan hdev->last_reset_time = jiffies; 2108dea846e8SHuazhong Tan while ((hdev->reset_type = 2109dea846e8SHuazhong Tan hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 21101cc9bc6eSHuazhong Tan != HNAE3_NONE_RESET) 21111cc9bc6eSHuazhong Tan hclgevf_reset(hdev); 2112436667d2SSalil Mehta } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 2113436667d2SSalil Mehta &hdev->reset_state)) { 2114436667d2SSalil Mehta /* we could be here when either of below happens: 21159b2f3477SWeihang Li * 1. reset was initiated due to watchdog timeout caused by 2116436667d2SSalil Mehta * a. IMP was earlier reset and our TX got choked down and 2117436667d2SSalil Mehta * which resulted in watchdog reacting and inducing VF 2118436667d2SSalil Mehta * reset. This also means our cmdq would be unreliable. 2119436667d2SSalil Mehta * b. problem in TX due to other lower layer(example link 2120436667d2SSalil Mehta * layer not functioning properly etc.) 2121436667d2SSalil Mehta * 2. VF reset might have been initiated due to some config 2122436667d2SSalil Mehta * change. 2123436667d2SSalil Mehta * 2124436667d2SSalil Mehta * NOTE: Theres no clear way to detect above cases than to react 2125436667d2SSalil Mehta * to the response of PF for this reset request. PF will ack the 2126436667d2SSalil Mehta * 1b and 2. cases but we will not get any intimation about 1a 2127436667d2SSalil Mehta * from PF as cmdq would be in unreliable state i.e. mailbox 2128436667d2SSalil Mehta * communication between PF and VF would be broken. 212946ee7350SGuojia Liao * 213046ee7350SGuojia Liao * if we are never geting into pending state it means either: 2131436667d2SSalil Mehta * 1. PF is not receiving our request which could be due to IMP 2132436667d2SSalil Mehta * reset 2133436667d2SSalil Mehta * 2. PF is screwed 2134436667d2SSalil Mehta * We cannot do much for 2. but to check first we can try reset 2135436667d2SSalil Mehta * our PCIe + stack and see if it alleviates the problem. 2136436667d2SSalil Mehta */ 2137d6ad7c53SGuojia Liao if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) { 2138436667d2SSalil Mehta /* prepare for full reset of stack + pcie interface */ 2139dea846e8SHuazhong Tan set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 2140436667d2SSalil Mehta 2141436667d2SSalil Mehta /* "defer" schedule the reset task again */ 2142436667d2SSalil Mehta set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2143436667d2SSalil Mehta } else { 2144436667d2SSalil Mehta hdev->reset_attempts++; 2145436667d2SSalil Mehta 2146dea846e8SHuazhong Tan set_bit(hdev->reset_level, &hdev->reset_pending); 2147dea846e8SHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2148436667d2SSalil Mehta } 2149dea846e8SHuazhong Tan hclgevf_reset_task_schedule(hdev); 2150436667d2SSalil Mehta } 215135a1e503SSalil Mehta 2152afb6afdbSHuazhong Tan hdev->reset_type = HNAE3_NONE_RESET; 215335a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2154f28368bbSHuazhong Tan up(&hdev->reset_sem); 215535a1e503SSalil Mehta } 215635a1e503SSalil Mehta 2157ff200099SYunsheng Lin static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev) 2158e2cb1decSSalil Mehta { 2159ff200099SYunsheng Lin if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state)) 2160ff200099SYunsheng Lin return; 2161e2cb1decSSalil Mehta 2162e2cb1decSSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 2163e2cb1decSSalil Mehta return; 2164e2cb1decSSalil Mehta 216507a0556aSSalil Mehta hclgevf_mbx_async_handler(hdev); 2166e2cb1decSSalil Mehta 2167e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2168e2cb1decSSalil Mehta } 2169e2cb1decSSalil Mehta 2170ff200099SYunsheng Lin static void hclgevf_keep_alive(struct hclgevf_dev *hdev) 2171a6d818e3SYunsheng Lin { 2172d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 2173a6d818e3SYunsheng Lin int ret; 2174a6d818e3SYunsheng Lin 21751416d333SHuazhong Tan if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 2176c59a85c0SJian Shen return; 2177c59a85c0SJian Shen 2178d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_KEEP_ALIVE, 0); 2179d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2180a6d818e3SYunsheng Lin if (ret) 2181a6d818e3SYunsheng Lin dev_err(&hdev->pdev->dev, 2182a6d818e3SYunsheng Lin "VF sends keep alive cmd failed(=%d)\n", ret); 2183a6d818e3SYunsheng Lin } 2184a6d818e3SYunsheng Lin 2185ff200099SYunsheng Lin static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev) 2186e2cb1decSSalil Mehta { 2187ff200099SYunsheng Lin unsigned long delta = round_jiffies_relative(HZ); 2188ff200099SYunsheng Lin struct hnae3_handle *handle = &hdev->nic; 2189e2cb1decSSalil Mehta 2190e6394363SGuangbin Huang if (test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 2191e6394363SGuangbin Huang return; 2192e6394363SGuangbin Huang 2193ff200099SYunsheng Lin if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 2194ff200099SYunsheng Lin delta = jiffies - hdev->last_serv_processed; 2195db01afebSliuzhongzhu 2196ff200099SYunsheng Lin if (delta < round_jiffies_relative(HZ)) { 2197ff200099SYunsheng Lin delta = round_jiffies_relative(HZ) - delta; 2198ff200099SYunsheng Lin goto out; 2199db01afebSliuzhongzhu } 2200ff200099SYunsheng Lin } 2201ff200099SYunsheng Lin 2202ff200099SYunsheng Lin hdev->serv_processed_cnt++; 2203ff200099SYunsheng Lin if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL)) 2204ff200099SYunsheng Lin hclgevf_keep_alive(hdev); 2205ff200099SYunsheng Lin 2206ff200099SYunsheng Lin if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) { 2207ff200099SYunsheng Lin hdev->last_serv_processed = jiffies; 2208ff200099SYunsheng Lin goto out; 2209ff200099SYunsheng Lin } 2210ff200099SYunsheng Lin 2211ff200099SYunsheng Lin if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL)) 2212ff200099SYunsheng Lin hclgevf_tqps_update_stats(handle); 2213e2cb1decSSalil Mehta 2214e2cb1decSSalil Mehta /* request the link status from the PF. PF would be able to tell VF 2215e2cb1decSSalil Mehta * about such updates in future so we might remove this later 2216e2cb1decSSalil Mehta */ 2217e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 2218e2cb1decSSalil Mehta 22199194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 22209194d18bSliuzhongzhu 2221fe4144d4SJian Shen hclgevf_sync_vlan_filter(hdev); 2222fe4144d4SJian Shen 2223ee4bcd3bSJian Shen hclgevf_sync_mac_table(hdev); 2224ee4bcd3bSJian Shen 2225c631c696SJian Shen hclgevf_sync_promisc_mode(hdev); 2226c631c696SJian Shen 2227ff200099SYunsheng Lin hdev->last_serv_processed = jiffies; 2228436667d2SSalil Mehta 2229ff200099SYunsheng Lin out: 2230ff200099SYunsheng Lin hclgevf_task_schedule(hdev, delta); 2231ff200099SYunsheng Lin } 2232b3c3fe8eSYunsheng Lin 2233ff200099SYunsheng Lin static void hclgevf_service_task(struct work_struct *work) 2234ff200099SYunsheng Lin { 2235ff200099SYunsheng Lin struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev, 2236ff200099SYunsheng Lin service_task.work); 2237ff200099SYunsheng Lin 2238ff200099SYunsheng Lin hclgevf_reset_service_task(hdev); 2239ff200099SYunsheng Lin hclgevf_mailbox_service_task(hdev); 2240ff200099SYunsheng Lin hclgevf_periodic_service_task(hdev); 2241ff200099SYunsheng Lin 2242ff200099SYunsheng Lin /* Handle reset and mbx again in case periodical task delays the 2243ff200099SYunsheng Lin * handling by calling hclgevf_task_schedule() in 2244ff200099SYunsheng Lin * hclgevf_periodic_service_task() 2245ff200099SYunsheng Lin */ 2246ff200099SYunsheng Lin hclgevf_reset_service_task(hdev); 2247ff200099SYunsheng Lin hclgevf_mailbox_service_task(hdev); 2248e2cb1decSSalil Mehta } 2249e2cb1decSSalil Mehta 2250e2cb1decSSalil Mehta static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 2251e2cb1decSSalil Mehta { 2252e2cb1decSSalil Mehta hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 2253e2cb1decSSalil Mehta } 2254e2cb1decSSalil Mehta 2255b90fcc5bSHuazhong Tan static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 2256b90fcc5bSHuazhong Tan u32 *clearval) 2257e2cb1decSSalil Mehta { 225813050921SHuazhong Tan u32 val, cmdq_stat_reg, rst_ing_reg; 2259e2cb1decSSalil Mehta 2260e2cb1decSSalil Mehta /* fetch the events from their corresponding regs */ 226113050921SHuazhong Tan cmdq_stat_reg = hclgevf_read_dev(&hdev->hw, 22629cee2e8dSHuazhong Tan HCLGEVF_VECTOR0_CMDQ_STATE_REG); 2263e2cb1decSSalil Mehta 226413050921SHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 2265b90fcc5bSHuazhong Tan rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 2266b90fcc5bSHuazhong Tan dev_info(&hdev->pdev->dev, 2267b90fcc5bSHuazhong Tan "receive reset interrupt 0x%x!\n", rst_ing_reg); 2268b90fcc5bSHuazhong Tan set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 2269b90fcc5bSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2270ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 227113050921SHuazhong Tan *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B); 2272c88a6e7dSHuazhong Tan hdev->rst_stats.vf_rst_cnt++; 227372e2fb07SHuazhong Tan /* set up VF hardware reset status, its PF will clear 227472e2fb07SHuazhong Tan * this status when PF has initialized done. 227572e2fb07SHuazhong Tan */ 227672e2fb07SHuazhong Tan val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING); 227772e2fb07SHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING, 227872e2fb07SHuazhong Tan val | HCLGEVF_VF_RST_ING_BIT); 2279b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_RST; 2280b90fcc5bSHuazhong Tan } 2281b90fcc5bSHuazhong Tan 2282e2cb1decSSalil Mehta /* check for vector0 mailbox(=CMDQ RX) event source */ 228313050921SHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 228413050921SHuazhong Tan /* for revision 0x21, clearing interrupt is writing bit 0 228513050921SHuazhong Tan * to the clear register, writing bit 1 means to keep the 228613050921SHuazhong Tan * old value. 228713050921SHuazhong Tan * for revision 0x20, the clear register is a read & write 228813050921SHuazhong Tan * register, so we should just write 0 to the bit we are 228913050921SHuazhong Tan * handling, and keep other bits as cmdq_stat_reg. 229013050921SHuazhong Tan */ 229113050921SHuazhong Tan if (hdev->pdev->revision >= 0x21) 229213050921SHuazhong Tan *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 229313050921SHuazhong Tan else 229413050921SHuazhong Tan *clearval = cmdq_stat_reg & 229513050921SHuazhong Tan ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 229613050921SHuazhong Tan 2297b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_MBX; 2298e2cb1decSSalil Mehta } 2299e2cb1decSSalil Mehta 2300e45afb39SHuazhong Tan /* print other vector0 event source */ 2301e45afb39SHuazhong Tan dev_info(&hdev->pdev->dev, 2302e45afb39SHuazhong Tan "vector 0 interrupt from unknown source, cmdq_src = %#x\n", 2303e45afb39SHuazhong Tan cmdq_stat_reg); 2304e2cb1decSSalil Mehta 2305b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_OTHER; 2306e2cb1decSSalil Mehta } 2307e2cb1decSSalil Mehta 2308e2cb1decSSalil Mehta static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 2309e2cb1decSSalil Mehta { 2310b90fcc5bSHuazhong Tan enum hclgevf_evt_cause event_cause; 2311e2cb1decSSalil Mehta struct hclgevf_dev *hdev = data; 2312e2cb1decSSalil Mehta u32 clearval; 2313e2cb1decSSalil Mehta 2314e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 2315b90fcc5bSHuazhong Tan event_cause = hclgevf_check_evt_cause(hdev, &clearval); 2316e2cb1decSSalil Mehta 2317b90fcc5bSHuazhong Tan switch (event_cause) { 2318b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_RST: 2319b90fcc5bSHuazhong Tan hclgevf_reset_task_schedule(hdev); 2320b90fcc5bSHuazhong Tan break; 2321b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_MBX: 232207a0556aSSalil Mehta hclgevf_mbx_handler(hdev); 2323b90fcc5bSHuazhong Tan break; 2324b90fcc5bSHuazhong Tan default: 2325b90fcc5bSHuazhong Tan break; 2326b90fcc5bSHuazhong Tan } 2327e2cb1decSSalil Mehta 2328b90fcc5bSHuazhong Tan if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 2329e2cb1decSSalil Mehta hclgevf_clear_event_cause(hdev, clearval); 2330e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2331b90fcc5bSHuazhong Tan } 2332e2cb1decSSalil Mehta 2333e2cb1decSSalil Mehta return IRQ_HANDLED; 2334e2cb1decSSalil Mehta } 2335e2cb1decSSalil Mehta 2336e2cb1decSSalil Mehta static int hclgevf_configure(struct hclgevf_dev *hdev) 2337e2cb1decSSalil Mehta { 2338e2cb1decSSalil Mehta int ret; 2339e2cb1decSSalil Mehta 234092f11ea1SJian Shen /* get current port based vlan state from PF */ 234192f11ea1SJian Shen ret = hclgevf_get_port_base_vlan_filter_state(hdev); 234292f11ea1SJian Shen if (ret) 234392f11ea1SJian Shen return ret; 234492f11ea1SJian Shen 2345e2cb1decSSalil Mehta /* get queue configuration from PF */ 23466cee6fc3SJian Shen ret = hclgevf_get_queue_info(hdev); 2347e2cb1decSSalil Mehta if (ret) 2348e2cb1decSSalil Mehta return ret; 2349c0425944SPeng Li 2350c0425944SPeng Li /* get queue depth info from PF */ 2351c0425944SPeng Li ret = hclgevf_get_queue_depth(hdev); 2352c0425944SPeng Li if (ret) 2353c0425944SPeng Li return ret; 2354c0425944SPeng Li 23559c3e7130Sliuzhongzhu ret = hclgevf_get_pf_media_type(hdev); 23569c3e7130Sliuzhongzhu if (ret) 23579c3e7130Sliuzhongzhu return ret; 23589c3e7130Sliuzhongzhu 2359e2cb1decSSalil Mehta /* get tc configuration from PF */ 2360e2cb1decSSalil Mehta return hclgevf_get_tc_info(hdev); 2361e2cb1decSSalil Mehta } 2362e2cb1decSSalil Mehta 23637a01c897SSalil Mehta static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 23647a01c897SSalil Mehta { 23657a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 23661154bb26SPeng Li struct hclgevf_dev *hdev; 23677a01c897SSalil Mehta 23687a01c897SSalil Mehta hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 23697a01c897SSalil Mehta if (!hdev) 23707a01c897SSalil Mehta return -ENOMEM; 23717a01c897SSalil Mehta 23727a01c897SSalil Mehta hdev->pdev = pdev; 23737a01c897SSalil Mehta hdev->ae_dev = ae_dev; 23747a01c897SSalil Mehta ae_dev->priv = hdev; 23757a01c897SSalil Mehta 23767a01c897SSalil Mehta return 0; 23777a01c897SSalil Mehta } 23787a01c897SSalil Mehta 2379e2cb1decSSalil Mehta static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 2380e2cb1decSSalil Mehta { 2381e2cb1decSSalil Mehta struct hnae3_handle *roce = &hdev->roce; 2382e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 2383e2cb1decSSalil Mehta 238407acf909SJian Shen roce->rinfo.num_vectors = hdev->num_roce_msix; 2385e2cb1decSSalil Mehta 2386e2cb1decSSalil Mehta if (hdev->num_msi_left < roce->rinfo.num_vectors || 2387e2cb1decSSalil Mehta hdev->num_msi_left == 0) 2388e2cb1decSSalil Mehta return -EINVAL; 2389e2cb1decSSalil Mehta 239007acf909SJian Shen roce->rinfo.base_vector = hdev->roce_base_vector; 2391e2cb1decSSalil Mehta 2392e2cb1decSSalil Mehta roce->rinfo.netdev = nic->kinfo.netdev; 2393e2cb1decSSalil Mehta roce->rinfo.roce_io_base = hdev->hw.io_base; 2394e2cb1decSSalil Mehta 2395e2cb1decSSalil Mehta roce->pdev = nic->pdev; 2396e2cb1decSSalil Mehta roce->ae_algo = nic->ae_algo; 2397e2cb1decSSalil Mehta roce->numa_node_mask = nic->numa_node_mask; 2398e2cb1decSSalil Mehta 2399e2cb1decSSalil Mehta return 0; 2400e2cb1decSSalil Mehta } 2401e2cb1decSSalil Mehta 2402b26a6feaSPeng Li static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 2403b26a6feaSPeng Li { 2404b26a6feaSPeng Li struct hclgevf_cfg_gro_status_cmd *req; 2405b26a6feaSPeng Li struct hclgevf_desc desc; 2406b26a6feaSPeng Li int ret; 2407b26a6feaSPeng Li 2408b26a6feaSPeng Li if (!hnae3_dev_gro_supported(hdev)) 2409b26a6feaSPeng Li return 0; 2410b26a6feaSPeng Li 2411b26a6feaSPeng Li hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 2412b26a6feaSPeng Li false); 2413b26a6feaSPeng Li req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2414b26a6feaSPeng Li 2415fb9e44d6SHuazhong Tan req->gro_en = en ? 1 : 0; 2416b26a6feaSPeng Li 2417b26a6feaSPeng Li ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2418b26a6feaSPeng Li if (ret) 2419b26a6feaSPeng Li dev_err(&hdev->pdev->dev, 2420b26a6feaSPeng Li "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2421b26a6feaSPeng Li 2422b26a6feaSPeng Li return ret; 2423b26a6feaSPeng Li } 2424b26a6feaSPeng Li 2425944de484SGuojia Liao static void hclgevf_rss_init_cfg(struct hclgevf_dev *hdev) 2426e2cb1decSSalil Mehta { 2427e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2428944de484SGuojia Liao struct hclgevf_rss_tuple_cfg *tuple_sets; 24294093d1a2SGuangbin Huang u32 i; 2430e2cb1decSSalil Mehta 2431944de484SGuojia Liao rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 24324093d1a2SGuangbin Huang rss_cfg->rss_size = hdev->nic.kinfo.rss_size; 2433944de484SGuojia Liao tuple_sets = &rss_cfg->rss_tuple_sets; 2434374ad291SJian Shen if (hdev->pdev->revision >= 0x21) { 2435472d7eceSJian Shen rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 2436472d7eceSJian Shen memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 2437374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 2438374ad291SJian Shen 2439944de484SGuojia Liao tuple_sets->ipv4_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2440944de484SGuojia Liao tuple_sets->ipv4_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2441944de484SGuojia Liao tuple_sets->ipv4_sctp_en = HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2442944de484SGuojia Liao tuple_sets->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2443944de484SGuojia Liao tuple_sets->ipv6_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2444944de484SGuojia Liao tuple_sets->ipv6_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2445944de484SGuojia Liao tuple_sets->ipv6_sctp_en = HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2446944de484SGuojia Liao tuple_sets->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2447374ad291SJian Shen } 2448374ad291SJian Shen 24499b2f3477SWeihang Li /* Initialize RSS indirect table */ 2450e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 24514093d1a2SGuangbin Huang rss_cfg->rss_indirection_tbl[i] = i % rss_cfg->rss_size; 2452944de484SGuojia Liao } 2453944de484SGuojia Liao 2454944de484SGuojia Liao static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2455944de484SGuojia Liao { 2456944de484SGuojia Liao struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2457944de484SGuojia Liao int ret; 2458944de484SGuojia Liao 2459944de484SGuojia Liao if (hdev->pdev->revision >= 0x21) { 2460944de484SGuojia Liao ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 2461944de484SGuojia Liao rss_cfg->rss_hash_key); 2462944de484SGuojia Liao if (ret) 2463944de484SGuojia Liao return ret; 2464944de484SGuojia Liao 2465944de484SGuojia Liao ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 2466944de484SGuojia Liao if (ret) 2467944de484SGuojia Liao return ret; 2468944de484SGuojia Liao } 2469e2cb1decSSalil Mehta 2470e2cb1decSSalil Mehta ret = hclgevf_set_rss_indir_table(hdev); 2471e2cb1decSSalil Mehta if (ret) 2472e2cb1decSSalil Mehta return ret; 2473e2cb1decSSalil Mehta 24744093d1a2SGuangbin Huang return hclgevf_set_rss_tc_mode(hdev, rss_cfg->rss_size); 2475e2cb1decSSalil Mehta } 2476e2cb1decSSalil Mehta 2477e2cb1decSSalil Mehta static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2478e2cb1decSSalil Mehta { 2479e2cb1decSSalil Mehta return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2480e2cb1decSSalil Mehta false); 2481e2cb1decSSalil Mehta } 2482e2cb1decSSalil Mehta 2483ff200099SYunsheng Lin static void hclgevf_flush_link_update(struct hclgevf_dev *hdev) 2484ff200099SYunsheng Lin { 2485ff200099SYunsheng Lin #define HCLGEVF_FLUSH_LINK_TIMEOUT 100000 2486ff200099SYunsheng Lin 2487ff200099SYunsheng Lin unsigned long last = hdev->serv_processed_cnt; 2488ff200099SYunsheng Lin int i = 0; 2489ff200099SYunsheng Lin 2490ff200099SYunsheng Lin while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) && 2491ff200099SYunsheng Lin i++ < HCLGEVF_FLUSH_LINK_TIMEOUT && 2492ff200099SYunsheng Lin last == hdev->serv_processed_cnt) 2493ff200099SYunsheng Lin usleep_range(1, 1); 2494ff200099SYunsheng Lin } 2495ff200099SYunsheng Lin 24968cdb992fSJian Shen static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 24978cdb992fSJian Shen { 24988cdb992fSJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 24998cdb992fSJian Shen 25008cdb992fSJian Shen if (enable) { 2501ff200099SYunsheng Lin hclgevf_task_schedule(hdev, 0); 25028cdb992fSJian Shen } else { 2503b3c3fe8eSYunsheng Lin set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2504ff200099SYunsheng Lin 2505ff200099SYunsheng Lin /* flush memory to make sure DOWN is seen by service task */ 2506ff200099SYunsheng Lin smp_mb__before_atomic(); 2507ff200099SYunsheng Lin hclgevf_flush_link_update(hdev); 25088cdb992fSJian Shen } 25098cdb992fSJian Shen } 25108cdb992fSJian Shen 2511e2cb1decSSalil Mehta static int hclgevf_ae_start(struct hnae3_handle *handle) 2512e2cb1decSSalil Mehta { 2513e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2514e2cb1decSSalil Mehta 2515e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 2516e2cb1decSSalil Mehta 2517e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 2518e2cb1decSSalil Mehta 25199194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 25209194d18bSliuzhongzhu 2521e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2522e2cb1decSSalil Mehta 2523e2cb1decSSalil Mehta return 0; 2524e2cb1decSSalil Mehta } 2525e2cb1decSSalil Mehta 2526e2cb1decSSalil Mehta static void hclgevf_ae_stop(struct hnae3_handle *handle) 2527e2cb1decSSalil Mehta { 2528e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 252939cfbc9cSHuazhong Tan int i; 2530e2cb1decSSalil Mehta 25312f7e4896SFuyun Liang set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 25322f7e4896SFuyun Liang 2533146e92c1SHuazhong Tan if (hdev->reset_type != HNAE3_VF_RESET) 253439cfbc9cSHuazhong Tan for (i = 0; i < handle->kinfo.num_tqps; i++) 2535146e92c1SHuazhong Tan if (hclgevf_reset_tqp(handle, i)) 2536146e92c1SHuazhong Tan break; 253739cfbc9cSHuazhong Tan 2538e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 25398cc6c1f7SFuyun Liang hclgevf_update_link_status(hdev, 0); 2540e2cb1decSSalil Mehta } 2541e2cb1decSSalil Mehta 2542a6d818e3SYunsheng Lin static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2543a6d818e3SYunsheng Lin { 2544d3410018SYufeng Mo #define HCLGEVF_STATE_ALIVE 1 2545d3410018SYufeng Mo #define HCLGEVF_STATE_NOT_ALIVE 0 2546a6d818e3SYunsheng Lin 2547d3410018SYufeng Mo struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2548d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 2549d3410018SYufeng Mo 2550d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_ALIVE, 0); 2551d3410018SYufeng Mo send_msg.data[0] = alive ? HCLGEVF_STATE_ALIVE : 2552d3410018SYufeng Mo HCLGEVF_STATE_NOT_ALIVE; 2553d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2554a6d818e3SYunsheng Lin } 2555a6d818e3SYunsheng Lin 2556a6d818e3SYunsheng Lin static int hclgevf_client_start(struct hnae3_handle *handle) 2557a6d818e3SYunsheng Lin { 2558f621df96SQinglang Miao return hclgevf_set_alive(handle, true); 2559a6d818e3SYunsheng Lin } 2560a6d818e3SYunsheng Lin 2561a6d818e3SYunsheng Lin static void hclgevf_client_stop(struct hnae3_handle *handle) 2562a6d818e3SYunsheng Lin { 2563a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2564a6d818e3SYunsheng Lin int ret; 2565a6d818e3SYunsheng Lin 2566a6d818e3SYunsheng Lin ret = hclgevf_set_alive(handle, false); 2567a6d818e3SYunsheng Lin if (ret) 2568a6d818e3SYunsheng Lin dev_warn(&hdev->pdev->dev, 2569a6d818e3SYunsheng Lin "%s failed %d\n", __func__, ret); 2570a6d818e3SYunsheng Lin } 2571a6d818e3SYunsheng Lin 2572e2cb1decSSalil Mehta static void hclgevf_state_init(struct hclgevf_dev *hdev) 2573e2cb1decSSalil Mehta { 2574e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2575e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2576d5432455SGuojia Liao clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 2577e2cb1decSSalil Mehta 2578b3c3fe8eSYunsheng Lin INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task); 257935a1e503SSalil Mehta 2580e2cb1decSSalil Mehta mutex_init(&hdev->mbx_resp.mbx_mutex); 2581f28368bbSHuazhong Tan sema_init(&hdev->reset_sem, 1); 2582e2cb1decSSalil Mehta 2583ee4bcd3bSJian Shen spin_lock_init(&hdev->mac_table.mac_list_lock); 2584ee4bcd3bSJian Shen INIT_LIST_HEAD(&hdev->mac_table.uc_mac_list); 2585ee4bcd3bSJian Shen INIT_LIST_HEAD(&hdev->mac_table.mc_mac_list); 2586ee4bcd3bSJian Shen 2587e2cb1decSSalil Mehta /* bring the device down */ 2588e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2589e2cb1decSSalil Mehta } 2590e2cb1decSSalil Mehta 2591e2cb1decSSalil Mehta static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2592e2cb1decSSalil Mehta { 2593e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2594acfc3d55SHuazhong Tan set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2595e2cb1decSSalil Mehta 2596b3c3fe8eSYunsheng Lin if (hdev->service_task.work.func) 2597b3c3fe8eSYunsheng Lin cancel_delayed_work_sync(&hdev->service_task); 2598e2cb1decSSalil Mehta 2599e2cb1decSSalil Mehta mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2600e2cb1decSSalil Mehta } 2601e2cb1decSSalil Mehta 2602e2cb1decSSalil Mehta static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2603e2cb1decSSalil Mehta { 2604e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2605e2cb1decSSalil Mehta int vectors; 2606e2cb1decSSalil Mehta int i; 2607e2cb1decSSalil Mehta 2608580a05f9SYonglong Liu if (hnae3_dev_roce_supported(hdev)) 260907acf909SJian Shen vectors = pci_alloc_irq_vectors(pdev, 261007acf909SJian Shen hdev->roce_base_msix_offset + 1, 261107acf909SJian Shen hdev->num_msi, 261207acf909SJian Shen PCI_IRQ_MSIX); 261307acf909SJian Shen else 2614580a05f9SYonglong Liu vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2615580a05f9SYonglong Liu hdev->num_msi, 2616e2cb1decSSalil Mehta PCI_IRQ_MSI | PCI_IRQ_MSIX); 261707acf909SJian Shen 2618e2cb1decSSalil Mehta if (vectors < 0) { 2619e2cb1decSSalil Mehta dev_err(&pdev->dev, 2620e2cb1decSSalil Mehta "failed(%d) to allocate MSI/MSI-X vectors\n", 2621e2cb1decSSalil Mehta vectors); 2622e2cb1decSSalil Mehta return vectors; 2623e2cb1decSSalil Mehta } 2624e2cb1decSSalil Mehta if (vectors < hdev->num_msi) 2625e2cb1decSSalil Mehta dev_warn(&hdev->pdev->dev, 2626adcf738bSGuojia Liao "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2627e2cb1decSSalil Mehta hdev->num_msi, vectors); 2628e2cb1decSSalil Mehta 2629e2cb1decSSalil Mehta hdev->num_msi = vectors; 2630e2cb1decSSalil Mehta hdev->num_msi_left = vectors; 2631580a05f9SYonglong Liu 2632e2cb1decSSalil Mehta hdev->base_msi_vector = pdev->irq; 263307acf909SJian Shen hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2634e2cb1decSSalil Mehta 2635e2cb1decSSalil Mehta hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2636e2cb1decSSalil Mehta sizeof(u16), GFP_KERNEL); 2637e2cb1decSSalil Mehta if (!hdev->vector_status) { 2638e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2639e2cb1decSSalil Mehta return -ENOMEM; 2640e2cb1decSSalil Mehta } 2641e2cb1decSSalil Mehta 2642e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 2643e2cb1decSSalil Mehta hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2644e2cb1decSSalil Mehta 2645e2cb1decSSalil Mehta hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2646e2cb1decSSalil Mehta sizeof(int), GFP_KERNEL); 2647e2cb1decSSalil Mehta if (!hdev->vector_irq) { 2648862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2649e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2650e2cb1decSSalil Mehta return -ENOMEM; 2651e2cb1decSSalil Mehta } 2652e2cb1decSSalil Mehta 2653e2cb1decSSalil Mehta return 0; 2654e2cb1decSSalil Mehta } 2655e2cb1decSSalil Mehta 2656e2cb1decSSalil Mehta static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2657e2cb1decSSalil Mehta { 2658e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2659e2cb1decSSalil Mehta 2660862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2661862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_irq); 2662e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2663e2cb1decSSalil Mehta } 2664e2cb1decSSalil Mehta 2665e2cb1decSSalil Mehta static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2666e2cb1decSSalil Mehta { 2667cdd332acSGuojia Liao int ret; 2668e2cb1decSSalil Mehta 2669e2cb1decSSalil Mehta hclgevf_get_misc_vector(hdev); 2670e2cb1decSSalil Mehta 2671f97c4d82SYonglong Liu snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 2672f97c4d82SYonglong Liu HCLGEVF_NAME, pci_name(hdev->pdev)); 2673e2cb1decSSalil Mehta ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2674f97c4d82SYonglong Liu 0, hdev->misc_vector.name, hdev); 2675e2cb1decSSalil Mehta if (ret) { 2676e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2677e2cb1decSSalil Mehta hdev->misc_vector.vector_irq); 2678e2cb1decSSalil Mehta return ret; 2679e2cb1decSSalil Mehta } 2680e2cb1decSSalil Mehta 26811819e409SXi Wang hclgevf_clear_event_cause(hdev, 0); 26821819e409SXi Wang 2683e2cb1decSSalil Mehta /* enable misc. vector(vector 0) */ 2684e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2685e2cb1decSSalil Mehta 2686e2cb1decSSalil Mehta return ret; 2687e2cb1decSSalil Mehta } 2688e2cb1decSSalil Mehta 2689e2cb1decSSalil Mehta static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2690e2cb1decSSalil Mehta { 2691e2cb1decSSalil Mehta /* disable misc vector(vector 0) */ 2692e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 26931819e409SXi Wang synchronize_irq(hdev->misc_vector.vector_irq); 2694e2cb1decSSalil Mehta free_irq(hdev->misc_vector.vector_irq, hdev); 2695e2cb1decSSalil Mehta hclgevf_free_vector(hdev, 0); 2696e2cb1decSSalil Mehta } 2697e2cb1decSSalil Mehta 2698bb87be87SYonglong Liu static void hclgevf_info_show(struct hclgevf_dev *hdev) 2699bb87be87SYonglong Liu { 2700bb87be87SYonglong Liu struct device *dev = &hdev->pdev->dev; 2701bb87be87SYonglong Liu 2702bb87be87SYonglong Liu dev_info(dev, "VF info begin:\n"); 2703bb87be87SYonglong Liu 2704adcf738bSGuojia Liao dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 2705adcf738bSGuojia Liao dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 2706adcf738bSGuojia Liao dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 2707adcf738bSGuojia Liao dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 2708adcf738bSGuojia Liao dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 2709adcf738bSGuojia Liao dev_info(dev, "PF media type of this VF: %u\n", 2710bb87be87SYonglong Liu hdev->hw.mac.media_type); 2711bb87be87SYonglong Liu 2712bb87be87SYonglong Liu dev_info(dev, "VF info end.\n"); 2713bb87be87SYonglong Liu } 2714bb87be87SYonglong Liu 27151db58f86SHuazhong Tan static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 27161db58f86SHuazhong Tan struct hnae3_client *client) 27171db58f86SHuazhong Tan { 27181db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 27194cd5beaaSGuangbin Huang int rst_cnt = hdev->rst_stats.rst_cnt; 27201db58f86SHuazhong Tan int ret; 27211db58f86SHuazhong Tan 27221db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->nic); 27231db58f86SHuazhong Tan if (ret) 27241db58f86SHuazhong Tan return ret; 27251db58f86SHuazhong Tan 27261db58f86SHuazhong Tan set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 27274cd5beaaSGuangbin Huang if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 27284cd5beaaSGuangbin Huang rst_cnt != hdev->rst_stats.rst_cnt) { 27294cd5beaaSGuangbin Huang clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 27304cd5beaaSGuangbin Huang 27314cd5beaaSGuangbin Huang client->ops->uninit_instance(&hdev->nic, 0); 27324cd5beaaSGuangbin Huang return -EBUSY; 27334cd5beaaSGuangbin Huang } 27344cd5beaaSGuangbin Huang 27351db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 27361db58f86SHuazhong Tan 27371db58f86SHuazhong Tan if (netif_msg_drv(&hdev->nic)) 27381db58f86SHuazhong Tan hclgevf_info_show(hdev); 27391db58f86SHuazhong Tan 27401db58f86SHuazhong Tan return 0; 27411db58f86SHuazhong Tan } 27421db58f86SHuazhong Tan 27431db58f86SHuazhong Tan static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 27441db58f86SHuazhong Tan struct hnae3_client *client) 27451db58f86SHuazhong Tan { 27461db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 27471db58f86SHuazhong Tan int ret; 27481db58f86SHuazhong Tan 27491db58f86SHuazhong Tan if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 27501db58f86SHuazhong Tan !hdev->nic_client) 27511db58f86SHuazhong Tan return 0; 27521db58f86SHuazhong Tan 27531db58f86SHuazhong Tan ret = hclgevf_init_roce_base_info(hdev); 27541db58f86SHuazhong Tan if (ret) 27551db58f86SHuazhong Tan return ret; 27561db58f86SHuazhong Tan 27571db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->roce); 27581db58f86SHuazhong Tan if (ret) 27591db58f86SHuazhong Tan return ret; 27601db58f86SHuazhong Tan 27611db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 27621db58f86SHuazhong Tan 27631db58f86SHuazhong Tan return 0; 27641db58f86SHuazhong Tan } 27651db58f86SHuazhong Tan 2766e718a93fSPeng Li static int hclgevf_init_client_instance(struct hnae3_client *client, 2767e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2768e2cb1decSSalil Mehta { 2769e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2770e2cb1decSSalil Mehta int ret; 2771e2cb1decSSalil Mehta 2772e2cb1decSSalil Mehta switch (client->type) { 2773e2cb1decSSalil Mehta case HNAE3_CLIENT_KNIC: 2774e2cb1decSSalil Mehta hdev->nic_client = client; 2775e2cb1decSSalil Mehta hdev->nic.client = client; 2776e2cb1decSSalil Mehta 27771db58f86SHuazhong Tan ret = hclgevf_init_nic_client_instance(ae_dev, client); 2778e2cb1decSSalil Mehta if (ret) 277949dd8054SJian Shen goto clear_nic; 2780e2cb1decSSalil Mehta 27811db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, 27821db58f86SHuazhong Tan hdev->roce_client); 2783e2cb1decSSalil Mehta if (ret) 278449dd8054SJian Shen goto clear_roce; 2785d9f28fc2SJian Shen 2786e2cb1decSSalil Mehta break; 2787e2cb1decSSalil Mehta case HNAE3_CLIENT_ROCE: 2788544a7bcdSLijun Ou if (hnae3_dev_roce_supported(hdev)) { 2789e2cb1decSSalil Mehta hdev->roce_client = client; 2790e2cb1decSSalil Mehta hdev->roce.client = client; 2791544a7bcdSLijun Ou } 2792e2cb1decSSalil Mehta 27931db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, client); 2794e2cb1decSSalil Mehta if (ret) 279549dd8054SJian Shen goto clear_roce; 2796e2cb1decSSalil Mehta 2797fa7a4bd5SJian Shen break; 2798fa7a4bd5SJian Shen default: 2799fa7a4bd5SJian Shen return -EINVAL; 2800e2cb1decSSalil Mehta } 2801e2cb1decSSalil Mehta 2802e2cb1decSSalil Mehta return 0; 280349dd8054SJian Shen 280449dd8054SJian Shen clear_nic: 280549dd8054SJian Shen hdev->nic_client = NULL; 280649dd8054SJian Shen hdev->nic.client = NULL; 280749dd8054SJian Shen return ret; 280849dd8054SJian Shen clear_roce: 280949dd8054SJian Shen hdev->roce_client = NULL; 281049dd8054SJian Shen hdev->roce.client = NULL; 281149dd8054SJian Shen return ret; 2812e2cb1decSSalil Mehta } 2813e2cb1decSSalil Mehta 2814e718a93fSPeng Li static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2815e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2816e2cb1decSSalil Mehta { 2817e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2818e718a93fSPeng Li 2819e2cb1decSSalil Mehta /* un-init roce, if it exists */ 282049dd8054SJian Shen if (hdev->roce_client) { 2821e2cb1decSSalil Mehta hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 282249dd8054SJian Shen hdev->roce_client = NULL; 282349dd8054SJian Shen hdev->roce.client = NULL; 282449dd8054SJian Shen } 2825e2cb1decSSalil Mehta 2826e2cb1decSSalil Mehta /* un-init nic/unic, if this was not called by roce client */ 282749dd8054SJian Shen if (client->ops->uninit_instance && hdev->nic_client && 282849dd8054SJian Shen client->type != HNAE3_CLIENT_ROCE) { 282925d1817cSHuazhong Tan clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 283025d1817cSHuazhong Tan 2831e2cb1decSSalil Mehta client->ops->uninit_instance(&hdev->nic, 0); 283249dd8054SJian Shen hdev->nic_client = NULL; 283349dd8054SJian Shen hdev->nic.client = NULL; 283449dd8054SJian Shen } 2835e2cb1decSSalil Mehta } 2836e2cb1decSSalil Mehta 2837e2cb1decSSalil Mehta static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2838e2cb1decSSalil Mehta { 2839e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2840e2cb1decSSalil Mehta struct hclgevf_hw *hw; 2841e2cb1decSSalil Mehta int ret; 2842e2cb1decSSalil Mehta 2843e2cb1decSSalil Mehta ret = pci_enable_device(pdev); 2844e2cb1decSSalil Mehta if (ret) { 2845e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed to enable PCI device\n"); 28463e249d3bSFuyun Liang return ret; 2847e2cb1decSSalil Mehta } 2848e2cb1decSSalil Mehta 2849e2cb1decSSalil Mehta ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2850e2cb1decSSalil Mehta if (ret) { 2851e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2852e2cb1decSSalil Mehta goto err_disable_device; 2853e2cb1decSSalil Mehta } 2854e2cb1decSSalil Mehta 2855e2cb1decSSalil Mehta ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2856e2cb1decSSalil Mehta if (ret) { 2857e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2858e2cb1decSSalil Mehta goto err_disable_device; 2859e2cb1decSSalil Mehta } 2860e2cb1decSSalil Mehta 2861e2cb1decSSalil Mehta pci_set_master(pdev); 2862e2cb1decSSalil Mehta hw = &hdev->hw; 2863e2cb1decSSalil Mehta hw->hdev = hdev; 28642e1ea493SPeng Li hw->io_base = pci_iomap(pdev, 2, 0); 2865e2cb1decSSalil Mehta if (!hw->io_base) { 2866e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't map configuration register space\n"); 2867e2cb1decSSalil Mehta ret = -ENOMEM; 2868e2cb1decSSalil Mehta goto err_clr_master; 2869e2cb1decSSalil Mehta } 2870e2cb1decSSalil Mehta 2871e2cb1decSSalil Mehta return 0; 2872e2cb1decSSalil Mehta 2873e2cb1decSSalil Mehta err_clr_master: 2874e2cb1decSSalil Mehta pci_clear_master(pdev); 2875e2cb1decSSalil Mehta pci_release_regions(pdev); 2876e2cb1decSSalil Mehta err_disable_device: 2877e2cb1decSSalil Mehta pci_disable_device(pdev); 28783e249d3bSFuyun Liang 2879e2cb1decSSalil Mehta return ret; 2880e2cb1decSSalil Mehta } 2881e2cb1decSSalil Mehta 2882e2cb1decSSalil Mehta static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2883e2cb1decSSalil Mehta { 2884e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2885e2cb1decSSalil Mehta 2886e2cb1decSSalil Mehta pci_iounmap(pdev, hdev->hw.io_base); 2887e2cb1decSSalil Mehta pci_clear_master(pdev); 2888e2cb1decSSalil Mehta pci_release_regions(pdev); 2889e2cb1decSSalil Mehta pci_disable_device(pdev); 2890e2cb1decSSalil Mehta } 2891e2cb1decSSalil Mehta 289207acf909SJian Shen static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 289307acf909SJian Shen { 289407acf909SJian Shen struct hclgevf_query_res_cmd *req; 289507acf909SJian Shen struct hclgevf_desc desc; 289607acf909SJian Shen int ret; 289707acf909SJian Shen 289807acf909SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 289907acf909SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 290007acf909SJian Shen if (ret) { 290107acf909SJian Shen dev_err(&hdev->pdev->dev, 290207acf909SJian Shen "query vf resource failed, ret = %d.\n", ret); 290307acf909SJian Shen return ret; 290407acf909SJian Shen } 290507acf909SJian Shen 290607acf909SJian Shen req = (struct hclgevf_query_res_cmd *)desc.data; 290707acf909SJian Shen 2908580a05f9SYonglong Liu if (hnae3_dev_roce_supported(hdev)) { 290907acf909SJian Shen hdev->roce_base_msix_offset = 291060df7e91SHuazhong Tan hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee), 291107acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_M, 291207acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_S); 291307acf909SJian Shen hdev->num_roce_msix = 291460df7e91SHuazhong Tan hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 291507acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 291607acf909SJian Shen 2917580a05f9SYonglong Liu /* nic's msix numbers is always equals to the roce's. */ 2918580a05f9SYonglong Liu hdev->num_nic_msix = hdev->num_roce_msix; 2919580a05f9SYonglong Liu 292007acf909SJian Shen /* VF should have NIC vectors and Roce vectors, NIC vectors 292107acf909SJian Shen * are queued before Roce vectors. The offset is fixed to 64. 292207acf909SJian Shen */ 292307acf909SJian Shen hdev->num_msi = hdev->num_roce_msix + 292407acf909SJian Shen hdev->roce_base_msix_offset; 292507acf909SJian Shen } else { 292607acf909SJian Shen hdev->num_msi = 292760df7e91SHuazhong Tan hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 292807acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2929580a05f9SYonglong Liu 2930580a05f9SYonglong Liu hdev->num_nic_msix = hdev->num_msi; 2931580a05f9SYonglong Liu } 2932580a05f9SYonglong Liu 2933580a05f9SYonglong Liu if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) { 2934580a05f9SYonglong Liu dev_err(&hdev->pdev->dev, 2935580a05f9SYonglong Liu "Just %u msi resources, not enough for vf(min:2).\n", 2936580a05f9SYonglong Liu hdev->num_nic_msix); 2937580a05f9SYonglong Liu return -EINVAL; 293807acf909SJian Shen } 293907acf909SJian Shen 294007acf909SJian Shen return 0; 294107acf909SJian Shen } 294207acf909SJian Shen 2943862d969aSHuazhong Tan static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2944862d969aSHuazhong Tan { 2945862d969aSHuazhong Tan struct pci_dev *pdev = hdev->pdev; 2946862d969aSHuazhong Tan int ret = 0; 2947862d969aSHuazhong Tan 2948862d969aSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2949862d969aSHuazhong Tan test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2950862d969aSHuazhong Tan hclgevf_misc_irq_uninit(hdev); 2951862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2952862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2953862d969aSHuazhong Tan } 2954862d969aSHuazhong Tan 2955862d969aSHuazhong Tan if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2956862d969aSHuazhong Tan pci_set_master(pdev); 2957862d969aSHuazhong Tan ret = hclgevf_init_msi(hdev); 2958862d969aSHuazhong Tan if (ret) { 2959862d969aSHuazhong Tan dev_err(&pdev->dev, 2960862d969aSHuazhong Tan "failed(%d) to init MSI/MSI-X\n", ret); 2961862d969aSHuazhong Tan return ret; 2962862d969aSHuazhong Tan } 2963862d969aSHuazhong Tan 2964862d969aSHuazhong Tan ret = hclgevf_misc_irq_init(hdev); 2965862d969aSHuazhong Tan if (ret) { 2966862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2967862d969aSHuazhong Tan dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2968862d969aSHuazhong Tan ret); 2969862d969aSHuazhong Tan return ret; 2970862d969aSHuazhong Tan } 2971862d969aSHuazhong Tan 2972862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2973862d969aSHuazhong Tan } 2974862d969aSHuazhong Tan 2975862d969aSHuazhong Tan return ret; 2976862d969aSHuazhong Tan } 2977862d969aSHuazhong Tan 2978039ba863SJian Shen static int hclgevf_clear_vport_list(struct hclgevf_dev *hdev) 2979039ba863SJian Shen { 2980039ba863SJian Shen struct hclge_vf_to_pf_msg send_msg; 2981039ba863SJian Shen 2982039ba863SJian Shen hclgevf_build_send_msg(&send_msg, HCLGE_MBX_HANDLE_VF_TBL, 2983039ba863SJian Shen HCLGE_MBX_VPORT_LIST_CLEAR); 2984039ba863SJian Shen return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2985039ba863SJian Shen } 2986039ba863SJian Shen 29879c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2988e2cb1decSSalil Mehta { 29897a01c897SSalil Mehta struct pci_dev *pdev = hdev->pdev; 2990e2cb1decSSalil Mehta int ret; 2991e2cb1decSSalil Mehta 2992862d969aSHuazhong Tan ret = hclgevf_pci_reset(hdev); 2993862d969aSHuazhong Tan if (ret) { 2994862d969aSHuazhong Tan dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2995862d969aSHuazhong Tan return ret; 2996862d969aSHuazhong Tan } 2997862d969aSHuazhong Tan 29989c6f7085SHuazhong Tan ret = hclgevf_cmd_init(hdev); 29999c6f7085SHuazhong Tan if (ret) { 30009c6f7085SHuazhong Tan dev_err(&pdev->dev, "cmd failed %d\n", ret); 30019c6f7085SHuazhong Tan return ret; 30027a01c897SSalil Mehta } 3003e2cb1decSSalil Mehta 30049c6f7085SHuazhong Tan ret = hclgevf_rss_init_hw(hdev); 30059c6f7085SHuazhong Tan if (ret) { 30069c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 30079c6f7085SHuazhong Tan "failed(%d) to initialize RSS\n", ret); 30089c6f7085SHuazhong Tan return ret; 30099c6f7085SHuazhong Tan } 30109c6f7085SHuazhong Tan 3011b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 3012b26a6feaSPeng Li if (ret) 3013b26a6feaSPeng Li return ret; 3014b26a6feaSPeng Li 30159c6f7085SHuazhong Tan ret = hclgevf_init_vlan_config(hdev); 30169c6f7085SHuazhong Tan if (ret) { 30179c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 30189c6f7085SHuazhong Tan "failed(%d) to initialize VLAN config\n", ret); 30199c6f7085SHuazhong Tan return ret; 30209c6f7085SHuazhong Tan } 30219c6f7085SHuazhong Tan 3022c631c696SJian Shen set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 3023c631c696SJian Shen 30249c6f7085SHuazhong Tan dev_info(&hdev->pdev->dev, "Reset done\n"); 30259c6f7085SHuazhong Tan 30269c6f7085SHuazhong Tan return 0; 30279c6f7085SHuazhong Tan } 30289c6f7085SHuazhong Tan 30299c6f7085SHuazhong Tan static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 30309c6f7085SHuazhong Tan { 30319c6f7085SHuazhong Tan struct pci_dev *pdev = hdev->pdev; 30329c6f7085SHuazhong Tan int ret; 30339c6f7085SHuazhong Tan 3034e2cb1decSSalil Mehta ret = hclgevf_pci_init(hdev); 303560df7e91SHuazhong Tan if (ret) 3036e2cb1decSSalil Mehta return ret; 3037e2cb1decSSalil Mehta 30388b0195a3SHuazhong Tan ret = hclgevf_cmd_queue_init(hdev); 303960df7e91SHuazhong Tan if (ret) 30408b0195a3SHuazhong Tan goto err_cmd_queue_init; 30418b0195a3SHuazhong Tan 3042eddf0462SYunsheng Lin ret = hclgevf_cmd_init(hdev); 3043eddf0462SYunsheng Lin if (ret) 3044eddf0462SYunsheng Lin goto err_cmd_init; 3045eddf0462SYunsheng Lin 304607acf909SJian Shen /* Get vf resource */ 304707acf909SJian Shen ret = hclgevf_query_vf_resource(hdev); 304860df7e91SHuazhong Tan if (ret) 30498b0195a3SHuazhong Tan goto err_cmd_init; 305007acf909SJian Shen 305107acf909SJian Shen ret = hclgevf_init_msi(hdev); 305207acf909SJian Shen if (ret) { 305307acf909SJian Shen dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 30548b0195a3SHuazhong Tan goto err_cmd_init; 305507acf909SJian Shen } 305607acf909SJian Shen 305707acf909SJian Shen hclgevf_state_init(hdev); 3058dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 3059afb6afdbSHuazhong Tan hdev->reset_type = HNAE3_NONE_RESET; 306007acf909SJian Shen 3061e2cb1decSSalil Mehta ret = hclgevf_misc_irq_init(hdev); 306260df7e91SHuazhong Tan if (ret) 3063e2cb1decSSalil Mehta goto err_misc_irq_init; 3064e2cb1decSSalil Mehta 3065862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3066862d969aSHuazhong Tan 3067e2cb1decSSalil Mehta ret = hclgevf_configure(hdev); 3068e2cb1decSSalil Mehta if (ret) { 3069e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 3070e2cb1decSSalil Mehta goto err_config; 3071e2cb1decSSalil Mehta } 3072e2cb1decSSalil Mehta 3073e2cb1decSSalil Mehta ret = hclgevf_alloc_tqps(hdev); 3074e2cb1decSSalil Mehta if (ret) { 3075e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 3076e2cb1decSSalil Mehta goto err_config; 3077e2cb1decSSalil Mehta } 3078e2cb1decSSalil Mehta 3079e2cb1decSSalil Mehta ret = hclgevf_set_handle_info(hdev); 308060df7e91SHuazhong Tan if (ret) 3081e2cb1decSSalil Mehta goto err_config; 3082e2cb1decSSalil Mehta 3083b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 3084b26a6feaSPeng Li if (ret) 3085b26a6feaSPeng Li goto err_config; 3086b26a6feaSPeng Li 3087e2cb1decSSalil Mehta /* Initialize RSS for this VF */ 3088944de484SGuojia Liao hclgevf_rss_init_cfg(hdev); 3089e2cb1decSSalil Mehta ret = hclgevf_rss_init_hw(hdev); 3090e2cb1decSSalil Mehta if (ret) { 3091e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 3092e2cb1decSSalil Mehta "failed(%d) to initialize RSS\n", ret); 3093e2cb1decSSalil Mehta goto err_config; 3094e2cb1decSSalil Mehta } 3095e2cb1decSSalil Mehta 3096039ba863SJian Shen /* ensure vf tbl list as empty before init*/ 3097039ba863SJian Shen ret = hclgevf_clear_vport_list(hdev); 3098039ba863SJian Shen if (ret) { 3099039ba863SJian Shen dev_err(&pdev->dev, 3100039ba863SJian Shen "failed to clear tbl list configuration, ret = %d.\n", 3101039ba863SJian Shen ret); 3102039ba863SJian Shen goto err_config; 3103039ba863SJian Shen } 3104039ba863SJian Shen 3105e2cb1decSSalil Mehta ret = hclgevf_init_vlan_config(hdev); 3106e2cb1decSSalil Mehta if (ret) { 3107e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 3108e2cb1decSSalil Mehta "failed(%d) to initialize VLAN config\n", ret); 3109e2cb1decSSalil Mehta goto err_config; 3110e2cb1decSSalil Mehta } 3111e2cb1decSSalil Mehta 31120742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 311308d80a4cSHuazhong Tan dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 311408d80a4cSHuazhong Tan HCLGEVF_DRIVER_NAME); 3115e2cb1decSSalil Mehta 3116ff200099SYunsheng Lin hclgevf_task_schedule(hdev, round_jiffies_relative(HZ)); 3117ff200099SYunsheng Lin 3118e2cb1decSSalil Mehta return 0; 3119e2cb1decSSalil Mehta 3120e2cb1decSSalil Mehta err_config: 3121e2cb1decSSalil Mehta hclgevf_misc_irq_uninit(hdev); 3122e2cb1decSSalil Mehta err_misc_irq_init: 3123e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 3124e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 312507acf909SJian Shen err_cmd_init: 31268b0195a3SHuazhong Tan hclgevf_cmd_uninit(hdev); 31278b0195a3SHuazhong Tan err_cmd_queue_init: 3128e2cb1decSSalil Mehta hclgevf_pci_uninit(hdev); 3129862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3130e2cb1decSSalil Mehta return ret; 3131e2cb1decSSalil Mehta } 3132e2cb1decSSalil Mehta 31337a01c897SSalil Mehta static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 3134e2cb1decSSalil Mehta { 3135d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 3136d3410018SYufeng Mo 3137e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 3138862d969aSHuazhong Tan 3139d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_VF_UNINIT, 0); 3140d3410018SYufeng Mo hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 314123b4201dSJian Shen 3142862d969aSHuazhong Tan if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3143eddf0462SYunsheng Lin hclgevf_misc_irq_uninit(hdev); 3144e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 31457a01c897SSalil Mehta } 31467a01c897SSalil Mehta 3147e3338205SHuazhong Tan hclgevf_pci_uninit(hdev); 3148862d969aSHuazhong Tan hclgevf_cmd_uninit(hdev); 3149ee4bcd3bSJian Shen hclgevf_uninit_mac_list(hdev); 3150862d969aSHuazhong Tan } 3151862d969aSHuazhong Tan 31527a01c897SSalil Mehta static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 31537a01c897SSalil Mehta { 31547a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 31557a01c897SSalil Mehta int ret; 31567a01c897SSalil Mehta 31577a01c897SSalil Mehta ret = hclgevf_alloc_hdev(ae_dev); 31587a01c897SSalil Mehta if (ret) { 31597a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device allocation failed\n"); 31607a01c897SSalil Mehta return ret; 31617a01c897SSalil Mehta } 31627a01c897SSalil Mehta 31637a01c897SSalil Mehta ret = hclgevf_init_hdev(ae_dev->priv); 3164a6d818e3SYunsheng Lin if (ret) { 31657a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device initialization failed\n"); 31667a01c897SSalil Mehta return ret; 31677a01c897SSalil Mehta } 31687a01c897SSalil Mehta 3169a6d818e3SYunsheng Lin return 0; 3170a6d818e3SYunsheng Lin } 3171a6d818e3SYunsheng Lin 31727a01c897SSalil Mehta static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 31737a01c897SSalil Mehta { 31747a01c897SSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 31757a01c897SSalil Mehta 31767a01c897SSalil Mehta hclgevf_uninit_hdev(hdev); 3177e2cb1decSSalil Mehta ae_dev->priv = NULL; 3178e2cb1decSSalil Mehta } 3179e2cb1decSSalil Mehta 3180849e4607SPeng Li static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 3181849e4607SPeng Li { 3182849e4607SPeng Li struct hnae3_handle *nic = &hdev->nic; 3183849e4607SPeng Li struct hnae3_knic_private_info *kinfo = &nic->kinfo; 3184849e4607SPeng Li 31858be73621SHuazhong Tan return min_t(u32, hdev->rss_size_max, 31868be73621SHuazhong Tan hdev->num_tqps / kinfo->num_tc); 3187849e4607SPeng Li } 3188849e4607SPeng Li 3189849e4607SPeng Li /** 3190849e4607SPeng Li * hclgevf_get_channels - Get the current channels enabled and max supported. 3191849e4607SPeng Li * @handle: hardware information for network interface 3192849e4607SPeng Li * @ch: ethtool channels structure 3193849e4607SPeng Li * 3194849e4607SPeng Li * We don't support separate tx and rx queues as channels. The other count 3195849e4607SPeng Li * represents how many queues are being used for control. max_combined counts 3196849e4607SPeng Li * how many queue pairs we can support. They may not be mapped 1 to 1 with 3197849e4607SPeng Li * q_vectors since we support a lot more queue pairs than q_vectors. 3198849e4607SPeng Li **/ 3199849e4607SPeng Li static void hclgevf_get_channels(struct hnae3_handle *handle, 3200849e4607SPeng Li struct ethtool_channels *ch) 3201849e4607SPeng Li { 3202849e4607SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3203849e4607SPeng Li 3204849e4607SPeng Li ch->max_combined = hclgevf_get_max_channels(hdev); 3205849e4607SPeng Li ch->other_count = 0; 3206849e4607SPeng Li ch->max_other = 0; 32078be73621SHuazhong Tan ch->combined_count = handle->kinfo.rss_size; 3208849e4607SPeng Li } 3209849e4607SPeng Li 3210cc719218SPeng Li static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 32110d43bf45SHuazhong Tan u16 *alloc_tqps, u16 *max_rss_size) 3212cc719218SPeng Li { 3213cc719218SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3214cc719218SPeng Li 32150d43bf45SHuazhong Tan *alloc_tqps = hdev->num_tqps; 3216cc719218SPeng Li *max_rss_size = hdev->rss_size_max; 3217cc719218SPeng Li } 3218cc719218SPeng Li 32194093d1a2SGuangbin Huang static void hclgevf_update_rss_size(struct hnae3_handle *handle, 32204093d1a2SGuangbin Huang u32 new_tqps_num) 32214093d1a2SGuangbin Huang { 32224093d1a2SGuangbin Huang struct hnae3_knic_private_info *kinfo = &handle->kinfo; 32234093d1a2SGuangbin Huang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 32244093d1a2SGuangbin Huang u16 max_rss_size; 32254093d1a2SGuangbin Huang 32264093d1a2SGuangbin Huang kinfo->req_rss_size = new_tqps_num; 32274093d1a2SGuangbin Huang 32284093d1a2SGuangbin Huang max_rss_size = min_t(u16, hdev->rss_size_max, 32294093d1a2SGuangbin Huang hdev->num_tqps / kinfo->num_tc); 32304093d1a2SGuangbin Huang 32314093d1a2SGuangbin Huang /* Use the user's configuration when it is not larger than 32324093d1a2SGuangbin Huang * max_rss_size, otherwise, use the maximum specification value. 32334093d1a2SGuangbin Huang */ 32344093d1a2SGuangbin Huang if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 32354093d1a2SGuangbin Huang kinfo->req_rss_size <= max_rss_size) 32364093d1a2SGuangbin Huang kinfo->rss_size = kinfo->req_rss_size; 32374093d1a2SGuangbin Huang else if (kinfo->rss_size > max_rss_size || 32384093d1a2SGuangbin Huang (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) 32394093d1a2SGuangbin Huang kinfo->rss_size = max_rss_size; 32404093d1a2SGuangbin Huang 32414093d1a2SGuangbin Huang kinfo->num_tqps = kinfo->num_tc * kinfo->rss_size; 32424093d1a2SGuangbin Huang } 32434093d1a2SGuangbin Huang 32444093d1a2SGuangbin Huang static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 32454093d1a2SGuangbin Huang bool rxfh_configured) 32464093d1a2SGuangbin Huang { 32474093d1a2SGuangbin Huang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 32484093d1a2SGuangbin Huang struct hnae3_knic_private_info *kinfo = &handle->kinfo; 32494093d1a2SGuangbin Huang u16 cur_rss_size = kinfo->rss_size; 32504093d1a2SGuangbin Huang u16 cur_tqps = kinfo->num_tqps; 32514093d1a2SGuangbin Huang u32 *rss_indir; 32524093d1a2SGuangbin Huang unsigned int i; 32534093d1a2SGuangbin Huang int ret; 32544093d1a2SGuangbin Huang 32554093d1a2SGuangbin Huang hclgevf_update_rss_size(handle, new_tqps_num); 32564093d1a2SGuangbin Huang 32574093d1a2SGuangbin Huang ret = hclgevf_set_rss_tc_mode(hdev, kinfo->rss_size); 32584093d1a2SGuangbin Huang if (ret) 32594093d1a2SGuangbin Huang return ret; 32604093d1a2SGuangbin Huang 32614093d1a2SGuangbin Huang /* RSS indirection table has been configuared by user */ 32624093d1a2SGuangbin Huang if (rxfh_configured) 32634093d1a2SGuangbin Huang goto out; 32644093d1a2SGuangbin Huang 32654093d1a2SGuangbin Huang /* Reinitializes the rss indirect table according to the new RSS size */ 32664093d1a2SGuangbin Huang rss_indir = kcalloc(HCLGEVF_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL); 32674093d1a2SGuangbin Huang if (!rss_indir) 32684093d1a2SGuangbin Huang return -ENOMEM; 32694093d1a2SGuangbin Huang 32704093d1a2SGuangbin Huang for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 32714093d1a2SGuangbin Huang rss_indir[i] = i % kinfo->rss_size; 32724093d1a2SGuangbin Huang 3273944de484SGuojia Liao hdev->rss_cfg.rss_size = kinfo->rss_size; 3274944de484SGuojia Liao 32754093d1a2SGuangbin Huang ret = hclgevf_set_rss(handle, rss_indir, NULL, 0); 32764093d1a2SGuangbin Huang if (ret) 32774093d1a2SGuangbin Huang dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 32784093d1a2SGuangbin Huang ret); 32794093d1a2SGuangbin Huang 32804093d1a2SGuangbin Huang kfree(rss_indir); 32814093d1a2SGuangbin Huang 32824093d1a2SGuangbin Huang out: 32834093d1a2SGuangbin Huang if (!ret) 32844093d1a2SGuangbin Huang dev_info(&hdev->pdev->dev, 32854093d1a2SGuangbin Huang "Channels changed, rss_size from %u to %u, tqps from %u to %u", 32864093d1a2SGuangbin Huang cur_rss_size, kinfo->rss_size, 32874093d1a2SGuangbin Huang cur_tqps, kinfo->rss_size * kinfo->num_tc); 32884093d1a2SGuangbin Huang 32894093d1a2SGuangbin Huang return ret; 32904093d1a2SGuangbin Huang } 32914093d1a2SGuangbin Huang 3292175ec96bSFuyun Liang static int hclgevf_get_status(struct hnae3_handle *handle) 3293175ec96bSFuyun Liang { 3294175ec96bSFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3295175ec96bSFuyun Liang 3296175ec96bSFuyun Liang return hdev->hw.mac.link; 3297175ec96bSFuyun Liang } 3298175ec96bSFuyun Liang 32994a152de9SFuyun Liang static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 33004a152de9SFuyun Liang u8 *auto_neg, u32 *speed, 33014a152de9SFuyun Liang u8 *duplex) 33024a152de9SFuyun Liang { 33034a152de9SFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 33044a152de9SFuyun Liang 33054a152de9SFuyun Liang if (speed) 33064a152de9SFuyun Liang *speed = hdev->hw.mac.speed; 33074a152de9SFuyun Liang if (duplex) 33084a152de9SFuyun Liang *duplex = hdev->hw.mac.duplex; 33094a152de9SFuyun Liang if (auto_neg) 33104a152de9SFuyun Liang *auto_neg = AUTONEG_DISABLE; 33114a152de9SFuyun Liang } 33124a152de9SFuyun Liang 33134a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 33144a152de9SFuyun Liang u8 duplex) 33154a152de9SFuyun Liang { 33164a152de9SFuyun Liang hdev->hw.mac.speed = speed; 33174a152de9SFuyun Liang hdev->hw.mac.duplex = duplex; 33184a152de9SFuyun Liang } 33194a152de9SFuyun Liang 33201731be4cSYonglong Liu static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 33215c9f6b39SPeng Li { 33225c9f6b39SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 33235c9f6b39SPeng Li 33245c9f6b39SPeng Li return hclgevf_config_gro(hdev, enable); 33255c9f6b39SPeng Li } 33265c9f6b39SPeng Li 332788d10bd6SJian Shen static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 332888d10bd6SJian Shen u8 *module_type) 3329c136b884SPeng Li { 3330c136b884SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 333188d10bd6SJian Shen 3332c136b884SPeng Li if (media_type) 3333c136b884SPeng Li *media_type = hdev->hw.mac.media_type; 333488d10bd6SJian Shen 333588d10bd6SJian Shen if (module_type) 333688d10bd6SJian Shen *module_type = hdev->hw.mac.module_type; 3337c136b884SPeng Li } 3338c136b884SPeng Li 33394d60291bSHuazhong Tan static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 33404d60291bSHuazhong Tan { 33414d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 33424d60291bSHuazhong Tan 3343aa5c4f17SHuazhong Tan return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 33444d60291bSHuazhong Tan } 33454d60291bSHuazhong Tan 33464d60291bSHuazhong Tan static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 33474d60291bSHuazhong Tan { 33484d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 33494d60291bSHuazhong Tan 33504d60291bSHuazhong Tan return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 33514d60291bSHuazhong Tan } 33524d60291bSHuazhong Tan 33534d60291bSHuazhong Tan static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 33544d60291bSHuazhong Tan { 33554d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 33564d60291bSHuazhong Tan 3357c88a6e7dSHuazhong Tan return hdev->rst_stats.hw_rst_done_cnt; 33584d60291bSHuazhong Tan } 33594d60291bSHuazhong Tan 33609194d18bSliuzhongzhu static void hclgevf_get_link_mode(struct hnae3_handle *handle, 33619194d18bSliuzhongzhu unsigned long *supported, 33629194d18bSliuzhongzhu unsigned long *advertising) 33639194d18bSliuzhongzhu { 33649194d18bSliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 33659194d18bSliuzhongzhu 33669194d18bSliuzhongzhu *supported = hdev->hw.mac.supported; 33679194d18bSliuzhongzhu *advertising = hdev->hw.mac.advertising; 33689194d18bSliuzhongzhu } 33699194d18bSliuzhongzhu 33701600c3e5SJian Shen #define MAX_SEPARATE_NUM 4 33711600c3e5SJian Shen #define SEPARATOR_VALUE 0xFFFFFFFF 33721600c3e5SJian Shen #define REG_NUM_PER_LINE 4 33731600c3e5SJian Shen #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 33741600c3e5SJian Shen 33751600c3e5SJian Shen static int hclgevf_get_regs_len(struct hnae3_handle *handle) 33761600c3e5SJian Shen { 33771600c3e5SJian Shen int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 33781600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 33791600c3e5SJian Shen 33801600c3e5SJian Shen cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 33811600c3e5SJian Shen common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 33821600c3e5SJian Shen ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 33831600c3e5SJian Shen tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 33841600c3e5SJian Shen 33851600c3e5SJian Shen return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 33861600c3e5SJian Shen tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 33871600c3e5SJian Shen } 33881600c3e5SJian Shen 33891600c3e5SJian Shen static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 33901600c3e5SJian Shen void *data) 33911600c3e5SJian Shen { 33921600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 33931600c3e5SJian Shen int i, j, reg_um, separator_num; 33941600c3e5SJian Shen u32 *reg = data; 33951600c3e5SJian Shen 33961600c3e5SJian Shen *version = hdev->fw_version; 33971600c3e5SJian Shen 33981600c3e5SJian Shen /* fetching per-VF registers values from VF PCIe register space */ 33991600c3e5SJian Shen reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 34001600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 34011600c3e5SJian Shen for (i = 0; i < reg_um; i++) 34021600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 34031600c3e5SJian Shen for (i = 0; i < separator_num; i++) 34041600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 34051600c3e5SJian Shen 34061600c3e5SJian Shen reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 34071600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 34081600c3e5SJian Shen for (i = 0; i < reg_um; i++) 34091600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 34101600c3e5SJian Shen for (i = 0; i < separator_num; i++) 34111600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 34121600c3e5SJian Shen 34131600c3e5SJian Shen reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 34141600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 34151600c3e5SJian Shen for (j = 0; j < hdev->num_tqps; j++) { 34161600c3e5SJian Shen for (i = 0; i < reg_um; i++) 34171600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 34181600c3e5SJian Shen ring_reg_addr_list[i] + 34191600c3e5SJian Shen 0x200 * j); 34201600c3e5SJian Shen for (i = 0; i < separator_num; i++) 34211600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 34221600c3e5SJian Shen } 34231600c3e5SJian Shen 34241600c3e5SJian Shen reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 34251600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 34261600c3e5SJian Shen for (j = 0; j < hdev->num_msi_used - 1; j++) { 34271600c3e5SJian Shen for (i = 0; i < reg_um; i++) 34281600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 34291600c3e5SJian Shen tqp_intr_reg_addr_list[i] + 34301600c3e5SJian Shen 4 * j); 34311600c3e5SJian Shen for (i = 0; i < separator_num; i++) 34321600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 34331600c3e5SJian Shen } 34341600c3e5SJian Shen } 34351600c3e5SJian Shen 343692f11ea1SJian Shen void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 343792f11ea1SJian Shen u8 *port_base_vlan_info, u8 data_size) 343892f11ea1SJian Shen { 343992f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 3440d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 3441a6f7bfdcSJian Shen int ret; 344292f11ea1SJian Shen 344392f11ea1SJian Shen rtnl_lock(); 3444a6f7bfdcSJian Shen 3445b7b5d25bSGuojia Liao if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 3446b7b5d25bSGuojia Liao test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) { 3447a6f7bfdcSJian Shen dev_warn(&hdev->pdev->dev, 3448a6f7bfdcSJian Shen "is resetting when updating port based vlan info\n"); 344992f11ea1SJian Shen rtnl_unlock(); 3450a6f7bfdcSJian Shen return; 3451a6f7bfdcSJian Shen } 3452a6f7bfdcSJian Shen 3453a6f7bfdcSJian Shen ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 3454a6f7bfdcSJian Shen if (ret) { 3455a6f7bfdcSJian Shen rtnl_unlock(); 3456a6f7bfdcSJian Shen return; 3457a6f7bfdcSJian Shen } 345892f11ea1SJian Shen 345992f11ea1SJian Shen /* send msg to PF and wait update port based vlan info */ 3460d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 3461d3410018SYufeng Mo HCLGE_MBX_PORT_BASE_VLAN_CFG); 3462d3410018SYufeng Mo memcpy(send_msg.data, port_base_vlan_info, data_size); 3463a6f7bfdcSJian Shen ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3464a6f7bfdcSJian Shen if (!ret) { 346592f11ea1SJian Shen if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 3466a6f7bfdcSJian Shen nic->port_base_vlan_state = state; 346792f11ea1SJian Shen else 346892f11ea1SJian Shen nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 3469a6f7bfdcSJian Shen } 347092f11ea1SJian Shen 347192f11ea1SJian Shen hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 347292f11ea1SJian Shen rtnl_unlock(); 347392f11ea1SJian Shen } 347492f11ea1SJian Shen 3475e2cb1decSSalil Mehta static const struct hnae3_ae_ops hclgevf_ops = { 3476e2cb1decSSalil Mehta .init_ae_dev = hclgevf_init_ae_dev, 3477e2cb1decSSalil Mehta .uninit_ae_dev = hclgevf_uninit_ae_dev, 34786ff3cf07SHuazhong Tan .flr_prepare = hclgevf_flr_prepare, 34796ff3cf07SHuazhong Tan .flr_done = hclgevf_flr_done, 3480e718a93fSPeng Li .init_client_instance = hclgevf_init_client_instance, 3481e718a93fSPeng Li .uninit_client_instance = hclgevf_uninit_client_instance, 3482e2cb1decSSalil Mehta .start = hclgevf_ae_start, 3483e2cb1decSSalil Mehta .stop = hclgevf_ae_stop, 3484a6d818e3SYunsheng Lin .client_start = hclgevf_client_start, 3485a6d818e3SYunsheng Lin .client_stop = hclgevf_client_stop, 3486e2cb1decSSalil Mehta .map_ring_to_vector = hclgevf_map_ring_to_vector, 3487e2cb1decSSalil Mehta .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 3488e2cb1decSSalil Mehta .get_vector = hclgevf_get_vector, 34890d3e6631SYunsheng Lin .put_vector = hclgevf_put_vector, 3490e2cb1decSSalil Mehta .reset_queue = hclgevf_reset_tqp, 3491e2cb1decSSalil Mehta .get_mac_addr = hclgevf_get_mac_addr, 3492e2cb1decSSalil Mehta .set_mac_addr = hclgevf_set_mac_addr, 3493e2cb1decSSalil Mehta .add_uc_addr = hclgevf_add_uc_addr, 3494e2cb1decSSalil Mehta .rm_uc_addr = hclgevf_rm_uc_addr, 3495e2cb1decSSalil Mehta .add_mc_addr = hclgevf_add_mc_addr, 3496e2cb1decSSalil Mehta .rm_mc_addr = hclgevf_rm_mc_addr, 3497e2cb1decSSalil Mehta .get_stats = hclgevf_get_stats, 3498e2cb1decSSalil Mehta .update_stats = hclgevf_update_stats, 3499e2cb1decSSalil Mehta .get_strings = hclgevf_get_strings, 3500e2cb1decSSalil Mehta .get_sset_count = hclgevf_get_sset_count, 3501e2cb1decSSalil Mehta .get_rss_key_size = hclgevf_get_rss_key_size, 3502e2cb1decSSalil Mehta .get_rss_indir_size = hclgevf_get_rss_indir_size, 3503e2cb1decSSalil Mehta .get_rss = hclgevf_get_rss, 3504e2cb1decSSalil Mehta .set_rss = hclgevf_set_rss, 3505d97b3072SJian Shen .get_rss_tuple = hclgevf_get_rss_tuple, 3506d97b3072SJian Shen .set_rss_tuple = hclgevf_set_rss_tuple, 3507e2cb1decSSalil Mehta .get_tc_size = hclgevf_get_tc_size, 3508e2cb1decSSalil Mehta .get_fw_version = hclgevf_get_fw_version, 3509e2cb1decSSalil Mehta .set_vlan_filter = hclgevf_set_vlan_filter, 3510b2641e2aSYunsheng Lin .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 35116d4c3981SSalil Mehta .reset_event = hclgevf_reset_event, 3512720bd583SHuazhong Tan .set_default_reset_request = hclgevf_set_def_reset_request, 35134093d1a2SGuangbin Huang .set_channels = hclgevf_set_channels, 3514849e4607SPeng Li .get_channels = hclgevf_get_channels, 3515cc719218SPeng Li .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 35161600c3e5SJian Shen .get_regs_len = hclgevf_get_regs_len, 35171600c3e5SJian Shen .get_regs = hclgevf_get_regs, 3518175ec96bSFuyun Liang .get_status = hclgevf_get_status, 35194a152de9SFuyun Liang .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3520c136b884SPeng Li .get_media_type = hclgevf_get_media_type, 35214d60291bSHuazhong Tan .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 35224d60291bSHuazhong Tan .ae_dev_resetting = hclgevf_ae_dev_resetting, 35234d60291bSHuazhong Tan .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 35245c9f6b39SPeng Li .set_gro_en = hclgevf_gro_en, 3525818f1675SYunsheng Lin .set_mtu = hclgevf_set_mtu, 35260c29d191Sliuzhongzhu .get_global_queue_id = hclgevf_get_qid_global, 35278cdb992fSJian Shen .set_timer_task = hclgevf_set_timer_task, 35289194d18bSliuzhongzhu .get_link_mode = hclgevf_get_link_mode, 3529e196ec75SJian Shen .set_promisc_mode = hclgevf_set_promisc_mode, 3530c631c696SJian Shen .request_update_promisc_mode = hclgevf_request_update_promisc_mode, 3531e2cb1decSSalil Mehta }; 3532e2cb1decSSalil Mehta 3533e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf = { 3534e2cb1decSSalil Mehta .ops = &hclgevf_ops, 3535e2cb1decSSalil Mehta .pdev_id_table = ae_algovf_pci_tbl, 3536e2cb1decSSalil Mehta }; 3537e2cb1decSSalil Mehta 3538e2cb1decSSalil Mehta static int hclgevf_init(void) 3539e2cb1decSSalil Mehta { 3540e2cb1decSSalil Mehta pr_info("%s is initializing\n", HCLGEVF_NAME); 3541e2cb1decSSalil Mehta 354216deaef2SYunsheng Lin hclgevf_wq = alloc_workqueue("%s", 0, 0, HCLGEVF_NAME); 35430ea68902SYunsheng Lin if (!hclgevf_wq) { 35440ea68902SYunsheng Lin pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME); 35450ea68902SYunsheng Lin return -ENOMEM; 35460ea68902SYunsheng Lin } 35470ea68902SYunsheng Lin 3548854cf33aSFuyun Liang hnae3_register_ae_algo(&ae_algovf); 3549854cf33aSFuyun Liang 3550854cf33aSFuyun Liang return 0; 3551e2cb1decSSalil Mehta } 3552e2cb1decSSalil Mehta 3553e2cb1decSSalil Mehta static void hclgevf_exit(void) 3554e2cb1decSSalil Mehta { 3555e2cb1decSSalil Mehta hnae3_unregister_ae_algo(&ae_algovf); 35560ea68902SYunsheng Lin destroy_workqueue(hclgevf_wq); 3557e2cb1decSSalil Mehta } 3558e2cb1decSSalil Mehta module_init(hclgevf_init); 3559e2cb1decSSalil Mehta module_exit(hclgevf_exit); 3560e2cb1decSSalil Mehta 3561e2cb1decSSalil Mehta MODULE_LICENSE("GPL"); 3562e2cb1decSSalil Mehta MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3563e2cb1decSSalil Mehta MODULE_DESCRIPTION("HCLGEVF Driver"); 3564e2cb1decSSalil Mehta MODULE_VERSION(HCLGEVF_MOD_VERSION); 3565