1e2cb1decSSalil Mehta // SPDX-License-Identifier: GPL-2.0+ 2e2cb1decSSalil Mehta // Copyright (c) 2016-2017 Hisilicon Limited. 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #include <linux/etherdevice.h> 5aa5c4f17SHuazhong Tan #include <linux/iopoll.h> 66988eb2aSSalil Mehta #include <net/rtnetlink.h> 7e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 8e2cb1decSSalil Mehta #include "hclgevf_main.h" 9e2cb1decSSalil Mehta #include "hclge_mbx.h" 10e2cb1decSSalil Mehta #include "hnae3.h" 11e2cb1decSSalil Mehta 12e2cb1decSSalil Mehta #define HCLGEVF_NAME "hclgevf" 13e2cb1decSSalil Mehta 149c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 15e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf; 16e2cb1decSSalil Mehta 17e2cb1decSSalil Mehta static const struct pci_device_id ae_algovf_pci_tbl[] = { 18e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 19e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 20e2cb1decSSalil Mehta /* required last entry */ 21e2cb1decSSalil Mehta {0, } 22e2cb1decSSalil Mehta }; 23e2cb1decSSalil Mehta 24472d7eceSJian Shen static const u8 hclgevf_hash_key[] = { 25472d7eceSJian Shen 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 26472d7eceSJian Shen 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 27472d7eceSJian Shen 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 28472d7eceSJian Shen 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 29472d7eceSJian Shen 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 30472d7eceSJian Shen }; 31472d7eceSJian Shen 322f550a46SYunsheng Lin MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 332f550a46SYunsheng Lin 341600c3e5SJian Shen static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 351600c3e5SJian Shen HCLGEVF_CMDQ_TX_ADDR_H_REG, 361600c3e5SJian Shen HCLGEVF_CMDQ_TX_DEPTH_REG, 371600c3e5SJian Shen HCLGEVF_CMDQ_TX_TAIL_REG, 381600c3e5SJian Shen HCLGEVF_CMDQ_TX_HEAD_REG, 391600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_L_REG, 401600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_H_REG, 411600c3e5SJian Shen HCLGEVF_CMDQ_RX_DEPTH_REG, 421600c3e5SJian Shen HCLGEVF_CMDQ_RX_TAIL_REG, 431600c3e5SJian Shen HCLGEVF_CMDQ_RX_HEAD_REG, 441600c3e5SJian Shen HCLGEVF_VECTOR0_CMDQ_SRC_REG, 451600c3e5SJian Shen HCLGEVF_CMDQ_INTR_STS_REG, 461600c3e5SJian Shen HCLGEVF_CMDQ_INTR_EN_REG, 471600c3e5SJian Shen HCLGEVF_CMDQ_INTR_GEN_REG}; 481600c3e5SJian Shen 491600c3e5SJian Shen static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 501600c3e5SJian Shen HCLGEVF_RST_ING, 511600c3e5SJian Shen HCLGEVF_GRO_EN_REG}; 521600c3e5SJian Shen 531600c3e5SJian Shen static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 541600c3e5SJian Shen HCLGEVF_RING_RX_ADDR_H_REG, 551600c3e5SJian Shen HCLGEVF_RING_RX_BD_NUM_REG, 561600c3e5SJian Shen HCLGEVF_RING_RX_BD_LENGTH_REG, 571600c3e5SJian Shen HCLGEVF_RING_RX_MERGE_EN_REG, 581600c3e5SJian Shen HCLGEVF_RING_RX_TAIL_REG, 591600c3e5SJian Shen HCLGEVF_RING_RX_HEAD_REG, 601600c3e5SJian Shen HCLGEVF_RING_RX_FBD_NUM_REG, 611600c3e5SJian Shen HCLGEVF_RING_RX_OFFSET_REG, 621600c3e5SJian Shen HCLGEVF_RING_RX_FBD_OFFSET_REG, 631600c3e5SJian Shen HCLGEVF_RING_RX_STASH_REG, 641600c3e5SJian Shen HCLGEVF_RING_RX_BD_ERR_REG, 651600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_L_REG, 661600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_H_REG, 671600c3e5SJian Shen HCLGEVF_RING_TX_BD_NUM_REG, 681600c3e5SJian Shen HCLGEVF_RING_TX_PRIORITY_REG, 691600c3e5SJian Shen HCLGEVF_RING_TX_TC_REG, 701600c3e5SJian Shen HCLGEVF_RING_TX_MERGE_EN_REG, 711600c3e5SJian Shen HCLGEVF_RING_TX_TAIL_REG, 721600c3e5SJian Shen HCLGEVF_RING_TX_HEAD_REG, 731600c3e5SJian Shen HCLGEVF_RING_TX_FBD_NUM_REG, 741600c3e5SJian Shen HCLGEVF_RING_TX_OFFSET_REG, 751600c3e5SJian Shen HCLGEVF_RING_TX_EBD_NUM_REG, 761600c3e5SJian Shen HCLGEVF_RING_TX_EBD_OFFSET_REG, 771600c3e5SJian Shen HCLGEVF_RING_TX_BD_ERR_REG, 781600c3e5SJian Shen HCLGEVF_RING_EN_REG}; 791600c3e5SJian Shen 801600c3e5SJian Shen static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 811600c3e5SJian Shen HCLGEVF_TQP_INTR_GL0_REG, 821600c3e5SJian Shen HCLGEVF_TQP_INTR_GL1_REG, 831600c3e5SJian Shen HCLGEVF_TQP_INTR_GL2_REG, 841600c3e5SJian Shen HCLGEVF_TQP_INTR_RL_REG}; 851600c3e5SJian Shen 86e2cb1decSSalil Mehta static inline struct hclgevf_dev *hclgevf_ae_get_hdev( 87e2cb1decSSalil Mehta struct hnae3_handle *handle) 88e2cb1decSSalil Mehta { 89eed9535fSPeng Li if (!handle->client) 90eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, nic); 91eed9535fSPeng Li else if (handle->client->type == HNAE3_CLIENT_ROCE) 92eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, roce); 93eed9535fSPeng Li else 94e2cb1decSSalil Mehta return container_of(handle, struct hclgevf_dev, nic); 95e2cb1decSSalil Mehta } 96e2cb1decSSalil Mehta 97e2cb1decSSalil Mehta static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 98e2cb1decSSalil Mehta { 99b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 100e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 101e2cb1decSSalil Mehta struct hclgevf_desc desc; 102e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 103e2cb1decSSalil Mehta int status; 104e2cb1decSSalil Mehta int i; 105e2cb1decSSalil Mehta 106b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 107b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 108e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 109e2cb1decSSalil Mehta HCLGEVF_OPC_QUERY_RX_STATUS, 110e2cb1decSSalil Mehta true); 111e2cb1decSSalil Mehta 112e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 113e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 114e2cb1decSSalil Mehta if (status) { 115e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 116e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 117e2cb1decSSalil Mehta status, i); 118e2cb1decSSalil Mehta return status; 119e2cb1decSSalil Mehta } 120e2cb1decSSalil Mehta tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 121cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 122e2cb1decSSalil Mehta 123e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 124e2cb1decSSalil Mehta true); 125e2cb1decSSalil Mehta 126e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 127e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 128e2cb1decSSalil Mehta if (status) { 129e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 130e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 131e2cb1decSSalil Mehta status, i); 132e2cb1decSSalil Mehta return status; 133e2cb1decSSalil Mehta } 134e2cb1decSSalil Mehta tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 135cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 136e2cb1decSSalil Mehta } 137e2cb1decSSalil Mehta 138e2cb1decSSalil Mehta return 0; 139e2cb1decSSalil Mehta } 140e2cb1decSSalil Mehta 141e2cb1decSSalil Mehta static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 142e2cb1decSSalil Mehta { 143e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo = &handle->kinfo; 144e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 145e2cb1decSSalil Mehta u64 *buff = data; 146e2cb1decSSalil Mehta int i; 147e2cb1decSSalil Mehta 148b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 149b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 150e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 151e2cb1decSSalil Mehta } 152e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 153b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 154e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 155e2cb1decSSalil Mehta } 156e2cb1decSSalil Mehta 157e2cb1decSSalil Mehta return buff; 158e2cb1decSSalil Mehta } 159e2cb1decSSalil Mehta 160e2cb1decSSalil Mehta static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 161e2cb1decSSalil Mehta { 162b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 163e2cb1decSSalil Mehta 164b4f1d303SJian Shen return kinfo->num_tqps * 2; 165e2cb1decSSalil Mehta } 166e2cb1decSSalil Mehta 167e2cb1decSSalil Mehta static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 168e2cb1decSSalil Mehta { 169b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 170e2cb1decSSalil Mehta u8 *buff = data; 171e2cb1decSSalil Mehta int i = 0; 172e2cb1decSSalil Mehta 173b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 174b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 175e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1760c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 177e2cb1decSSalil Mehta tqp->index); 178e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 179e2cb1decSSalil Mehta } 180e2cb1decSSalil Mehta 181b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 182b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 183e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1840c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 185e2cb1decSSalil Mehta tqp->index); 186e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 187e2cb1decSSalil Mehta } 188e2cb1decSSalil Mehta 189e2cb1decSSalil Mehta return buff; 190e2cb1decSSalil Mehta } 191e2cb1decSSalil Mehta 192e2cb1decSSalil Mehta static void hclgevf_update_stats(struct hnae3_handle *handle, 193e2cb1decSSalil Mehta struct net_device_stats *net_stats) 194e2cb1decSSalil Mehta { 195e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 196e2cb1decSSalil Mehta int status; 197e2cb1decSSalil Mehta 198e2cb1decSSalil Mehta status = hclgevf_tqps_update_stats(handle); 199e2cb1decSSalil Mehta if (status) 200e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 201e2cb1decSSalil Mehta "VF update of TQPS stats fail, status = %d.\n", 202e2cb1decSSalil Mehta status); 203e2cb1decSSalil Mehta } 204e2cb1decSSalil Mehta 205e2cb1decSSalil Mehta static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 206e2cb1decSSalil Mehta { 207e2cb1decSSalil Mehta if (strset == ETH_SS_TEST) 208e2cb1decSSalil Mehta return -EOPNOTSUPP; 209e2cb1decSSalil Mehta else if (strset == ETH_SS_STATS) 210e2cb1decSSalil Mehta return hclgevf_tqps_get_sset_count(handle, strset); 211e2cb1decSSalil Mehta 212e2cb1decSSalil Mehta return 0; 213e2cb1decSSalil Mehta } 214e2cb1decSSalil Mehta 215e2cb1decSSalil Mehta static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 216e2cb1decSSalil Mehta u8 *data) 217e2cb1decSSalil Mehta { 218e2cb1decSSalil Mehta u8 *p = (char *)data; 219e2cb1decSSalil Mehta 220e2cb1decSSalil Mehta if (strset == ETH_SS_STATS) 221e2cb1decSSalil Mehta p = hclgevf_tqps_get_strings(handle, p); 222e2cb1decSSalil Mehta } 223e2cb1decSSalil Mehta 224e2cb1decSSalil Mehta static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 225e2cb1decSSalil Mehta { 226e2cb1decSSalil Mehta hclgevf_tqps_get_stats(handle, data); 227e2cb1decSSalil Mehta } 228e2cb1decSSalil Mehta 229e2cb1decSSalil Mehta static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 230e2cb1decSSalil Mehta { 231e2cb1decSSalil Mehta u8 resp_msg; 232e2cb1decSSalil Mehta int status; 233e2cb1decSSalil Mehta 234e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 235e2cb1decSSalil Mehta true, &resp_msg, sizeof(u8)); 236e2cb1decSSalil Mehta if (status) { 237e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 238e2cb1decSSalil Mehta "VF request to get TC info from PF failed %d", 239e2cb1decSSalil Mehta status); 240e2cb1decSSalil Mehta return status; 241e2cb1decSSalil Mehta } 242e2cb1decSSalil Mehta 243e2cb1decSSalil Mehta hdev->hw_tc_map = resp_msg; 244e2cb1decSSalil Mehta 245e2cb1decSSalil Mehta return 0; 246e2cb1decSSalil Mehta } 247e2cb1decSSalil Mehta 2486cee6fc3SJian Shen static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 249e2cb1decSSalil Mehta { 250c0425944SPeng Li #define HCLGEVF_TQPS_RSS_INFO_LEN 6 251e2cb1decSSalil Mehta u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 252e2cb1decSSalil Mehta int status; 253e2cb1decSSalil Mehta 254e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 255e2cb1decSSalil Mehta true, resp_msg, 256e2cb1decSSalil Mehta HCLGEVF_TQPS_RSS_INFO_LEN); 257e2cb1decSSalil Mehta if (status) { 258e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 259e2cb1decSSalil Mehta "VF request to get tqp info from PF failed %d", 260e2cb1decSSalil Mehta status); 261e2cb1decSSalil Mehta return status; 262e2cb1decSSalil Mehta } 263e2cb1decSSalil Mehta 264e2cb1decSSalil Mehta memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 265e2cb1decSSalil Mehta memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 266c0425944SPeng Li memcpy(&hdev->rx_buf_len, &resp_msg[4], sizeof(u16)); 267c0425944SPeng Li 268c0425944SPeng Li return 0; 269c0425944SPeng Li } 270c0425944SPeng Li 271c0425944SPeng Li static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 272c0425944SPeng Li { 273c0425944SPeng Li #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 274c0425944SPeng Li u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 275c0425944SPeng Li int ret; 276c0425944SPeng Li 277c0425944SPeng Li ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QDEPTH, 0, NULL, 0, 278c0425944SPeng Li true, resp_msg, 279c0425944SPeng Li HCLGEVF_TQPS_DEPTH_INFO_LEN); 280c0425944SPeng Li if (ret) { 281c0425944SPeng Li dev_err(&hdev->pdev->dev, 282c0425944SPeng Li "VF request to get tqp depth info from PF failed %d", 283c0425944SPeng Li ret); 284c0425944SPeng Li return ret; 285c0425944SPeng Li } 286c0425944SPeng Li 287c0425944SPeng Li memcpy(&hdev->num_tx_desc, &resp_msg[0], sizeof(u16)); 288c0425944SPeng Li memcpy(&hdev->num_rx_desc, &resp_msg[2], sizeof(u16)); 289e2cb1decSSalil Mehta 290e2cb1decSSalil Mehta return 0; 291e2cb1decSSalil Mehta } 292e2cb1decSSalil Mehta 2930c29d191Sliuzhongzhu static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 2940c29d191Sliuzhongzhu { 2950c29d191Sliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2960c29d191Sliuzhongzhu u8 msg_data[2], resp_data[2]; 2970c29d191Sliuzhongzhu u16 qid_in_pf = 0; 2980c29d191Sliuzhongzhu int ret; 2990c29d191Sliuzhongzhu 3000c29d191Sliuzhongzhu memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 3010c29d191Sliuzhongzhu 3020c29d191Sliuzhongzhu ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data, 3030c29d191Sliuzhongzhu 2, true, resp_data, 2); 3040c29d191Sliuzhongzhu if (!ret) 3050c29d191Sliuzhongzhu qid_in_pf = *(u16 *)resp_data; 3060c29d191Sliuzhongzhu 3070c29d191Sliuzhongzhu return qid_in_pf; 3080c29d191Sliuzhongzhu } 3090c29d191Sliuzhongzhu 310e2cb1decSSalil Mehta static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 311e2cb1decSSalil Mehta { 312e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 313e2cb1decSSalil Mehta int i; 314e2cb1decSSalil Mehta 315e2cb1decSSalil Mehta hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 316e2cb1decSSalil Mehta sizeof(struct hclgevf_tqp), GFP_KERNEL); 317e2cb1decSSalil Mehta if (!hdev->htqp) 318e2cb1decSSalil Mehta return -ENOMEM; 319e2cb1decSSalil Mehta 320e2cb1decSSalil Mehta tqp = hdev->htqp; 321e2cb1decSSalil Mehta 322e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 323e2cb1decSSalil Mehta tqp->dev = &hdev->pdev->dev; 324e2cb1decSSalil Mehta tqp->index = i; 325e2cb1decSSalil Mehta 326e2cb1decSSalil Mehta tqp->q.ae_algo = &ae_algovf; 327e2cb1decSSalil Mehta tqp->q.buf_size = hdev->rx_buf_len; 328c0425944SPeng Li tqp->q.tx_desc_num = hdev->num_tx_desc; 329c0425944SPeng Li tqp->q.rx_desc_num = hdev->num_rx_desc; 330e2cb1decSSalil Mehta tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 331e2cb1decSSalil Mehta i * HCLGEVF_TQP_REG_SIZE; 332e2cb1decSSalil Mehta 333e2cb1decSSalil Mehta tqp++; 334e2cb1decSSalil Mehta } 335e2cb1decSSalil Mehta 336e2cb1decSSalil Mehta return 0; 337e2cb1decSSalil Mehta } 338e2cb1decSSalil Mehta 339e2cb1decSSalil Mehta static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 340e2cb1decSSalil Mehta { 341e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 342e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo; 343e2cb1decSSalil Mehta u16 new_tqps = hdev->num_tqps; 344e2cb1decSSalil Mehta int i; 345e2cb1decSSalil Mehta 346e2cb1decSSalil Mehta kinfo = &nic->kinfo; 347e2cb1decSSalil Mehta kinfo->num_tc = 0; 348c0425944SPeng Li kinfo->num_tx_desc = hdev->num_tx_desc; 349c0425944SPeng Li kinfo->num_rx_desc = hdev->num_rx_desc; 350e2cb1decSSalil Mehta kinfo->rx_buf_len = hdev->rx_buf_len; 351e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 352e2cb1decSSalil Mehta if (hdev->hw_tc_map & BIT(i)) 353e2cb1decSSalil Mehta kinfo->num_tc++; 354e2cb1decSSalil Mehta 355e2cb1decSSalil Mehta kinfo->rss_size 356e2cb1decSSalil Mehta = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 357e2cb1decSSalil Mehta new_tqps = kinfo->rss_size * kinfo->num_tc; 358e2cb1decSSalil Mehta kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 359e2cb1decSSalil Mehta 360e2cb1decSSalil Mehta kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 361e2cb1decSSalil Mehta sizeof(struct hnae3_queue *), GFP_KERNEL); 362e2cb1decSSalil Mehta if (!kinfo->tqp) 363e2cb1decSSalil Mehta return -ENOMEM; 364e2cb1decSSalil Mehta 365e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 366e2cb1decSSalil Mehta hdev->htqp[i].q.handle = &hdev->nic; 367e2cb1decSSalil Mehta hdev->htqp[i].q.tqp_index = i; 368e2cb1decSSalil Mehta kinfo->tqp[i] = &hdev->htqp[i].q; 369e2cb1decSSalil Mehta } 370e2cb1decSSalil Mehta 371e2cb1decSSalil Mehta return 0; 372e2cb1decSSalil Mehta } 373e2cb1decSSalil Mehta 374e2cb1decSSalil Mehta static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 375e2cb1decSSalil Mehta { 376e2cb1decSSalil Mehta int status; 377e2cb1decSSalil Mehta u8 resp_msg; 378e2cb1decSSalil Mehta 379e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 380e2cb1decSSalil Mehta 0, false, &resp_msg, sizeof(u8)); 381e2cb1decSSalil Mehta if (status) 382e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 383e2cb1decSSalil Mehta "VF failed to fetch link status(%d) from PF", status); 384e2cb1decSSalil Mehta } 385e2cb1decSSalil Mehta 386e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 387e2cb1decSSalil Mehta { 38845e92b7eSPeng Li struct hnae3_handle *rhandle = &hdev->roce; 389e2cb1decSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 39045e92b7eSPeng Li struct hnae3_client *rclient; 391e2cb1decSSalil Mehta struct hnae3_client *client; 392e2cb1decSSalil Mehta 393e2cb1decSSalil Mehta client = handle->client; 39445e92b7eSPeng Li rclient = hdev->roce_client; 395e2cb1decSSalil Mehta 396582d37bbSPeng Li link_state = 397582d37bbSPeng Li test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 398582d37bbSPeng Li 399e2cb1decSSalil Mehta if (link_state != hdev->hw.mac.link) { 400e2cb1decSSalil Mehta client->ops->link_status_change(handle, !!link_state); 40145e92b7eSPeng Li if (rclient && rclient->ops->link_status_change) 40245e92b7eSPeng Li rclient->ops->link_status_change(rhandle, !!link_state); 403e2cb1decSSalil Mehta hdev->hw.mac.link = link_state; 404e2cb1decSSalil Mehta } 405e2cb1decSSalil Mehta } 406e2cb1decSSalil Mehta 4079194d18bSliuzhongzhu void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 4089194d18bSliuzhongzhu { 4099194d18bSliuzhongzhu #define HCLGEVF_ADVERTISING 0 4109194d18bSliuzhongzhu #define HCLGEVF_SUPPORTED 1 4119194d18bSliuzhongzhu u8 send_msg; 4129194d18bSliuzhongzhu u8 resp_msg; 4139194d18bSliuzhongzhu 4149194d18bSliuzhongzhu send_msg = HCLGEVF_ADVERTISING; 4159194d18bSliuzhongzhu hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, &send_msg, 4169194d18bSliuzhongzhu sizeof(u8), false, &resp_msg, sizeof(u8)); 4179194d18bSliuzhongzhu send_msg = HCLGEVF_SUPPORTED; 4189194d18bSliuzhongzhu hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, &send_msg, 4199194d18bSliuzhongzhu sizeof(u8), false, &resp_msg, sizeof(u8)); 4209194d18bSliuzhongzhu } 4219194d18bSliuzhongzhu 422e2cb1decSSalil Mehta static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 423e2cb1decSSalil Mehta { 424e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 425e2cb1decSSalil Mehta int ret; 426e2cb1decSSalil Mehta 427e2cb1decSSalil Mehta nic->ae_algo = &ae_algovf; 428e2cb1decSSalil Mehta nic->pdev = hdev->pdev; 429e2cb1decSSalil Mehta nic->numa_node_mask = hdev->numa_node_mask; 430424eb834SSalil Mehta nic->flags |= HNAE3_SUPPORT_VF; 431e2cb1decSSalil Mehta 432e2cb1decSSalil Mehta if (hdev->ae_dev->dev_type != HNAE3_DEV_KNIC) { 433e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "unsupported device type %d\n", 434e2cb1decSSalil Mehta hdev->ae_dev->dev_type); 435e2cb1decSSalil Mehta return -EINVAL; 436e2cb1decSSalil Mehta } 437e2cb1decSSalil Mehta 438e2cb1decSSalil Mehta ret = hclgevf_knic_setup(hdev); 439e2cb1decSSalil Mehta if (ret) 440e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 441e2cb1decSSalil Mehta ret); 442e2cb1decSSalil Mehta return ret; 443e2cb1decSSalil Mehta } 444e2cb1decSSalil Mehta 445e2cb1decSSalil Mehta static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 446e2cb1decSSalil Mehta { 44736cbbdf6SPeng Li if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 44836cbbdf6SPeng Li dev_warn(&hdev->pdev->dev, 44936cbbdf6SPeng Li "vector(vector_id %d) has been freed.\n", vector_id); 45036cbbdf6SPeng Li return; 45136cbbdf6SPeng Li } 45236cbbdf6SPeng Li 453e2cb1decSSalil Mehta hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 454e2cb1decSSalil Mehta hdev->num_msi_left += 1; 455e2cb1decSSalil Mehta hdev->num_msi_used -= 1; 456e2cb1decSSalil Mehta } 457e2cb1decSSalil Mehta 458e2cb1decSSalil Mehta static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 459e2cb1decSSalil Mehta struct hnae3_vector_info *vector_info) 460e2cb1decSSalil Mehta { 461e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 462e2cb1decSSalil Mehta struct hnae3_vector_info *vector = vector_info; 463e2cb1decSSalil Mehta int alloc = 0; 464e2cb1decSSalil Mehta int i, j; 465e2cb1decSSalil Mehta 466e2cb1decSSalil Mehta vector_num = min(hdev->num_msi_left, vector_num); 467e2cb1decSSalil Mehta 468e2cb1decSSalil Mehta for (j = 0; j < vector_num; j++) { 469e2cb1decSSalil Mehta for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 470e2cb1decSSalil Mehta if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 471e2cb1decSSalil Mehta vector->vector = pci_irq_vector(hdev->pdev, i); 472e2cb1decSSalil Mehta vector->io_addr = hdev->hw.io_base + 473e2cb1decSSalil Mehta HCLGEVF_VECTOR_REG_BASE + 474e2cb1decSSalil Mehta (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 475e2cb1decSSalil Mehta hdev->vector_status[i] = 0; 476e2cb1decSSalil Mehta hdev->vector_irq[i] = vector->vector; 477e2cb1decSSalil Mehta 478e2cb1decSSalil Mehta vector++; 479e2cb1decSSalil Mehta alloc++; 480e2cb1decSSalil Mehta 481e2cb1decSSalil Mehta break; 482e2cb1decSSalil Mehta } 483e2cb1decSSalil Mehta } 484e2cb1decSSalil Mehta } 485e2cb1decSSalil Mehta hdev->num_msi_left -= alloc; 486e2cb1decSSalil Mehta hdev->num_msi_used += alloc; 487e2cb1decSSalil Mehta 488e2cb1decSSalil Mehta return alloc; 489e2cb1decSSalil Mehta } 490e2cb1decSSalil Mehta 491e2cb1decSSalil Mehta static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 492e2cb1decSSalil Mehta { 493e2cb1decSSalil Mehta int i; 494e2cb1decSSalil Mehta 495e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 496e2cb1decSSalil Mehta if (vector == hdev->vector_irq[i]) 497e2cb1decSSalil Mehta return i; 498e2cb1decSSalil Mehta 499e2cb1decSSalil Mehta return -EINVAL; 500e2cb1decSSalil Mehta } 501e2cb1decSSalil Mehta 502374ad291SJian Shen static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 503374ad291SJian Shen const u8 hfunc, const u8 *key) 504374ad291SJian Shen { 505374ad291SJian Shen struct hclgevf_rss_config_cmd *req; 506374ad291SJian Shen struct hclgevf_desc desc; 507374ad291SJian Shen int key_offset; 508374ad291SJian Shen int key_size; 509374ad291SJian Shen int ret; 510374ad291SJian Shen 511374ad291SJian Shen req = (struct hclgevf_rss_config_cmd *)desc.data; 512374ad291SJian Shen 513374ad291SJian Shen for (key_offset = 0; key_offset < 3; key_offset++) { 514374ad291SJian Shen hclgevf_cmd_setup_basic_desc(&desc, 515374ad291SJian Shen HCLGEVF_OPC_RSS_GENERIC_CONFIG, 516374ad291SJian Shen false); 517374ad291SJian Shen 518374ad291SJian Shen req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 519374ad291SJian Shen req->hash_config |= 520374ad291SJian Shen (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 521374ad291SJian Shen 522374ad291SJian Shen if (key_offset == 2) 523374ad291SJian Shen key_size = 524374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE - HCLGEVF_RSS_HASH_KEY_NUM * 2; 525374ad291SJian Shen else 526374ad291SJian Shen key_size = HCLGEVF_RSS_HASH_KEY_NUM; 527374ad291SJian Shen 528374ad291SJian Shen memcpy(req->hash_key, 529374ad291SJian Shen key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 530374ad291SJian Shen 531374ad291SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 532374ad291SJian Shen if (ret) { 533374ad291SJian Shen dev_err(&hdev->pdev->dev, 534374ad291SJian Shen "Configure RSS config fail, status = %d\n", 535374ad291SJian Shen ret); 536374ad291SJian Shen return ret; 537374ad291SJian Shen } 538374ad291SJian Shen } 539374ad291SJian Shen 540374ad291SJian Shen return 0; 541374ad291SJian Shen } 542374ad291SJian Shen 543e2cb1decSSalil Mehta static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 544e2cb1decSSalil Mehta { 545e2cb1decSSalil Mehta return HCLGEVF_RSS_KEY_SIZE; 546e2cb1decSSalil Mehta } 547e2cb1decSSalil Mehta 548e2cb1decSSalil Mehta static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 549e2cb1decSSalil Mehta { 550e2cb1decSSalil Mehta return HCLGEVF_RSS_IND_TBL_SIZE; 551e2cb1decSSalil Mehta } 552e2cb1decSSalil Mehta 553e2cb1decSSalil Mehta static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 554e2cb1decSSalil Mehta { 555e2cb1decSSalil Mehta const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 556e2cb1decSSalil Mehta struct hclgevf_rss_indirection_table_cmd *req; 557e2cb1decSSalil Mehta struct hclgevf_desc desc; 558e2cb1decSSalil Mehta int status; 559e2cb1decSSalil Mehta int i, j; 560e2cb1decSSalil Mehta 561e2cb1decSSalil Mehta req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 562e2cb1decSSalil Mehta 563e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 564e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 565e2cb1decSSalil Mehta false); 566e2cb1decSSalil Mehta req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 567e2cb1decSSalil Mehta req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 568e2cb1decSSalil Mehta for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 569e2cb1decSSalil Mehta req->rss_result[j] = 570e2cb1decSSalil Mehta indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 571e2cb1decSSalil Mehta 572e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 573e2cb1decSSalil Mehta if (status) { 574e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 575e2cb1decSSalil Mehta "VF failed(=%d) to set RSS indirection table\n", 576e2cb1decSSalil Mehta status); 577e2cb1decSSalil Mehta return status; 578e2cb1decSSalil Mehta } 579e2cb1decSSalil Mehta } 580e2cb1decSSalil Mehta 581e2cb1decSSalil Mehta return 0; 582e2cb1decSSalil Mehta } 583e2cb1decSSalil Mehta 584e2cb1decSSalil Mehta static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 585e2cb1decSSalil Mehta { 586e2cb1decSSalil Mehta struct hclgevf_rss_tc_mode_cmd *req; 587e2cb1decSSalil Mehta u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 588e2cb1decSSalil Mehta u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 589e2cb1decSSalil Mehta u16 tc_size[HCLGEVF_MAX_TC_NUM]; 590e2cb1decSSalil Mehta struct hclgevf_desc desc; 591e2cb1decSSalil Mehta u16 roundup_size; 592e2cb1decSSalil Mehta int status; 593e2cb1decSSalil Mehta int i; 594e2cb1decSSalil Mehta 595e2cb1decSSalil Mehta req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 596e2cb1decSSalil Mehta 597e2cb1decSSalil Mehta roundup_size = roundup_pow_of_two(rss_size); 598e2cb1decSSalil Mehta roundup_size = ilog2(roundup_size); 599e2cb1decSSalil Mehta 600e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 601e2cb1decSSalil Mehta tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 602e2cb1decSSalil Mehta tc_size[i] = roundup_size; 603e2cb1decSSalil Mehta tc_offset[i] = rss_size * i; 604e2cb1decSSalil Mehta } 605e2cb1decSSalil Mehta 606e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 607e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 608e4e87715SPeng Li hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 609e2cb1decSSalil Mehta (tc_valid[i] & 0x1)); 610e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 611e2cb1decSSalil Mehta HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 612e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 613e2cb1decSSalil Mehta HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 614e2cb1decSSalil Mehta } 615e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 616e2cb1decSSalil Mehta if (status) 617e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 618e2cb1decSSalil Mehta "VF failed(=%d) to set rss tc mode\n", status); 619e2cb1decSSalil Mehta 620e2cb1decSSalil Mehta return status; 621e2cb1decSSalil Mehta } 622e2cb1decSSalil Mehta 623e2cb1decSSalil Mehta static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 624e2cb1decSSalil Mehta u8 *hfunc) 625e2cb1decSSalil Mehta { 626e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 627e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 628e2cb1decSSalil Mehta int i; 629e2cb1decSSalil Mehta 630374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 631374ad291SJian Shen /* Get hash algorithm */ 632374ad291SJian Shen if (hfunc) { 633374ad291SJian Shen switch (rss_cfg->hash_algo) { 634374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 635374ad291SJian Shen *hfunc = ETH_RSS_HASH_TOP; 636374ad291SJian Shen break; 637374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 638374ad291SJian Shen *hfunc = ETH_RSS_HASH_XOR; 639374ad291SJian Shen break; 640374ad291SJian Shen default: 641374ad291SJian Shen *hfunc = ETH_RSS_HASH_UNKNOWN; 642374ad291SJian Shen break; 643374ad291SJian Shen } 644374ad291SJian Shen } 645374ad291SJian Shen 646374ad291SJian Shen /* Get the RSS Key required by the user */ 647374ad291SJian Shen if (key) 648374ad291SJian Shen memcpy(key, rss_cfg->rss_hash_key, 649374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 650374ad291SJian Shen } 651374ad291SJian Shen 652e2cb1decSSalil Mehta if (indir) 653e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 654e2cb1decSSalil Mehta indir[i] = rss_cfg->rss_indirection_tbl[i]; 655e2cb1decSSalil Mehta 656374ad291SJian Shen return 0; 657e2cb1decSSalil Mehta } 658e2cb1decSSalil Mehta 659e2cb1decSSalil Mehta static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 660e2cb1decSSalil Mehta const u8 *key, const u8 hfunc) 661e2cb1decSSalil Mehta { 662e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 663e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 664374ad291SJian Shen int ret, i; 665374ad291SJian Shen 666374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 667374ad291SJian Shen /* Set the RSS Hash Key if specififed by the user */ 668374ad291SJian Shen if (key) { 669374ad291SJian Shen switch (hfunc) { 670374ad291SJian Shen case ETH_RSS_HASH_TOP: 671374ad291SJian Shen rss_cfg->hash_algo = 672374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 673374ad291SJian Shen break; 674374ad291SJian Shen case ETH_RSS_HASH_XOR: 675374ad291SJian Shen rss_cfg->hash_algo = 676374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_SIMPLE; 677374ad291SJian Shen break; 678374ad291SJian Shen case ETH_RSS_HASH_NO_CHANGE: 679374ad291SJian Shen break; 680374ad291SJian Shen default: 681374ad291SJian Shen return -EINVAL; 682374ad291SJian Shen } 683374ad291SJian Shen 684374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 685374ad291SJian Shen key); 686374ad291SJian Shen if (ret) 687374ad291SJian Shen return ret; 688374ad291SJian Shen 689374ad291SJian Shen /* Update the shadow RSS key with user specified qids */ 690374ad291SJian Shen memcpy(rss_cfg->rss_hash_key, key, 691374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 692374ad291SJian Shen } 693374ad291SJian Shen } 694e2cb1decSSalil Mehta 695e2cb1decSSalil Mehta /* update the shadow RSS table with user specified qids */ 696e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 697e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = indir[i]; 698e2cb1decSSalil Mehta 699e2cb1decSSalil Mehta /* update the hardware */ 700e2cb1decSSalil Mehta return hclgevf_set_rss_indir_table(hdev); 701e2cb1decSSalil Mehta } 702e2cb1decSSalil Mehta 703d97b3072SJian Shen static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 704d97b3072SJian Shen { 705d97b3072SJian Shen u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 706d97b3072SJian Shen 707d97b3072SJian Shen if (nfc->data & RXH_L4_B_2_3) 708d97b3072SJian Shen hash_sets |= HCLGEVF_D_PORT_BIT; 709d97b3072SJian Shen else 710d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_PORT_BIT; 711d97b3072SJian Shen 712d97b3072SJian Shen if (nfc->data & RXH_IP_SRC) 713d97b3072SJian Shen hash_sets |= HCLGEVF_S_IP_BIT; 714d97b3072SJian Shen else 715d97b3072SJian Shen hash_sets &= ~HCLGEVF_S_IP_BIT; 716d97b3072SJian Shen 717d97b3072SJian Shen if (nfc->data & RXH_IP_DST) 718d97b3072SJian Shen hash_sets |= HCLGEVF_D_IP_BIT; 719d97b3072SJian Shen else 720d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_IP_BIT; 721d97b3072SJian Shen 722d97b3072SJian Shen if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 723d97b3072SJian Shen hash_sets |= HCLGEVF_V_TAG_BIT; 724d97b3072SJian Shen 725d97b3072SJian Shen return hash_sets; 726d97b3072SJian Shen } 727d97b3072SJian Shen 728d97b3072SJian Shen static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 729d97b3072SJian Shen struct ethtool_rxnfc *nfc) 730d97b3072SJian Shen { 731d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 732d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 733d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 734d97b3072SJian Shen struct hclgevf_desc desc; 735d97b3072SJian Shen u8 tuple_sets; 736d97b3072SJian Shen int ret; 737d97b3072SJian Shen 738d97b3072SJian Shen if (handle->pdev->revision == 0x20) 739d97b3072SJian Shen return -EOPNOTSUPP; 740d97b3072SJian Shen 741d97b3072SJian Shen if (nfc->data & 742d97b3072SJian Shen ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 743d97b3072SJian Shen return -EINVAL; 744d97b3072SJian Shen 745d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 746d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 747d97b3072SJian Shen 748d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 749d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 750d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 751d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 752d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 753d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 754d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 755d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 756d97b3072SJian Shen 757d97b3072SJian Shen tuple_sets = hclgevf_get_rss_hash_bits(nfc); 758d97b3072SJian Shen switch (nfc->flow_type) { 759d97b3072SJian Shen case TCP_V4_FLOW: 760d97b3072SJian Shen req->ipv4_tcp_en = tuple_sets; 761d97b3072SJian Shen break; 762d97b3072SJian Shen case TCP_V6_FLOW: 763d97b3072SJian Shen req->ipv6_tcp_en = tuple_sets; 764d97b3072SJian Shen break; 765d97b3072SJian Shen case UDP_V4_FLOW: 766d97b3072SJian Shen req->ipv4_udp_en = tuple_sets; 767d97b3072SJian Shen break; 768d97b3072SJian Shen case UDP_V6_FLOW: 769d97b3072SJian Shen req->ipv6_udp_en = tuple_sets; 770d97b3072SJian Shen break; 771d97b3072SJian Shen case SCTP_V4_FLOW: 772d97b3072SJian Shen req->ipv4_sctp_en = tuple_sets; 773d97b3072SJian Shen break; 774d97b3072SJian Shen case SCTP_V6_FLOW: 775d97b3072SJian Shen if ((nfc->data & RXH_L4_B_0_1) || 776d97b3072SJian Shen (nfc->data & RXH_L4_B_2_3)) 777d97b3072SJian Shen return -EINVAL; 778d97b3072SJian Shen 779d97b3072SJian Shen req->ipv6_sctp_en = tuple_sets; 780d97b3072SJian Shen break; 781d97b3072SJian Shen case IPV4_FLOW: 782d97b3072SJian Shen req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 783d97b3072SJian Shen break; 784d97b3072SJian Shen case IPV6_FLOW: 785d97b3072SJian Shen req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 786d97b3072SJian Shen break; 787d97b3072SJian Shen default: 788d97b3072SJian Shen return -EINVAL; 789d97b3072SJian Shen } 790d97b3072SJian Shen 791d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 792d97b3072SJian Shen if (ret) { 793d97b3072SJian Shen dev_err(&hdev->pdev->dev, 794d97b3072SJian Shen "Set rss tuple fail, status = %d\n", ret); 795d97b3072SJian Shen return ret; 796d97b3072SJian Shen } 797d97b3072SJian Shen 798d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 799d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 800d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 801d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 802d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 803d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 804d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 805d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 806d97b3072SJian Shen return 0; 807d97b3072SJian Shen } 808d97b3072SJian Shen 809d97b3072SJian Shen static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 810d97b3072SJian Shen struct ethtool_rxnfc *nfc) 811d97b3072SJian Shen { 812d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 813d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 814d97b3072SJian Shen u8 tuple_sets; 815d97b3072SJian Shen 816d97b3072SJian Shen if (handle->pdev->revision == 0x20) 817d97b3072SJian Shen return -EOPNOTSUPP; 818d97b3072SJian Shen 819d97b3072SJian Shen nfc->data = 0; 820d97b3072SJian Shen 821d97b3072SJian Shen switch (nfc->flow_type) { 822d97b3072SJian Shen case TCP_V4_FLOW: 823d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 824d97b3072SJian Shen break; 825d97b3072SJian Shen case UDP_V4_FLOW: 826d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 827d97b3072SJian Shen break; 828d97b3072SJian Shen case TCP_V6_FLOW: 829d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 830d97b3072SJian Shen break; 831d97b3072SJian Shen case UDP_V6_FLOW: 832d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 833d97b3072SJian Shen break; 834d97b3072SJian Shen case SCTP_V4_FLOW: 835d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 836d97b3072SJian Shen break; 837d97b3072SJian Shen case SCTP_V6_FLOW: 838d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 839d97b3072SJian Shen break; 840d97b3072SJian Shen case IPV4_FLOW: 841d97b3072SJian Shen case IPV6_FLOW: 842d97b3072SJian Shen tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 843d97b3072SJian Shen break; 844d97b3072SJian Shen default: 845d97b3072SJian Shen return -EINVAL; 846d97b3072SJian Shen } 847d97b3072SJian Shen 848d97b3072SJian Shen if (!tuple_sets) 849d97b3072SJian Shen return 0; 850d97b3072SJian Shen 851d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_PORT_BIT) 852d97b3072SJian Shen nfc->data |= RXH_L4_B_2_3; 853d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_PORT_BIT) 854d97b3072SJian Shen nfc->data |= RXH_L4_B_0_1; 855d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_IP_BIT) 856d97b3072SJian Shen nfc->data |= RXH_IP_DST; 857d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_IP_BIT) 858d97b3072SJian Shen nfc->data |= RXH_IP_SRC; 859d97b3072SJian Shen 860d97b3072SJian Shen return 0; 861d97b3072SJian Shen } 862d97b3072SJian Shen 863d97b3072SJian Shen static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 864d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg) 865d97b3072SJian Shen { 866d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 867d97b3072SJian Shen struct hclgevf_desc desc; 868d97b3072SJian Shen int ret; 869d97b3072SJian Shen 870d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 871d97b3072SJian Shen 872d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 873d97b3072SJian Shen 874d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 875d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 876d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 877d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 878d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 879d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 880d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 881d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 882d97b3072SJian Shen 883d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 884d97b3072SJian Shen if (ret) 885d97b3072SJian Shen dev_err(&hdev->pdev->dev, 886d97b3072SJian Shen "Configure rss input fail, status = %d\n", ret); 887d97b3072SJian Shen return ret; 888d97b3072SJian Shen } 889d97b3072SJian Shen 890e2cb1decSSalil Mehta static int hclgevf_get_tc_size(struct hnae3_handle *handle) 891e2cb1decSSalil Mehta { 892e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 893e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 894e2cb1decSSalil Mehta 895e2cb1decSSalil Mehta return rss_cfg->rss_size; 896e2cb1decSSalil Mehta } 897e2cb1decSSalil Mehta 898e2cb1decSSalil Mehta static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 899b204bc74SPeng Li int vector_id, 900e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 901e2cb1decSSalil Mehta { 902e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 903e2cb1decSSalil Mehta struct hnae3_ring_chain_node *node; 904e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 905e2cb1decSSalil Mehta struct hclgevf_desc desc; 906b204bc74SPeng Li int i = 0; 907e2cb1decSSalil Mehta int status; 908e2cb1decSSalil Mehta u8 type; 909e2cb1decSSalil Mehta 910e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 911e2cb1decSSalil Mehta 912e2cb1decSSalil Mehta for (node = ring_chain; node; node = node->next) { 9135d02a58dSYunsheng Lin int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 9145d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 9155d02a58dSYunsheng Lin 9165d02a58dSYunsheng Lin if (i == 0) { 9175d02a58dSYunsheng Lin hclgevf_cmd_setup_basic_desc(&desc, 9185d02a58dSYunsheng Lin HCLGEVF_OPC_MBX_VF_TO_PF, 9195d02a58dSYunsheng Lin false); 9205d02a58dSYunsheng Lin type = en ? 9215d02a58dSYunsheng Lin HCLGE_MBX_MAP_RING_TO_VECTOR : 9225d02a58dSYunsheng Lin HCLGE_MBX_UNMAP_RING_TO_VECTOR; 9235d02a58dSYunsheng Lin req->msg[0] = type; 9245d02a58dSYunsheng Lin req->msg[1] = vector_id; 9255d02a58dSYunsheng Lin } 9265d02a58dSYunsheng Lin 9275d02a58dSYunsheng Lin req->msg[idx_offset] = 928e4e87715SPeng Li hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 9295d02a58dSYunsheng Lin req->msg[idx_offset + 1] = node->tqp_index; 930e4e87715SPeng Li req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 93179eee410SFuyun Liang HNAE3_RING_GL_IDX_M, 93279eee410SFuyun Liang HNAE3_RING_GL_IDX_S); 93379eee410SFuyun Liang 9345d02a58dSYunsheng Lin i++; 9355d02a58dSYunsheng Lin if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 9365d02a58dSYunsheng Lin HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 9375d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 9385d02a58dSYunsheng Lin !node->next) { 939e2cb1decSSalil Mehta req->msg[2] = i; 940e2cb1decSSalil Mehta 941e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 942e2cb1decSSalil Mehta if (status) { 943e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 944e2cb1decSSalil Mehta "Map TQP fail, status is %d.\n", 945e2cb1decSSalil Mehta status); 946e2cb1decSSalil Mehta return status; 947e2cb1decSSalil Mehta } 948e2cb1decSSalil Mehta i = 0; 949e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 950e2cb1decSSalil Mehta HCLGEVF_OPC_MBX_VF_TO_PF, 951e2cb1decSSalil Mehta false); 952e2cb1decSSalil Mehta req->msg[0] = type; 953e2cb1decSSalil Mehta req->msg[1] = vector_id; 954e2cb1decSSalil Mehta } 955e2cb1decSSalil Mehta } 956e2cb1decSSalil Mehta 957e2cb1decSSalil Mehta return 0; 958e2cb1decSSalil Mehta } 959e2cb1decSSalil Mehta 960e2cb1decSSalil Mehta static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 961e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 962e2cb1decSSalil Mehta { 963b204bc74SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 964b204bc74SPeng Li int vector_id; 965b204bc74SPeng Li 966b204bc74SPeng Li vector_id = hclgevf_get_vector_index(hdev, vector); 967b204bc74SPeng Li if (vector_id < 0) { 968b204bc74SPeng Li dev_err(&handle->pdev->dev, 969b204bc74SPeng Li "Get vector index fail. ret =%d\n", vector_id); 970b204bc74SPeng Li return vector_id; 971b204bc74SPeng Li } 972b204bc74SPeng Li 973b204bc74SPeng Li return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 974e2cb1decSSalil Mehta } 975e2cb1decSSalil Mehta 976e2cb1decSSalil Mehta static int hclgevf_unmap_ring_from_vector( 977e2cb1decSSalil Mehta struct hnae3_handle *handle, 978e2cb1decSSalil Mehta int vector, 979e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 980e2cb1decSSalil Mehta { 981e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 982e2cb1decSSalil Mehta int ret, vector_id; 983e2cb1decSSalil Mehta 984dea846e8SHuazhong Tan if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 985dea846e8SHuazhong Tan return 0; 986dea846e8SHuazhong Tan 987e2cb1decSSalil Mehta vector_id = hclgevf_get_vector_index(hdev, vector); 988e2cb1decSSalil Mehta if (vector_id < 0) { 989e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 990e2cb1decSSalil Mehta "Get vector index fail. ret =%d\n", vector_id); 991e2cb1decSSalil Mehta return vector_id; 992e2cb1decSSalil Mehta } 993e2cb1decSSalil Mehta 994b204bc74SPeng Li ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 9950d3e6631SYunsheng Lin if (ret) 996e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 997e2cb1decSSalil Mehta "Unmap ring from vector fail. vector=%d, ret =%d\n", 998e2cb1decSSalil Mehta vector_id, 999e2cb1decSSalil Mehta ret); 10000d3e6631SYunsheng Lin 1001e2cb1decSSalil Mehta return ret; 1002e2cb1decSSalil Mehta } 1003e2cb1decSSalil Mehta 10040d3e6631SYunsheng Lin static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 10050d3e6631SYunsheng Lin { 10060d3e6631SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 100703718db9SYunsheng Lin int vector_id; 10080d3e6631SYunsheng Lin 100903718db9SYunsheng Lin vector_id = hclgevf_get_vector_index(hdev, vector); 101003718db9SYunsheng Lin if (vector_id < 0) { 101103718db9SYunsheng Lin dev_err(&handle->pdev->dev, 101203718db9SYunsheng Lin "hclgevf_put_vector get vector index fail. ret =%d\n", 101303718db9SYunsheng Lin vector_id); 101403718db9SYunsheng Lin return vector_id; 101503718db9SYunsheng Lin } 101603718db9SYunsheng Lin 101703718db9SYunsheng Lin hclgevf_free_vector(hdev, vector_id); 1018e2cb1decSSalil Mehta 1019e2cb1decSSalil Mehta return 0; 1020e2cb1decSSalil Mehta } 1021e2cb1decSSalil Mehta 10223b75c3dfSPeng Li static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1023f01f5559SJian Shen bool en_bc_pmc) 1024e2cb1decSSalil Mehta { 1025e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 1026e2cb1decSSalil Mehta struct hclgevf_desc desc; 1027f01f5559SJian Shen int ret; 1028e2cb1decSSalil Mehta 1029e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1030e2cb1decSSalil Mehta 1031e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 1032e2cb1decSSalil Mehta req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 1033f01f5559SJian Shen req->msg[1] = en_bc_pmc ? 1 : 0; 1034e2cb1decSSalil Mehta 1035f01f5559SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1036f01f5559SJian Shen if (ret) 1037e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1038f01f5559SJian Shen "Set promisc mode fail, status is %d.\n", ret); 1039e2cb1decSSalil Mehta 1040f01f5559SJian Shen return ret; 1041e2cb1decSSalil Mehta } 1042e2cb1decSSalil Mehta 1043f01f5559SJian Shen static int hclgevf_set_promisc_mode(struct hclgevf_dev *hdev, bool en_bc_pmc) 1044e2cb1decSSalil Mehta { 1045f01f5559SJian Shen return hclgevf_cmd_set_promisc_mode(hdev, en_bc_pmc); 1046e2cb1decSSalil Mehta } 1047e2cb1decSSalil Mehta 1048e2cb1decSSalil Mehta static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, int tqp_id, 1049e2cb1decSSalil Mehta int stream_id, bool enable) 1050e2cb1decSSalil Mehta { 1051e2cb1decSSalil Mehta struct hclgevf_cfg_com_tqp_queue_cmd *req; 1052e2cb1decSSalil Mehta struct hclgevf_desc desc; 1053e2cb1decSSalil Mehta int status; 1054e2cb1decSSalil Mehta 1055e2cb1decSSalil Mehta req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1056e2cb1decSSalil Mehta 1057e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1058e2cb1decSSalil Mehta false); 1059e2cb1decSSalil Mehta req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1060e2cb1decSSalil Mehta req->stream_id = cpu_to_le16(stream_id); 1061e2cb1decSSalil Mehta req->enable |= enable << HCLGEVF_TQP_ENABLE_B; 1062e2cb1decSSalil Mehta 1063e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1064e2cb1decSSalil Mehta if (status) 1065e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1066e2cb1decSSalil Mehta "TQP enable fail, status =%d.\n", status); 1067e2cb1decSSalil Mehta 1068e2cb1decSSalil Mehta return status; 1069e2cb1decSSalil Mehta } 1070e2cb1decSSalil Mehta 1071e2cb1decSSalil Mehta static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1072e2cb1decSSalil Mehta { 1073b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1074e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 1075e2cb1decSSalil Mehta int i; 1076e2cb1decSSalil Mehta 1077b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 1078b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1079e2cb1decSSalil Mehta memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1080e2cb1decSSalil Mehta } 1081e2cb1decSSalil Mehta } 1082e2cb1decSSalil Mehta 1083e2cb1decSSalil Mehta static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1084e2cb1decSSalil Mehta { 1085e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1086e2cb1decSSalil Mehta 1087e2cb1decSSalil Mehta ether_addr_copy(p, hdev->hw.mac.mac_addr); 1088e2cb1decSSalil Mehta } 1089e2cb1decSSalil Mehta 109059098055SFuyun Liang static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 109159098055SFuyun Liang bool is_first) 1092e2cb1decSSalil Mehta { 1093e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1094e2cb1decSSalil Mehta u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1095e2cb1decSSalil Mehta u8 *new_mac_addr = (u8 *)p; 1096e2cb1decSSalil Mehta u8 msg_data[ETH_ALEN * 2]; 109759098055SFuyun Liang u16 subcode; 1098e2cb1decSSalil Mehta int status; 1099e2cb1decSSalil Mehta 1100e2cb1decSSalil Mehta ether_addr_copy(msg_data, new_mac_addr); 1101e2cb1decSSalil Mehta ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 1102e2cb1decSSalil Mehta 110359098055SFuyun Liang subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 110459098055SFuyun Liang HCLGE_MBX_MAC_VLAN_UC_MODIFY; 110559098055SFuyun Liang 1106e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 110759098055SFuyun Liang subcode, msg_data, ETH_ALEN * 2, 11082097fdefSJian Shen true, NULL, 0); 1109e2cb1decSSalil Mehta if (!status) 1110e2cb1decSSalil Mehta ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1111e2cb1decSSalil Mehta 1112e2cb1decSSalil Mehta return status; 1113e2cb1decSSalil Mehta } 1114e2cb1decSSalil Mehta 1115e2cb1decSSalil Mehta static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1116e2cb1decSSalil Mehta const unsigned char *addr) 1117e2cb1decSSalil Mehta { 1118e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1119e2cb1decSSalil Mehta 1120e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1121e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_ADD, 1122e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1123e2cb1decSSalil Mehta } 1124e2cb1decSSalil Mehta 1125e2cb1decSSalil Mehta static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1126e2cb1decSSalil Mehta const unsigned char *addr) 1127e2cb1decSSalil Mehta { 1128e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1129e2cb1decSSalil Mehta 1130e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1131e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1132e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1133e2cb1decSSalil Mehta } 1134e2cb1decSSalil Mehta 1135e2cb1decSSalil Mehta static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1136e2cb1decSSalil Mehta const unsigned char *addr) 1137e2cb1decSSalil Mehta { 1138e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1139e2cb1decSSalil Mehta 1140e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1141e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_ADD, 1142e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1143e2cb1decSSalil Mehta } 1144e2cb1decSSalil Mehta 1145e2cb1decSSalil Mehta static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1146e2cb1decSSalil Mehta const unsigned char *addr) 1147e2cb1decSSalil Mehta { 1148e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1149e2cb1decSSalil Mehta 1150e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1151e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1152e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1153e2cb1decSSalil Mehta } 1154e2cb1decSSalil Mehta 1155e2cb1decSSalil Mehta static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1156e2cb1decSSalil Mehta __be16 proto, u16 vlan_id, 1157e2cb1decSSalil Mehta bool is_kill) 1158e2cb1decSSalil Mehta { 1159e2cb1decSSalil Mehta #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1160e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1161e2cb1decSSalil Mehta u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1162e2cb1decSSalil Mehta 1163e2cb1decSSalil Mehta if (vlan_id > 4095) 1164e2cb1decSSalil Mehta return -EINVAL; 1165e2cb1decSSalil Mehta 1166e2cb1decSSalil Mehta if (proto != htons(ETH_P_8021Q)) 1167e2cb1decSSalil Mehta return -EPROTONOSUPPORT; 1168e2cb1decSSalil Mehta 1169e2cb1decSSalil Mehta msg_data[0] = is_kill; 1170e2cb1decSSalil Mehta memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1171e2cb1decSSalil Mehta memcpy(&msg_data[3], &proto, sizeof(proto)); 1172e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1173e2cb1decSSalil Mehta HCLGE_MBX_VLAN_FILTER, msg_data, 1174e2cb1decSSalil Mehta HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 1175e2cb1decSSalil Mehta } 1176e2cb1decSSalil Mehta 1177b2641e2aSYunsheng Lin static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1178b2641e2aSYunsheng Lin { 1179b2641e2aSYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1180b2641e2aSYunsheng Lin u8 msg_data; 1181b2641e2aSYunsheng Lin 1182b2641e2aSYunsheng Lin msg_data = enable ? 1 : 0; 1183b2641e2aSYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1184b2641e2aSYunsheng Lin HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1185b2641e2aSYunsheng Lin 1, false, NULL, 0); 1186b2641e2aSYunsheng Lin } 1187b2641e2aSYunsheng Lin 11887fa6be4fSHuazhong Tan static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1189e2cb1decSSalil Mehta { 1190e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1191e2cb1decSSalil Mehta u8 msg_data[2]; 11921a426f8bSPeng Li int ret; 1193e2cb1decSSalil Mehta 1194e2cb1decSSalil Mehta memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 1195e2cb1decSSalil Mehta 11961a426f8bSPeng Li /* disable vf queue before send queue reset msg to PF */ 11971a426f8bSPeng Li ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 11981a426f8bSPeng Li if (ret) 11997fa6be4fSHuazhong Tan return ret; 12001a426f8bSPeng Li 12017fa6be4fSHuazhong Tan return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 12021a426f8bSPeng Li 2, true, NULL, 0); 1203e2cb1decSSalil Mehta } 1204e2cb1decSSalil Mehta 1205818f1675SYunsheng Lin static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1206818f1675SYunsheng Lin { 1207818f1675SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1208818f1675SYunsheng Lin 1209818f1675SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu, 1210818f1675SYunsheng Lin sizeof(new_mtu), true, NULL, 0); 1211818f1675SYunsheng Lin } 1212818f1675SYunsheng Lin 12136988eb2aSSalil Mehta static int hclgevf_notify_client(struct hclgevf_dev *hdev, 12146988eb2aSSalil Mehta enum hnae3_reset_notify_type type) 12156988eb2aSSalil Mehta { 12166988eb2aSSalil Mehta struct hnae3_client *client = hdev->nic_client; 12176988eb2aSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 12186a5f6fa3SHuazhong Tan int ret; 12196988eb2aSSalil Mehta 12206988eb2aSSalil Mehta if (!client->ops->reset_notify) 12216988eb2aSSalil Mehta return -EOPNOTSUPP; 12226988eb2aSSalil Mehta 12236a5f6fa3SHuazhong Tan ret = client->ops->reset_notify(handle, type); 12246a5f6fa3SHuazhong Tan if (ret) 12256a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 12266a5f6fa3SHuazhong Tan type, ret); 12276a5f6fa3SHuazhong Tan 12286a5f6fa3SHuazhong Tan return ret; 12296988eb2aSSalil Mehta } 12306988eb2aSSalil Mehta 12316ff3cf07SHuazhong Tan static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 12326ff3cf07SHuazhong Tan { 12336ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 12346ff3cf07SHuazhong Tan 12356ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DONE, &hdev->flr_state); 12366ff3cf07SHuazhong Tan } 12376ff3cf07SHuazhong Tan 12386ff3cf07SHuazhong Tan static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev, 12396ff3cf07SHuazhong Tan unsigned long delay_us, 12406ff3cf07SHuazhong Tan unsigned long wait_cnt) 12416ff3cf07SHuazhong Tan { 12426ff3cf07SHuazhong Tan unsigned long cnt = 0; 12436ff3cf07SHuazhong Tan 12446ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) && 12456ff3cf07SHuazhong Tan cnt++ < wait_cnt) 12466ff3cf07SHuazhong Tan usleep_range(delay_us, delay_us * 2); 12476ff3cf07SHuazhong Tan 12486ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) { 12496ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 12506ff3cf07SHuazhong Tan "flr wait timeout\n"); 12516ff3cf07SHuazhong Tan return -ETIMEDOUT; 12526ff3cf07SHuazhong Tan } 12536ff3cf07SHuazhong Tan 12546ff3cf07SHuazhong Tan return 0; 12556ff3cf07SHuazhong Tan } 12566ff3cf07SHuazhong Tan 12576988eb2aSSalil Mehta static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 12586988eb2aSSalil Mehta { 1259aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_US 20000 1260aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_CNT 2000 1261aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1262aa5c4f17SHuazhong Tan (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1263aa5c4f17SHuazhong Tan 1264aa5c4f17SHuazhong Tan u32 val; 1265aa5c4f17SHuazhong Tan int ret; 12666988eb2aSSalil Mehta 12676988eb2aSSalil Mehta /* wait to check the hardware reset completion status */ 1268aa5c4f17SHuazhong Tan val = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1269aa5c4f17SHuazhong Tan dev_info(&hdev->pdev->dev, "checking vf resetting status: %x\n", val); 1270aa5c4f17SHuazhong Tan 12716ff3cf07SHuazhong Tan if (hdev->reset_type == HNAE3_FLR_RESET) 12726ff3cf07SHuazhong Tan return hclgevf_flr_poll_timeout(hdev, 12736ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_US, 12746ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_CNT); 12756ff3cf07SHuazhong Tan 1276aa5c4f17SHuazhong Tan ret = readl_poll_timeout(hdev->hw.io_base + HCLGEVF_RST_ING, val, 1277aa5c4f17SHuazhong Tan !(val & HCLGEVF_RST_ING_BITS), 1278aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_US, 1279aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 12806988eb2aSSalil Mehta 12816988eb2aSSalil Mehta /* hardware completion status should be available by this time */ 1282aa5c4f17SHuazhong Tan if (ret) { 1283aa5c4f17SHuazhong Tan dev_err(&hdev->pdev->dev, 12846988eb2aSSalil Mehta "could'nt get reset done status from h/w, timeout!\n"); 1285aa5c4f17SHuazhong Tan return ret; 12866988eb2aSSalil Mehta } 12876988eb2aSSalil Mehta 12886988eb2aSSalil Mehta /* we will wait a bit more to let reset of the stack to complete. This 12896988eb2aSSalil Mehta * might happen in case reset assertion was made by PF. Yes, this also 12906988eb2aSSalil Mehta * means we might end up waiting bit more even for VF reset. 12916988eb2aSSalil Mehta */ 12926988eb2aSSalil Mehta msleep(5000); 12936988eb2aSSalil Mehta 12946988eb2aSSalil Mehta return 0; 12956988eb2aSSalil Mehta } 12966988eb2aSSalil Mehta 12976988eb2aSSalil Mehta static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 12986988eb2aSSalil Mehta { 12997a01c897SSalil Mehta int ret; 13007a01c897SSalil Mehta 13016988eb2aSSalil Mehta /* uninitialize the nic client */ 13026a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 13036a5f6fa3SHuazhong Tan if (ret) 13046a5f6fa3SHuazhong Tan return ret; 13056988eb2aSSalil Mehta 13067a01c897SSalil Mehta /* re-initialize the hclge device */ 13079c6f7085SHuazhong Tan ret = hclgevf_reset_hdev(hdev); 13087a01c897SSalil Mehta if (ret) { 13097a01c897SSalil Mehta dev_err(&hdev->pdev->dev, 13107a01c897SSalil Mehta "hclge device re-init failed, VF is disabled!\n"); 13117a01c897SSalil Mehta return ret; 13127a01c897SSalil Mehta } 13136988eb2aSSalil Mehta 13146988eb2aSSalil Mehta /* bring up the nic client again */ 13156a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 13166a5f6fa3SHuazhong Tan if (ret) 13176a5f6fa3SHuazhong Tan return ret; 13186988eb2aSSalil Mehta 13191f609492SYunsheng Lin return hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT); 13206988eb2aSSalil Mehta } 13216988eb2aSSalil Mehta 1322dea846e8SHuazhong Tan static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1323dea846e8SHuazhong Tan { 1324dea846e8SHuazhong Tan int ret = 0; 1325dea846e8SHuazhong Tan 1326dea846e8SHuazhong Tan switch (hdev->reset_type) { 1327dea846e8SHuazhong Tan case HNAE3_VF_FUNC_RESET: 1328dea846e8SHuazhong Tan ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1329dea846e8SHuazhong Tan 0, true, NULL, sizeof(u8)); 1330dea846e8SHuazhong Tan break; 13316ff3cf07SHuazhong Tan case HNAE3_FLR_RESET: 13326ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 13336ff3cf07SHuazhong Tan break; 1334dea846e8SHuazhong Tan default: 1335dea846e8SHuazhong Tan break; 1336dea846e8SHuazhong Tan } 1337dea846e8SHuazhong Tan 1338ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1339ef5f8e50SHuazhong Tan 1340dea846e8SHuazhong Tan dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1341dea846e8SHuazhong Tan hdev->reset_type, ret); 1342dea846e8SHuazhong Tan 1343dea846e8SHuazhong Tan return ret; 1344dea846e8SHuazhong Tan } 1345dea846e8SHuazhong Tan 13466988eb2aSSalil Mehta static int hclgevf_reset(struct hclgevf_dev *hdev) 13476988eb2aSSalil Mehta { 1348dea846e8SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 13496988eb2aSSalil Mehta int ret; 13506988eb2aSSalil Mehta 1351dea846e8SHuazhong Tan /* Initialize ae_dev reset status as well, in case enet layer wants to 1352dea846e8SHuazhong Tan * know if device is undergoing reset 1353dea846e8SHuazhong Tan */ 1354dea846e8SHuazhong Tan ae_dev->reset_type = hdev->reset_type; 13554d60291bSHuazhong Tan hdev->reset_count++; 13566988eb2aSSalil Mehta rtnl_lock(); 13576988eb2aSSalil Mehta 13586988eb2aSSalil Mehta /* bring down the nic to stop any ongoing TX/RX */ 13596a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 13606a5f6fa3SHuazhong Tan if (ret) 13616a5f6fa3SHuazhong Tan goto err_reset_lock; 13626988eb2aSSalil Mehta 136329118ab9SHuazhong Tan rtnl_unlock(); 136429118ab9SHuazhong Tan 13656a5f6fa3SHuazhong Tan ret = hclgevf_reset_prepare_wait(hdev); 13666a5f6fa3SHuazhong Tan if (ret) 13676a5f6fa3SHuazhong Tan goto err_reset; 1368dea846e8SHuazhong Tan 13696988eb2aSSalil Mehta /* check if VF could successfully fetch the hardware reset completion 13706988eb2aSSalil Mehta * status from the hardware 13716988eb2aSSalil Mehta */ 13726988eb2aSSalil Mehta ret = hclgevf_reset_wait(hdev); 13736988eb2aSSalil Mehta if (ret) { 13746988eb2aSSalil Mehta /* can't do much in this situation, will disable VF */ 13756988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, 13766988eb2aSSalil Mehta "VF failed(=%d) to fetch H/W reset completion status\n", 13776988eb2aSSalil Mehta ret); 13786a5f6fa3SHuazhong Tan goto err_reset; 13796988eb2aSSalil Mehta } 13806988eb2aSSalil Mehta 138129118ab9SHuazhong Tan rtnl_lock(); 138229118ab9SHuazhong Tan 13836988eb2aSSalil Mehta /* now, re-initialize the nic client and ae device*/ 13846988eb2aSSalil Mehta ret = hclgevf_reset_stack(hdev); 13856a5f6fa3SHuazhong Tan if (ret) { 13866988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 13876a5f6fa3SHuazhong Tan goto err_reset_lock; 13886a5f6fa3SHuazhong Tan } 13896988eb2aSSalil Mehta 13906988eb2aSSalil Mehta /* bring up the nic to enable TX/RX again */ 13916a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 13926a5f6fa3SHuazhong Tan if (ret) 13936a5f6fa3SHuazhong Tan goto err_reset_lock; 13946988eb2aSSalil Mehta 13956988eb2aSSalil Mehta rtnl_unlock(); 13966988eb2aSSalil Mehta 1397b644a8d4SHuazhong Tan hdev->last_reset_time = jiffies; 1398b644a8d4SHuazhong Tan ae_dev->reset_type = HNAE3_NONE_RESET; 1399b644a8d4SHuazhong Tan 14006988eb2aSSalil Mehta return ret; 14016a5f6fa3SHuazhong Tan err_reset_lock: 14026a5f6fa3SHuazhong Tan rtnl_unlock(); 14036a5f6fa3SHuazhong Tan err_reset: 14046a5f6fa3SHuazhong Tan /* When VF reset failed, only the higher level reset asserted by PF 14056a5f6fa3SHuazhong Tan * can restore it, so re-initialize the command queue to receive 14066a5f6fa3SHuazhong Tan * this higher reset event. 14076a5f6fa3SHuazhong Tan */ 14086a5f6fa3SHuazhong Tan hclgevf_cmd_init(hdev); 14096a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "failed to reset VF\n"); 14106a5f6fa3SHuazhong Tan 14116a5f6fa3SHuazhong Tan return ret; 14126988eb2aSSalil Mehta } 14136988eb2aSSalil Mehta 1414720bd583SHuazhong Tan static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1415720bd583SHuazhong Tan unsigned long *addr) 1416720bd583SHuazhong Tan { 1417720bd583SHuazhong Tan enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1418720bd583SHuazhong Tan 1419dea846e8SHuazhong Tan /* return the highest priority reset level amongst all */ 1420b90fcc5bSHuazhong Tan if (test_bit(HNAE3_VF_RESET, addr)) { 1421b90fcc5bSHuazhong Tan rst_level = HNAE3_VF_RESET; 1422b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_RESET, addr); 1423b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1424b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1425b90fcc5bSHuazhong Tan } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1426dea846e8SHuazhong Tan rst_level = HNAE3_VF_FULL_RESET; 1427dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FULL_RESET, addr); 1428dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1429aa5c4f17SHuazhong Tan } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1430aa5c4f17SHuazhong Tan rst_level = HNAE3_VF_PF_FUNC_RESET; 1431aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1432aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1433dea846e8SHuazhong Tan } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1434dea846e8SHuazhong Tan rst_level = HNAE3_VF_FUNC_RESET; 1435dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 14366ff3cf07SHuazhong Tan } else if (test_bit(HNAE3_FLR_RESET, addr)) { 14376ff3cf07SHuazhong Tan rst_level = HNAE3_FLR_RESET; 14386ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_RESET, addr); 1439720bd583SHuazhong Tan } 1440720bd583SHuazhong Tan 1441720bd583SHuazhong Tan return rst_level; 1442720bd583SHuazhong Tan } 1443720bd583SHuazhong Tan 14446ae4e733SShiju Jose static void hclgevf_reset_event(struct pci_dev *pdev, 14456ae4e733SShiju Jose struct hnae3_handle *handle) 14466d4c3981SSalil Mehta { 14476ff3cf07SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 14486ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 14496d4c3981SSalil Mehta 14506d4c3981SSalil Mehta dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 14516d4c3981SSalil Mehta 14526ff3cf07SHuazhong Tan if (hdev->default_reset_request) 14530742ed7cSHuazhong Tan hdev->reset_level = 1454720bd583SHuazhong Tan hclgevf_get_reset_level(hdev, 1455720bd583SHuazhong Tan &hdev->default_reset_request); 1456720bd583SHuazhong Tan else 1457dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 14586d4c3981SSalil Mehta 1459436667d2SSalil Mehta /* reset of this VF requested */ 1460436667d2SSalil Mehta set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1461436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 14626d4c3981SSalil Mehta 14630742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 14646d4c3981SSalil Mehta } 14656d4c3981SSalil Mehta 1466720bd583SHuazhong Tan static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1467720bd583SHuazhong Tan enum hnae3_reset_type rst_type) 1468720bd583SHuazhong Tan { 1469720bd583SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1470720bd583SHuazhong Tan 1471720bd583SHuazhong Tan set_bit(rst_type, &hdev->default_reset_request); 1472720bd583SHuazhong Tan } 1473720bd583SHuazhong Tan 14746ff3cf07SHuazhong Tan static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 14756ff3cf07SHuazhong Tan { 14766ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_MS 100 14776ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_CNT 50 14786ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 14796ff3cf07SHuazhong Tan int cnt = 0; 14806ff3cf07SHuazhong Tan 14816ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 14826ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DONE, &hdev->flr_state); 14836ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request); 14846ff3cf07SHuazhong Tan hclgevf_reset_event(hdev->pdev, NULL); 14856ff3cf07SHuazhong Tan 14866ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) && 14876ff3cf07SHuazhong Tan cnt++ < HCLGEVF_FLR_WAIT_CNT) 14886ff3cf07SHuazhong Tan msleep(HCLGEVF_FLR_WAIT_MS); 14896ff3cf07SHuazhong Tan 14906ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state)) 14916ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 14926ff3cf07SHuazhong Tan "flr wait down timeout: %d\n", cnt); 14936ff3cf07SHuazhong Tan } 14946ff3cf07SHuazhong Tan 1495e2cb1decSSalil Mehta static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1496e2cb1decSSalil Mehta { 1497e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1498e2cb1decSSalil Mehta 1499e2cb1decSSalil Mehta return hdev->fw_version; 1500e2cb1decSSalil Mehta } 1501e2cb1decSSalil Mehta 1502e2cb1decSSalil Mehta static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1503e2cb1decSSalil Mehta { 1504e2cb1decSSalil Mehta struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1505e2cb1decSSalil Mehta 1506e2cb1decSSalil Mehta vector->vector_irq = pci_irq_vector(hdev->pdev, 1507e2cb1decSSalil Mehta HCLGEVF_MISC_VECTOR_NUM); 1508e2cb1decSSalil Mehta vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1509e2cb1decSSalil Mehta /* vector status always valid for Vector 0 */ 1510e2cb1decSSalil Mehta hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1511e2cb1decSSalil Mehta hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1512e2cb1decSSalil Mehta 1513e2cb1decSSalil Mehta hdev->num_msi_left -= 1; 1514e2cb1decSSalil Mehta hdev->num_msi_used += 1; 1515e2cb1decSSalil Mehta } 1516e2cb1decSSalil Mehta 151735a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 151835a1e503SSalil Mehta { 151935a1e503SSalil Mehta if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) && 152035a1e503SSalil Mehta !test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) { 152135a1e503SSalil Mehta set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 152235a1e503SSalil Mehta schedule_work(&hdev->rst_service_task); 152335a1e503SSalil Mehta } 152435a1e503SSalil Mehta } 152535a1e503SSalil Mehta 152607a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1527e2cb1decSSalil Mehta { 152807a0556aSSalil Mehta if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) && 152907a0556aSSalil Mehta !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) { 153007a0556aSSalil Mehta set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1531e2cb1decSSalil Mehta schedule_work(&hdev->mbx_service_task); 1532e2cb1decSSalil Mehta } 153307a0556aSSalil Mehta } 1534e2cb1decSSalil Mehta 1535e2cb1decSSalil Mehta static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 1536e2cb1decSSalil Mehta { 1537e2cb1decSSalil Mehta if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 1538e2cb1decSSalil Mehta !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 1539e2cb1decSSalil Mehta schedule_work(&hdev->service_task); 1540e2cb1decSSalil Mehta } 1541e2cb1decSSalil Mehta 1542436667d2SSalil Mehta static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev) 1543436667d2SSalil Mehta { 154407a0556aSSalil Mehta /* if we have any pending mailbox event then schedule the mbx task */ 154507a0556aSSalil Mehta if (hdev->mbx_event_pending) 154607a0556aSSalil Mehta hclgevf_mbx_task_schedule(hdev); 154707a0556aSSalil Mehta 1548436667d2SSalil Mehta if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state)) 1549436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 1550436667d2SSalil Mehta } 1551436667d2SSalil Mehta 1552e2cb1decSSalil Mehta static void hclgevf_service_timer(struct timer_list *t) 1553e2cb1decSSalil Mehta { 1554e2cb1decSSalil Mehta struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 1555e2cb1decSSalil Mehta 1556e2cb1decSSalil Mehta mod_timer(&hdev->service_timer, jiffies + 5 * HZ); 1557e2cb1decSSalil Mehta 1558e2cb1decSSalil Mehta hclgevf_task_schedule(hdev); 1559e2cb1decSSalil Mehta } 1560e2cb1decSSalil Mehta 156135a1e503SSalil Mehta static void hclgevf_reset_service_task(struct work_struct *work) 156235a1e503SSalil Mehta { 156335a1e503SSalil Mehta struct hclgevf_dev *hdev = 156435a1e503SSalil Mehta container_of(work, struct hclgevf_dev, rst_service_task); 1565a8dedb65SSalil Mehta int ret; 156635a1e503SSalil Mehta 156735a1e503SSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 156835a1e503SSalil Mehta return; 156935a1e503SSalil Mehta 157035a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 157135a1e503SSalil Mehta 1572436667d2SSalil Mehta if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1573436667d2SSalil Mehta &hdev->reset_state)) { 1574436667d2SSalil Mehta /* PF has initmated that it is about to reset the hardware. 1575436667d2SSalil Mehta * We now have to poll & check if harware has actually completed 1576436667d2SSalil Mehta * the reset sequence. On hardware reset completion, VF needs to 1577436667d2SSalil Mehta * reset the client and ae device. 157835a1e503SSalil Mehta */ 1579436667d2SSalil Mehta hdev->reset_attempts = 0; 1580436667d2SSalil Mehta 1581dea846e8SHuazhong Tan hdev->last_reset_time = jiffies; 1582dea846e8SHuazhong Tan while ((hdev->reset_type = 1583dea846e8SHuazhong Tan hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 1584dea846e8SHuazhong Tan != HNAE3_NONE_RESET) { 15856988eb2aSSalil Mehta ret = hclgevf_reset(hdev); 15866988eb2aSSalil Mehta if (ret) 1587dea846e8SHuazhong Tan dev_err(&hdev->pdev->dev, 1588dea846e8SHuazhong Tan "VF stack reset failed %d.\n", ret); 1589dea846e8SHuazhong Tan } 1590436667d2SSalil Mehta } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1591436667d2SSalil Mehta &hdev->reset_state)) { 1592436667d2SSalil Mehta /* we could be here when either of below happens: 1593436667d2SSalil Mehta * 1. reset was initiated due to watchdog timeout due to 1594436667d2SSalil Mehta * a. IMP was earlier reset and our TX got choked down and 1595436667d2SSalil Mehta * which resulted in watchdog reacting and inducing VF 1596436667d2SSalil Mehta * reset. This also means our cmdq would be unreliable. 1597436667d2SSalil Mehta * b. problem in TX due to other lower layer(example link 1598436667d2SSalil Mehta * layer not functioning properly etc.) 1599436667d2SSalil Mehta * 2. VF reset might have been initiated due to some config 1600436667d2SSalil Mehta * change. 1601436667d2SSalil Mehta * 1602436667d2SSalil Mehta * NOTE: Theres no clear way to detect above cases than to react 1603436667d2SSalil Mehta * to the response of PF for this reset request. PF will ack the 1604436667d2SSalil Mehta * 1b and 2. cases but we will not get any intimation about 1a 1605436667d2SSalil Mehta * from PF as cmdq would be in unreliable state i.e. mailbox 1606436667d2SSalil Mehta * communication between PF and VF would be broken. 1607436667d2SSalil Mehta */ 1608436667d2SSalil Mehta 1609436667d2SSalil Mehta /* if we are never geting into pending state it means either: 1610436667d2SSalil Mehta * 1. PF is not receiving our request which could be due to IMP 1611436667d2SSalil Mehta * reset 1612436667d2SSalil Mehta * 2. PF is screwed 1613436667d2SSalil Mehta * We cannot do much for 2. but to check first we can try reset 1614436667d2SSalil Mehta * our PCIe + stack and see if it alleviates the problem. 1615436667d2SSalil Mehta */ 1616436667d2SSalil Mehta if (hdev->reset_attempts > 3) { 1617436667d2SSalil Mehta /* prepare for full reset of stack + pcie interface */ 1618dea846e8SHuazhong Tan set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1619436667d2SSalil Mehta 1620436667d2SSalil Mehta /* "defer" schedule the reset task again */ 1621436667d2SSalil Mehta set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1622436667d2SSalil Mehta } else { 1623436667d2SSalil Mehta hdev->reset_attempts++; 1624436667d2SSalil Mehta 1625dea846e8SHuazhong Tan set_bit(hdev->reset_level, &hdev->reset_pending); 1626dea846e8SHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1627436667d2SSalil Mehta } 1628dea846e8SHuazhong Tan hclgevf_reset_task_schedule(hdev); 1629436667d2SSalil Mehta } 163035a1e503SSalil Mehta 163135a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 163235a1e503SSalil Mehta } 163335a1e503SSalil Mehta 1634e2cb1decSSalil Mehta static void hclgevf_mailbox_service_task(struct work_struct *work) 1635e2cb1decSSalil Mehta { 1636e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1637e2cb1decSSalil Mehta 1638e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 1639e2cb1decSSalil Mehta 1640e2cb1decSSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1641e2cb1decSSalil Mehta return; 1642e2cb1decSSalil Mehta 1643e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1644e2cb1decSSalil Mehta 164507a0556aSSalil Mehta hclgevf_mbx_async_handler(hdev); 1646e2cb1decSSalil Mehta 1647e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1648e2cb1decSSalil Mehta } 1649e2cb1decSSalil Mehta 1650a6d818e3SYunsheng Lin static void hclgevf_keep_alive_timer(struct timer_list *t) 1651a6d818e3SYunsheng Lin { 1652a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = from_timer(hdev, t, keep_alive_timer); 1653a6d818e3SYunsheng Lin 1654a6d818e3SYunsheng Lin schedule_work(&hdev->keep_alive_task); 1655a6d818e3SYunsheng Lin mod_timer(&hdev->keep_alive_timer, jiffies + 2 * HZ); 1656a6d818e3SYunsheng Lin } 1657a6d818e3SYunsheng Lin 1658a6d818e3SYunsheng Lin static void hclgevf_keep_alive_task(struct work_struct *work) 1659a6d818e3SYunsheng Lin { 1660a6d818e3SYunsheng Lin struct hclgevf_dev *hdev; 1661a6d818e3SYunsheng Lin u8 respmsg; 1662a6d818e3SYunsheng Lin int ret; 1663a6d818e3SYunsheng Lin 1664a6d818e3SYunsheng Lin hdev = container_of(work, struct hclgevf_dev, keep_alive_task); 1665c59a85c0SJian Shen 1666c59a85c0SJian Shen if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1667c59a85c0SJian Shen return; 1668c59a85c0SJian Shen 1669a6d818e3SYunsheng Lin ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL, 1670a6d818e3SYunsheng Lin 0, false, &respmsg, sizeof(u8)); 1671a6d818e3SYunsheng Lin if (ret) 1672a6d818e3SYunsheng Lin dev_err(&hdev->pdev->dev, 1673a6d818e3SYunsheng Lin "VF sends keep alive cmd failed(=%d)\n", ret); 1674a6d818e3SYunsheng Lin } 1675a6d818e3SYunsheng Lin 1676e2cb1decSSalil Mehta static void hclgevf_service_task(struct work_struct *work) 1677e2cb1decSSalil Mehta { 1678e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1679e2cb1decSSalil Mehta 1680e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, service_task); 1681e2cb1decSSalil Mehta 1682e2cb1decSSalil Mehta /* request the link status from the PF. PF would be able to tell VF 1683e2cb1decSSalil Mehta * about such updates in future so we might remove this later 1684e2cb1decSSalil Mehta */ 1685e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1686e2cb1decSSalil Mehta 16879194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 16889194d18bSliuzhongzhu 1689436667d2SSalil Mehta hclgevf_deferred_task_schedule(hdev); 1690436667d2SSalil Mehta 1691e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1692e2cb1decSSalil Mehta } 1693e2cb1decSSalil Mehta 1694e2cb1decSSalil Mehta static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1695e2cb1decSSalil Mehta { 1696e2cb1decSSalil Mehta hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1697e2cb1decSSalil Mehta } 1698e2cb1decSSalil Mehta 1699b90fcc5bSHuazhong Tan static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1700b90fcc5bSHuazhong Tan u32 *clearval) 1701e2cb1decSSalil Mehta { 1702b90fcc5bSHuazhong Tan u32 cmdq_src_reg, rst_ing_reg; 1703e2cb1decSSalil Mehta 1704e2cb1decSSalil Mehta /* fetch the events from their corresponding regs */ 1705e2cb1decSSalil Mehta cmdq_src_reg = hclgevf_read_dev(&hdev->hw, 1706e2cb1decSSalil Mehta HCLGEVF_VECTOR0_CMDQ_SRC_REG); 1707e2cb1decSSalil Mehta 1708b90fcc5bSHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_src_reg) { 1709b90fcc5bSHuazhong Tan rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1710b90fcc5bSHuazhong Tan dev_info(&hdev->pdev->dev, 1711b90fcc5bSHuazhong Tan "receive reset interrupt 0x%x!\n", rst_ing_reg); 1712b90fcc5bSHuazhong Tan set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1713b90fcc5bSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1714ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1715b90fcc5bSHuazhong Tan cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RST_INT_B); 1716b90fcc5bSHuazhong Tan *clearval = cmdq_src_reg; 1717b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_RST; 1718b90fcc5bSHuazhong Tan } 1719b90fcc5bSHuazhong Tan 1720e2cb1decSSalil Mehta /* check for vector0 mailbox(=CMDQ RX) event source */ 1721e2cb1decSSalil Mehta if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 1722e2cb1decSSalil Mehta cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1723e2cb1decSSalil Mehta *clearval = cmdq_src_reg; 1724b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_MBX; 1725e2cb1decSSalil Mehta } 1726e2cb1decSSalil Mehta 1727e2cb1decSSalil Mehta dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 1728e2cb1decSSalil Mehta 1729b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_OTHER; 1730e2cb1decSSalil Mehta } 1731e2cb1decSSalil Mehta 1732e2cb1decSSalil Mehta static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1733e2cb1decSSalil Mehta { 1734e2cb1decSSalil Mehta writel(en ? 1 : 0, vector->addr); 1735e2cb1decSSalil Mehta } 1736e2cb1decSSalil Mehta 1737e2cb1decSSalil Mehta static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1738e2cb1decSSalil Mehta { 1739b90fcc5bSHuazhong Tan enum hclgevf_evt_cause event_cause; 1740e2cb1decSSalil Mehta struct hclgevf_dev *hdev = data; 1741e2cb1decSSalil Mehta u32 clearval; 1742e2cb1decSSalil Mehta 1743e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 1744b90fcc5bSHuazhong Tan event_cause = hclgevf_check_evt_cause(hdev, &clearval); 1745e2cb1decSSalil Mehta 1746b90fcc5bSHuazhong Tan switch (event_cause) { 1747b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_RST: 1748b90fcc5bSHuazhong Tan hclgevf_reset_task_schedule(hdev); 1749b90fcc5bSHuazhong Tan break; 1750b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_MBX: 175107a0556aSSalil Mehta hclgevf_mbx_handler(hdev); 1752b90fcc5bSHuazhong Tan break; 1753b90fcc5bSHuazhong Tan default: 1754b90fcc5bSHuazhong Tan break; 1755b90fcc5bSHuazhong Tan } 1756e2cb1decSSalil Mehta 1757b90fcc5bSHuazhong Tan if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 1758e2cb1decSSalil Mehta hclgevf_clear_event_cause(hdev, clearval); 1759e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 1760b90fcc5bSHuazhong Tan } 1761e2cb1decSSalil Mehta 1762e2cb1decSSalil Mehta return IRQ_HANDLED; 1763e2cb1decSSalil Mehta } 1764e2cb1decSSalil Mehta 1765e2cb1decSSalil Mehta static int hclgevf_configure(struct hclgevf_dev *hdev) 1766e2cb1decSSalil Mehta { 1767e2cb1decSSalil Mehta int ret; 1768e2cb1decSSalil Mehta 1769e2cb1decSSalil Mehta /* get queue configuration from PF */ 17706cee6fc3SJian Shen ret = hclgevf_get_queue_info(hdev); 1771e2cb1decSSalil Mehta if (ret) 1772e2cb1decSSalil Mehta return ret; 1773c0425944SPeng Li 1774c0425944SPeng Li /* get queue depth info from PF */ 1775c0425944SPeng Li ret = hclgevf_get_queue_depth(hdev); 1776c0425944SPeng Li if (ret) 1777c0425944SPeng Li return ret; 1778c0425944SPeng Li 1779e2cb1decSSalil Mehta /* get tc configuration from PF */ 1780e2cb1decSSalil Mehta return hclgevf_get_tc_info(hdev); 1781e2cb1decSSalil Mehta } 1782e2cb1decSSalil Mehta 17837a01c897SSalil Mehta static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 17847a01c897SSalil Mehta { 17857a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 17861154bb26SPeng Li struct hclgevf_dev *hdev; 17877a01c897SSalil Mehta 17887a01c897SSalil Mehta hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 17897a01c897SSalil Mehta if (!hdev) 17907a01c897SSalil Mehta return -ENOMEM; 17917a01c897SSalil Mehta 17927a01c897SSalil Mehta hdev->pdev = pdev; 17937a01c897SSalil Mehta hdev->ae_dev = ae_dev; 17947a01c897SSalil Mehta ae_dev->priv = hdev; 17957a01c897SSalil Mehta 17967a01c897SSalil Mehta return 0; 17977a01c897SSalil Mehta } 17987a01c897SSalil Mehta 1799e2cb1decSSalil Mehta static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 1800e2cb1decSSalil Mehta { 1801e2cb1decSSalil Mehta struct hnae3_handle *roce = &hdev->roce; 1802e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 1803e2cb1decSSalil Mehta 180407acf909SJian Shen roce->rinfo.num_vectors = hdev->num_roce_msix; 1805e2cb1decSSalil Mehta 1806e2cb1decSSalil Mehta if (hdev->num_msi_left < roce->rinfo.num_vectors || 1807e2cb1decSSalil Mehta hdev->num_msi_left == 0) 1808e2cb1decSSalil Mehta return -EINVAL; 1809e2cb1decSSalil Mehta 181007acf909SJian Shen roce->rinfo.base_vector = hdev->roce_base_vector; 1811e2cb1decSSalil Mehta 1812e2cb1decSSalil Mehta roce->rinfo.netdev = nic->kinfo.netdev; 1813e2cb1decSSalil Mehta roce->rinfo.roce_io_base = hdev->hw.io_base; 1814e2cb1decSSalil Mehta 1815e2cb1decSSalil Mehta roce->pdev = nic->pdev; 1816e2cb1decSSalil Mehta roce->ae_algo = nic->ae_algo; 1817e2cb1decSSalil Mehta roce->numa_node_mask = nic->numa_node_mask; 1818e2cb1decSSalil Mehta 1819e2cb1decSSalil Mehta return 0; 1820e2cb1decSSalil Mehta } 1821e2cb1decSSalil Mehta 1822b26a6feaSPeng Li static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 1823b26a6feaSPeng Li { 1824b26a6feaSPeng Li struct hclgevf_cfg_gro_status_cmd *req; 1825b26a6feaSPeng Li struct hclgevf_desc desc; 1826b26a6feaSPeng Li int ret; 1827b26a6feaSPeng Li 1828b26a6feaSPeng Li if (!hnae3_dev_gro_supported(hdev)) 1829b26a6feaSPeng Li return 0; 1830b26a6feaSPeng Li 1831b26a6feaSPeng Li hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 1832b26a6feaSPeng Li false); 1833b26a6feaSPeng Li req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 1834b26a6feaSPeng Li 1835b26a6feaSPeng Li req->gro_en = cpu_to_le16(en ? 1 : 0); 1836b26a6feaSPeng Li 1837b26a6feaSPeng Li ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1838b26a6feaSPeng Li if (ret) 1839b26a6feaSPeng Li dev_err(&hdev->pdev->dev, 1840b26a6feaSPeng Li "VF GRO hardware config cmd failed, ret = %d.\n", ret); 1841b26a6feaSPeng Li 1842b26a6feaSPeng Li return ret; 1843b26a6feaSPeng Li } 1844b26a6feaSPeng Li 1845e2cb1decSSalil Mehta static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 1846e2cb1decSSalil Mehta { 1847e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1848e2cb1decSSalil Mehta int i, ret; 1849e2cb1decSSalil Mehta 1850e2cb1decSSalil Mehta rss_cfg->rss_size = hdev->rss_size_max; 1851e2cb1decSSalil Mehta 1852374ad291SJian Shen if (hdev->pdev->revision >= 0x21) { 1853472d7eceSJian Shen rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 1854472d7eceSJian Shen memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 1855374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 1856374ad291SJian Shen 1857374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 1858374ad291SJian Shen rss_cfg->rss_hash_key); 1859374ad291SJian Shen if (ret) 1860374ad291SJian Shen return ret; 1861d97b3072SJian Shen 1862d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = 1863d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1864d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = 1865d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1866d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = 1867d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1868d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = 1869d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1870d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = 1871d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1872d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = 1873d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1874d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = 1875d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1876d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = 1877d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1878d97b3072SJian Shen 1879d97b3072SJian Shen ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 1880d97b3072SJian Shen if (ret) 1881d97b3072SJian Shen return ret; 1882d97b3072SJian Shen 1883374ad291SJian Shen } 1884374ad291SJian Shen 1885e2cb1decSSalil Mehta /* Initialize RSS indirect table for each vport */ 1886e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 1887e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max; 1888e2cb1decSSalil Mehta 1889e2cb1decSSalil Mehta ret = hclgevf_set_rss_indir_table(hdev); 1890e2cb1decSSalil Mehta if (ret) 1891e2cb1decSSalil Mehta return ret; 1892e2cb1decSSalil Mehta 1893e2cb1decSSalil Mehta return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max); 1894e2cb1decSSalil Mehta } 1895e2cb1decSSalil Mehta 1896e2cb1decSSalil Mehta static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 1897e2cb1decSSalil Mehta { 1898e2cb1decSSalil Mehta /* other vlan config(like, VLAN TX/RX offload) would also be added 1899e2cb1decSSalil Mehta * here later 1900e2cb1decSSalil Mehta */ 1901e2cb1decSSalil Mehta return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 1902e2cb1decSSalil Mehta false); 1903e2cb1decSSalil Mehta } 1904e2cb1decSSalil Mehta 19058cdb992fSJian Shen static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 19068cdb992fSJian Shen { 19078cdb992fSJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 19088cdb992fSJian Shen 19098cdb992fSJian Shen if (enable) { 19108cdb992fSJian Shen mod_timer(&hdev->service_timer, jiffies + HZ); 19118cdb992fSJian Shen } else { 19128cdb992fSJian Shen del_timer_sync(&hdev->service_timer); 19138cdb992fSJian Shen cancel_work_sync(&hdev->service_task); 19148cdb992fSJian Shen clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 19158cdb992fSJian Shen } 19168cdb992fSJian Shen } 19178cdb992fSJian Shen 1918e2cb1decSSalil Mehta static int hclgevf_ae_start(struct hnae3_handle *handle) 1919e2cb1decSSalil Mehta { 1920e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1921e2cb1decSSalil Mehta 1922e2cb1decSSalil Mehta /* reset tqp stats */ 1923e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 1924e2cb1decSSalil Mehta 1925e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1926e2cb1decSSalil Mehta 19279194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 19289194d18bSliuzhongzhu 1929e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1930e2cb1decSSalil Mehta 1931e2cb1decSSalil Mehta return 0; 1932e2cb1decSSalil Mehta } 1933e2cb1decSSalil Mehta 1934e2cb1decSSalil Mehta static void hclgevf_ae_stop(struct hnae3_handle *handle) 1935e2cb1decSSalil Mehta { 1936e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 193739cfbc9cSHuazhong Tan int i; 1938e2cb1decSSalil Mehta 19392f7e4896SFuyun Liang set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 19402f7e4896SFuyun Liang 194139cfbc9cSHuazhong Tan for (i = 0; i < handle->kinfo.num_tqps; i++) 194239cfbc9cSHuazhong Tan hclgevf_reset_tqp(handle, i); 194339cfbc9cSHuazhong Tan 1944e2cb1decSSalil Mehta /* reset tqp stats */ 1945e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 19468cc6c1f7SFuyun Liang hclgevf_update_link_status(hdev, 0); 1947e2cb1decSSalil Mehta } 1948e2cb1decSSalil Mehta 1949a6d818e3SYunsheng Lin static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 1950a6d818e3SYunsheng Lin { 1951a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1952a6d818e3SYunsheng Lin u8 msg_data; 1953a6d818e3SYunsheng Lin 1954a6d818e3SYunsheng Lin msg_data = alive ? 1 : 0; 1955a6d818e3SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE, 1956a6d818e3SYunsheng Lin 0, &msg_data, 1, false, NULL, 0); 1957a6d818e3SYunsheng Lin } 1958a6d818e3SYunsheng Lin 1959a6d818e3SYunsheng Lin static int hclgevf_client_start(struct hnae3_handle *handle) 1960a6d818e3SYunsheng Lin { 1961a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1962a6d818e3SYunsheng Lin 1963a6d818e3SYunsheng Lin mod_timer(&hdev->keep_alive_timer, jiffies + 2 * HZ); 1964a6d818e3SYunsheng Lin return hclgevf_set_alive(handle, true); 1965a6d818e3SYunsheng Lin } 1966a6d818e3SYunsheng Lin 1967a6d818e3SYunsheng Lin static void hclgevf_client_stop(struct hnae3_handle *handle) 1968a6d818e3SYunsheng Lin { 1969a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1970a6d818e3SYunsheng Lin int ret; 1971a6d818e3SYunsheng Lin 1972a6d818e3SYunsheng Lin ret = hclgevf_set_alive(handle, false); 1973a6d818e3SYunsheng Lin if (ret) 1974a6d818e3SYunsheng Lin dev_warn(&hdev->pdev->dev, 1975a6d818e3SYunsheng Lin "%s failed %d\n", __func__, ret); 1976a6d818e3SYunsheng Lin 1977a6d818e3SYunsheng Lin del_timer_sync(&hdev->keep_alive_timer); 1978a6d818e3SYunsheng Lin cancel_work_sync(&hdev->keep_alive_task); 1979a6d818e3SYunsheng Lin } 1980a6d818e3SYunsheng Lin 1981e2cb1decSSalil Mehta static void hclgevf_state_init(struct hclgevf_dev *hdev) 1982e2cb1decSSalil Mehta { 1983e2cb1decSSalil Mehta /* setup tasks for the MBX */ 1984e2cb1decSSalil Mehta INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 1985e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1986e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1987e2cb1decSSalil Mehta 1988e2cb1decSSalil Mehta /* setup tasks for service timer */ 1989e2cb1decSSalil Mehta timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 1990e2cb1decSSalil Mehta 1991e2cb1decSSalil Mehta INIT_WORK(&hdev->service_task, hclgevf_service_task); 1992e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1993e2cb1decSSalil Mehta 199435a1e503SSalil Mehta INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task); 199535a1e503SSalil Mehta 1996e2cb1decSSalil Mehta mutex_init(&hdev->mbx_resp.mbx_mutex); 1997e2cb1decSSalil Mehta 1998e2cb1decSSalil Mehta /* bring the device down */ 1999e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2000e2cb1decSSalil Mehta } 2001e2cb1decSSalil Mehta 2002e2cb1decSSalil Mehta static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2003e2cb1decSSalil Mehta { 2004e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2005e2cb1decSSalil Mehta 2006e2cb1decSSalil Mehta if (hdev->service_timer.function) 2007e2cb1decSSalil Mehta del_timer_sync(&hdev->service_timer); 2008e2cb1decSSalil Mehta if (hdev->service_task.func) 2009e2cb1decSSalil Mehta cancel_work_sync(&hdev->service_task); 2010e2cb1decSSalil Mehta if (hdev->mbx_service_task.func) 2011e2cb1decSSalil Mehta cancel_work_sync(&hdev->mbx_service_task); 201235a1e503SSalil Mehta if (hdev->rst_service_task.func) 201335a1e503SSalil Mehta cancel_work_sync(&hdev->rst_service_task); 2014e2cb1decSSalil Mehta 2015e2cb1decSSalil Mehta mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2016e2cb1decSSalil Mehta } 2017e2cb1decSSalil Mehta 2018e2cb1decSSalil Mehta static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2019e2cb1decSSalil Mehta { 2020e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2021e2cb1decSSalil Mehta int vectors; 2022e2cb1decSSalil Mehta int i; 2023e2cb1decSSalil Mehta 202407acf909SJian Shen if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) 202507acf909SJian Shen vectors = pci_alloc_irq_vectors(pdev, 202607acf909SJian Shen hdev->roce_base_msix_offset + 1, 202707acf909SJian Shen hdev->num_msi, 202807acf909SJian Shen PCI_IRQ_MSIX); 202907acf909SJian Shen else 2030e2cb1decSSalil Mehta vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 2031e2cb1decSSalil Mehta PCI_IRQ_MSI | PCI_IRQ_MSIX); 203207acf909SJian Shen 2033e2cb1decSSalil Mehta if (vectors < 0) { 2034e2cb1decSSalil Mehta dev_err(&pdev->dev, 2035e2cb1decSSalil Mehta "failed(%d) to allocate MSI/MSI-X vectors\n", 2036e2cb1decSSalil Mehta vectors); 2037e2cb1decSSalil Mehta return vectors; 2038e2cb1decSSalil Mehta } 2039e2cb1decSSalil Mehta if (vectors < hdev->num_msi) 2040e2cb1decSSalil Mehta dev_warn(&hdev->pdev->dev, 2041e2cb1decSSalil Mehta "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2042e2cb1decSSalil Mehta hdev->num_msi, vectors); 2043e2cb1decSSalil Mehta 2044e2cb1decSSalil Mehta hdev->num_msi = vectors; 2045e2cb1decSSalil Mehta hdev->num_msi_left = vectors; 2046e2cb1decSSalil Mehta hdev->base_msi_vector = pdev->irq; 204707acf909SJian Shen hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2048e2cb1decSSalil Mehta 2049e2cb1decSSalil Mehta hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2050e2cb1decSSalil Mehta sizeof(u16), GFP_KERNEL); 2051e2cb1decSSalil Mehta if (!hdev->vector_status) { 2052e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2053e2cb1decSSalil Mehta return -ENOMEM; 2054e2cb1decSSalil Mehta } 2055e2cb1decSSalil Mehta 2056e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 2057e2cb1decSSalil Mehta hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2058e2cb1decSSalil Mehta 2059e2cb1decSSalil Mehta hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2060e2cb1decSSalil Mehta sizeof(int), GFP_KERNEL); 2061e2cb1decSSalil Mehta if (!hdev->vector_irq) { 2062862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2063e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2064e2cb1decSSalil Mehta return -ENOMEM; 2065e2cb1decSSalil Mehta } 2066e2cb1decSSalil Mehta 2067e2cb1decSSalil Mehta return 0; 2068e2cb1decSSalil Mehta } 2069e2cb1decSSalil Mehta 2070e2cb1decSSalil Mehta static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2071e2cb1decSSalil Mehta { 2072e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2073e2cb1decSSalil Mehta 2074862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2075862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_irq); 2076e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2077e2cb1decSSalil Mehta } 2078e2cb1decSSalil Mehta 2079e2cb1decSSalil Mehta static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2080e2cb1decSSalil Mehta { 2081e2cb1decSSalil Mehta int ret = 0; 2082e2cb1decSSalil Mehta 2083e2cb1decSSalil Mehta hclgevf_get_misc_vector(hdev); 2084e2cb1decSSalil Mehta 2085e2cb1decSSalil Mehta ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2086e2cb1decSSalil Mehta 0, "hclgevf_cmd", hdev); 2087e2cb1decSSalil Mehta if (ret) { 2088e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2089e2cb1decSSalil Mehta hdev->misc_vector.vector_irq); 2090e2cb1decSSalil Mehta return ret; 2091e2cb1decSSalil Mehta } 2092e2cb1decSSalil Mehta 20931819e409SXi Wang hclgevf_clear_event_cause(hdev, 0); 20941819e409SXi Wang 2095e2cb1decSSalil Mehta /* enable misc. vector(vector 0) */ 2096e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2097e2cb1decSSalil Mehta 2098e2cb1decSSalil Mehta return ret; 2099e2cb1decSSalil Mehta } 2100e2cb1decSSalil Mehta 2101e2cb1decSSalil Mehta static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2102e2cb1decSSalil Mehta { 2103e2cb1decSSalil Mehta /* disable misc vector(vector 0) */ 2104e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 21051819e409SXi Wang synchronize_irq(hdev->misc_vector.vector_irq); 2106e2cb1decSSalil Mehta free_irq(hdev->misc_vector.vector_irq, hdev); 2107e2cb1decSSalil Mehta hclgevf_free_vector(hdev, 0); 2108e2cb1decSSalil Mehta } 2109e2cb1decSSalil Mehta 2110e718a93fSPeng Li static int hclgevf_init_client_instance(struct hnae3_client *client, 2111e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2112e2cb1decSSalil Mehta { 2113e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2114e2cb1decSSalil Mehta int ret; 2115e2cb1decSSalil Mehta 2116e2cb1decSSalil Mehta switch (client->type) { 2117e2cb1decSSalil Mehta case HNAE3_CLIENT_KNIC: 2118e2cb1decSSalil Mehta hdev->nic_client = client; 2119e2cb1decSSalil Mehta hdev->nic.client = client; 2120e2cb1decSSalil Mehta 2121e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->nic); 2122e2cb1decSSalil Mehta if (ret) 212349dd8054SJian Shen goto clear_nic; 2124e2cb1decSSalil Mehta 2125d9f28fc2SJian Shen hnae3_set_client_init_flag(client, ae_dev, 1); 2126d9f28fc2SJian Shen 2127e2cb1decSSalil Mehta if (hdev->roce_client && hnae3_dev_roce_supported(hdev)) { 2128e2cb1decSSalil Mehta struct hnae3_client *rc = hdev->roce_client; 2129e2cb1decSSalil Mehta 2130e2cb1decSSalil Mehta ret = hclgevf_init_roce_base_info(hdev); 2131e2cb1decSSalil Mehta if (ret) 213249dd8054SJian Shen goto clear_roce; 2133e2cb1decSSalil Mehta ret = rc->ops->init_instance(&hdev->roce); 2134e2cb1decSSalil Mehta if (ret) 213549dd8054SJian Shen goto clear_roce; 2136d9f28fc2SJian Shen 2137d9f28fc2SJian Shen hnae3_set_client_init_flag(hdev->roce_client, ae_dev, 2138d9f28fc2SJian Shen 1); 2139e2cb1decSSalil Mehta } 2140e2cb1decSSalil Mehta break; 2141e2cb1decSSalil Mehta case HNAE3_CLIENT_UNIC: 2142e2cb1decSSalil Mehta hdev->nic_client = client; 2143e2cb1decSSalil Mehta hdev->nic.client = client; 2144e2cb1decSSalil Mehta 2145e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->nic); 2146e2cb1decSSalil Mehta if (ret) 214749dd8054SJian Shen goto clear_nic; 2148d9f28fc2SJian Shen 2149d9f28fc2SJian Shen hnae3_set_client_init_flag(client, ae_dev, 1); 2150e2cb1decSSalil Mehta break; 2151e2cb1decSSalil Mehta case HNAE3_CLIENT_ROCE: 2152544a7bcdSLijun Ou if (hnae3_dev_roce_supported(hdev)) { 2153e2cb1decSSalil Mehta hdev->roce_client = client; 2154e2cb1decSSalil Mehta hdev->roce.client = client; 2155544a7bcdSLijun Ou } 2156e2cb1decSSalil Mehta 2157544a7bcdSLijun Ou if (hdev->roce_client && hdev->nic_client) { 2158e2cb1decSSalil Mehta ret = hclgevf_init_roce_base_info(hdev); 2159e2cb1decSSalil Mehta if (ret) 216049dd8054SJian Shen goto clear_roce; 2161e2cb1decSSalil Mehta 2162e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->roce); 2163e2cb1decSSalil Mehta if (ret) 216449dd8054SJian Shen goto clear_roce; 2165e2cb1decSSalil Mehta } 2166d9f28fc2SJian Shen 2167d9f28fc2SJian Shen hnae3_set_client_init_flag(client, ae_dev, 1); 2168fa7a4bd5SJian Shen break; 2169fa7a4bd5SJian Shen default: 2170fa7a4bd5SJian Shen return -EINVAL; 2171e2cb1decSSalil Mehta } 2172e2cb1decSSalil Mehta 2173e2cb1decSSalil Mehta return 0; 217449dd8054SJian Shen 217549dd8054SJian Shen clear_nic: 217649dd8054SJian Shen hdev->nic_client = NULL; 217749dd8054SJian Shen hdev->nic.client = NULL; 217849dd8054SJian Shen return ret; 217949dd8054SJian Shen clear_roce: 218049dd8054SJian Shen hdev->roce_client = NULL; 218149dd8054SJian Shen hdev->roce.client = NULL; 218249dd8054SJian Shen return ret; 2183e2cb1decSSalil Mehta } 2184e2cb1decSSalil Mehta 2185e718a93fSPeng Li static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2186e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2187e2cb1decSSalil Mehta { 2188e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2189e718a93fSPeng Li 2190e2cb1decSSalil Mehta /* un-init roce, if it exists */ 219149dd8054SJian Shen if (hdev->roce_client) { 2192e2cb1decSSalil Mehta hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 219349dd8054SJian Shen hdev->roce_client = NULL; 219449dd8054SJian Shen hdev->roce.client = NULL; 219549dd8054SJian Shen } 2196e2cb1decSSalil Mehta 2197e2cb1decSSalil Mehta /* un-init nic/unic, if this was not called by roce client */ 219849dd8054SJian Shen if (client->ops->uninit_instance && hdev->nic_client && 219949dd8054SJian Shen client->type != HNAE3_CLIENT_ROCE) { 2200e2cb1decSSalil Mehta client->ops->uninit_instance(&hdev->nic, 0); 220149dd8054SJian Shen hdev->nic_client = NULL; 220249dd8054SJian Shen hdev->nic.client = NULL; 220349dd8054SJian Shen } 2204e2cb1decSSalil Mehta } 2205e2cb1decSSalil Mehta 2206e2cb1decSSalil Mehta static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2207e2cb1decSSalil Mehta { 2208e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2209e2cb1decSSalil Mehta struct hclgevf_hw *hw; 2210e2cb1decSSalil Mehta int ret; 2211e2cb1decSSalil Mehta 2212e2cb1decSSalil Mehta ret = pci_enable_device(pdev); 2213e2cb1decSSalil Mehta if (ret) { 2214e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed to enable PCI device\n"); 22153e249d3bSFuyun Liang return ret; 2216e2cb1decSSalil Mehta } 2217e2cb1decSSalil Mehta 2218e2cb1decSSalil Mehta ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2219e2cb1decSSalil Mehta if (ret) { 2220e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2221e2cb1decSSalil Mehta goto err_disable_device; 2222e2cb1decSSalil Mehta } 2223e2cb1decSSalil Mehta 2224e2cb1decSSalil Mehta ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2225e2cb1decSSalil Mehta if (ret) { 2226e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2227e2cb1decSSalil Mehta goto err_disable_device; 2228e2cb1decSSalil Mehta } 2229e2cb1decSSalil Mehta 2230e2cb1decSSalil Mehta pci_set_master(pdev); 2231e2cb1decSSalil Mehta hw = &hdev->hw; 2232e2cb1decSSalil Mehta hw->hdev = hdev; 22332e1ea493SPeng Li hw->io_base = pci_iomap(pdev, 2, 0); 2234e2cb1decSSalil Mehta if (!hw->io_base) { 2235e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't map configuration register space\n"); 2236e2cb1decSSalil Mehta ret = -ENOMEM; 2237e2cb1decSSalil Mehta goto err_clr_master; 2238e2cb1decSSalil Mehta } 2239e2cb1decSSalil Mehta 2240e2cb1decSSalil Mehta return 0; 2241e2cb1decSSalil Mehta 2242e2cb1decSSalil Mehta err_clr_master: 2243e2cb1decSSalil Mehta pci_clear_master(pdev); 2244e2cb1decSSalil Mehta pci_release_regions(pdev); 2245e2cb1decSSalil Mehta err_disable_device: 2246e2cb1decSSalil Mehta pci_disable_device(pdev); 22473e249d3bSFuyun Liang 2248e2cb1decSSalil Mehta return ret; 2249e2cb1decSSalil Mehta } 2250e2cb1decSSalil Mehta 2251e2cb1decSSalil Mehta static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2252e2cb1decSSalil Mehta { 2253e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2254e2cb1decSSalil Mehta 2255e2cb1decSSalil Mehta pci_iounmap(pdev, hdev->hw.io_base); 2256e2cb1decSSalil Mehta pci_clear_master(pdev); 2257e2cb1decSSalil Mehta pci_release_regions(pdev); 2258e2cb1decSSalil Mehta pci_disable_device(pdev); 2259e2cb1decSSalil Mehta } 2260e2cb1decSSalil Mehta 226107acf909SJian Shen static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 226207acf909SJian Shen { 226307acf909SJian Shen struct hclgevf_query_res_cmd *req; 226407acf909SJian Shen struct hclgevf_desc desc; 226507acf909SJian Shen int ret; 226607acf909SJian Shen 226707acf909SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 226807acf909SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 226907acf909SJian Shen if (ret) { 227007acf909SJian Shen dev_err(&hdev->pdev->dev, 227107acf909SJian Shen "query vf resource failed, ret = %d.\n", ret); 227207acf909SJian Shen return ret; 227307acf909SJian Shen } 227407acf909SJian Shen 227507acf909SJian Shen req = (struct hclgevf_query_res_cmd *)desc.data; 227607acf909SJian Shen 227707acf909SJian Shen if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) { 227807acf909SJian Shen hdev->roce_base_msix_offset = 227907acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 228007acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_M, 228107acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_S); 228207acf909SJian Shen hdev->num_roce_msix = 228307acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 228407acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 228507acf909SJian Shen 228607acf909SJian Shen /* VF should have NIC vectors and Roce vectors, NIC vectors 228707acf909SJian Shen * are queued before Roce vectors. The offset is fixed to 64. 228807acf909SJian Shen */ 228907acf909SJian Shen hdev->num_msi = hdev->num_roce_msix + 229007acf909SJian Shen hdev->roce_base_msix_offset; 229107acf909SJian Shen } else { 229207acf909SJian Shen hdev->num_msi = 229307acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 229407acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 229507acf909SJian Shen } 229607acf909SJian Shen 229707acf909SJian Shen return 0; 229807acf909SJian Shen } 229907acf909SJian Shen 2300862d969aSHuazhong Tan static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2301862d969aSHuazhong Tan { 2302862d969aSHuazhong Tan struct pci_dev *pdev = hdev->pdev; 2303862d969aSHuazhong Tan int ret = 0; 2304862d969aSHuazhong Tan 2305862d969aSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2306862d969aSHuazhong Tan test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2307862d969aSHuazhong Tan hclgevf_misc_irq_uninit(hdev); 2308862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2309862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2310862d969aSHuazhong Tan } 2311862d969aSHuazhong Tan 2312862d969aSHuazhong Tan if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2313862d969aSHuazhong Tan pci_set_master(pdev); 2314862d969aSHuazhong Tan ret = hclgevf_init_msi(hdev); 2315862d969aSHuazhong Tan if (ret) { 2316862d969aSHuazhong Tan dev_err(&pdev->dev, 2317862d969aSHuazhong Tan "failed(%d) to init MSI/MSI-X\n", ret); 2318862d969aSHuazhong Tan return ret; 2319862d969aSHuazhong Tan } 2320862d969aSHuazhong Tan 2321862d969aSHuazhong Tan ret = hclgevf_misc_irq_init(hdev); 2322862d969aSHuazhong Tan if (ret) { 2323862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2324862d969aSHuazhong Tan dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2325862d969aSHuazhong Tan ret); 2326862d969aSHuazhong Tan return ret; 2327862d969aSHuazhong Tan } 2328862d969aSHuazhong Tan 2329862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2330862d969aSHuazhong Tan } 2331862d969aSHuazhong Tan 2332862d969aSHuazhong Tan return ret; 2333862d969aSHuazhong Tan } 2334862d969aSHuazhong Tan 23359c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2336e2cb1decSSalil Mehta { 23377a01c897SSalil Mehta struct pci_dev *pdev = hdev->pdev; 2338e2cb1decSSalil Mehta int ret; 2339e2cb1decSSalil Mehta 2340862d969aSHuazhong Tan ret = hclgevf_pci_reset(hdev); 2341862d969aSHuazhong Tan if (ret) { 2342862d969aSHuazhong Tan dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2343862d969aSHuazhong Tan return ret; 2344862d969aSHuazhong Tan } 2345862d969aSHuazhong Tan 23469c6f7085SHuazhong Tan ret = hclgevf_cmd_init(hdev); 23479c6f7085SHuazhong Tan if (ret) { 23489c6f7085SHuazhong Tan dev_err(&pdev->dev, "cmd failed %d\n", ret); 23499c6f7085SHuazhong Tan return ret; 23507a01c897SSalil Mehta } 2351e2cb1decSSalil Mehta 23529c6f7085SHuazhong Tan ret = hclgevf_rss_init_hw(hdev); 23539c6f7085SHuazhong Tan if (ret) { 23549c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 23559c6f7085SHuazhong Tan "failed(%d) to initialize RSS\n", ret); 23569c6f7085SHuazhong Tan return ret; 23579c6f7085SHuazhong Tan } 23589c6f7085SHuazhong Tan 2359b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2360b26a6feaSPeng Li if (ret) 2361b26a6feaSPeng Li return ret; 2362b26a6feaSPeng Li 23639c6f7085SHuazhong Tan ret = hclgevf_init_vlan_config(hdev); 23649c6f7085SHuazhong Tan if (ret) { 23659c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 23669c6f7085SHuazhong Tan "failed(%d) to initialize VLAN config\n", ret); 23679c6f7085SHuazhong Tan return ret; 23689c6f7085SHuazhong Tan } 23699c6f7085SHuazhong Tan 23709c6f7085SHuazhong Tan dev_info(&hdev->pdev->dev, "Reset done\n"); 23719c6f7085SHuazhong Tan 23729c6f7085SHuazhong Tan return 0; 23739c6f7085SHuazhong Tan } 23749c6f7085SHuazhong Tan 23759c6f7085SHuazhong Tan static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 23769c6f7085SHuazhong Tan { 23779c6f7085SHuazhong Tan struct pci_dev *pdev = hdev->pdev; 23789c6f7085SHuazhong Tan int ret; 23799c6f7085SHuazhong Tan 2380e2cb1decSSalil Mehta ret = hclgevf_pci_init(hdev); 2381e2cb1decSSalil Mehta if (ret) { 2382e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI initialization failed\n"); 2383e2cb1decSSalil Mehta return ret; 2384e2cb1decSSalil Mehta } 2385e2cb1decSSalil Mehta 23868b0195a3SHuazhong Tan ret = hclgevf_cmd_queue_init(hdev); 23878b0195a3SHuazhong Tan if (ret) { 23888b0195a3SHuazhong Tan dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret); 23898b0195a3SHuazhong Tan goto err_cmd_queue_init; 23908b0195a3SHuazhong Tan } 23918b0195a3SHuazhong Tan 2392eddf0462SYunsheng Lin ret = hclgevf_cmd_init(hdev); 2393eddf0462SYunsheng Lin if (ret) 2394eddf0462SYunsheng Lin goto err_cmd_init; 2395eddf0462SYunsheng Lin 239607acf909SJian Shen /* Get vf resource */ 239707acf909SJian Shen ret = hclgevf_query_vf_resource(hdev); 239807acf909SJian Shen if (ret) { 239907acf909SJian Shen dev_err(&hdev->pdev->dev, 240007acf909SJian Shen "Query vf status error, ret = %d.\n", ret); 24018b0195a3SHuazhong Tan goto err_cmd_init; 240207acf909SJian Shen } 240307acf909SJian Shen 240407acf909SJian Shen ret = hclgevf_init_msi(hdev); 240507acf909SJian Shen if (ret) { 240607acf909SJian Shen dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 24078b0195a3SHuazhong Tan goto err_cmd_init; 240807acf909SJian Shen } 240907acf909SJian Shen 241007acf909SJian Shen hclgevf_state_init(hdev); 2411dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 241207acf909SJian Shen 2413e2cb1decSSalil Mehta ret = hclgevf_misc_irq_init(hdev); 2414e2cb1decSSalil Mehta if (ret) { 2415e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2416e2cb1decSSalil Mehta ret); 2417e2cb1decSSalil Mehta goto err_misc_irq_init; 2418e2cb1decSSalil Mehta } 2419e2cb1decSSalil Mehta 2420862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2421862d969aSHuazhong Tan 2422e2cb1decSSalil Mehta ret = hclgevf_configure(hdev); 2423e2cb1decSSalil Mehta if (ret) { 2424e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2425e2cb1decSSalil Mehta goto err_config; 2426e2cb1decSSalil Mehta } 2427e2cb1decSSalil Mehta 2428e2cb1decSSalil Mehta ret = hclgevf_alloc_tqps(hdev); 2429e2cb1decSSalil Mehta if (ret) { 2430e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2431e2cb1decSSalil Mehta goto err_config; 2432e2cb1decSSalil Mehta } 2433e2cb1decSSalil Mehta 2434e2cb1decSSalil Mehta ret = hclgevf_set_handle_info(hdev); 2435e2cb1decSSalil Mehta if (ret) { 2436e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 2437e2cb1decSSalil Mehta goto err_config; 2438e2cb1decSSalil Mehta } 2439e2cb1decSSalil Mehta 2440b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2441b26a6feaSPeng Li if (ret) 2442b26a6feaSPeng Li goto err_config; 2443b26a6feaSPeng Li 2444f01f5559SJian Shen /* vf is not allowed to enable unicast/multicast promisc mode. 2445f01f5559SJian Shen * For revision 0x20, default to disable broadcast promisc mode, 2446f01f5559SJian Shen * firmware makes sure broadcast packets can be accepted. 2447f01f5559SJian Shen * For revision 0x21, default to enable broadcast promisc mode. 2448f01f5559SJian Shen */ 2449f01f5559SJian Shen ret = hclgevf_set_promisc_mode(hdev, true); 2450f01f5559SJian Shen if (ret) 2451f01f5559SJian Shen goto err_config; 2452f01f5559SJian Shen 2453e2cb1decSSalil Mehta /* Initialize RSS for this VF */ 2454e2cb1decSSalil Mehta ret = hclgevf_rss_init_hw(hdev); 2455e2cb1decSSalil Mehta if (ret) { 2456e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2457e2cb1decSSalil Mehta "failed(%d) to initialize RSS\n", ret); 2458e2cb1decSSalil Mehta goto err_config; 2459e2cb1decSSalil Mehta } 2460e2cb1decSSalil Mehta 2461e2cb1decSSalil Mehta ret = hclgevf_init_vlan_config(hdev); 2462e2cb1decSSalil Mehta if (ret) { 2463e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2464e2cb1decSSalil Mehta "failed(%d) to initialize VLAN config\n", ret); 2465e2cb1decSSalil Mehta goto err_config; 2466e2cb1decSSalil Mehta } 2467e2cb1decSSalil Mehta 24680742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 2469e2cb1decSSalil Mehta pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME); 2470e2cb1decSSalil Mehta 2471e2cb1decSSalil Mehta return 0; 2472e2cb1decSSalil Mehta 2473e2cb1decSSalil Mehta err_config: 2474e2cb1decSSalil Mehta hclgevf_misc_irq_uninit(hdev); 2475e2cb1decSSalil Mehta err_misc_irq_init: 2476e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2477e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 247807acf909SJian Shen err_cmd_init: 24798b0195a3SHuazhong Tan hclgevf_cmd_uninit(hdev); 24808b0195a3SHuazhong Tan err_cmd_queue_init: 2481e2cb1decSSalil Mehta hclgevf_pci_uninit(hdev); 2482862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2483e2cb1decSSalil Mehta return ret; 2484e2cb1decSSalil Mehta } 2485e2cb1decSSalil Mehta 24867a01c897SSalil Mehta static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2487e2cb1decSSalil Mehta { 2488e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2489862d969aSHuazhong Tan 2490862d969aSHuazhong Tan if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2491eddf0462SYunsheng Lin hclgevf_misc_irq_uninit(hdev); 2492e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 24937a01c897SSalil Mehta } 24947a01c897SSalil Mehta 2495e3338205SHuazhong Tan hclgevf_pci_uninit(hdev); 2496862d969aSHuazhong Tan hclgevf_cmd_uninit(hdev); 2497862d969aSHuazhong Tan } 2498862d969aSHuazhong Tan 24997a01c897SSalil Mehta static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 25007a01c897SSalil Mehta { 25017a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 2502a6d818e3SYunsheng Lin struct hclgevf_dev *hdev; 25037a01c897SSalil Mehta int ret; 25047a01c897SSalil Mehta 25057a01c897SSalil Mehta ret = hclgevf_alloc_hdev(ae_dev); 25067a01c897SSalil Mehta if (ret) { 25077a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device allocation failed\n"); 25087a01c897SSalil Mehta return ret; 25097a01c897SSalil Mehta } 25107a01c897SSalil Mehta 25117a01c897SSalil Mehta ret = hclgevf_init_hdev(ae_dev->priv); 2512a6d818e3SYunsheng Lin if (ret) { 25137a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device initialization failed\n"); 25147a01c897SSalil Mehta return ret; 25157a01c897SSalil Mehta } 25167a01c897SSalil Mehta 2517a6d818e3SYunsheng Lin hdev = ae_dev->priv; 2518a6d818e3SYunsheng Lin timer_setup(&hdev->keep_alive_timer, hclgevf_keep_alive_timer, 0); 2519a6d818e3SYunsheng Lin INIT_WORK(&hdev->keep_alive_task, hclgevf_keep_alive_task); 2520a6d818e3SYunsheng Lin 2521a6d818e3SYunsheng Lin return 0; 2522a6d818e3SYunsheng Lin } 2523a6d818e3SYunsheng Lin 25247a01c897SSalil Mehta static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 25257a01c897SSalil Mehta { 25267a01c897SSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 25277a01c897SSalil Mehta 25287a01c897SSalil Mehta hclgevf_uninit_hdev(hdev); 2529e2cb1decSSalil Mehta ae_dev->priv = NULL; 2530e2cb1decSSalil Mehta } 2531e2cb1decSSalil Mehta 2532849e4607SPeng Li static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2533849e4607SPeng Li { 2534849e4607SPeng Li struct hnae3_handle *nic = &hdev->nic; 2535849e4607SPeng Li struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2536849e4607SPeng Li 25378be73621SHuazhong Tan return min_t(u32, hdev->rss_size_max, 25388be73621SHuazhong Tan hdev->num_tqps / kinfo->num_tc); 2539849e4607SPeng Li } 2540849e4607SPeng Li 2541849e4607SPeng Li /** 2542849e4607SPeng Li * hclgevf_get_channels - Get the current channels enabled and max supported. 2543849e4607SPeng Li * @handle: hardware information for network interface 2544849e4607SPeng Li * @ch: ethtool channels structure 2545849e4607SPeng Li * 2546849e4607SPeng Li * We don't support separate tx and rx queues as channels. The other count 2547849e4607SPeng Li * represents how many queues are being used for control. max_combined counts 2548849e4607SPeng Li * how many queue pairs we can support. They may not be mapped 1 to 1 with 2549849e4607SPeng Li * q_vectors since we support a lot more queue pairs than q_vectors. 2550849e4607SPeng Li **/ 2551849e4607SPeng Li static void hclgevf_get_channels(struct hnae3_handle *handle, 2552849e4607SPeng Li struct ethtool_channels *ch) 2553849e4607SPeng Li { 2554849e4607SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2555849e4607SPeng Li 2556849e4607SPeng Li ch->max_combined = hclgevf_get_max_channels(hdev); 2557849e4607SPeng Li ch->other_count = 0; 2558849e4607SPeng Li ch->max_other = 0; 25598be73621SHuazhong Tan ch->combined_count = handle->kinfo.rss_size; 2560849e4607SPeng Li } 2561849e4607SPeng Li 2562cc719218SPeng Li static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 25630d43bf45SHuazhong Tan u16 *alloc_tqps, u16 *max_rss_size) 2564cc719218SPeng Li { 2565cc719218SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2566cc719218SPeng Li 25670d43bf45SHuazhong Tan *alloc_tqps = hdev->num_tqps; 2568cc719218SPeng Li *max_rss_size = hdev->rss_size_max; 2569cc719218SPeng Li } 2570cc719218SPeng Li 2571175ec96bSFuyun Liang static int hclgevf_get_status(struct hnae3_handle *handle) 2572175ec96bSFuyun Liang { 2573175ec96bSFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2574175ec96bSFuyun Liang 2575175ec96bSFuyun Liang return hdev->hw.mac.link; 2576175ec96bSFuyun Liang } 2577175ec96bSFuyun Liang 25784a152de9SFuyun Liang static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 25794a152de9SFuyun Liang u8 *auto_neg, u32 *speed, 25804a152de9SFuyun Liang u8 *duplex) 25814a152de9SFuyun Liang { 25824a152de9SFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 25834a152de9SFuyun Liang 25844a152de9SFuyun Liang if (speed) 25854a152de9SFuyun Liang *speed = hdev->hw.mac.speed; 25864a152de9SFuyun Liang if (duplex) 25874a152de9SFuyun Liang *duplex = hdev->hw.mac.duplex; 25884a152de9SFuyun Liang if (auto_neg) 25894a152de9SFuyun Liang *auto_neg = AUTONEG_DISABLE; 25904a152de9SFuyun Liang } 25914a152de9SFuyun Liang 25924a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 25934a152de9SFuyun Liang u8 duplex) 25944a152de9SFuyun Liang { 25954a152de9SFuyun Liang hdev->hw.mac.speed = speed; 25964a152de9SFuyun Liang hdev->hw.mac.duplex = duplex; 25974a152de9SFuyun Liang } 25984a152de9SFuyun Liang 25991731be4cSYonglong Liu static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 26005c9f6b39SPeng Li { 26015c9f6b39SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 26025c9f6b39SPeng Li 26035c9f6b39SPeng Li return hclgevf_config_gro(hdev, enable); 26045c9f6b39SPeng Li } 26055c9f6b39SPeng Li 2606c136b884SPeng Li static void hclgevf_get_media_type(struct hnae3_handle *handle, 2607c136b884SPeng Li u8 *media_type) 2608c136b884SPeng Li { 2609c136b884SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2610c136b884SPeng Li if (media_type) 2611c136b884SPeng Li *media_type = hdev->hw.mac.media_type; 2612c136b884SPeng Li } 2613c136b884SPeng Li 26144d60291bSHuazhong Tan static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 26154d60291bSHuazhong Tan { 26164d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 26174d60291bSHuazhong Tan 2618aa5c4f17SHuazhong Tan return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 26194d60291bSHuazhong Tan } 26204d60291bSHuazhong Tan 26214d60291bSHuazhong Tan static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 26224d60291bSHuazhong Tan { 26234d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 26244d60291bSHuazhong Tan 26254d60291bSHuazhong Tan return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 26264d60291bSHuazhong Tan } 26274d60291bSHuazhong Tan 26284d60291bSHuazhong Tan static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 26294d60291bSHuazhong Tan { 26304d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 26314d60291bSHuazhong Tan 26324d60291bSHuazhong Tan return hdev->reset_count; 26334d60291bSHuazhong Tan } 26344d60291bSHuazhong Tan 26359194d18bSliuzhongzhu static void hclgevf_get_link_mode(struct hnae3_handle *handle, 26369194d18bSliuzhongzhu unsigned long *supported, 26379194d18bSliuzhongzhu unsigned long *advertising) 26389194d18bSliuzhongzhu { 26399194d18bSliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 26409194d18bSliuzhongzhu 26419194d18bSliuzhongzhu *supported = hdev->hw.mac.supported; 26429194d18bSliuzhongzhu *advertising = hdev->hw.mac.advertising; 26439194d18bSliuzhongzhu } 26449194d18bSliuzhongzhu 26451600c3e5SJian Shen #define MAX_SEPARATE_NUM 4 26461600c3e5SJian Shen #define SEPARATOR_VALUE 0xFFFFFFFF 26471600c3e5SJian Shen #define REG_NUM_PER_LINE 4 26481600c3e5SJian Shen #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 26491600c3e5SJian Shen 26501600c3e5SJian Shen static int hclgevf_get_regs_len(struct hnae3_handle *handle) 26511600c3e5SJian Shen { 26521600c3e5SJian Shen int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 26531600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 26541600c3e5SJian Shen 26551600c3e5SJian Shen cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 26561600c3e5SJian Shen common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 26571600c3e5SJian Shen ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 26581600c3e5SJian Shen tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 26591600c3e5SJian Shen 26601600c3e5SJian Shen return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 26611600c3e5SJian Shen tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 26621600c3e5SJian Shen } 26631600c3e5SJian Shen 26641600c3e5SJian Shen static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 26651600c3e5SJian Shen void *data) 26661600c3e5SJian Shen { 26671600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 26681600c3e5SJian Shen int i, j, reg_um, separator_num; 26691600c3e5SJian Shen u32 *reg = data; 26701600c3e5SJian Shen 26711600c3e5SJian Shen *version = hdev->fw_version; 26721600c3e5SJian Shen 26731600c3e5SJian Shen /* fetching per-VF registers values from VF PCIe register space */ 26741600c3e5SJian Shen reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 26751600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 26761600c3e5SJian Shen for (i = 0; i < reg_um; i++) 26771600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 26781600c3e5SJian Shen for (i = 0; i < separator_num; i++) 26791600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 26801600c3e5SJian Shen 26811600c3e5SJian Shen reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 26821600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 26831600c3e5SJian Shen for (i = 0; i < reg_um; i++) 26841600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 26851600c3e5SJian Shen for (i = 0; i < separator_num; i++) 26861600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 26871600c3e5SJian Shen 26881600c3e5SJian Shen reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 26891600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 26901600c3e5SJian Shen for (j = 0; j < hdev->num_tqps; j++) { 26911600c3e5SJian Shen for (i = 0; i < reg_um; i++) 26921600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 26931600c3e5SJian Shen ring_reg_addr_list[i] + 26941600c3e5SJian Shen 0x200 * j); 26951600c3e5SJian Shen for (i = 0; i < separator_num; i++) 26961600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 26971600c3e5SJian Shen } 26981600c3e5SJian Shen 26991600c3e5SJian Shen reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 27001600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 27011600c3e5SJian Shen for (j = 0; j < hdev->num_msi_used - 1; j++) { 27021600c3e5SJian Shen for (i = 0; i < reg_um; i++) 27031600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 27041600c3e5SJian Shen tqp_intr_reg_addr_list[i] + 27051600c3e5SJian Shen 4 * j); 27061600c3e5SJian Shen for (i = 0; i < separator_num; i++) 27071600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 27081600c3e5SJian Shen } 27091600c3e5SJian Shen } 27101600c3e5SJian Shen 2711e2cb1decSSalil Mehta static const struct hnae3_ae_ops hclgevf_ops = { 2712e2cb1decSSalil Mehta .init_ae_dev = hclgevf_init_ae_dev, 2713e2cb1decSSalil Mehta .uninit_ae_dev = hclgevf_uninit_ae_dev, 27146ff3cf07SHuazhong Tan .flr_prepare = hclgevf_flr_prepare, 27156ff3cf07SHuazhong Tan .flr_done = hclgevf_flr_done, 2716e718a93fSPeng Li .init_client_instance = hclgevf_init_client_instance, 2717e718a93fSPeng Li .uninit_client_instance = hclgevf_uninit_client_instance, 2718e2cb1decSSalil Mehta .start = hclgevf_ae_start, 2719e2cb1decSSalil Mehta .stop = hclgevf_ae_stop, 2720a6d818e3SYunsheng Lin .client_start = hclgevf_client_start, 2721a6d818e3SYunsheng Lin .client_stop = hclgevf_client_stop, 2722e2cb1decSSalil Mehta .map_ring_to_vector = hclgevf_map_ring_to_vector, 2723e2cb1decSSalil Mehta .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 2724e2cb1decSSalil Mehta .get_vector = hclgevf_get_vector, 27250d3e6631SYunsheng Lin .put_vector = hclgevf_put_vector, 2726e2cb1decSSalil Mehta .reset_queue = hclgevf_reset_tqp, 2727e2cb1decSSalil Mehta .get_mac_addr = hclgevf_get_mac_addr, 2728e2cb1decSSalil Mehta .set_mac_addr = hclgevf_set_mac_addr, 2729e2cb1decSSalil Mehta .add_uc_addr = hclgevf_add_uc_addr, 2730e2cb1decSSalil Mehta .rm_uc_addr = hclgevf_rm_uc_addr, 2731e2cb1decSSalil Mehta .add_mc_addr = hclgevf_add_mc_addr, 2732e2cb1decSSalil Mehta .rm_mc_addr = hclgevf_rm_mc_addr, 2733e2cb1decSSalil Mehta .get_stats = hclgevf_get_stats, 2734e2cb1decSSalil Mehta .update_stats = hclgevf_update_stats, 2735e2cb1decSSalil Mehta .get_strings = hclgevf_get_strings, 2736e2cb1decSSalil Mehta .get_sset_count = hclgevf_get_sset_count, 2737e2cb1decSSalil Mehta .get_rss_key_size = hclgevf_get_rss_key_size, 2738e2cb1decSSalil Mehta .get_rss_indir_size = hclgevf_get_rss_indir_size, 2739e2cb1decSSalil Mehta .get_rss = hclgevf_get_rss, 2740e2cb1decSSalil Mehta .set_rss = hclgevf_set_rss, 2741d97b3072SJian Shen .get_rss_tuple = hclgevf_get_rss_tuple, 2742d97b3072SJian Shen .set_rss_tuple = hclgevf_set_rss_tuple, 2743e2cb1decSSalil Mehta .get_tc_size = hclgevf_get_tc_size, 2744e2cb1decSSalil Mehta .get_fw_version = hclgevf_get_fw_version, 2745e2cb1decSSalil Mehta .set_vlan_filter = hclgevf_set_vlan_filter, 2746b2641e2aSYunsheng Lin .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 27476d4c3981SSalil Mehta .reset_event = hclgevf_reset_event, 2748720bd583SHuazhong Tan .set_default_reset_request = hclgevf_set_def_reset_request, 2749849e4607SPeng Li .get_channels = hclgevf_get_channels, 2750cc719218SPeng Li .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 27511600c3e5SJian Shen .get_regs_len = hclgevf_get_regs_len, 27521600c3e5SJian Shen .get_regs = hclgevf_get_regs, 2753175ec96bSFuyun Liang .get_status = hclgevf_get_status, 27544a152de9SFuyun Liang .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 2755c136b884SPeng Li .get_media_type = hclgevf_get_media_type, 27564d60291bSHuazhong Tan .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 27574d60291bSHuazhong Tan .ae_dev_resetting = hclgevf_ae_dev_resetting, 27584d60291bSHuazhong Tan .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 27595c9f6b39SPeng Li .set_gro_en = hclgevf_gro_en, 2760818f1675SYunsheng Lin .set_mtu = hclgevf_set_mtu, 27610c29d191Sliuzhongzhu .get_global_queue_id = hclgevf_get_qid_global, 27628cdb992fSJian Shen .set_timer_task = hclgevf_set_timer_task, 27639194d18bSliuzhongzhu .get_link_mode = hclgevf_get_link_mode, 2764e2cb1decSSalil Mehta }; 2765e2cb1decSSalil Mehta 2766e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf = { 2767e2cb1decSSalil Mehta .ops = &hclgevf_ops, 2768e2cb1decSSalil Mehta .pdev_id_table = ae_algovf_pci_tbl, 2769e2cb1decSSalil Mehta }; 2770e2cb1decSSalil Mehta 2771e2cb1decSSalil Mehta static int hclgevf_init(void) 2772e2cb1decSSalil Mehta { 2773e2cb1decSSalil Mehta pr_info("%s is initializing\n", HCLGEVF_NAME); 2774e2cb1decSSalil Mehta 2775854cf33aSFuyun Liang hnae3_register_ae_algo(&ae_algovf); 2776854cf33aSFuyun Liang 2777854cf33aSFuyun Liang return 0; 2778e2cb1decSSalil Mehta } 2779e2cb1decSSalil Mehta 2780e2cb1decSSalil Mehta static void hclgevf_exit(void) 2781e2cb1decSSalil Mehta { 2782e2cb1decSSalil Mehta hnae3_unregister_ae_algo(&ae_algovf); 2783e2cb1decSSalil Mehta } 2784e2cb1decSSalil Mehta module_init(hclgevf_init); 2785e2cb1decSSalil Mehta module_exit(hclgevf_exit); 2786e2cb1decSSalil Mehta 2787e2cb1decSSalil Mehta MODULE_LICENSE("GPL"); 2788e2cb1decSSalil Mehta MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 2789e2cb1decSSalil Mehta MODULE_DESCRIPTION("HCLGEVF Driver"); 2790e2cb1decSSalil Mehta MODULE_VERSION(HCLGEVF_MOD_VERSION); 2791