1e2cb1decSSalil Mehta // SPDX-License-Identifier: GPL-2.0+ 2e2cb1decSSalil Mehta // Copyright (c) 2016-2017 Hisilicon Limited. 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #include <linux/etherdevice.h> 5aa5c4f17SHuazhong Tan #include <linux/iopoll.h> 66988eb2aSSalil Mehta #include <net/rtnetlink.h> 7e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 8e2cb1decSSalil Mehta #include "hclgevf_main.h" 9e2cb1decSSalil Mehta #include "hclge_mbx.h" 10e2cb1decSSalil Mehta #include "hnae3.h" 11e2cb1decSSalil Mehta 12e2cb1decSSalil Mehta #define HCLGEVF_NAME "hclgevf" 13e2cb1decSSalil Mehta 14bbe6540eSHuazhong Tan #define HCLGEVF_RESET_MAX_FAIL_CNT 5 15bbe6540eSHuazhong Tan 169c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 17e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf; 18e2cb1decSSalil Mehta 19e2cb1decSSalil Mehta static const struct pci_device_id ae_algovf_pci_tbl[] = { 20e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 21e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 22e2cb1decSSalil Mehta /* required last entry */ 23e2cb1decSSalil Mehta {0, } 24e2cb1decSSalil Mehta }; 25e2cb1decSSalil Mehta 26472d7eceSJian Shen static const u8 hclgevf_hash_key[] = { 27472d7eceSJian Shen 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 28472d7eceSJian Shen 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 29472d7eceSJian Shen 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 30472d7eceSJian Shen 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 31472d7eceSJian Shen 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 32472d7eceSJian Shen }; 33472d7eceSJian Shen 342f550a46SYunsheng Lin MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 352f550a46SYunsheng Lin 361600c3e5SJian Shen static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 371600c3e5SJian Shen HCLGEVF_CMDQ_TX_ADDR_H_REG, 381600c3e5SJian Shen HCLGEVF_CMDQ_TX_DEPTH_REG, 391600c3e5SJian Shen HCLGEVF_CMDQ_TX_TAIL_REG, 401600c3e5SJian Shen HCLGEVF_CMDQ_TX_HEAD_REG, 411600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_L_REG, 421600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_H_REG, 431600c3e5SJian Shen HCLGEVF_CMDQ_RX_DEPTH_REG, 441600c3e5SJian Shen HCLGEVF_CMDQ_RX_TAIL_REG, 451600c3e5SJian Shen HCLGEVF_CMDQ_RX_HEAD_REG, 461600c3e5SJian Shen HCLGEVF_VECTOR0_CMDQ_SRC_REG, 471600c3e5SJian Shen HCLGEVF_CMDQ_INTR_STS_REG, 481600c3e5SJian Shen HCLGEVF_CMDQ_INTR_EN_REG, 491600c3e5SJian Shen HCLGEVF_CMDQ_INTR_GEN_REG}; 501600c3e5SJian Shen 511600c3e5SJian Shen static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 521600c3e5SJian Shen HCLGEVF_RST_ING, 531600c3e5SJian Shen HCLGEVF_GRO_EN_REG}; 541600c3e5SJian Shen 551600c3e5SJian Shen static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 561600c3e5SJian Shen HCLGEVF_RING_RX_ADDR_H_REG, 571600c3e5SJian Shen HCLGEVF_RING_RX_BD_NUM_REG, 581600c3e5SJian Shen HCLGEVF_RING_RX_BD_LENGTH_REG, 591600c3e5SJian Shen HCLGEVF_RING_RX_MERGE_EN_REG, 601600c3e5SJian Shen HCLGEVF_RING_RX_TAIL_REG, 611600c3e5SJian Shen HCLGEVF_RING_RX_HEAD_REG, 621600c3e5SJian Shen HCLGEVF_RING_RX_FBD_NUM_REG, 631600c3e5SJian Shen HCLGEVF_RING_RX_OFFSET_REG, 641600c3e5SJian Shen HCLGEVF_RING_RX_FBD_OFFSET_REG, 651600c3e5SJian Shen HCLGEVF_RING_RX_STASH_REG, 661600c3e5SJian Shen HCLGEVF_RING_RX_BD_ERR_REG, 671600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_L_REG, 681600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_H_REG, 691600c3e5SJian Shen HCLGEVF_RING_TX_BD_NUM_REG, 701600c3e5SJian Shen HCLGEVF_RING_TX_PRIORITY_REG, 711600c3e5SJian Shen HCLGEVF_RING_TX_TC_REG, 721600c3e5SJian Shen HCLGEVF_RING_TX_MERGE_EN_REG, 731600c3e5SJian Shen HCLGEVF_RING_TX_TAIL_REG, 741600c3e5SJian Shen HCLGEVF_RING_TX_HEAD_REG, 751600c3e5SJian Shen HCLGEVF_RING_TX_FBD_NUM_REG, 761600c3e5SJian Shen HCLGEVF_RING_TX_OFFSET_REG, 771600c3e5SJian Shen HCLGEVF_RING_TX_EBD_NUM_REG, 781600c3e5SJian Shen HCLGEVF_RING_TX_EBD_OFFSET_REG, 791600c3e5SJian Shen HCLGEVF_RING_TX_BD_ERR_REG, 801600c3e5SJian Shen HCLGEVF_RING_EN_REG}; 811600c3e5SJian Shen 821600c3e5SJian Shen static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 831600c3e5SJian Shen HCLGEVF_TQP_INTR_GL0_REG, 841600c3e5SJian Shen HCLGEVF_TQP_INTR_GL1_REG, 851600c3e5SJian Shen HCLGEVF_TQP_INTR_GL2_REG, 861600c3e5SJian Shen HCLGEVF_TQP_INTR_RL_REG}; 871600c3e5SJian Shen 889b2f3477SWeihang Li static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 89e2cb1decSSalil Mehta { 90eed9535fSPeng Li if (!handle->client) 91eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, nic); 92eed9535fSPeng Li else if (handle->client->type == HNAE3_CLIENT_ROCE) 93eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, roce); 94eed9535fSPeng Li else 95e2cb1decSSalil Mehta return container_of(handle, struct hclgevf_dev, nic); 96e2cb1decSSalil Mehta } 97e2cb1decSSalil Mehta 98e2cb1decSSalil Mehta static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 99e2cb1decSSalil Mehta { 100b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 101e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 102e2cb1decSSalil Mehta struct hclgevf_desc desc; 103e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 104e2cb1decSSalil Mehta int status; 105e2cb1decSSalil Mehta int i; 106e2cb1decSSalil Mehta 107b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 108b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 109e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 110e2cb1decSSalil Mehta HCLGEVF_OPC_QUERY_RX_STATUS, 111e2cb1decSSalil Mehta true); 112e2cb1decSSalil Mehta 113e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 114e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 115e2cb1decSSalil Mehta if (status) { 116e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 117e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 118e2cb1decSSalil Mehta status, i); 119e2cb1decSSalil Mehta return status; 120e2cb1decSSalil Mehta } 121e2cb1decSSalil Mehta tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 122cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 123e2cb1decSSalil Mehta 124e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 125e2cb1decSSalil Mehta true); 126e2cb1decSSalil Mehta 127e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 128e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 129e2cb1decSSalil Mehta if (status) { 130e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 131e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 132e2cb1decSSalil Mehta status, i); 133e2cb1decSSalil Mehta return status; 134e2cb1decSSalil Mehta } 135e2cb1decSSalil Mehta tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 136cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 137e2cb1decSSalil Mehta } 138e2cb1decSSalil Mehta 139e2cb1decSSalil Mehta return 0; 140e2cb1decSSalil Mehta } 141e2cb1decSSalil Mehta 142e2cb1decSSalil Mehta static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 143e2cb1decSSalil Mehta { 144e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo = &handle->kinfo; 145e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 146e2cb1decSSalil Mehta u64 *buff = data; 147e2cb1decSSalil Mehta int i; 148e2cb1decSSalil Mehta 149b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 150b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 151e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 152e2cb1decSSalil Mehta } 153e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 154b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 155e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 156e2cb1decSSalil Mehta } 157e2cb1decSSalil Mehta 158e2cb1decSSalil Mehta return buff; 159e2cb1decSSalil Mehta } 160e2cb1decSSalil Mehta 161e2cb1decSSalil Mehta static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 162e2cb1decSSalil Mehta { 163b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 164e2cb1decSSalil Mehta 165b4f1d303SJian Shen return kinfo->num_tqps * 2; 166e2cb1decSSalil Mehta } 167e2cb1decSSalil Mehta 168e2cb1decSSalil Mehta static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 169e2cb1decSSalil Mehta { 170b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 171e2cb1decSSalil Mehta u8 *buff = data; 172e2cb1decSSalil Mehta int i = 0; 173e2cb1decSSalil Mehta 174b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 175b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 176e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1770c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 178e2cb1decSSalil Mehta tqp->index); 179e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 180e2cb1decSSalil Mehta } 181e2cb1decSSalil Mehta 182b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 183b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 184e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1850c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 186e2cb1decSSalil Mehta tqp->index); 187e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 188e2cb1decSSalil Mehta } 189e2cb1decSSalil Mehta 190e2cb1decSSalil Mehta return buff; 191e2cb1decSSalil Mehta } 192e2cb1decSSalil Mehta 193e2cb1decSSalil Mehta static void hclgevf_update_stats(struct hnae3_handle *handle, 194e2cb1decSSalil Mehta struct net_device_stats *net_stats) 195e2cb1decSSalil Mehta { 196e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 197e2cb1decSSalil Mehta int status; 198e2cb1decSSalil Mehta 199e2cb1decSSalil Mehta status = hclgevf_tqps_update_stats(handle); 200e2cb1decSSalil Mehta if (status) 201e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 202e2cb1decSSalil Mehta "VF update of TQPS stats fail, status = %d.\n", 203e2cb1decSSalil Mehta status); 204e2cb1decSSalil Mehta } 205e2cb1decSSalil Mehta 206e2cb1decSSalil Mehta static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 207e2cb1decSSalil Mehta { 208e2cb1decSSalil Mehta if (strset == ETH_SS_TEST) 209e2cb1decSSalil Mehta return -EOPNOTSUPP; 210e2cb1decSSalil Mehta else if (strset == ETH_SS_STATS) 211e2cb1decSSalil Mehta return hclgevf_tqps_get_sset_count(handle, strset); 212e2cb1decSSalil Mehta 213e2cb1decSSalil Mehta return 0; 214e2cb1decSSalil Mehta } 215e2cb1decSSalil Mehta 216e2cb1decSSalil Mehta static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 217e2cb1decSSalil Mehta u8 *data) 218e2cb1decSSalil Mehta { 219e2cb1decSSalil Mehta u8 *p = (char *)data; 220e2cb1decSSalil Mehta 221e2cb1decSSalil Mehta if (strset == ETH_SS_STATS) 222e2cb1decSSalil Mehta p = hclgevf_tqps_get_strings(handle, p); 223e2cb1decSSalil Mehta } 224e2cb1decSSalil Mehta 225e2cb1decSSalil Mehta static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 226e2cb1decSSalil Mehta { 227e2cb1decSSalil Mehta hclgevf_tqps_get_stats(handle, data); 228e2cb1decSSalil Mehta } 229e2cb1decSSalil Mehta 230e2cb1decSSalil Mehta static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 231e2cb1decSSalil Mehta { 232e2cb1decSSalil Mehta u8 resp_msg; 233e2cb1decSSalil Mehta int status; 234e2cb1decSSalil Mehta 235e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 23663cbf7a9SYufeng Mo true, &resp_msg, sizeof(resp_msg)); 237e2cb1decSSalil Mehta if (status) { 238e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 239e2cb1decSSalil Mehta "VF request to get TC info from PF failed %d", 240e2cb1decSSalil Mehta status); 241e2cb1decSSalil Mehta return status; 242e2cb1decSSalil Mehta } 243e2cb1decSSalil Mehta 244e2cb1decSSalil Mehta hdev->hw_tc_map = resp_msg; 245e2cb1decSSalil Mehta 246e2cb1decSSalil Mehta return 0; 247e2cb1decSSalil Mehta } 248e2cb1decSSalil Mehta 24992f11ea1SJian Shen static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 25092f11ea1SJian Shen { 25192f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 25292f11ea1SJian Shen u8 resp_msg; 25392f11ea1SJian Shen int ret; 25492f11ea1SJian Shen 25592f11ea1SJian Shen ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 25692f11ea1SJian Shen HCLGE_MBX_GET_PORT_BASE_VLAN_STATE, 25792f11ea1SJian Shen NULL, 0, true, &resp_msg, sizeof(u8)); 25892f11ea1SJian Shen if (ret) { 25992f11ea1SJian Shen dev_err(&hdev->pdev->dev, 26092f11ea1SJian Shen "VF request to get port based vlan state failed %d", 26192f11ea1SJian Shen ret); 26292f11ea1SJian Shen return ret; 26392f11ea1SJian Shen } 26492f11ea1SJian Shen 26592f11ea1SJian Shen nic->port_base_vlan_state = resp_msg; 26692f11ea1SJian Shen 26792f11ea1SJian Shen return 0; 26892f11ea1SJian Shen } 26992f11ea1SJian Shen 2706cee6fc3SJian Shen static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 271e2cb1decSSalil Mehta { 272c0425944SPeng Li #define HCLGEVF_TQPS_RSS_INFO_LEN 6 273e2cb1decSSalil Mehta u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 274e2cb1decSSalil Mehta int status; 275e2cb1decSSalil Mehta 276e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 277e2cb1decSSalil Mehta true, resp_msg, 278e2cb1decSSalil Mehta HCLGEVF_TQPS_RSS_INFO_LEN); 279e2cb1decSSalil Mehta if (status) { 280e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 281e2cb1decSSalil Mehta "VF request to get tqp info from PF failed %d", 282e2cb1decSSalil Mehta status); 283e2cb1decSSalil Mehta return status; 284e2cb1decSSalil Mehta } 285e2cb1decSSalil Mehta 286e2cb1decSSalil Mehta memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 287e2cb1decSSalil Mehta memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 288c0425944SPeng Li memcpy(&hdev->rx_buf_len, &resp_msg[4], sizeof(u16)); 289c0425944SPeng Li 290c0425944SPeng Li return 0; 291c0425944SPeng Li } 292c0425944SPeng Li 293c0425944SPeng Li static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 294c0425944SPeng Li { 295c0425944SPeng Li #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 296c0425944SPeng Li u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 297c0425944SPeng Li int ret; 298c0425944SPeng Li 299c0425944SPeng Li ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QDEPTH, 0, NULL, 0, 300c0425944SPeng Li true, resp_msg, 301c0425944SPeng Li HCLGEVF_TQPS_DEPTH_INFO_LEN); 302c0425944SPeng Li if (ret) { 303c0425944SPeng Li dev_err(&hdev->pdev->dev, 304c0425944SPeng Li "VF request to get tqp depth info from PF failed %d", 305c0425944SPeng Li ret); 306c0425944SPeng Li return ret; 307c0425944SPeng Li } 308c0425944SPeng Li 309c0425944SPeng Li memcpy(&hdev->num_tx_desc, &resp_msg[0], sizeof(u16)); 310c0425944SPeng Li memcpy(&hdev->num_rx_desc, &resp_msg[2], sizeof(u16)); 311e2cb1decSSalil Mehta 312e2cb1decSSalil Mehta return 0; 313e2cb1decSSalil Mehta } 314e2cb1decSSalil Mehta 3150c29d191Sliuzhongzhu static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 3160c29d191Sliuzhongzhu { 3170c29d191Sliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3180c29d191Sliuzhongzhu u8 msg_data[2], resp_data[2]; 3190c29d191Sliuzhongzhu u16 qid_in_pf = 0; 3200c29d191Sliuzhongzhu int ret; 3210c29d191Sliuzhongzhu 3220c29d191Sliuzhongzhu memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 3230c29d191Sliuzhongzhu 3240c29d191Sliuzhongzhu ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data, 32563cbf7a9SYufeng Mo sizeof(msg_data), true, resp_data, 32663cbf7a9SYufeng Mo sizeof(resp_data)); 3270c29d191Sliuzhongzhu if (!ret) 3280c29d191Sliuzhongzhu qid_in_pf = *(u16 *)resp_data; 3290c29d191Sliuzhongzhu 3300c29d191Sliuzhongzhu return qid_in_pf; 3310c29d191Sliuzhongzhu } 3320c29d191Sliuzhongzhu 3339c3e7130Sliuzhongzhu static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 3349c3e7130Sliuzhongzhu { 33588d10bd6SJian Shen u8 resp_msg[2]; 3369c3e7130Sliuzhongzhu int ret; 3379c3e7130Sliuzhongzhu 3389c3e7130Sliuzhongzhu ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_MEDIA_TYPE, 0, NULL, 0, 33988d10bd6SJian Shen true, resp_msg, sizeof(resp_msg)); 3409c3e7130Sliuzhongzhu if (ret) { 3419c3e7130Sliuzhongzhu dev_err(&hdev->pdev->dev, 3429c3e7130Sliuzhongzhu "VF request to get the pf port media type failed %d", 3439c3e7130Sliuzhongzhu ret); 3449c3e7130Sliuzhongzhu return ret; 3459c3e7130Sliuzhongzhu } 3469c3e7130Sliuzhongzhu 34788d10bd6SJian Shen hdev->hw.mac.media_type = resp_msg[0]; 34888d10bd6SJian Shen hdev->hw.mac.module_type = resp_msg[1]; 3499c3e7130Sliuzhongzhu 3509c3e7130Sliuzhongzhu return 0; 3519c3e7130Sliuzhongzhu } 3529c3e7130Sliuzhongzhu 353e2cb1decSSalil Mehta static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 354e2cb1decSSalil Mehta { 355e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 356e2cb1decSSalil Mehta int i; 357e2cb1decSSalil Mehta 358e2cb1decSSalil Mehta hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 359e2cb1decSSalil Mehta sizeof(struct hclgevf_tqp), GFP_KERNEL); 360e2cb1decSSalil Mehta if (!hdev->htqp) 361e2cb1decSSalil Mehta return -ENOMEM; 362e2cb1decSSalil Mehta 363e2cb1decSSalil Mehta tqp = hdev->htqp; 364e2cb1decSSalil Mehta 365e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 366e2cb1decSSalil Mehta tqp->dev = &hdev->pdev->dev; 367e2cb1decSSalil Mehta tqp->index = i; 368e2cb1decSSalil Mehta 369e2cb1decSSalil Mehta tqp->q.ae_algo = &ae_algovf; 370e2cb1decSSalil Mehta tqp->q.buf_size = hdev->rx_buf_len; 371c0425944SPeng Li tqp->q.tx_desc_num = hdev->num_tx_desc; 372c0425944SPeng Li tqp->q.rx_desc_num = hdev->num_rx_desc; 373e2cb1decSSalil Mehta tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 374e2cb1decSSalil Mehta i * HCLGEVF_TQP_REG_SIZE; 375e2cb1decSSalil Mehta 376e2cb1decSSalil Mehta tqp++; 377e2cb1decSSalil Mehta } 378e2cb1decSSalil Mehta 379e2cb1decSSalil Mehta return 0; 380e2cb1decSSalil Mehta } 381e2cb1decSSalil Mehta 382e2cb1decSSalil Mehta static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 383e2cb1decSSalil Mehta { 384e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 385e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo; 386e2cb1decSSalil Mehta u16 new_tqps = hdev->num_tqps; 387ebaf1908SWeihang Li unsigned int i; 388e2cb1decSSalil Mehta 389e2cb1decSSalil Mehta kinfo = &nic->kinfo; 390e2cb1decSSalil Mehta kinfo->num_tc = 0; 391c0425944SPeng Li kinfo->num_tx_desc = hdev->num_tx_desc; 392c0425944SPeng Li kinfo->num_rx_desc = hdev->num_rx_desc; 393e2cb1decSSalil Mehta kinfo->rx_buf_len = hdev->rx_buf_len; 394e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 395e2cb1decSSalil Mehta if (hdev->hw_tc_map & BIT(i)) 396e2cb1decSSalil Mehta kinfo->num_tc++; 397e2cb1decSSalil Mehta 398e2cb1decSSalil Mehta kinfo->rss_size 399e2cb1decSSalil Mehta = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 400e2cb1decSSalil Mehta new_tqps = kinfo->rss_size * kinfo->num_tc; 401e2cb1decSSalil Mehta kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 402e2cb1decSSalil Mehta 403e2cb1decSSalil Mehta kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 404e2cb1decSSalil Mehta sizeof(struct hnae3_queue *), GFP_KERNEL); 405e2cb1decSSalil Mehta if (!kinfo->tqp) 406e2cb1decSSalil Mehta return -ENOMEM; 407e2cb1decSSalil Mehta 408e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 409e2cb1decSSalil Mehta hdev->htqp[i].q.handle = &hdev->nic; 410e2cb1decSSalil Mehta hdev->htqp[i].q.tqp_index = i; 411e2cb1decSSalil Mehta kinfo->tqp[i] = &hdev->htqp[i].q; 412e2cb1decSSalil Mehta } 413e2cb1decSSalil Mehta 414e2cb1decSSalil Mehta return 0; 415e2cb1decSSalil Mehta } 416e2cb1decSSalil Mehta 417e2cb1decSSalil Mehta static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 418e2cb1decSSalil Mehta { 419e2cb1decSSalil Mehta int status; 420e2cb1decSSalil Mehta u8 resp_msg; 421e2cb1decSSalil Mehta 422e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 42363cbf7a9SYufeng Mo 0, false, &resp_msg, sizeof(resp_msg)); 424e2cb1decSSalil Mehta if (status) 425e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 426e2cb1decSSalil Mehta "VF failed to fetch link status(%d) from PF", status); 427e2cb1decSSalil Mehta } 428e2cb1decSSalil Mehta 429e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 430e2cb1decSSalil Mehta { 43145e92b7eSPeng Li struct hnae3_handle *rhandle = &hdev->roce; 432e2cb1decSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 43345e92b7eSPeng Li struct hnae3_client *rclient; 434e2cb1decSSalil Mehta struct hnae3_client *client; 435e2cb1decSSalil Mehta 436e2cb1decSSalil Mehta client = handle->client; 43745e92b7eSPeng Li rclient = hdev->roce_client; 438e2cb1decSSalil Mehta 439582d37bbSPeng Li link_state = 440582d37bbSPeng Li test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 441582d37bbSPeng Li 442e2cb1decSSalil Mehta if (link_state != hdev->hw.mac.link) { 443e2cb1decSSalil Mehta client->ops->link_status_change(handle, !!link_state); 44445e92b7eSPeng Li if (rclient && rclient->ops->link_status_change) 44545e92b7eSPeng Li rclient->ops->link_status_change(rhandle, !!link_state); 446e2cb1decSSalil Mehta hdev->hw.mac.link = link_state; 447e2cb1decSSalil Mehta } 448e2cb1decSSalil Mehta } 449e2cb1decSSalil Mehta 450538abaf3SYueHaibing static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 4519194d18bSliuzhongzhu { 4529194d18bSliuzhongzhu #define HCLGEVF_ADVERTISING 0 4539194d18bSliuzhongzhu #define HCLGEVF_SUPPORTED 1 4549194d18bSliuzhongzhu u8 send_msg; 4559194d18bSliuzhongzhu u8 resp_msg; 4569194d18bSliuzhongzhu 4579194d18bSliuzhongzhu send_msg = HCLGEVF_ADVERTISING; 45863cbf7a9SYufeng Mo hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 45963cbf7a9SYufeng Mo &send_msg, sizeof(send_msg), false, 46063cbf7a9SYufeng Mo &resp_msg, sizeof(resp_msg)); 4619194d18bSliuzhongzhu send_msg = HCLGEVF_SUPPORTED; 46263cbf7a9SYufeng Mo hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 46363cbf7a9SYufeng Mo &send_msg, sizeof(send_msg), false, 46463cbf7a9SYufeng Mo &resp_msg, sizeof(resp_msg)); 4659194d18bSliuzhongzhu } 4669194d18bSliuzhongzhu 467e2cb1decSSalil Mehta static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 468e2cb1decSSalil Mehta { 469e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 470e2cb1decSSalil Mehta int ret; 471e2cb1decSSalil Mehta 472e2cb1decSSalil Mehta nic->ae_algo = &ae_algovf; 473e2cb1decSSalil Mehta nic->pdev = hdev->pdev; 474e2cb1decSSalil Mehta nic->numa_node_mask = hdev->numa_node_mask; 475424eb834SSalil Mehta nic->flags |= HNAE3_SUPPORT_VF; 476e2cb1decSSalil Mehta 477e2cb1decSSalil Mehta ret = hclgevf_knic_setup(hdev); 478e2cb1decSSalil Mehta if (ret) 479e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 480e2cb1decSSalil Mehta ret); 481e2cb1decSSalil Mehta return ret; 482e2cb1decSSalil Mehta } 483e2cb1decSSalil Mehta 484e2cb1decSSalil Mehta static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 485e2cb1decSSalil Mehta { 48636cbbdf6SPeng Li if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 48736cbbdf6SPeng Li dev_warn(&hdev->pdev->dev, 48836cbbdf6SPeng Li "vector(vector_id %d) has been freed.\n", vector_id); 48936cbbdf6SPeng Li return; 49036cbbdf6SPeng Li } 49136cbbdf6SPeng Li 492e2cb1decSSalil Mehta hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 493e2cb1decSSalil Mehta hdev->num_msi_left += 1; 494e2cb1decSSalil Mehta hdev->num_msi_used -= 1; 495e2cb1decSSalil Mehta } 496e2cb1decSSalil Mehta 497e2cb1decSSalil Mehta static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 498e2cb1decSSalil Mehta struct hnae3_vector_info *vector_info) 499e2cb1decSSalil Mehta { 500e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 501e2cb1decSSalil Mehta struct hnae3_vector_info *vector = vector_info; 502e2cb1decSSalil Mehta int alloc = 0; 503e2cb1decSSalil Mehta int i, j; 504e2cb1decSSalil Mehta 505e2cb1decSSalil Mehta vector_num = min(hdev->num_msi_left, vector_num); 506e2cb1decSSalil Mehta 507e2cb1decSSalil Mehta for (j = 0; j < vector_num; j++) { 508e2cb1decSSalil Mehta for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 509e2cb1decSSalil Mehta if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 510e2cb1decSSalil Mehta vector->vector = pci_irq_vector(hdev->pdev, i); 511e2cb1decSSalil Mehta vector->io_addr = hdev->hw.io_base + 512e2cb1decSSalil Mehta HCLGEVF_VECTOR_REG_BASE + 513e2cb1decSSalil Mehta (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 514e2cb1decSSalil Mehta hdev->vector_status[i] = 0; 515e2cb1decSSalil Mehta hdev->vector_irq[i] = vector->vector; 516e2cb1decSSalil Mehta 517e2cb1decSSalil Mehta vector++; 518e2cb1decSSalil Mehta alloc++; 519e2cb1decSSalil Mehta 520e2cb1decSSalil Mehta break; 521e2cb1decSSalil Mehta } 522e2cb1decSSalil Mehta } 523e2cb1decSSalil Mehta } 524e2cb1decSSalil Mehta hdev->num_msi_left -= alloc; 525e2cb1decSSalil Mehta hdev->num_msi_used += alloc; 526e2cb1decSSalil Mehta 527e2cb1decSSalil Mehta return alloc; 528e2cb1decSSalil Mehta } 529e2cb1decSSalil Mehta 530e2cb1decSSalil Mehta static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 531e2cb1decSSalil Mehta { 532e2cb1decSSalil Mehta int i; 533e2cb1decSSalil Mehta 534e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 535e2cb1decSSalil Mehta if (vector == hdev->vector_irq[i]) 536e2cb1decSSalil Mehta return i; 537e2cb1decSSalil Mehta 538e2cb1decSSalil Mehta return -EINVAL; 539e2cb1decSSalil Mehta } 540e2cb1decSSalil Mehta 541374ad291SJian Shen static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 542374ad291SJian Shen const u8 hfunc, const u8 *key) 543374ad291SJian Shen { 544374ad291SJian Shen struct hclgevf_rss_config_cmd *req; 545ebaf1908SWeihang Li unsigned int key_offset = 0; 546374ad291SJian Shen struct hclgevf_desc desc; 5473caf772bSYufeng Mo int key_counts; 548374ad291SJian Shen int key_size; 549374ad291SJian Shen int ret; 550374ad291SJian Shen 5513caf772bSYufeng Mo key_counts = HCLGEVF_RSS_KEY_SIZE; 552374ad291SJian Shen req = (struct hclgevf_rss_config_cmd *)desc.data; 553374ad291SJian Shen 5543caf772bSYufeng Mo while (key_counts) { 555374ad291SJian Shen hclgevf_cmd_setup_basic_desc(&desc, 556374ad291SJian Shen HCLGEVF_OPC_RSS_GENERIC_CONFIG, 557374ad291SJian Shen false); 558374ad291SJian Shen 559374ad291SJian Shen req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 560374ad291SJian Shen req->hash_config |= 561374ad291SJian Shen (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 562374ad291SJian Shen 5633caf772bSYufeng Mo key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts); 564374ad291SJian Shen memcpy(req->hash_key, 565374ad291SJian Shen key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 566374ad291SJian Shen 5673caf772bSYufeng Mo key_counts -= key_size; 5683caf772bSYufeng Mo key_offset++; 569374ad291SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 570374ad291SJian Shen if (ret) { 571374ad291SJian Shen dev_err(&hdev->pdev->dev, 572374ad291SJian Shen "Configure RSS config fail, status = %d\n", 573374ad291SJian Shen ret); 574374ad291SJian Shen return ret; 575374ad291SJian Shen } 576374ad291SJian Shen } 577374ad291SJian Shen 578374ad291SJian Shen return 0; 579374ad291SJian Shen } 580374ad291SJian Shen 581e2cb1decSSalil Mehta static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 582e2cb1decSSalil Mehta { 583e2cb1decSSalil Mehta return HCLGEVF_RSS_KEY_SIZE; 584e2cb1decSSalil Mehta } 585e2cb1decSSalil Mehta 586e2cb1decSSalil Mehta static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 587e2cb1decSSalil Mehta { 588e2cb1decSSalil Mehta return HCLGEVF_RSS_IND_TBL_SIZE; 589e2cb1decSSalil Mehta } 590e2cb1decSSalil Mehta 591e2cb1decSSalil Mehta static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 592e2cb1decSSalil Mehta { 593e2cb1decSSalil Mehta const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 594e2cb1decSSalil Mehta struct hclgevf_rss_indirection_table_cmd *req; 595e2cb1decSSalil Mehta struct hclgevf_desc desc; 596e2cb1decSSalil Mehta int status; 597e2cb1decSSalil Mehta int i, j; 598e2cb1decSSalil Mehta 599e2cb1decSSalil Mehta req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 600e2cb1decSSalil Mehta 601e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 602e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 603e2cb1decSSalil Mehta false); 604e2cb1decSSalil Mehta req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 605e2cb1decSSalil Mehta req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 606e2cb1decSSalil Mehta for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 607e2cb1decSSalil Mehta req->rss_result[j] = 608e2cb1decSSalil Mehta indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 609e2cb1decSSalil Mehta 610e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 611e2cb1decSSalil Mehta if (status) { 612e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 613e2cb1decSSalil Mehta "VF failed(=%d) to set RSS indirection table\n", 614e2cb1decSSalil Mehta status); 615e2cb1decSSalil Mehta return status; 616e2cb1decSSalil Mehta } 617e2cb1decSSalil Mehta } 618e2cb1decSSalil Mehta 619e2cb1decSSalil Mehta return 0; 620e2cb1decSSalil Mehta } 621e2cb1decSSalil Mehta 622e2cb1decSSalil Mehta static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 623e2cb1decSSalil Mehta { 624e2cb1decSSalil Mehta struct hclgevf_rss_tc_mode_cmd *req; 625e2cb1decSSalil Mehta u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 626e2cb1decSSalil Mehta u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 627e2cb1decSSalil Mehta u16 tc_size[HCLGEVF_MAX_TC_NUM]; 628e2cb1decSSalil Mehta struct hclgevf_desc desc; 629e2cb1decSSalil Mehta u16 roundup_size; 630e2cb1decSSalil Mehta int status; 631ebaf1908SWeihang Li unsigned int i; 632e2cb1decSSalil Mehta 633e2cb1decSSalil Mehta req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 634e2cb1decSSalil Mehta 635e2cb1decSSalil Mehta roundup_size = roundup_pow_of_two(rss_size); 636e2cb1decSSalil Mehta roundup_size = ilog2(roundup_size); 637e2cb1decSSalil Mehta 638e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 639e2cb1decSSalil Mehta tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 640e2cb1decSSalil Mehta tc_size[i] = roundup_size; 641e2cb1decSSalil Mehta tc_offset[i] = rss_size * i; 642e2cb1decSSalil Mehta } 643e2cb1decSSalil Mehta 644e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 645e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 646e4e87715SPeng Li hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 647e2cb1decSSalil Mehta (tc_valid[i] & 0x1)); 648e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 649e2cb1decSSalil Mehta HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 650e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 651e2cb1decSSalil Mehta HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 652e2cb1decSSalil Mehta } 653e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 654e2cb1decSSalil Mehta if (status) 655e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 656e2cb1decSSalil Mehta "VF failed(=%d) to set rss tc mode\n", status); 657e2cb1decSSalil Mehta 658e2cb1decSSalil Mehta return status; 659e2cb1decSSalil Mehta } 660e2cb1decSSalil Mehta 661a638b1d8SJian Shen /* for revision 0x20, vf shared the same rss config with pf */ 662a638b1d8SJian Shen static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 663a638b1d8SJian Shen { 664a638b1d8SJian Shen #define HCLGEVF_RSS_MBX_RESP_LEN 8 665a638b1d8SJian Shen 666a638b1d8SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 667a638b1d8SJian Shen u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 668a638b1d8SJian Shen u16 msg_num, hash_key_index; 669a638b1d8SJian Shen u8 index; 670a638b1d8SJian Shen int ret; 671a638b1d8SJian Shen 672a638b1d8SJian Shen msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 673a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN; 674a638b1d8SJian Shen for (index = 0; index < msg_num; index++) { 675a638b1d8SJian Shen ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_RSS_KEY, 0, 676a638b1d8SJian Shen &index, sizeof(index), 677a638b1d8SJian Shen true, resp_msg, 678a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN); 679a638b1d8SJian Shen if (ret) { 680a638b1d8SJian Shen dev_err(&hdev->pdev->dev, 681a638b1d8SJian Shen "VF get rss hash key from PF failed, ret=%d", 682a638b1d8SJian Shen ret); 683a638b1d8SJian Shen return ret; 684a638b1d8SJian Shen } 685a638b1d8SJian Shen 686a638b1d8SJian Shen hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 687a638b1d8SJian Shen if (index == msg_num - 1) 688a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 689a638b1d8SJian Shen &resp_msg[0], 690a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE - hash_key_index); 691a638b1d8SJian Shen else 692a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 693a638b1d8SJian Shen &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 694a638b1d8SJian Shen } 695a638b1d8SJian Shen 696a638b1d8SJian Shen return 0; 697a638b1d8SJian Shen } 698a638b1d8SJian Shen 699e2cb1decSSalil Mehta static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 700e2cb1decSSalil Mehta u8 *hfunc) 701e2cb1decSSalil Mehta { 702e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 703e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 704a638b1d8SJian Shen int i, ret; 705e2cb1decSSalil Mehta 706374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 707374ad291SJian Shen /* Get hash algorithm */ 708374ad291SJian Shen if (hfunc) { 709374ad291SJian Shen switch (rss_cfg->hash_algo) { 710374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 711374ad291SJian Shen *hfunc = ETH_RSS_HASH_TOP; 712374ad291SJian Shen break; 713374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 714374ad291SJian Shen *hfunc = ETH_RSS_HASH_XOR; 715374ad291SJian Shen break; 716374ad291SJian Shen default: 717374ad291SJian Shen *hfunc = ETH_RSS_HASH_UNKNOWN; 718374ad291SJian Shen break; 719374ad291SJian Shen } 720374ad291SJian Shen } 721374ad291SJian Shen 722374ad291SJian Shen /* Get the RSS Key required by the user */ 723374ad291SJian Shen if (key) 724374ad291SJian Shen memcpy(key, rss_cfg->rss_hash_key, 725374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 726a638b1d8SJian Shen } else { 727a638b1d8SJian Shen if (hfunc) 728a638b1d8SJian Shen *hfunc = ETH_RSS_HASH_TOP; 729a638b1d8SJian Shen if (key) { 730a638b1d8SJian Shen ret = hclgevf_get_rss_hash_key(hdev); 731a638b1d8SJian Shen if (ret) 732a638b1d8SJian Shen return ret; 733a638b1d8SJian Shen memcpy(key, rss_cfg->rss_hash_key, 734a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE); 735a638b1d8SJian Shen } 736374ad291SJian Shen } 737374ad291SJian Shen 738e2cb1decSSalil Mehta if (indir) 739e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 740e2cb1decSSalil Mehta indir[i] = rss_cfg->rss_indirection_tbl[i]; 741e2cb1decSSalil Mehta 742374ad291SJian Shen return 0; 743e2cb1decSSalil Mehta } 744e2cb1decSSalil Mehta 745e2cb1decSSalil Mehta static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 746e2cb1decSSalil Mehta const u8 *key, const u8 hfunc) 747e2cb1decSSalil Mehta { 748e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 749e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 750374ad291SJian Shen int ret, i; 751374ad291SJian Shen 752374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 753374ad291SJian Shen /* Set the RSS Hash Key if specififed by the user */ 754374ad291SJian Shen if (key) { 755374ad291SJian Shen switch (hfunc) { 756374ad291SJian Shen case ETH_RSS_HASH_TOP: 757374ad291SJian Shen rss_cfg->hash_algo = 758374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 759374ad291SJian Shen break; 760374ad291SJian Shen case ETH_RSS_HASH_XOR: 761374ad291SJian Shen rss_cfg->hash_algo = 762374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_SIMPLE; 763374ad291SJian Shen break; 764374ad291SJian Shen case ETH_RSS_HASH_NO_CHANGE: 765374ad291SJian Shen break; 766374ad291SJian Shen default: 767374ad291SJian Shen return -EINVAL; 768374ad291SJian Shen } 769374ad291SJian Shen 770374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 771374ad291SJian Shen key); 772374ad291SJian Shen if (ret) 773374ad291SJian Shen return ret; 774374ad291SJian Shen 775374ad291SJian Shen /* Update the shadow RSS key with user specified qids */ 776374ad291SJian Shen memcpy(rss_cfg->rss_hash_key, key, 777374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 778374ad291SJian Shen } 779374ad291SJian Shen } 780e2cb1decSSalil Mehta 781e2cb1decSSalil Mehta /* update the shadow RSS table with user specified qids */ 782e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 783e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = indir[i]; 784e2cb1decSSalil Mehta 785e2cb1decSSalil Mehta /* update the hardware */ 786e2cb1decSSalil Mehta return hclgevf_set_rss_indir_table(hdev); 787e2cb1decSSalil Mehta } 788e2cb1decSSalil Mehta 789d97b3072SJian Shen static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 790d97b3072SJian Shen { 791d97b3072SJian Shen u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 792d97b3072SJian Shen 793d97b3072SJian Shen if (nfc->data & RXH_L4_B_2_3) 794d97b3072SJian Shen hash_sets |= HCLGEVF_D_PORT_BIT; 795d97b3072SJian Shen else 796d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_PORT_BIT; 797d97b3072SJian Shen 798d97b3072SJian Shen if (nfc->data & RXH_IP_SRC) 799d97b3072SJian Shen hash_sets |= HCLGEVF_S_IP_BIT; 800d97b3072SJian Shen else 801d97b3072SJian Shen hash_sets &= ~HCLGEVF_S_IP_BIT; 802d97b3072SJian Shen 803d97b3072SJian Shen if (nfc->data & RXH_IP_DST) 804d97b3072SJian Shen hash_sets |= HCLGEVF_D_IP_BIT; 805d97b3072SJian Shen else 806d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_IP_BIT; 807d97b3072SJian Shen 808d97b3072SJian Shen if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 809d97b3072SJian Shen hash_sets |= HCLGEVF_V_TAG_BIT; 810d97b3072SJian Shen 811d97b3072SJian Shen return hash_sets; 812d97b3072SJian Shen } 813d97b3072SJian Shen 814d97b3072SJian Shen static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 815d97b3072SJian Shen struct ethtool_rxnfc *nfc) 816d97b3072SJian Shen { 817d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 818d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 819d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 820d97b3072SJian Shen struct hclgevf_desc desc; 821d97b3072SJian Shen u8 tuple_sets; 822d97b3072SJian Shen int ret; 823d97b3072SJian Shen 824d97b3072SJian Shen if (handle->pdev->revision == 0x20) 825d97b3072SJian Shen return -EOPNOTSUPP; 826d97b3072SJian Shen 827d97b3072SJian Shen if (nfc->data & 828d97b3072SJian Shen ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 829d97b3072SJian Shen return -EINVAL; 830d97b3072SJian Shen 831d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 832d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 833d97b3072SJian Shen 834d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 835d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 836d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 837d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 838d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 839d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 840d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 841d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 842d97b3072SJian Shen 843d97b3072SJian Shen tuple_sets = hclgevf_get_rss_hash_bits(nfc); 844d97b3072SJian Shen switch (nfc->flow_type) { 845d97b3072SJian Shen case TCP_V4_FLOW: 846d97b3072SJian Shen req->ipv4_tcp_en = tuple_sets; 847d97b3072SJian Shen break; 848d97b3072SJian Shen case TCP_V6_FLOW: 849d97b3072SJian Shen req->ipv6_tcp_en = tuple_sets; 850d97b3072SJian Shen break; 851d97b3072SJian Shen case UDP_V4_FLOW: 852d97b3072SJian Shen req->ipv4_udp_en = tuple_sets; 853d97b3072SJian Shen break; 854d97b3072SJian Shen case UDP_V6_FLOW: 855d97b3072SJian Shen req->ipv6_udp_en = tuple_sets; 856d97b3072SJian Shen break; 857d97b3072SJian Shen case SCTP_V4_FLOW: 858d97b3072SJian Shen req->ipv4_sctp_en = tuple_sets; 859d97b3072SJian Shen break; 860d97b3072SJian Shen case SCTP_V6_FLOW: 861d97b3072SJian Shen if ((nfc->data & RXH_L4_B_0_1) || 862d97b3072SJian Shen (nfc->data & RXH_L4_B_2_3)) 863d97b3072SJian Shen return -EINVAL; 864d97b3072SJian Shen 865d97b3072SJian Shen req->ipv6_sctp_en = tuple_sets; 866d97b3072SJian Shen break; 867d97b3072SJian Shen case IPV4_FLOW: 868d97b3072SJian Shen req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 869d97b3072SJian Shen break; 870d97b3072SJian Shen case IPV6_FLOW: 871d97b3072SJian Shen req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 872d97b3072SJian Shen break; 873d97b3072SJian Shen default: 874d97b3072SJian Shen return -EINVAL; 875d97b3072SJian Shen } 876d97b3072SJian Shen 877d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 878d97b3072SJian Shen if (ret) { 879d97b3072SJian Shen dev_err(&hdev->pdev->dev, 880d97b3072SJian Shen "Set rss tuple fail, status = %d\n", ret); 881d97b3072SJian Shen return ret; 882d97b3072SJian Shen } 883d97b3072SJian Shen 884d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 885d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 886d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 887d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 888d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 889d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 890d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 891d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 892d97b3072SJian Shen return 0; 893d97b3072SJian Shen } 894d97b3072SJian Shen 895d97b3072SJian Shen static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 896d97b3072SJian Shen struct ethtool_rxnfc *nfc) 897d97b3072SJian Shen { 898d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 899d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 900d97b3072SJian Shen u8 tuple_sets; 901d97b3072SJian Shen 902d97b3072SJian Shen if (handle->pdev->revision == 0x20) 903d97b3072SJian Shen return -EOPNOTSUPP; 904d97b3072SJian Shen 905d97b3072SJian Shen nfc->data = 0; 906d97b3072SJian Shen 907d97b3072SJian Shen switch (nfc->flow_type) { 908d97b3072SJian Shen case TCP_V4_FLOW: 909d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 910d97b3072SJian Shen break; 911d97b3072SJian Shen case UDP_V4_FLOW: 912d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 913d97b3072SJian Shen break; 914d97b3072SJian Shen case TCP_V6_FLOW: 915d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 916d97b3072SJian Shen break; 917d97b3072SJian Shen case UDP_V6_FLOW: 918d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 919d97b3072SJian Shen break; 920d97b3072SJian Shen case SCTP_V4_FLOW: 921d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 922d97b3072SJian Shen break; 923d97b3072SJian Shen case SCTP_V6_FLOW: 924d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 925d97b3072SJian Shen break; 926d97b3072SJian Shen case IPV4_FLOW: 927d97b3072SJian Shen case IPV6_FLOW: 928d97b3072SJian Shen tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 929d97b3072SJian Shen break; 930d97b3072SJian Shen default: 931d97b3072SJian Shen return -EINVAL; 932d97b3072SJian Shen } 933d97b3072SJian Shen 934d97b3072SJian Shen if (!tuple_sets) 935d97b3072SJian Shen return 0; 936d97b3072SJian Shen 937d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_PORT_BIT) 938d97b3072SJian Shen nfc->data |= RXH_L4_B_2_3; 939d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_PORT_BIT) 940d97b3072SJian Shen nfc->data |= RXH_L4_B_0_1; 941d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_IP_BIT) 942d97b3072SJian Shen nfc->data |= RXH_IP_DST; 943d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_IP_BIT) 944d97b3072SJian Shen nfc->data |= RXH_IP_SRC; 945d97b3072SJian Shen 946d97b3072SJian Shen return 0; 947d97b3072SJian Shen } 948d97b3072SJian Shen 949d97b3072SJian Shen static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 950d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg) 951d97b3072SJian Shen { 952d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 953d97b3072SJian Shen struct hclgevf_desc desc; 954d97b3072SJian Shen int ret; 955d97b3072SJian Shen 956d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 957d97b3072SJian Shen 958d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 959d97b3072SJian Shen 960d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 961d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 962d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 963d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 964d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 965d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 966d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 967d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 968d97b3072SJian Shen 969d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 970d97b3072SJian Shen if (ret) 971d97b3072SJian Shen dev_err(&hdev->pdev->dev, 972d97b3072SJian Shen "Configure rss input fail, status = %d\n", ret); 973d97b3072SJian Shen return ret; 974d97b3072SJian Shen } 975d97b3072SJian Shen 976e2cb1decSSalil Mehta static int hclgevf_get_tc_size(struct hnae3_handle *handle) 977e2cb1decSSalil Mehta { 978e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 979e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 980e2cb1decSSalil Mehta 981e2cb1decSSalil Mehta return rss_cfg->rss_size; 982e2cb1decSSalil Mehta } 983e2cb1decSSalil Mehta 984e2cb1decSSalil Mehta static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 985b204bc74SPeng Li int vector_id, 986e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 987e2cb1decSSalil Mehta { 988e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 989e2cb1decSSalil Mehta struct hnae3_ring_chain_node *node; 990e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 991e2cb1decSSalil Mehta struct hclgevf_desc desc; 992b204bc74SPeng Li int i = 0; 993e2cb1decSSalil Mehta int status; 994e2cb1decSSalil Mehta u8 type; 995e2cb1decSSalil Mehta 996e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 997e2cb1decSSalil Mehta 998e2cb1decSSalil Mehta for (node = ring_chain; node; node = node->next) { 9995d02a58dSYunsheng Lin int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 10005d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 10015d02a58dSYunsheng Lin 10025d02a58dSYunsheng Lin if (i == 0) { 10035d02a58dSYunsheng Lin hclgevf_cmd_setup_basic_desc(&desc, 10045d02a58dSYunsheng Lin HCLGEVF_OPC_MBX_VF_TO_PF, 10055d02a58dSYunsheng Lin false); 10065d02a58dSYunsheng Lin type = en ? 10075d02a58dSYunsheng Lin HCLGE_MBX_MAP_RING_TO_VECTOR : 10085d02a58dSYunsheng Lin HCLGE_MBX_UNMAP_RING_TO_VECTOR; 10095d02a58dSYunsheng Lin req->msg[0] = type; 10105d02a58dSYunsheng Lin req->msg[1] = vector_id; 10115d02a58dSYunsheng Lin } 10125d02a58dSYunsheng Lin 10135d02a58dSYunsheng Lin req->msg[idx_offset] = 1014e4e87715SPeng Li hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 10155d02a58dSYunsheng Lin req->msg[idx_offset + 1] = node->tqp_index; 1016e4e87715SPeng Li req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 101779eee410SFuyun Liang HNAE3_RING_GL_IDX_M, 101879eee410SFuyun Liang HNAE3_RING_GL_IDX_S); 101979eee410SFuyun Liang 10205d02a58dSYunsheng Lin i++; 10215d02a58dSYunsheng Lin if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 10225d02a58dSYunsheng Lin HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 10235d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 10245d02a58dSYunsheng Lin !node->next) { 1025e2cb1decSSalil Mehta req->msg[2] = i; 1026e2cb1decSSalil Mehta 1027e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1028e2cb1decSSalil Mehta if (status) { 1029e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1030e2cb1decSSalil Mehta "Map TQP fail, status is %d.\n", 1031e2cb1decSSalil Mehta status); 1032e2cb1decSSalil Mehta return status; 1033e2cb1decSSalil Mehta } 1034e2cb1decSSalil Mehta i = 0; 1035e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 1036e2cb1decSSalil Mehta HCLGEVF_OPC_MBX_VF_TO_PF, 1037e2cb1decSSalil Mehta false); 1038e2cb1decSSalil Mehta req->msg[0] = type; 1039e2cb1decSSalil Mehta req->msg[1] = vector_id; 1040e2cb1decSSalil Mehta } 1041e2cb1decSSalil Mehta } 1042e2cb1decSSalil Mehta 1043e2cb1decSSalil Mehta return 0; 1044e2cb1decSSalil Mehta } 1045e2cb1decSSalil Mehta 1046e2cb1decSSalil Mehta static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1047e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1048e2cb1decSSalil Mehta { 1049b204bc74SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1050b204bc74SPeng Li int vector_id; 1051b204bc74SPeng Li 1052b204bc74SPeng Li vector_id = hclgevf_get_vector_index(hdev, vector); 1053b204bc74SPeng Li if (vector_id < 0) { 1054b204bc74SPeng Li dev_err(&handle->pdev->dev, 1055b204bc74SPeng Li "Get vector index fail. ret =%d\n", vector_id); 1056b204bc74SPeng Li return vector_id; 1057b204bc74SPeng Li } 1058b204bc74SPeng Li 1059b204bc74SPeng Li return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1060e2cb1decSSalil Mehta } 1061e2cb1decSSalil Mehta 1062e2cb1decSSalil Mehta static int hclgevf_unmap_ring_from_vector( 1063e2cb1decSSalil Mehta struct hnae3_handle *handle, 1064e2cb1decSSalil Mehta int vector, 1065e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1066e2cb1decSSalil Mehta { 1067e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1068e2cb1decSSalil Mehta int ret, vector_id; 1069e2cb1decSSalil Mehta 1070dea846e8SHuazhong Tan if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1071dea846e8SHuazhong Tan return 0; 1072dea846e8SHuazhong Tan 1073e2cb1decSSalil Mehta vector_id = hclgevf_get_vector_index(hdev, vector); 1074e2cb1decSSalil Mehta if (vector_id < 0) { 1075e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1076e2cb1decSSalil Mehta "Get vector index fail. ret =%d\n", vector_id); 1077e2cb1decSSalil Mehta return vector_id; 1078e2cb1decSSalil Mehta } 1079e2cb1decSSalil Mehta 1080b204bc74SPeng Li ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 10810d3e6631SYunsheng Lin if (ret) 1082e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1083e2cb1decSSalil Mehta "Unmap ring from vector fail. vector=%d, ret =%d\n", 1084e2cb1decSSalil Mehta vector_id, 1085e2cb1decSSalil Mehta ret); 10860d3e6631SYunsheng Lin 1087e2cb1decSSalil Mehta return ret; 1088e2cb1decSSalil Mehta } 1089e2cb1decSSalil Mehta 10900d3e6631SYunsheng Lin static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 10910d3e6631SYunsheng Lin { 10920d3e6631SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 109303718db9SYunsheng Lin int vector_id; 10940d3e6631SYunsheng Lin 109503718db9SYunsheng Lin vector_id = hclgevf_get_vector_index(hdev, vector); 109603718db9SYunsheng Lin if (vector_id < 0) { 109703718db9SYunsheng Lin dev_err(&handle->pdev->dev, 109803718db9SYunsheng Lin "hclgevf_put_vector get vector index fail. ret =%d\n", 109903718db9SYunsheng Lin vector_id); 110003718db9SYunsheng Lin return vector_id; 110103718db9SYunsheng Lin } 110203718db9SYunsheng Lin 110303718db9SYunsheng Lin hclgevf_free_vector(hdev, vector_id); 1104e2cb1decSSalil Mehta 1105e2cb1decSSalil Mehta return 0; 1106e2cb1decSSalil Mehta } 1107e2cb1decSSalil Mehta 11083b75c3dfSPeng Li static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1109f01f5559SJian Shen bool en_bc_pmc) 1110e2cb1decSSalil Mehta { 1111e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 1112e2cb1decSSalil Mehta struct hclgevf_desc desc; 1113f01f5559SJian Shen int ret; 1114e2cb1decSSalil Mehta 1115e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1116e2cb1decSSalil Mehta 1117e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 1118e2cb1decSSalil Mehta req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 1119f01f5559SJian Shen req->msg[1] = en_bc_pmc ? 1 : 0; 1120e2cb1decSSalil Mehta 1121f01f5559SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1122f01f5559SJian Shen if (ret) 1123e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1124f01f5559SJian Shen "Set promisc mode fail, status is %d.\n", ret); 1125e2cb1decSSalil Mehta 1126f01f5559SJian Shen return ret; 1127e2cb1decSSalil Mehta } 1128e2cb1decSSalil Mehta 1129f01f5559SJian Shen static int hclgevf_set_promisc_mode(struct hclgevf_dev *hdev, bool en_bc_pmc) 1130e2cb1decSSalil Mehta { 1131f01f5559SJian Shen return hclgevf_cmd_set_promisc_mode(hdev, en_bc_pmc); 1132e2cb1decSSalil Mehta } 1133e2cb1decSSalil Mehta 1134ebaf1908SWeihang Li static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, unsigned int tqp_id, 1135e2cb1decSSalil Mehta int stream_id, bool enable) 1136e2cb1decSSalil Mehta { 1137e2cb1decSSalil Mehta struct hclgevf_cfg_com_tqp_queue_cmd *req; 1138e2cb1decSSalil Mehta struct hclgevf_desc desc; 1139e2cb1decSSalil Mehta int status; 1140e2cb1decSSalil Mehta 1141e2cb1decSSalil Mehta req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1142e2cb1decSSalil Mehta 1143e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1144e2cb1decSSalil Mehta false); 1145e2cb1decSSalil Mehta req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1146e2cb1decSSalil Mehta req->stream_id = cpu_to_le16(stream_id); 1147ebaf1908SWeihang Li if (enable) 1148ebaf1908SWeihang Li req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 1149e2cb1decSSalil Mehta 1150e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1151e2cb1decSSalil Mehta if (status) 1152e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1153e2cb1decSSalil Mehta "TQP enable fail, status =%d.\n", status); 1154e2cb1decSSalil Mehta 1155e2cb1decSSalil Mehta return status; 1156e2cb1decSSalil Mehta } 1157e2cb1decSSalil Mehta 1158e2cb1decSSalil Mehta static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1159e2cb1decSSalil Mehta { 1160b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1161e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 1162e2cb1decSSalil Mehta int i; 1163e2cb1decSSalil Mehta 1164b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 1165b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1166e2cb1decSSalil Mehta memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1167e2cb1decSSalil Mehta } 1168e2cb1decSSalil Mehta } 1169e2cb1decSSalil Mehta 1170e2cb1decSSalil Mehta static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1171e2cb1decSSalil Mehta { 1172e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1173e2cb1decSSalil Mehta 1174e2cb1decSSalil Mehta ether_addr_copy(p, hdev->hw.mac.mac_addr); 1175e2cb1decSSalil Mehta } 1176e2cb1decSSalil Mehta 117759098055SFuyun Liang static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 117859098055SFuyun Liang bool is_first) 1179e2cb1decSSalil Mehta { 1180e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1181e2cb1decSSalil Mehta u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1182e2cb1decSSalil Mehta u8 *new_mac_addr = (u8 *)p; 1183e2cb1decSSalil Mehta u8 msg_data[ETH_ALEN * 2]; 118459098055SFuyun Liang u16 subcode; 1185e2cb1decSSalil Mehta int status; 1186e2cb1decSSalil Mehta 1187e2cb1decSSalil Mehta ether_addr_copy(msg_data, new_mac_addr); 1188e2cb1decSSalil Mehta ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 1189e2cb1decSSalil Mehta 119059098055SFuyun Liang subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 119159098055SFuyun Liang HCLGE_MBX_MAC_VLAN_UC_MODIFY; 119259098055SFuyun Liang 1193e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 119463cbf7a9SYufeng Mo subcode, msg_data, sizeof(msg_data), 11952097fdefSJian Shen true, NULL, 0); 1196e2cb1decSSalil Mehta if (!status) 1197e2cb1decSSalil Mehta ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1198e2cb1decSSalil Mehta 1199e2cb1decSSalil Mehta return status; 1200e2cb1decSSalil Mehta } 1201e2cb1decSSalil Mehta 1202e2cb1decSSalil Mehta static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1203e2cb1decSSalil Mehta const unsigned char *addr) 1204e2cb1decSSalil Mehta { 1205e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1206e2cb1decSSalil Mehta 1207e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1208e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_ADD, 1209e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1210e2cb1decSSalil Mehta } 1211e2cb1decSSalil Mehta 1212e2cb1decSSalil Mehta static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1213e2cb1decSSalil Mehta const unsigned char *addr) 1214e2cb1decSSalil Mehta { 1215e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1216e2cb1decSSalil Mehta 1217e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1218e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1219e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1220e2cb1decSSalil Mehta } 1221e2cb1decSSalil Mehta 1222e2cb1decSSalil Mehta static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1223e2cb1decSSalil Mehta const unsigned char *addr) 1224e2cb1decSSalil Mehta { 1225e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1226e2cb1decSSalil Mehta 1227e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1228e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_ADD, 1229e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1230e2cb1decSSalil Mehta } 1231e2cb1decSSalil Mehta 1232e2cb1decSSalil Mehta static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1233e2cb1decSSalil Mehta const unsigned char *addr) 1234e2cb1decSSalil Mehta { 1235e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1236e2cb1decSSalil Mehta 1237e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1238e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1239e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1240e2cb1decSSalil Mehta } 1241e2cb1decSSalil Mehta 1242e2cb1decSSalil Mehta static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1243e2cb1decSSalil Mehta __be16 proto, u16 vlan_id, 1244e2cb1decSSalil Mehta bool is_kill) 1245e2cb1decSSalil Mehta { 1246e2cb1decSSalil Mehta #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1247e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1248e2cb1decSSalil Mehta u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1249fe4144d4SJian Shen int ret; 1250e2cb1decSSalil Mehta 1251b37ce587SYufeng Mo if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1252e2cb1decSSalil Mehta return -EINVAL; 1253e2cb1decSSalil Mehta 1254e2cb1decSSalil Mehta if (proto != htons(ETH_P_8021Q)) 1255e2cb1decSSalil Mehta return -EPROTONOSUPPORT; 1256e2cb1decSSalil Mehta 1257fe4144d4SJian Shen /* When device is resetting, firmware is unable to handle 1258fe4144d4SJian Shen * mailbox. Just record the vlan id, and remove it after 1259fe4144d4SJian Shen * reset finished. 1260fe4144d4SJian Shen */ 1261fe4144d4SJian Shen if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) && is_kill) { 1262fe4144d4SJian Shen set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1263fe4144d4SJian Shen return -EBUSY; 1264fe4144d4SJian Shen } 1265fe4144d4SJian Shen 1266e2cb1decSSalil Mehta msg_data[0] = is_kill; 1267e2cb1decSSalil Mehta memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1268e2cb1decSSalil Mehta memcpy(&msg_data[3], &proto, sizeof(proto)); 1269fe4144d4SJian Shen ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1270e2cb1decSSalil Mehta HCLGE_MBX_VLAN_FILTER, msg_data, 1271e2cb1decSSalil Mehta HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 1272fe4144d4SJian Shen 1273fe4144d4SJian Shen /* When remove hw vlan filter failed, record the vlan id, 1274fe4144d4SJian Shen * and try to remove it from hw later, to be consistence 1275fe4144d4SJian Shen * with stack. 1276fe4144d4SJian Shen */ 1277fe4144d4SJian Shen if (is_kill && ret) 1278fe4144d4SJian Shen set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1279fe4144d4SJian Shen 1280fe4144d4SJian Shen return ret; 1281fe4144d4SJian Shen } 1282fe4144d4SJian Shen 1283fe4144d4SJian Shen static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1284fe4144d4SJian Shen { 1285fe4144d4SJian Shen #define HCLGEVF_MAX_SYNC_COUNT 60 1286fe4144d4SJian Shen struct hnae3_handle *handle = &hdev->nic; 1287fe4144d4SJian Shen int ret, sync_cnt = 0; 1288fe4144d4SJian Shen u16 vlan_id; 1289fe4144d4SJian Shen 1290fe4144d4SJian Shen vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1291fe4144d4SJian Shen while (vlan_id != VLAN_N_VID) { 1292fe4144d4SJian Shen ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1293fe4144d4SJian Shen vlan_id, true); 1294fe4144d4SJian Shen if (ret) 1295fe4144d4SJian Shen return; 1296fe4144d4SJian Shen 1297fe4144d4SJian Shen clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1298fe4144d4SJian Shen sync_cnt++; 1299fe4144d4SJian Shen if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1300fe4144d4SJian Shen return; 1301fe4144d4SJian Shen 1302fe4144d4SJian Shen vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1303fe4144d4SJian Shen } 1304e2cb1decSSalil Mehta } 1305e2cb1decSSalil Mehta 1306b2641e2aSYunsheng Lin static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1307b2641e2aSYunsheng Lin { 1308b2641e2aSYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1309b2641e2aSYunsheng Lin u8 msg_data; 1310b2641e2aSYunsheng Lin 1311b2641e2aSYunsheng Lin msg_data = enable ? 1 : 0; 1312b2641e2aSYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1313b2641e2aSYunsheng Lin HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1314b2641e2aSYunsheng Lin 1, false, NULL, 0); 1315b2641e2aSYunsheng Lin } 1316b2641e2aSYunsheng Lin 13177fa6be4fSHuazhong Tan static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1318e2cb1decSSalil Mehta { 1319e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1320e2cb1decSSalil Mehta u8 msg_data[2]; 13211a426f8bSPeng Li int ret; 1322e2cb1decSSalil Mehta 132363cbf7a9SYufeng Mo memcpy(msg_data, &queue_id, sizeof(queue_id)); 1324e2cb1decSSalil Mehta 13251a426f8bSPeng Li /* disable vf queue before send queue reset msg to PF */ 13261a426f8bSPeng Li ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 13271a426f8bSPeng Li if (ret) 13287fa6be4fSHuazhong Tan return ret; 13291a426f8bSPeng Li 13307fa6be4fSHuazhong Tan return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 133163cbf7a9SYufeng Mo sizeof(msg_data), true, NULL, 0); 1332e2cb1decSSalil Mehta } 1333e2cb1decSSalil Mehta 1334818f1675SYunsheng Lin static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1335818f1675SYunsheng Lin { 1336818f1675SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1337818f1675SYunsheng Lin 1338818f1675SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu, 1339818f1675SYunsheng Lin sizeof(new_mtu), true, NULL, 0); 1340818f1675SYunsheng Lin } 1341818f1675SYunsheng Lin 13426988eb2aSSalil Mehta static int hclgevf_notify_client(struct hclgevf_dev *hdev, 13436988eb2aSSalil Mehta enum hnae3_reset_notify_type type) 13446988eb2aSSalil Mehta { 13456988eb2aSSalil Mehta struct hnae3_client *client = hdev->nic_client; 13466988eb2aSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 13476a5f6fa3SHuazhong Tan int ret; 13486988eb2aSSalil Mehta 134925d1817cSHuazhong Tan if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 135025d1817cSHuazhong Tan !client) 135125d1817cSHuazhong Tan return 0; 135225d1817cSHuazhong Tan 13536988eb2aSSalil Mehta if (!client->ops->reset_notify) 13546988eb2aSSalil Mehta return -EOPNOTSUPP; 13556988eb2aSSalil Mehta 13566a5f6fa3SHuazhong Tan ret = client->ops->reset_notify(handle, type); 13576a5f6fa3SHuazhong Tan if (ret) 13586a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 13596a5f6fa3SHuazhong Tan type, ret); 13606a5f6fa3SHuazhong Tan 13616a5f6fa3SHuazhong Tan return ret; 13626988eb2aSSalil Mehta } 13636988eb2aSSalil Mehta 13646ff3cf07SHuazhong Tan static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 13656ff3cf07SHuazhong Tan { 13666ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 13676ff3cf07SHuazhong Tan 13686ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DONE, &hdev->flr_state); 13696ff3cf07SHuazhong Tan } 13706ff3cf07SHuazhong Tan 13716ff3cf07SHuazhong Tan static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev, 13726ff3cf07SHuazhong Tan unsigned long delay_us, 13736ff3cf07SHuazhong Tan unsigned long wait_cnt) 13746ff3cf07SHuazhong Tan { 13756ff3cf07SHuazhong Tan unsigned long cnt = 0; 13766ff3cf07SHuazhong Tan 13776ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) && 13786ff3cf07SHuazhong Tan cnt++ < wait_cnt) 13796ff3cf07SHuazhong Tan usleep_range(delay_us, delay_us * 2); 13806ff3cf07SHuazhong Tan 13816ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) { 13826ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 13836ff3cf07SHuazhong Tan "flr wait timeout\n"); 13846ff3cf07SHuazhong Tan return -ETIMEDOUT; 13856ff3cf07SHuazhong Tan } 13866ff3cf07SHuazhong Tan 13876ff3cf07SHuazhong Tan return 0; 13886ff3cf07SHuazhong Tan } 13896ff3cf07SHuazhong Tan 13906988eb2aSSalil Mehta static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 13916988eb2aSSalil Mehta { 1392aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_US 20000 1393aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_CNT 2000 1394aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1395aa5c4f17SHuazhong Tan (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1396aa5c4f17SHuazhong Tan 1397aa5c4f17SHuazhong Tan u32 val; 1398aa5c4f17SHuazhong Tan int ret; 13996988eb2aSSalil Mehta 14006988eb2aSSalil Mehta /* wait to check the hardware reset completion status */ 1401aa5c4f17SHuazhong Tan val = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1402aa5c4f17SHuazhong Tan dev_info(&hdev->pdev->dev, "checking vf resetting status: %x\n", val); 1403aa5c4f17SHuazhong Tan 14046ff3cf07SHuazhong Tan if (hdev->reset_type == HNAE3_FLR_RESET) 14056ff3cf07SHuazhong Tan return hclgevf_flr_poll_timeout(hdev, 14066ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_US, 14076ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_CNT); 14086ff3cf07SHuazhong Tan 1409aa5c4f17SHuazhong Tan ret = readl_poll_timeout(hdev->hw.io_base + HCLGEVF_RST_ING, val, 1410aa5c4f17SHuazhong Tan !(val & HCLGEVF_RST_ING_BITS), 1411aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_US, 1412aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 14136988eb2aSSalil Mehta 14146988eb2aSSalil Mehta /* hardware completion status should be available by this time */ 1415aa5c4f17SHuazhong Tan if (ret) { 1416aa5c4f17SHuazhong Tan dev_err(&hdev->pdev->dev, 14176988eb2aSSalil Mehta "could'nt get reset done status from h/w, timeout!\n"); 1418aa5c4f17SHuazhong Tan return ret; 14196988eb2aSSalil Mehta } 14206988eb2aSSalil Mehta 14216988eb2aSSalil Mehta /* we will wait a bit more to let reset of the stack to complete. This 14226988eb2aSSalil Mehta * might happen in case reset assertion was made by PF. Yes, this also 14236988eb2aSSalil Mehta * means we might end up waiting bit more even for VF reset. 14246988eb2aSSalil Mehta */ 14256988eb2aSSalil Mehta msleep(5000); 14266988eb2aSSalil Mehta 14276988eb2aSSalil Mehta return 0; 14286988eb2aSSalil Mehta } 14296988eb2aSSalil Mehta 14306988eb2aSSalil Mehta static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 14316988eb2aSSalil Mehta { 14327a01c897SSalil Mehta int ret; 14337a01c897SSalil Mehta 14346988eb2aSSalil Mehta /* uninitialize the nic client */ 14356a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 14366a5f6fa3SHuazhong Tan if (ret) 14376a5f6fa3SHuazhong Tan return ret; 14386988eb2aSSalil Mehta 14397a01c897SSalil Mehta /* re-initialize the hclge device */ 14409c6f7085SHuazhong Tan ret = hclgevf_reset_hdev(hdev); 14417a01c897SSalil Mehta if (ret) { 14427a01c897SSalil Mehta dev_err(&hdev->pdev->dev, 14437a01c897SSalil Mehta "hclge device re-init failed, VF is disabled!\n"); 14447a01c897SSalil Mehta return ret; 14457a01c897SSalil Mehta } 14466988eb2aSSalil Mehta 14476988eb2aSSalil Mehta /* bring up the nic client again */ 14486a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 14496a5f6fa3SHuazhong Tan if (ret) 14506a5f6fa3SHuazhong Tan return ret; 14516988eb2aSSalil Mehta 14521f609492SYunsheng Lin return hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT); 14536988eb2aSSalil Mehta } 14546988eb2aSSalil Mehta 1455dea846e8SHuazhong Tan static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1456dea846e8SHuazhong Tan { 1457ada13ee3SHuazhong Tan #define HCLGEVF_RESET_SYNC_TIME 100 1458ada13ee3SHuazhong Tan 1459dea846e8SHuazhong Tan int ret = 0; 1460dea846e8SHuazhong Tan 1461dea846e8SHuazhong Tan switch (hdev->reset_type) { 1462dea846e8SHuazhong Tan case HNAE3_VF_FUNC_RESET: 1463dea846e8SHuazhong Tan ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1464dea846e8SHuazhong Tan 0, true, NULL, sizeof(u8)); 1465c88a6e7dSHuazhong Tan hdev->rst_stats.vf_func_rst_cnt++; 1466dea846e8SHuazhong Tan break; 14676ff3cf07SHuazhong Tan case HNAE3_FLR_RESET: 14686ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1469c88a6e7dSHuazhong Tan hdev->rst_stats.flr_rst_cnt++; 14706ff3cf07SHuazhong Tan break; 1471dea846e8SHuazhong Tan default: 1472dea846e8SHuazhong Tan break; 1473dea846e8SHuazhong Tan } 1474dea846e8SHuazhong Tan 1475ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1476ada13ee3SHuazhong Tan /* inform hardware that preparatory work is done */ 1477ada13ee3SHuazhong Tan msleep(HCLGEVF_RESET_SYNC_TIME); 1478ada13ee3SHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 1479ada13ee3SHuazhong Tan HCLGEVF_NIC_CMQ_ENABLE); 1480dea846e8SHuazhong Tan dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1481dea846e8SHuazhong Tan hdev->reset_type, ret); 1482dea846e8SHuazhong Tan 1483dea846e8SHuazhong Tan return ret; 1484dea846e8SHuazhong Tan } 1485dea846e8SHuazhong Tan 1486bbe6540eSHuazhong Tan static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1487bbe6540eSHuazhong Tan { 1488bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt++; 1489bbe6540eSHuazhong Tan dev_err(&hdev->pdev->dev, "failed to reset VF(%d)\n", 1490bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt); 1491bbe6540eSHuazhong Tan 1492bbe6540eSHuazhong Tan if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1493bbe6540eSHuazhong Tan set_bit(hdev->reset_type, &hdev->reset_pending); 1494bbe6540eSHuazhong Tan 1495bbe6540eSHuazhong Tan if (hclgevf_is_reset_pending(hdev)) { 1496bbe6540eSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1497bbe6540eSHuazhong Tan hclgevf_reset_task_schedule(hdev); 1498bbe6540eSHuazhong Tan } else { 1499bbe6540eSHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 1500bbe6540eSHuazhong Tan HCLGEVF_NIC_CMQ_ENABLE); 1501bbe6540eSHuazhong Tan } 1502bbe6540eSHuazhong Tan } 1503bbe6540eSHuazhong Tan 15046988eb2aSSalil Mehta static int hclgevf_reset(struct hclgevf_dev *hdev) 15056988eb2aSSalil Mehta { 1506dea846e8SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 15076988eb2aSSalil Mehta int ret; 15086988eb2aSSalil Mehta 1509dea846e8SHuazhong Tan /* Initialize ae_dev reset status as well, in case enet layer wants to 1510dea846e8SHuazhong Tan * know if device is undergoing reset 1511dea846e8SHuazhong Tan */ 1512dea846e8SHuazhong Tan ae_dev->reset_type = hdev->reset_type; 1513c88a6e7dSHuazhong Tan hdev->rst_stats.rst_cnt++; 15146988eb2aSSalil Mehta rtnl_lock(); 15156988eb2aSSalil Mehta 15166988eb2aSSalil Mehta /* bring down the nic to stop any ongoing TX/RX */ 15176a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 15186a5f6fa3SHuazhong Tan if (ret) 15196a5f6fa3SHuazhong Tan goto err_reset_lock; 15206988eb2aSSalil Mehta 152129118ab9SHuazhong Tan rtnl_unlock(); 152229118ab9SHuazhong Tan 15236a5f6fa3SHuazhong Tan ret = hclgevf_reset_prepare_wait(hdev); 15246a5f6fa3SHuazhong Tan if (ret) 15256a5f6fa3SHuazhong Tan goto err_reset; 1526dea846e8SHuazhong Tan 15276988eb2aSSalil Mehta /* check if VF could successfully fetch the hardware reset completion 15286988eb2aSSalil Mehta * status from the hardware 15296988eb2aSSalil Mehta */ 15306988eb2aSSalil Mehta ret = hclgevf_reset_wait(hdev); 15316988eb2aSSalil Mehta if (ret) { 15326988eb2aSSalil Mehta /* can't do much in this situation, will disable VF */ 15336988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, 15346988eb2aSSalil Mehta "VF failed(=%d) to fetch H/W reset completion status\n", 15356988eb2aSSalil Mehta ret); 15366a5f6fa3SHuazhong Tan goto err_reset; 15376988eb2aSSalil Mehta } 15386988eb2aSSalil Mehta 1539c88a6e7dSHuazhong Tan hdev->rst_stats.hw_rst_done_cnt++; 1540c88a6e7dSHuazhong Tan 154129118ab9SHuazhong Tan rtnl_lock(); 154229118ab9SHuazhong Tan 15436988eb2aSSalil Mehta /* now, re-initialize the nic client and ae device*/ 15446988eb2aSSalil Mehta ret = hclgevf_reset_stack(hdev); 15456a5f6fa3SHuazhong Tan if (ret) { 15466988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 15476a5f6fa3SHuazhong Tan goto err_reset_lock; 15486a5f6fa3SHuazhong Tan } 15496988eb2aSSalil Mehta 15506988eb2aSSalil Mehta /* bring up the nic to enable TX/RX again */ 15516a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 15526a5f6fa3SHuazhong Tan if (ret) 15536a5f6fa3SHuazhong Tan goto err_reset_lock; 15546988eb2aSSalil Mehta 15556988eb2aSSalil Mehta rtnl_unlock(); 15566988eb2aSSalil Mehta 1557b644a8d4SHuazhong Tan hdev->last_reset_time = jiffies; 1558b644a8d4SHuazhong Tan ae_dev->reset_type = HNAE3_NONE_RESET; 1559c88a6e7dSHuazhong Tan hdev->rst_stats.rst_done_cnt++; 1560bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt = 0; 1561b644a8d4SHuazhong Tan 15626988eb2aSSalil Mehta return ret; 15636a5f6fa3SHuazhong Tan err_reset_lock: 15646a5f6fa3SHuazhong Tan rtnl_unlock(); 15656a5f6fa3SHuazhong Tan err_reset: 1566bbe6540eSHuazhong Tan hclgevf_reset_err_handle(hdev); 15676a5f6fa3SHuazhong Tan 15686a5f6fa3SHuazhong Tan return ret; 15696988eb2aSSalil Mehta } 15706988eb2aSSalil Mehta 1571720bd583SHuazhong Tan static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1572720bd583SHuazhong Tan unsigned long *addr) 1573720bd583SHuazhong Tan { 1574720bd583SHuazhong Tan enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1575720bd583SHuazhong Tan 1576dea846e8SHuazhong Tan /* return the highest priority reset level amongst all */ 1577b90fcc5bSHuazhong Tan if (test_bit(HNAE3_VF_RESET, addr)) { 1578b90fcc5bSHuazhong Tan rst_level = HNAE3_VF_RESET; 1579b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_RESET, addr); 1580b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1581b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1582b90fcc5bSHuazhong Tan } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1583dea846e8SHuazhong Tan rst_level = HNAE3_VF_FULL_RESET; 1584dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FULL_RESET, addr); 1585dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1586aa5c4f17SHuazhong Tan } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1587aa5c4f17SHuazhong Tan rst_level = HNAE3_VF_PF_FUNC_RESET; 1588aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1589aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1590dea846e8SHuazhong Tan } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1591dea846e8SHuazhong Tan rst_level = HNAE3_VF_FUNC_RESET; 1592dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 15936ff3cf07SHuazhong Tan } else if (test_bit(HNAE3_FLR_RESET, addr)) { 15946ff3cf07SHuazhong Tan rst_level = HNAE3_FLR_RESET; 15956ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_RESET, addr); 1596720bd583SHuazhong Tan } 1597720bd583SHuazhong Tan 1598720bd583SHuazhong Tan return rst_level; 1599720bd583SHuazhong Tan } 1600720bd583SHuazhong Tan 16016ae4e733SShiju Jose static void hclgevf_reset_event(struct pci_dev *pdev, 16026ae4e733SShiju Jose struct hnae3_handle *handle) 16036d4c3981SSalil Mehta { 16046ff3cf07SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 16056ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 16066d4c3981SSalil Mehta 16076d4c3981SSalil Mehta dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 16086d4c3981SSalil Mehta 16096ff3cf07SHuazhong Tan if (hdev->default_reset_request) 16100742ed7cSHuazhong Tan hdev->reset_level = 1611720bd583SHuazhong Tan hclgevf_get_reset_level(hdev, 1612720bd583SHuazhong Tan &hdev->default_reset_request); 1613720bd583SHuazhong Tan else 1614dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 16156d4c3981SSalil Mehta 1616436667d2SSalil Mehta /* reset of this VF requested */ 1617436667d2SSalil Mehta set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1618436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 16196d4c3981SSalil Mehta 16200742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 16216d4c3981SSalil Mehta } 16226d4c3981SSalil Mehta 1623720bd583SHuazhong Tan static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1624720bd583SHuazhong Tan enum hnae3_reset_type rst_type) 1625720bd583SHuazhong Tan { 1626720bd583SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1627720bd583SHuazhong Tan 1628720bd583SHuazhong Tan set_bit(rst_type, &hdev->default_reset_request); 1629720bd583SHuazhong Tan } 1630720bd583SHuazhong Tan 16316ff3cf07SHuazhong Tan static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 16326ff3cf07SHuazhong Tan { 16336ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_MS 100 16346ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_CNT 50 16356ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 16366ff3cf07SHuazhong Tan int cnt = 0; 16376ff3cf07SHuazhong Tan 16386ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 16396ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DONE, &hdev->flr_state); 16406ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request); 16416ff3cf07SHuazhong Tan hclgevf_reset_event(hdev->pdev, NULL); 16426ff3cf07SHuazhong Tan 16436ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) && 16446ff3cf07SHuazhong Tan cnt++ < HCLGEVF_FLR_WAIT_CNT) 16456ff3cf07SHuazhong Tan msleep(HCLGEVF_FLR_WAIT_MS); 16466ff3cf07SHuazhong Tan 16476ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state)) 16486ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 16496ff3cf07SHuazhong Tan "flr wait down timeout: %d\n", cnt); 16506ff3cf07SHuazhong Tan } 16516ff3cf07SHuazhong Tan 1652e2cb1decSSalil Mehta static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1653e2cb1decSSalil Mehta { 1654e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1655e2cb1decSSalil Mehta 1656e2cb1decSSalil Mehta return hdev->fw_version; 1657e2cb1decSSalil Mehta } 1658e2cb1decSSalil Mehta 1659e2cb1decSSalil Mehta static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1660e2cb1decSSalil Mehta { 1661e2cb1decSSalil Mehta struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1662e2cb1decSSalil Mehta 1663e2cb1decSSalil Mehta vector->vector_irq = pci_irq_vector(hdev->pdev, 1664e2cb1decSSalil Mehta HCLGEVF_MISC_VECTOR_NUM); 1665e2cb1decSSalil Mehta vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1666e2cb1decSSalil Mehta /* vector status always valid for Vector 0 */ 1667e2cb1decSSalil Mehta hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1668e2cb1decSSalil Mehta hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1669e2cb1decSSalil Mehta 1670e2cb1decSSalil Mehta hdev->num_msi_left -= 1; 1671e2cb1decSSalil Mehta hdev->num_msi_used += 1; 1672e2cb1decSSalil Mehta } 1673e2cb1decSSalil Mehta 167435a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 167535a1e503SSalil Mehta { 1676acfc3d55SHuazhong Tan if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) && 1677acfc3d55SHuazhong Tan !test_bit(HCLGEVF_STATE_REMOVING, &hdev->state)) { 167835a1e503SSalil Mehta set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 167935a1e503SSalil Mehta schedule_work(&hdev->rst_service_task); 168035a1e503SSalil Mehta } 168135a1e503SSalil Mehta } 168235a1e503SSalil Mehta 168307a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1684e2cb1decSSalil Mehta { 168507a0556aSSalil Mehta if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) && 168607a0556aSSalil Mehta !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) { 168707a0556aSSalil Mehta set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1688e2cb1decSSalil Mehta schedule_work(&hdev->mbx_service_task); 1689e2cb1decSSalil Mehta } 169007a0556aSSalil Mehta } 1691e2cb1decSSalil Mehta 1692e2cb1decSSalil Mehta static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 1693e2cb1decSSalil Mehta { 1694e2cb1decSSalil Mehta if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 1695e2cb1decSSalil Mehta !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 1696e2cb1decSSalil Mehta schedule_work(&hdev->service_task); 1697e2cb1decSSalil Mehta } 1698e2cb1decSSalil Mehta 1699436667d2SSalil Mehta static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev) 1700436667d2SSalil Mehta { 170107a0556aSSalil Mehta /* if we have any pending mailbox event then schedule the mbx task */ 170207a0556aSSalil Mehta if (hdev->mbx_event_pending) 170307a0556aSSalil Mehta hclgevf_mbx_task_schedule(hdev); 170407a0556aSSalil Mehta 1705436667d2SSalil Mehta if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state)) 1706436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 1707436667d2SSalil Mehta } 1708436667d2SSalil Mehta 1709e2cb1decSSalil Mehta static void hclgevf_service_timer(struct timer_list *t) 1710e2cb1decSSalil Mehta { 1711e2cb1decSSalil Mehta struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 1712e2cb1decSSalil Mehta 1713b37ce587SYufeng Mo mod_timer(&hdev->service_timer, jiffies + 1714b37ce587SYufeng Mo HCLGEVF_GENERAL_TASK_INTERVAL * HZ); 1715e2cb1decSSalil Mehta 1716db01afebSliuzhongzhu hdev->stats_timer++; 1717e2cb1decSSalil Mehta hclgevf_task_schedule(hdev); 1718e2cb1decSSalil Mehta } 1719e2cb1decSSalil Mehta 172035a1e503SSalil Mehta static void hclgevf_reset_service_task(struct work_struct *work) 172135a1e503SSalil Mehta { 172235a1e503SSalil Mehta struct hclgevf_dev *hdev = 172335a1e503SSalil Mehta container_of(work, struct hclgevf_dev, rst_service_task); 1724a8dedb65SSalil Mehta int ret; 172535a1e503SSalil Mehta 172635a1e503SSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 172735a1e503SSalil Mehta return; 172835a1e503SSalil Mehta 172935a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 173035a1e503SSalil Mehta 1731436667d2SSalil Mehta if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1732436667d2SSalil Mehta &hdev->reset_state)) { 1733436667d2SSalil Mehta /* PF has initmated that it is about to reset the hardware. 17349b2f3477SWeihang Li * We now have to poll & check if hardware has actually 17359b2f3477SWeihang Li * completed the reset sequence. On hardware reset completion, 17369b2f3477SWeihang Li * VF needs to reset the client and ae device. 173735a1e503SSalil Mehta */ 1738436667d2SSalil Mehta hdev->reset_attempts = 0; 1739436667d2SSalil Mehta 1740dea846e8SHuazhong Tan hdev->last_reset_time = jiffies; 1741dea846e8SHuazhong Tan while ((hdev->reset_type = 1742dea846e8SHuazhong Tan hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 1743dea846e8SHuazhong Tan != HNAE3_NONE_RESET) { 17446988eb2aSSalil Mehta ret = hclgevf_reset(hdev); 17456988eb2aSSalil Mehta if (ret) 1746dea846e8SHuazhong Tan dev_err(&hdev->pdev->dev, 1747dea846e8SHuazhong Tan "VF stack reset failed %d.\n", ret); 1748dea846e8SHuazhong Tan } 1749436667d2SSalil Mehta } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1750436667d2SSalil Mehta &hdev->reset_state)) { 1751436667d2SSalil Mehta /* we could be here when either of below happens: 17529b2f3477SWeihang Li * 1. reset was initiated due to watchdog timeout caused by 1753436667d2SSalil Mehta * a. IMP was earlier reset and our TX got choked down and 1754436667d2SSalil Mehta * which resulted in watchdog reacting and inducing VF 1755436667d2SSalil Mehta * reset. This also means our cmdq would be unreliable. 1756436667d2SSalil Mehta * b. problem in TX due to other lower layer(example link 1757436667d2SSalil Mehta * layer not functioning properly etc.) 1758436667d2SSalil Mehta * 2. VF reset might have been initiated due to some config 1759436667d2SSalil Mehta * change. 1760436667d2SSalil Mehta * 1761436667d2SSalil Mehta * NOTE: Theres no clear way to detect above cases than to react 1762436667d2SSalil Mehta * to the response of PF for this reset request. PF will ack the 1763436667d2SSalil Mehta * 1b and 2. cases but we will not get any intimation about 1a 1764436667d2SSalil Mehta * from PF as cmdq would be in unreliable state i.e. mailbox 1765436667d2SSalil Mehta * communication between PF and VF would be broken. 1766436667d2SSalil Mehta */ 1767436667d2SSalil Mehta 1768436667d2SSalil Mehta /* if we are never geting into pending state it means either: 1769436667d2SSalil Mehta * 1. PF is not receiving our request which could be due to IMP 1770436667d2SSalil Mehta * reset 1771436667d2SSalil Mehta * 2. PF is screwed 1772436667d2SSalil Mehta * We cannot do much for 2. but to check first we can try reset 1773436667d2SSalil Mehta * our PCIe + stack and see if it alleviates the problem. 1774436667d2SSalil Mehta */ 1775436667d2SSalil Mehta if (hdev->reset_attempts > 3) { 1776436667d2SSalil Mehta /* prepare for full reset of stack + pcie interface */ 1777dea846e8SHuazhong Tan set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1778436667d2SSalil Mehta 1779436667d2SSalil Mehta /* "defer" schedule the reset task again */ 1780436667d2SSalil Mehta set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1781436667d2SSalil Mehta } else { 1782436667d2SSalil Mehta hdev->reset_attempts++; 1783436667d2SSalil Mehta 1784dea846e8SHuazhong Tan set_bit(hdev->reset_level, &hdev->reset_pending); 1785dea846e8SHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1786436667d2SSalil Mehta } 1787dea846e8SHuazhong Tan hclgevf_reset_task_schedule(hdev); 1788436667d2SSalil Mehta } 178935a1e503SSalil Mehta 179035a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 179135a1e503SSalil Mehta } 179235a1e503SSalil Mehta 1793e2cb1decSSalil Mehta static void hclgevf_mailbox_service_task(struct work_struct *work) 1794e2cb1decSSalil Mehta { 1795e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1796e2cb1decSSalil Mehta 1797e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 1798e2cb1decSSalil Mehta 1799e2cb1decSSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1800e2cb1decSSalil Mehta return; 1801e2cb1decSSalil Mehta 1802e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1803e2cb1decSSalil Mehta 180407a0556aSSalil Mehta hclgevf_mbx_async_handler(hdev); 1805e2cb1decSSalil Mehta 1806e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1807e2cb1decSSalil Mehta } 1808e2cb1decSSalil Mehta 1809a6d818e3SYunsheng Lin static void hclgevf_keep_alive_timer(struct timer_list *t) 1810a6d818e3SYunsheng Lin { 1811a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = from_timer(hdev, t, keep_alive_timer); 1812a6d818e3SYunsheng Lin 1813a6d818e3SYunsheng Lin schedule_work(&hdev->keep_alive_task); 1814b37ce587SYufeng Mo mod_timer(&hdev->keep_alive_timer, jiffies + 1815b37ce587SYufeng Mo HCLGEVF_KEEP_ALIVE_TASK_INTERVAL * HZ); 1816a6d818e3SYunsheng Lin } 1817a6d818e3SYunsheng Lin 1818a6d818e3SYunsheng Lin static void hclgevf_keep_alive_task(struct work_struct *work) 1819a6d818e3SYunsheng Lin { 1820a6d818e3SYunsheng Lin struct hclgevf_dev *hdev; 1821a6d818e3SYunsheng Lin u8 respmsg; 1822a6d818e3SYunsheng Lin int ret; 1823a6d818e3SYunsheng Lin 1824a6d818e3SYunsheng Lin hdev = container_of(work, struct hclgevf_dev, keep_alive_task); 1825c59a85c0SJian Shen 18261416d333SHuazhong Tan if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 1827c59a85c0SJian Shen return; 1828c59a85c0SJian Shen 1829a6d818e3SYunsheng Lin ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL, 183063cbf7a9SYufeng Mo 0, false, &respmsg, sizeof(respmsg)); 1831a6d818e3SYunsheng Lin if (ret) 1832a6d818e3SYunsheng Lin dev_err(&hdev->pdev->dev, 1833a6d818e3SYunsheng Lin "VF sends keep alive cmd failed(=%d)\n", ret); 1834a6d818e3SYunsheng Lin } 1835a6d818e3SYunsheng Lin 1836e2cb1decSSalil Mehta static void hclgevf_service_task(struct work_struct *work) 1837e2cb1decSSalil Mehta { 1838db01afebSliuzhongzhu struct hnae3_handle *handle; 1839e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1840e2cb1decSSalil Mehta 1841e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, service_task); 1842db01afebSliuzhongzhu handle = &hdev->nic; 1843db01afebSliuzhongzhu 1844db01afebSliuzhongzhu if (hdev->stats_timer >= HCLGEVF_STATS_TIMER_INTERVAL) { 1845db01afebSliuzhongzhu hclgevf_tqps_update_stats(handle); 1846db01afebSliuzhongzhu hdev->stats_timer = 0; 1847db01afebSliuzhongzhu } 1848e2cb1decSSalil Mehta 1849e2cb1decSSalil Mehta /* request the link status from the PF. PF would be able to tell VF 1850e2cb1decSSalil Mehta * about such updates in future so we might remove this later 1851e2cb1decSSalil Mehta */ 1852e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1853e2cb1decSSalil Mehta 18549194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 18559194d18bSliuzhongzhu 1856fe4144d4SJian Shen hclgevf_sync_vlan_filter(hdev); 1857fe4144d4SJian Shen 1858436667d2SSalil Mehta hclgevf_deferred_task_schedule(hdev); 1859436667d2SSalil Mehta 1860e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1861e2cb1decSSalil Mehta } 1862e2cb1decSSalil Mehta 1863e2cb1decSSalil Mehta static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1864e2cb1decSSalil Mehta { 1865e2cb1decSSalil Mehta hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1866e2cb1decSSalil Mehta } 1867e2cb1decSSalil Mehta 1868b90fcc5bSHuazhong Tan static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1869b90fcc5bSHuazhong Tan u32 *clearval) 1870e2cb1decSSalil Mehta { 1871b90fcc5bSHuazhong Tan u32 cmdq_src_reg, rst_ing_reg; 1872e2cb1decSSalil Mehta 1873e2cb1decSSalil Mehta /* fetch the events from their corresponding regs */ 1874e2cb1decSSalil Mehta cmdq_src_reg = hclgevf_read_dev(&hdev->hw, 1875e2cb1decSSalil Mehta HCLGEVF_VECTOR0_CMDQ_SRC_REG); 1876e2cb1decSSalil Mehta 1877b90fcc5bSHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_src_reg) { 1878b90fcc5bSHuazhong Tan rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1879b90fcc5bSHuazhong Tan dev_info(&hdev->pdev->dev, 1880b90fcc5bSHuazhong Tan "receive reset interrupt 0x%x!\n", rst_ing_reg); 1881b90fcc5bSHuazhong Tan set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1882b90fcc5bSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1883ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1884b90fcc5bSHuazhong Tan cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RST_INT_B); 1885b90fcc5bSHuazhong Tan *clearval = cmdq_src_reg; 1886c88a6e7dSHuazhong Tan hdev->rst_stats.vf_rst_cnt++; 1887b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_RST; 1888b90fcc5bSHuazhong Tan } 1889b90fcc5bSHuazhong Tan 1890e2cb1decSSalil Mehta /* check for vector0 mailbox(=CMDQ RX) event source */ 1891e2cb1decSSalil Mehta if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 1892e2cb1decSSalil Mehta cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1893e2cb1decSSalil Mehta *clearval = cmdq_src_reg; 1894b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_MBX; 1895e2cb1decSSalil Mehta } 1896e2cb1decSSalil Mehta 1897e2cb1decSSalil Mehta dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 1898e2cb1decSSalil Mehta 1899b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_OTHER; 1900e2cb1decSSalil Mehta } 1901e2cb1decSSalil Mehta 1902e2cb1decSSalil Mehta static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1903e2cb1decSSalil Mehta { 1904e2cb1decSSalil Mehta writel(en ? 1 : 0, vector->addr); 1905e2cb1decSSalil Mehta } 1906e2cb1decSSalil Mehta 1907e2cb1decSSalil Mehta static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1908e2cb1decSSalil Mehta { 1909b90fcc5bSHuazhong Tan enum hclgevf_evt_cause event_cause; 1910e2cb1decSSalil Mehta struct hclgevf_dev *hdev = data; 1911e2cb1decSSalil Mehta u32 clearval; 1912e2cb1decSSalil Mehta 1913e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 1914b90fcc5bSHuazhong Tan event_cause = hclgevf_check_evt_cause(hdev, &clearval); 1915e2cb1decSSalil Mehta 1916b90fcc5bSHuazhong Tan switch (event_cause) { 1917b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_RST: 1918b90fcc5bSHuazhong Tan hclgevf_reset_task_schedule(hdev); 1919b90fcc5bSHuazhong Tan break; 1920b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_MBX: 192107a0556aSSalil Mehta hclgevf_mbx_handler(hdev); 1922b90fcc5bSHuazhong Tan break; 1923b90fcc5bSHuazhong Tan default: 1924b90fcc5bSHuazhong Tan break; 1925b90fcc5bSHuazhong Tan } 1926e2cb1decSSalil Mehta 1927b90fcc5bSHuazhong Tan if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 1928e2cb1decSSalil Mehta hclgevf_clear_event_cause(hdev, clearval); 1929e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 1930b90fcc5bSHuazhong Tan } 1931e2cb1decSSalil Mehta 1932e2cb1decSSalil Mehta return IRQ_HANDLED; 1933e2cb1decSSalil Mehta } 1934e2cb1decSSalil Mehta 1935e2cb1decSSalil Mehta static int hclgevf_configure(struct hclgevf_dev *hdev) 1936e2cb1decSSalil Mehta { 1937e2cb1decSSalil Mehta int ret; 1938e2cb1decSSalil Mehta 193992f11ea1SJian Shen /* get current port based vlan state from PF */ 194092f11ea1SJian Shen ret = hclgevf_get_port_base_vlan_filter_state(hdev); 194192f11ea1SJian Shen if (ret) 194292f11ea1SJian Shen return ret; 194392f11ea1SJian Shen 1944e2cb1decSSalil Mehta /* get queue configuration from PF */ 19456cee6fc3SJian Shen ret = hclgevf_get_queue_info(hdev); 1946e2cb1decSSalil Mehta if (ret) 1947e2cb1decSSalil Mehta return ret; 1948c0425944SPeng Li 1949c0425944SPeng Li /* get queue depth info from PF */ 1950c0425944SPeng Li ret = hclgevf_get_queue_depth(hdev); 1951c0425944SPeng Li if (ret) 1952c0425944SPeng Li return ret; 1953c0425944SPeng Li 19549c3e7130Sliuzhongzhu ret = hclgevf_get_pf_media_type(hdev); 19559c3e7130Sliuzhongzhu if (ret) 19569c3e7130Sliuzhongzhu return ret; 19579c3e7130Sliuzhongzhu 1958e2cb1decSSalil Mehta /* get tc configuration from PF */ 1959e2cb1decSSalil Mehta return hclgevf_get_tc_info(hdev); 1960e2cb1decSSalil Mehta } 1961e2cb1decSSalil Mehta 19627a01c897SSalil Mehta static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 19637a01c897SSalil Mehta { 19647a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 19651154bb26SPeng Li struct hclgevf_dev *hdev; 19667a01c897SSalil Mehta 19677a01c897SSalil Mehta hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 19687a01c897SSalil Mehta if (!hdev) 19697a01c897SSalil Mehta return -ENOMEM; 19707a01c897SSalil Mehta 19717a01c897SSalil Mehta hdev->pdev = pdev; 19727a01c897SSalil Mehta hdev->ae_dev = ae_dev; 19737a01c897SSalil Mehta ae_dev->priv = hdev; 19747a01c897SSalil Mehta 19757a01c897SSalil Mehta return 0; 19767a01c897SSalil Mehta } 19777a01c897SSalil Mehta 1978e2cb1decSSalil Mehta static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 1979e2cb1decSSalil Mehta { 1980e2cb1decSSalil Mehta struct hnae3_handle *roce = &hdev->roce; 1981e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 1982e2cb1decSSalil Mehta 198307acf909SJian Shen roce->rinfo.num_vectors = hdev->num_roce_msix; 1984e2cb1decSSalil Mehta 1985e2cb1decSSalil Mehta if (hdev->num_msi_left < roce->rinfo.num_vectors || 1986e2cb1decSSalil Mehta hdev->num_msi_left == 0) 1987e2cb1decSSalil Mehta return -EINVAL; 1988e2cb1decSSalil Mehta 198907acf909SJian Shen roce->rinfo.base_vector = hdev->roce_base_vector; 1990e2cb1decSSalil Mehta 1991e2cb1decSSalil Mehta roce->rinfo.netdev = nic->kinfo.netdev; 1992e2cb1decSSalil Mehta roce->rinfo.roce_io_base = hdev->hw.io_base; 1993e2cb1decSSalil Mehta 1994e2cb1decSSalil Mehta roce->pdev = nic->pdev; 1995e2cb1decSSalil Mehta roce->ae_algo = nic->ae_algo; 1996e2cb1decSSalil Mehta roce->numa_node_mask = nic->numa_node_mask; 1997e2cb1decSSalil Mehta 1998e2cb1decSSalil Mehta return 0; 1999e2cb1decSSalil Mehta } 2000e2cb1decSSalil Mehta 2001b26a6feaSPeng Li static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 2002b26a6feaSPeng Li { 2003b26a6feaSPeng Li struct hclgevf_cfg_gro_status_cmd *req; 2004b26a6feaSPeng Li struct hclgevf_desc desc; 2005b26a6feaSPeng Li int ret; 2006b26a6feaSPeng Li 2007b26a6feaSPeng Li if (!hnae3_dev_gro_supported(hdev)) 2008b26a6feaSPeng Li return 0; 2009b26a6feaSPeng Li 2010b26a6feaSPeng Li hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 2011b26a6feaSPeng Li false); 2012b26a6feaSPeng Li req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2013b26a6feaSPeng Li 2014b26a6feaSPeng Li req->gro_en = cpu_to_le16(en ? 1 : 0); 2015b26a6feaSPeng Li 2016b26a6feaSPeng Li ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2017b26a6feaSPeng Li if (ret) 2018b26a6feaSPeng Li dev_err(&hdev->pdev->dev, 2019b26a6feaSPeng Li "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2020b26a6feaSPeng Li 2021b26a6feaSPeng Li return ret; 2022b26a6feaSPeng Li } 2023b26a6feaSPeng Li 2024e2cb1decSSalil Mehta static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2025e2cb1decSSalil Mehta { 2026e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2027e2cb1decSSalil Mehta int i, ret; 2028e2cb1decSSalil Mehta 2029e2cb1decSSalil Mehta rss_cfg->rss_size = hdev->rss_size_max; 2030e2cb1decSSalil Mehta 2031374ad291SJian Shen if (hdev->pdev->revision >= 0x21) { 2032472d7eceSJian Shen rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 2033472d7eceSJian Shen memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 2034374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 2035374ad291SJian Shen 2036374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 2037374ad291SJian Shen rss_cfg->rss_hash_key); 2038374ad291SJian Shen if (ret) 2039374ad291SJian Shen return ret; 2040d97b3072SJian Shen 2041d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = 2042d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2043d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = 2044d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2045d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = 2046d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2047d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = 2048d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2049d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = 2050d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2051d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = 2052d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2053d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = 2054d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2055d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = 2056d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2057d97b3072SJian Shen 2058d97b3072SJian Shen ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 2059d97b3072SJian Shen if (ret) 2060d97b3072SJian Shen return ret; 2061d97b3072SJian Shen 2062374ad291SJian Shen } 2063374ad291SJian Shen 20649b2f3477SWeihang Li /* Initialize RSS indirect table */ 2065e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 2066e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max; 2067e2cb1decSSalil Mehta 2068e2cb1decSSalil Mehta ret = hclgevf_set_rss_indir_table(hdev); 2069e2cb1decSSalil Mehta if (ret) 2070e2cb1decSSalil Mehta return ret; 2071e2cb1decSSalil Mehta 2072e2cb1decSSalil Mehta return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max); 2073e2cb1decSSalil Mehta } 2074e2cb1decSSalil Mehta 2075e2cb1decSSalil Mehta static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2076e2cb1decSSalil Mehta { 2077e2cb1decSSalil Mehta return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2078e2cb1decSSalil Mehta false); 2079e2cb1decSSalil Mehta } 2080e2cb1decSSalil Mehta 20818cdb992fSJian Shen static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 20828cdb992fSJian Shen { 20838cdb992fSJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 20848cdb992fSJian Shen 20858cdb992fSJian Shen if (enable) { 20868cdb992fSJian Shen mod_timer(&hdev->service_timer, jiffies + HZ); 20878cdb992fSJian Shen } else { 20888cdb992fSJian Shen del_timer_sync(&hdev->service_timer); 20898cdb992fSJian Shen cancel_work_sync(&hdev->service_task); 20908cdb992fSJian Shen clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 20918cdb992fSJian Shen } 20928cdb992fSJian Shen } 20938cdb992fSJian Shen 2094e2cb1decSSalil Mehta static int hclgevf_ae_start(struct hnae3_handle *handle) 2095e2cb1decSSalil Mehta { 2096e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2097e2cb1decSSalil Mehta 2098e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 2099e2cb1decSSalil Mehta 2100e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 2101e2cb1decSSalil Mehta 21029194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 21039194d18bSliuzhongzhu 2104e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2105e2cb1decSSalil Mehta 2106e2cb1decSSalil Mehta return 0; 2107e2cb1decSSalil Mehta } 2108e2cb1decSSalil Mehta 2109e2cb1decSSalil Mehta static void hclgevf_ae_stop(struct hnae3_handle *handle) 2110e2cb1decSSalil Mehta { 2111e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 211239cfbc9cSHuazhong Tan int i; 2113e2cb1decSSalil Mehta 21142f7e4896SFuyun Liang set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 21152f7e4896SFuyun Liang 2116146e92c1SHuazhong Tan if (hdev->reset_type != HNAE3_VF_RESET) 211739cfbc9cSHuazhong Tan for (i = 0; i < handle->kinfo.num_tqps; i++) 2118146e92c1SHuazhong Tan if (hclgevf_reset_tqp(handle, i)) 2119146e92c1SHuazhong Tan break; 212039cfbc9cSHuazhong Tan 2121e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 21228cc6c1f7SFuyun Liang hclgevf_update_link_status(hdev, 0); 2123e2cb1decSSalil Mehta } 2124e2cb1decSSalil Mehta 2125a6d818e3SYunsheng Lin static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2126a6d818e3SYunsheng Lin { 2127a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2128a6d818e3SYunsheng Lin u8 msg_data; 2129a6d818e3SYunsheng Lin 2130a6d818e3SYunsheng Lin msg_data = alive ? 1 : 0; 2131a6d818e3SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE, 2132a6d818e3SYunsheng Lin 0, &msg_data, 1, false, NULL, 0); 2133a6d818e3SYunsheng Lin } 2134a6d818e3SYunsheng Lin 2135a6d818e3SYunsheng Lin static int hclgevf_client_start(struct hnae3_handle *handle) 2136a6d818e3SYunsheng Lin { 2137a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2138e233516eSHuazhong Tan int ret; 2139e233516eSHuazhong Tan 2140e233516eSHuazhong Tan ret = hclgevf_set_alive(handle, true); 2141e233516eSHuazhong Tan if (ret) 2142e233516eSHuazhong Tan return ret; 2143a6d818e3SYunsheng Lin 2144b37ce587SYufeng Mo mod_timer(&hdev->keep_alive_timer, jiffies + 2145b37ce587SYufeng Mo HCLGEVF_KEEP_ALIVE_TASK_INTERVAL * HZ); 2146e233516eSHuazhong Tan 2147e233516eSHuazhong Tan return 0; 2148a6d818e3SYunsheng Lin } 2149a6d818e3SYunsheng Lin 2150a6d818e3SYunsheng Lin static void hclgevf_client_stop(struct hnae3_handle *handle) 2151a6d818e3SYunsheng Lin { 2152a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2153a6d818e3SYunsheng Lin int ret; 2154a6d818e3SYunsheng Lin 2155a6d818e3SYunsheng Lin ret = hclgevf_set_alive(handle, false); 2156a6d818e3SYunsheng Lin if (ret) 2157a6d818e3SYunsheng Lin dev_warn(&hdev->pdev->dev, 2158a6d818e3SYunsheng Lin "%s failed %d\n", __func__, ret); 2159a6d818e3SYunsheng Lin 2160a6d818e3SYunsheng Lin del_timer_sync(&hdev->keep_alive_timer); 2161a6d818e3SYunsheng Lin cancel_work_sync(&hdev->keep_alive_task); 2162a6d818e3SYunsheng Lin } 2163a6d818e3SYunsheng Lin 2164e2cb1decSSalil Mehta static void hclgevf_state_init(struct hclgevf_dev *hdev) 2165e2cb1decSSalil Mehta { 2166e2cb1decSSalil Mehta /* setup tasks for the MBX */ 2167e2cb1decSSalil Mehta INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 2168e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2169e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2170e2cb1decSSalil Mehta 2171e2cb1decSSalil Mehta /* setup tasks for service timer */ 2172e2cb1decSSalil Mehta timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 2173e2cb1decSSalil Mehta 2174e2cb1decSSalil Mehta INIT_WORK(&hdev->service_task, hclgevf_service_task); 2175e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2176e2cb1decSSalil Mehta 217735a1e503SSalil Mehta INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task); 217835a1e503SSalil Mehta 2179e2cb1decSSalil Mehta mutex_init(&hdev->mbx_resp.mbx_mutex); 2180e2cb1decSSalil Mehta 2181e2cb1decSSalil Mehta /* bring the device down */ 2182e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2183e2cb1decSSalil Mehta } 2184e2cb1decSSalil Mehta 2185e2cb1decSSalil Mehta static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2186e2cb1decSSalil Mehta { 2187e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2188acfc3d55SHuazhong Tan set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2189e2cb1decSSalil Mehta 2190e233516eSHuazhong Tan if (hdev->keep_alive_timer.function) 2191e233516eSHuazhong Tan del_timer_sync(&hdev->keep_alive_timer); 2192e233516eSHuazhong Tan if (hdev->keep_alive_task.func) 2193e233516eSHuazhong Tan cancel_work_sync(&hdev->keep_alive_task); 2194e2cb1decSSalil Mehta if (hdev->service_timer.function) 2195e2cb1decSSalil Mehta del_timer_sync(&hdev->service_timer); 2196e2cb1decSSalil Mehta if (hdev->service_task.func) 2197e2cb1decSSalil Mehta cancel_work_sync(&hdev->service_task); 2198e2cb1decSSalil Mehta if (hdev->mbx_service_task.func) 2199e2cb1decSSalil Mehta cancel_work_sync(&hdev->mbx_service_task); 220035a1e503SSalil Mehta if (hdev->rst_service_task.func) 220135a1e503SSalil Mehta cancel_work_sync(&hdev->rst_service_task); 2202e2cb1decSSalil Mehta 2203e2cb1decSSalil Mehta mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2204e2cb1decSSalil Mehta } 2205e2cb1decSSalil Mehta 2206e2cb1decSSalil Mehta static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2207e2cb1decSSalil Mehta { 2208e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2209e2cb1decSSalil Mehta int vectors; 2210e2cb1decSSalil Mehta int i; 2211e2cb1decSSalil Mehta 221207acf909SJian Shen if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) 221307acf909SJian Shen vectors = pci_alloc_irq_vectors(pdev, 221407acf909SJian Shen hdev->roce_base_msix_offset + 1, 221507acf909SJian Shen hdev->num_msi, 221607acf909SJian Shen PCI_IRQ_MSIX); 221707acf909SJian Shen else 2218e2cb1decSSalil Mehta vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 2219e2cb1decSSalil Mehta PCI_IRQ_MSI | PCI_IRQ_MSIX); 222007acf909SJian Shen 2221e2cb1decSSalil Mehta if (vectors < 0) { 2222e2cb1decSSalil Mehta dev_err(&pdev->dev, 2223e2cb1decSSalil Mehta "failed(%d) to allocate MSI/MSI-X vectors\n", 2224e2cb1decSSalil Mehta vectors); 2225e2cb1decSSalil Mehta return vectors; 2226e2cb1decSSalil Mehta } 2227e2cb1decSSalil Mehta if (vectors < hdev->num_msi) 2228e2cb1decSSalil Mehta dev_warn(&hdev->pdev->dev, 2229e2cb1decSSalil Mehta "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2230e2cb1decSSalil Mehta hdev->num_msi, vectors); 2231e2cb1decSSalil Mehta 2232e2cb1decSSalil Mehta hdev->num_msi = vectors; 2233e2cb1decSSalil Mehta hdev->num_msi_left = vectors; 2234e2cb1decSSalil Mehta hdev->base_msi_vector = pdev->irq; 223507acf909SJian Shen hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2236e2cb1decSSalil Mehta 2237e2cb1decSSalil Mehta hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2238e2cb1decSSalil Mehta sizeof(u16), GFP_KERNEL); 2239e2cb1decSSalil Mehta if (!hdev->vector_status) { 2240e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2241e2cb1decSSalil Mehta return -ENOMEM; 2242e2cb1decSSalil Mehta } 2243e2cb1decSSalil Mehta 2244e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 2245e2cb1decSSalil Mehta hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2246e2cb1decSSalil Mehta 2247e2cb1decSSalil Mehta hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2248e2cb1decSSalil Mehta sizeof(int), GFP_KERNEL); 2249e2cb1decSSalil Mehta if (!hdev->vector_irq) { 2250862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2251e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2252e2cb1decSSalil Mehta return -ENOMEM; 2253e2cb1decSSalil Mehta } 2254e2cb1decSSalil Mehta 2255e2cb1decSSalil Mehta return 0; 2256e2cb1decSSalil Mehta } 2257e2cb1decSSalil Mehta 2258e2cb1decSSalil Mehta static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2259e2cb1decSSalil Mehta { 2260e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2261e2cb1decSSalil Mehta 2262862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2263862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_irq); 2264e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2265e2cb1decSSalil Mehta } 2266e2cb1decSSalil Mehta 2267e2cb1decSSalil Mehta static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2268e2cb1decSSalil Mehta { 2269e2cb1decSSalil Mehta int ret = 0; 2270e2cb1decSSalil Mehta 2271e2cb1decSSalil Mehta hclgevf_get_misc_vector(hdev); 2272e2cb1decSSalil Mehta 2273e2cb1decSSalil Mehta ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2274e2cb1decSSalil Mehta 0, "hclgevf_cmd", hdev); 2275e2cb1decSSalil Mehta if (ret) { 2276e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2277e2cb1decSSalil Mehta hdev->misc_vector.vector_irq); 2278e2cb1decSSalil Mehta return ret; 2279e2cb1decSSalil Mehta } 2280e2cb1decSSalil Mehta 22811819e409SXi Wang hclgevf_clear_event_cause(hdev, 0); 22821819e409SXi Wang 2283e2cb1decSSalil Mehta /* enable misc. vector(vector 0) */ 2284e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2285e2cb1decSSalil Mehta 2286e2cb1decSSalil Mehta return ret; 2287e2cb1decSSalil Mehta } 2288e2cb1decSSalil Mehta 2289e2cb1decSSalil Mehta static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2290e2cb1decSSalil Mehta { 2291e2cb1decSSalil Mehta /* disable misc vector(vector 0) */ 2292e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 22931819e409SXi Wang synchronize_irq(hdev->misc_vector.vector_irq); 2294e2cb1decSSalil Mehta free_irq(hdev->misc_vector.vector_irq, hdev); 2295e2cb1decSSalil Mehta hclgevf_free_vector(hdev, 0); 2296e2cb1decSSalil Mehta } 2297e2cb1decSSalil Mehta 2298bb87be87SYonglong Liu static void hclgevf_info_show(struct hclgevf_dev *hdev) 2299bb87be87SYonglong Liu { 2300bb87be87SYonglong Liu struct device *dev = &hdev->pdev->dev; 2301bb87be87SYonglong Liu 2302bb87be87SYonglong Liu dev_info(dev, "VF info begin:\n"); 2303bb87be87SYonglong Liu 2304bb87be87SYonglong Liu dev_info(dev, "Task queue pairs numbers: %d\n", hdev->num_tqps); 2305bb87be87SYonglong Liu dev_info(dev, "Desc num per TX queue: %d\n", hdev->num_tx_desc); 2306bb87be87SYonglong Liu dev_info(dev, "Desc num per RX queue: %d\n", hdev->num_rx_desc); 2307bb87be87SYonglong Liu dev_info(dev, "Numbers of vports: %d\n", hdev->num_alloc_vport); 2308bb87be87SYonglong Liu dev_info(dev, "HW tc map: %d\n", hdev->hw_tc_map); 2309bb87be87SYonglong Liu dev_info(dev, "PF media type of this VF: %d\n", 2310bb87be87SYonglong Liu hdev->hw.mac.media_type); 2311bb87be87SYonglong Liu 2312bb87be87SYonglong Liu dev_info(dev, "VF info end.\n"); 2313bb87be87SYonglong Liu } 2314bb87be87SYonglong Liu 23151db58f86SHuazhong Tan static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 23161db58f86SHuazhong Tan struct hnae3_client *client) 23171db58f86SHuazhong Tan { 23181db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 23191db58f86SHuazhong Tan int ret; 23201db58f86SHuazhong Tan 23211db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->nic); 23221db58f86SHuazhong Tan if (ret) 23231db58f86SHuazhong Tan return ret; 23241db58f86SHuazhong Tan 23251db58f86SHuazhong Tan set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 23261db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 23271db58f86SHuazhong Tan 23281db58f86SHuazhong Tan if (netif_msg_drv(&hdev->nic)) 23291db58f86SHuazhong Tan hclgevf_info_show(hdev); 23301db58f86SHuazhong Tan 23311db58f86SHuazhong Tan return 0; 23321db58f86SHuazhong Tan } 23331db58f86SHuazhong Tan 23341db58f86SHuazhong Tan static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 23351db58f86SHuazhong Tan struct hnae3_client *client) 23361db58f86SHuazhong Tan { 23371db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 23381db58f86SHuazhong Tan int ret; 23391db58f86SHuazhong Tan 23401db58f86SHuazhong Tan if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 23411db58f86SHuazhong Tan !hdev->nic_client) 23421db58f86SHuazhong Tan return 0; 23431db58f86SHuazhong Tan 23441db58f86SHuazhong Tan ret = hclgevf_init_roce_base_info(hdev); 23451db58f86SHuazhong Tan if (ret) 23461db58f86SHuazhong Tan return ret; 23471db58f86SHuazhong Tan 23481db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->roce); 23491db58f86SHuazhong Tan if (ret) 23501db58f86SHuazhong Tan return ret; 23511db58f86SHuazhong Tan 23521db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 23531db58f86SHuazhong Tan 23541db58f86SHuazhong Tan return 0; 23551db58f86SHuazhong Tan } 23561db58f86SHuazhong Tan 2357e718a93fSPeng Li static int hclgevf_init_client_instance(struct hnae3_client *client, 2358e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2359e2cb1decSSalil Mehta { 2360e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2361e2cb1decSSalil Mehta int ret; 2362e2cb1decSSalil Mehta 2363e2cb1decSSalil Mehta switch (client->type) { 2364e2cb1decSSalil Mehta case HNAE3_CLIENT_KNIC: 2365e2cb1decSSalil Mehta hdev->nic_client = client; 2366e2cb1decSSalil Mehta hdev->nic.client = client; 2367e2cb1decSSalil Mehta 23681db58f86SHuazhong Tan ret = hclgevf_init_nic_client_instance(ae_dev, client); 2369e2cb1decSSalil Mehta if (ret) 237049dd8054SJian Shen goto clear_nic; 2371e2cb1decSSalil Mehta 23721db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, 23731db58f86SHuazhong Tan hdev->roce_client); 2374e2cb1decSSalil Mehta if (ret) 237549dd8054SJian Shen goto clear_roce; 2376d9f28fc2SJian Shen 2377e2cb1decSSalil Mehta break; 2378e2cb1decSSalil Mehta case HNAE3_CLIENT_ROCE: 2379544a7bcdSLijun Ou if (hnae3_dev_roce_supported(hdev)) { 2380e2cb1decSSalil Mehta hdev->roce_client = client; 2381e2cb1decSSalil Mehta hdev->roce.client = client; 2382544a7bcdSLijun Ou } 2383e2cb1decSSalil Mehta 23841db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, client); 2385e2cb1decSSalil Mehta if (ret) 238649dd8054SJian Shen goto clear_roce; 2387e2cb1decSSalil Mehta 2388fa7a4bd5SJian Shen break; 2389fa7a4bd5SJian Shen default: 2390fa7a4bd5SJian Shen return -EINVAL; 2391e2cb1decSSalil Mehta } 2392e2cb1decSSalil Mehta 2393e2cb1decSSalil Mehta return 0; 239449dd8054SJian Shen 239549dd8054SJian Shen clear_nic: 239649dd8054SJian Shen hdev->nic_client = NULL; 239749dd8054SJian Shen hdev->nic.client = NULL; 239849dd8054SJian Shen return ret; 239949dd8054SJian Shen clear_roce: 240049dd8054SJian Shen hdev->roce_client = NULL; 240149dd8054SJian Shen hdev->roce.client = NULL; 240249dd8054SJian Shen return ret; 2403e2cb1decSSalil Mehta } 2404e2cb1decSSalil Mehta 2405e718a93fSPeng Li static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2406e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2407e2cb1decSSalil Mehta { 2408e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2409e718a93fSPeng Li 2410e2cb1decSSalil Mehta /* un-init roce, if it exists */ 241149dd8054SJian Shen if (hdev->roce_client) { 2412e2cb1decSSalil Mehta hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 241349dd8054SJian Shen hdev->roce_client = NULL; 241449dd8054SJian Shen hdev->roce.client = NULL; 241549dd8054SJian Shen } 2416e2cb1decSSalil Mehta 2417e2cb1decSSalil Mehta /* un-init nic/unic, if this was not called by roce client */ 241849dd8054SJian Shen if (client->ops->uninit_instance && hdev->nic_client && 241949dd8054SJian Shen client->type != HNAE3_CLIENT_ROCE) { 242025d1817cSHuazhong Tan clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 242125d1817cSHuazhong Tan 2422e2cb1decSSalil Mehta client->ops->uninit_instance(&hdev->nic, 0); 242349dd8054SJian Shen hdev->nic_client = NULL; 242449dd8054SJian Shen hdev->nic.client = NULL; 242549dd8054SJian Shen } 2426e2cb1decSSalil Mehta } 2427e2cb1decSSalil Mehta 2428e2cb1decSSalil Mehta static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2429e2cb1decSSalil Mehta { 2430e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2431e2cb1decSSalil Mehta struct hclgevf_hw *hw; 2432e2cb1decSSalil Mehta int ret; 2433e2cb1decSSalil Mehta 2434e2cb1decSSalil Mehta ret = pci_enable_device(pdev); 2435e2cb1decSSalil Mehta if (ret) { 2436e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed to enable PCI device\n"); 24373e249d3bSFuyun Liang return ret; 2438e2cb1decSSalil Mehta } 2439e2cb1decSSalil Mehta 2440e2cb1decSSalil Mehta ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2441e2cb1decSSalil Mehta if (ret) { 2442e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2443e2cb1decSSalil Mehta goto err_disable_device; 2444e2cb1decSSalil Mehta } 2445e2cb1decSSalil Mehta 2446e2cb1decSSalil Mehta ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2447e2cb1decSSalil Mehta if (ret) { 2448e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2449e2cb1decSSalil Mehta goto err_disable_device; 2450e2cb1decSSalil Mehta } 2451e2cb1decSSalil Mehta 2452e2cb1decSSalil Mehta pci_set_master(pdev); 2453e2cb1decSSalil Mehta hw = &hdev->hw; 2454e2cb1decSSalil Mehta hw->hdev = hdev; 24552e1ea493SPeng Li hw->io_base = pci_iomap(pdev, 2, 0); 2456e2cb1decSSalil Mehta if (!hw->io_base) { 2457e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't map configuration register space\n"); 2458e2cb1decSSalil Mehta ret = -ENOMEM; 2459e2cb1decSSalil Mehta goto err_clr_master; 2460e2cb1decSSalil Mehta } 2461e2cb1decSSalil Mehta 2462e2cb1decSSalil Mehta return 0; 2463e2cb1decSSalil Mehta 2464e2cb1decSSalil Mehta err_clr_master: 2465e2cb1decSSalil Mehta pci_clear_master(pdev); 2466e2cb1decSSalil Mehta pci_release_regions(pdev); 2467e2cb1decSSalil Mehta err_disable_device: 2468e2cb1decSSalil Mehta pci_disable_device(pdev); 24693e249d3bSFuyun Liang 2470e2cb1decSSalil Mehta return ret; 2471e2cb1decSSalil Mehta } 2472e2cb1decSSalil Mehta 2473e2cb1decSSalil Mehta static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2474e2cb1decSSalil Mehta { 2475e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2476e2cb1decSSalil Mehta 2477e2cb1decSSalil Mehta pci_iounmap(pdev, hdev->hw.io_base); 2478e2cb1decSSalil Mehta pci_clear_master(pdev); 2479e2cb1decSSalil Mehta pci_release_regions(pdev); 2480e2cb1decSSalil Mehta pci_disable_device(pdev); 2481e2cb1decSSalil Mehta } 2482e2cb1decSSalil Mehta 248307acf909SJian Shen static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 248407acf909SJian Shen { 248507acf909SJian Shen struct hclgevf_query_res_cmd *req; 248607acf909SJian Shen struct hclgevf_desc desc; 248707acf909SJian Shen int ret; 248807acf909SJian Shen 248907acf909SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 249007acf909SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 249107acf909SJian Shen if (ret) { 249207acf909SJian Shen dev_err(&hdev->pdev->dev, 249307acf909SJian Shen "query vf resource failed, ret = %d.\n", ret); 249407acf909SJian Shen return ret; 249507acf909SJian Shen } 249607acf909SJian Shen 249707acf909SJian Shen req = (struct hclgevf_query_res_cmd *)desc.data; 249807acf909SJian Shen 249907acf909SJian Shen if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) { 250007acf909SJian Shen hdev->roce_base_msix_offset = 250107acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 250207acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_M, 250307acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_S); 250407acf909SJian Shen hdev->num_roce_msix = 250507acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 250607acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 250707acf909SJian Shen 250807acf909SJian Shen /* VF should have NIC vectors and Roce vectors, NIC vectors 250907acf909SJian Shen * are queued before Roce vectors. The offset is fixed to 64. 251007acf909SJian Shen */ 251107acf909SJian Shen hdev->num_msi = hdev->num_roce_msix + 251207acf909SJian Shen hdev->roce_base_msix_offset; 251307acf909SJian Shen } else { 251407acf909SJian Shen hdev->num_msi = 251507acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 251607acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 251707acf909SJian Shen } 251807acf909SJian Shen 251907acf909SJian Shen return 0; 252007acf909SJian Shen } 252107acf909SJian Shen 2522862d969aSHuazhong Tan static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2523862d969aSHuazhong Tan { 2524862d969aSHuazhong Tan struct pci_dev *pdev = hdev->pdev; 2525862d969aSHuazhong Tan int ret = 0; 2526862d969aSHuazhong Tan 2527862d969aSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2528862d969aSHuazhong Tan test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2529862d969aSHuazhong Tan hclgevf_misc_irq_uninit(hdev); 2530862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2531862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2532862d969aSHuazhong Tan } 2533862d969aSHuazhong Tan 2534862d969aSHuazhong Tan if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2535862d969aSHuazhong Tan pci_set_master(pdev); 2536862d969aSHuazhong Tan ret = hclgevf_init_msi(hdev); 2537862d969aSHuazhong Tan if (ret) { 2538862d969aSHuazhong Tan dev_err(&pdev->dev, 2539862d969aSHuazhong Tan "failed(%d) to init MSI/MSI-X\n", ret); 2540862d969aSHuazhong Tan return ret; 2541862d969aSHuazhong Tan } 2542862d969aSHuazhong Tan 2543862d969aSHuazhong Tan ret = hclgevf_misc_irq_init(hdev); 2544862d969aSHuazhong Tan if (ret) { 2545862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2546862d969aSHuazhong Tan dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2547862d969aSHuazhong Tan ret); 2548862d969aSHuazhong Tan return ret; 2549862d969aSHuazhong Tan } 2550862d969aSHuazhong Tan 2551862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2552862d969aSHuazhong Tan } 2553862d969aSHuazhong Tan 2554862d969aSHuazhong Tan return ret; 2555862d969aSHuazhong Tan } 2556862d969aSHuazhong Tan 25579c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2558e2cb1decSSalil Mehta { 25597a01c897SSalil Mehta struct pci_dev *pdev = hdev->pdev; 2560e2cb1decSSalil Mehta int ret; 2561e2cb1decSSalil Mehta 2562862d969aSHuazhong Tan ret = hclgevf_pci_reset(hdev); 2563862d969aSHuazhong Tan if (ret) { 2564862d969aSHuazhong Tan dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2565862d969aSHuazhong Tan return ret; 2566862d969aSHuazhong Tan } 2567862d969aSHuazhong Tan 25689c6f7085SHuazhong Tan ret = hclgevf_cmd_init(hdev); 25699c6f7085SHuazhong Tan if (ret) { 25709c6f7085SHuazhong Tan dev_err(&pdev->dev, "cmd failed %d\n", ret); 25719c6f7085SHuazhong Tan return ret; 25727a01c897SSalil Mehta } 2573e2cb1decSSalil Mehta 25749c6f7085SHuazhong Tan ret = hclgevf_rss_init_hw(hdev); 25759c6f7085SHuazhong Tan if (ret) { 25769c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 25779c6f7085SHuazhong Tan "failed(%d) to initialize RSS\n", ret); 25789c6f7085SHuazhong Tan return ret; 25799c6f7085SHuazhong Tan } 25809c6f7085SHuazhong Tan 2581b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2582b26a6feaSPeng Li if (ret) 2583b26a6feaSPeng Li return ret; 2584b26a6feaSPeng Li 25859c6f7085SHuazhong Tan ret = hclgevf_init_vlan_config(hdev); 25869c6f7085SHuazhong Tan if (ret) { 25879c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 25889c6f7085SHuazhong Tan "failed(%d) to initialize VLAN config\n", ret); 25899c6f7085SHuazhong Tan return ret; 25909c6f7085SHuazhong Tan } 25919c6f7085SHuazhong Tan 25929c6f7085SHuazhong Tan dev_info(&hdev->pdev->dev, "Reset done\n"); 25939c6f7085SHuazhong Tan 25949c6f7085SHuazhong Tan return 0; 25959c6f7085SHuazhong Tan } 25969c6f7085SHuazhong Tan 25979c6f7085SHuazhong Tan static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 25989c6f7085SHuazhong Tan { 25999c6f7085SHuazhong Tan struct pci_dev *pdev = hdev->pdev; 26009c6f7085SHuazhong Tan int ret; 26019c6f7085SHuazhong Tan 2602e2cb1decSSalil Mehta ret = hclgevf_pci_init(hdev); 2603e2cb1decSSalil Mehta if (ret) { 2604e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI initialization failed\n"); 2605e2cb1decSSalil Mehta return ret; 2606e2cb1decSSalil Mehta } 2607e2cb1decSSalil Mehta 26088b0195a3SHuazhong Tan ret = hclgevf_cmd_queue_init(hdev); 26098b0195a3SHuazhong Tan if (ret) { 26108b0195a3SHuazhong Tan dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret); 26118b0195a3SHuazhong Tan goto err_cmd_queue_init; 26128b0195a3SHuazhong Tan } 26138b0195a3SHuazhong Tan 2614eddf0462SYunsheng Lin ret = hclgevf_cmd_init(hdev); 2615eddf0462SYunsheng Lin if (ret) 2616eddf0462SYunsheng Lin goto err_cmd_init; 2617eddf0462SYunsheng Lin 261807acf909SJian Shen /* Get vf resource */ 261907acf909SJian Shen ret = hclgevf_query_vf_resource(hdev); 262007acf909SJian Shen if (ret) { 262107acf909SJian Shen dev_err(&hdev->pdev->dev, 262207acf909SJian Shen "Query vf status error, ret = %d.\n", ret); 26238b0195a3SHuazhong Tan goto err_cmd_init; 262407acf909SJian Shen } 262507acf909SJian Shen 262607acf909SJian Shen ret = hclgevf_init_msi(hdev); 262707acf909SJian Shen if (ret) { 262807acf909SJian Shen dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 26298b0195a3SHuazhong Tan goto err_cmd_init; 263007acf909SJian Shen } 263107acf909SJian Shen 263207acf909SJian Shen hclgevf_state_init(hdev); 2633dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 263407acf909SJian Shen 2635e2cb1decSSalil Mehta ret = hclgevf_misc_irq_init(hdev); 2636e2cb1decSSalil Mehta if (ret) { 2637e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2638e2cb1decSSalil Mehta ret); 2639e2cb1decSSalil Mehta goto err_misc_irq_init; 2640e2cb1decSSalil Mehta } 2641e2cb1decSSalil Mehta 2642862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2643862d969aSHuazhong Tan 2644e2cb1decSSalil Mehta ret = hclgevf_configure(hdev); 2645e2cb1decSSalil Mehta if (ret) { 2646e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2647e2cb1decSSalil Mehta goto err_config; 2648e2cb1decSSalil Mehta } 2649e2cb1decSSalil Mehta 2650e2cb1decSSalil Mehta ret = hclgevf_alloc_tqps(hdev); 2651e2cb1decSSalil Mehta if (ret) { 2652e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2653e2cb1decSSalil Mehta goto err_config; 2654e2cb1decSSalil Mehta } 2655e2cb1decSSalil Mehta 2656e2cb1decSSalil Mehta ret = hclgevf_set_handle_info(hdev); 2657e2cb1decSSalil Mehta if (ret) { 2658e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 2659e2cb1decSSalil Mehta goto err_config; 2660e2cb1decSSalil Mehta } 2661e2cb1decSSalil Mehta 2662b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2663b26a6feaSPeng Li if (ret) 2664b26a6feaSPeng Li goto err_config; 2665b26a6feaSPeng Li 2666f01f5559SJian Shen /* vf is not allowed to enable unicast/multicast promisc mode. 2667f01f5559SJian Shen * For revision 0x20, default to disable broadcast promisc mode, 2668f01f5559SJian Shen * firmware makes sure broadcast packets can be accepted. 2669f01f5559SJian Shen * For revision 0x21, default to enable broadcast promisc mode. 2670f01f5559SJian Shen */ 2671f01f5559SJian Shen ret = hclgevf_set_promisc_mode(hdev, true); 2672f01f5559SJian Shen if (ret) 2673f01f5559SJian Shen goto err_config; 2674f01f5559SJian Shen 2675e2cb1decSSalil Mehta /* Initialize RSS for this VF */ 2676e2cb1decSSalil Mehta ret = hclgevf_rss_init_hw(hdev); 2677e2cb1decSSalil Mehta if (ret) { 2678e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2679e2cb1decSSalil Mehta "failed(%d) to initialize RSS\n", ret); 2680e2cb1decSSalil Mehta goto err_config; 2681e2cb1decSSalil Mehta } 2682e2cb1decSSalil Mehta 2683e2cb1decSSalil Mehta ret = hclgevf_init_vlan_config(hdev); 2684e2cb1decSSalil Mehta if (ret) { 2685e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2686e2cb1decSSalil Mehta "failed(%d) to initialize VLAN config\n", ret); 2687e2cb1decSSalil Mehta goto err_config; 2688e2cb1decSSalil Mehta } 2689e2cb1decSSalil Mehta 26900742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 2691e2cb1decSSalil Mehta pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME); 2692e2cb1decSSalil Mehta 2693e2cb1decSSalil Mehta return 0; 2694e2cb1decSSalil Mehta 2695e2cb1decSSalil Mehta err_config: 2696e2cb1decSSalil Mehta hclgevf_misc_irq_uninit(hdev); 2697e2cb1decSSalil Mehta err_misc_irq_init: 2698e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2699e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 270007acf909SJian Shen err_cmd_init: 27018b0195a3SHuazhong Tan hclgevf_cmd_uninit(hdev); 27028b0195a3SHuazhong Tan err_cmd_queue_init: 2703e2cb1decSSalil Mehta hclgevf_pci_uninit(hdev); 2704862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2705e2cb1decSSalil Mehta return ret; 2706e2cb1decSSalil Mehta } 2707e2cb1decSSalil Mehta 27087a01c897SSalil Mehta static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2709e2cb1decSSalil Mehta { 2710e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2711862d969aSHuazhong Tan 2712862d969aSHuazhong Tan if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2713eddf0462SYunsheng Lin hclgevf_misc_irq_uninit(hdev); 2714e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 27157a01c897SSalil Mehta } 27167a01c897SSalil Mehta 2717e3338205SHuazhong Tan hclgevf_pci_uninit(hdev); 2718862d969aSHuazhong Tan hclgevf_cmd_uninit(hdev); 2719862d969aSHuazhong Tan } 2720862d969aSHuazhong Tan 27217a01c897SSalil Mehta static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 27227a01c897SSalil Mehta { 27237a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 2724a6d818e3SYunsheng Lin struct hclgevf_dev *hdev; 27257a01c897SSalil Mehta int ret; 27267a01c897SSalil Mehta 27277a01c897SSalil Mehta ret = hclgevf_alloc_hdev(ae_dev); 27287a01c897SSalil Mehta if (ret) { 27297a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device allocation failed\n"); 27307a01c897SSalil Mehta return ret; 27317a01c897SSalil Mehta } 27327a01c897SSalil Mehta 27337a01c897SSalil Mehta ret = hclgevf_init_hdev(ae_dev->priv); 2734a6d818e3SYunsheng Lin if (ret) { 27357a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device initialization failed\n"); 27367a01c897SSalil Mehta return ret; 27377a01c897SSalil Mehta } 27387a01c897SSalil Mehta 2739a6d818e3SYunsheng Lin hdev = ae_dev->priv; 2740a6d818e3SYunsheng Lin timer_setup(&hdev->keep_alive_timer, hclgevf_keep_alive_timer, 0); 2741a6d818e3SYunsheng Lin INIT_WORK(&hdev->keep_alive_task, hclgevf_keep_alive_task); 2742a6d818e3SYunsheng Lin 2743a6d818e3SYunsheng Lin return 0; 2744a6d818e3SYunsheng Lin } 2745a6d818e3SYunsheng Lin 27467a01c897SSalil Mehta static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 27477a01c897SSalil Mehta { 27487a01c897SSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 27497a01c897SSalil Mehta 27507a01c897SSalil Mehta hclgevf_uninit_hdev(hdev); 2751e2cb1decSSalil Mehta ae_dev->priv = NULL; 2752e2cb1decSSalil Mehta } 2753e2cb1decSSalil Mehta 2754849e4607SPeng Li static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2755849e4607SPeng Li { 2756849e4607SPeng Li struct hnae3_handle *nic = &hdev->nic; 2757849e4607SPeng Li struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2758849e4607SPeng Li 27598be73621SHuazhong Tan return min_t(u32, hdev->rss_size_max, 27608be73621SHuazhong Tan hdev->num_tqps / kinfo->num_tc); 2761849e4607SPeng Li } 2762849e4607SPeng Li 2763849e4607SPeng Li /** 2764849e4607SPeng Li * hclgevf_get_channels - Get the current channels enabled and max supported. 2765849e4607SPeng Li * @handle: hardware information for network interface 2766849e4607SPeng Li * @ch: ethtool channels structure 2767849e4607SPeng Li * 2768849e4607SPeng Li * We don't support separate tx and rx queues as channels. The other count 2769849e4607SPeng Li * represents how many queues are being used for control. max_combined counts 2770849e4607SPeng Li * how many queue pairs we can support. They may not be mapped 1 to 1 with 2771849e4607SPeng Li * q_vectors since we support a lot more queue pairs than q_vectors. 2772849e4607SPeng Li **/ 2773849e4607SPeng Li static void hclgevf_get_channels(struct hnae3_handle *handle, 2774849e4607SPeng Li struct ethtool_channels *ch) 2775849e4607SPeng Li { 2776849e4607SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2777849e4607SPeng Li 2778849e4607SPeng Li ch->max_combined = hclgevf_get_max_channels(hdev); 2779849e4607SPeng Li ch->other_count = 0; 2780849e4607SPeng Li ch->max_other = 0; 27818be73621SHuazhong Tan ch->combined_count = handle->kinfo.rss_size; 2782849e4607SPeng Li } 2783849e4607SPeng Li 2784cc719218SPeng Li static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 27850d43bf45SHuazhong Tan u16 *alloc_tqps, u16 *max_rss_size) 2786cc719218SPeng Li { 2787cc719218SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2788cc719218SPeng Li 27890d43bf45SHuazhong Tan *alloc_tqps = hdev->num_tqps; 2790cc719218SPeng Li *max_rss_size = hdev->rss_size_max; 2791cc719218SPeng Li } 2792cc719218SPeng Li 2793175ec96bSFuyun Liang static int hclgevf_get_status(struct hnae3_handle *handle) 2794175ec96bSFuyun Liang { 2795175ec96bSFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2796175ec96bSFuyun Liang 2797175ec96bSFuyun Liang return hdev->hw.mac.link; 2798175ec96bSFuyun Liang } 2799175ec96bSFuyun Liang 28004a152de9SFuyun Liang static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 28014a152de9SFuyun Liang u8 *auto_neg, u32 *speed, 28024a152de9SFuyun Liang u8 *duplex) 28034a152de9SFuyun Liang { 28044a152de9SFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 28054a152de9SFuyun Liang 28064a152de9SFuyun Liang if (speed) 28074a152de9SFuyun Liang *speed = hdev->hw.mac.speed; 28084a152de9SFuyun Liang if (duplex) 28094a152de9SFuyun Liang *duplex = hdev->hw.mac.duplex; 28104a152de9SFuyun Liang if (auto_neg) 28114a152de9SFuyun Liang *auto_neg = AUTONEG_DISABLE; 28124a152de9SFuyun Liang } 28134a152de9SFuyun Liang 28144a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 28154a152de9SFuyun Liang u8 duplex) 28164a152de9SFuyun Liang { 28174a152de9SFuyun Liang hdev->hw.mac.speed = speed; 28184a152de9SFuyun Liang hdev->hw.mac.duplex = duplex; 28194a152de9SFuyun Liang } 28204a152de9SFuyun Liang 28211731be4cSYonglong Liu static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 28225c9f6b39SPeng Li { 28235c9f6b39SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 28245c9f6b39SPeng Li 28255c9f6b39SPeng Li return hclgevf_config_gro(hdev, enable); 28265c9f6b39SPeng Li } 28275c9f6b39SPeng Li 282888d10bd6SJian Shen static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 282988d10bd6SJian Shen u8 *module_type) 2830c136b884SPeng Li { 2831c136b884SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 283288d10bd6SJian Shen 2833c136b884SPeng Li if (media_type) 2834c136b884SPeng Li *media_type = hdev->hw.mac.media_type; 283588d10bd6SJian Shen 283688d10bd6SJian Shen if (module_type) 283788d10bd6SJian Shen *module_type = hdev->hw.mac.module_type; 2838c136b884SPeng Li } 2839c136b884SPeng Li 28404d60291bSHuazhong Tan static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 28414d60291bSHuazhong Tan { 28424d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 28434d60291bSHuazhong Tan 2844aa5c4f17SHuazhong Tan return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 28454d60291bSHuazhong Tan } 28464d60291bSHuazhong Tan 28474d60291bSHuazhong Tan static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 28484d60291bSHuazhong Tan { 28494d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 28504d60291bSHuazhong Tan 28514d60291bSHuazhong Tan return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 28524d60291bSHuazhong Tan } 28534d60291bSHuazhong Tan 28544d60291bSHuazhong Tan static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 28554d60291bSHuazhong Tan { 28564d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 28574d60291bSHuazhong Tan 2858c88a6e7dSHuazhong Tan return hdev->rst_stats.hw_rst_done_cnt; 28594d60291bSHuazhong Tan } 28604d60291bSHuazhong Tan 28619194d18bSliuzhongzhu static void hclgevf_get_link_mode(struct hnae3_handle *handle, 28629194d18bSliuzhongzhu unsigned long *supported, 28639194d18bSliuzhongzhu unsigned long *advertising) 28649194d18bSliuzhongzhu { 28659194d18bSliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 28669194d18bSliuzhongzhu 28679194d18bSliuzhongzhu *supported = hdev->hw.mac.supported; 28689194d18bSliuzhongzhu *advertising = hdev->hw.mac.advertising; 28699194d18bSliuzhongzhu } 28709194d18bSliuzhongzhu 28711600c3e5SJian Shen #define MAX_SEPARATE_NUM 4 28721600c3e5SJian Shen #define SEPARATOR_VALUE 0xFFFFFFFF 28731600c3e5SJian Shen #define REG_NUM_PER_LINE 4 28741600c3e5SJian Shen #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 28751600c3e5SJian Shen 28761600c3e5SJian Shen static int hclgevf_get_regs_len(struct hnae3_handle *handle) 28771600c3e5SJian Shen { 28781600c3e5SJian Shen int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 28791600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 28801600c3e5SJian Shen 28811600c3e5SJian Shen cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 28821600c3e5SJian Shen common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 28831600c3e5SJian Shen ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 28841600c3e5SJian Shen tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 28851600c3e5SJian Shen 28861600c3e5SJian Shen return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 28871600c3e5SJian Shen tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 28881600c3e5SJian Shen } 28891600c3e5SJian Shen 28901600c3e5SJian Shen static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 28911600c3e5SJian Shen void *data) 28921600c3e5SJian Shen { 28931600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 28941600c3e5SJian Shen int i, j, reg_um, separator_num; 28951600c3e5SJian Shen u32 *reg = data; 28961600c3e5SJian Shen 28971600c3e5SJian Shen *version = hdev->fw_version; 28981600c3e5SJian Shen 28991600c3e5SJian Shen /* fetching per-VF registers values from VF PCIe register space */ 29001600c3e5SJian Shen reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 29011600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 29021600c3e5SJian Shen for (i = 0; i < reg_um; i++) 29031600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 29041600c3e5SJian Shen for (i = 0; i < separator_num; i++) 29051600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 29061600c3e5SJian Shen 29071600c3e5SJian Shen reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 29081600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 29091600c3e5SJian Shen for (i = 0; i < reg_um; i++) 29101600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 29111600c3e5SJian Shen for (i = 0; i < separator_num; i++) 29121600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 29131600c3e5SJian Shen 29141600c3e5SJian Shen reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 29151600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 29161600c3e5SJian Shen for (j = 0; j < hdev->num_tqps; j++) { 29171600c3e5SJian Shen for (i = 0; i < reg_um; i++) 29181600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 29191600c3e5SJian Shen ring_reg_addr_list[i] + 29201600c3e5SJian Shen 0x200 * j); 29211600c3e5SJian Shen for (i = 0; i < separator_num; i++) 29221600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 29231600c3e5SJian Shen } 29241600c3e5SJian Shen 29251600c3e5SJian Shen reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 29261600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 29271600c3e5SJian Shen for (j = 0; j < hdev->num_msi_used - 1; j++) { 29281600c3e5SJian Shen for (i = 0; i < reg_um; i++) 29291600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 29301600c3e5SJian Shen tqp_intr_reg_addr_list[i] + 29311600c3e5SJian Shen 4 * j); 29321600c3e5SJian Shen for (i = 0; i < separator_num; i++) 29331600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 29341600c3e5SJian Shen } 29351600c3e5SJian Shen } 29361600c3e5SJian Shen 293792f11ea1SJian Shen void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 293892f11ea1SJian Shen u8 *port_base_vlan_info, u8 data_size) 293992f11ea1SJian Shen { 294092f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 294192f11ea1SJian Shen 294292f11ea1SJian Shen rtnl_lock(); 294392f11ea1SJian Shen hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 294492f11ea1SJian Shen rtnl_unlock(); 294592f11ea1SJian Shen 294692f11ea1SJian Shen /* send msg to PF and wait update port based vlan info */ 294792f11ea1SJian Shen hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 294892f11ea1SJian Shen HCLGE_MBX_PORT_BASE_VLAN_CFG, 294992f11ea1SJian Shen port_base_vlan_info, data_size, 295092f11ea1SJian Shen false, NULL, 0); 295192f11ea1SJian Shen 295292f11ea1SJian Shen if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 295392f11ea1SJian Shen nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 295492f11ea1SJian Shen else 295592f11ea1SJian Shen nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 295692f11ea1SJian Shen 295792f11ea1SJian Shen rtnl_lock(); 295892f11ea1SJian Shen hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 295992f11ea1SJian Shen rtnl_unlock(); 296092f11ea1SJian Shen } 296192f11ea1SJian Shen 2962e2cb1decSSalil Mehta static const struct hnae3_ae_ops hclgevf_ops = { 2963e2cb1decSSalil Mehta .init_ae_dev = hclgevf_init_ae_dev, 2964e2cb1decSSalil Mehta .uninit_ae_dev = hclgevf_uninit_ae_dev, 29656ff3cf07SHuazhong Tan .flr_prepare = hclgevf_flr_prepare, 29666ff3cf07SHuazhong Tan .flr_done = hclgevf_flr_done, 2967e718a93fSPeng Li .init_client_instance = hclgevf_init_client_instance, 2968e718a93fSPeng Li .uninit_client_instance = hclgevf_uninit_client_instance, 2969e2cb1decSSalil Mehta .start = hclgevf_ae_start, 2970e2cb1decSSalil Mehta .stop = hclgevf_ae_stop, 2971a6d818e3SYunsheng Lin .client_start = hclgevf_client_start, 2972a6d818e3SYunsheng Lin .client_stop = hclgevf_client_stop, 2973e2cb1decSSalil Mehta .map_ring_to_vector = hclgevf_map_ring_to_vector, 2974e2cb1decSSalil Mehta .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 2975e2cb1decSSalil Mehta .get_vector = hclgevf_get_vector, 29760d3e6631SYunsheng Lin .put_vector = hclgevf_put_vector, 2977e2cb1decSSalil Mehta .reset_queue = hclgevf_reset_tqp, 2978e2cb1decSSalil Mehta .get_mac_addr = hclgevf_get_mac_addr, 2979e2cb1decSSalil Mehta .set_mac_addr = hclgevf_set_mac_addr, 2980e2cb1decSSalil Mehta .add_uc_addr = hclgevf_add_uc_addr, 2981e2cb1decSSalil Mehta .rm_uc_addr = hclgevf_rm_uc_addr, 2982e2cb1decSSalil Mehta .add_mc_addr = hclgevf_add_mc_addr, 2983e2cb1decSSalil Mehta .rm_mc_addr = hclgevf_rm_mc_addr, 2984e2cb1decSSalil Mehta .get_stats = hclgevf_get_stats, 2985e2cb1decSSalil Mehta .update_stats = hclgevf_update_stats, 2986e2cb1decSSalil Mehta .get_strings = hclgevf_get_strings, 2987e2cb1decSSalil Mehta .get_sset_count = hclgevf_get_sset_count, 2988e2cb1decSSalil Mehta .get_rss_key_size = hclgevf_get_rss_key_size, 2989e2cb1decSSalil Mehta .get_rss_indir_size = hclgevf_get_rss_indir_size, 2990e2cb1decSSalil Mehta .get_rss = hclgevf_get_rss, 2991e2cb1decSSalil Mehta .set_rss = hclgevf_set_rss, 2992d97b3072SJian Shen .get_rss_tuple = hclgevf_get_rss_tuple, 2993d97b3072SJian Shen .set_rss_tuple = hclgevf_set_rss_tuple, 2994e2cb1decSSalil Mehta .get_tc_size = hclgevf_get_tc_size, 2995e2cb1decSSalil Mehta .get_fw_version = hclgevf_get_fw_version, 2996e2cb1decSSalil Mehta .set_vlan_filter = hclgevf_set_vlan_filter, 2997b2641e2aSYunsheng Lin .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 29986d4c3981SSalil Mehta .reset_event = hclgevf_reset_event, 2999720bd583SHuazhong Tan .set_default_reset_request = hclgevf_set_def_reset_request, 3000849e4607SPeng Li .get_channels = hclgevf_get_channels, 3001cc719218SPeng Li .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 30021600c3e5SJian Shen .get_regs_len = hclgevf_get_regs_len, 30031600c3e5SJian Shen .get_regs = hclgevf_get_regs, 3004175ec96bSFuyun Liang .get_status = hclgevf_get_status, 30054a152de9SFuyun Liang .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3006c136b884SPeng Li .get_media_type = hclgevf_get_media_type, 30074d60291bSHuazhong Tan .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 30084d60291bSHuazhong Tan .ae_dev_resetting = hclgevf_ae_dev_resetting, 30094d60291bSHuazhong Tan .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 30105c9f6b39SPeng Li .set_gro_en = hclgevf_gro_en, 3011818f1675SYunsheng Lin .set_mtu = hclgevf_set_mtu, 30120c29d191Sliuzhongzhu .get_global_queue_id = hclgevf_get_qid_global, 30138cdb992fSJian Shen .set_timer_task = hclgevf_set_timer_task, 30149194d18bSliuzhongzhu .get_link_mode = hclgevf_get_link_mode, 3015e2cb1decSSalil Mehta }; 3016e2cb1decSSalil Mehta 3017e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf = { 3018e2cb1decSSalil Mehta .ops = &hclgevf_ops, 3019e2cb1decSSalil Mehta .pdev_id_table = ae_algovf_pci_tbl, 3020e2cb1decSSalil Mehta }; 3021e2cb1decSSalil Mehta 3022e2cb1decSSalil Mehta static int hclgevf_init(void) 3023e2cb1decSSalil Mehta { 3024e2cb1decSSalil Mehta pr_info("%s is initializing\n", HCLGEVF_NAME); 3025e2cb1decSSalil Mehta 3026854cf33aSFuyun Liang hnae3_register_ae_algo(&ae_algovf); 3027854cf33aSFuyun Liang 3028854cf33aSFuyun Liang return 0; 3029e2cb1decSSalil Mehta } 3030e2cb1decSSalil Mehta 3031e2cb1decSSalil Mehta static void hclgevf_exit(void) 3032e2cb1decSSalil Mehta { 3033e2cb1decSSalil Mehta hnae3_unregister_ae_algo(&ae_algovf); 3034e2cb1decSSalil Mehta } 3035e2cb1decSSalil Mehta module_init(hclgevf_init); 3036e2cb1decSSalil Mehta module_exit(hclgevf_exit); 3037e2cb1decSSalil Mehta 3038e2cb1decSSalil Mehta MODULE_LICENSE("GPL"); 3039e2cb1decSSalil Mehta MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3040e2cb1decSSalil Mehta MODULE_DESCRIPTION("HCLGEVF Driver"); 3041e2cb1decSSalil Mehta MODULE_VERSION(HCLGEVF_MOD_VERSION); 3042