1e2cb1decSSalil Mehta // SPDX-License-Identifier: GPL-2.0+ 2e2cb1decSSalil Mehta // Copyright (c) 2016-2017 Hisilicon Limited. 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #include <linux/etherdevice.h> 5aa5c4f17SHuazhong Tan #include <linux/iopoll.h> 66988eb2aSSalil Mehta #include <net/rtnetlink.h> 7e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 8e2cb1decSSalil Mehta #include "hclgevf_main.h" 9e2cb1decSSalil Mehta #include "hclge_mbx.h" 10e2cb1decSSalil Mehta #include "hnae3.h" 11e2cb1decSSalil Mehta 12e2cb1decSSalil Mehta #define HCLGEVF_NAME "hclgevf" 13e2cb1decSSalil Mehta 149c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 15e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf; 16e2cb1decSSalil Mehta 17e2cb1decSSalil Mehta static const struct pci_device_id ae_algovf_pci_tbl[] = { 18e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 19e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 20e2cb1decSSalil Mehta /* required last entry */ 21e2cb1decSSalil Mehta {0, } 22e2cb1decSSalil Mehta }; 23e2cb1decSSalil Mehta 242f550a46SYunsheng Lin MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 252f550a46SYunsheng Lin 261600c3e5SJian Shen static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 271600c3e5SJian Shen HCLGEVF_CMDQ_TX_ADDR_H_REG, 281600c3e5SJian Shen HCLGEVF_CMDQ_TX_DEPTH_REG, 291600c3e5SJian Shen HCLGEVF_CMDQ_TX_TAIL_REG, 301600c3e5SJian Shen HCLGEVF_CMDQ_TX_HEAD_REG, 311600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_L_REG, 321600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_H_REG, 331600c3e5SJian Shen HCLGEVF_CMDQ_RX_DEPTH_REG, 341600c3e5SJian Shen HCLGEVF_CMDQ_RX_TAIL_REG, 351600c3e5SJian Shen HCLGEVF_CMDQ_RX_HEAD_REG, 361600c3e5SJian Shen HCLGEVF_VECTOR0_CMDQ_SRC_REG, 371600c3e5SJian Shen HCLGEVF_CMDQ_INTR_STS_REG, 381600c3e5SJian Shen HCLGEVF_CMDQ_INTR_EN_REG, 391600c3e5SJian Shen HCLGEVF_CMDQ_INTR_GEN_REG}; 401600c3e5SJian Shen 411600c3e5SJian Shen static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 421600c3e5SJian Shen HCLGEVF_RST_ING, 431600c3e5SJian Shen HCLGEVF_GRO_EN_REG}; 441600c3e5SJian Shen 451600c3e5SJian Shen static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 461600c3e5SJian Shen HCLGEVF_RING_RX_ADDR_H_REG, 471600c3e5SJian Shen HCLGEVF_RING_RX_BD_NUM_REG, 481600c3e5SJian Shen HCLGEVF_RING_RX_BD_LENGTH_REG, 491600c3e5SJian Shen HCLGEVF_RING_RX_MERGE_EN_REG, 501600c3e5SJian Shen HCLGEVF_RING_RX_TAIL_REG, 511600c3e5SJian Shen HCLGEVF_RING_RX_HEAD_REG, 521600c3e5SJian Shen HCLGEVF_RING_RX_FBD_NUM_REG, 531600c3e5SJian Shen HCLGEVF_RING_RX_OFFSET_REG, 541600c3e5SJian Shen HCLGEVF_RING_RX_FBD_OFFSET_REG, 551600c3e5SJian Shen HCLGEVF_RING_RX_STASH_REG, 561600c3e5SJian Shen HCLGEVF_RING_RX_BD_ERR_REG, 571600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_L_REG, 581600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_H_REG, 591600c3e5SJian Shen HCLGEVF_RING_TX_BD_NUM_REG, 601600c3e5SJian Shen HCLGEVF_RING_TX_PRIORITY_REG, 611600c3e5SJian Shen HCLGEVF_RING_TX_TC_REG, 621600c3e5SJian Shen HCLGEVF_RING_TX_MERGE_EN_REG, 631600c3e5SJian Shen HCLGEVF_RING_TX_TAIL_REG, 641600c3e5SJian Shen HCLGEVF_RING_TX_HEAD_REG, 651600c3e5SJian Shen HCLGEVF_RING_TX_FBD_NUM_REG, 661600c3e5SJian Shen HCLGEVF_RING_TX_OFFSET_REG, 671600c3e5SJian Shen HCLGEVF_RING_TX_EBD_NUM_REG, 681600c3e5SJian Shen HCLGEVF_RING_TX_EBD_OFFSET_REG, 691600c3e5SJian Shen HCLGEVF_RING_TX_BD_ERR_REG, 701600c3e5SJian Shen HCLGEVF_RING_EN_REG}; 711600c3e5SJian Shen 721600c3e5SJian Shen static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 731600c3e5SJian Shen HCLGEVF_TQP_INTR_GL0_REG, 741600c3e5SJian Shen HCLGEVF_TQP_INTR_GL1_REG, 751600c3e5SJian Shen HCLGEVF_TQP_INTR_GL2_REG, 761600c3e5SJian Shen HCLGEVF_TQP_INTR_RL_REG}; 771600c3e5SJian Shen 78e2cb1decSSalil Mehta static inline struct hclgevf_dev *hclgevf_ae_get_hdev( 79e2cb1decSSalil Mehta struct hnae3_handle *handle) 80e2cb1decSSalil Mehta { 81e2cb1decSSalil Mehta return container_of(handle, struct hclgevf_dev, nic); 82e2cb1decSSalil Mehta } 83e2cb1decSSalil Mehta 84e2cb1decSSalil Mehta static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 85e2cb1decSSalil Mehta { 86b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 87e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 88e2cb1decSSalil Mehta struct hclgevf_desc desc; 89e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 90e2cb1decSSalil Mehta int status; 91e2cb1decSSalil Mehta int i; 92e2cb1decSSalil Mehta 93b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 94b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 95e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 96e2cb1decSSalil Mehta HCLGEVF_OPC_QUERY_RX_STATUS, 97e2cb1decSSalil Mehta true); 98e2cb1decSSalil Mehta 99e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 100e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 101e2cb1decSSalil Mehta if (status) { 102e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 103e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 104e2cb1decSSalil Mehta status, i); 105e2cb1decSSalil Mehta return status; 106e2cb1decSSalil Mehta } 107e2cb1decSSalil Mehta tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 108cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 109e2cb1decSSalil Mehta 110e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 111e2cb1decSSalil Mehta true); 112e2cb1decSSalil Mehta 113e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 114e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 115e2cb1decSSalil Mehta if (status) { 116e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 117e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 118e2cb1decSSalil Mehta status, i); 119e2cb1decSSalil Mehta return status; 120e2cb1decSSalil Mehta } 121e2cb1decSSalil Mehta tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 122cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 123e2cb1decSSalil Mehta } 124e2cb1decSSalil Mehta 125e2cb1decSSalil Mehta return 0; 126e2cb1decSSalil Mehta } 127e2cb1decSSalil Mehta 128e2cb1decSSalil Mehta static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 129e2cb1decSSalil Mehta { 130e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo = &handle->kinfo; 131e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 132e2cb1decSSalil Mehta u64 *buff = data; 133e2cb1decSSalil Mehta int i; 134e2cb1decSSalil Mehta 135b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 136b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 137e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 138e2cb1decSSalil Mehta } 139e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 140b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 141e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 142e2cb1decSSalil Mehta } 143e2cb1decSSalil Mehta 144e2cb1decSSalil Mehta return buff; 145e2cb1decSSalil Mehta } 146e2cb1decSSalil Mehta 147e2cb1decSSalil Mehta static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 148e2cb1decSSalil Mehta { 149b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 150e2cb1decSSalil Mehta 151b4f1d303SJian Shen return kinfo->num_tqps * 2; 152e2cb1decSSalil Mehta } 153e2cb1decSSalil Mehta 154e2cb1decSSalil Mehta static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 155e2cb1decSSalil Mehta { 156b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 157e2cb1decSSalil Mehta u8 *buff = data; 158e2cb1decSSalil Mehta int i = 0; 159e2cb1decSSalil Mehta 160b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 161b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 162e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1630c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 164e2cb1decSSalil Mehta tqp->index); 165e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 166e2cb1decSSalil Mehta } 167e2cb1decSSalil Mehta 168b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 169b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 170e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1710c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 172e2cb1decSSalil Mehta tqp->index); 173e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 174e2cb1decSSalil Mehta } 175e2cb1decSSalil Mehta 176e2cb1decSSalil Mehta return buff; 177e2cb1decSSalil Mehta } 178e2cb1decSSalil Mehta 179e2cb1decSSalil Mehta static void hclgevf_update_stats(struct hnae3_handle *handle, 180e2cb1decSSalil Mehta struct net_device_stats *net_stats) 181e2cb1decSSalil Mehta { 182e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 183e2cb1decSSalil Mehta int status; 184e2cb1decSSalil Mehta 185e2cb1decSSalil Mehta status = hclgevf_tqps_update_stats(handle); 186e2cb1decSSalil Mehta if (status) 187e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 188e2cb1decSSalil Mehta "VF update of TQPS stats fail, status = %d.\n", 189e2cb1decSSalil Mehta status); 190e2cb1decSSalil Mehta } 191e2cb1decSSalil Mehta 192e2cb1decSSalil Mehta static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 193e2cb1decSSalil Mehta { 194e2cb1decSSalil Mehta if (strset == ETH_SS_TEST) 195e2cb1decSSalil Mehta return -EOPNOTSUPP; 196e2cb1decSSalil Mehta else if (strset == ETH_SS_STATS) 197e2cb1decSSalil Mehta return hclgevf_tqps_get_sset_count(handle, strset); 198e2cb1decSSalil Mehta 199e2cb1decSSalil Mehta return 0; 200e2cb1decSSalil Mehta } 201e2cb1decSSalil Mehta 202e2cb1decSSalil Mehta static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 203e2cb1decSSalil Mehta u8 *data) 204e2cb1decSSalil Mehta { 205e2cb1decSSalil Mehta u8 *p = (char *)data; 206e2cb1decSSalil Mehta 207e2cb1decSSalil Mehta if (strset == ETH_SS_STATS) 208e2cb1decSSalil Mehta p = hclgevf_tqps_get_strings(handle, p); 209e2cb1decSSalil Mehta } 210e2cb1decSSalil Mehta 211e2cb1decSSalil Mehta static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 212e2cb1decSSalil Mehta { 213e2cb1decSSalil Mehta hclgevf_tqps_get_stats(handle, data); 214e2cb1decSSalil Mehta } 215e2cb1decSSalil Mehta 216e2cb1decSSalil Mehta static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 217e2cb1decSSalil Mehta { 218e2cb1decSSalil Mehta u8 resp_msg; 219e2cb1decSSalil Mehta int status; 220e2cb1decSSalil Mehta 221e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 222e2cb1decSSalil Mehta true, &resp_msg, sizeof(u8)); 223e2cb1decSSalil Mehta if (status) { 224e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 225e2cb1decSSalil Mehta "VF request to get TC info from PF failed %d", 226e2cb1decSSalil Mehta status); 227e2cb1decSSalil Mehta return status; 228e2cb1decSSalil Mehta } 229e2cb1decSSalil Mehta 230e2cb1decSSalil Mehta hdev->hw_tc_map = resp_msg; 231e2cb1decSSalil Mehta 232e2cb1decSSalil Mehta return 0; 233e2cb1decSSalil Mehta } 234e2cb1decSSalil Mehta 2356cee6fc3SJian Shen static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 236e2cb1decSSalil Mehta { 237e2cb1decSSalil Mehta #define HCLGEVF_TQPS_RSS_INFO_LEN 8 238e2cb1decSSalil Mehta u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 239e2cb1decSSalil Mehta int status; 240e2cb1decSSalil Mehta 241e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 242e2cb1decSSalil Mehta true, resp_msg, 243e2cb1decSSalil Mehta HCLGEVF_TQPS_RSS_INFO_LEN); 244e2cb1decSSalil Mehta if (status) { 245e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 246e2cb1decSSalil Mehta "VF request to get tqp info from PF failed %d", 247e2cb1decSSalil Mehta status); 248e2cb1decSSalil Mehta return status; 249e2cb1decSSalil Mehta } 250e2cb1decSSalil Mehta 251e2cb1decSSalil Mehta memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 252e2cb1decSSalil Mehta memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 253e2cb1decSSalil Mehta memcpy(&hdev->num_desc, &resp_msg[4], sizeof(u16)); 254e2cb1decSSalil Mehta memcpy(&hdev->rx_buf_len, &resp_msg[6], sizeof(u16)); 255e2cb1decSSalil Mehta 256e2cb1decSSalil Mehta return 0; 257e2cb1decSSalil Mehta } 258e2cb1decSSalil Mehta 2590c29d191Sliuzhongzhu static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 2600c29d191Sliuzhongzhu { 2610c29d191Sliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2620c29d191Sliuzhongzhu u8 msg_data[2], resp_data[2]; 2630c29d191Sliuzhongzhu u16 qid_in_pf = 0; 2640c29d191Sliuzhongzhu int ret; 2650c29d191Sliuzhongzhu 2660c29d191Sliuzhongzhu memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 2670c29d191Sliuzhongzhu 2680c29d191Sliuzhongzhu ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data, 2690c29d191Sliuzhongzhu 2, true, resp_data, 2); 2700c29d191Sliuzhongzhu if (!ret) 2710c29d191Sliuzhongzhu qid_in_pf = *(u16 *)resp_data; 2720c29d191Sliuzhongzhu 2730c29d191Sliuzhongzhu return qid_in_pf; 2740c29d191Sliuzhongzhu } 2750c29d191Sliuzhongzhu 276e2cb1decSSalil Mehta static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 277e2cb1decSSalil Mehta { 278e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 279e2cb1decSSalil Mehta int i; 280e2cb1decSSalil Mehta 281e2cb1decSSalil Mehta hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 282e2cb1decSSalil Mehta sizeof(struct hclgevf_tqp), GFP_KERNEL); 283e2cb1decSSalil Mehta if (!hdev->htqp) 284e2cb1decSSalil Mehta return -ENOMEM; 285e2cb1decSSalil Mehta 286e2cb1decSSalil Mehta tqp = hdev->htqp; 287e2cb1decSSalil Mehta 288e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 289e2cb1decSSalil Mehta tqp->dev = &hdev->pdev->dev; 290e2cb1decSSalil Mehta tqp->index = i; 291e2cb1decSSalil Mehta 292e2cb1decSSalil Mehta tqp->q.ae_algo = &ae_algovf; 293e2cb1decSSalil Mehta tqp->q.buf_size = hdev->rx_buf_len; 294e2cb1decSSalil Mehta tqp->q.desc_num = hdev->num_desc; 295e2cb1decSSalil Mehta tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 296e2cb1decSSalil Mehta i * HCLGEVF_TQP_REG_SIZE; 297e2cb1decSSalil Mehta 298e2cb1decSSalil Mehta tqp++; 299e2cb1decSSalil Mehta } 300e2cb1decSSalil Mehta 301e2cb1decSSalil Mehta return 0; 302e2cb1decSSalil Mehta } 303e2cb1decSSalil Mehta 304e2cb1decSSalil Mehta static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 305e2cb1decSSalil Mehta { 306e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 307e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo; 308e2cb1decSSalil Mehta u16 new_tqps = hdev->num_tqps; 309e2cb1decSSalil Mehta int i; 310e2cb1decSSalil Mehta 311e2cb1decSSalil Mehta kinfo = &nic->kinfo; 312e2cb1decSSalil Mehta kinfo->num_tc = 0; 313e2cb1decSSalil Mehta kinfo->num_desc = hdev->num_desc; 314e2cb1decSSalil Mehta kinfo->rx_buf_len = hdev->rx_buf_len; 315e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 316e2cb1decSSalil Mehta if (hdev->hw_tc_map & BIT(i)) 317e2cb1decSSalil Mehta kinfo->num_tc++; 318e2cb1decSSalil Mehta 319e2cb1decSSalil Mehta kinfo->rss_size 320e2cb1decSSalil Mehta = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 321e2cb1decSSalil Mehta new_tqps = kinfo->rss_size * kinfo->num_tc; 322e2cb1decSSalil Mehta kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 323e2cb1decSSalil Mehta 324e2cb1decSSalil Mehta kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 325e2cb1decSSalil Mehta sizeof(struct hnae3_queue *), GFP_KERNEL); 326e2cb1decSSalil Mehta if (!kinfo->tqp) 327e2cb1decSSalil Mehta return -ENOMEM; 328e2cb1decSSalil Mehta 329e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 330e2cb1decSSalil Mehta hdev->htqp[i].q.handle = &hdev->nic; 331e2cb1decSSalil Mehta hdev->htqp[i].q.tqp_index = i; 332e2cb1decSSalil Mehta kinfo->tqp[i] = &hdev->htqp[i].q; 333e2cb1decSSalil Mehta } 334e2cb1decSSalil Mehta 335e2cb1decSSalil Mehta return 0; 336e2cb1decSSalil Mehta } 337e2cb1decSSalil Mehta 338e2cb1decSSalil Mehta static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 339e2cb1decSSalil Mehta { 340e2cb1decSSalil Mehta int status; 341e2cb1decSSalil Mehta u8 resp_msg; 342e2cb1decSSalil Mehta 343e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 344e2cb1decSSalil Mehta 0, false, &resp_msg, sizeof(u8)); 345e2cb1decSSalil Mehta if (status) 346e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 347e2cb1decSSalil Mehta "VF failed to fetch link status(%d) from PF", status); 348e2cb1decSSalil Mehta } 349e2cb1decSSalil Mehta 350e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 351e2cb1decSSalil Mehta { 352e2cb1decSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 353e2cb1decSSalil Mehta struct hnae3_client *client; 354e2cb1decSSalil Mehta 355e2cb1decSSalil Mehta client = handle->client; 356e2cb1decSSalil Mehta 357582d37bbSPeng Li link_state = 358582d37bbSPeng Li test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 359582d37bbSPeng Li 360e2cb1decSSalil Mehta if (link_state != hdev->hw.mac.link) { 361e2cb1decSSalil Mehta client->ops->link_status_change(handle, !!link_state); 362e2cb1decSSalil Mehta hdev->hw.mac.link = link_state; 363e2cb1decSSalil Mehta } 364e2cb1decSSalil Mehta } 365e2cb1decSSalil Mehta 366e2cb1decSSalil Mehta static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 367e2cb1decSSalil Mehta { 368e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 369e2cb1decSSalil Mehta int ret; 370e2cb1decSSalil Mehta 371e2cb1decSSalil Mehta nic->ae_algo = &ae_algovf; 372e2cb1decSSalil Mehta nic->pdev = hdev->pdev; 373e2cb1decSSalil Mehta nic->numa_node_mask = hdev->numa_node_mask; 374424eb834SSalil Mehta nic->flags |= HNAE3_SUPPORT_VF; 375e2cb1decSSalil Mehta 376e2cb1decSSalil Mehta if (hdev->ae_dev->dev_type != HNAE3_DEV_KNIC) { 377e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "unsupported device type %d\n", 378e2cb1decSSalil Mehta hdev->ae_dev->dev_type); 379e2cb1decSSalil Mehta return -EINVAL; 380e2cb1decSSalil Mehta } 381e2cb1decSSalil Mehta 382e2cb1decSSalil Mehta ret = hclgevf_knic_setup(hdev); 383e2cb1decSSalil Mehta if (ret) 384e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 385e2cb1decSSalil Mehta ret); 386e2cb1decSSalil Mehta return ret; 387e2cb1decSSalil Mehta } 388e2cb1decSSalil Mehta 389e2cb1decSSalil Mehta static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 390e2cb1decSSalil Mehta { 39136cbbdf6SPeng Li if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 39236cbbdf6SPeng Li dev_warn(&hdev->pdev->dev, 39336cbbdf6SPeng Li "vector(vector_id %d) has been freed.\n", vector_id); 39436cbbdf6SPeng Li return; 39536cbbdf6SPeng Li } 39636cbbdf6SPeng Li 397e2cb1decSSalil Mehta hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 398e2cb1decSSalil Mehta hdev->num_msi_left += 1; 399e2cb1decSSalil Mehta hdev->num_msi_used -= 1; 400e2cb1decSSalil Mehta } 401e2cb1decSSalil Mehta 402e2cb1decSSalil Mehta static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 403e2cb1decSSalil Mehta struct hnae3_vector_info *vector_info) 404e2cb1decSSalil Mehta { 405e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 406e2cb1decSSalil Mehta struct hnae3_vector_info *vector = vector_info; 407e2cb1decSSalil Mehta int alloc = 0; 408e2cb1decSSalil Mehta int i, j; 409e2cb1decSSalil Mehta 410e2cb1decSSalil Mehta vector_num = min(hdev->num_msi_left, vector_num); 411e2cb1decSSalil Mehta 412e2cb1decSSalil Mehta for (j = 0; j < vector_num; j++) { 413e2cb1decSSalil Mehta for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 414e2cb1decSSalil Mehta if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 415e2cb1decSSalil Mehta vector->vector = pci_irq_vector(hdev->pdev, i); 416e2cb1decSSalil Mehta vector->io_addr = hdev->hw.io_base + 417e2cb1decSSalil Mehta HCLGEVF_VECTOR_REG_BASE + 418e2cb1decSSalil Mehta (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 419e2cb1decSSalil Mehta hdev->vector_status[i] = 0; 420e2cb1decSSalil Mehta hdev->vector_irq[i] = vector->vector; 421e2cb1decSSalil Mehta 422e2cb1decSSalil Mehta vector++; 423e2cb1decSSalil Mehta alloc++; 424e2cb1decSSalil Mehta 425e2cb1decSSalil Mehta break; 426e2cb1decSSalil Mehta } 427e2cb1decSSalil Mehta } 428e2cb1decSSalil Mehta } 429e2cb1decSSalil Mehta hdev->num_msi_left -= alloc; 430e2cb1decSSalil Mehta hdev->num_msi_used += alloc; 431e2cb1decSSalil Mehta 432e2cb1decSSalil Mehta return alloc; 433e2cb1decSSalil Mehta } 434e2cb1decSSalil Mehta 435e2cb1decSSalil Mehta static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 436e2cb1decSSalil Mehta { 437e2cb1decSSalil Mehta int i; 438e2cb1decSSalil Mehta 439e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 440e2cb1decSSalil Mehta if (vector == hdev->vector_irq[i]) 441e2cb1decSSalil Mehta return i; 442e2cb1decSSalil Mehta 443e2cb1decSSalil Mehta return -EINVAL; 444e2cb1decSSalil Mehta } 445e2cb1decSSalil Mehta 446374ad291SJian Shen static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 447374ad291SJian Shen const u8 hfunc, const u8 *key) 448374ad291SJian Shen { 449374ad291SJian Shen struct hclgevf_rss_config_cmd *req; 450374ad291SJian Shen struct hclgevf_desc desc; 451374ad291SJian Shen int key_offset; 452374ad291SJian Shen int key_size; 453374ad291SJian Shen int ret; 454374ad291SJian Shen 455374ad291SJian Shen req = (struct hclgevf_rss_config_cmd *)desc.data; 456374ad291SJian Shen 457374ad291SJian Shen for (key_offset = 0; key_offset < 3; key_offset++) { 458374ad291SJian Shen hclgevf_cmd_setup_basic_desc(&desc, 459374ad291SJian Shen HCLGEVF_OPC_RSS_GENERIC_CONFIG, 460374ad291SJian Shen false); 461374ad291SJian Shen 462374ad291SJian Shen req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 463374ad291SJian Shen req->hash_config |= 464374ad291SJian Shen (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 465374ad291SJian Shen 466374ad291SJian Shen if (key_offset == 2) 467374ad291SJian Shen key_size = 468374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE - HCLGEVF_RSS_HASH_KEY_NUM * 2; 469374ad291SJian Shen else 470374ad291SJian Shen key_size = HCLGEVF_RSS_HASH_KEY_NUM; 471374ad291SJian Shen 472374ad291SJian Shen memcpy(req->hash_key, 473374ad291SJian Shen key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 474374ad291SJian Shen 475374ad291SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 476374ad291SJian Shen if (ret) { 477374ad291SJian Shen dev_err(&hdev->pdev->dev, 478374ad291SJian Shen "Configure RSS config fail, status = %d\n", 479374ad291SJian Shen ret); 480374ad291SJian Shen return ret; 481374ad291SJian Shen } 482374ad291SJian Shen } 483374ad291SJian Shen 484374ad291SJian Shen return 0; 485374ad291SJian Shen } 486374ad291SJian Shen 487e2cb1decSSalil Mehta static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 488e2cb1decSSalil Mehta { 489e2cb1decSSalil Mehta return HCLGEVF_RSS_KEY_SIZE; 490e2cb1decSSalil Mehta } 491e2cb1decSSalil Mehta 492e2cb1decSSalil Mehta static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 493e2cb1decSSalil Mehta { 494e2cb1decSSalil Mehta return HCLGEVF_RSS_IND_TBL_SIZE; 495e2cb1decSSalil Mehta } 496e2cb1decSSalil Mehta 497e2cb1decSSalil Mehta static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 498e2cb1decSSalil Mehta { 499e2cb1decSSalil Mehta const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 500e2cb1decSSalil Mehta struct hclgevf_rss_indirection_table_cmd *req; 501e2cb1decSSalil Mehta struct hclgevf_desc desc; 502e2cb1decSSalil Mehta int status; 503e2cb1decSSalil Mehta int i, j; 504e2cb1decSSalil Mehta 505e2cb1decSSalil Mehta req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 506e2cb1decSSalil Mehta 507e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 508e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 509e2cb1decSSalil Mehta false); 510e2cb1decSSalil Mehta req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 511e2cb1decSSalil Mehta req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 512e2cb1decSSalil Mehta for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 513e2cb1decSSalil Mehta req->rss_result[j] = 514e2cb1decSSalil Mehta indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 515e2cb1decSSalil Mehta 516e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 517e2cb1decSSalil Mehta if (status) { 518e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 519e2cb1decSSalil Mehta "VF failed(=%d) to set RSS indirection table\n", 520e2cb1decSSalil Mehta status); 521e2cb1decSSalil Mehta return status; 522e2cb1decSSalil Mehta } 523e2cb1decSSalil Mehta } 524e2cb1decSSalil Mehta 525e2cb1decSSalil Mehta return 0; 526e2cb1decSSalil Mehta } 527e2cb1decSSalil Mehta 528e2cb1decSSalil Mehta static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 529e2cb1decSSalil Mehta { 530e2cb1decSSalil Mehta struct hclgevf_rss_tc_mode_cmd *req; 531e2cb1decSSalil Mehta u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 532e2cb1decSSalil Mehta u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 533e2cb1decSSalil Mehta u16 tc_size[HCLGEVF_MAX_TC_NUM]; 534e2cb1decSSalil Mehta struct hclgevf_desc desc; 535e2cb1decSSalil Mehta u16 roundup_size; 536e2cb1decSSalil Mehta int status; 537e2cb1decSSalil Mehta int i; 538e2cb1decSSalil Mehta 539e2cb1decSSalil Mehta req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 540e2cb1decSSalil Mehta 541e2cb1decSSalil Mehta roundup_size = roundup_pow_of_two(rss_size); 542e2cb1decSSalil Mehta roundup_size = ilog2(roundup_size); 543e2cb1decSSalil Mehta 544e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 545e2cb1decSSalil Mehta tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 546e2cb1decSSalil Mehta tc_size[i] = roundup_size; 547e2cb1decSSalil Mehta tc_offset[i] = rss_size * i; 548e2cb1decSSalil Mehta } 549e2cb1decSSalil Mehta 550e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 551e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 552e4e87715SPeng Li hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 553e2cb1decSSalil Mehta (tc_valid[i] & 0x1)); 554e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 555e2cb1decSSalil Mehta HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 556e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 557e2cb1decSSalil Mehta HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 558e2cb1decSSalil Mehta } 559e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 560e2cb1decSSalil Mehta if (status) 561e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 562e2cb1decSSalil Mehta "VF failed(=%d) to set rss tc mode\n", status); 563e2cb1decSSalil Mehta 564e2cb1decSSalil Mehta return status; 565e2cb1decSSalil Mehta } 566e2cb1decSSalil Mehta 567e2cb1decSSalil Mehta static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 568e2cb1decSSalil Mehta u8 *hfunc) 569e2cb1decSSalil Mehta { 570e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 571e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 572e2cb1decSSalil Mehta int i; 573e2cb1decSSalil Mehta 574374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 575374ad291SJian Shen /* Get hash algorithm */ 576374ad291SJian Shen if (hfunc) { 577374ad291SJian Shen switch (rss_cfg->hash_algo) { 578374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 579374ad291SJian Shen *hfunc = ETH_RSS_HASH_TOP; 580374ad291SJian Shen break; 581374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 582374ad291SJian Shen *hfunc = ETH_RSS_HASH_XOR; 583374ad291SJian Shen break; 584374ad291SJian Shen default: 585374ad291SJian Shen *hfunc = ETH_RSS_HASH_UNKNOWN; 586374ad291SJian Shen break; 587374ad291SJian Shen } 588374ad291SJian Shen } 589374ad291SJian Shen 590374ad291SJian Shen /* Get the RSS Key required by the user */ 591374ad291SJian Shen if (key) 592374ad291SJian Shen memcpy(key, rss_cfg->rss_hash_key, 593374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 594374ad291SJian Shen } 595374ad291SJian Shen 596e2cb1decSSalil Mehta if (indir) 597e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 598e2cb1decSSalil Mehta indir[i] = rss_cfg->rss_indirection_tbl[i]; 599e2cb1decSSalil Mehta 600374ad291SJian Shen return 0; 601e2cb1decSSalil Mehta } 602e2cb1decSSalil Mehta 603e2cb1decSSalil Mehta static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 604e2cb1decSSalil Mehta const u8 *key, const u8 hfunc) 605e2cb1decSSalil Mehta { 606e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 607e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 608374ad291SJian Shen int ret, i; 609374ad291SJian Shen 610374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 611374ad291SJian Shen /* Set the RSS Hash Key if specififed by the user */ 612374ad291SJian Shen if (key) { 613374ad291SJian Shen switch (hfunc) { 614374ad291SJian Shen case ETH_RSS_HASH_TOP: 615374ad291SJian Shen rss_cfg->hash_algo = 616374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 617374ad291SJian Shen break; 618374ad291SJian Shen case ETH_RSS_HASH_XOR: 619374ad291SJian Shen rss_cfg->hash_algo = 620374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_SIMPLE; 621374ad291SJian Shen break; 622374ad291SJian Shen case ETH_RSS_HASH_NO_CHANGE: 623374ad291SJian Shen break; 624374ad291SJian Shen default: 625374ad291SJian Shen return -EINVAL; 626374ad291SJian Shen } 627374ad291SJian Shen 628374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 629374ad291SJian Shen key); 630374ad291SJian Shen if (ret) 631374ad291SJian Shen return ret; 632374ad291SJian Shen 633374ad291SJian Shen /* Update the shadow RSS key with user specified qids */ 634374ad291SJian Shen memcpy(rss_cfg->rss_hash_key, key, 635374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 636374ad291SJian Shen } 637374ad291SJian Shen } 638e2cb1decSSalil Mehta 639e2cb1decSSalil Mehta /* update the shadow RSS table with user specified qids */ 640e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 641e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = indir[i]; 642e2cb1decSSalil Mehta 643e2cb1decSSalil Mehta /* update the hardware */ 644e2cb1decSSalil Mehta return hclgevf_set_rss_indir_table(hdev); 645e2cb1decSSalil Mehta } 646e2cb1decSSalil Mehta 647d97b3072SJian Shen static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 648d97b3072SJian Shen { 649d97b3072SJian Shen u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 650d97b3072SJian Shen 651d97b3072SJian Shen if (nfc->data & RXH_L4_B_2_3) 652d97b3072SJian Shen hash_sets |= HCLGEVF_D_PORT_BIT; 653d97b3072SJian Shen else 654d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_PORT_BIT; 655d97b3072SJian Shen 656d97b3072SJian Shen if (nfc->data & RXH_IP_SRC) 657d97b3072SJian Shen hash_sets |= HCLGEVF_S_IP_BIT; 658d97b3072SJian Shen else 659d97b3072SJian Shen hash_sets &= ~HCLGEVF_S_IP_BIT; 660d97b3072SJian Shen 661d97b3072SJian Shen if (nfc->data & RXH_IP_DST) 662d97b3072SJian Shen hash_sets |= HCLGEVF_D_IP_BIT; 663d97b3072SJian Shen else 664d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_IP_BIT; 665d97b3072SJian Shen 666d97b3072SJian Shen if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 667d97b3072SJian Shen hash_sets |= HCLGEVF_V_TAG_BIT; 668d97b3072SJian Shen 669d97b3072SJian Shen return hash_sets; 670d97b3072SJian Shen } 671d97b3072SJian Shen 672d97b3072SJian Shen static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 673d97b3072SJian Shen struct ethtool_rxnfc *nfc) 674d97b3072SJian Shen { 675d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 676d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 677d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 678d97b3072SJian Shen struct hclgevf_desc desc; 679d97b3072SJian Shen u8 tuple_sets; 680d97b3072SJian Shen int ret; 681d97b3072SJian Shen 682d97b3072SJian Shen if (handle->pdev->revision == 0x20) 683d97b3072SJian Shen return -EOPNOTSUPP; 684d97b3072SJian Shen 685d97b3072SJian Shen if (nfc->data & 686d97b3072SJian Shen ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 687d97b3072SJian Shen return -EINVAL; 688d97b3072SJian Shen 689d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 690d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 691d97b3072SJian Shen 692d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 693d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 694d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 695d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 696d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 697d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 698d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 699d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 700d97b3072SJian Shen 701d97b3072SJian Shen tuple_sets = hclgevf_get_rss_hash_bits(nfc); 702d97b3072SJian Shen switch (nfc->flow_type) { 703d97b3072SJian Shen case TCP_V4_FLOW: 704d97b3072SJian Shen req->ipv4_tcp_en = tuple_sets; 705d97b3072SJian Shen break; 706d97b3072SJian Shen case TCP_V6_FLOW: 707d97b3072SJian Shen req->ipv6_tcp_en = tuple_sets; 708d97b3072SJian Shen break; 709d97b3072SJian Shen case UDP_V4_FLOW: 710d97b3072SJian Shen req->ipv4_udp_en = tuple_sets; 711d97b3072SJian Shen break; 712d97b3072SJian Shen case UDP_V6_FLOW: 713d97b3072SJian Shen req->ipv6_udp_en = tuple_sets; 714d97b3072SJian Shen break; 715d97b3072SJian Shen case SCTP_V4_FLOW: 716d97b3072SJian Shen req->ipv4_sctp_en = tuple_sets; 717d97b3072SJian Shen break; 718d97b3072SJian Shen case SCTP_V6_FLOW: 719d97b3072SJian Shen if ((nfc->data & RXH_L4_B_0_1) || 720d97b3072SJian Shen (nfc->data & RXH_L4_B_2_3)) 721d97b3072SJian Shen return -EINVAL; 722d97b3072SJian Shen 723d97b3072SJian Shen req->ipv6_sctp_en = tuple_sets; 724d97b3072SJian Shen break; 725d97b3072SJian Shen case IPV4_FLOW: 726d97b3072SJian Shen req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 727d97b3072SJian Shen break; 728d97b3072SJian Shen case IPV6_FLOW: 729d97b3072SJian Shen req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 730d97b3072SJian Shen break; 731d97b3072SJian Shen default: 732d97b3072SJian Shen return -EINVAL; 733d97b3072SJian Shen } 734d97b3072SJian Shen 735d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 736d97b3072SJian Shen if (ret) { 737d97b3072SJian Shen dev_err(&hdev->pdev->dev, 738d97b3072SJian Shen "Set rss tuple fail, status = %d\n", ret); 739d97b3072SJian Shen return ret; 740d97b3072SJian Shen } 741d97b3072SJian Shen 742d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 743d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 744d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 745d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 746d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 747d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 748d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 749d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 750d97b3072SJian Shen return 0; 751d97b3072SJian Shen } 752d97b3072SJian Shen 753d97b3072SJian Shen static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 754d97b3072SJian Shen struct ethtool_rxnfc *nfc) 755d97b3072SJian Shen { 756d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 757d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 758d97b3072SJian Shen u8 tuple_sets; 759d97b3072SJian Shen 760d97b3072SJian Shen if (handle->pdev->revision == 0x20) 761d97b3072SJian Shen return -EOPNOTSUPP; 762d97b3072SJian Shen 763d97b3072SJian Shen nfc->data = 0; 764d97b3072SJian Shen 765d97b3072SJian Shen switch (nfc->flow_type) { 766d97b3072SJian Shen case TCP_V4_FLOW: 767d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 768d97b3072SJian Shen break; 769d97b3072SJian Shen case UDP_V4_FLOW: 770d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 771d97b3072SJian Shen break; 772d97b3072SJian Shen case TCP_V6_FLOW: 773d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 774d97b3072SJian Shen break; 775d97b3072SJian Shen case UDP_V6_FLOW: 776d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 777d97b3072SJian Shen break; 778d97b3072SJian Shen case SCTP_V4_FLOW: 779d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 780d97b3072SJian Shen break; 781d97b3072SJian Shen case SCTP_V6_FLOW: 782d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 783d97b3072SJian Shen break; 784d97b3072SJian Shen case IPV4_FLOW: 785d97b3072SJian Shen case IPV6_FLOW: 786d97b3072SJian Shen tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 787d97b3072SJian Shen break; 788d97b3072SJian Shen default: 789d97b3072SJian Shen return -EINVAL; 790d97b3072SJian Shen } 791d97b3072SJian Shen 792d97b3072SJian Shen if (!tuple_sets) 793d97b3072SJian Shen return 0; 794d97b3072SJian Shen 795d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_PORT_BIT) 796d97b3072SJian Shen nfc->data |= RXH_L4_B_2_3; 797d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_PORT_BIT) 798d97b3072SJian Shen nfc->data |= RXH_L4_B_0_1; 799d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_IP_BIT) 800d97b3072SJian Shen nfc->data |= RXH_IP_DST; 801d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_IP_BIT) 802d97b3072SJian Shen nfc->data |= RXH_IP_SRC; 803d97b3072SJian Shen 804d97b3072SJian Shen return 0; 805d97b3072SJian Shen } 806d97b3072SJian Shen 807d97b3072SJian Shen static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 808d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg) 809d97b3072SJian Shen { 810d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 811d97b3072SJian Shen struct hclgevf_desc desc; 812d97b3072SJian Shen int ret; 813d97b3072SJian Shen 814d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 815d97b3072SJian Shen 816d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 817d97b3072SJian Shen 818d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 819d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 820d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 821d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 822d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 823d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 824d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 825d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 826d97b3072SJian Shen 827d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 828d97b3072SJian Shen if (ret) 829d97b3072SJian Shen dev_err(&hdev->pdev->dev, 830d97b3072SJian Shen "Configure rss input fail, status = %d\n", ret); 831d97b3072SJian Shen return ret; 832d97b3072SJian Shen } 833d97b3072SJian Shen 834e2cb1decSSalil Mehta static int hclgevf_get_tc_size(struct hnae3_handle *handle) 835e2cb1decSSalil Mehta { 836e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 837e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 838e2cb1decSSalil Mehta 839e2cb1decSSalil Mehta return rss_cfg->rss_size; 840e2cb1decSSalil Mehta } 841e2cb1decSSalil Mehta 842e2cb1decSSalil Mehta static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 843b204bc74SPeng Li int vector_id, 844e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 845e2cb1decSSalil Mehta { 846e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 847e2cb1decSSalil Mehta struct hnae3_ring_chain_node *node; 848e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 849e2cb1decSSalil Mehta struct hclgevf_desc desc; 850b204bc74SPeng Li int i = 0; 851e2cb1decSSalil Mehta int status; 852e2cb1decSSalil Mehta u8 type; 853e2cb1decSSalil Mehta 854e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 855e2cb1decSSalil Mehta 856e2cb1decSSalil Mehta for (node = ring_chain; node; node = node->next) { 8575d02a58dSYunsheng Lin int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 8585d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 8595d02a58dSYunsheng Lin 8605d02a58dSYunsheng Lin if (i == 0) { 8615d02a58dSYunsheng Lin hclgevf_cmd_setup_basic_desc(&desc, 8625d02a58dSYunsheng Lin HCLGEVF_OPC_MBX_VF_TO_PF, 8635d02a58dSYunsheng Lin false); 8645d02a58dSYunsheng Lin type = en ? 8655d02a58dSYunsheng Lin HCLGE_MBX_MAP_RING_TO_VECTOR : 8665d02a58dSYunsheng Lin HCLGE_MBX_UNMAP_RING_TO_VECTOR; 8675d02a58dSYunsheng Lin req->msg[0] = type; 8685d02a58dSYunsheng Lin req->msg[1] = vector_id; 8695d02a58dSYunsheng Lin } 8705d02a58dSYunsheng Lin 8715d02a58dSYunsheng Lin req->msg[idx_offset] = 872e4e87715SPeng Li hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 8735d02a58dSYunsheng Lin req->msg[idx_offset + 1] = node->tqp_index; 874e4e87715SPeng Li req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 87579eee410SFuyun Liang HNAE3_RING_GL_IDX_M, 87679eee410SFuyun Liang HNAE3_RING_GL_IDX_S); 87779eee410SFuyun Liang 8785d02a58dSYunsheng Lin i++; 8795d02a58dSYunsheng Lin if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 8805d02a58dSYunsheng Lin HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 8815d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 8825d02a58dSYunsheng Lin !node->next) { 883e2cb1decSSalil Mehta req->msg[2] = i; 884e2cb1decSSalil Mehta 885e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 886e2cb1decSSalil Mehta if (status) { 887e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 888e2cb1decSSalil Mehta "Map TQP fail, status is %d.\n", 889e2cb1decSSalil Mehta status); 890e2cb1decSSalil Mehta return status; 891e2cb1decSSalil Mehta } 892e2cb1decSSalil Mehta i = 0; 893e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 894e2cb1decSSalil Mehta HCLGEVF_OPC_MBX_VF_TO_PF, 895e2cb1decSSalil Mehta false); 896e2cb1decSSalil Mehta req->msg[0] = type; 897e2cb1decSSalil Mehta req->msg[1] = vector_id; 898e2cb1decSSalil Mehta } 899e2cb1decSSalil Mehta } 900e2cb1decSSalil Mehta 901e2cb1decSSalil Mehta return 0; 902e2cb1decSSalil Mehta } 903e2cb1decSSalil Mehta 904e2cb1decSSalil Mehta static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 905e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 906e2cb1decSSalil Mehta { 907b204bc74SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 908b204bc74SPeng Li int vector_id; 909b204bc74SPeng Li 910b204bc74SPeng Li vector_id = hclgevf_get_vector_index(hdev, vector); 911b204bc74SPeng Li if (vector_id < 0) { 912b204bc74SPeng Li dev_err(&handle->pdev->dev, 913b204bc74SPeng Li "Get vector index fail. ret =%d\n", vector_id); 914b204bc74SPeng Li return vector_id; 915b204bc74SPeng Li } 916b204bc74SPeng Li 917b204bc74SPeng Li return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 918e2cb1decSSalil Mehta } 919e2cb1decSSalil Mehta 920e2cb1decSSalil Mehta static int hclgevf_unmap_ring_from_vector( 921e2cb1decSSalil Mehta struct hnae3_handle *handle, 922e2cb1decSSalil Mehta int vector, 923e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 924e2cb1decSSalil Mehta { 925e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 926e2cb1decSSalil Mehta int ret, vector_id; 927e2cb1decSSalil Mehta 928dea846e8SHuazhong Tan if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 929dea846e8SHuazhong Tan return 0; 930dea846e8SHuazhong Tan 931e2cb1decSSalil Mehta vector_id = hclgevf_get_vector_index(hdev, vector); 932e2cb1decSSalil Mehta if (vector_id < 0) { 933e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 934e2cb1decSSalil Mehta "Get vector index fail. ret =%d\n", vector_id); 935e2cb1decSSalil Mehta return vector_id; 936e2cb1decSSalil Mehta } 937e2cb1decSSalil Mehta 938b204bc74SPeng Li ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 9390d3e6631SYunsheng Lin if (ret) 940e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 941e2cb1decSSalil Mehta "Unmap ring from vector fail. vector=%d, ret =%d\n", 942e2cb1decSSalil Mehta vector_id, 943e2cb1decSSalil Mehta ret); 9440d3e6631SYunsheng Lin 945e2cb1decSSalil Mehta return ret; 946e2cb1decSSalil Mehta } 947e2cb1decSSalil Mehta 9480d3e6631SYunsheng Lin static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 9490d3e6631SYunsheng Lin { 9500d3e6631SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 95103718db9SYunsheng Lin int vector_id; 9520d3e6631SYunsheng Lin 95303718db9SYunsheng Lin vector_id = hclgevf_get_vector_index(hdev, vector); 95403718db9SYunsheng Lin if (vector_id < 0) { 95503718db9SYunsheng Lin dev_err(&handle->pdev->dev, 95603718db9SYunsheng Lin "hclgevf_put_vector get vector index fail. ret =%d\n", 95703718db9SYunsheng Lin vector_id); 95803718db9SYunsheng Lin return vector_id; 95903718db9SYunsheng Lin } 96003718db9SYunsheng Lin 96103718db9SYunsheng Lin hclgevf_free_vector(hdev, vector_id); 962e2cb1decSSalil Mehta 963e2cb1decSSalil Mehta return 0; 964e2cb1decSSalil Mehta } 965e2cb1decSSalil Mehta 9663b75c3dfSPeng Li static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 9673b75c3dfSPeng Li bool en_uc_pmc, bool en_mc_pmc) 968e2cb1decSSalil Mehta { 969e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 970e2cb1decSSalil Mehta struct hclgevf_desc desc; 971e2cb1decSSalil Mehta int status; 972e2cb1decSSalil Mehta 973e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 974e2cb1decSSalil Mehta 975e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 976e2cb1decSSalil Mehta req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 9773b75c3dfSPeng Li req->msg[1] = en_uc_pmc ? 1 : 0; 9783b75c3dfSPeng Li req->msg[2] = en_mc_pmc ? 1 : 0; 979e2cb1decSSalil Mehta 980e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 981e2cb1decSSalil Mehta if (status) 982e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 983e2cb1decSSalil Mehta "Set promisc mode fail, status is %d.\n", status); 984e2cb1decSSalil Mehta 985e2cb1decSSalil Mehta return status; 986e2cb1decSSalil Mehta } 987e2cb1decSSalil Mehta 9887fa6be4fSHuazhong Tan static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, 9893b75c3dfSPeng Li bool en_uc_pmc, bool en_mc_pmc) 990e2cb1decSSalil Mehta { 991e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 992e2cb1decSSalil Mehta 9937fa6be4fSHuazhong Tan return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc); 994e2cb1decSSalil Mehta } 995e2cb1decSSalil Mehta 996e2cb1decSSalil Mehta static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, int tqp_id, 997e2cb1decSSalil Mehta int stream_id, bool enable) 998e2cb1decSSalil Mehta { 999e2cb1decSSalil Mehta struct hclgevf_cfg_com_tqp_queue_cmd *req; 1000e2cb1decSSalil Mehta struct hclgevf_desc desc; 1001e2cb1decSSalil Mehta int status; 1002e2cb1decSSalil Mehta 1003e2cb1decSSalil Mehta req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1004e2cb1decSSalil Mehta 1005e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1006e2cb1decSSalil Mehta false); 1007e2cb1decSSalil Mehta req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1008e2cb1decSSalil Mehta req->stream_id = cpu_to_le16(stream_id); 1009e2cb1decSSalil Mehta req->enable |= enable << HCLGEVF_TQP_ENABLE_B; 1010e2cb1decSSalil Mehta 1011e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1012e2cb1decSSalil Mehta if (status) 1013e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1014e2cb1decSSalil Mehta "TQP enable fail, status =%d.\n", status); 1015e2cb1decSSalil Mehta 1016e2cb1decSSalil Mehta return status; 1017e2cb1decSSalil Mehta } 1018e2cb1decSSalil Mehta 1019e2cb1decSSalil Mehta static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1020e2cb1decSSalil Mehta { 1021b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1022e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 1023e2cb1decSSalil Mehta int i; 1024e2cb1decSSalil Mehta 1025b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 1026b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1027e2cb1decSSalil Mehta memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1028e2cb1decSSalil Mehta } 1029e2cb1decSSalil Mehta } 1030e2cb1decSSalil Mehta 1031e2cb1decSSalil Mehta static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1032e2cb1decSSalil Mehta { 1033e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1034e2cb1decSSalil Mehta 1035e2cb1decSSalil Mehta ether_addr_copy(p, hdev->hw.mac.mac_addr); 1036e2cb1decSSalil Mehta } 1037e2cb1decSSalil Mehta 103859098055SFuyun Liang static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 103959098055SFuyun Liang bool is_first) 1040e2cb1decSSalil Mehta { 1041e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1042e2cb1decSSalil Mehta u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1043e2cb1decSSalil Mehta u8 *new_mac_addr = (u8 *)p; 1044e2cb1decSSalil Mehta u8 msg_data[ETH_ALEN * 2]; 104559098055SFuyun Liang u16 subcode; 1046e2cb1decSSalil Mehta int status; 1047e2cb1decSSalil Mehta 1048e2cb1decSSalil Mehta ether_addr_copy(msg_data, new_mac_addr); 1049e2cb1decSSalil Mehta ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 1050e2cb1decSSalil Mehta 105159098055SFuyun Liang subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 105259098055SFuyun Liang HCLGE_MBX_MAC_VLAN_UC_MODIFY; 105359098055SFuyun Liang 1054e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 105559098055SFuyun Liang subcode, msg_data, ETH_ALEN * 2, 10562097fdefSJian Shen true, NULL, 0); 1057e2cb1decSSalil Mehta if (!status) 1058e2cb1decSSalil Mehta ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1059e2cb1decSSalil Mehta 1060e2cb1decSSalil Mehta return status; 1061e2cb1decSSalil Mehta } 1062e2cb1decSSalil Mehta 1063e2cb1decSSalil Mehta static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1064e2cb1decSSalil Mehta const unsigned char *addr) 1065e2cb1decSSalil Mehta { 1066e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1067e2cb1decSSalil Mehta 1068e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1069e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_ADD, 1070e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1071e2cb1decSSalil Mehta } 1072e2cb1decSSalil Mehta 1073e2cb1decSSalil Mehta static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1074e2cb1decSSalil Mehta const unsigned char *addr) 1075e2cb1decSSalil Mehta { 1076e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1077e2cb1decSSalil Mehta 1078e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1079e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1080e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1081e2cb1decSSalil Mehta } 1082e2cb1decSSalil Mehta 1083e2cb1decSSalil Mehta static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1084e2cb1decSSalil Mehta const unsigned char *addr) 1085e2cb1decSSalil Mehta { 1086e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1087e2cb1decSSalil Mehta 1088e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1089e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_ADD, 1090e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1091e2cb1decSSalil Mehta } 1092e2cb1decSSalil Mehta 1093e2cb1decSSalil Mehta static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1094e2cb1decSSalil Mehta const unsigned char *addr) 1095e2cb1decSSalil Mehta { 1096e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1097e2cb1decSSalil Mehta 1098e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1099e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1100e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1101e2cb1decSSalil Mehta } 1102e2cb1decSSalil Mehta 1103e2cb1decSSalil Mehta static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1104e2cb1decSSalil Mehta __be16 proto, u16 vlan_id, 1105e2cb1decSSalil Mehta bool is_kill) 1106e2cb1decSSalil Mehta { 1107e2cb1decSSalil Mehta #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1108e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1109e2cb1decSSalil Mehta u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1110e2cb1decSSalil Mehta 1111e2cb1decSSalil Mehta if (vlan_id > 4095) 1112e2cb1decSSalil Mehta return -EINVAL; 1113e2cb1decSSalil Mehta 1114e2cb1decSSalil Mehta if (proto != htons(ETH_P_8021Q)) 1115e2cb1decSSalil Mehta return -EPROTONOSUPPORT; 1116e2cb1decSSalil Mehta 1117e2cb1decSSalil Mehta msg_data[0] = is_kill; 1118e2cb1decSSalil Mehta memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1119e2cb1decSSalil Mehta memcpy(&msg_data[3], &proto, sizeof(proto)); 1120e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1121e2cb1decSSalil Mehta HCLGE_MBX_VLAN_FILTER, msg_data, 1122e2cb1decSSalil Mehta HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 1123e2cb1decSSalil Mehta } 1124e2cb1decSSalil Mehta 1125b2641e2aSYunsheng Lin static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1126b2641e2aSYunsheng Lin { 1127b2641e2aSYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1128b2641e2aSYunsheng Lin u8 msg_data; 1129b2641e2aSYunsheng Lin 1130b2641e2aSYunsheng Lin msg_data = enable ? 1 : 0; 1131b2641e2aSYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1132b2641e2aSYunsheng Lin HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1133b2641e2aSYunsheng Lin 1, false, NULL, 0); 1134b2641e2aSYunsheng Lin } 1135b2641e2aSYunsheng Lin 11367fa6be4fSHuazhong Tan static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1137e2cb1decSSalil Mehta { 1138e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1139e2cb1decSSalil Mehta u8 msg_data[2]; 11401a426f8bSPeng Li int ret; 1141e2cb1decSSalil Mehta 1142e2cb1decSSalil Mehta memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 1143e2cb1decSSalil Mehta 11441a426f8bSPeng Li /* disable vf queue before send queue reset msg to PF */ 11451a426f8bSPeng Li ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 11461a426f8bSPeng Li if (ret) 11477fa6be4fSHuazhong Tan return ret; 11481a426f8bSPeng Li 11497fa6be4fSHuazhong Tan return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 11501a426f8bSPeng Li 2, true, NULL, 0); 1151e2cb1decSSalil Mehta } 1152e2cb1decSSalil Mehta 1153818f1675SYunsheng Lin static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1154818f1675SYunsheng Lin { 1155818f1675SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1156818f1675SYunsheng Lin 1157818f1675SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu, 1158818f1675SYunsheng Lin sizeof(new_mtu), true, NULL, 0); 1159818f1675SYunsheng Lin } 1160818f1675SYunsheng Lin 11616988eb2aSSalil Mehta static int hclgevf_notify_client(struct hclgevf_dev *hdev, 11626988eb2aSSalil Mehta enum hnae3_reset_notify_type type) 11636988eb2aSSalil Mehta { 11646988eb2aSSalil Mehta struct hnae3_client *client = hdev->nic_client; 11656988eb2aSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 11666a5f6fa3SHuazhong Tan int ret; 11676988eb2aSSalil Mehta 11686988eb2aSSalil Mehta if (!client->ops->reset_notify) 11696988eb2aSSalil Mehta return -EOPNOTSUPP; 11706988eb2aSSalil Mehta 11716a5f6fa3SHuazhong Tan ret = client->ops->reset_notify(handle, type); 11726a5f6fa3SHuazhong Tan if (ret) 11736a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 11746a5f6fa3SHuazhong Tan type, ret); 11756a5f6fa3SHuazhong Tan 11766a5f6fa3SHuazhong Tan return ret; 11776988eb2aSSalil Mehta } 11786988eb2aSSalil Mehta 11796ff3cf07SHuazhong Tan static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 11806ff3cf07SHuazhong Tan { 11816ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 11826ff3cf07SHuazhong Tan 11836ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DONE, &hdev->flr_state); 11846ff3cf07SHuazhong Tan } 11856ff3cf07SHuazhong Tan 11866ff3cf07SHuazhong Tan static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev, 11876ff3cf07SHuazhong Tan unsigned long delay_us, 11886ff3cf07SHuazhong Tan unsigned long wait_cnt) 11896ff3cf07SHuazhong Tan { 11906ff3cf07SHuazhong Tan unsigned long cnt = 0; 11916ff3cf07SHuazhong Tan 11926ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) && 11936ff3cf07SHuazhong Tan cnt++ < wait_cnt) 11946ff3cf07SHuazhong Tan usleep_range(delay_us, delay_us * 2); 11956ff3cf07SHuazhong Tan 11966ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) { 11976ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 11986ff3cf07SHuazhong Tan "flr wait timeout\n"); 11996ff3cf07SHuazhong Tan return -ETIMEDOUT; 12006ff3cf07SHuazhong Tan } 12016ff3cf07SHuazhong Tan 12026ff3cf07SHuazhong Tan return 0; 12036ff3cf07SHuazhong Tan } 12046ff3cf07SHuazhong Tan 12056988eb2aSSalil Mehta static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 12066988eb2aSSalil Mehta { 1207aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_US 20000 1208aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_CNT 2000 1209aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1210aa5c4f17SHuazhong Tan (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1211aa5c4f17SHuazhong Tan 1212aa5c4f17SHuazhong Tan u32 val; 1213aa5c4f17SHuazhong Tan int ret; 12146988eb2aSSalil Mehta 12156988eb2aSSalil Mehta /* wait to check the hardware reset completion status */ 1216aa5c4f17SHuazhong Tan val = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1217aa5c4f17SHuazhong Tan dev_info(&hdev->pdev->dev, "checking vf resetting status: %x\n", val); 1218aa5c4f17SHuazhong Tan 12196ff3cf07SHuazhong Tan if (hdev->reset_type == HNAE3_FLR_RESET) 12206ff3cf07SHuazhong Tan return hclgevf_flr_poll_timeout(hdev, 12216ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_US, 12226ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_CNT); 12236ff3cf07SHuazhong Tan 1224aa5c4f17SHuazhong Tan ret = readl_poll_timeout(hdev->hw.io_base + HCLGEVF_RST_ING, val, 1225aa5c4f17SHuazhong Tan !(val & HCLGEVF_RST_ING_BITS), 1226aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_US, 1227aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 12286988eb2aSSalil Mehta 12296988eb2aSSalil Mehta /* hardware completion status should be available by this time */ 1230aa5c4f17SHuazhong Tan if (ret) { 1231aa5c4f17SHuazhong Tan dev_err(&hdev->pdev->dev, 12326988eb2aSSalil Mehta "could'nt get reset done status from h/w, timeout!\n"); 1233aa5c4f17SHuazhong Tan return ret; 12346988eb2aSSalil Mehta } 12356988eb2aSSalil Mehta 12366988eb2aSSalil Mehta /* we will wait a bit more to let reset of the stack to complete. This 12376988eb2aSSalil Mehta * might happen in case reset assertion was made by PF. Yes, this also 12386988eb2aSSalil Mehta * means we might end up waiting bit more even for VF reset. 12396988eb2aSSalil Mehta */ 12406988eb2aSSalil Mehta msleep(5000); 12416988eb2aSSalil Mehta 12426988eb2aSSalil Mehta return 0; 12436988eb2aSSalil Mehta } 12446988eb2aSSalil Mehta 12456988eb2aSSalil Mehta static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 12466988eb2aSSalil Mehta { 12477a01c897SSalil Mehta int ret; 12487a01c897SSalil Mehta 12496988eb2aSSalil Mehta /* uninitialize the nic client */ 12506a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 12516a5f6fa3SHuazhong Tan if (ret) 12526a5f6fa3SHuazhong Tan return ret; 12536988eb2aSSalil Mehta 12547a01c897SSalil Mehta /* re-initialize the hclge device */ 12559c6f7085SHuazhong Tan ret = hclgevf_reset_hdev(hdev); 12567a01c897SSalil Mehta if (ret) { 12577a01c897SSalil Mehta dev_err(&hdev->pdev->dev, 12587a01c897SSalil Mehta "hclge device re-init failed, VF is disabled!\n"); 12597a01c897SSalil Mehta return ret; 12607a01c897SSalil Mehta } 12616988eb2aSSalil Mehta 12626988eb2aSSalil Mehta /* bring up the nic client again */ 12636a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 12646a5f6fa3SHuazhong Tan if (ret) 12656a5f6fa3SHuazhong Tan return ret; 12666988eb2aSSalil Mehta 12676988eb2aSSalil Mehta return 0; 12686988eb2aSSalil Mehta } 12696988eb2aSSalil Mehta 1270dea846e8SHuazhong Tan static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1271dea846e8SHuazhong Tan { 1272dea846e8SHuazhong Tan int ret = 0; 1273dea846e8SHuazhong Tan 1274dea846e8SHuazhong Tan switch (hdev->reset_type) { 1275dea846e8SHuazhong Tan case HNAE3_VF_FUNC_RESET: 1276dea846e8SHuazhong Tan ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1277dea846e8SHuazhong Tan 0, true, NULL, sizeof(u8)); 1278dea846e8SHuazhong Tan break; 12796ff3cf07SHuazhong Tan case HNAE3_FLR_RESET: 12806ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 12816ff3cf07SHuazhong Tan break; 1282dea846e8SHuazhong Tan default: 1283dea846e8SHuazhong Tan break; 1284dea846e8SHuazhong Tan } 1285dea846e8SHuazhong Tan 1286ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1287ef5f8e50SHuazhong Tan 1288dea846e8SHuazhong Tan dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1289dea846e8SHuazhong Tan hdev->reset_type, ret); 1290dea846e8SHuazhong Tan 1291dea846e8SHuazhong Tan return ret; 1292dea846e8SHuazhong Tan } 1293dea846e8SHuazhong Tan 12946988eb2aSSalil Mehta static int hclgevf_reset(struct hclgevf_dev *hdev) 12956988eb2aSSalil Mehta { 1296dea846e8SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 12976988eb2aSSalil Mehta int ret; 12986988eb2aSSalil Mehta 1299dea846e8SHuazhong Tan /* Initialize ae_dev reset status as well, in case enet layer wants to 1300dea846e8SHuazhong Tan * know if device is undergoing reset 1301dea846e8SHuazhong Tan */ 1302dea846e8SHuazhong Tan ae_dev->reset_type = hdev->reset_type; 13034d60291bSHuazhong Tan hdev->reset_count++; 13046988eb2aSSalil Mehta rtnl_lock(); 13056988eb2aSSalil Mehta 13066988eb2aSSalil Mehta /* bring down the nic to stop any ongoing TX/RX */ 13076a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 13086a5f6fa3SHuazhong Tan if (ret) 13096a5f6fa3SHuazhong Tan goto err_reset_lock; 13106988eb2aSSalil Mehta 131129118ab9SHuazhong Tan rtnl_unlock(); 131229118ab9SHuazhong Tan 13136a5f6fa3SHuazhong Tan ret = hclgevf_reset_prepare_wait(hdev); 13146a5f6fa3SHuazhong Tan if (ret) 13156a5f6fa3SHuazhong Tan goto err_reset; 1316dea846e8SHuazhong Tan 13176988eb2aSSalil Mehta /* check if VF could successfully fetch the hardware reset completion 13186988eb2aSSalil Mehta * status from the hardware 13196988eb2aSSalil Mehta */ 13206988eb2aSSalil Mehta ret = hclgevf_reset_wait(hdev); 13216988eb2aSSalil Mehta if (ret) { 13226988eb2aSSalil Mehta /* can't do much in this situation, will disable VF */ 13236988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, 13246988eb2aSSalil Mehta "VF failed(=%d) to fetch H/W reset completion status\n", 13256988eb2aSSalil Mehta ret); 13266a5f6fa3SHuazhong Tan goto err_reset; 13276988eb2aSSalil Mehta } 13286988eb2aSSalil Mehta 132929118ab9SHuazhong Tan rtnl_lock(); 133029118ab9SHuazhong Tan 13316988eb2aSSalil Mehta /* now, re-initialize the nic client and ae device*/ 13326988eb2aSSalil Mehta ret = hclgevf_reset_stack(hdev); 13336a5f6fa3SHuazhong Tan if (ret) { 13346988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 13356a5f6fa3SHuazhong Tan goto err_reset_lock; 13366a5f6fa3SHuazhong Tan } 13376988eb2aSSalil Mehta 13386988eb2aSSalil Mehta /* bring up the nic to enable TX/RX again */ 13396a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 13406a5f6fa3SHuazhong Tan if (ret) 13416a5f6fa3SHuazhong Tan goto err_reset_lock; 13426988eb2aSSalil Mehta 13436988eb2aSSalil Mehta rtnl_unlock(); 13446988eb2aSSalil Mehta 1345b644a8d4SHuazhong Tan hdev->last_reset_time = jiffies; 1346b644a8d4SHuazhong Tan ae_dev->reset_type = HNAE3_NONE_RESET; 1347b644a8d4SHuazhong Tan 13486988eb2aSSalil Mehta return ret; 13496a5f6fa3SHuazhong Tan err_reset_lock: 13506a5f6fa3SHuazhong Tan rtnl_unlock(); 13516a5f6fa3SHuazhong Tan err_reset: 13526a5f6fa3SHuazhong Tan /* When VF reset failed, only the higher level reset asserted by PF 13536a5f6fa3SHuazhong Tan * can restore it, so re-initialize the command queue to receive 13546a5f6fa3SHuazhong Tan * this higher reset event. 13556a5f6fa3SHuazhong Tan */ 13566a5f6fa3SHuazhong Tan hclgevf_cmd_init(hdev); 13576a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "failed to reset VF\n"); 13586a5f6fa3SHuazhong Tan 13596a5f6fa3SHuazhong Tan return ret; 13606988eb2aSSalil Mehta } 13616988eb2aSSalil Mehta 1362720bd583SHuazhong Tan static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1363720bd583SHuazhong Tan unsigned long *addr) 1364720bd583SHuazhong Tan { 1365720bd583SHuazhong Tan enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1366720bd583SHuazhong Tan 1367dea846e8SHuazhong Tan /* return the highest priority reset level amongst all */ 1368b90fcc5bSHuazhong Tan if (test_bit(HNAE3_VF_RESET, addr)) { 1369b90fcc5bSHuazhong Tan rst_level = HNAE3_VF_RESET; 1370b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_RESET, addr); 1371b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1372b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1373b90fcc5bSHuazhong Tan } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1374dea846e8SHuazhong Tan rst_level = HNAE3_VF_FULL_RESET; 1375dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FULL_RESET, addr); 1376dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1377aa5c4f17SHuazhong Tan } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1378aa5c4f17SHuazhong Tan rst_level = HNAE3_VF_PF_FUNC_RESET; 1379aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1380aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1381dea846e8SHuazhong Tan } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1382dea846e8SHuazhong Tan rst_level = HNAE3_VF_FUNC_RESET; 1383dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 13846ff3cf07SHuazhong Tan } else if (test_bit(HNAE3_FLR_RESET, addr)) { 13856ff3cf07SHuazhong Tan rst_level = HNAE3_FLR_RESET; 13866ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_RESET, addr); 1387720bd583SHuazhong Tan } 1388720bd583SHuazhong Tan 1389720bd583SHuazhong Tan return rst_level; 1390720bd583SHuazhong Tan } 1391720bd583SHuazhong Tan 13926ae4e733SShiju Jose static void hclgevf_reset_event(struct pci_dev *pdev, 13936ae4e733SShiju Jose struct hnae3_handle *handle) 13946d4c3981SSalil Mehta { 13956ff3cf07SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 13966ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 13976d4c3981SSalil Mehta 13986d4c3981SSalil Mehta dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 13996d4c3981SSalil Mehta 14006ff3cf07SHuazhong Tan if (hdev->default_reset_request) 14010742ed7cSHuazhong Tan hdev->reset_level = 1402720bd583SHuazhong Tan hclgevf_get_reset_level(hdev, 1403720bd583SHuazhong Tan &hdev->default_reset_request); 1404720bd583SHuazhong Tan else 1405dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 14066d4c3981SSalil Mehta 1407436667d2SSalil Mehta /* reset of this VF requested */ 1408436667d2SSalil Mehta set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1409436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 14106d4c3981SSalil Mehta 14110742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 14126d4c3981SSalil Mehta } 14136d4c3981SSalil Mehta 1414720bd583SHuazhong Tan static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1415720bd583SHuazhong Tan enum hnae3_reset_type rst_type) 1416720bd583SHuazhong Tan { 1417720bd583SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1418720bd583SHuazhong Tan 1419720bd583SHuazhong Tan set_bit(rst_type, &hdev->default_reset_request); 1420720bd583SHuazhong Tan } 1421720bd583SHuazhong Tan 14226ff3cf07SHuazhong Tan static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 14236ff3cf07SHuazhong Tan { 14246ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_MS 100 14256ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_CNT 50 14266ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 14276ff3cf07SHuazhong Tan int cnt = 0; 14286ff3cf07SHuazhong Tan 14296ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 14306ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DONE, &hdev->flr_state); 14316ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request); 14326ff3cf07SHuazhong Tan hclgevf_reset_event(hdev->pdev, NULL); 14336ff3cf07SHuazhong Tan 14346ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) && 14356ff3cf07SHuazhong Tan cnt++ < HCLGEVF_FLR_WAIT_CNT) 14366ff3cf07SHuazhong Tan msleep(HCLGEVF_FLR_WAIT_MS); 14376ff3cf07SHuazhong Tan 14386ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state)) 14396ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 14406ff3cf07SHuazhong Tan "flr wait down timeout: %d\n", cnt); 14416ff3cf07SHuazhong Tan } 14426ff3cf07SHuazhong Tan 1443e2cb1decSSalil Mehta static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1444e2cb1decSSalil Mehta { 1445e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1446e2cb1decSSalil Mehta 1447e2cb1decSSalil Mehta return hdev->fw_version; 1448e2cb1decSSalil Mehta } 1449e2cb1decSSalil Mehta 1450e2cb1decSSalil Mehta static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1451e2cb1decSSalil Mehta { 1452e2cb1decSSalil Mehta struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1453e2cb1decSSalil Mehta 1454e2cb1decSSalil Mehta vector->vector_irq = pci_irq_vector(hdev->pdev, 1455e2cb1decSSalil Mehta HCLGEVF_MISC_VECTOR_NUM); 1456e2cb1decSSalil Mehta vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1457e2cb1decSSalil Mehta /* vector status always valid for Vector 0 */ 1458e2cb1decSSalil Mehta hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1459e2cb1decSSalil Mehta hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1460e2cb1decSSalil Mehta 1461e2cb1decSSalil Mehta hdev->num_msi_left -= 1; 1462e2cb1decSSalil Mehta hdev->num_msi_used += 1; 1463e2cb1decSSalil Mehta } 1464e2cb1decSSalil Mehta 146535a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 146635a1e503SSalil Mehta { 146735a1e503SSalil Mehta if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) && 146835a1e503SSalil Mehta !test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) { 146935a1e503SSalil Mehta set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 147035a1e503SSalil Mehta schedule_work(&hdev->rst_service_task); 147135a1e503SSalil Mehta } 147235a1e503SSalil Mehta } 147335a1e503SSalil Mehta 147407a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1475e2cb1decSSalil Mehta { 147607a0556aSSalil Mehta if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) && 147707a0556aSSalil Mehta !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) { 147807a0556aSSalil Mehta set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1479e2cb1decSSalil Mehta schedule_work(&hdev->mbx_service_task); 1480e2cb1decSSalil Mehta } 148107a0556aSSalil Mehta } 1482e2cb1decSSalil Mehta 1483e2cb1decSSalil Mehta static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 1484e2cb1decSSalil Mehta { 1485e2cb1decSSalil Mehta if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 1486e2cb1decSSalil Mehta !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 1487e2cb1decSSalil Mehta schedule_work(&hdev->service_task); 1488e2cb1decSSalil Mehta } 1489e2cb1decSSalil Mehta 1490436667d2SSalil Mehta static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev) 1491436667d2SSalil Mehta { 149207a0556aSSalil Mehta /* if we have any pending mailbox event then schedule the mbx task */ 149307a0556aSSalil Mehta if (hdev->mbx_event_pending) 149407a0556aSSalil Mehta hclgevf_mbx_task_schedule(hdev); 149507a0556aSSalil Mehta 1496436667d2SSalil Mehta if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state)) 1497436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 1498436667d2SSalil Mehta } 1499436667d2SSalil Mehta 1500e2cb1decSSalil Mehta static void hclgevf_service_timer(struct timer_list *t) 1501e2cb1decSSalil Mehta { 1502e2cb1decSSalil Mehta struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 1503e2cb1decSSalil Mehta 1504e2cb1decSSalil Mehta mod_timer(&hdev->service_timer, jiffies + 5 * HZ); 1505e2cb1decSSalil Mehta 1506e2cb1decSSalil Mehta hclgevf_task_schedule(hdev); 1507e2cb1decSSalil Mehta } 1508e2cb1decSSalil Mehta 150935a1e503SSalil Mehta static void hclgevf_reset_service_task(struct work_struct *work) 151035a1e503SSalil Mehta { 151135a1e503SSalil Mehta struct hclgevf_dev *hdev = 151235a1e503SSalil Mehta container_of(work, struct hclgevf_dev, rst_service_task); 1513a8dedb65SSalil Mehta int ret; 151435a1e503SSalil Mehta 151535a1e503SSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 151635a1e503SSalil Mehta return; 151735a1e503SSalil Mehta 151835a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 151935a1e503SSalil Mehta 1520436667d2SSalil Mehta if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1521436667d2SSalil Mehta &hdev->reset_state)) { 1522436667d2SSalil Mehta /* PF has initmated that it is about to reset the hardware. 1523436667d2SSalil Mehta * We now have to poll & check if harware has actually completed 1524436667d2SSalil Mehta * the reset sequence. On hardware reset completion, VF needs to 1525436667d2SSalil Mehta * reset the client and ae device. 152635a1e503SSalil Mehta */ 1527436667d2SSalil Mehta hdev->reset_attempts = 0; 1528436667d2SSalil Mehta 1529dea846e8SHuazhong Tan hdev->last_reset_time = jiffies; 1530dea846e8SHuazhong Tan while ((hdev->reset_type = 1531dea846e8SHuazhong Tan hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 1532dea846e8SHuazhong Tan != HNAE3_NONE_RESET) { 15336988eb2aSSalil Mehta ret = hclgevf_reset(hdev); 15346988eb2aSSalil Mehta if (ret) 1535dea846e8SHuazhong Tan dev_err(&hdev->pdev->dev, 1536dea846e8SHuazhong Tan "VF stack reset failed %d.\n", ret); 1537dea846e8SHuazhong Tan } 1538436667d2SSalil Mehta } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1539436667d2SSalil Mehta &hdev->reset_state)) { 1540436667d2SSalil Mehta /* we could be here when either of below happens: 1541436667d2SSalil Mehta * 1. reset was initiated due to watchdog timeout due to 1542436667d2SSalil Mehta * a. IMP was earlier reset and our TX got choked down and 1543436667d2SSalil Mehta * which resulted in watchdog reacting and inducing VF 1544436667d2SSalil Mehta * reset. This also means our cmdq would be unreliable. 1545436667d2SSalil Mehta * b. problem in TX due to other lower layer(example link 1546436667d2SSalil Mehta * layer not functioning properly etc.) 1547436667d2SSalil Mehta * 2. VF reset might have been initiated due to some config 1548436667d2SSalil Mehta * change. 1549436667d2SSalil Mehta * 1550436667d2SSalil Mehta * NOTE: Theres no clear way to detect above cases than to react 1551436667d2SSalil Mehta * to the response of PF for this reset request. PF will ack the 1552436667d2SSalil Mehta * 1b and 2. cases but we will not get any intimation about 1a 1553436667d2SSalil Mehta * from PF as cmdq would be in unreliable state i.e. mailbox 1554436667d2SSalil Mehta * communication between PF and VF would be broken. 1555436667d2SSalil Mehta */ 1556436667d2SSalil Mehta 1557436667d2SSalil Mehta /* if we are never geting into pending state it means either: 1558436667d2SSalil Mehta * 1. PF is not receiving our request which could be due to IMP 1559436667d2SSalil Mehta * reset 1560436667d2SSalil Mehta * 2. PF is screwed 1561436667d2SSalil Mehta * We cannot do much for 2. but to check first we can try reset 1562436667d2SSalil Mehta * our PCIe + stack and see if it alleviates the problem. 1563436667d2SSalil Mehta */ 1564436667d2SSalil Mehta if (hdev->reset_attempts > 3) { 1565436667d2SSalil Mehta /* prepare for full reset of stack + pcie interface */ 1566dea846e8SHuazhong Tan set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1567436667d2SSalil Mehta 1568436667d2SSalil Mehta /* "defer" schedule the reset task again */ 1569436667d2SSalil Mehta set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1570436667d2SSalil Mehta } else { 1571436667d2SSalil Mehta hdev->reset_attempts++; 1572436667d2SSalil Mehta 1573dea846e8SHuazhong Tan set_bit(hdev->reset_level, &hdev->reset_pending); 1574dea846e8SHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1575436667d2SSalil Mehta } 1576dea846e8SHuazhong Tan hclgevf_reset_task_schedule(hdev); 1577436667d2SSalil Mehta } 157835a1e503SSalil Mehta 157935a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 158035a1e503SSalil Mehta } 158135a1e503SSalil Mehta 1582e2cb1decSSalil Mehta static void hclgevf_mailbox_service_task(struct work_struct *work) 1583e2cb1decSSalil Mehta { 1584e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1585e2cb1decSSalil Mehta 1586e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 1587e2cb1decSSalil Mehta 1588e2cb1decSSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1589e2cb1decSSalil Mehta return; 1590e2cb1decSSalil Mehta 1591e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1592e2cb1decSSalil Mehta 159307a0556aSSalil Mehta hclgevf_mbx_async_handler(hdev); 1594e2cb1decSSalil Mehta 1595e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1596e2cb1decSSalil Mehta } 1597e2cb1decSSalil Mehta 1598a6d818e3SYunsheng Lin static void hclgevf_keep_alive_timer(struct timer_list *t) 1599a6d818e3SYunsheng Lin { 1600a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = from_timer(hdev, t, keep_alive_timer); 1601a6d818e3SYunsheng Lin 1602a6d818e3SYunsheng Lin schedule_work(&hdev->keep_alive_task); 1603a6d818e3SYunsheng Lin mod_timer(&hdev->keep_alive_timer, jiffies + 2 * HZ); 1604a6d818e3SYunsheng Lin } 1605a6d818e3SYunsheng Lin 1606a6d818e3SYunsheng Lin static void hclgevf_keep_alive_task(struct work_struct *work) 1607a6d818e3SYunsheng Lin { 1608a6d818e3SYunsheng Lin struct hclgevf_dev *hdev; 1609a6d818e3SYunsheng Lin u8 respmsg; 1610a6d818e3SYunsheng Lin int ret; 1611a6d818e3SYunsheng Lin 1612a6d818e3SYunsheng Lin hdev = container_of(work, struct hclgevf_dev, keep_alive_task); 1613a6d818e3SYunsheng Lin ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL, 1614a6d818e3SYunsheng Lin 0, false, &respmsg, sizeof(u8)); 1615a6d818e3SYunsheng Lin if (ret) 1616a6d818e3SYunsheng Lin dev_err(&hdev->pdev->dev, 1617a6d818e3SYunsheng Lin "VF sends keep alive cmd failed(=%d)\n", ret); 1618a6d818e3SYunsheng Lin } 1619a6d818e3SYunsheng Lin 1620e2cb1decSSalil Mehta static void hclgevf_service_task(struct work_struct *work) 1621e2cb1decSSalil Mehta { 1622e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1623e2cb1decSSalil Mehta 1624e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, service_task); 1625e2cb1decSSalil Mehta 1626e2cb1decSSalil Mehta /* request the link status from the PF. PF would be able to tell VF 1627e2cb1decSSalil Mehta * about such updates in future so we might remove this later 1628e2cb1decSSalil Mehta */ 1629e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1630e2cb1decSSalil Mehta 1631436667d2SSalil Mehta hclgevf_deferred_task_schedule(hdev); 1632436667d2SSalil Mehta 1633e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1634e2cb1decSSalil Mehta } 1635e2cb1decSSalil Mehta 1636e2cb1decSSalil Mehta static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1637e2cb1decSSalil Mehta { 1638e2cb1decSSalil Mehta hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1639e2cb1decSSalil Mehta } 1640e2cb1decSSalil Mehta 1641b90fcc5bSHuazhong Tan static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1642b90fcc5bSHuazhong Tan u32 *clearval) 1643e2cb1decSSalil Mehta { 1644b90fcc5bSHuazhong Tan u32 cmdq_src_reg, rst_ing_reg; 1645e2cb1decSSalil Mehta 1646e2cb1decSSalil Mehta /* fetch the events from their corresponding regs */ 1647e2cb1decSSalil Mehta cmdq_src_reg = hclgevf_read_dev(&hdev->hw, 1648e2cb1decSSalil Mehta HCLGEVF_VECTOR0_CMDQ_SRC_REG); 1649e2cb1decSSalil Mehta 1650b90fcc5bSHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_src_reg) { 1651b90fcc5bSHuazhong Tan rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1652b90fcc5bSHuazhong Tan dev_info(&hdev->pdev->dev, 1653b90fcc5bSHuazhong Tan "receive reset interrupt 0x%x!\n", rst_ing_reg); 1654b90fcc5bSHuazhong Tan set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1655b90fcc5bSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1656ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1657b90fcc5bSHuazhong Tan cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RST_INT_B); 1658b90fcc5bSHuazhong Tan *clearval = cmdq_src_reg; 1659b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_RST; 1660b90fcc5bSHuazhong Tan } 1661b90fcc5bSHuazhong Tan 1662e2cb1decSSalil Mehta /* check for vector0 mailbox(=CMDQ RX) event source */ 1663e2cb1decSSalil Mehta if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 1664e2cb1decSSalil Mehta cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1665e2cb1decSSalil Mehta *clearval = cmdq_src_reg; 1666b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_MBX; 1667e2cb1decSSalil Mehta } 1668e2cb1decSSalil Mehta 1669e2cb1decSSalil Mehta dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 1670e2cb1decSSalil Mehta 1671b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_OTHER; 1672e2cb1decSSalil Mehta } 1673e2cb1decSSalil Mehta 1674e2cb1decSSalil Mehta static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1675e2cb1decSSalil Mehta { 1676e2cb1decSSalil Mehta writel(en ? 1 : 0, vector->addr); 1677e2cb1decSSalil Mehta } 1678e2cb1decSSalil Mehta 1679e2cb1decSSalil Mehta static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1680e2cb1decSSalil Mehta { 1681b90fcc5bSHuazhong Tan enum hclgevf_evt_cause event_cause; 1682e2cb1decSSalil Mehta struct hclgevf_dev *hdev = data; 1683e2cb1decSSalil Mehta u32 clearval; 1684e2cb1decSSalil Mehta 1685e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 1686b90fcc5bSHuazhong Tan event_cause = hclgevf_check_evt_cause(hdev, &clearval); 1687e2cb1decSSalil Mehta 1688b90fcc5bSHuazhong Tan switch (event_cause) { 1689b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_RST: 1690b90fcc5bSHuazhong Tan hclgevf_reset_task_schedule(hdev); 1691b90fcc5bSHuazhong Tan break; 1692b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_MBX: 169307a0556aSSalil Mehta hclgevf_mbx_handler(hdev); 1694b90fcc5bSHuazhong Tan break; 1695b90fcc5bSHuazhong Tan default: 1696b90fcc5bSHuazhong Tan break; 1697b90fcc5bSHuazhong Tan } 1698e2cb1decSSalil Mehta 1699b90fcc5bSHuazhong Tan if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 1700e2cb1decSSalil Mehta hclgevf_clear_event_cause(hdev, clearval); 1701e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 1702b90fcc5bSHuazhong Tan } 1703e2cb1decSSalil Mehta 1704e2cb1decSSalil Mehta return IRQ_HANDLED; 1705e2cb1decSSalil Mehta } 1706e2cb1decSSalil Mehta 1707e2cb1decSSalil Mehta static int hclgevf_configure(struct hclgevf_dev *hdev) 1708e2cb1decSSalil Mehta { 1709e2cb1decSSalil Mehta int ret; 1710e2cb1decSSalil Mehta 1711c136b884SPeng Li hdev->hw.mac.media_type = HNAE3_MEDIA_TYPE_NONE; 1712c136b884SPeng Li 1713e2cb1decSSalil Mehta /* get queue configuration from PF */ 17146cee6fc3SJian Shen ret = hclgevf_get_queue_info(hdev); 1715e2cb1decSSalil Mehta if (ret) 1716e2cb1decSSalil Mehta return ret; 1717e2cb1decSSalil Mehta /* get tc configuration from PF */ 1718e2cb1decSSalil Mehta return hclgevf_get_tc_info(hdev); 1719e2cb1decSSalil Mehta } 1720e2cb1decSSalil Mehta 17217a01c897SSalil Mehta static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 17227a01c897SSalil Mehta { 17237a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 17247a01c897SSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 17257a01c897SSalil Mehta 17267a01c897SSalil Mehta hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 17277a01c897SSalil Mehta if (!hdev) 17287a01c897SSalil Mehta return -ENOMEM; 17297a01c897SSalil Mehta 17307a01c897SSalil Mehta hdev->pdev = pdev; 17317a01c897SSalil Mehta hdev->ae_dev = ae_dev; 17327a01c897SSalil Mehta ae_dev->priv = hdev; 17337a01c897SSalil Mehta 17347a01c897SSalil Mehta return 0; 17357a01c897SSalil Mehta } 17367a01c897SSalil Mehta 1737e2cb1decSSalil Mehta static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 1738e2cb1decSSalil Mehta { 1739e2cb1decSSalil Mehta struct hnae3_handle *roce = &hdev->roce; 1740e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 1741e2cb1decSSalil Mehta 174207acf909SJian Shen roce->rinfo.num_vectors = hdev->num_roce_msix; 1743e2cb1decSSalil Mehta 1744e2cb1decSSalil Mehta if (hdev->num_msi_left < roce->rinfo.num_vectors || 1745e2cb1decSSalil Mehta hdev->num_msi_left == 0) 1746e2cb1decSSalil Mehta return -EINVAL; 1747e2cb1decSSalil Mehta 174807acf909SJian Shen roce->rinfo.base_vector = hdev->roce_base_vector; 1749e2cb1decSSalil Mehta 1750e2cb1decSSalil Mehta roce->rinfo.netdev = nic->kinfo.netdev; 1751e2cb1decSSalil Mehta roce->rinfo.roce_io_base = hdev->hw.io_base; 1752e2cb1decSSalil Mehta 1753e2cb1decSSalil Mehta roce->pdev = nic->pdev; 1754e2cb1decSSalil Mehta roce->ae_algo = nic->ae_algo; 1755e2cb1decSSalil Mehta roce->numa_node_mask = nic->numa_node_mask; 1756e2cb1decSSalil Mehta 1757e2cb1decSSalil Mehta return 0; 1758e2cb1decSSalil Mehta } 1759e2cb1decSSalil Mehta 1760b26a6feaSPeng Li static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 1761b26a6feaSPeng Li { 1762b26a6feaSPeng Li struct hclgevf_cfg_gro_status_cmd *req; 1763b26a6feaSPeng Li struct hclgevf_desc desc; 1764b26a6feaSPeng Li int ret; 1765b26a6feaSPeng Li 1766b26a6feaSPeng Li if (!hnae3_dev_gro_supported(hdev)) 1767b26a6feaSPeng Li return 0; 1768b26a6feaSPeng Li 1769b26a6feaSPeng Li hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 1770b26a6feaSPeng Li false); 1771b26a6feaSPeng Li req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 1772b26a6feaSPeng Li 1773b26a6feaSPeng Li req->gro_en = cpu_to_le16(en ? 1 : 0); 1774b26a6feaSPeng Li 1775b26a6feaSPeng Li ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1776b26a6feaSPeng Li if (ret) 1777b26a6feaSPeng Li dev_err(&hdev->pdev->dev, 1778b26a6feaSPeng Li "VF GRO hardware config cmd failed, ret = %d.\n", ret); 1779b26a6feaSPeng Li 1780b26a6feaSPeng Li return ret; 1781b26a6feaSPeng Li } 1782b26a6feaSPeng Li 1783e2cb1decSSalil Mehta static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 1784e2cb1decSSalil Mehta { 1785e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1786e2cb1decSSalil Mehta int i, ret; 1787e2cb1decSSalil Mehta 1788e2cb1decSSalil Mehta rss_cfg->rss_size = hdev->rss_size_max; 1789e2cb1decSSalil Mehta 1790374ad291SJian Shen if (hdev->pdev->revision >= 0x21) { 1791374ad291SJian Shen rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 1792374ad291SJian Shen netdev_rss_key_fill(rss_cfg->rss_hash_key, 1793374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 1794374ad291SJian Shen 1795374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 1796374ad291SJian Shen rss_cfg->rss_hash_key); 1797374ad291SJian Shen if (ret) 1798374ad291SJian Shen return ret; 1799d97b3072SJian Shen 1800d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = 1801d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1802d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = 1803d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1804d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = 1805d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1806d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = 1807d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1808d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = 1809d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1810d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = 1811d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1812d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = 1813d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1814d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = 1815d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1816d97b3072SJian Shen 1817d97b3072SJian Shen ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 1818d97b3072SJian Shen if (ret) 1819d97b3072SJian Shen return ret; 1820d97b3072SJian Shen 1821374ad291SJian Shen } 1822374ad291SJian Shen 1823e2cb1decSSalil Mehta /* Initialize RSS indirect table for each vport */ 1824e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 1825e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max; 1826e2cb1decSSalil Mehta 1827e2cb1decSSalil Mehta ret = hclgevf_set_rss_indir_table(hdev); 1828e2cb1decSSalil Mehta if (ret) 1829e2cb1decSSalil Mehta return ret; 1830e2cb1decSSalil Mehta 1831e2cb1decSSalil Mehta return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max); 1832e2cb1decSSalil Mehta } 1833e2cb1decSSalil Mehta 1834e2cb1decSSalil Mehta static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 1835e2cb1decSSalil Mehta { 1836e2cb1decSSalil Mehta /* other vlan config(like, VLAN TX/RX offload) would also be added 1837e2cb1decSSalil Mehta * here later 1838e2cb1decSSalil Mehta */ 1839e2cb1decSSalil Mehta return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 1840e2cb1decSSalil Mehta false); 1841e2cb1decSSalil Mehta } 1842e2cb1decSSalil Mehta 1843e2cb1decSSalil Mehta static int hclgevf_ae_start(struct hnae3_handle *handle) 1844e2cb1decSSalil Mehta { 1845e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1846e2cb1decSSalil Mehta 1847e2cb1decSSalil Mehta /* reset tqp stats */ 1848e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 1849e2cb1decSSalil Mehta 1850e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1851e2cb1decSSalil Mehta 1852e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1853e2cb1decSSalil Mehta mod_timer(&hdev->service_timer, jiffies + HZ); 1854e2cb1decSSalil Mehta 1855e2cb1decSSalil Mehta return 0; 1856e2cb1decSSalil Mehta } 1857e2cb1decSSalil Mehta 1858e2cb1decSSalil Mehta static void hclgevf_ae_stop(struct hnae3_handle *handle) 1859e2cb1decSSalil Mehta { 1860e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1861e2cb1decSSalil Mehta 18622f7e4896SFuyun Liang set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 18632f7e4896SFuyun Liang 1864e2cb1decSSalil Mehta /* reset tqp stats */ 1865e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 18668cc6c1f7SFuyun Liang del_timer_sync(&hdev->service_timer); 18678cc6c1f7SFuyun Liang cancel_work_sync(&hdev->service_task); 1868f5be7967SYunsheng Lin clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 18698cc6c1f7SFuyun Liang hclgevf_update_link_status(hdev, 0); 1870e2cb1decSSalil Mehta } 1871e2cb1decSSalil Mehta 1872a6d818e3SYunsheng Lin static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 1873a6d818e3SYunsheng Lin { 1874a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1875a6d818e3SYunsheng Lin u8 msg_data; 1876a6d818e3SYunsheng Lin 1877a6d818e3SYunsheng Lin msg_data = alive ? 1 : 0; 1878a6d818e3SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE, 1879a6d818e3SYunsheng Lin 0, &msg_data, 1, false, NULL, 0); 1880a6d818e3SYunsheng Lin } 1881a6d818e3SYunsheng Lin 1882a6d818e3SYunsheng Lin static int hclgevf_client_start(struct hnae3_handle *handle) 1883a6d818e3SYunsheng Lin { 1884a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1885a6d818e3SYunsheng Lin 1886a6d818e3SYunsheng Lin mod_timer(&hdev->keep_alive_timer, jiffies + 2 * HZ); 1887a6d818e3SYunsheng Lin return hclgevf_set_alive(handle, true); 1888a6d818e3SYunsheng Lin } 1889a6d818e3SYunsheng Lin 1890a6d818e3SYunsheng Lin static void hclgevf_client_stop(struct hnae3_handle *handle) 1891a6d818e3SYunsheng Lin { 1892a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1893a6d818e3SYunsheng Lin int ret; 1894a6d818e3SYunsheng Lin 1895a6d818e3SYunsheng Lin ret = hclgevf_set_alive(handle, false); 1896a6d818e3SYunsheng Lin if (ret) 1897a6d818e3SYunsheng Lin dev_warn(&hdev->pdev->dev, 1898a6d818e3SYunsheng Lin "%s failed %d\n", __func__, ret); 1899a6d818e3SYunsheng Lin 1900a6d818e3SYunsheng Lin del_timer_sync(&hdev->keep_alive_timer); 1901a6d818e3SYunsheng Lin cancel_work_sync(&hdev->keep_alive_task); 1902a6d818e3SYunsheng Lin } 1903a6d818e3SYunsheng Lin 1904e2cb1decSSalil Mehta static void hclgevf_state_init(struct hclgevf_dev *hdev) 1905e2cb1decSSalil Mehta { 1906e2cb1decSSalil Mehta /* setup tasks for the MBX */ 1907e2cb1decSSalil Mehta INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 1908e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1909e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1910e2cb1decSSalil Mehta 1911e2cb1decSSalil Mehta /* setup tasks for service timer */ 1912e2cb1decSSalil Mehta timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 1913e2cb1decSSalil Mehta 1914e2cb1decSSalil Mehta INIT_WORK(&hdev->service_task, hclgevf_service_task); 1915e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1916e2cb1decSSalil Mehta 191735a1e503SSalil Mehta INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task); 191835a1e503SSalil Mehta 1919e2cb1decSSalil Mehta mutex_init(&hdev->mbx_resp.mbx_mutex); 1920e2cb1decSSalil Mehta 1921e2cb1decSSalil Mehta /* bring the device down */ 1922e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1923e2cb1decSSalil Mehta } 1924e2cb1decSSalil Mehta 1925e2cb1decSSalil Mehta static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 1926e2cb1decSSalil Mehta { 1927e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1928e2cb1decSSalil Mehta 1929e2cb1decSSalil Mehta if (hdev->service_timer.function) 1930e2cb1decSSalil Mehta del_timer_sync(&hdev->service_timer); 1931e2cb1decSSalil Mehta if (hdev->service_task.func) 1932e2cb1decSSalil Mehta cancel_work_sync(&hdev->service_task); 1933e2cb1decSSalil Mehta if (hdev->mbx_service_task.func) 1934e2cb1decSSalil Mehta cancel_work_sync(&hdev->mbx_service_task); 193535a1e503SSalil Mehta if (hdev->rst_service_task.func) 193635a1e503SSalil Mehta cancel_work_sync(&hdev->rst_service_task); 1937e2cb1decSSalil Mehta 1938e2cb1decSSalil Mehta mutex_destroy(&hdev->mbx_resp.mbx_mutex); 1939e2cb1decSSalil Mehta } 1940e2cb1decSSalil Mehta 1941e2cb1decSSalil Mehta static int hclgevf_init_msi(struct hclgevf_dev *hdev) 1942e2cb1decSSalil Mehta { 1943e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 1944e2cb1decSSalil Mehta int vectors; 1945e2cb1decSSalil Mehta int i; 1946e2cb1decSSalil Mehta 194707acf909SJian Shen if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) 194807acf909SJian Shen vectors = pci_alloc_irq_vectors(pdev, 194907acf909SJian Shen hdev->roce_base_msix_offset + 1, 195007acf909SJian Shen hdev->num_msi, 195107acf909SJian Shen PCI_IRQ_MSIX); 195207acf909SJian Shen else 1953e2cb1decSSalil Mehta vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 1954e2cb1decSSalil Mehta PCI_IRQ_MSI | PCI_IRQ_MSIX); 195507acf909SJian Shen 1956e2cb1decSSalil Mehta if (vectors < 0) { 1957e2cb1decSSalil Mehta dev_err(&pdev->dev, 1958e2cb1decSSalil Mehta "failed(%d) to allocate MSI/MSI-X vectors\n", 1959e2cb1decSSalil Mehta vectors); 1960e2cb1decSSalil Mehta return vectors; 1961e2cb1decSSalil Mehta } 1962e2cb1decSSalil Mehta if (vectors < hdev->num_msi) 1963e2cb1decSSalil Mehta dev_warn(&hdev->pdev->dev, 1964e2cb1decSSalil Mehta "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 1965e2cb1decSSalil Mehta hdev->num_msi, vectors); 1966e2cb1decSSalil Mehta 1967e2cb1decSSalil Mehta hdev->num_msi = vectors; 1968e2cb1decSSalil Mehta hdev->num_msi_left = vectors; 1969e2cb1decSSalil Mehta hdev->base_msi_vector = pdev->irq; 197007acf909SJian Shen hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 1971e2cb1decSSalil Mehta 1972e2cb1decSSalil Mehta hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 1973e2cb1decSSalil Mehta sizeof(u16), GFP_KERNEL); 1974e2cb1decSSalil Mehta if (!hdev->vector_status) { 1975e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 1976e2cb1decSSalil Mehta return -ENOMEM; 1977e2cb1decSSalil Mehta } 1978e2cb1decSSalil Mehta 1979e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 1980e2cb1decSSalil Mehta hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 1981e2cb1decSSalil Mehta 1982e2cb1decSSalil Mehta hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 1983e2cb1decSSalil Mehta sizeof(int), GFP_KERNEL); 1984e2cb1decSSalil Mehta if (!hdev->vector_irq) { 1985862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 1986e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 1987e2cb1decSSalil Mehta return -ENOMEM; 1988e2cb1decSSalil Mehta } 1989e2cb1decSSalil Mehta 1990e2cb1decSSalil Mehta return 0; 1991e2cb1decSSalil Mehta } 1992e2cb1decSSalil Mehta 1993e2cb1decSSalil Mehta static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 1994e2cb1decSSalil Mehta { 1995e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 1996e2cb1decSSalil Mehta 1997862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 1998862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_irq); 1999e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2000e2cb1decSSalil Mehta } 2001e2cb1decSSalil Mehta 2002e2cb1decSSalil Mehta static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2003e2cb1decSSalil Mehta { 2004e2cb1decSSalil Mehta int ret = 0; 2005e2cb1decSSalil Mehta 2006e2cb1decSSalil Mehta hclgevf_get_misc_vector(hdev); 2007e2cb1decSSalil Mehta 2008e2cb1decSSalil Mehta ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2009e2cb1decSSalil Mehta 0, "hclgevf_cmd", hdev); 2010e2cb1decSSalil Mehta if (ret) { 2011e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2012e2cb1decSSalil Mehta hdev->misc_vector.vector_irq); 2013e2cb1decSSalil Mehta return ret; 2014e2cb1decSSalil Mehta } 2015e2cb1decSSalil Mehta 20161819e409SXi Wang hclgevf_clear_event_cause(hdev, 0); 20171819e409SXi Wang 2018e2cb1decSSalil Mehta /* enable misc. vector(vector 0) */ 2019e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2020e2cb1decSSalil Mehta 2021e2cb1decSSalil Mehta return ret; 2022e2cb1decSSalil Mehta } 2023e2cb1decSSalil Mehta 2024e2cb1decSSalil Mehta static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2025e2cb1decSSalil Mehta { 2026e2cb1decSSalil Mehta /* disable misc vector(vector 0) */ 2027e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 20281819e409SXi Wang synchronize_irq(hdev->misc_vector.vector_irq); 2029e2cb1decSSalil Mehta free_irq(hdev->misc_vector.vector_irq, hdev); 2030e2cb1decSSalil Mehta hclgevf_free_vector(hdev, 0); 2031e2cb1decSSalil Mehta } 2032e2cb1decSSalil Mehta 2033e718a93fSPeng Li static int hclgevf_init_client_instance(struct hnae3_client *client, 2034e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2035e2cb1decSSalil Mehta { 2036e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2037e2cb1decSSalil Mehta int ret; 2038e2cb1decSSalil Mehta 2039e2cb1decSSalil Mehta switch (client->type) { 2040e2cb1decSSalil Mehta case HNAE3_CLIENT_KNIC: 2041e2cb1decSSalil Mehta hdev->nic_client = client; 2042e2cb1decSSalil Mehta hdev->nic.client = client; 2043e2cb1decSSalil Mehta 2044e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->nic); 2045e2cb1decSSalil Mehta if (ret) 204649dd8054SJian Shen goto clear_nic; 2047e2cb1decSSalil Mehta 2048d9f28fc2SJian Shen hnae3_set_client_init_flag(client, ae_dev, 1); 2049d9f28fc2SJian Shen 2050e2cb1decSSalil Mehta if (hdev->roce_client && hnae3_dev_roce_supported(hdev)) { 2051e2cb1decSSalil Mehta struct hnae3_client *rc = hdev->roce_client; 2052e2cb1decSSalil Mehta 2053e2cb1decSSalil Mehta ret = hclgevf_init_roce_base_info(hdev); 2054e2cb1decSSalil Mehta if (ret) 205549dd8054SJian Shen goto clear_roce; 2056e2cb1decSSalil Mehta ret = rc->ops->init_instance(&hdev->roce); 2057e2cb1decSSalil Mehta if (ret) 205849dd8054SJian Shen goto clear_roce; 2059d9f28fc2SJian Shen 2060d9f28fc2SJian Shen hnae3_set_client_init_flag(hdev->roce_client, ae_dev, 2061d9f28fc2SJian Shen 1); 2062e2cb1decSSalil Mehta } 2063e2cb1decSSalil Mehta break; 2064e2cb1decSSalil Mehta case HNAE3_CLIENT_UNIC: 2065e2cb1decSSalil Mehta hdev->nic_client = client; 2066e2cb1decSSalil Mehta hdev->nic.client = client; 2067e2cb1decSSalil Mehta 2068e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->nic); 2069e2cb1decSSalil Mehta if (ret) 207049dd8054SJian Shen goto clear_nic; 2071d9f28fc2SJian Shen 2072d9f28fc2SJian Shen hnae3_set_client_init_flag(client, ae_dev, 1); 2073e2cb1decSSalil Mehta break; 2074e2cb1decSSalil Mehta case HNAE3_CLIENT_ROCE: 2075544a7bcdSLijun Ou if (hnae3_dev_roce_supported(hdev)) { 2076e2cb1decSSalil Mehta hdev->roce_client = client; 2077e2cb1decSSalil Mehta hdev->roce.client = client; 2078544a7bcdSLijun Ou } 2079e2cb1decSSalil Mehta 2080544a7bcdSLijun Ou if (hdev->roce_client && hdev->nic_client) { 2081e2cb1decSSalil Mehta ret = hclgevf_init_roce_base_info(hdev); 2082e2cb1decSSalil Mehta if (ret) 208349dd8054SJian Shen goto clear_roce; 2084e2cb1decSSalil Mehta 2085e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->roce); 2086e2cb1decSSalil Mehta if (ret) 208749dd8054SJian Shen goto clear_roce; 2088e2cb1decSSalil Mehta } 2089d9f28fc2SJian Shen 2090d9f28fc2SJian Shen hnae3_set_client_init_flag(client, ae_dev, 1); 2091fa7a4bd5SJian Shen break; 2092fa7a4bd5SJian Shen default: 2093fa7a4bd5SJian Shen return -EINVAL; 2094e2cb1decSSalil Mehta } 2095e2cb1decSSalil Mehta 2096e2cb1decSSalil Mehta return 0; 209749dd8054SJian Shen 209849dd8054SJian Shen clear_nic: 209949dd8054SJian Shen hdev->nic_client = NULL; 210049dd8054SJian Shen hdev->nic.client = NULL; 210149dd8054SJian Shen return ret; 210249dd8054SJian Shen clear_roce: 210349dd8054SJian Shen hdev->roce_client = NULL; 210449dd8054SJian Shen hdev->roce.client = NULL; 210549dd8054SJian Shen return ret; 2106e2cb1decSSalil Mehta } 2107e2cb1decSSalil Mehta 2108e718a93fSPeng Li static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2109e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2110e2cb1decSSalil Mehta { 2111e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2112e718a93fSPeng Li 2113e2cb1decSSalil Mehta /* un-init roce, if it exists */ 211449dd8054SJian Shen if (hdev->roce_client) { 2115e2cb1decSSalil Mehta hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 211649dd8054SJian Shen hdev->roce_client = NULL; 211749dd8054SJian Shen hdev->roce.client = NULL; 211849dd8054SJian Shen } 2119e2cb1decSSalil Mehta 2120e2cb1decSSalil Mehta /* un-init nic/unic, if this was not called by roce client */ 212149dd8054SJian Shen if (client->ops->uninit_instance && hdev->nic_client && 212249dd8054SJian Shen client->type != HNAE3_CLIENT_ROCE) { 2123e2cb1decSSalil Mehta client->ops->uninit_instance(&hdev->nic, 0); 212449dd8054SJian Shen hdev->nic_client = NULL; 212549dd8054SJian Shen hdev->nic.client = NULL; 212649dd8054SJian Shen } 2127e2cb1decSSalil Mehta } 2128e2cb1decSSalil Mehta 2129e2cb1decSSalil Mehta static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2130e2cb1decSSalil Mehta { 2131e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2132e2cb1decSSalil Mehta struct hclgevf_hw *hw; 2133e2cb1decSSalil Mehta int ret; 2134e2cb1decSSalil Mehta 2135e2cb1decSSalil Mehta ret = pci_enable_device(pdev); 2136e2cb1decSSalil Mehta if (ret) { 2137e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed to enable PCI device\n"); 21383e249d3bSFuyun Liang return ret; 2139e2cb1decSSalil Mehta } 2140e2cb1decSSalil Mehta 2141e2cb1decSSalil Mehta ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2142e2cb1decSSalil Mehta if (ret) { 2143e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2144e2cb1decSSalil Mehta goto err_disable_device; 2145e2cb1decSSalil Mehta } 2146e2cb1decSSalil Mehta 2147e2cb1decSSalil Mehta ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2148e2cb1decSSalil Mehta if (ret) { 2149e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2150e2cb1decSSalil Mehta goto err_disable_device; 2151e2cb1decSSalil Mehta } 2152e2cb1decSSalil Mehta 2153e2cb1decSSalil Mehta pci_set_master(pdev); 2154e2cb1decSSalil Mehta hw = &hdev->hw; 2155e2cb1decSSalil Mehta hw->hdev = hdev; 21562e1ea493SPeng Li hw->io_base = pci_iomap(pdev, 2, 0); 2157e2cb1decSSalil Mehta if (!hw->io_base) { 2158e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't map configuration register space\n"); 2159e2cb1decSSalil Mehta ret = -ENOMEM; 2160e2cb1decSSalil Mehta goto err_clr_master; 2161e2cb1decSSalil Mehta } 2162e2cb1decSSalil Mehta 2163e2cb1decSSalil Mehta return 0; 2164e2cb1decSSalil Mehta 2165e2cb1decSSalil Mehta err_clr_master: 2166e2cb1decSSalil Mehta pci_clear_master(pdev); 2167e2cb1decSSalil Mehta pci_release_regions(pdev); 2168e2cb1decSSalil Mehta err_disable_device: 2169e2cb1decSSalil Mehta pci_disable_device(pdev); 21703e249d3bSFuyun Liang 2171e2cb1decSSalil Mehta return ret; 2172e2cb1decSSalil Mehta } 2173e2cb1decSSalil Mehta 2174e2cb1decSSalil Mehta static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2175e2cb1decSSalil Mehta { 2176e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2177e2cb1decSSalil Mehta 2178e2cb1decSSalil Mehta pci_iounmap(pdev, hdev->hw.io_base); 2179e2cb1decSSalil Mehta pci_clear_master(pdev); 2180e2cb1decSSalil Mehta pci_release_regions(pdev); 2181e2cb1decSSalil Mehta pci_disable_device(pdev); 2182e2cb1decSSalil Mehta } 2183e2cb1decSSalil Mehta 218407acf909SJian Shen static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 218507acf909SJian Shen { 218607acf909SJian Shen struct hclgevf_query_res_cmd *req; 218707acf909SJian Shen struct hclgevf_desc desc; 218807acf909SJian Shen int ret; 218907acf909SJian Shen 219007acf909SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 219107acf909SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 219207acf909SJian Shen if (ret) { 219307acf909SJian Shen dev_err(&hdev->pdev->dev, 219407acf909SJian Shen "query vf resource failed, ret = %d.\n", ret); 219507acf909SJian Shen return ret; 219607acf909SJian Shen } 219707acf909SJian Shen 219807acf909SJian Shen req = (struct hclgevf_query_res_cmd *)desc.data; 219907acf909SJian Shen 220007acf909SJian Shen if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) { 220107acf909SJian Shen hdev->roce_base_msix_offset = 220207acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 220307acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_M, 220407acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_S); 220507acf909SJian Shen hdev->num_roce_msix = 220607acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 220707acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 220807acf909SJian Shen 220907acf909SJian Shen /* VF should have NIC vectors and Roce vectors, NIC vectors 221007acf909SJian Shen * are queued before Roce vectors. The offset is fixed to 64. 221107acf909SJian Shen */ 221207acf909SJian Shen hdev->num_msi = hdev->num_roce_msix + 221307acf909SJian Shen hdev->roce_base_msix_offset; 221407acf909SJian Shen } else { 221507acf909SJian Shen hdev->num_msi = 221607acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 221707acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 221807acf909SJian Shen } 221907acf909SJian Shen 222007acf909SJian Shen return 0; 222107acf909SJian Shen } 222207acf909SJian Shen 2223862d969aSHuazhong Tan static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2224862d969aSHuazhong Tan { 2225862d969aSHuazhong Tan struct pci_dev *pdev = hdev->pdev; 2226862d969aSHuazhong Tan int ret = 0; 2227862d969aSHuazhong Tan 2228862d969aSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2229862d969aSHuazhong Tan test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2230862d969aSHuazhong Tan hclgevf_misc_irq_uninit(hdev); 2231862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2232862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2233862d969aSHuazhong Tan } 2234862d969aSHuazhong Tan 2235862d969aSHuazhong Tan if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2236862d969aSHuazhong Tan pci_set_master(pdev); 2237862d969aSHuazhong Tan ret = hclgevf_init_msi(hdev); 2238862d969aSHuazhong Tan if (ret) { 2239862d969aSHuazhong Tan dev_err(&pdev->dev, 2240862d969aSHuazhong Tan "failed(%d) to init MSI/MSI-X\n", ret); 2241862d969aSHuazhong Tan return ret; 2242862d969aSHuazhong Tan } 2243862d969aSHuazhong Tan 2244862d969aSHuazhong Tan ret = hclgevf_misc_irq_init(hdev); 2245862d969aSHuazhong Tan if (ret) { 2246862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2247862d969aSHuazhong Tan dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2248862d969aSHuazhong Tan ret); 2249862d969aSHuazhong Tan return ret; 2250862d969aSHuazhong Tan } 2251862d969aSHuazhong Tan 2252862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2253862d969aSHuazhong Tan } 2254862d969aSHuazhong Tan 2255862d969aSHuazhong Tan return ret; 2256862d969aSHuazhong Tan } 2257862d969aSHuazhong Tan 22589c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2259e2cb1decSSalil Mehta { 22607a01c897SSalil Mehta struct pci_dev *pdev = hdev->pdev; 2261e2cb1decSSalil Mehta int ret; 2262e2cb1decSSalil Mehta 2263862d969aSHuazhong Tan ret = hclgevf_pci_reset(hdev); 2264862d969aSHuazhong Tan if (ret) { 2265862d969aSHuazhong Tan dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2266862d969aSHuazhong Tan return ret; 2267862d969aSHuazhong Tan } 2268862d969aSHuazhong Tan 22699c6f7085SHuazhong Tan ret = hclgevf_cmd_init(hdev); 22709c6f7085SHuazhong Tan if (ret) { 22719c6f7085SHuazhong Tan dev_err(&pdev->dev, "cmd failed %d\n", ret); 22729c6f7085SHuazhong Tan return ret; 22737a01c897SSalil Mehta } 2274e2cb1decSSalil Mehta 22759c6f7085SHuazhong Tan ret = hclgevf_rss_init_hw(hdev); 22769c6f7085SHuazhong Tan if (ret) { 22779c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 22789c6f7085SHuazhong Tan "failed(%d) to initialize RSS\n", ret); 22799c6f7085SHuazhong Tan return ret; 22809c6f7085SHuazhong Tan } 22819c6f7085SHuazhong Tan 2282b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2283b26a6feaSPeng Li if (ret) 2284b26a6feaSPeng Li return ret; 2285b26a6feaSPeng Li 22869c6f7085SHuazhong Tan ret = hclgevf_init_vlan_config(hdev); 22879c6f7085SHuazhong Tan if (ret) { 22889c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 22899c6f7085SHuazhong Tan "failed(%d) to initialize VLAN config\n", ret); 22909c6f7085SHuazhong Tan return ret; 22919c6f7085SHuazhong Tan } 22929c6f7085SHuazhong Tan 22939c6f7085SHuazhong Tan dev_info(&hdev->pdev->dev, "Reset done\n"); 22949c6f7085SHuazhong Tan 22959c6f7085SHuazhong Tan return 0; 22969c6f7085SHuazhong Tan } 22979c6f7085SHuazhong Tan 22989c6f7085SHuazhong Tan static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 22999c6f7085SHuazhong Tan { 23009c6f7085SHuazhong Tan struct pci_dev *pdev = hdev->pdev; 23019c6f7085SHuazhong Tan int ret; 23029c6f7085SHuazhong Tan 2303e2cb1decSSalil Mehta ret = hclgevf_pci_init(hdev); 2304e2cb1decSSalil Mehta if (ret) { 2305e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI initialization failed\n"); 2306e2cb1decSSalil Mehta return ret; 2307e2cb1decSSalil Mehta } 2308e2cb1decSSalil Mehta 23098b0195a3SHuazhong Tan ret = hclgevf_cmd_queue_init(hdev); 23108b0195a3SHuazhong Tan if (ret) { 23118b0195a3SHuazhong Tan dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret); 23128b0195a3SHuazhong Tan goto err_cmd_queue_init; 23138b0195a3SHuazhong Tan } 23148b0195a3SHuazhong Tan 2315eddf0462SYunsheng Lin ret = hclgevf_cmd_init(hdev); 2316eddf0462SYunsheng Lin if (ret) 2317eddf0462SYunsheng Lin goto err_cmd_init; 2318eddf0462SYunsheng Lin 231907acf909SJian Shen /* Get vf resource */ 232007acf909SJian Shen ret = hclgevf_query_vf_resource(hdev); 232107acf909SJian Shen if (ret) { 232207acf909SJian Shen dev_err(&hdev->pdev->dev, 232307acf909SJian Shen "Query vf status error, ret = %d.\n", ret); 23248b0195a3SHuazhong Tan goto err_cmd_init; 232507acf909SJian Shen } 232607acf909SJian Shen 232707acf909SJian Shen ret = hclgevf_init_msi(hdev); 232807acf909SJian Shen if (ret) { 232907acf909SJian Shen dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 23308b0195a3SHuazhong Tan goto err_cmd_init; 233107acf909SJian Shen } 233207acf909SJian Shen 233307acf909SJian Shen hclgevf_state_init(hdev); 2334dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 233507acf909SJian Shen 2336e2cb1decSSalil Mehta ret = hclgevf_misc_irq_init(hdev); 2337e2cb1decSSalil Mehta if (ret) { 2338e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2339e2cb1decSSalil Mehta ret); 2340e2cb1decSSalil Mehta goto err_misc_irq_init; 2341e2cb1decSSalil Mehta } 2342e2cb1decSSalil Mehta 2343862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2344862d969aSHuazhong Tan 2345e2cb1decSSalil Mehta ret = hclgevf_configure(hdev); 2346e2cb1decSSalil Mehta if (ret) { 2347e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2348e2cb1decSSalil Mehta goto err_config; 2349e2cb1decSSalil Mehta } 2350e2cb1decSSalil Mehta 2351e2cb1decSSalil Mehta ret = hclgevf_alloc_tqps(hdev); 2352e2cb1decSSalil Mehta if (ret) { 2353e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2354e2cb1decSSalil Mehta goto err_config; 2355e2cb1decSSalil Mehta } 2356e2cb1decSSalil Mehta 2357e2cb1decSSalil Mehta ret = hclgevf_set_handle_info(hdev); 2358e2cb1decSSalil Mehta if (ret) { 2359e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 2360e2cb1decSSalil Mehta goto err_config; 2361e2cb1decSSalil Mehta } 2362e2cb1decSSalil Mehta 2363b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2364b26a6feaSPeng Li if (ret) 2365b26a6feaSPeng Li goto err_config; 2366b26a6feaSPeng Li 2367e2cb1decSSalil Mehta /* Initialize RSS for this VF */ 2368e2cb1decSSalil Mehta ret = hclgevf_rss_init_hw(hdev); 2369e2cb1decSSalil Mehta if (ret) { 2370e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2371e2cb1decSSalil Mehta "failed(%d) to initialize RSS\n", ret); 2372e2cb1decSSalil Mehta goto err_config; 2373e2cb1decSSalil Mehta } 2374e2cb1decSSalil Mehta 2375e2cb1decSSalil Mehta ret = hclgevf_init_vlan_config(hdev); 2376e2cb1decSSalil Mehta if (ret) { 2377e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2378e2cb1decSSalil Mehta "failed(%d) to initialize VLAN config\n", ret); 2379e2cb1decSSalil Mehta goto err_config; 2380e2cb1decSSalil Mehta } 2381e2cb1decSSalil Mehta 23820742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 2383e2cb1decSSalil Mehta pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME); 2384e2cb1decSSalil Mehta 2385e2cb1decSSalil Mehta return 0; 2386e2cb1decSSalil Mehta 2387e2cb1decSSalil Mehta err_config: 2388e2cb1decSSalil Mehta hclgevf_misc_irq_uninit(hdev); 2389e2cb1decSSalil Mehta err_misc_irq_init: 2390e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2391e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 239207acf909SJian Shen err_cmd_init: 23938b0195a3SHuazhong Tan hclgevf_cmd_uninit(hdev); 23948b0195a3SHuazhong Tan err_cmd_queue_init: 2395e2cb1decSSalil Mehta hclgevf_pci_uninit(hdev); 2396862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2397e2cb1decSSalil Mehta return ret; 2398e2cb1decSSalil Mehta } 2399e2cb1decSSalil Mehta 24007a01c897SSalil Mehta static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2401e2cb1decSSalil Mehta { 2402e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2403862d969aSHuazhong Tan 2404862d969aSHuazhong Tan if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2405eddf0462SYunsheng Lin hclgevf_misc_irq_uninit(hdev); 2406e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 24077a01c897SSalil Mehta } 24087a01c897SSalil Mehta 2409e3338205SHuazhong Tan hclgevf_pci_uninit(hdev); 2410862d969aSHuazhong Tan hclgevf_cmd_uninit(hdev); 2411862d969aSHuazhong Tan } 2412862d969aSHuazhong Tan 24137a01c897SSalil Mehta static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 24147a01c897SSalil Mehta { 24157a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 2416a6d818e3SYunsheng Lin struct hclgevf_dev *hdev; 24177a01c897SSalil Mehta int ret; 24187a01c897SSalil Mehta 24197a01c897SSalil Mehta ret = hclgevf_alloc_hdev(ae_dev); 24207a01c897SSalil Mehta if (ret) { 24217a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device allocation failed\n"); 24227a01c897SSalil Mehta return ret; 24237a01c897SSalil Mehta } 24247a01c897SSalil Mehta 24257a01c897SSalil Mehta ret = hclgevf_init_hdev(ae_dev->priv); 2426a6d818e3SYunsheng Lin if (ret) { 24277a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device initialization failed\n"); 24287a01c897SSalil Mehta return ret; 24297a01c897SSalil Mehta } 24307a01c897SSalil Mehta 2431a6d818e3SYunsheng Lin hdev = ae_dev->priv; 2432a6d818e3SYunsheng Lin timer_setup(&hdev->keep_alive_timer, hclgevf_keep_alive_timer, 0); 2433a6d818e3SYunsheng Lin INIT_WORK(&hdev->keep_alive_task, hclgevf_keep_alive_task); 2434a6d818e3SYunsheng Lin 2435a6d818e3SYunsheng Lin return 0; 2436a6d818e3SYunsheng Lin } 2437a6d818e3SYunsheng Lin 24387a01c897SSalil Mehta static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 24397a01c897SSalil Mehta { 24407a01c897SSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 24417a01c897SSalil Mehta 24427a01c897SSalil Mehta hclgevf_uninit_hdev(hdev); 2443e2cb1decSSalil Mehta ae_dev->priv = NULL; 2444e2cb1decSSalil Mehta } 2445e2cb1decSSalil Mehta 2446849e4607SPeng Li static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2447849e4607SPeng Li { 2448849e4607SPeng Li struct hnae3_handle *nic = &hdev->nic; 2449849e4607SPeng Li struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2450849e4607SPeng Li 2451849e4607SPeng Li return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps); 2452849e4607SPeng Li } 2453849e4607SPeng Li 2454849e4607SPeng Li /** 2455849e4607SPeng Li * hclgevf_get_channels - Get the current channels enabled and max supported. 2456849e4607SPeng Li * @handle: hardware information for network interface 2457849e4607SPeng Li * @ch: ethtool channels structure 2458849e4607SPeng Li * 2459849e4607SPeng Li * We don't support separate tx and rx queues as channels. The other count 2460849e4607SPeng Li * represents how many queues are being used for control. max_combined counts 2461849e4607SPeng Li * how many queue pairs we can support. They may not be mapped 1 to 1 with 2462849e4607SPeng Li * q_vectors since we support a lot more queue pairs than q_vectors. 2463849e4607SPeng Li **/ 2464849e4607SPeng Li static void hclgevf_get_channels(struct hnae3_handle *handle, 2465849e4607SPeng Li struct ethtool_channels *ch) 2466849e4607SPeng Li { 2467849e4607SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2468849e4607SPeng Li 2469849e4607SPeng Li ch->max_combined = hclgevf_get_max_channels(hdev); 2470849e4607SPeng Li ch->other_count = 0; 2471849e4607SPeng Li ch->max_other = 0; 2472849e4607SPeng Li ch->combined_count = hdev->num_tqps; 2473849e4607SPeng Li } 2474849e4607SPeng Li 2475cc719218SPeng Li static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 24760d43bf45SHuazhong Tan u16 *alloc_tqps, u16 *max_rss_size) 2477cc719218SPeng Li { 2478cc719218SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2479cc719218SPeng Li 24800d43bf45SHuazhong Tan *alloc_tqps = hdev->num_tqps; 2481cc719218SPeng Li *max_rss_size = hdev->rss_size_max; 2482cc719218SPeng Li } 2483cc719218SPeng Li 2484175ec96bSFuyun Liang static int hclgevf_get_status(struct hnae3_handle *handle) 2485175ec96bSFuyun Liang { 2486175ec96bSFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2487175ec96bSFuyun Liang 2488175ec96bSFuyun Liang return hdev->hw.mac.link; 2489175ec96bSFuyun Liang } 2490175ec96bSFuyun Liang 24914a152de9SFuyun Liang static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 24924a152de9SFuyun Liang u8 *auto_neg, u32 *speed, 24934a152de9SFuyun Liang u8 *duplex) 24944a152de9SFuyun Liang { 24954a152de9SFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 24964a152de9SFuyun Liang 24974a152de9SFuyun Liang if (speed) 24984a152de9SFuyun Liang *speed = hdev->hw.mac.speed; 24994a152de9SFuyun Liang if (duplex) 25004a152de9SFuyun Liang *duplex = hdev->hw.mac.duplex; 25014a152de9SFuyun Liang if (auto_neg) 25024a152de9SFuyun Liang *auto_neg = AUTONEG_DISABLE; 25034a152de9SFuyun Liang } 25044a152de9SFuyun Liang 25054a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 25064a152de9SFuyun Liang u8 duplex) 25074a152de9SFuyun Liang { 25084a152de9SFuyun Liang hdev->hw.mac.speed = speed; 25094a152de9SFuyun Liang hdev->hw.mac.duplex = duplex; 25104a152de9SFuyun Liang } 25114a152de9SFuyun Liang 25125c9f6b39SPeng Li static int hclgevf_gro_en(struct hnae3_handle *handle, int enable) 25135c9f6b39SPeng Li { 25145c9f6b39SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 25155c9f6b39SPeng Li 25165c9f6b39SPeng Li return hclgevf_config_gro(hdev, enable); 25175c9f6b39SPeng Li } 25185c9f6b39SPeng Li 2519c136b884SPeng Li static void hclgevf_get_media_type(struct hnae3_handle *handle, 2520c136b884SPeng Li u8 *media_type) 2521c136b884SPeng Li { 2522c136b884SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2523c136b884SPeng Li if (media_type) 2524c136b884SPeng Li *media_type = hdev->hw.mac.media_type; 2525c136b884SPeng Li } 2526c136b884SPeng Li 25274d60291bSHuazhong Tan static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 25284d60291bSHuazhong Tan { 25294d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 25304d60291bSHuazhong Tan 2531aa5c4f17SHuazhong Tan return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 25324d60291bSHuazhong Tan } 25334d60291bSHuazhong Tan 25344d60291bSHuazhong Tan static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 25354d60291bSHuazhong Tan { 25364d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 25374d60291bSHuazhong Tan 25384d60291bSHuazhong Tan return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 25394d60291bSHuazhong Tan } 25404d60291bSHuazhong Tan 25414d60291bSHuazhong Tan static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 25424d60291bSHuazhong Tan { 25434d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 25444d60291bSHuazhong Tan 25454d60291bSHuazhong Tan return hdev->reset_count; 25464d60291bSHuazhong Tan } 25474d60291bSHuazhong Tan 25481600c3e5SJian Shen #define MAX_SEPARATE_NUM 4 25491600c3e5SJian Shen #define SEPARATOR_VALUE 0xFFFFFFFF 25501600c3e5SJian Shen #define REG_NUM_PER_LINE 4 25511600c3e5SJian Shen #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 25521600c3e5SJian Shen 25531600c3e5SJian Shen static int hclgevf_get_regs_len(struct hnae3_handle *handle) 25541600c3e5SJian Shen { 25551600c3e5SJian Shen int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 25561600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 25571600c3e5SJian Shen 25581600c3e5SJian Shen cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 25591600c3e5SJian Shen common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 25601600c3e5SJian Shen ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 25611600c3e5SJian Shen tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 25621600c3e5SJian Shen 25631600c3e5SJian Shen return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 25641600c3e5SJian Shen tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 25651600c3e5SJian Shen } 25661600c3e5SJian Shen 25671600c3e5SJian Shen static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 25681600c3e5SJian Shen void *data) 25691600c3e5SJian Shen { 25701600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 25711600c3e5SJian Shen int i, j, reg_um, separator_num; 25721600c3e5SJian Shen u32 *reg = data; 25731600c3e5SJian Shen 25741600c3e5SJian Shen *version = hdev->fw_version; 25751600c3e5SJian Shen 25761600c3e5SJian Shen /* fetching per-VF registers values from VF PCIe register space */ 25771600c3e5SJian Shen reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 25781600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 25791600c3e5SJian Shen for (i = 0; i < reg_um; i++) 25801600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 25811600c3e5SJian Shen for (i = 0; i < separator_num; i++) 25821600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 25831600c3e5SJian Shen 25841600c3e5SJian Shen reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 25851600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 25861600c3e5SJian Shen for (i = 0; i < reg_um; i++) 25871600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 25881600c3e5SJian Shen for (i = 0; i < separator_num; i++) 25891600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 25901600c3e5SJian Shen 25911600c3e5SJian Shen reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 25921600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 25931600c3e5SJian Shen for (j = 0; j < hdev->num_tqps; j++) { 25941600c3e5SJian Shen for (i = 0; i < reg_um; i++) 25951600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 25961600c3e5SJian Shen ring_reg_addr_list[i] + 25971600c3e5SJian Shen 0x200 * j); 25981600c3e5SJian Shen for (i = 0; i < separator_num; i++) 25991600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 26001600c3e5SJian Shen } 26011600c3e5SJian Shen 26021600c3e5SJian Shen reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 26031600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 26041600c3e5SJian Shen for (j = 0; j < hdev->num_msi_used - 1; j++) { 26051600c3e5SJian Shen for (i = 0; i < reg_um; i++) 26061600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 26071600c3e5SJian Shen tqp_intr_reg_addr_list[i] + 26081600c3e5SJian Shen 4 * j); 26091600c3e5SJian Shen for (i = 0; i < separator_num; i++) 26101600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 26111600c3e5SJian Shen } 26121600c3e5SJian Shen } 26131600c3e5SJian Shen 2614e2cb1decSSalil Mehta static const struct hnae3_ae_ops hclgevf_ops = { 2615e2cb1decSSalil Mehta .init_ae_dev = hclgevf_init_ae_dev, 2616e2cb1decSSalil Mehta .uninit_ae_dev = hclgevf_uninit_ae_dev, 26176ff3cf07SHuazhong Tan .flr_prepare = hclgevf_flr_prepare, 26186ff3cf07SHuazhong Tan .flr_done = hclgevf_flr_done, 2619e718a93fSPeng Li .init_client_instance = hclgevf_init_client_instance, 2620e718a93fSPeng Li .uninit_client_instance = hclgevf_uninit_client_instance, 2621e2cb1decSSalil Mehta .start = hclgevf_ae_start, 2622e2cb1decSSalil Mehta .stop = hclgevf_ae_stop, 2623a6d818e3SYunsheng Lin .client_start = hclgevf_client_start, 2624a6d818e3SYunsheng Lin .client_stop = hclgevf_client_stop, 2625e2cb1decSSalil Mehta .map_ring_to_vector = hclgevf_map_ring_to_vector, 2626e2cb1decSSalil Mehta .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 2627e2cb1decSSalil Mehta .get_vector = hclgevf_get_vector, 26280d3e6631SYunsheng Lin .put_vector = hclgevf_put_vector, 2629e2cb1decSSalil Mehta .reset_queue = hclgevf_reset_tqp, 2630e2cb1decSSalil Mehta .set_promisc_mode = hclgevf_set_promisc_mode, 2631e2cb1decSSalil Mehta .get_mac_addr = hclgevf_get_mac_addr, 2632e2cb1decSSalil Mehta .set_mac_addr = hclgevf_set_mac_addr, 2633e2cb1decSSalil Mehta .add_uc_addr = hclgevf_add_uc_addr, 2634e2cb1decSSalil Mehta .rm_uc_addr = hclgevf_rm_uc_addr, 2635e2cb1decSSalil Mehta .add_mc_addr = hclgevf_add_mc_addr, 2636e2cb1decSSalil Mehta .rm_mc_addr = hclgevf_rm_mc_addr, 2637e2cb1decSSalil Mehta .get_stats = hclgevf_get_stats, 2638e2cb1decSSalil Mehta .update_stats = hclgevf_update_stats, 2639e2cb1decSSalil Mehta .get_strings = hclgevf_get_strings, 2640e2cb1decSSalil Mehta .get_sset_count = hclgevf_get_sset_count, 2641e2cb1decSSalil Mehta .get_rss_key_size = hclgevf_get_rss_key_size, 2642e2cb1decSSalil Mehta .get_rss_indir_size = hclgevf_get_rss_indir_size, 2643e2cb1decSSalil Mehta .get_rss = hclgevf_get_rss, 2644e2cb1decSSalil Mehta .set_rss = hclgevf_set_rss, 2645d97b3072SJian Shen .get_rss_tuple = hclgevf_get_rss_tuple, 2646d97b3072SJian Shen .set_rss_tuple = hclgevf_set_rss_tuple, 2647e2cb1decSSalil Mehta .get_tc_size = hclgevf_get_tc_size, 2648e2cb1decSSalil Mehta .get_fw_version = hclgevf_get_fw_version, 2649e2cb1decSSalil Mehta .set_vlan_filter = hclgevf_set_vlan_filter, 2650b2641e2aSYunsheng Lin .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 26516d4c3981SSalil Mehta .reset_event = hclgevf_reset_event, 2652720bd583SHuazhong Tan .set_default_reset_request = hclgevf_set_def_reset_request, 2653849e4607SPeng Li .get_channels = hclgevf_get_channels, 2654cc719218SPeng Li .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 26551600c3e5SJian Shen .get_regs_len = hclgevf_get_regs_len, 26561600c3e5SJian Shen .get_regs = hclgevf_get_regs, 2657175ec96bSFuyun Liang .get_status = hclgevf_get_status, 26584a152de9SFuyun Liang .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 2659c136b884SPeng Li .get_media_type = hclgevf_get_media_type, 26604d60291bSHuazhong Tan .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 26614d60291bSHuazhong Tan .ae_dev_resetting = hclgevf_ae_dev_resetting, 26624d60291bSHuazhong Tan .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 26635c9f6b39SPeng Li .set_gro_en = hclgevf_gro_en, 2664818f1675SYunsheng Lin .set_mtu = hclgevf_set_mtu, 26650c29d191Sliuzhongzhu .get_global_queue_id = hclgevf_get_qid_global, 2666e2cb1decSSalil Mehta }; 2667e2cb1decSSalil Mehta 2668e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf = { 2669e2cb1decSSalil Mehta .ops = &hclgevf_ops, 2670e2cb1decSSalil Mehta .pdev_id_table = ae_algovf_pci_tbl, 2671e2cb1decSSalil Mehta }; 2672e2cb1decSSalil Mehta 2673e2cb1decSSalil Mehta static int hclgevf_init(void) 2674e2cb1decSSalil Mehta { 2675e2cb1decSSalil Mehta pr_info("%s is initializing\n", HCLGEVF_NAME); 2676e2cb1decSSalil Mehta 2677854cf33aSFuyun Liang hnae3_register_ae_algo(&ae_algovf); 2678854cf33aSFuyun Liang 2679854cf33aSFuyun Liang return 0; 2680e2cb1decSSalil Mehta } 2681e2cb1decSSalil Mehta 2682e2cb1decSSalil Mehta static void hclgevf_exit(void) 2683e2cb1decSSalil Mehta { 2684e2cb1decSSalil Mehta hnae3_unregister_ae_algo(&ae_algovf); 2685e2cb1decSSalil Mehta } 2686e2cb1decSSalil Mehta module_init(hclgevf_init); 2687e2cb1decSSalil Mehta module_exit(hclgevf_exit); 2688e2cb1decSSalil Mehta 2689e2cb1decSSalil Mehta MODULE_LICENSE("GPL"); 2690e2cb1decSSalil Mehta MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 2691e2cb1decSSalil Mehta MODULE_DESCRIPTION("HCLGEVF Driver"); 2692e2cb1decSSalil Mehta MODULE_VERSION(HCLGEVF_MOD_VERSION); 2693