1e2cb1decSSalil Mehta // SPDX-License-Identifier: GPL-2.0+ 2e2cb1decSSalil Mehta // Copyright (c) 2016-2017 Hisilicon Limited. 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #include <linux/etherdevice.h> 5aa5c4f17SHuazhong Tan #include <linux/iopoll.h> 66988eb2aSSalil Mehta #include <net/rtnetlink.h> 7e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 8e2cb1decSSalil Mehta #include "hclgevf_main.h" 9e2cb1decSSalil Mehta #include "hclge_mbx.h" 10e2cb1decSSalil Mehta #include "hnae3.h" 11e2cb1decSSalil Mehta 12e2cb1decSSalil Mehta #define HCLGEVF_NAME "hclgevf" 13e2cb1decSSalil Mehta 14bbe6540eSHuazhong Tan #define HCLGEVF_RESET_MAX_FAIL_CNT 5 15bbe6540eSHuazhong Tan 169c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 17e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf; 18e2cb1decSSalil Mehta 19e2cb1decSSalil Mehta static const struct pci_device_id ae_algovf_pci_tbl[] = { 20e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 21e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 22e2cb1decSSalil Mehta /* required last entry */ 23e2cb1decSSalil Mehta {0, } 24e2cb1decSSalil Mehta }; 25e2cb1decSSalil Mehta 26472d7eceSJian Shen static const u8 hclgevf_hash_key[] = { 27472d7eceSJian Shen 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 28472d7eceSJian Shen 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 29472d7eceSJian Shen 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 30472d7eceSJian Shen 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 31472d7eceSJian Shen 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 32472d7eceSJian Shen }; 33472d7eceSJian Shen 342f550a46SYunsheng Lin MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 352f550a46SYunsheng Lin 361600c3e5SJian Shen static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 371600c3e5SJian Shen HCLGEVF_CMDQ_TX_ADDR_H_REG, 381600c3e5SJian Shen HCLGEVF_CMDQ_TX_DEPTH_REG, 391600c3e5SJian Shen HCLGEVF_CMDQ_TX_TAIL_REG, 401600c3e5SJian Shen HCLGEVF_CMDQ_TX_HEAD_REG, 411600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_L_REG, 421600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_H_REG, 431600c3e5SJian Shen HCLGEVF_CMDQ_RX_DEPTH_REG, 441600c3e5SJian Shen HCLGEVF_CMDQ_RX_TAIL_REG, 451600c3e5SJian Shen HCLGEVF_CMDQ_RX_HEAD_REG, 461600c3e5SJian Shen HCLGEVF_VECTOR0_CMDQ_SRC_REG, 471600c3e5SJian Shen HCLGEVF_CMDQ_INTR_STS_REG, 481600c3e5SJian Shen HCLGEVF_CMDQ_INTR_EN_REG, 491600c3e5SJian Shen HCLGEVF_CMDQ_INTR_GEN_REG}; 501600c3e5SJian Shen 511600c3e5SJian Shen static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 521600c3e5SJian Shen HCLGEVF_RST_ING, 531600c3e5SJian Shen HCLGEVF_GRO_EN_REG}; 541600c3e5SJian Shen 551600c3e5SJian Shen static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 561600c3e5SJian Shen HCLGEVF_RING_RX_ADDR_H_REG, 571600c3e5SJian Shen HCLGEVF_RING_RX_BD_NUM_REG, 581600c3e5SJian Shen HCLGEVF_RING_RX_BD_LENGTH_REG, 591600c3e5SJian Shen HCLGEVF_RING_RX_MERGE_EN_REG, 601600c3e5SJian Shen HCLGEVF_RING_RX_TAIL_REG, 611600c3e5SJian Shen HCLGEVF_RING_RX_HEAD_REG, 621600c3e5SJian Shen HCLGEVF_RING_RX_FBD_NUM_REG, 631600c3e5SJian Shen HCLGEVF_RING_RX_OFFSET_REG, 641600c3e5SJian Shen HCLGEVF_RING_RX_FBD_OFFSET_REG, 651600c3e5SJian Shen HCLGEVF_RING_RX_STASH_REG, 661600c3e5SJian Shen HCLGEVF_RING_RX_BD_ERR_REG, 671600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_L_REG, 681600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_H_REG, 691600c3e5SJian Shen HCLGEVF_RING_TX_BD_NUM_REG, 701600c3e5SJian Shen HCLGEVF_RING_TX_PRIORITY_REG, 711600c3e5SJian Shen HCLGEVF_RING_TX_TC_REG, 721600c3e5SJian Shen HCLGEVF_RING_TX_MERGE_EN_REG, 731600c3e5SJian Shen HCLGEVF_RING_TX_TAIL_REG, 741600c3e5SJian Shen HCLGEVF_RING_TX_HEAD_REG, 751600c3e5SJian Shen HCLGEVF_RING_TX_FBD_NUM_REG, 761600c3e5SJian Shen HCLGEVF_RING_TX_OFFSET_REG, 771600c3e5SJian Shen HCLGEVF_RING_TX_EBD_NUM_REG, 781600c3e5SJian Shen HCLGEVF_RING_TX_EBD_OFFSET_REG, 791600c3e5SJian Shen HCLGEVF_RING_TX_BD_ERR_REG, 801600c3e5SJian Shen HCLGEVF_RING_EN_REG}; 811600c3e5SJian Shen 821600c3e5SJian Shen static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 831600c3e5SJian Shen HCLGEVF_TQP_INTR_GL0_REG, 841600c3e5SJian Shen HCLGEVF_TQP_INTR_GL1_REG, 851600c3e5SJian Shen HCLGEVF_TQP_INTR_GL2_REG, 861600c3e5SJian Shen HCLGEVF_TQP_INTR_RL_REG}; 871600c3e5SJian Shen 889b2f3477SWeihang Li static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 89e2cb1decSSalil Mehta { 90eed9535fSPeng Li if (!handle->client) 91eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, nic); 92eed9535fSPeng Li else if (handle->client->type == HNAE3_CLIENT_ROCE) 93eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, roce); 94eed9535fSPeng Li else 95e2cb1decSSalil Mehta return container_of(handle, struct hclgevf_dev, nic); 96e2cb1decSSalil Mehta } 97e2cb1decSSalil Mehta 98e2cb1decSSalil Mehta static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 99e2cb1decSSalil Mehta { 100b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 101e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 102e2cb1decSSalil Mehta struct hclgevf_desc desc; 103e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 104e2cb1decSSalil Mehta int status; 105e2cb1decSSalil Mehta int i; 106e2cb1decSSalil Mehta 107b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 108b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 109e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 110e2cb1decSSalil Mehta HCLGEVF_OPC_QUERY_RX_STATUS, 111e2cb1decSSalil Mehta true); 112e2cb1decSSalil Mehta 113e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 114e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 115e2cb1decSSalil Mehta if (status) { 116e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 117e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 118e2cb1decSSalil Mehta status, i); 119e2cb1decSSalil Mehta return status; 120e2cb1decSSalil Mehta } 121e2cb1decSSalil Mehta tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 122cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 123e2cb1decSSalil Mehta 124e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 125e2cb1decSSalil Mehta true); 126e2cb1decSSalil Mehta 127e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 128e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 129e2cb1decSSalil Mehta if (status) { 130e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 131e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 132e2cb1decSSalil Mehta status, i); 133e2cb1decSSalil Mehta return status; 134e2cb1decSSalil Mehta } 135e2cb1decSSalil Mehta tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 136cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 137e2cb1decSSalil Mehta } 138e2cb1decSSalil Mehta 139e2cb1decSSalil Mehta return 0; 140e2cb1decSSalil Mehta } 141e2cb1decSSalil Mehta 142e2cb1decSSalil Mehta static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 143e2cb1decSSalil Mehta { 144e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo = &handle->kinfo; 145e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 146e2cb1decSSalil Mehta u64 *buff = data; 147e2cb1decSSalil Mehta int i; 148e2cb1decSSalil Mehta 149b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 150b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 151e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 152e2cb1decSSalil Mehta } 153e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 154b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 155e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 156e2cb1decSSalil Mehta } 157e2cb1decSSalil Mehta 158e2cb1decSSalil Mehta return buff; 159e2cb1decSSalil Mehta } 160e2cb1decSSalil Mehta 161e2cb1decSSalil Mehta static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 162e2cb1decSSalil Mehta { 163b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 164e2cb1decSSalil Mehta 165b4f1d303SJian Shen return kinfo->num_tqps * 2; 166e2cb1decSSalil Mehta } 167e2cb1decSSalil Mehta 168e2cb1decSSalil Mehta static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 169e2cb1decSSalil Mehta { 170b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 171e2cb1decSSalil Mehta u8 *buff = data; 172e2cb1decSSalil Mehta int i = 0; 173e2cb1decSSalil Mehta 174b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 175b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 176e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1770c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 178e2cb1decSSalil Mehta tqp->index); 179e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 180e2cb1decSSalil Mehta } 181e2cb1decSSalil Mehta 182b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 183b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 184e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1850c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 186e2cb1decSSalil Mehta tqp->index); 187e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 188e2cb1decSSalil Mehta } 189e2cb1decSSalil Mehta 190e2cb1decSSalil Mehta return buff; 191e2cb1decSSalil Mehta } 192e2cb1decSSalil Mehta 193e2cb1decSSalil Mehta static void hclgevf_update_stats(struct hnae3_handle *handle, 194e2cb1decSSalil Mehta struct net_device_stats *net_stats) 195e2cb1decSSalil Mehta { 196e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 197e2cb1decSSalil Mehta int status; 198e2cb1decSSalil Mehta 199e2cb1decSSalil Mehta status = hclgevf_tqps_update_stats(handle); 200e2cb1decSSalil Mehta if (status) 201e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 202e2cb1decSSalil Mehta "VF update of TQPS stats fail, status = %d.\n", 203e2cb1decSSalil Mehta status); 204e2cb1decSSalil Mehta } 205e2cb1decSSalil Mehta 206e2cb1decSSalil Mehta static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 207e2cb1decSSalil Mehta { 208e2cb1decSSalil Mehta if (strset == ETH_SS_TEST) 209e2cb1decSSalil Mehta return -EOPNOTSUPP; 210e2cb1decSSalil Mehta else if (strset == ETH_SS_STATS) 211e2cb1decSSalil Mehta return hclgevf_tqps_get_sset_count(handle, strset); 212e2cb1decSSalil Mehta 213e2cb1decSSalil Mehta return 0; 214e2cb1decSSalil Mehta } 215e2cb1decSSalil Mehta 216e2cb1decSSalil Mehta static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 217e2cb1decSSalil Mehta u8 *data) 218e2cb1decSSalil Mehta { 219e2cb1decSSalil Mehta u8 *p = (char *)data; 220e2cb1decSSalil Mehta 221e2cb1decSSalil Mehta if (strset == ETH_SS_STATS) 222e2cb1decSSalil Mehta p = hclgevf_tqps_get_strings(handle, p); 223e2cb1decSSalil Mehta } 224e2cb1decSSalil Mehta 225e2cb1decSSalil Mehta static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 226e2cb1decSSalil Mehta { 227e2cb1decSSalil Mehta hclgevf_tqps_get_stats(handle, data); 228e2cb1decSSalil Mehta } 229e2cb1decSSalil Mehta 230e2cb1decSSalil Mehta static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 231e2cb1decSSalil Mehta { 232e2cb1decSSalil Mehta u8 resp_msg; 233e2cb1decSSalil Mehta int status; 234e2cb1decSSalil Mehta 235e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 23663cbf7a9SYufeng Mo true, &resp_msg, sizeof(resp_msg)); 237e2cb1decSSalil Mehta if (status) { 238e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 239e2cb1decSSalil Mehta "VF request to get TC info from PF failed %d", 240e2cb1decSSalil Mehta status); 241e2cb1decSSalil Mehta return status; 242e2cb1decSSalil Mehta } 243e2cb1decSSalil Mehta 244e2cb1decSSalil Mehta hdev->hw_tc_map = resp_msg; 245e2cb1decSSalil Mehta 246e2cb1decSSalil Mehta return 0; 247e2cb1decSSalil Mehta } 248e2cb1decSSalil Mehta 24992f11ea1SJian Shen static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 25092f11ea1SJian Shen { 25192f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 25292f11ea1SJian Shen u8 resp_msg; 25392f11ea1SJian Shen int ret; 25492f11ea1SJian Shen 25592f11ea1SJian Shen ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 25692f11ea1SJian Shen HCLGE_MBX_GET_PORT_BASE_VLAN_STATE, 25792f11ea1SJian Shen NULL, 0, true, &resp_msg, sizeof(u8)); 25892f11ea1SJian Shen if (ret) { 25992f11ea1SJian Shen dev_err(&hdev->pdev->dev, 26092f11ea1SJian Shen "VF request to get port based vlan state failed %d", 26192f11ea1SJian Shen ret); 26292f11ea1SJian Shen return ret; 26392f11ea1SJian Shen } 26492f11ea1SJian Shen 26592f11ea1SJian Shen nic->port_base_vlan_state = resp_msg; 26692f11ea1SJian Shen 26792f11ea1SJian Shen return 0; 26892f11ea1SJian Shen } 26992f11ea1SJian Shen 2706cee6fc3SJian Shen static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 271e2cb1decSSalil Mehta { 272c0425944SPeng Li #define HCLGEVF_TQPS_RSS_INFO_LEN 6 273e2cb1decSSalil Mehta u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 274e2cb1decSSalil Mehta int status; 275e2cb1decSSalil Mehta 276e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 277e2cb1decSSalil Mehta true, resp_msg, 278e2cb1decSSalil Mehta HCLGEVF_TQPS_RSS_INFO_LEN); 279e2cb1decSSalil Mehta if (status) { 280e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 281e2cb1decSSalil Mehta "VF request to get tqp info from PF failed %d", 282e2cb1decSSalil Mehta status); 283e2cb1decSSalil Mehta return status; 284e2cb1decSSalil Mehta } 285e2cb1decSSalil Mehta 286e2cb1decSSalil Mehta memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 287e2cb1decSSalil Mehta memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 288c0425944SPeng Li memcpy(&hdev->rx_buf_len, &resp_msg[4], sizeof(u16)); 289c0425944SPeng Li 290c0425944SPeng Li return 0; 291c0425944SPeng Li } 292c0425944SPeng Li 293c0425944SPeng Li static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 294c0425944SPeng Li { 295c0425944SPeng Li #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 296c0425944SPeng Li u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 297c0425944SPeng Li int ret; 298c0425944SPeng Li 299c0425944SPeng Li ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QDEPTH, 0, NULL, 0, 300c0425944SPeng Li true, resp_msg, 301c0425944SPeng Li HCLGEVF_TQPS_DEPTH_INFO_LEN); 302c0425944SPeng Li if (ret) { 303c0425944SPeng Li dev_err(&hdev->pdev->dev, 304c0425944SPeng Li "VF request to get tqp depth info from PF failed %d", 305c0425944SPeng Li ret); 306c0425944SPeng Li return ret; 307c0425944SPeng Li } 308c0425944SPeng Li 309c0425944SPeng Li memcpy(&hdev->num_tx_desc, &resp_msg[0], sizeof(u16)); 310c0425944SPeng Li memcpy(&hdev->num_rx_desc, &resp_msg[2], sizeof(u16)); 311e2cb1decSSalil Mehta 312e2cb1decSSalil Mehta return 0; 313e2cb1decSSalil Mehta } 314e2cb1decSSalil Mehta 3150c29d191Sliuzhongzhu static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 3160c29d191Sliuzhongzhu { 3170c29d191Sliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3180c29d191Sliuzhongzhu u8 msg_data[2], resp_data[2]; 3190c29d191Sliuzhongzhu u16 qid_in_pf = 0; 3200c29d191Sliuzhongzhu int ret; 3210c29d191Sliuzhongzhu 3220c29d191Sliuzhongzhu memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 3230c29d191Sliuzhongzhu 3240c29d191Sliuzhongzhu ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data, 32563cbf7a9SYufeng Mo sizeof(msg_data), true, resp_data, 32663cbf7a9SYufeng Mo sizeof(resp_data)); 3270c29d191Sliuzhongzhu if (!ret) 3280c29d191Sliuzhongzhu qid_in_pf = *(u16 *)resp_data; 3290c29d191Sliuzhongzhu 3300c29d191Sliuzhongzhu return qid_in_pf; 3310c29d191Sliuzhongzhu } 3320c29d191Sliuzhongzhu 3339c3e7130Sliuzhongzhu static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 3349c3e7130Sliuzhongzhu { 33588d10bd6SJian Shen u8 resp_msg[2]; 3369c3e7130Sliuzhongzhu int ret; 3379c3e7130Sliuzhongzhu 3389c3e7130Sliuzhongzhu ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_MEDIA_TYPE, 0, NULL, 0, 33988d10bd6SJian Shen true, resp_msg, sizeof(resp_msg)); 3409c3e7130Sliuzhongzhu if (ret) { 3419c3e7130Sliuzhongzhu dev_err(&hdev->pdev->dev, 3429c3e7130Sliuzhongzhu "VF request to get the pf port media type failed %d", 3439c3e7130Sliuzhongzhu ret); 3449c3e7130Sliuzhongzhu return ret; 3459c3e7130Sliuzhongzhu } 3469c3e7130Sliuzhongzhu 34788d10bd6SJian Shen hdev->hw.mac.media_type = resp_msg[0]; 34888d10bd6SJian Shen hdev->hw.mac.module_type = resp_msg[1]; 3499c3e7130Sliuzhongzhu 3509c3e7130Sliuzhongzhu return 0; 3519c3e7130Sliuzhongzhu } 3529c3e7130Sliuzhongzhu 353e2cb1decSSalil Mehta static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 354e2cb1decSSalil Mehta { 355e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 356e2cb1decSSalil Mehta int i; 357e2cb1decSSalil Mehta 358e2cb1decSSalil Mehta hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 359e2cb1decSSalil Mehta sizeof(struct hclgevf_tqp), GFP_KERNEL); 360e2cb1decSSalil Mehta if (!hdev->htqp) 361e2cb1decSSalil Mehta return -ENOMEM; 362e2cb1decSSalil Mehta 363e2cb1decSSalil Mehta tqp = hdev->htqp; 364e2cb1decSSalil Mehta 365e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 366e2cb1decSSalil Mehta tqp->dev = &hdev->pdev->dev; 367e2cb1decSSalil Mehta tqp->index = i; 368e2cb1decSSalil Mehta 369e2cb1decSSalil Mehta tqp->q.ae_algo = &ae_algovf; 370e2cb1decSSalil Mehta tqp->q.buf_size = hdev->rx_buf_len; 371c0425944SPeng Li tqp->q.tx_desc_num = hdev->num_tx_desc; 372c0425944SPeng Li tqp->q.rx_desc_num = hdev->num_rx_desc; 373e2cb1decSSalil Mehta tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 374e2cb1decSSalil Mehta i * HCLGEVF_TQP_REG_SIZE; 375e2cb1decSSalil Mehta 376e2cb1decSSalil Mehta tqp++; 377e2cb1decSSalil Mehta } 378e2cb1decSSalil Mehta 379e2cb1decSSalil Mehta return 0; 380e2cb1decSSalil Mehta } 381e2cb1decSSalil Mehta 382e2cb1decSSalil Mehta static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 383e2cb1decSSalil Mehta { 384e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 385e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo; 386e2cb1decSSalil Mehta u16 new_tqps = hdev->num_tqps; 387ebaf1908SWeihang Li unsigned int i; 388e2cb1decSSalil Mehta 389e2cb1decSSalil Mehta kinfo = &nic->kinfo; 390e2cb1decSSalil Mehta kinfo->num_tc = 0; 391c0425944SPeng Li kinfo->num_tx_desc = hdev->num_tx_desc; 392c0425944SPeng Li kinfo->num_rx_desc = hdev->num_rx_desc; 393e2cb1decSSalil Mehta kinfo->rx_buf_len = hdev->rx_buf_len; 394e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 395e2cb1decSSalil Mehta if (hdev->hw_tc_map & BIT(i)) 396e2cb1decSSalil Mehta kinfo->num_tc++; 397e2cb1decSSalil Mehta 398e2cb1decSSalil Mehta kinfo->rss_size 399e2cb1decSSalil Mehta = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 400e2cb1decSSalil Mehta new_tqps = kinfo->rss_size * kinfo->num_tc; 401e2cb1decSSalil Mehta kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 402e2cb1decSSalil Mehta 403e2cb1decSSalil Mehta kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 404e2cb1decSSalil Mehta sizeof(struct hnae3_queue *), GFP_KERNEL); 405e2cb1decSSalil Mehta if (!kinfo->tqp) 406e2cb1decSSalil Mehta return -ENOMEM; 407e2cb1decSSalil Mehta 408e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 409e2cb1decSSalil Mehta hdev->htqp[i].q.handle = &hdev->nic; 410e2cb1decSSalil Mehta hdev->htqp[i].q.tqp_index = i; 411e2cb1decSSalil Mehta kinfo->tqp[i] = &hdev->htqp[i].q; 412e2cb1decSSalil Mehta } 413e2cb1decSSalil Mehta 414580a05f9SYonglong Liu /* after init the max rss_size and tqps, adjust the default tqp numbers 415580a05f9SYonglong Liu * and rss size with the actual vector numbers 416580a05f9SYonglong Liu */ 417580a05f9SYonglong Liu kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps); 418580a05f9SYonglong Liu kinfo->rss_size = min_t(u16, kinfo->num_tqps / kinfo->num_tc, 419580a05f9SYonglong Liu kinfo->rss_size); 420580a05f9SYonglong Liu 421e2cb1decSSalil Mehta return 0; 422e2cb1decSSalil Mehta } 423e2cb1decSSalil Mehta 424e2cb1decSSalil Mehta static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 425e2cb1decSSalil Mehta { 426e2cb1decSSalil Mehta int status; 427e2cb1decSSalil Mehta u8 resp_msg; 428e2cb1decSSalil Mehta 429e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 43063cbf7a9SYufeng Mo 0, false, &resp_msg, sizeof(resp_msg)); 431e2cb1decSSalil Mehta if (status) 432e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 433e2cb1decSSalil Mehta "VF failed to fetch link status(%d) from PF", status); 434e2cb1decSSalil Mehta } 435e2cb1decSSalil Mehta 436e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 437e2cb1decSSalil Mehta { 43845e92b7eSPeng Li struct hnae3_handle *rhandle = &hdev->roce; 439e2cb1decSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 44045e92b7eSPeng Li struct hnae3_client *rclient; 441e2cb1decSSalil Mehta struct hnae3_client *client; 442e2cb1decSSalil Mehta 443e2cb1decSSalil Mehta client = handle->client; 44445e92b7eSPeng Li rclient = hdev->roce_client; 445e2cb1decSSalil Mehta 446582d37bbSPeng Li link_state = 447582d37bbSPeng Li test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 448582d37bbSPeng Li 449e2cb1decSSalil Mehta if (link_state != hdev->hw.mac.link) { 450e2cb1decSSalil Mehta client->ops->link_status_change(handle, !!link_state); 45145e92b7eSPeng Li if (rclient && rclient->ops->link_status_change) 45245e92b7eSPeng Li rclient->ops->link_status_change(rhandle, !!link_state); 453e2cb1decSSalil Mehta hdev->hw.mac.link = link_state; 454e2cb1decSSalil Mehta } 455e2cb1decSSalil Mehta } 456e2cb1decSSalil Mehta 457538abaf3SYueHaibing static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 4589194d18bSliuzhongzhu { 4599194d18bSliuzhongzhu #define HCLGEVF_ADVERTISING 0 4609194d18bSliuzhongzhu #define HCLGEVF_SUPPORTED 1 4619194d18bSliuzhongzhu u8 send_msg; 4629194d18bSliuzhongzhu u8 resp_msg; 4639194d18bSliuzhongzhu 4649194d18bSliuzhongzhu send_msg = HCLGEVF_ADVERTISING; 46563cbf7a9SYufeng Mo hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 46663cbf7a9SYufeng Mo &send_msg, sizeof(send_msg), false, 46763cbf7a9SYufeng Mo &resp_msg, sizeof(resp_msg)); 4689194d18bSliuzhongzhu send_msg = HCLGEVF_SUPPORTED; 46963cbf7a9SYufeng Mo hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 47063cbf7a9SYufeng Mo &send_msg, sizeof(send_msg), false, 47163cbf7a9SYufeng Mo &resp_msg, sizeof(resp_msg)); 4729194d18bSliuzhongzhu } 4739194d18bSliuzhongzhu 474e2cb1decSSalil Mehta static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 475e2cb1decSSalil Mehta { 476e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 477e2cb1decSSalil Mehta int ret; 478e2cb1decSSalil Mehta 479e2cb1decSSalil Mehta nic->ae_algo = &ae_algovf; 480e2cb1decSSalil Mehta nic->pdev = hdev->pdev; 481e2cb1decSSalil Mehta nic->numa_node_mask = hdev->numa_node_mask; 482424eb834SSalil Mehta nic->flags |= HNAE3_SUPPORT_VF; 483e2cb1decSSalil Mehta 484e2cb1decSSalil Mehta ret = hclgevf_knic_setup(hdev); 485e2cb1decSSalil Mehta if (ret) 486e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 487e2cb1decSSalil Mehta ret); 488e2cb1decSSalil Mehta return ret; 489e2cb1decSSalil Mehta } 490e2cb1decSSalil Mehta 491e2cb1decSSalil Mehta static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 492e2cb1decSSalil Mehta { 49336cbbdf6SPeng Li if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 49436cbbdf6SPeng Li dev_warn(&hdev->pdev->dev, 49536cbbdf6SPeng Li "vector(vector_id %d) has been freed.\n", vector_id); 49636cbbdf6SPeng Li return; 49736cbbdf6SPeng Li } 49836cbbdf6SPeng Li 499e2cb1decSSalil Mehta hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 500e2cb1decSSalil Mehta hdev->num_msi_left += 1; 501e2cb1decSSalil Mehta hdev->num_msi_used -= 1; 502e2cb1decSSalil Mehta } 503e2cb1decSSalil Mehta 504e2cb1decSSalil Mehta static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 505e2cb1decSSalil Mehta struct hnae3_vector_info *vector_info) 506e2cb1decSSalil Mehta { 507e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 508e2cb1decSSalil Mehta struct hnae3_vector_info *vector = vector_info; 509e2cb1decSSalil Mehta int alloc = 0; 510e2cb1decSSalil Mehta int i, j; 511e2cb1decSSalil Mehta 512580a05f9SYonglong Liu vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num); 513e2cb1decSSalil Mehta vector_num = min(hdev->num_msi_left, vector_num); 514e2cb1decSSalil Mehta 515e2cb1decSSalil Mehta for (j = 0; j < vector_num; j++) { 516e2cb1decSSalil Mehta for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 517e2cb1decSSalil Mehta if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 518e2cb1decSSalil Mehta vector->vector = pci_irq_vector(hdev->pdev, i); 519e2cb1decSSalil Mehta vector->io_addr = hdev->hw.io_base + 520e2cb1decSSalil Mehta HCLGEVF_VECTOR_REG_BASE + 521e2cb1decSSalil Mehta (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 522e2cb1decSSalil Mehta hdev->vector_status[i] = 0; 523e2cb1decSSalil Mehta hdev->vector_irq[i] = vector->vector; 524e2cb1decSSalil Mehta 525e2cb1decSSalil Mehta vector++; 526e2cb1decSSalil Mehta alloc++; 527e2cb1decSSalil Mehta 528e2cb1decSSalil Mehta break; 529e2cb1decSSalil Mehta } 530e2cb1decSSalil Mehta } 531e2cb1decSSalil Mehta } 532e2cb1decSSalil Mehta hdev->num_msi_left -= alloc; 533e2cb1decSSalil Mehta hdev->num_msi_used += alloc; 534e2cb1decSSalil Mehta 535e2cb1decSSalil Mehta return alloc; 536e2cb1decSSalil Mehta } 537e2cb1decSSalil Mehta 538e2cb1decSSalil Mehta static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 539e2cb1decSSalil Mehta { 540e2cb1decSSalil Mehta int i; 541e2cb1decSSalil Mehta 542e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 543e2cb1decSSalil Mehta if (vector == hdev->vector_irq[i]) 544e2cb1decSSalil Mehta return i; 545e2cb1decSSalil Mehta 546e2cb1decSSalil Mehta return -EINVAL; 547e2cb1decSSalil Mehta } 548e2cb1decSSalil Mehta 549374ad291SJian Shen static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 550374ad291SJian Shen const u8 hfunc, const u8 *key) 551374ad291SJian Shen { 552374ad291SJian Shen struct hclgevf_rss_config_cmd *req; 553ebaf1908SWeihang Li unsigned int key_offset = 0; 554374ad291SJian Shen struct hclgevf_desc desc; 5553caf772bSYufeng Mo int key_counts; 556374ad291SJian Shen int key_size; 557374ad291SJian Shen int ret; 558374ad291SJian Shen 5593caf772bSYufeng Mo key_counts = HCLGEVF_RSS_KEY_SIZE; 560374ad291SJian Shen req = (struct hclgevf_rss_config_cmd *)desc.data; 561374ad291SJian Shen 5623caf772bSYufeng Mo while (key_counts) { 563374ad291SJian Shen hclgevf_cmd_setup_basic_desc(&desc, 564374ad291SJian Shen HCLGEVF_OPC_RSS_GENERIC_CONFIG, 565374ad291SJian Shen false); 566374ad291SJian Shen 567374ad291SJian Shen req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 568374ad291SJian Shen req->hash_config |= 569374ad291SJian Shen (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 570374ad291SJian Shen 5713caf772bSYufeng Mo key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts); 572374ad291SJian Shen memcpy(req->hash_key, 573374ad291SJian Shen key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 574374ad291SJian Shen 5753caf772bSYufeng Mo key_counts -= key_size; 5763caf772bSYufeng Mo key_offset++; 577374ad291SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 578374ad291SJian Shen if (ret) { 579374ad291SJian Shen dev_err(&hdev->pdev->dev, 580374ad291SJian Shen "Configure RSS config fail, status = %d\n", 581374ad291SJian Shen ret); 582374ad291SJian Shen return ret; 583374ad291SJian Shen } 584374ad291SJian Shen } 585374ad291SJian Shen 586374ad291SJian Shen return 0; 587374ad291SJian Shen } 588374ad291SJian Shen 589e2cb1decSSalil Mehta static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 590e2cb1decSSalil Mehta { 591e2cb1decSSalil Mehta return HCLGEVF_RSS_KEY_SIZE; 592e2cb1decSSalil Mehta } 593e2cb1decSSalil Mehta 594e2cb1decSSalil Mehta static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 595e2cb1decSSalil Mehta { 596e2cb1decSSalil Mehta return HCLGEVF_RSS_IND_TBL_SIZE; 597e2cb1decSSalil Mehta } 598e2cb1decSSalil Mehta 599e2cb1decSSalil Mehta static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 600e2cb1decSSalil Mehta { 601e2cb1decSSalil Mehta const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 602e2cb1decSSalil Mehta struct hclgevf_rss_indirection_table_cmd *req; 603e2cb1decSSalil Mehta struct hclgevf_desc desc; 604e2cb1decSSalil Mehta int status; 605e2cb1decSSalil Mehta int i, j; 606e2cb1decSSalil Mehta 607e2cb1decSSalil Mehta req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 608e2cb1decSSalil Mehta 609e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 610e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 611e2cb1decSSalil Mehta false); 612e2cb1decSSalil Mehta req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 613e2cb1decSSalil Mehta req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 614e2cb1decSSalil Mehta for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 615e2cb1decSSalil Mehta req->rss_result[j] = 616e2cb1decSSalil Mehta indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 617e2cb1decSSalil Mehta 618e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 619e2cb1decSSalil Mehta if (status) { 620e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 621e2cb1decSSalil Mehta "VF failed(=%d) to set RSS indirection table\n", 622e2cb1decSSalil Mehta status); 623e2cb1decSSalil Mehta return status; 624e2cb1decSSalil Mehta } 625e2cb1decSSalil Mehta } 626e2cb1decSSalil Mehta 627e2cb1decSSalil Mehta return 0; 628e2cb1decSSalil Mehta } 629e2cb1decSSalil Mehta 630e2cb1decSSalil Mehta static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 631e2cb1decSSalil Mehta { 632e2cb1decSSalil Mehta struct hclgevf_rss_tc_mode_cmd *req; 633e2cb1decSSalil Mehta u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 634e2cb1decSSalil Mehta u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 635e2cb1decSSalil Mehta u16 tc_size[HCLGEVF_MAX_TC_NUM]; 636e2cb1decSSalil Mehta struct hclgevf_desc desc; 637e2cb1decSSalil Mehta u16 roundup_size; 638e2cb1decSSalil Mehta int status; 639ebaf1908SWeihang Li unsigned int i; 640e2cb1decSSalil Mehta 641e2cb1decSSalil Mehta req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 642e2cb1decSSalil Mehta 643e2cb1decSSalil Mehta roundup_size = roundup_pow_of_two(rss_size); 644e2cb1decSSalil Mehta roundup_size = ilog2(roundup_size); 645e2cb1decSSalil Mehta 646e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 647e2cb1decSSalil Mehta tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 648e2cb1decSSalil Mehta tc_size[i] = roundup_size; 649e2cb1decSSalil Mehta tc_offset[i] = rss_size * i; 650e2cb1decSSalil Mehta } 651e2cb1decSSalil Mehta 652e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 653e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 654e4e87715SPeng Li hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 655e2cb1decSSalil Mehta (tc_valid[i] & 0x1)); 656e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 657e2cb1decSSalil Mehta HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 658e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 659e2cb1decSSalil Mehta HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 660e2cb1decSSalil Mehta } 661e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 662e2cb1decSSalil Mehta if (status) 663e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 664e2cb1decSSalil Mehta "VF failed(=%d) to set rss tc mode\n", status); 665e2cb1decSSalil Mehta 666e2cb1decSSalil Mehta return status; 667e2cb1decSSalil Mehta } 668e2cb1decSSalil Mehta 669a638b1d8SJian Shen /* for revision 0x20, vf shared the same rss config with pf */ 670a638b1d8SJian Shen static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 671a638b1d8SJian Shen { 672a638b1d8SJian Shen #define HCLGEVF_RSS_MBX_RESP_LEN 8 673a638b1d8SJian Shen 674a638b1d8SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 675a638b1d8SJian Shen u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 676a638b1d8SJian Shen u16 msg_num, hash_key_index; 677a638b1d8SJian Shen u8 index; 678a638b1d8SJian Shen int ret; 679a638b1d8SJian Shen 680a638b1d8SJian Shen msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 681a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN; 682a638b1d8SJian Shen for (index = 0; index < msg_num; index++) { 683a638b1d8SJian Shen ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_RSS_KEY, 0, 684a638b1d8SJian Shen &index, sizeof(index), 685a638b1d8SJian Shen true, resp_msg, 686a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN); 687a638b1d8SJian Shen if (ret) { 688a638b1d8SJian Shen dev_err(&hdev->pdev->dev, 689a638b1d8SJian Shen "VF get rss hash key from PF failed, ret=%d", 690a638b1d8SJian Shen ret); 691a638b1d8SJian Shen return ret; 692a638b1d8SJian Shen } 693a638b1d8SJian Shen 694a638b1d8SJian Shen hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 695a638b1d8SJian Shen if (index == msg_num - 1) 696a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 697a638b1d8SJian Shen &resp_msg[0], 698a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE - hash_key_index); 699a638b1d8SJian Shen else 700a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 701a638b1d8SJian Shen &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 702a638b1d8SJian Shen } 703a638b1d8SJian Shen 704a638b1d8SJian Shen return 0; 705a638b1d8SJian Shen } 706a638b1d8SJian Shen 707e2cb1decSSalil Mehta static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 708e2cb1decSSalil Mehta u8 *hfunc) 709e2cb1decSSalil Mehta { 710e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 711e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 712a638b1d8SJian Shen int i, ret; 713e2cb1decSSalil Mehta 714374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 715374ad291SJian Shen /* Get hash algorithm */ 716374ad291SJian Shen if (hfunc) { 717374ad291SJian Shen switch (rss_cfg->hash_algo) { 718374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 719374ad291SJian Shen *hfunc = ETH_RSS_HASH_TOP; 720374ad291SJian Shen break; 721374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 722374ad291SJian Shen *hfunc = ETH_RSS_HASH_XOR; 723374ad291SJian Shen break; 724374ad291SJian Shen default: 725374ad291SJian Shen *hfunc = ETH_RSS_HASH_UNKNOWN; 726374ad291SJian Shen break; 727374ad291SJian Shen } 728374ad291SJian Shen } 729374ad291SJian Shen 730374ad291SJian Shen /* Get the RSS Key required by the user */ 731374ad291SJian Shen if (key) 732374ad291SJian Shen memcpy(key, rss_cfg->rss_hash_key, 733374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 734a638b1d8SJian Shen } else { 735a638b1d8SJian Shen if (hfunc) 736a638b1d8SJian Shen *hfunc = ETH_RSS_HASH_TOP; 737a638b1d8SJian Shen if (key) { 738a638b1d8SJian Shen ret = hclgevf_get_rss_hash_key(hdev); 739a638b1d8SJian Shen if (ret) 740a638b1d8SJian Shen return ret; 741a638b1d8SJian Shen memcpy(key, rss_cfg->rss_hash_key, 742a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE); 743a638b1d8SJian Shen } 744374ad291SJian Shen } 745374ad291SJian Shen 746e2cb1decSSalil Mehta if (indir) 747e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 748e2cb1decSSalil Mehta indir[i] = rss_cfg->rss_indirection_tbl[i]; 749e2cb1decSSalil Mehta 750374ad291SJian Shen return 0; 751e2cb1decSSalil Mehta } 752e2cb1decSSalil Mehta 753e2cb1decSSalil Mehta static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 754e2cb1decSSalil Mehta const u8 *key, const u8 hfunc) 755e2cb1decSSalil Mehta { 756e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 757e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 758374ad291SJian Shen int ret, i; 759374ad291SJian Shen 760374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 761374ad291SJian Shen /* Set the RSS Hash Key if specififed by the user */ 762374ad291SJian Shen if (key) { 763374ad291SJian Shen switch (hfunc) { 764374ad291SJian Shen case ETH_RSS_HASH_TOP: 765374ad291SJian Shen rss_cfg->hash_algo = 766374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 767374ad291SJian Shen break; 768374ad291SJian Shen case ETH_RSS_HASH_XOR: 769374ad291SJian Shen rss_cfg->hash_algo = 770374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_SIMPLE; 771374ad291SJian Shen break; 772374ad291SJian Shen case ETH_RSS_HASH_NO_CHANGE: 773374ad291SJian Shen break; 774374ad291SJian Shen default: 775374ad291SJian Shen return -EINVAL; 776374ad291SJian Shen } 777374ad291SJian Shen 778374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 779374ad291SJian Shen key); 780374ad291SJian Shen if (ret) 781374ad291SJian Shen return ret; 782374ad291SJian Shen 783374ad291SJian Shen /* Update the shadow RSS key with user specified qids */ 784374ad291SJian Shen memcpy(rss_cfg->rss_hash_key, key, 785374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 786374ad291SJian Shen } 787374ad291SJian Shen } 788e2cb1decSSalil Mehta 789e2cb1decSSalil Mehta /* update the shadow RSS table with user specified qids */ 790e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 791e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = indir[i]; 792e2cb1decSSalil Mehta 793e2cb1decSSalil Mehta /* update the hardware */ 794e2cb1decSSalil Mehta return hclgevf_set_rss_indir_table(hdev); 795e2cb1decSSalil Mehta } 796e2cb1decSSalil Mehta 797d97b3072SJian Shen static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 798d97b3072SJian Shen { 799d97b3072SJian Shen u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 800d97b3072SJian Shen 801d97b3072SJian Shen if (nfc->data & RXH_L4_B_2_3) 802d97b3072SJian Shen hash_sets |= HCLGEVF_D_PORT_BIT; 803d97b3072SJian Shen else 804d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_PORT_BIT; 805d97b3072SJian Shen 806d97b3072SJian Shen if (nfc->data & RXH_IP_SRC) 807d97b3072SJian Shen hash_sets |= HCLGEVF_S_IP_BIT; 808d97b3072SJian Shen else 809d97b3072SJian Shen hash_sets &= ~HCLGEVF_S_IP_BIT; 810d97b3072SJian Shen 811d97b3072SJian Shen if (nfc->data & RXH_IP_DST) 812d97b3072SJian Shen hash_sets |= HCLGEVF_D_IP_BIT; 813d97b3072SJian Shen else 814d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_IP_BIT; 815d97b3072SJian Shen 816d97b3072SJian Shen if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 817d97b3072SJian Shen hash_sets |= HCLGEVF_V_TAG_BIT; 818d97b3072SJian Shen 819d97b3072SJian Shen return hash_sets; 820d97b3072SJian Shen } 821d97b3072SJian Shen 822d97b3072SJian Shen static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 823d97b3072SJian Shen struct ethtool_rxnfc *nfc) 824d97b3072SJian Shen { 825d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 826d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 827d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 828d97b3072SJian Shen struct hclgevf_desc desc; 829d97b3072SJian Shen u8 tuple_sets; 830d97b3072SJian Shen int ret; 831d97b3072SJian Shen 832d97b3072SJian Shen if (handle->pdev->revision == 0x20) 833d97b3072SJian Shen return -EOPNOTSUPP; 834d97b3072SJian Shen 835d97b3072SJian Shen if (nfc->data & 836d97b3072SJian Shen ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 837d97b3072SJian Shen return -EINVAL; 838d97b3072SJian Shen 839d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 840d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 841d97b3072SJian Shen 842d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 843d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 844d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 845d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 846d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 847d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 848d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 849d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 850d97b3072SJian Shen 851d97b3072SJian Shen tuple_sets = hclgevf_get_rss_hash_bits(nfc); 852d97b3072SJian Shen switch (nfc->flow_type) { 853d97b3072SJian Shen case TCP_V4_FLOW: 854d97b3072SJian Shen req->ipv4_tcp_en = tuple_sets; 855d97b3072SJian Shen break; 856d97b3072SJian Shen case TCP_V6_FLOW: 857d97b3072SJian Shen req->ipv6_tcp_en = tuple_sets; 858d97b3072SJian Shen break; 859d97b3072SJian Shen case UDP_V4_FLOW: 860d97b3072SJian Shen req->ipv4_udp_en = tuple_sets; 861d97b3072SJian Shen break; 862d97b3072SJian Shen case UDP_V6_FLOW: 863d97b3072SJian Shen req->ipv6_udp_en = tuple_sets; 864d97b3072SJian Shen break; 865d97b3072SJian Shen case SCTP_V4_FLOW: 866d97b3072SJian Shen req->ipv4_sctp_en = tuple_sets; 867d97b3072SJian Shen break; 868d97b3072SJian Shen case SCTP_V6_FLOW: 869d97b3072SJian Shen if ((nfc->data & RXH_L4_B_0_1) || 870d97b3072SJian Shen (nfc->data & RXH_L4_B_2_3)) 871d97b3072SJian Shen return -EINVAL; 872d97b3072SJian Shen 873d97b3072SJian Shen req->ipv6_sctp_en = tuple_sets; 874d97b3072SJian Shen break; 875d97b3072SJian Shen case IPV4_FLOW: 876d97b3072SJian Shen req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 877d97b3072SJian Shen break; 878d97b3072SJian Shen case IPV6_FLOW: 879d97b3072SJian Shen req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 880d97b3072SJian Shen break; 881d97b3072SJian Shen default: 882d97b3072SJian Shen return -EINVAL; 883d97b3072SJian Shen } 884d97b3072SJian Shen 885d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 886d97b3072SJian Shen if (ret) { 887d97b3072SJian Shen dev_err(&hdev->pdev->dev, 888d97b3072SJian Shen "Set rss tuple fail, status = %d\n", ret); 889d97b3072SJian Shen return ret; 890d97b3072SJian Shen } 891d97b3072SJian Shen 892d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 893d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 894d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 895d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 896d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 897d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 898d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 899d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 900d97b3072SJian Shen return 0; 901d97b3072SJian Shen } 902d97b3072SJian Shen 903d97b3072SJian Shen static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 904d97b3072SJian Shen struct ethtool_rxnfc *nfc) 905d97b3072SJian Shen { 906d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 907d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 908d97b3072SJian Shen u8 tuple_sets; 909d97b3072SJian Shen 910d97b3072SJian Shen if (handle->pdev->revision == 0x20) 911d97b3072SJian Shen return -EOPNOTSUPP; 912d97b3072SJian Shen 913d97b3072SJian Shen nfc->data = 0; 914d97b3072SJian Shen 915d97b3072SJian Shen switch (nfc->flow_type) { 916d97b3072SJian Shen case TCP_V4_FLOW: 917d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 918d97b3072SJian Shen break; 919d97b3072SJian Shen case UDP_V4_FLOW: 920d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 921d97b3072SJian Shen break; 922d97b3072SJian Shen case TCP_V6_FLOW: 923d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 924d97b3072SJian Shen break; 925d97b3072SJian Shen case UDP_V6_FLOW: 926d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 927d97b3072SJian Shen break; 928d97b3072SJian Shen case SCTP_V4_FLOW: 929d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 930d97b3072SJian Shen break; 931d97b3072SJian Shen case SCTP_V6_FLOW: 932d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 933d97b3072SJian Shen break; 934d97b3072SJian Shen case IPV4_FLOW: 935d97b3072SJian Shen case IPV6_FLOW: 936d97b3072SJian Shen tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 937d97b3072SJian Shen break; 938d97b3072SJian Shen default: 939d97b3072SJian Shen return -EINVAL; 940d97b3072SJian Shen } 941d97b3072SJian Shen 942d97b3072SJian Shen if (!tuple_sets) 943d97b3072SJian Shen return 0; 944d97b3072SJian Shen 945d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_PORT_BIT) 946d97b3072SJian Shen nfc->data |= RXH_L4_B_2_3; 947d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_PORT_BIT) 948d97b3072SJian Shen nfc->data |= RXH_L4_B_0_1; 949d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_IP_BIT) 950d97b3072SJian Shen nfc->data |= RXH_IP_DST; 951d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_IP_BIT) 952d97b3072SJian Shen nfc->data |= RXH_IP_SRC; 953d97b3072SJian Shen 954d97b3072SJian Shen return 0; 955d97b3072SJian Shen } 956d97b3072SJian Shen 957d97b3072SJian Shen static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 958d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg) 959d97b3072SJian Shen { 960d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 961d97b3072SJian Shen struct hclgevf_desc desc; 962d97b3072SJian Shen int ret; 963d97b3072SJian Shen 964d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 965d97b3072SJian Shen 966d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 967d97b3072SJian Shen 968d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 969d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 970d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 971d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 972d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 973d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 974d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 975d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 976d97b3072SJian Shen 977d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 978d97b3072SJian Shen if (ret) 979d97b3072SJian Shen dev_err(&hdev->pdev->dev, 980d97b3072SJian Shen "Configure rss input fail, status = %d\n", ret); 981d97b3072SJian Shen return ret; 982d97b3072SJian Shen } 983d97b3072SJian Shen 984e2cb1decSSalil Mehta static int hclgevf_get_tc_size(struct hnae3_handle *handle) 985e2cb1decSSalil Mehta { 986e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 987e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 988e2cb1decSSalil Mehta 989e2cb1decSSalil Mehta return rss_cfg->rss_size; 990e2cb1decSSalil Mehta } 991e2cb1decSSalil Mehta 992e2cb1decSSalil Mehta static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 993b204bc74SPeng Li int vector_id, 994e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 995e2cb1decSSalil Mehta { 996e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 997e2cb1decSSalil Mehta struct hnae3_ring_chain_node *node; 998e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 999e2cb1decSSalil Mehta struct hclgevf_desc desc; 1000b204bc74SPeng Li int i = 0; 1001e2cb1decSSalil Mehta int status; 1002e2cb1decSSalil Mehta u8 type; 1003e2cb1decSSalil Mehta 1004e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1005c09ba484SPeng Li type = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 1006c09ba484SPeng Li HCLGE_MBX_UNMAP_RING_TO_VECTOR; 1007e2cb1decSSalil Mehta 1008e2cb1decSSalil Mehta for (node = ring_chain; node; node = node->next) { 10095d02a58dSYunsheng Lin int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 10105d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 10115d02a58dSYunsheng Lin 10125d02a58dSYunsheng Lin if (i == 0) { 10135d02a58dSYunsheng Lin hclgevf_cmd_setup_basic_desc(&desc, 10145d02a58dSYunsheng Lin HCLGEVF_OPC_MBX_VF_TO_PF, 10155d02a58dSYunsheng Lin false); 10165d02a58dSYunsheng Lin req->msg[0] = type; 10175d02a58dSYunsheng Lin req->msg[1] = vector_id; 10185d02a58dSYunsheng Lin } 10195d02a58dSYunsheng Lin 10205d02a58dSYunsheng Lin req->msg[idx_offset] = 1021e4e87715SPeng Li hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 10225d02a58dSYunsheng Lin req->msg[idx_offset + 1] = node->tqp_index; 1023e4e87715SPeng Li req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 102479eee410SFuyun Liang HNAE3_RING_GL_IDX_M, 102579eee410SFuyun Liang HNAE3_RING_GL_IDX_S); 102679eee410SFuyun Liang 10275d02a58dSYunsheng Lin i++; 10285d02a58dSYunsheng Lin if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 10295d02a58dSYunsheng Lin HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 10305d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 10315d02a58dSYunsheng Lin !node->next) { 1032e2cb1decSSalil Mehta req->msg[2] = i; 1033e2cb1decSSalil Mehta 1034e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1035e2cb1decSSalil Mehta if (status) { 1036e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1037e2cb1decSSalil Mehta "Map TQP fail, status is %d.\n", 1038e2cb1decSSalil Mehta status); 1039e2cb1decSSalil Mehta return status; 1040e2cb1decSSalil Mehta } 1041e2cb1decSSalil Mehta i = 0; 1042e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 1043e2cb1decSSalil Mehta HCLGEVF_OPC_MBX_VF_TO_PF, 1044e2cb1decSSalil Mehta false); 1045e2cb1decSSalil Mehta req->msg[0] = type; 1046e2cb1decSSalil Mehta req->msg[1] = vector_id; 1047e2cb1decSSalil Mehta } 1048e2cb1decSSalil Mehta } 1049e2cb1decSSalil Mehta 1050e2cb1decSSalil Mehta return 0; 1051e2cb1decSSalil Mehta } 1052e2cb1decSSalil Mehta 1053e2cb1decSSalil Mehta static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1054e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1055e2cb1decSSalil Mehta { 1056b204bc74SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1057b204bc74SPeng Li int vector_id; 1058b204bc74SPeng Li 1059b204bc74SPeng Li vector_id = hclgevf_get_vector_index(hdev, vector); 1060b204bc74SPeng Li if (vector_id < 0) { 1061b204bc74SPeng Li dev_err(&handle->pdev->dev, 1062b204bc74SPeng Li "Get vector index fail. ret =%d\n", vector_id); 1063b204bc74SPeng Li return vector_id; 1064b204bc74SPeng Li } 1065b204bc74SPeng Li 1066b204bc74SPeng Li return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1067e2cb1decSSalil Mehta } 1068e2cb1decSSalil Mehta 1069e2cb1decSSalil Mehta static int hclgevf_unmap_ring_from_vector( 1070e2cb1decSSalil Mehta struct hnae3_handle *handle, 1071e2cb1decSSalil Mehta int vector, 1072e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1073e2cb1decSSalil Mehta { 1074e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1075e2cb1decSSalil Mehta int ret, vector_id; 1076e2cb1decSSalil Mehta 1077dea846e8SHuazhong Tan if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1078dea846e8SHuazhong Tan return 0; 1079dea846e8SHuazhong Tan 1080e2cb1decSSalil Mehta vector_id = hclgevf_get_vector_index(hdev, vector); 1081e2cb1decSSalil Mehta if (vector_id < 0) { 1082e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1083e2cb1decSSalil Mehta "Get vector index fail. ret =%d\n", vector_id); 1084e2cb1decSSalil Mehta return vector_id; 1085e2cb1decSSalil Mehta } 1086e2cb1decSSalil Mehta 1087b204bc74SPeng Li ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 10880d3e6631SYunsheng Lin if (ret) 1089e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1090e2cb1decSSalil Mehta "Unmap ring from vector fail. vector=%d, ret =%d\n", 1091e2cb1decSSalil Mehta vector_id, 1092e2cb1decSSalil Mehta ret); 10930d3e6631SYunsheng Lin 1094e2cb1decSSalil Mehta return ret; 1095e2cb1decSSalil Mehta } 1096e2cb1decSSalil Mehta 10970d3e6631SYunsheng Lin static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 10980d3e6631SYunsheng Lin { 10990d3e6631SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 110003718db9SYunsheng Lin int vector_id; 11010d3e6631SYunsheng Lin 110203718db9SYunsheng Lin vector_id = hclgevf_get_vector_index(hdev, vector); 110303718db9SYunsheng Lin if (vector_id < 0) { 110403718db9SYunsheng Lin dev_err(&handle->pdev->dev, 110503718db9SYunsheng Lin "hclgevf_put_vector get vector index fail. ret =%d\n", 110603718db9SYunsheng Lin vector_id); 110703718db9SYunsheng Lin return vector_id; 110803718db9SYunsheng Lin } 110903718db9SYunsheng Lin 111003718db9SYunsheng Lin hclgevf_free_vector(hdev, vector_id); 1111e2cb1decSSalil Mehta 1112e2cb1decSSalil Mehta return 0; 1113e2cb1decSSalil Mehta } 1114e2cb1decSSalil Mehta 11153b75c3dfSPeng Li static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1116e196ec75SJian Shen bool en_uc_pmc, bool en_mc_pmc, 1117f01f5559SJian Shen bool en_bc_pmc) 1118e2cb1decSSalil Mehta { 1119e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 1120e2cb1decSSalil Mehta struct hclgevf_desc desc; 1121f01f5559SJian Shen int ret; 1122e2cb1decSSalil Mehta 1123e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1124e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 1125e2cb1decSSalil Mehta req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 1126f01f5559SJian Shen req->msg[1] = en_bc_pmc ? 1 : 0; 1127e196ec75SJian Shen req->msg[2] = en_uc_pmc ? 1 : 0; 1128e196ec75SJian Shen req->msg[3] = en_mc_pmc ? 1 : 0; 1129e2cb1decSSalil Mehta 1130f01f5559SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1131f01f5559SJian Shen if (ret) 1132e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1133f01f5559SJian Shen "Set promisc mode fail, status is %d.\n", ret); 1134e2cb1decSSalil Mehta 1135f01f5559SJian Shen return ret; 1136e2cb1decSSalil Mehta } 1137e2cb1decSSalil Mehta 1138e196ec75SJian Shen static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 1139e196ec75SJian Shen bool en_mc_pmc) 1140e2cb1decSSalil Mehta { 1141e196ec75SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1142e196ec75SJian Shen struct pci_dev *pdev = hdev->pdev; 1143e196ec75SJian Shen bool en_bc_pmc; 1144e196ec75SJian Shen 1145e196ec75SJian Shen en_bc_pmc = pdev->revision != 0x20; 1146e196ec75SJian Shen 1147e196ec75SJian Shen return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc, 1148e196ec75SJian Shen en_bc_pmc); 1149e2cb1decSSalil Mehta } 1150e2cb1decSSalil Mehta 1151ebaf1908SWeihang Li static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, unsigned int tqp_id, 1152e2cb1decSSalil Mehta int stream_id, bool enable) 1153e2cb1decSSalil Mehta { 1154e2cb1decSSalil Mehta struct hclgevf_cfg_com_tqp_queue_cmd *req; 1155e2cb1decSSalil Mehta struct hclgevf_desc desc; 1156e2cb1decSSalil Mehta int status; 1157e2cb1decSSalil Mehta 1158e2cb1decSSalil Mehta req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1159e2cb1decSSalil Mehta 1160e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1161e2cb1decSSalil Mehta false); 1162e2cb1decSSalil Mehta req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1163e2cb1decSSalil Mehta req->stream_id = cpu_to_le16(stream_id); 1164ebaf1908SWeihang Li if (enable) 1165ebaf1908SWeihang Li req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 1166e2cb1decSSalil Mehta 1167e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1168e2cb1decSSalil Mehta if (status) 1169e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1170e2cb1decSSalil Mehta "TQP enable fail, status =%d.\n", status); 1171e2cb1decSSalil Mehta 1172e2cb1decSSalil Mehta return status; 1173e2cb1decSSalil Mehta } 1174e2cb1decSSalil Mehta 1175e2cb1decSSalil Mehta static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1176e2cb1decSSalil Mehta { 1177b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1178e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 1179e2cb1decSSalil Mehta int i; 1180e2cb1decSSalil Mehta 1181b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 1182b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1183e2cb1decSSalil Mehta memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1184e2cb1decSSalil Mehta } 1185e2cb1decSSalil Mehta } 1186e2cb1decSSalil Mehta 11878e6de441SHuazhong Tan static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p) 11888e6de441SHuazhong Tan { 11898e6de441SHuazhong Tan u8 host_mac[ETH_ALEN]; 11908e6de441SHuazhong Tan int status; 11918e6de441SHuazhong Tan 11928e6de441SHuazhong Tan status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_MAC_ADDR, 0, NULL, 0, 11938e6de441SHuazhong Tan true, host_mac, ETH_ALEN); 11948e6de441SHuazhong Tan if (status) { 11958e6de441SHuazhong Tan dev_err(&hdev->pdev->dev, 11968e6de441SHuazhong Tan "fail to get VF MAC from host %d", status); 11978e6de441SHuazhong Tan return status; 11988e6de441SHuazhong Tan } 11998e6de441SHuazhong Tan 12008e6de441SHuazhong Tan ether_addr_copy(p, host_mac); 12018e6de441SHuazhong Tan 12028e6de441SHuazhong Tan return 0; 12038e6de441SHuazhong Tan } 12048e6de441SHuazhong Tan 1205e2cb1decSSalil Mehta static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1206e2cb1decSSalil Mehta { 1207e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 12088e6de441SHuazhong Tan u8 host_mac_addr[ETH_ALEN]; 1209e2cb1decSSalil Mehta 12108e6de441SHuazhong Tan if (hclgevf_get_host_mac_addr(hdev, host_mac_addr)) 12118e6de441SHuazhong Tan return; 12128e6de441SHuazhong Tan 12138e6de441SHuazhong Tan hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr); 12148e6de441SHuazhong Tan if (hdev->has_pf_mac) 12158e6de441SHuazhong Tan ether_addr_copy(p, host_mac_addr); 12168e6de441SHuazhong Tan else 1217e2cb1decSSalil Mehta ether_addr_copy(p, hdev->hw.mac.mac_addr); 1218e2cb1decSSalil Mehta } 1219e2cb1decSSalil Mehta 122059098055SFuyun Liang static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 122159098055SFuyun Liang bool is_first) 1222e2cb1decSSalil Mehta { 1223e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1224e2cb1decSSalil Mehta u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1225e2cb1decSSalil Mehta u8 *new_mac_addr = (u8 *)p; 1226e2cb1decSSalil Mehta u8 msg_data[ETH_ALEN * 2]; 122759098055SFuyun Liang u16 subcode; 1228e2cb1decSSalil Mehta int status; 1229e2cb1decSSalil Mehta 1230e2cb1decSSalil Mehta ether_addr_copy(msg_data, new_mac_addr); 1231e2cb1decSSalil Mehta ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 1232e2cb1decSSalil Mehta 123359098055SFuyun Liang subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 123459098055SFuyun Liang HCLGE_MBX_MAC_VLAN_UC_MODIFY; 123559098055SFuyun Liang 1236e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 123763cbf7a9SYufeng Mo subcode, msg_data, sizeof(msg_data), 12382097fdefSJian Shen true, NULL, 0); 1239e2cb1decSSalil Mehta if (!status) 1240e2cb1decSSalil Mehta ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1241e2cb1decSSalil Mehta 1242e2cb1decSSalil Mehta return status; 1243e2cb1decSSalil Mehta } 1244e2cb1decSSalil Mehta 1245e2cb1decSSalil Mehta static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1246e2cb1decSSalil Mehta const unsigned char *addr) 1247e2cb1decSSalil Mehta { 1248e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1249e2cb1decSSalil Mehta 1250e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1251e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_ADD, 1252e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1253e2cb1decSSalil Mehta } 1254e2cb1decSSalil Mehta 1255e2cb1decSSalil Mehta static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1256e2cb1decSSalil Mehta const unsigned char *addr) 1257e2cb1decSSalil Mehta { 1258e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1259e2cb1decSSalil Mehta 1260e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1261e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1262e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1263e2cb1decSSalil Mehta } 1264e2cb1decSSalil Mehta 1265e2cb1decSSalil Mehta static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1266e2cb1decSSalil Mehta const unsigned char *addr) 1267e2cb1decSSalil Mehta { 1268e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1269e2cb1decSSalil Mehta 1270e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1271e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_ADD, 1272e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1273e2cb1decSSalil Mehta } 1274e2cb1decSSalil Mehta 1275e2cb1decSSalil Mehta static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1276e2cb1decSSalil Mehta const unsigned char *addr) 1277e2cb1decSSalil Mehta { 1278e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1279e2cb1decSSalil Mehta 1280e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1281e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1282e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1283e2cb1decSSalil Mehta } 1284e2cb1decSSalil Mehta 1285e2cb1decSSalil Mehta static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1286e2cb1decSSalil Mehta __be16 proto, u16 vlan_id, 1287e2cb1decSSalil Mehta bool is_kill) 1288e2cb1decSSalil Mehta { 1289e2cb1decSSalil Mehta #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1290e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1291e2cb1decSSalil Mehta u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1292fe4144d4SJian Shen int ret; 1293e2cb1decSSalil Mehta 1294b37ce587SYufeng Mo if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1295e2cb1decSSalil Mehta return -EINVAL; 1296e2cb1decSSalil Mehta 1297e2cb1decSSalil Mehta if (proto != htons(ETH_P_8021Q)) 1298e2cb1decSSalil Mehta return -EPROTONOSUPPORT; 1299e2cb1decSSalil Mehta 1300fe4144d4SJian Shen /* When device is resetting, firmware is unable to handle 1301fe4144d4SJian Shen * mailbox. Just record the vlan id, and remove it after 1302fe4144d4SJian Shen * reset finished. 1303fe4144d4SJian Shen */ 1304fe4144d4SJian Shen if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) && is_kill) { 1305fe4144d4SJian Shen set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1306fe4144d4SJian Shen return -EBUSY; 1307fe4144d4SJian Shen } 1308fe4144d4SJian Shen 1309e2cb1decSSalil Mehta msg_data[0] = is_kill; 1310e2cb1decSSalil Mehta memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1311e2cb1decSSalil Mehta memcpy(&msg_data[3], &proto, sizeof(proto)); 1312fe4144d4SJian Shen ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1313e2cb1decSSalil Mehta HCLGE_MBX_VLAN_FILTER, msg_data, 131422044f95SJian Shen HCLGEVF_VLAN_MBX_MSG_LEN, true, NULL, 0); 1315fe4144d4SJian Shen 131646ee7350SGuojia Liao /* when remove hw vlan filter failed, record the vlan id, 1317fe4144d4SJian Shen * and try to remove it from hw later, to be consistence 1318fe4144d4SJian Shen * with stack. 1319fe4144d4SJian Shen */ 1320fe4144d4SJian Shen if (is_kill && ret) 1321fe4144d4SJian Shen set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1322fe4144d4SJian Shen 1323fe4144d4SJian Shen return ret; 1324fe4144d4SJian Shen } 1325fe4144d4SJian Shen 1326fe4144d4SJian Shen static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1327fe4144d4SJian Shen { 1328fe4144d4SJian Shen #define HCLGEVF_MAX_SYNC_COUNT 60 1329fe4144d4SJian Shen struct hnae3_handle *handle = &hdev->nic; 1330fe4144d4SJian Shen int ret, sync_cnt = 0; 1331fe4144d4SJian Shen u16 vlan_id; 1332fe4144d4SJian Shen 1333fe4144d4SJian Shen vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1334fe4144d4SJian Shen while (vlan_id != VLAN_N_VID) { 1335fe4144d4SJian Shen ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1336fe4144d4SJian Shen vlan_id, true); 1337fe4144d4SJian Shen if (ret) 1338fe4144d4SJian Shen return; 1339fe4144d4SJian Shen 1340fe4144d4SJian Shen clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1341fe4144d4SJian Shen sync_cnt++; 1342fe4144d4SJian Shen if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1343fe4144d4SJian Shen return; 1344fe4144d4SJian Shen 1345fe4144d4SJian Shen vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1346fe4144d4SJian Shen } 1347e2cb1decSSalil Mehta } 1348e2cb1decSSalil Mehta 1349b2641e2aSYunsheng Lin static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1350b2641e2aSYunsheng Lin { 1351b2641e2aSYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1352b2641e2aSYunsheng Lin u8 msg_data; 1353b2641e2aSYunsheng Lin 1354b2641e2aSYunsheng Lin msg_data = enable ? 1 : 0; 1355b2641e2aSYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1356b2641e2aSYunsheng Lin HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1357b2641e2aSYunsheng Lin 1, false, NULL, 0); 1358b2641e2aSYunsheng Lin } 1359b2641e2aSYunsheng Lin 13607fa6be4fSHuazhong Tan static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1361e2cb1decSSalil Mehta { 1362e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1363e2cb1decSSalil Mehta u8 msg_data[2]; 13641a426f8bSPeng Li int ret; 1365e2cb1decSSalil Mehta 136663cbf7a9SYufeng Mo memcpy(msg_data, &queue_id, sizeof(queue_id)); 1367e2cb1decSSalil Mehta 13681a426f8bSPeng Li /* disable vf queue before send queue reset msg to PF */ 13691a426f8bSPeng Li ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 13701a426f8bSPeng Li if (ret) 13717fa6be4fSHuazhong Tan return ret; 13721a426f8bSPeng Li 13737fa6be4fSHuazhong Tan return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 137463cbf7a9SYufeng Mo sizeof(msg_data), true, NULL, 0); 1375e2cb1decSSalil Mehta } 1376e2cb1decSSalil Mehta 1377818f1675SYunsheng Lin static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1378818f1675SYunsheng Lin { 1379818f1675SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1380818f1675SYunsheng Lin 1381818f1675SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu, 1382818f1675SYunsheng Lin sizeof(new_mtu), true, NULL, 0); 1383818f1675SYunsheng Lin } 1384818f1675SYunsheng Lin 13856988eb2aSSalil Mehta static int hclgevf_notify_client(struct hclgevf_dev *hdev, 13866988eb2aSSalil Mehta enum hnae3_reset_notify_type type) 13876988eb2aSSalil Mehta { 13886988eb2aSSalil Mehta struct hnae3_client *client = hdev->nic_client; 13896988eb2aSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 13906a5f6fa3SHuazhong Tan int ret; 13916988eb2aSSalil Mehta 139225d1817cSHuazhong Tan if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 139325d1817cSHuazhong Tan !client) 139425d1817cSHuazhong Tan return 0; 139525d1817cSHuazhong Tan 13966988eb2aSSalil Mehta if (!client->ops->reset_notify) 13976988eb2aSSalil Mehta return -EOPNOTSUPP; 13986988eb2aSSalil Mehta 13996a5f6fa3SHuazhong Tan ret = client->ops->reset_notify(handle, type); 14006a5f6fa3SHuazhong Tan if (ret) 14016a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 14026a5f6fa3SHuazhong Tan type, ret); 14036a5f6fa3SHuazhong Tan 14046a5f6fa3SHuazhong Tan return ret; 14056988eb2aSSalil Mehta } 14066988eb2aSSalil Mehta 14076ff3cf07SHuazhong Tan static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 14086ff3cf07SHuazhong Tan { 14096ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 14106ff3cf07SHuazhong Tan 14116ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DONE, &hdev->flr_state); 14126ff3cf07SHuazhong Tan } 14136ff3cf07SHuazhong Tan 14146ff3cf07SHuazhong Tan static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev, 14156ff3cf07SHuazhong Tan unsigned long delay_us, 14166ff3cf07SHuazhong Tan unsigned long wait_cnt) 14176ff3cf07SHuazhong Tan { 14186ff3cf07SHuazhong Tan unsigned long cnt = 0; 14196ff3cf07SHuazhong Tan 14206ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) && 14216ff3cf07SHuazhong Tan cnt++ < wait_cnt) 14226ff3cf07SHuazhong Tan usleep_range(delay_us, delay_us * 2); 14236ff3cf07SHuazhong Tan 14246ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) { 14256ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 14266ff3cf07SHuazhong Tan "flr wait timeout\n"); 14276ff3cf07SHuazhong Tan return -ETIMEDOUT; 14286ff3cf07SHuazhong Tan } 14296ff3cf07SHuazhong Tan 14306ff3cf07SHuazhong Tan return 0; 14316ff3cf07SHuazhong Tan } 14326ff3cf07SHuazhong Tan 14336988eb2aSSalil Mehta static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 14346988eb2aSSalil Mehta { 1435aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_US 20000 1436aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_CNT 2000 1437aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1438aa5c4f17SHuazhong Tan (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1439aa5c4f17SHuazhong Tan 1440aa5c4f17SHuazhong Tan u32 val; 1441aa5c4f17SHuazhong Tan int ret; 14426988eb2aSSalil Mehta 14436ff3cf07SHuazhong Tan if (hdev->reset_type == HNAE3_FLR_RESET) 14446ff3cf07SHuazhong Tan return hclgevf_flr_poll_timeout(hdev, 14456ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_US, 14466ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_CNT); 144772e2fb07SHuazhong Tan else if (hdev->reset_type == HNAE3_VF_RESET) 144872e2fb07SHuazhong Tan ret = readl_poll_timeout(hdev->hw.io_base + 144972e2fb07SHuazhong Tan HCLGEVF_VF_RST_ING, val, 145072e2fb07SHuazhong Tan !(val & HCLGEVF_VF_RST_ING_BIT), 145172e2fb07SHuazhong Tan HCLGEVF_RESET_WAIT_US, 145272e2fb07SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 145372e2fb07SHuazhong Tan else 145472e2fb07SHuazhong Tan ret = readl_poll_timeout(hdev->hw.io_base + 145572e2fb07SHuazhong Tan HCLGEVF_RST_ING, val, 1456aa5c4f17SHuazhong Tan !(val & HCLGEVF_RST_ING_BITS), 1457aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_US, 1458aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 14596988eb2aSSalil Mehta 14606988eb2aSSalil Mehta /* hardware completion status should be available by this time */ 1461aa5c4f17SHuazhong Tan if (ret) { 1462aa5c4f17SHuazhong Tan dev_err(&hdev->pdev->dev, 14636988eb2aSSalil Mehta "could'nt get reset done status from h/w, timeout!\n"); 1464aa5c4f17SHuazhong Tan return ret; 14656988eb2aSSalil Mehta } 14666988eb2aSSalil Mehta 14676988eb2aSSalil Mehta /* we will wait a bit more to let reset of the stack to complete. This 14686988eb2aSSalil Mehta * might happen in case reset assertion was made by PF. Yes, this also 14696988eb2aSSalil Mehta * means we might end up waiting bit more even for VF reset. 14706988eb2aSSalil Mehta */ 14716988eb2aSSalil Mehta msleep(5000); 14726988eb2aSSalil Mehta 14736988eb2aSSalil Mehta return 0; 14746988eb2aSSalil Mehta } 14756988eb2aSSalil Mehta 14766b428b4fSHuazhong Tan static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable) 14776b428b4fSHuazhong Tan { 14786b428b4fSHuazhong Tan u32 reg_val; 14796b428b4fSHuazhong Tan 14806b428b4fSHuazhong Tan reg_val = hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG); 14816b428b4fSHuazhong Tan if (enable) 14826b428b4fSHuazhong Tan reg_val |= HCLGEVF_NIC_SW_RST_RDY; 14836b428b4fSHuazhong Tan else 14846b428b4fSHuazhong Tan reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; 14856b428b4fSHuazhong Tan 14866b428b4fSHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 14876b428b4fSHuazhong Tan reg_val); 14886b428b4fSHuazhong Tan } 14896b428b4fSHuazhong Tan 14906988eb2aSSalil Mehta static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 14916988eb2aSSalil Mehta { 14927a01c897SSalil Mehta int ret; 14937a01c897SSalil Mehta 14946988eb2aSSalil Mehta /* uninitialize the nic client */ 14956a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 14966a5f6fa3SHuazhong Tan if (ret) 14976a5f6fa3SHuazhong Tan return ret; 14986988eb2aSSalil Mehta 14997a01c897SSalil Mehta /* re-initialize the hclge device */ 15009c6f7085SHuazhong Tan ret = hclgevf_reset_hdev(hdev); 15017a01c897SSalil Mehta if (ret) { 15027a01c897SSalil Mehta dev_err(&hdev->pdev->dev, 15037a01c897SSalil Mehta "hclge device re-init failed, VF is disabled!\n"); 15047a01c897SSalil Mehta return ret; 15057a01c897SSalil Mehta } 15066988eb2aSSalil Mehta 15076988eb2aSSalil Mehta /* bring up the nic client again */ 15086a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 15096a5f6fa3SHuazhong Tan if (ret) 15106a5f6fa3SHuazhong Tan return ret; 15116988eb2aSSalil Mehta 15126b428b4fSHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT); 15136b428b4fSHuazhong Tan if (ret) 15146b428b4fSHuazhong Tan return ret; 15156b428b4fSHuazhong Tan 15166b428b4fSHuazhong Tan /* clear handshake status with IMP */ 15176b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, false); 15186b428b4fSHuazhong Tan 15196b428b4fSHuazhong Tan return 0; 15206988eb2aSSalil Mehta } 15216988eb2aSSalil Mehta 1522dea846e8SHuazhong Tan static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1523dea846e8SHuazhong Tan { 1524ada13ee3SHuazhong Tan #define HCLGEVF_RESET_SYNC_TIME 100 1525ada13ee3SHuazhong Tan 1526dea846e8SHuazhong Tan int ret = 0; 1527dea846e8SHuazhong Tan 1528dea846e8SHuazhong Tan switch (hdev->reset_type) { 1529dea846e8SHuazhong Tan case HNAE3_VF_FUNC_RESET: 1530dea846e8SHuazhong Tan ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1531dea846e8SHuazhong Tan 0, true, NULL, sizeof(u8)); 1532c88a6e7dSHuazhong Tan hdev->rst_stats.vf_func_rst_cnt++; 1533dea846e8SHuazhong Tan break; 15346ff3cf07SHuazhong Tan case HNAE3_FLR_RESET: 15356ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1536c88a6e7dSHuazhong Tan hdev->rst_stats.flr_rst_cnt++; 15376ff3cf07SHuazhong Tan break; 1538dea846e8SHuazhong Tan default: 1539dea846e8SHuazhong Tan break; 1540dea846e8SHuazhong Tan } 1541dea846e8SHuazhong Tan 1542ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1543ada13ee3SHuazhong Tan /* inform hardware that preparatory work is done */ 1544ada13ee3SHuazhong Tan msleep(HCLGEVF_RESET_SYNC_TIME); 15456b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, true); 1546dea846e8SHuazhong Tan dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1547dea846e8SHuazhong Tan hdev->reset_type, ret); 1548dea846e8SHuazhong Tan 1549dea846e8SHuazhong Tan return ret; 1550dea846e8SHuazhong Tan } 1551dea846e8SHuazhong Tan 15523d77d0cbSHuazhong Tan static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev) 15533d77d0cbSHuazhong Tan { 15543d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "VF function reset count: %u\n", 15553d77d0cbSHuazhong Tan hdev->rst_stats.vf_func_rst_cnt); 15563d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "FLR reset count: %u\n", 15573d77d0cbSHuazhong Tan hdev->rst_stats.flr_rst_cnt); 15583d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "VF reset count: %u\n", 15593d77d0cbSHuazhong Tan hdev->rst_stats.vf_rst_cnt); 15603d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "reset done count: %u\n", 15613d77d0cbSHuazhong Tan hdev->rst_stats.rst_done_cnt); 15623d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "HW reset done count: %u\n", 15633d77d0cbSHuazhong Tan hdev->rst_stats.hw_rst_done_cnt); 15643d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "reset count: %u\n", 15653d77d0cbSHuazhong Tan hdev->rst_stats.rst_cnt); 15663d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "reset fail count: %u\n", 15673d77d0cbSHuazhong Tan hdev->rst_stats.rst_fail_cnt); 15683d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n", 15693d77d0cbSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE)); 15703d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n", 15713d77d0cbSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_STAT_REG)); 15723d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n", 15733d77d0cbSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_CMDQ_TX_DEPTH_REG)); 15743d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n", 15753d77d0cbSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING)); 15763d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state); 15773d77d0cbSHuazhong Tan } 15783d77d0cbSHuazhong Tan 1579bbe6540eSHuazhong Tan static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1580bbe6540eSHuazhong Tan { 15816b428b4fSHuazhong Tan /* recover handshake status with IMP when reset fail */ 15826b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, true); 1583bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt++; 1584adcf738bSGuojia Liao dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n", 1585bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt); 1586bbe6540eSHuazhong Tan 1587bbe6540eSHuazhong Tan if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1588bbe6540eSHuazhong Tan set_bit(hdev->reset_type, &hdev->reset_pending); 1589bbe6540eSHuazhong Tan 1590bbe6540eSHuazhong Tan if (hclgevf_is_reset_pending(hdev)) { 1591bbe6540eSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1592bbe6540eSHuazhong Tan hclgevf_reset_task_schedule(hdev); 15933d77d0cbSHuazhong Tan } else { 15943d77d0cbSHuazhong Tan hclgevf_dump_rst_info(hdev); 1595bbe6540eSHuazhong Tan } 1596bbe6540eSHuazhong Tan } 1597bbe6540eSHuazhong Tan 15986988eb2aSSalil Mehta static int hclgevf_reset(struct hclgevf_dev *hdev) 15996988eb2aSSalil Mehta { 1600dea846e8SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 16016988eb2aSSalil Mehta int ret; 16026988eb2aSSalil Mehta 1603dea846e8SHuazhong Tan /* Initialize ae_dev reset status as well, in case enet layer wants to 1604dea846e8SHuazhong Tan * know if device is undergoing reset 1605dea846e8SHuazhong Tan */ 1606dea846e8SHuazhong Tan ae_dev->reset_type = hdev->reset_type; 1607c88a6e7dSHuazhong Tan hdev->rst_stats.rst_cnt++; 16086988eb2aSSalil Mehta rtnl_lock(); 16096988eb2aSSalil Mehta 16106988eb2aSSalil Mehta /* bring down the nic to stop any ongoing TX/RX */ 16116a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 16126a5f6fa3SHuazhong Tan if (ret) 16136a5f6fa3SHuazhong Tan goto err_reset_lock; 16146988eb2aSSalil Mehta 161529118ab9SHuazhong Tan rtnl_unlock(); 161629118ab9SHuazhong Tan 16176a5f6fa3SHuazhong Tan ret = hclgevf_reset_prepare_wait(hdev); 16186a5f6fa3SHuazhong Tan if (ret) 16196a5f6fa3SHuazhong Tan goto err_reset; 1620dea846e8SHuazhong Tan 16216988eb2aSSalil Mehta /* check if VF could successfully fetch the hardware reset completion 16226988eb2aSSalil Mehta * status from the hardware 16236988eb2aSSalil Mehta */ 16246988eb2aSSalil Mehta ret = hclgevf_reset_wait(hdev); 16256988eb2aSSalil Mehta if (ret) { 16266988eb2aSSalil Mehta /* can't do much in this situation, will disable VF */ 16276988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, 16286988eb2aSSalil Mehta "VF failed(=%d) to fetch H/W reset completion status\n", 16296988eb2aSSalil Mehta ret); 16306a5f6fa3SHuazhong Tan goto err_reset; 16316988eb2aSSalil Mehta } 16326988eb2aSSalil Mehta 1633c88a6e7dSHuazhong Tan hdev->rst_stats.hw_rst_done_cnt++; 1634c88a6e7dSHuazhong Tan 163529118ab9SHuazhong Tan rtnl_lock(); 163629118ab9SHuazhong Tan 16376988eb2aSSalil Mehta /* now, re-initialize the nic client and ae device */ 16386988eb2aSSalil Mehta ret = hclgevf_reset_stack(hdev); 16396a5f6fa3SHuazhong Tan if (ret) { 16406988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 16416a5f6fa3SHuazhong Tan goto err_reset_lock; 16426a5f6fa3SHuazhong Tan } 16436988eb2aSSalil Mehta 16446988eb2aSSalil Mehta /* bring up the nic to enable TX/RX again */ 16456a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 16466a5f6fa3SHuazhong Tan if (ret) 16476a5f6fa3SHuazhong Tan goto err_reset_lock; 16486988eb2aSSalil Mehta 16496988eb2aSSalil Mehta rtnl_unlock(); 16506988eb2aSSalil Mehta 1651b644a8d4SHuazhong Tan hdev->last_reset_time = jiffies; 1652b644a8d4SHuazhong Tan ae_dev->reset_type = HNAE3_NONE_RESET; 1653c88a6e7dSHuazhong Tan hdev->rst_stats.rst_done_cnt++; 1654bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt = 0; 1655b644a8d4SHuazhong Tan 16566988eb2aSSalil Mehta return ret; 16576a5f6fa3SHuazhong Tan err_reset_lock: 16586a5f6fa3SHuazhong Tan rtnl_unlock(); 16596a5f6fa3SHuazhong Tan err_reset: 1660bbe6540eSHuazhong Tan hclgevf_reset_err_handle(hdev); 16616a5f6fa3SHuazhong Tan 16626a5f6fa3SHuazhong Tan return ret; 16636988eb2aSSalil Mehta } 16646988eb2aSSalil Mehta 1665720bd583SHuazhong Tan static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1666720bd583SHuazhong Tan unsigned long *addr) 1667720bd583SHuazhong Tan { 1668720bd583SHuazhong Tan enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1669720bd583SHuazhong Tan 1670dea846e8SHuazhong Tan /* return the highest priority reset level amongst all */ 1671b90fcc5bSHuazhong Tan if (test_bit(HNAE3_VF_RESET, addr)) { 1672b90fcc5bSHuazhong Tan rst_level = HNAE3_VF_RESET; 1673b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_RESET, addr); 1674b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1675b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1676b90fcc5bSHuazhong Tan } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1677dea846e8SHuazhong Tan rst_level = HNAE3_VF_FULL_RESET; 1678dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FULL_RESET, addr); 1679dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1680aa5c4f17SHuazhong Tan } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1681aa5c4f17SHuazhong Tan rst_level = HNAE3_VF_PF_FUNC_RESET; 1682aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1683aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1684dea846e8SHuazhong Tan } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1685dea846e8SHuazhong Tan rst_level = HNAE3_VF_FUNC_RESET; 1686dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 16876ff3cf07SHuazhong Tan } else if (test_bit(HNAE3_FLR_RESET, addr)) { 16886ff3cf07SHuazhong Tan rst_level = HNAE3_FLR_RESET; 16896ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_RESET, addr); 1690720bd583SHuazhong Tan } 1691720bd583SHuazhong Tan 1692720bd583SHuazhong Tan return rst_level; 1693720bd583SHuazhong Tan } 1694720bd583SHuazhong Tan 16956ae4e733SShiju Jose static void hclgevf_reset_event(struct pci_dev *pdev, 16966ae4e733SShiju Jose struct hnae3_handle *handle) 16976d4c3981SSalil Mehta { 16986ff3cf07SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 16996ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 17006d4c3981SSalil Mehta 17016d4c3981SSalil Mehta dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 17026d4c3981SSalil Mehta 17036ff3cf07SHuazhong Tan if (hdev->default_reset_request) 17040742ed7cSHuazhong Tan hdev->reset_level = 1705720bd583SHuazhong Tan hclgevf_get_reset_level(hdev, 1706720bd583SHuazhong Tan &hdev->default_reset_request); 1707720bd583SHuazhong Tan else 1708dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 17096d4c3981SSalil Mehta 1710436667d2SSalil Mehta /* reset of this VF requested */ 1711436667d2SSalil Mehta set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1712436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 17136d4c3981SSalil Mehta 17140742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 17156d4c3981SSalil Mehta } 17166d4c3981SSalil Mehta 1717720bd583SHuazhong Tan static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1718720bd583SHuazhong Tan enum hnae3_reset_type rst_type) 1719720bd583SHuazhong Tan { 1720720bd583SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1721720bd583SHuazhong Tan 1722720bd583SHuazhong Tan set_bit(rst_type, &hdev->default_reset_request); 1723720bd583SHuazhong Tan } 1724720bd583SHuazhong Tan 17256ff3cf07SHuazhong Tan static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 17266ff3cf07SHuazhong Tan { 17276ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_MS 100 17286ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_CNT 50 17296ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 17306ff3cf07SHuazhong Tan int cnt = 0; 17316ff3cf07SHuazhong Tan 17326ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 17336ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DONE, &hdev->flr_state); 17346ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request); 17356ff3cf07SHuazhong Tan hclgevf_reset_event(hdev->pdev, NULL); 17366ff3cf07SHuazhong Tan 17376ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) && 17386ff3cf07SHuazhong Tan cnt++ < HCLGEVF_FLR_WAIT_CNT) 17396ff3cf07SHuazhong Tan msleep(HCLGEVF_FLR_WAIT_MS); 17406ff3cf07SHuazhong Tan 17416ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state)) 17426ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 17436ff3cf07SHuazhong Tan "flr wait down timeout: %d\n", cnt); 17446ff3cf07SHuazhong Tan } 17456ff3cf07SHuazhong Tan 1746e2cb1decSSalil Mehta static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1747e2cb1decSSalil Mehta { 1748e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1749e2cb1decSSalil Mehta 1750e2cb1decSSalil Mehta return hdev->fw_version; 1751e2cb1decSSalil Mehta } 1752e2cb1decSSalil Mehta 1753e2cb1decSSalil Mehta static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1754e2cb1decSSalil Mehta { 1755e2cb1decSSalil Mehta struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1756e2cb1decSSalil Mehta 1757e2cb1decSSalil Mehta vector->vector_irq = pci_irq_vector(hdev->pdev, 1758e2cb1decSSalil Mehta HCLGEVF_MISC_VECTOR_NUM); 1759e2cb1decSSalil Mehta vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1760e2cb1decSSalil Mehta /* vector status always valid for Vector 0 */ 1761e2cb1decSSalil Mehta hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1762e2cb1decSSalil Mehta hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1763e2cb1decSSalil Mehta 1764e2cb1decSSalil Mehta hdev->num_msi_left -= 1; 1765e2cb1decSSalil Mehta hdev->num_msi_used += 1; 1766e2cb1decSSalil Mehta } 1767e2cb1decSSalil Mehta 176835a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 176935a1e503SSalil Mehta { 1770acfc3d55SHuazhong Tan if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) && 1771acfc3d55SHuazhong Tan !test_bit(HCLGEVF_STATE_REMOVING, &hdev->state)) { 177235a1e503SSalil Mehta set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 177335a1e503SSalil Mehta schedule_work(&hdev->rst_service_task); 177435a1e503SSalil Mehta } 177535a1e503SSalil Mehta } 177635a1e503SSalil Mehta 177707a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1778e2cb1decSSalil Mehta { 177907a0556aSSalil Mehta if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) && 178007a0556aSSalil Mehta !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) { 178107a0556aSSalil Mehta set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1782e2cb1decSSalil Mehta schedule_work(&hdev->mbx_service_task); 1783e2cb1decSSalil Mehta } 178407a0556aSSalil Mehta } 1785e2cb1decSSalil Mehta 1786e2cb1decSSalil Mehta static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 1787e2cb1decSSalil Mehta { 1788e2cb1decSSalil Mehta if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 1789b3c3fe8eSYunsheng Lin !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) { 1790b3c3fe8eSYunsheng Lin mod_delayed_work(system_wq, &hdev->service_task, 1791b3c3fe8eSYunsheng Lin round_jiffies_relative(HZ)); 1792b3c3fe8eSYunsheng Lin hdev->stats_timer++; 1793b3c3fe8eSYunsheng Lin } 1794e2cb1decSSalil Mehta } 1795e2cb1decSSalil Mehta 1796436667d2SSalil Mehta static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev) 1797436667d2SSalil Mehta { 179807a0556aSSalil Mehta /* if we have any pending mailbox event then schedule the mbx task */ 179907a0556aSSalil Mehta if (hdev->mbx_event_pending) 180007a0556aSSalil Mehta hclgevf_mbx_task_schedule(hdev); 180107a0556aSSalil Mehta 1802436667d2SSalil Mehta if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state)) 1803436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 1804436667d2SSalil Mehta } 1805436667d2SSalil Mehta 180635a1e503SSalil Mehta static void hclgevf_reset_service_task(struct work_struct *work) 180735a1e503SSalil Mehta { 1808d6ad7c53SGuojia Liao #define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3 1809d6ad7c53SGuojia Liao 181035a1e503SSalil Mehta struct hclgevf_dev *hdev = 181135a1e503SSalil Mehta container_of(work, struct hclgevf_dev, rst_service_task); 1812a8dedb65SSalil Mehta int ret; 181335a1e503SSalil Mehta 181435a1e503SSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 181535a1e503SSalil Mehta return; 181635a1e503SSalil Mehta 181735a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 181835a1e503SSalil Mehta 1819436667d2SSalil Mehta if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1820436667d2SSalil Mehta &hdev->reset_state)) { 1821436667d2SSalil Mehta /* PF has initmated that it is about to reset the hardware. 18229b2f3477SWeihang Li * We now have to poll & check if hardware has actually 18239b2f3477SWeihang Li * completed the reset sequence. On hardware reset completion, 18249b2f3477SWeihang Li * VF needs to reset the client and ae device. 182535a1e503SSalil Mehta */ 1826436667d2SSalil Mehta hdev->reset_attempts = 0; 1827436667d2SSalil Mehta 1828dea846e8SHuazhong Tan hdev->last_reset_time = jiffies; 1829dea846e8SHuazhong Tan while ((hdev->reset_type = 1830dea846e8SHuazhong Tan hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 1831dea846e8SHuazhong Tan != HNAE3_NONE_RESET) { 18326988eb2aSSalil Mehta ret = hclgevf_reset(hdev); 18336988eb2aSSalil Mehta if (ret) 1834dea846e8SHuazhong Tan dev_err(&hdev->pdev->dev, 1835dea846e8SHuazhong Tan "VF stack reset failed %d.\n", ret); 1836dea846e8SHuazhong Tan } 1837436667d2SSalil Mehta } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1838436667d2SSalil Mehta &hdev->reset_state)) { 1839436667d2SSalil Mehta /* we could be here when either of below happens: 18409b2f3477SWeihang Li * 1. reset was initiated due to watchdog timeout caused by 1841436667d2SSalil Mehta * a. IMP was earlier reset and our TX got choked down and 1842436667d2SSalil Mehta * which resulted in watchdog reacting and inducing VF 1843436667d2SSalil Mehta * reset. This also means our cmdq would be unreliable. 1844436667d2SSalil Mehta * b. problem in TX due to other lower layer(example link 1845436667d2SSalil Mehta * layer not functioning properly etc.) 1846436667d2SSalil Mehta * 2. VF reset might have been initiated due to some config 1847436667d2SSalil Mehta * change. 1848436667d2SSalil Mehta * 1849436667d2SSalil Mehta * NOTE: Theres no clear way to detect above cases than to react 1850436667d2SSalil Mehta * to the response of PF for this reset request. PF will ack the 1851436667d2SSalil Mehta * 1b and 2. cases but we will not get any intimation about 1a 1852436667d2SSalil Mehta * from PF as cmdq would be in unreliable state i.e. mailbox 1853436667d2SSalil Mehta * communication between PF and VF would be broken. 185446ee7350SGuojia Liao * 185546ee7350SGuojia Liao * if we are never geting into pending state it means either: 1856436667d2SSalil Mehta * 1. PF is not receiving our request which could be due to IMP 1857436667d2SSalil Mehta * reset 1858436667d2SSalil Mehta * 2. PF is screwed 1859436667d2SSalil Mehta * We cannot do much for 2. but to check first we can try reset 1860436667d2SSalil Mehta * our PCIe + stack and see if it alleviates the problem. 1861436667d2SSalil Mehta */ 1862d6ad7c53SGuojia Liao if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) { 1863436667d2SSalil Mehta /* prepare for full reset of stack + pcie interface */ 1864dea846e8SHuazhong Tan set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1865436667d2SSalil Mehta 1866436667d2SSalil Mehta /* "defer" schedule the reset task again */ 1867436667d2SSalil Mehta set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1868436667d2SSalil Mehta } else { 1869436667d2SSalil Mehta hdev->reset_attempts++; 1870436667d2SSalil Mehta 1871dea846e8SHuazhong Tan set_bit(hdev->reset_level, &hdev->reset_pending); 1872dea846e8SHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1873436667d2SSalil Mehta } 1874dea846e8SHuazhong Tan hclgevf_reset_task_schedule(hdev); 1875436667d2SSalil Mehta } 187635a1e503SSalil Mehta 187735a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 187835a1e503SSalil Mehta } 187935a1e503SSalil Mehta 1880e2cb1decSSalil Mehta static void hclgevf_mailbox_service_task(struct work_struct *work) 1881e2cb1decSSalil Mehta { 1882e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1883e2cb1decSSalil Mehta 1884e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 1885e2cb1decSSalil Mehta 1886e2cb1decSSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1887e2cb1decSSalil Mehta return; 1888e2cb1decSSalil Mehta 1889e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1890e2cb1decSSalil Mehta 189107a0556aSSalil Mehta hclgevf_mbx_async_handler(hdev); 1892e2cb1decSSalil Mehta 1893e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1894e2cb1decSSalil Mehta } 1895e2cb1decSSalil Mehta 1896a6d818e3SYunsheng Lin static void hclgevf_keep_alive_timer(struct timer_list *t) 1897a6d818e3SYunsheng Lin { 1898a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = from_timer(hdev, t, keep_alive_timer); 1899a6d818e3SYunsheng Lin 1900a6d818e3SYunsheng Lin schedule_work(&hdev->keep_alive_task); 1901b37ce587SYufeng Mo mod_timer(&hdev->keep_alive_timer, jiffies + 1902b37ce587SYufeng Mo HCLGEVF_KEEP_ALIVE_TASK_INTERVAL * HZ); 1903a6d818e3SYunsheng Lin } 1904a6d818e3SYunsheng Lin 1905a6d818e3SYunsheng Lin static void hclgevf_keep_alive_task(struct work_struct *work) 1906a6d818e3SYunsheng Lin { 1907a6d818e3SYunsheng Lin struct hclgevf_dev *hdev; 1908a6d818e3SYunsheng Lin u8 respmsg; 1909a6d818e3SYunsheng Lin int ret; 1910a6d818e3SYunsheng Lin 1911a6d818e3SYunsheng Lin hdev = container_of(work, struct hclgevf_dev, keep_alive_task); 1912c59a85c0SJian Shen 19131416d333SHuazhong Tan if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 1914c59a85c0SJian Shen return; 1915c59a85c0SJian Shen 1916a6d818e3SYunsheng Lin ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL, 191763cbf7a9SYufeng Mo 0, false, &respmsg, sizeof(respmsg)); 1918a6d818e3SYunsheng Lin if (ret) 1919a6d818e3SYunsheng Lin dev_err(&hdev->pdev->dev, 1920a6d818e3SYunsheng Lin "VF sends keep alive cmd failed(=%d)\n", ret); 1921a6d818e3SYunsheng Lin } 1922a6d818e3SYunsheng Lin 1923e2cb1decSSalil Mehta static void hclgevf_service_task(struct work_struct *work) 1924e2cb1decSSalil Mehta { 1925db01afebSliuzhongzhu struct hnae3_handle *handle; 1926e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1927e2cb1decSSalil Mehta 1928b3c3fe8eSYunsheng Lin hdev = container_of(work, struct hclgevf_dev, service_task.work); 1929db01afebSliuzhongzhu handle = &hdev->nic; 1930db01afebSliuzhongzhu 1931db01afebSliuzhongzhu if (hdev->stats_timer >= HCLGEVF_STATS_TIMER_INTERVAL) { 1932db01afebSliuzhongzhu hclgevf_tqps_update_stats(handle); 1933db01afebSliuzhongzhu hdev->stats_timer = 0; 1934db01afebSliuzhongzhu } 1935e2cb1decSSalil Mehta 1936e2cb1decSSalil Mehta /* request the link status from the PF. PF would be able to tell VF 1937e2cb1decSSalil Mehta * about such updates in future so we might remove this later 1938e2cb1decSSalil Mehta */ 1939e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1940e2cb1decSSalil Mehta 19419194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 19429194d18bSliuzhongzhu 1943fe4144d4SJian Shen hclgevf_sync_vlan_filter(hdev); 1944fe4144d4SJian Shen 1945436667d2SSalil Mehta hclgevf_deferred_task_schedule(hdev); 1946436667d2SSalil Mehta 1947e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1948b3c3fe8eSYunsheng Lin 1949b3c3fe8eSYunsheng Lin hclgevf_task_schedule(hdev); 1950e2cb1decSSalil Mehta } 1951e2cb1decSSalil Mehta 1952e2cb1decSSalil Mehta static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1953e2cb1decSSalil Mehta { 1954e2cb1decSSalil Mehta hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1955e2cb1decSSalil Mehta } 1956e2cb1decSSalil Mehta 1957b90fcc5bSHuazhong Tan static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1958b90fcc5bSHuazhong Tan u32 *clearval) 1959e2cb1decSSalil Mehta { 196013050921SHuazhong Tan u32 val, cmdq_stat_reg, rst_ing_reg; 1961e2cb1decSSalil Mehta 1962e2cb1decSSalil Mehta /* fetch the events from their corresponding regs */ 196313050921SHuazhong Tan cmdq_stat_reg = hclgevf_read_dev(&hdev->hw, 196413050921SHuazhong Tan HCLGEVF_VECTOR0_CMDQ_STAT_REG); 1965e2cb1decSSalil Mehta 196613050921SHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 1967b90fcc5bSHuazhong Tan rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1968b90fcc5bSHuazhong Tan dev_info(&hdev->pdev->dev, 1969b90fcc5bSHuazhong Tan "receive reset interrupt 0x%x!\n", rst_ing_reg); 1970b90fcc5bSHuazhong Tan set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1971b90fcc5bSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1972ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 197313050921SHuazhong Tan *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B); 1974c88a6e7dSHuazhong Tan hdev->rst_stats.vf_rst_cnt++; 197572e2fb07SHuazhong Tan /* set up VF hardware reset status, its PF will clear 197672e2fb07SHuazhong Tan * this status when PF has initialized done. 197772e2fb07SHuazhong Tan */ 197872e2fb07SHuazhong Tan val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING); 197972e2fb07SHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING, 198072e2fb07SHuazhong Tan val | HCLGEVF_VF_RST_ING_BIT); 1981b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_RST; 1982b90fcc5bSHuazhong Tan } 1983b90fcc5bSHuazhong Tan 1984e2cb1decSSalil Mehta /* check for vector0 mailbox(=CMDQ RX) event source */ 198513050921SHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 198613050921SHuazhong Tan /* for revision 0x21, clearing interrupt is writing bit 0 198713050921SHuazhong Tan * to the clear register, writing bit 1 means to keep the 198813050921SHuazhong Tan * old value. 198913050921SHuazhong Tan * for revision 0x20, the clear register is a read & write 199013050921SHuazhong Tan * register, so we should just write 0 to the bit we are 199113050921SHuazhong Tan * handling, and keep other bits as cmdq_stat_reg. 199213050921SHuazhong Tan */ 199313050921SHuazhong Tan if (hdev->pdev->revision >= 0x21) 199413050921SHuazhong Tan *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 199513050921SHuazhong Tan else 199613050921SHuazhong Tan *clearval = cmdq_stat_reg & 199713050921SHuazhong Tan ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 199813050921SHuazhong Tan 1999b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_MBX; 2000e2cb1decSSalil Mehta } 2001e2cb1decSSalil Mehta 2002e2cb1decSSalil Mehta dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 2003e2cb1decSSalil Mehta 2004b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_OTHER; 2005e2cb1decSSalil Mehta } 2006e2cb1decSSalil Mehta 2007e2cb1decSSalil Mehta static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 2008e2cb1decSSalil Mehta { 2009e2cb1decSSalil Mehta writel(en ? 1 : 0, vector->addr); 2010e2cb1decSSalil Mehta } 2011e2cb1decSSalil Mehta 2012e2cb1decSSalil Mehta static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 2013e2cb1decSSalil Mehta { 2014b90fcc5bSHuazhong Tan enum hclgevf_evt_cause event_cause; 2015e2cb1decSSalil Mehta struct hclgevf_dev *hdev = data; 2016e2cb1decSSalil Mehta u32 clearval; 2017e2cb1decSSalil Mehta 2018e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 2019b90fcc5bSHuazhong Tan event_cause = hclgevf_check_evt_cause(hdev, &clearval); 2020e2cb1decSSalil Mehta 2021b90fcc5bSHuazhong Tan switch (event_cause) { 2022b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_RST: 2023b90fcc5bSHuazhong Tan hclgevf_reset_task_schedule(hdev); 2024b90fcc5bSHuazhong Tan break; 2025b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_MBX: 202607a0556aSSalil Mehta hclgevf_mbx_handler(hdev); 2027b90fcc5bSHuazhong Tan break; 2028b90fcc5bSHuazhong Tan default: 2029b90fcc5bSHuazhong Tan break; 2030b90fcc5bSHuazhong Tan } 2031e2cb1decSSalil Mehta 2032b90fcc5bSHuazhong Tan if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 2033e2cb1decSSalil Mehta hclgevf_clear_event_cause(hdev, clearval); 2034e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2035b90fcc5bSHuazhong Tan } 2036e2cb1decSSalil Mehta 2037e2cb1decSSalil Mehta return IRQ_HANDLED; 2038e2cb1decSSalil Mehta } 2039e2cb1decSSalil Mehta 2040e2cb1decSSalil Mehta static int hclgevf_configure(struct hclgevf_dev *hdev) 2041e2cb1decSSalil Mehta { 2042e2cb1decSSalil Mehta int ret; 2043e2cb1decSSalil Mehta 204492f11ea1SJian Shen /* get current port based vlan state from PF */ 204592f11ea1SJian Shen ret = hclgevf_get_port_base_vlan_filter_state(hdev); 204692f11ea1SJian Shen if (ret) 204792f11ea1SJian Shen return ret; 204892f11ea1SJian Shen 2049e2cb1decSSalil Mehta /* get queue configuration from PF */ 20506cee6fc3SJian Shen ret = hclgevf_get_queue_info(hdev); 2051e2cb1decSSalil Mehta if (ret) 2052e2cb1decSSalil Mehta return ret; 2053c0425944SPeng Li 2054c0425944SPeng Li /* get queue depth info from PF */ 2055c0425944SPeng Li ret = hclgevf_get_queue_depth(hdev); 2056c0425944SPeng Li if (ret) 2057c0425944SPeng Li return ret; 2058c0425944SPeng Li 20599c3e7130Sliuzhongzhu ret = hclgevf_get_pf_media_type(hdev); 20609c3e7130Sliuzhongzhu if (ret) 20619c3e7130Sliuzhongzhu return ret; 20629c3e7130Sliuzhongzhu 2063e2cb1decSSalil Mehta /* get tc configuration from PF */ 2064e2cb1decSSalil Mehta return hclgevf_get_tc_info(hdev); 2065e2cb1decSSalil Mehta } 2066e2cb1decSSalil Mehta 20677a01c897SSalil Mehta static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 20687a01c897SSalil Mehta { 20697a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 20701154bb26SPeng Li struct hclgevf_dev *hdev; 20717a01c897SSalil Mehta 20727a01c897SSalil Mehta hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 20737a01c897SSalil Mehta if (!hdev) 20747a01c897SSalil Mehta return -ENOMEM; 20757a01c897SSalil Mehta 20767a01c897SSalil Mehta hdev->pdev = pdev; 20777a01c897SSalil Mehta hdev->ae_dev = ae_dev; 20787a01c897SSalil Mehta ae_dev->priv = hdev; 20797a01c897SSalil Mehta 20807a01c897SSalil Mehta return 0; 20817a01c897SSalil Mehta } 20827a01c897SSalil Mehta 2083e2cb1decSSalil Mehta static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 2084e2cb1decSSalil Mehta { 2085e2cb1decSSalil Mehta struct hnae3_handle *roce = &hdev->roce; 2086e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 2087e2cb1decSSalil Mehta 208807acf909SJian Shen roce->rinfo.num_vectors = hdev->num_roce_msix; 2089e2cb1decSSalil Mehta 2090e2cb1decSSalil Mehta if (hdev->num_msi_left < roce->rinfo.num_vectors || 2091e2cb1decSSalil Mehta hdev->num_msi_left == 0) 2092e2cb1decSSalil Mehta return -EINVAL; 2093e2cb1decSSalil Mehta 209407acf909SJian Shen roce->rinfo.base_vector = hdev->roce_base_vector; 2095e2cb1decSSalil Mehta 2096e2cb1decSSalil Mehta roce->rinfo.netdev = nic->kinfo.netdev; 2097e2cb1decSSalil Mehta roce->rinfo.roce_io_base = hdev->hw.io_base; 2098e2cb1decSSalil Mehta 2099e2cb1decSSalil Mehta roce->pdev = nic->pdev; 2100e2cb1decSSalil Mehta roce->ae_algo = nic->ae_algo; 2101e2cb1decSSalil Mehta roce->numa_node_mask = nic->numa_node_mask; 2102e2cb1decSSalil Mehta 2103e2cb1decSSalil Mehta return 0; 2104e2cb1decSSalil Mehta } 2105e2cb1decSSalil Mehta 2106b26a6feaSPeng Li static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 2107b26a6feaSPeng Li { 2108b26a6feaSPeng Li struct hclgevf_cfg_gro_status_cmd *req; 2109b26a6feaSPeng Li struct hclgevf_desc desc; 2110b26a6feaSPeng Li int ret; 2111b26a6feaSPeng Li 2112b26a6feaSPeng Li if (!hnae3_dev_gro_supported(hdev)) 2113b26a6feaSPeng Li return 0; 2114b26a6feaSPeng Li 2115b26a6feaSPeng Li hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 2116b26a6feaSPeng Li false); 2117b26a6feaSPeng Li req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2118b26a6feaSPeng Li 2119b26a6feaSPeng Li req->gro_en = cpu_to_le16(en ? 1 : 0); 2120b26a6feaSPeng Li 2121b26a6feaSPeng Li ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2122b26a6feaSPeng Li if (ret) 2123b26a6feaSPeng Li dev_err(&hdev->pdev->dev, 2124b26a6feaSPeng Li "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2125b26a6feaSPeng Li 2126b26a6feaSPeng Li return ret; 2127b26a6feaSPeng Li } 2128b26a6feaSPeng Li 2129e2cb1decSSalil Mehta static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2130e2cb1decSSalil Mehta { 2131e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 21324093d1a2SGuangbin Huang int ret; 21334093d1a2SGuangbin Huang u32 i; 2134e2cb1decSSalil Mehta 21354093d1a2SGuangbin Huang rss_cfg->rss_size = hdev->nic.kinfo.rss_size; 2136e2cb1decSSalil Mehta 2137374ad291SJian Shen if (hdev->pdev->revision >= 0x21) { 2138472d7eceSJian Shen rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 2139472d7eceSJian Shen memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 2140374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 2141374ad291SJian Shen 2142374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 2143374ad291SJian Shen rss_cfg->rss_hash_key); 2144374ad291SJian Shen if (ret) 2145374ad291SJian Shen return ret; 2146d97b3072SJian Shen 2147d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = 2148d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2149d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = 2150d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2151d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = 2152d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2153d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = 2154d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2155d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = 2156d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2157d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = 2158d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2159d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = 2160d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2161d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = 2162d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2163d97b3072SJian Shen 2164d97b3072SJian Shen ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 2165d97b3072SJian Shen if (ret) 2166d97b3072SJian Shen return ret; 2167374ad291SJian Shen } 2168374ad291SJian Shen 21699b2f3477SWeihang Li /* Initialize RSS indirect table */ 2170e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 21714093d1a2SGuangbin Huang rss_cfg->rss_indirection_tbl[i] = i % rss_cfg->rss_size; 2172e2cb1decSSalil Mehta 2173e2cb1decSSalil Mehta ret = hclgevf_set_rss_indir_table(hdev); 2174e2cb1decSSalil Mehta if (ret) 2175e2cb1decSSalil Mehta return ret; 2176e2cb1decSSalil Mehta 21774093d1a2SGuangbin Huang return hclgevf_set_rss_tc_mode(hdev, rss_cfg->rss_size); 2178e2cb1decSSalil Mehta } 2179e2cb1decSSalil Mehta 2180e2cb1decSSalil Mehta static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2181e2cb1decSSalil Mehta { 2182e2cb1decSSalil Mehta return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2183e2cb1decSSalil Mehta false); 2184e2cb1decSSalil Mehta } 2185e2cb1decSSalil Mehta 21868cdb992fSJian Shen static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 21878cdb992fSJian Shen { 21888cdb992fSJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 21898cdb992fSJian Shen 21908cdb992fSJian Shen if (enable) { 2191b3c3fe8eSYunsheng Lin hclgevf_task_schedule(hdev); 21928cdb992fSJian Shen } else { 2193b3c3fe8eSYunsheng Lin set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2194b3c3fe8eSYunsheng Lin cancel_delayed_work_sync(&hdev->service_task); 21958cdb992fSJian Shen clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 21968cdb992fSJian Shen } 21978cdb992fSJian Shen } 21988cdb992fSJian Shen 2199e2cb1decSSalil Mehta static int hclgevf_ae_start(struct hnae3_handle *handle) 2200e2cb1decSSalil Mehta { 2201e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2202e2cb1decSSalil Mehta 2203e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 2204e2cb1decSSalil Mehta 2205e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 2206e2cb1decSSalil Mehta 22079194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 22089194d18bSliuzhongzhu 2209e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2210e2cb1decSSalil Mehta 2211e2cb1decSSalil Mehta return 0; 2212e2cb1decSSalil Mehta } 2213e2cb1decSSalil Mehta 2214e2cb1decSSalil Mehta static void hclgevf_ae_stop(struct hnae3_handle *handle) 2215e2cb1decSSalil Mehta { 2216e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 221739cfbc9cSHuazhong Tan int i; 2218e2cb1decSSalil Mehta 22192f7e4896SFuyun Liang set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 22202f7e4896SFuyun Liang 2221146e92c1SHuazhong Tan if (hdev->reset_type != HNAE3_VF_RESET) 222239cfbc9cSHuazhong Tan for (i = 0; i < handle->kinfo.num_tqps; i++) 2223146e92c1SHuazhong Tan if (hclgevf_reset_tqp(handle, i)) 2224146e92c1SHuazhong Tan break; 222539cfbc9cSHuazhong Tan 2226e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 22278cc6c1f7SFuyun Liang hclgevf_update_link_status(hdev, 0); 2228e2cb1decSSalil Mehta } 2229e2cb1decSSalil Mehta 2230a6d818e3SYunsheng Lin static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2231a6d818e3SYunsheng Lin { 2232a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2233a6d818e3SYunsheng Lin u8 msg_data; 2234a6d818e3SYunsheng Lin 2235a6d818e3SYunsheng Lin msg_data = alive ? 1 : 0; 2236a6d818e3SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE, 2237a6d818e3SYunsheng Lin 0, &msg_data, 1, false, NULL, 0); 2238a6d818e3SYunsheng Lin } 2239a6d818e3SYunsheng Lin 2240a6d818e3SYunsheng Lin static int hclgevf_client_start(struct hnae3_handle *handle) 2241a6d818e3SYunsheng Lin { 2242a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2243e233516eSHuazhong Tan int ret; 2244e233516eSHuazhong Tan 2245e233516eSHuazhong Tan ret = hclgevf_set_alive(handle, true); 2246e233516eSHuazhong Tan if (ret) 2247e233516eSHuazhong Tan return ret; 2248a6d818e3SYunsheng Lin 2249b37ce587SYufeng Mo mod_timer(&hdev->keep_alive_timer, jiffies + 2250b37ce587SYufeng Mo HCLGEVF_KEEP_ALIVE_TASK_INTERVAL * HZ); 2251e233516eSHuazhong Tan 2252e233516eSHuazhong Tan return 0; 2253a6d818e3SYunsheng Lin } 2254a6d818e3SYunsheng Lin 2255a6d818e3SYunsheng Lin static void hclgevf_client_stop(struct hnae3_handle *handle) 2256a6d818e3SYunsheng Lin { 2257a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2258a6d818e3SYunsheng Lin int ret; 2259a6d818e3SYunsheng Lin 2260a6d818e3SYunsheng Lin ret = hclgevf_set_alive(handle, false); 2261a6d818e3SYunsheng Lin if (ret) 2262a6d818e3SYunsheng Lin dev_warn(&hdev->pdev->dev, 2263a6d818e3SYunsheng Lin "%s failed %d\n", __func__, ret); 2264a6d818e3SYunsheng Lin 2265a6d818e3SYunsheng Lin del_timer_sync(&hdev->keep_alive_timer); 2266a6d818e3SYunsheng Lin cancel_work_sync(&hdev->keep_alive_task); 2267a6d818e3SYunsheng Lin } 2268a6d818e3SYunsheng Lin 2269e2cb1decSSalil Mehta static void hclgevf_state_init(struct hclgevf_dev *hdev) 2270e2cb1decSSalil Mehta { 2271e2cb1decSSalil Mehta /* setup tasks for the MBX */ 2272e2cb1decSSalil Mehta INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 2273e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2274e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2275e2cb1decSSalil Mehta 2276b3c3fe8eSYunsheng Lin INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task); 2277e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2278e2cb1decSSalil Mehta 227935a1e503SSalil Mehta INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task); 228035a1e503SSalil Mehta 2281e2cb1decSSalil Mehta mutex_init(&hdev->mbx_resp.mbx_mutex); 2282e2cb1decSSalil Mehta 2283e2cb1decSSalil Mehta /* bring the device down */ 2284e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2285e2cb1decSSalil Mehta } 2286e2cb1decSSalil Mehta 2287e2cb1decSSalil Mehta static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2288e2cb1decSSalil Mehta { 2289e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2290acfc3d55SHuazhong Tan set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2291e2cb1decSSalil Mehta 2292e233516eSHuazhong Tan if (hdev->keep_alive_timer.function) 2293e233516eSHuazhong Tan del_timer_sync(&hdev->keep_alive_timer); 2294e233516eSHuazhong Tan if (hdev->keep_alive_task.func) 2295e233516eSHuazhong Tan cancel_work_sync(&hdev->keep_alive_task); 2296b3c3fe8eSYunsheng Lin if (hdev->service_task.work.func) 2297b3c3fe8eSYunsheng Lin cancel_delayed_work_sync(&hdev->service_task); 2298e2cb1decSSalil Mehta if (hdev->mbx_service_task.func) 2299e2cb1decSSalil Mehta cancel_work_sync(&hdev->mbx_service_task); 230035a1e503SSalil Mehta if (hdev->rst_service_task.func) 230135a1e503SSalil Mehta cancel_work_sync(&hdev->rst_service_task); 2302e2cb1decSSalil Mehta 2303e2cb1decSSalil Mehta mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2304e2cb1decSSalil Mehta } 2305e2cb1decSSalil Mehta 2306e2cb1decSSalil Mehta static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2307e2cb1decSSalil Mehta { 2308e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2309e2cb1decSSalil Mehta int vectors; 2310e2cb1decSSalil Mehta int i; 2311e2cb1decSSalil Mehta 2312580a05f9SYonglong Liu if (hnae3_dev_roce_supported(hdev)) 231307acf909SJian Shen vectors = pci_alloc_irq_vectors(pdev, 231407acf909SJian Shen hdev->roce_base_msix_offset + 1, 231507acf909SJian Shen hdev->num_msi, 231607acf909SJian Shen PCI_IRQ_MSIX); 231707acf909SJian Shen else 2318580a05f9SYonglong Liu vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2319580a05f9SYonglong Liu hdev->num_msi, 2320e2cb1decSSalil Mehta PCI_IRQ_MSI | PCI_IRQ_MSIX); 232107acf909SJian Shen 2322e2cb1decSSalil Mehta if (vectors < 0) { 2323e2cb1decSSalil Mehta dev_err(&pdev->dev, 2324e2cb1decSSalil Mehta "failed(%d) to allocate MSI/MSI-X vectors\n", 2325e2cb1decSSalil Mehta vectors); 2326e2cb1decSSalil Mehta return vectors; 2327e2cb1decSSalil Mehta } 2328e2cb1decSSalil Mehta if (vectors < hdev->num_msi) 2329e2cb1decSSalil Mehta dev_warn(&hdev->pdev->dev, 2330adcf738bSGuojia Liao "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2331e2cb1decSSalil Mehta hdev->num_msi, vectors); 2332e2cb1decSSalil Mehta 2333e2cb1decSSalil Mehta hdev->num_msi = vectors; 2334e2cb1decSSalil Mehta hdev->num_msi_left = vectors; 2335580a05f9SYonglong Liu 2336e2cb1decSSalil Mehta hdev->base_msi_vector = pdev->irq; 233707acf909SJian Shen hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2338e2cb1decSSalil Mehta 2339e2cb1decSSalil Mehta hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2340e2cb1decSSalil Mehta sizeof(u16), GFP_KERNEL); 2341e2cb1decSSalil Mehta if (!hdev->vector_status) { 2342e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2343e2cb1decSSalil Mehta return -ENOMEM; 2344e2cb1decSSalil Mehta } 2345e2cb1decSSalil Mehta 2346e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 2347e2cb1decSSalil Mehta hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2348e2cb1decSSalil Mehta 2349e2cb1decSSalil Mehta hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2350e2cb1decSSalil Mehta sizeof(int), GFP_KERNEL); 2351e2cb1decSSalil Mehta if (!hdev->vector_irq) { 2352862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2353e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2354e2cb1decSSalil Mehta return -ENOMEM; 2355e2cb1decSSalil Mehta } 2356e2cb1decSSalil Mehta 2357e2cb1decSSalil Mehta return 0; 2358e2cb1decSSalil Mehta } 2359e2cb1decSSalil Mehta 2360e2cb1decSSalil Mehta static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2361e2cb1decSSalil Mehta { 2362e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2363e2cb1decSSalil Mehta 2364862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2365862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_irq); 2366e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2367e2cb1decSSalil Mehta } 2368e2cb1decSSalil Mehta 2369e2cb1decSSalil Mehta static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2370e2cb1decSSalil Mehta { 2371cdd332acSGuojia Liao int ret; 2372e2cb1decSSalil Mehta 2373e2cb1decSSalil Mehta hclgevf_get_misc_vector(hdev); 2374e2cb1decSSalil Mehta 2375e2cb1decSSalil Mehta ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2376e2cb1decSSalil Mehta 0, "hclgevf_cmd", hdev); 2377e2cb1decSSalil Mehta if (ret) { 2378e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2379e2cb1decSSalil Mehta hdev->misc_vector.vector_irq); 2380e2cb1decSSalil Mehta return ret; 2381e2cb1decSSalil Mehta } 2382e2cb1decSSalil Mehta 23831819e409SXi Wang hclgevf_clear_event_cause(hdev, 0); 23841819e409SXi Wang 2385e2cb1decSSalil Mehta /* enable misc. vector(vector 0) */ 2386e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2387e2cb1decSSalil Mehta 2388e2cb1decSSalil Mehta return ret; 2389e2cb1decSSalil Mehta } 2390e2cb1decSSalil Mehta 2391e2cb1decSSalil Mehta static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2392e2cb1decSSalil Mehta { 2393e2cb1decSSalil Mehta /* disable misc vector(vector 0) */ 2394e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 23951819e409SXi Wang synchronize_irq(hdev->misc_vector.vector_irq); 2396e2cb1decSSalil Mehta free_irq(hdev->misc_vector.vector_irq, hdev); 2397e2cb1decSSalil Mehta hclgevf_free_vector(hdev, 0); 2398e2cb1decSSalil Mehta } 2399e2cb1decSSalil Mehta 2400bb87be87SYonglong Liu static void hclgevf_info_show(struct hclgevf_dev *hdev) 2401bb87be87SYonglong Liu { 2402bb87be87SYonglong Liu struct device *dev = &hdev->pdev->dev; 2403bb87be87SYonglong Liu 2404bb87be87SYonglong Liu dev_info(dev, "VF info begin:\n"); 2405bb87be87SYonglong Liu 2406adcf738bSGuojia Liao dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 2407adcf738bSGuojia Liao dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 2408adcf738bSGuojia Liao dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 2409adcf738bSGuojia Liao dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 2410adcf738bSGuojia Liao dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 2411adcf738bSGuojia Liao dev_info(dev, "PF media type of this VF: %u\n", 2412bb87be87SYonglong Liu hdev->hw.mac.media_type); 2413bb87be87SYonglong Liu 2414bb87be87SYonglong Liu dev_info(dev, "VF info end.\n"); 2415bb87be87SYonglong Liu } 2416bb87be87SYonglong Liu 24171db58f86SHuazhong Tan static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 24181db58f86SHuazhong Tan struct hnae3_client *client) 24191db58f86SHuazhong Tan { 24201db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 24211db58f86SHuazhong Tan int ret; 24221db58f86SHuazhong Tan 24231db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->nic); 24241db58f86SHuazhong Tan if (ret) 24251db58f86SHuazhong Tan return ret; 24261db58f86SHuazhong Tan 24271db58f86SHuazhong Tan set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 24281db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 24291db58f86SHuazhong Tan 24301db58f86SHuazhong Tan if (netif_msg_drv(&hdev->nic)) 24311db58f86SHuazhong Tan hclgevf_info_show(hdev); 24321db58f86SHuazhong Tan 24331db58f86SHuazhong Tan return 0; 24341db58f86SHuazhong Tan } 24351db58f86SHuazhong Tan 24361db58f86SHuazhong Tan static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 24371db58f86SHuazhong Tan struct hnae3_client *client) 24381db58f86SHuazhong Tan { 24391db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 24401db58f86SHuazhong Tan int ret; 24411db58f86SHuazhong Tan 24421db58f86SHuazhong Tan if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 24431db58f86SHuazhong Tan !hdev->nic_client) 24441db58f86SHuazhong Tan return 0; 24451db58f86SHuazhong Tan 24461db58f86SHuazhong Tan ret = hclgevf_init_roce_base_info(hdev); 24471db58f86SHuazhong Tan if (ret) 24481db58f86SHuazhong Tan return ret; 24491db58f86SHuazhong Tan 24501db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->roce); 24511db58f86SHuazhong Tan if (ret) 24521db58f86SHuazhong Tan return ret; 24531db58f86SHuazhong Tan 24541db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 24551db58f86SHuazhong Tan 24561db58f86SHuazhong Tan return 0; 24571db58f86SHuazhong Tan } 24581db58f86SHuazhong Tan 2459e718a93fSPeng Li static int hclgevf_init_client_instance(struct hnae3_client *client, 2460e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2461e2cb1decSSalil Mehta { 2462e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2463e2cb1decSSalil Mehta int ret; 2464e2cb1decSSalil Mehta 2465e2cb1decSSalil Mehta switch (client->type) { 2466e2cb1decSSalil Mehta case HNAE3_CLIENT_KNIC: 2467e2cb1decSSalil Mehta hdev->nic_client = client; 2468e2cb1decSSalil Mehta hdev->nic.client = client; 2469e2cb1decSSalil Mehta 24701db58f86SHuazhong Tan ret = hclgevf_init_nic_client_instance(ae_dev, client); 2471e2cb1decSSalil Mehta if (ret) 247249dd8054SJian Shen goto clear_nic; 2473e2cb1decSSalil Mehta 24741db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, 24751db58f86SHuazhong Tan hdev->roce_client); 2476e2cb1decSSalil Mehta if (ret) 247749dd8054SJian Shen goto clear_roce; 2478d9f28fc2SJian Shen 2479e2cb1decSSalil Mehta break; 2480e2cb1decSSalil Mehta case HNAE3_CLIENT_ROCE: 2481544a7bcdSLijun Ou if (hnae3_dev_roce_supported(hdev)) { 2482e2cb1decSSalil Mehta hdev->roce_client = client; 2483e2cb1decSSalil Mehta hdev->roce.client = client; 2484544a7bcdSLijun Ou } 2485e2cb1decSSalil Mehta 24861db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, client); 2487e2cb1decSSalil Mehta if (ret) 248849dd8054SJian Shen goto clear_roce; 2489e2cb1decSSalil Mehta 2490fa7a4bd5SJian Shen break; 2491fa7a4bd5SJian Shen default: 2492fa7a4bd5SJian Shen return -EINVAL; 2493e2cb1decSSalil Mehta } 2494e2cb1decSSalil Mehta 2495e2cb1decSSalil Mehta return 0; 249649dd8054SJian Shen 249749dd8054SJian Shen clear_nic: 249849dd8054SJian Shen hdev->nic_client = NULL; 249949dd8054SJian Shen hdev->nic.client = NULL; 250049dd8054SJian Shen return ret; 250149dd8054SJian Shen clear_roce: 250249dd8054SJian Shen hdev->roce_client = NULL; 250349dd8054SJian Shen hdev->roce.client = NULL; 250449dd8054SJian Shen return ret; 2505e2cb1decSSalil Mehta } 2506e2cb1decSSalil Mehta 2507e718a93fSPeng Li static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2508e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2509e2cb1decSSalil Mehta { 2510e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2511e718a93fSPeng Li 2512e2cb1decSSalil Mehta /* un-init roce, if it exists */ 251349dd8054SJian Shen if (hdev->roce_client) { 2514e2cb1decSSalil Mehta hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 251549dd8054SJian Shen hdev->roce_client = NULL; 251649dd8054SJian Shen hdev->roce.client = NULL; 251749dd8054SJian Shen } 2518e2cb1decSSalil Mehta 2519e2cb1decSSalil Mehta /* un-init nic/unic, if this was not called by roce client */ 252049dd8054SJian Shen if (client->ops->uninit_instance && hdev->nic_client && 252149dd8054SJian Shen client->type != HNAE3_CLIENT_ROCE) { 252225d1817cSHuazhong Tan clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 252325d1817cSHuazhong Tan 2524e2cb1decSSalil Mehta client->ops->uninit_instance(&hdev->nic, 0); 252549dd8054SJian Shen hdev->nic_client = NULL; 252649dd8054SJian Shen hdev->nic.client = NULL; 252749dd8054SJian Shen } 2528e2cb1decSSalil Mehta } 2529e2cb1decSSalil Mehta 2530e2cb1decSSalil Mehta static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2531e2cb1decSSalil Mehta { 2532e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2533e2cb1decSSalil Mehta struct hclgevf_hw *hw; 2534e2cb1decSSalil Mehta int ret; 2535e2cb1decSSalil Mehta 2536e2cb1decSSalil Mehta ret = pci_enable_device(pdev); 2537e2cb1decSSalil Mehta if (ret) { 2538e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed to enable PCI device\n"); 25393e249d3bSFuyun Liang return ret; 2540e2cb1decSSalil Mehta } 2541e2cb1decSSalil Mehta 2542e2cb1decSSalil Mehta ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2543e2cb1decSSalil Mehta if (ret) { 2544e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2545e2cb1decSSalil Mehta goto err_disable_device; 2546e2cb1decSSalil Mehta } 2547e2cb1decSSalil Mehta 2548e2cb1decSSalil Mehta ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2549e2cb1decSSalil Mehta if (ret) { 2550e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2551e2cb1decSSalil Mehta goto err_disable_device; 2552e2cb1decSSalil Mehta } 2553e2cb1decSSalil Mehta 2554e2cb1decSSalil Mehta pci_set_master(pdev); 2555e2cb1decSSalil Mehta hw = &hdev->hw; 2556e2cb1decSSalil Mehta hw->hdev = hdev; 25572e1ea493SPeng Li hw->io_base = pci_iomap(pdev, 2, 0); 2558e2cb1decSSalil Mehta if (!hw->io_base) { 2559e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't map configuration register space\n"); 2560e2cb1decSSalil Mehta ret = -ENOMEM; 2561e2cb1decSSalil Mehta goto err_clr_master; 2562e2cb1decSSalil Mehta } 2563e2cb1decSSalil Mehta 2564e2cb1decSSalil Mehta return 0; 2565e2cb1decSSalil Mehta 2566e2cb1decSSalil Mehta err_clr_master: 2567e2cb1decSSalil Mehta pci_clear_master(pdev); 2568e2cb1decSSalil Mehta pci_release_regions(pdev); 2569e2cb1decSSalil Mehta err_disable_device: 2570e2cb1decSSalil Mehta pci_disable_device(pdev); 25713e249d3bSFuyun Liang 2572e2cb1decSSalil Mehta return ret; 2573e2cb1decSSalil Mehta } 2574e2cb1decSSalil Mehta 2575e2cb1decSSalil Mehta static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2576e2cb1decSSalil Mehta { 2577e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2578e2cb1decSSalil Mehta 2579e2cb1decSSalil Mehta pci_iounmap(pdev, hdev->hw.io_base); 2580e2cb1decSSalil Mehta pci_clear_master(pdev); 2581e2cb1decSSalil Mehta pci_release_regions(pdev); 2582e2cb1decSSalil Mehta pci_disable_device(pdev); 2583e2cb1decSSalil Mehta } 2584e2cb1decSSalil Mehta 258507acf909SJian Shen static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 258607acf909SJian Shen { 258707acf909SJian Shen struct hclgevf_query_res_cmd *req; 258807acf909SJian Shen struct hclgevf_desc desc; 258907acf909SJian Shen int ret; 259007acf909SJian Shen 259107acf909SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 259207acf909SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 259307acf909SJian Shen if (ret) { 259407acf909SJian Shen dev_err(&hdev->pdev->dev, 259507acf909SJian Shen "query vf resource failed, ret = %d.\n", ret); 259607acf909SJian Shen return ret; 259707acf909SJian Shen } 259807acf909SJian Shen 259907acf909SJian Shen req = (struct hclgevf_query_res_cmd *)desc.data; 260007acf909SJian Shen 2601580a05f9SYonglong Liu if (hnae3_dev_roce_supported(hdev)) { 260207acf909SJian Shen hdev->roce_base_msix_offset = 260307acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 260407acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_M, 260507acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_S); 260607acf909SJian Shen hdev->num_roce_msix = 260707acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 260807acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 260907acf909SJian Shen 2610580a05f9SYonglong Liu /* nic's msix numbers is always equals to the roce's. */ 2611580a05f9SYonglong Liu hdev->num_nic_msix = hdev->num_roce_msix; 2612580a05f9SYonglong Liu 261307acf909SJian Shen /* VF should have NIC vectors and Roce vectors, NIC vectors 261407acf909SJian Shen * are queued before Roce vectors. The offset is fixed to 64. 261507acf909SJian Shen */ 261607acf909SJian Shen hdev->num_msi = hdev->num_roce_msix + 261707acf909SJian Shen hdev->roce_base_msix_offset; 261807acf909SJian Shen } else { 261907acf909SJian Shen hdev->num_msi = 262007acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 262107acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2622580a05f9SYonglong Liu 2623580a05f9SYonglong Liu hdev->num_nic_msix = hdev->num_msi; 2624580a05f9SYonglong Liu } 2625580a05f9SYonglong Liu 2626580a05f9SYonglong Liu if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) { 2627580a05f9SYonglong Liu dev_err(&hdev->pdev->dev, 2628580a05f9SYonglong Liu "Just %u msi resources, not enough for vf(min:2).\n", 2629580a05f9SYonglong Liu hdev->num_nic_msix); 2630580a05f9SYonglong Liu return -EINVAL; 263107acf909SJian Shen } 263207acf909SJian Shen 263307acf909SJian Shen return 0; 263407acf909SJian Shen } 263507acf909SJian Shen 2636862d969aSHuazhong Tan static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2637862d969aSHuazhong Tan { 2638862d969aSHuazhong Tan struct pci_dev *pdev = hdev->pdev; 2639862d969aSHuazhong Tan int ret = 0; 2640862d969aSHuazhong Tan 2641862d969aSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2642862d969aSHuazhong Tan test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2643862d969aSHuazhong Tan hclgevf_misc_irq_uninit(hdev); 2644862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2645862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2646862d969aSHuazhong Tan } 2647862d969aSHuazhong Tan 2648862d969aSHuazhong Tan if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2649862d969aSHuazhong Tan pci_set_master(pdev); 2650862d969aSHuazhong Tan ret = hclgevf_init_msi(hdev); 2651862d969aSHuazhong Tan if (ret) { 2652862d969aSHuazhong Tan dev_err(&pdev->dev, 2653862d969aSHuazhong Tan "failed(%d) to init MSI/MSI-X\n", ret); 2654862d969aSHuazhong Tan return ret; 2655862d969aSHuazhong Tan } 2656862d969aSHuazhong Tan 2657862d969aSHuazhong Tan ret = hclgevf_misc_irq_init(hdev); 2658862d969aSHuazhong Tan if (ret) { 2659862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2660862d969aSHuazhong Tan dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2661862d969aSHuazhong Tan ret); 2662862d969aSHuazhong Tan return ret; 2663862d969aSHuazhong Tan } 2664862d969aSHuazhong Tan 2665862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2666862d969aSHuazhong Tan } 2667862d969aSHuazhong Tan 2668862d969aSHuazhong Tan return ret; 2669862d969aSHuazhong Tan } 2670862d969aSHuazhong Tan 26719c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2672e2cb1decSSalil Mehta { 26737a01c897SSalil Mehta struct pci_dev *pdev = hdev->pdev; 2674e2cb1decSSalil Mehta int ret; 2675e2cb1decSSalil Mehta 2676862d969aSHuazhong Tan ret = hclgevf_pci_reset(hdev); 2677862d969aSHuazhong Tan if (ret) { 2678862d969aSHuazhong Tan dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2679862d969aSHuazhong Tan return ret; 2680862d969aSHuazhong Tan } 2681862d969aSHuazhong Tan 26829c6f7085SHuazhong Tan ret = hclgevf_cmd_init(hdev); 26839c6f7085SHuazhong Tan if (ret) { 26849c6f7085SHuazhong Tan dev_err(&pdev->dev, "cmd failed %d\n", ret); 26859c6f7085SHuazhong Tan return ret; 26867a01c897SSalil Mehta } 2687e2cb1decSSalil Mehta 26889c6f7085SHuazhong Tan ret = hclgevf_rss_init_hw(hdev); 26899c6f7085SHuazhong Tan if (ret) { 26909c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 26919c6f7085SHuazhong Tan "failed(%d) to initialize RSS\n", ret); 26929c6f7085SHuazhong Tan return ret; 26939c6f7085SHuazhong Tan } 26949c6f7085SHuazhong Tan 2695b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2696b26a6feaSPeng Li if (ret) 2697b26a6feaSPeng Li return ret; 2698b26a6feaSPeng Li 26999c6f7085SHuazhong Tan ret = hclgevf_init_vlan_config(hdev); 27009c6f7085SHuazhong Tan if (ret) { 27019c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 27029c6f7085SHuazhong Tan "failed(%d) to initialize VLAN config\n", ret); 27039c6f7085SHuazhong Tan return ret; 27049c6f7085SHuazhong Tan } 27059c6f7085SHuazhong Tan 27069c6f7085SHuazhong Tan dev_info(&hdev->pdev->dev, "Reset done\n"); 27079c6f7085SHuazhong Tan 27089c6f7085SHuazhong Tan return 0; 27099c6f7085SHuazhong Tan } 27109c6f7085SHuazhong Tan 27119c6f7085SHuazhong Tan static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 27129c6f7085SHuazhong Tan { 27139c6f7085SHuazhong Tan struct pci_dev *pdev = hdev->pdev; 27149c6f7085SHuazhong Tan int ret; 27159c6f7085SHuazhong Tan 2716e2cb1decSSalil Mehta ret = hclgevf_pci_init(hdev); 2717e2cb1decSSalil Mehta if (ret) { 2718e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI initialization failed\n"); 2719e2cb1decSSalil Mehta return ret; 2720e2cb1decSSalil Mehta } 2721e2cb1decSSalil Mehta 27228b0195a3SHuazhong Tan ret = hclgevf_cmd_queue_init(hdev); 27238b0195a3SHuazhong Tan if (ret) { 27248b0195a3SHuazhong Tan dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret); 27258b0195a3SHuazhong Tan goto err_cmd_queue_init; 27268b0195a3SHuazhong Tan } 27278b0195a3SHuazhong Tan 2728eddf0462SYunsheng Lin ret = hclgevf_cmd_init(hdev); 2729eddf0462SYunsheng Lin if (ret) 2730eddf0462SYunsheng Lin goto err_cmd_init; 2731eddf0462SYunsheng Lin 273207acf909SJian Shen /* Get vf resource */ 273307acf909SJian Shen ret = hclgevf_query_vf_resource(hdev); 273407acf909SJian Shen if (ret) { 273507acf909SJian Shen dev_err(&hdev->pdev->dev, 273607acf909SJian Shen "Query vf status error, ret = %d.\n", ret); 27378b0195a3SHuazhong Tan goto err_cmd_init; 273807acf909SJian Shen } 273907acf909SJian Shen 274007acf909SJian Shen ret = hclgevf_init_msi(hdev); 274107acf909SJian Shen if (ret) { 274207acf909SJian Shen dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 27438b0195a3SHuazhong Tan goto err_cmd_init; 274407acf909SJian Shen } 274507acf909SJian Shen 274607acf909SJian Shen hclgevf_state_init(hdev); 2747dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 274807acf909SJian Shen 2749e2cb1decSSalil Mehta ret = hclgevf_misc_irq_init(hdev); 2750e2cb1decSSalil Mehta if (ret) { 2751e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2752e2cb1decSSalil Mehta ret); 2753e2cb1decSSalil Mehta goto err_misc_irq_init; 2754e2cb1decSSalil Mehta } 2755e2cb1decSSalil Mehta 2756862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2757862d969aSHuazhong Tan 2758e2cb1decSSalil Mehta ret = hclgevf_configure(hdev); 2759e2cb1decSSalil Mehta if (ret) { 2760e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2761e2cb1decSSalil Mehta goto err_config; 2762e2cb1decSSalil Mehta } 2763e2cb1decSSalil Mehta 2764e2cb1decSSalil Mehta ret = hclgevf_alloc_tqps(hdev); 2765e2cb1decSSalil Mehta if (ret) { 2766e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2767e2cb1decSSalil Mehta goto err_config; 2768e2cb1decSSalil Mehta } 2769e2cb1decSSalil Mehta 2770e2cb1decSSalil Mehta ret = hclgevf_set_handle_info(hdev); 2771e2cb1decSSalil Mehta if (ret) { 2772e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 2773e2cb1decSSalil Mehta goto err_config; 2774e2cb1decSSalil Mehta } 2775e2cb1decSSalil Mehta 2776b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2777b26a6feaSPeng Li if (ret) 2778b26a6feaSPeng Li goto err_config; 2779b26a6feaSPeng Li 2780e2cb1decSSalil Mehta /* Initialize RSS for this VF */ 2781e2cb1decSSalil Mehta ret = hclgevf_rss_init_hw(hdev); 2782e2cb1decSSalil Mehta if (ret) { 2783e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2784e2cb1decSSalil Mehta "failed(%d) to initialize RSS\n", ret); 2785e2cb1decSSalil Mehta goto err_config; 2786e2cb1decSSalil Mehta } 2787e2cb1decSSalil Mehta 2788e2cb1decSSalil Mehta ret = hclgevf_init_vlan_config(hdev); 2789e2cb1decSSalil Mehta if (ret) { 2790e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2791e2cb1decSSalil Mehta "failed(%d) to initialize VLAN config\n", ret); 2792e2cb1decSSalil Mehta goto err_config; 2793e2cb1decSSalil Mehta } 2794e2cb1decSSalil Mehta 27950742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 279608d80a4cSHuazhong Tan dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 279708d80a4cSHuazhong Tan HCLGEVF_DRIVER_NAME); 2798e2cb1decSSalil Mehta 2799e2cb1decSSalil Mehta return 0; 2800e2cb1decSSalil Mehta 2801e2cb1decSSalil Mehta err_config: 2802e2cb1decSSalil Mehta hclgevf_misc_irq_uninit(hdev); 2803e2cb1decSSalil Mehta err_misc_irq_init: 2804e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2805e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 280607acf909SJian Shen err_cmd_init: 28078b0195a3SHuazhong Tan hclgevf_cmd_uninit(hdev); 28088b0195a3SHuazhong Tan err_cmd_queue_init: 2809e2cb1decSSalil Mehta hclgevf_pci_uninit(hdev); 2810862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2811e2cb1decSSalil Mehta return ret; 2812e2cb1decSSalil Mehta } 2813e2cb1decSSalil Mehta 28147a01c897SSalil Mehta static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2815e2cb1decSSalil Mehta { 2816e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2817862d969aSHuazhong Tan 2818862d969aSHuazhong Tan if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2819eddf0462SYunsheng Lin hclgevf_misc_irq_uninit(hdev); 2820e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 28217a01c897SSalil Mehta } 28227a01c897SSalil Mehta 2823e3338205SHuazhong Tan hclgevf_pci_uninit(hdev); 2824862d969aSHuazhong Tan hclgevf_cmd_uninit(hdev); 2825862d969aSHuazhong Tan } 2826862d969aSHuazhong Tan 28277a01c897SSalil Mehta static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 28287a01c897SSalil Mehta { 28297a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 2830a6d818e3SYunsheng Lin struct hclgevf_dev *hdev; 28317a01c897SSalil Mehta int ret; 28327a01c897SSalil Mehta 28337a01c897SSalil Mehta ret = hclgevf_alloc_hdev(ae_dev); 28347a01c897SSalil Mehta if (ret) { 28357a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device allocation failed\n"); 28367a01c897SSalil Mehta return ret; 28377a01c897SSalil Mehta } 28387a01c897SSalil Mehta 28397a01c897SSalil Mehta ret = hclgevf_init_hdev(ae_dev->priv); 2840a6d818e3SYunsheng Lin if (ret) { 28417a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device initialization failed\n"); 28427a01c897SSalil Mehta return ret; 28437a01c897SSalil Mehta } 28447a01c897SSalil Mehta 2845a6d818e3SYunsheng Lin hdev = ae_dev->priv; 2846a6d818e3SYunsheng Lin timer_setup(&hdev->keep_alive_timer, hclgevf_keep_alive_timer, 0); 2847a6d818e3SYunsheng Lin INIT_WORK(&hdev->keep_alive_task, hclgevf_keep_alive_task); 2848a6d818e3SYunsheng Lin 2849a6d818e3SYunsheng Lin return 0; 2850a6d818e3SYunsheng Lin } 2851a6d818e3SYunsheng Lin 28527a01c897SSalil Mehta static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 28537a01c897SSalil Mehta { 28547a01c897SSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 28557a01c897SSalil Mehta 28567a01c897SSalil Mehta hclgevf_uninit_hdev(hdev); 2857e2cb1decSSalil Mehta ae_dev->priv = NULL; 2858e2cb1decSSalil Mehta } 2859e2cb1decSSalil Mehta 2860849e4607SPeng Li static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2861849e4607SPeng Li { 2862849e4607SPeng Li struct hnae3_handle *nic = &hdev->nic; 2863849e4607SPeng Li struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2864849e4607SPeng Li 28658be73621SHuazhong Tan return min_t(u32, hdev->rss_size_max, 28668be73621SHuazhong Tan hdev->num_tqps / kinfo->num_tc); 2867849e4607SPeng Li } 2868849e4607SPeng Li 2869849e4607SPeng Li /** 2870849e4607SPeng Li * hclgevf_get_channels - Get the current channels enabled and max supported. 2871849e4607SPeng Li * @handle: hardware information for network interface 2872849e4607SPeng Li * @ch: ethtool channels structure 2873849e4607SPeng Li * 2874849e4607SPeng Li * We don't support separate tx and rx queues as channels. The other count 2875849e4607SPeng Li * represents how many queues are being used for control. max_combined counts 2876849e4607SPeng Li * how many queue pairs we can support. They may not be mapped 1 to 1 with 2877849e4607SPeng Li * q_vectors since we support a lot more queue pairs than q_vectors. 2878849e4607SPeng Li **/ 2879849e4607SPeng Li static void hclgevf_get_channels(struct hnae3_handle *handle, 2880849e4607SPeng Li struct ethtool_channels *ch) 2881849e4607SPeng Li { 2882849e4607SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2883849e4607SPeng Li 2884849e4607SPeng Li ch->max_combined = hclgevf_get_max_channels(hdev); 2885849e4607SPeng Li ch->other_count = 0; 2886849e4607SPeng Li ch->max_other = 0; 28878be73621SHuazhong Tan ch->combined_count = handle->kinfo.rss_size; 2888849e4607SPeng Li } 2889849e4607SPeng Li 2890cc719218SPeng Li static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 28910d43bf45SHuazhong Tan u16 *alloc_tqps, u16 *max_rss_size) 2892cc719218SPeng Li { 2893cc719218SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2894cc719218SPeng Li 28950d43bf45SHuazhong Tan *alloc_tqps = hdev->num_tqps; 2896cc719218SPeng Li *max_rss_size = hdev->rss_size_max; 2897cc719218SPeng Li } 2898cc719218SPeng Li 28994093d1a2SGuangbin Huang static void hclgevf_update_rss_size(struct hnae3_handle *handle, 29004093d1a2SGuangbin Huang u32 new_tqps_num) 29014093d1a2SGuangbin Huang { 29024093d1a2SGuangbin Huang struct hnae3_knic_private_info *kinfo = &handle->kinfo; 29034093d1a2SGuangbin Huang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 29044093d1a2SGuangbin Huang u16 max_rss_size; 29054093d1a2SGuangbin Huang 29064093d1a2SGuangbin Huang kinfo->req_rss_size = new_tqps_num; 29074093d1a2SGuangbin Huang 29084093d1a2SGuangbin Huang max_rss_size = min_t(u16, hdev->rss_size_max, 29094093d1a2SGuangbin Huang hdev->num_tqps / kinfo->num_tc); 29104093d1a2SGuangbin Huang 29114093d1a2SGuangbin Huang /* Use the user's configuration when it is not larger than 29124093d1a2SGuangbin Huang * max_rss_size, otherwise, use the maximum specification value. 29134093d1a2SGuangbin Huang */ 29144093d1a2SGuangbin Huang if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 29154093d1a2SGuangbin Huang kinfo->req_rss_size <= max_rss_size) 29164093d1a2SGuangbin Huang kinfo->rss_size = kinfo->req_rss_size; 29174093d1a2SGuangbin Huang else if (kinfo->rss_size > max_rss_size || 29184093d1a2SGuangbin Huang (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) 29194093d1a2SGuangbin Huang kinfo->rss_size = max_rss_size; 29204093d1a2SGuangbin Huang 29214093d1a2SGuangbin Huang kinfo->num_tqps = kinfo->num_tc * kinfo->rss_size; 29224093d1a2SGuangbin Huang } 29234093d1a2SGuangbin Huang 29244093d1a2SGuangbin Huang static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 29254093d1a2SGuangbin Huang bool rxfh_configured) 29264093d1a2SGuangbin Huang { 29274093d1a2SGuangbin Huang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 29284093d1a2SGuangbin Huang struct hnae3_knic_private_info *kinfo = &handle->kinfo; 29294093d1a2SGuangbin Huang u16 cur_rss_size = kinfo->rss_size; 29304093d1a2SGuangbin Huang u16 cur_tqps = kinfo->num_tqps; 29314093d1a2SGuangbin Huang u32 *rss_indir; 29324093d1a2SGuangbin Huang unsigned int i; 29334093d1a2SGuangbin Huang int ret; 29344093d1a2SGuangbin Huang 29354093d1a2SGuangbin Huang hclgevf_update_rss_size(handle, new_tqps_num); 29364093d1a2SGuangbin Huang 29374093d1a2SGuangbin Huang ret = hclgevf_set_rss_tc_mode(hdev, kinfo->rss_size); 29384093d1a2SGuangbin Huang if (ret) 29394093d1a2SGuangbin Huang return ret; 29404093d1a2SGuangbin Huang 29414093d1a2SGuangbin Huang /* RSS indirection table has been configuared by user */ 29424093d1a2SGuangbin Huang if (rxfh_configured) 29434093d1a2SGuangbin Huang goto out; 29444093d1a2SGuangbin Huang 29454093d1a2SGuangbin Huang /* Reinitializes the rss indirect table according to the new RSS size */ 29464093d1a2SGuangbin Huang rss_indir = kcalloc(HCLGEVF_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL); 29474093d1a2SGuangbin Huang if (!rss_indir) 29484093d1a2SGuangbin Huang return -ENOMEM; 29494093d1a2SGuangbin Huang 29504093d1a2SGuangbin Huang for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 29514093d1a2SGuangbin Huang rss_indir[i] = i % kinfo->rss_size; 29524093d1a2SGuangbin Huang 29534093d1a2SGuangbin Huang ret = hclgevf_set_rss(handle, rss_indir, NULL, 0); 29544093d1a2SGuangbin Huang if (ret) 29554093d1a2SGuangbin Huang dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 29564093d1a2SGuangbin Huang ret); 29574093d1a2SGuangbin Huang 29584093d1a2SGuangbin Huang kfree(rss_indir); 29594093d1a2SGuangbin Huang 29604093d1a2SGuangbin Huang out: 29614093d1a2SGuangbin Huang if (!ret) 29624093d1a2SGuangbin Huang dev_info(&hdev->pdev->dev, 29634093d1a2SGuangbin Huang "Channels changed, rss_size from %u to %u, tqps from %u to %u", 29644093d1a2SGuangbin Huang cur_rss_size, kinfo->rss_size, 29654093d1a2SGuangbin Huang cur_tqps, kinfo->rss_size * kinfo->num_tc); 29664093d1a2SGuangbin Huang 29674093d1a2SGuangbin Huang return ret; 29684093d1a2SGuangbin Huang } 29694093d1a2SGuangbin Huang 2970175ec96bSFuyun Liang static int hclgevf_get_status(struct hnae3_handle *handle) 2971175ec96bSFuyun Liang { 2972175ec96bSFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2973175ec96bSFuyun Liang 2974175ec96bSFuyun Liang return hdev->hw.mac.link; 2975175ec96bSFuyun Liang } 2976175ec96bSFuyun Liang 29774a152de9SFuyun Liang static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 29784a152de9SFuyun Liang u8 *auto_neg, u32 *speed, 29794a152de9SFuyun Liang u8 *duplex) 29804a152de9SFuyun Liang { 29814a152de9SFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 29824a152de9SFuyun Liang 29834a152de9SFuyun Liang if (speed) 29844a152de9SFuyun Liang *speed = hdev->hw.mac.speed; 29854a152de9SFuyun Liang if (duplex) 29864a152de9SFuyun Liang *duplex = hdev->hw.mac.duplex; 29874a152de9SFuyun Liang if (auto_neg) 29884a152de9SFuyun Liang *auto_neg = AUTONEG_DISABLE; 29894a152de9SFuyun Liang } 29904a152de9SFuyun Liang 29914a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 29924a152de9SFuyun Liang u8 duplex) 29934a152de9SFuyun Liang { 29944a152de9SFuyun Liang hdev->hw.mac.speed = speed; 29954a152de9SFuyun Liang hdev->hw.mac.duplex = duplex; 29964a152de9SFuyun Liang } 29974a152de9SFuyun Liang 29981731be4cSYonglong Liu static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 29995c9f6b39SPeng Li { 30005c9f6b39SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 30015c9f6b39SPeng Li 30025c9f6b39SPeng Li return hclgevf_config_gro(hdev, enable); 30035c9f6b39SPeng Li } 30045c9f6b39SPeng Li 300588d10bd6SJian Shen static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 300688d10bd6SJian Shen u8 *module_type) 3007c136b884SPeng Li { 3008c136b884SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 300988d10bd6SJian Shen 3010c136b884SPeng Li if (media_type) 3011c136b884SPeng Li *media_type = hdev->hw.mac.media_type; 301288d10bd6SJian Shen 301388d10bd6SJian Shen if (module_type) 301488d10bd6SJian Shen *module_type = hdev->hw.mac.module_type; 3015c136b884SPeng Li } 3016c136b884SPeng Li 30174d60291bSHuazhong Tan static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 30184d60291bSHuazhong Tan { 30194d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 30204d60291bSHuazhong Tan 3021aa5c4f17SHuazhong Tan return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 30224d60291bSHuazhong Tan } 30234d60291bSHuazhong Tan 30244d60291bSHuazhong Tan static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 30254d60291bSHuazhong Tan { 30264d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 30274d60291bSHuazhong Tan 30284d60291bSHuazhong Tan return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 30294d60291bSHuazhong Tan } 30304d60291bSHuazhong Tan 30314d60291bSHuazhong Tan static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 30324d60291bSHuazhong Tan { 30334d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 30344d60291bSHuazhong Tan 3035c88a6e7dSHuazhong Tan return hdev->rst_stats.hw_rst_done_cnt; 30364d60291bSHuazhong Tan } 30374d60291bSHuazhong Tan 30389194d18bSliuzhongzhu static void hclgevf_get_link_mode(struct hnae3_handle *handle, 30399194d18bSliuzhongzhu unsigned long *supported, 30409194d18bSliuzhongzhu unsigned long *advertising) 30419194d18bSliuzhongzhu { 30429194d18bSliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 30439194d18bSliuzhongzhu 30449194d18bSliuzhongzhu *supported = hdev->hw.mac.supported; 30459194d18bSliuzhongzhu *advertising = hdev->hw.mac.advertising; 30469194d18bSliuzhongzhu } 30479194d18bSliuzhongzhu 30481600c3e5SJian Shen #define MAX_SEPARATE_NUM 4 30491600c3e5SJian Shen #define SEPARATOR_VALUE 0xFFFFFFFF 30501600c3e5SJian Shen #define REG_NUM_PER_LINE 4 30511600c3e5SJian Shen #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 30521600c3e5SJian Shen 30531600c3e5SJian Shen static int hclgevf_get_regs_len(struct hnae3_handle *handle) 30541600c3e5SJian Shen { 30551600c3e5SJian Shen int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 30561600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 30571600c3e5SJian Shen 30581600c3e5SJian Shen cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 30591600c3e5SJian Shen common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 30601600c3e5SJian Shen ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 30611600c3e5SJian Shen tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 30621600c3e5SJian Shen 30631600c3e5SJian Shen return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 30641600c3e5SJian Shen tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 30651600c3e5SJian Shen } 30661600c3e5SJian Shen 30671600c3e5SJian Shen static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 30681600c3e5SJian Shen void *data) 30691600c3e5SJian Shen { 30701600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 30711600c3e5SJian Shen int i, j, reg_um, separator_num; 30721600c3e5SJian Shen u32 *reg = data; 30731600c3e5SJian Shen 30741600c3e5SJian Shen *version = hdev->fw_version; 30751600c3e5SJian Shen 30761600c3e5SJian Shen /* fetching per-VF registers values from VF PCIe register space */ 30771600c3e5SJian Shen reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 30781600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 30791600c3e5SJian Shen for (i = 0; i < reg_um; i++) 30801600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 30811600c3e5SJian Shen for (i = 0; i < separator_num; i++) 30821600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 30831600c3e5SJian Shen 30841600c3e5SJian Shen reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 30851600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 30861600c3e5SJian Shen for (i = 0; i < reg_um; i++) 30871600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 30881600c3e5SJian Shen for (i = 0; i < separator_num; i++) 30891600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 30901600c3e5SJian Shen 30911600c3e5SJian Shen reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 30921600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 30931600c3e5SJian Shen for (j = 0; j < hdev->num_tqps; j++) { 30941600c3e5SJian Shen for (i = 0; i < reg_um; i++) 30951600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 30961600c3e5SJian Shen ring_reg_addr_list[i] + 30971600c3e5SJian Shen 0x200 * j); 30981600c3e5SJian Shen for (i = 0; i < separator_num; i++) 30991600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 31001600c3e5SJian Shen } 31011600c3e5SJian Shen 31021600c3e5SJian Shen reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 31031600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 31041600c3e5SJian Shen for (j = 0; j < hdev->num_msi_used - 1; j++) { 31051600c3e5SJian Shen for (i = 0; i < reg_um; i++) 31061600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 31071600c3e5SJian Shen tqp_intr_reg_addr_list[i] + 31081600c3e5SJian Shen 4 * j); 31091600c3e5SJian Shen for (i = 0; i < separator_num; i++) 31101600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 31111600c3e5SJian Shen } 31121600c3e5SJian Shen } 31131600c3e5SJian Shen 311492f11ea1SJian Shen void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 311592f11ea1SJian Shen u8 *port_base_vlan_info, u8 data_size) 311692f11ea1SJian Shen { 311792f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 311892f11ea1SJian Shen 311992f11ea1SJian Shen rtnl_lock(); 312092f11ea1SJian Shen hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 312192f11ea1SJian Shen rtnl_unlock(); 312292f11ea1SJian Shen 312392f11ea1SJian Shen /* send msg to PF and wait update port based vlan info */ 312492f11ea1SJian Shen hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 312592f11ea1SJian Shen HCLGE_MBX_PORT_BASE_VLAN_CFG, 312692f11ea1SJian Shen port_base_vlan_info, data_size, 312792f11ea1SJian Shen false, NULL, 0); 312892f11ea1SJian Shen 312992f11ea1SJian Shen if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 313092f11ea1SJian Shen nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 313192f11ea1SJian Shen else 313292f11ea1SJian Shen nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 313392f11ea1SJian Shen 313492f11ea1SJian Shen rtnl_lock(); 313592f11ea1SJian Shen hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 313692f11ea1SJian Shen rtnl_unlock(); 313792f11ea1SJian Shen } 313892f11ea1SJian Shen 3139e2cb1decSSalil Mehta static const struct hnae3_ae_ops hclgevf_ops = { 3140e2cb1decSSalil Mehta .init_ae_dev = hclgevf_init_ae_dev, 3141e2cb1decSSalil Mehta .uninit_ae_dev = hclgevf_uninit_ae_dev, 31426ff3cf07SHuazhong Tan .flr_prepare = hclgevf_flr_prepare, 31436ff3cf07SHuazhong Tan .flr_done = hclgevf_flr_done, 3144e718a93fSPeng Li .init_client_instance = hclgevf_init_client_instance, 3145e718a93fSPeng Li .uninit_client_instance = hclgevf_uninit_client_instance, 3146e2cb1decSSalil Mehta .start = hclgevf_ae_start, 3147e2cb1decSSalil Mehta .stop = hclgevf_ae_stop, 3148a6d818e3SYunsheng Lin .client_start = hclgevf_client_start, 3149a6d818e3SYunsheng Lin .client_stop = hclgevf_client_stop, 3150e2cb1decSSalil Mehta .map_ring_to_vector = hclgevf_map_ring_to_vector, 3151e2cb1decSSalil Mehta .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 3152e2cb1decSSalil Mehta .get_vector = hclgevf_get_vector, 31530d3e6631SYunsheng Lin .put_vector = hclgevf_put_vector, 3154e2cb1decSSalil Mehta .reset_queue = hclgevf_reset_tqp, 3155e2cb1decSSalil Mehta .get_mac_addr = hclgevf_get_mac_addr, 3156e2cb1decSSalil Mehta .set_mac_addr = hclgevf_set_mac_addr, 3157e2cb1decSSalil Mehta .add_uc_addr = hclgevf_add_uc_addr, 3158e2cb1decSSalil Mehta .rm_uc_addr = hclgevf_rm_uc_addr, 3159e2cb1decSSalil Mehta .add_mc_addr = hclgevf_add_mc_addr, 3160e2cb1decSSalil Mehta .rm_mc_addr = hclgevf_rm_mc_addr, 3161e2cb1decSSalil Mehta .get_stats = hclgevf_get_stats, 3162e2cb1decSSalil Mehta .update_stats = hclgevf_update_stats, 3163e2cb1decSSalil Mehta .get_strings = hclgevf_get_strings, 3164e2cb1decSSalil Mehta .get_sset_count = hclgevf_get_sset_count, 3165e2cb1decSSalil Mehta .get_rss_key_size = hclgevf_get_rss_key_size, 3166e2cb1decSSalil Mehta .get_rss_indir_size = hclgevf_get_rss_indir_size, 3167e2cb1decSSalil Mehta .get_rss = hclgevf_get_rss, 3168e2cb1decSSalil Mehta .set_rss = hclgevf_set_rss, 3169d97b3072SJian Shen .get_rss_tuple = hclgevf_get_rss_tuple, 3170d97b3072SJian Shen .set_rss_tuple = hclgevf_set_rss_tuple, 3171e2cb1decSSalil Mehta .get_tc_size = hclgevf_get_tc_size, 3172e2cb1decSSalil Mehta .get_fw_version = hclgevf_get_fw_version, 3173e2cb1decSSalil Mehta .set_vlan_filter = hclgevf_set_vlan_filter, 3174b2641e2aSYunsheng Lin .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 31756d4c3981SSalil Mehta .reset_event = hclgevf_reset_event, 3176720bd583SHuazhong Tan .set_default_reset_request = hclgevf_set_def_reset_request, 31774093d1a2SGuangbin Huang .set_channels = hclgevf_set_channels, 3178849e4607SPeng Li .get_channels = hclgevf_get_channels, 3179cc719218SPeng Li .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 31801600c3e5SJian Shen .get_regs_len = hclgevf_get_regs_len, 31811600c3e5SJian Shen .get_regs = hclgevf_get_regs, 3182175ec96bSFuyun Liang .get_status = hclgevf_get_status, 31834a152de9SFuyun Liang .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3184c136b884SPeng Li .get_media_type = hclgevf_get_media_type, 31854d60291bSHuazhong Tan .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 31864d60291bSHuazhong Tan .ae_dev_resetting = hclgevf_ae_dev_resetting, 31874d60291bSHuazhong Tan .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 31885c9f6b39SPeng Li .set_gro_en = hclgevf_gro_en, 3189818f1675SYunsheng Lin .set_mtu = hclgevf_set_mtu, 31900c29d191Sliuzhongzhu .get_global_queue_id = hclgevf_get_qid_global, 31918cdb992fSJian Shen .set_timer_task = hclgevf_set_timer_task, 31929194d18bSliuzhongzhu .get_link_mode = hclgevf_get_link_mode, 3193e196ec75SJian Shen .set_promisc_mode = hclgevf_set_promisc_mode, 3194e2cb1decSSalil Mehta }; 3195e2cb1decSSalil Mehta 3196e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf = { 3197e2cb1decSSalil Mehta .ops = &hclgevf_ops, 3198e2cb1decSSalil Mehta .pdev_id_table = ae_algovf_pci_tbl, 3199e2cb1decSSalil Mehta }; 3200e2cb1decSSalil Mehta 3201e2cb1decSSalil Mehta static int hclgevf_init(void) 3202e2cb1decSSalil Mehta { 3203e2cb1decSSalil Mehta pr_info("%s is initializing\n", HCLGEVF_NAME); 3204e2cb1decSSalil Mehta 3205854cf33aSFuyun Liang hnae3_register_ae_algo(&ae_algovf); 3206854cf33aSFuyun Liang 3207854cf33aSFuyun Liang return 0; 3208e2cb1decSSalil Mehta } 3209e2cb1decSSalil Mehta 3210e2cb1decSSalil Mehta static void hclgevf_exit(void) 3211e2cb1decSSalil Mehta { 3212e2cb1decSSalil Mehta hnae3_unregister_ae_algo(&ae_algovf); 3213e2cb1decSSalil Mehta } 3214e2cb1decSSalil Mehta module_init(hclgevf_init); 3215e2cb1decSSalil Mehta module_exit(hclgevf_exit); 3216e2cb1decSSalil Mehta 3217e2cb1decSSalil Mehta MODULE_LICENSE("GPL"); 3218e2cb1decSSalil Mehta MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3219e2cb1decSSalil Mehta MODULE_DESCRIPTION("HCLGEVF Driver"); 3220e2cb1decSSalil Mehta MODULE_VERSION(HCLGEVF_MOD_VERSION); 3221