1e2cb1decSSalil Mehta // SPDX-License-Identifier: GPL-2.0+ 2e2cb1decSSalil Mehta // Copyright (c) 2016-2017 Hisilicon Limited. 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #include <linux/etherdevice.h> 5aa5c4f17SHuazhong Tan #include <linux/iopoll.h> 66988eb2aSSalil Mehta #include <net/rtnetlink.h> 7e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 8e2cb1decSSalil Mehta #include "hclgevf_main.h" 9e2cb1decSSalil Mehta #include "hclge_mbx.h" 10e2cb1decSSalil Mehta #include "hnae3.h" 11e2cb1decSSalil Mehta 12e2cb1decSSalil Mehta #define HCLGEVF_NAME "hclgevf" 13e2cb1decSSalil Mehta 149c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 15e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf; 16e2cb1decSSalil Mehta 17e2cb1decSSalil Mehta static const struct pci_device_id ae_algovf_pci_tbl[] = { 18e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 19e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 20e2cb1decSSalil Mehta /* required last entry */ 21e2cb1decSSalil Mehta {0, } 22e2cb1decSSalil Mehta }; 23e2cb1decSSalil Mehta 24472d7eceSJian Shen static const u8 hclgevf_hash_key[] = { 25472d7eceSJian Shen 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 26472d7eceSJian Shen 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 27472d7eceSJian Shen 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 28472d7eceSJian Shen 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 29472d7eceSJian Shen 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 30472d7eceSJian Shen }; 31472d7eceSJian Shen 322f550a46SYunsheng Lin MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 332f550a46SYunsheng Lin 341600c3e5SJian Shen static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 351600c3e5SJian Shen HCLGEVF_CMDQ_TX_ADDR_H_REG, 361600c3e5SJian Shen HCLGEVF_CMDQ_TX_DEPTH_REG, 371600c3e5SJian Shen HCLGEVF_CMDQ_TX_TAIL_REG, 381600c3e5SJian Shen HCLGEVF_CMDQ_TX_HEAD_REG, 391600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_L_REG, 401600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_H_REG, 411600c3e5SJian Shen HCLGEVF_CMDQ_RX_DEPTH_REG, 421600c3e5SJian Shen HCLGEVF_CMDQ_RX_TAIL_REG, 431600c3e5SJian Shen HCLGEVF_CMDQ_RX_HEAD_REG, 441600c3e5SJian Shen HCLGEVF_VECTOR0_CMDQ_SRC_REG, 451600c3e5SJian Shen HCLGEVF_CMDQ_INTR_STS_REG, 461600c3e5SJian Shen HCLGEVF_CMDQ_INTR_EN_REG, 471600c3e5SJian Shen HCLGEVF_CMDQ_INTR_GEN_REG}; 481600c3e5SJian Shen 491600c3e5SJian Shen static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 501600c3e5SJian Shen HCLGEVF_RST_ING, 511600c3e5SJian Shen HCLGEVF_GRO_EN_REG}; 521600c3e5SJian Shen 531600c3e5SJian Shen static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 541600c3e5SJian Shen HCLGEVF_RING_RX_ADDR_H_REG, 551600c3e5SJian Shen HCLGEVF_RING_RX_BD_NUM_REG, 561600c3e5SJian Shen HCLGEVF_RING_RX_BD_LENGTH_REG, 571600c3e5SJian Shen HCLGEVF_RING_RX_MERGE_EN_REG, 581600c3e5SJian Shen HCLGEVF_RING_RX_TAIL_REG, 591600c3e5SJian Shen HCLGEVF_RING_RX_HEAD_REG, 601600c3e5SJian Shen HCLGEVF_RING_RX_FBD_NUM_REG, 611600c3e5SJian Shen HCLGEVF_RING_RX_OFFSET_REG, 621600c3e5SJian Shen HCLGEVF_RING_RX_FBD_OFFSET_REG, 631600c3e5SJian Shen HCLGEVF_RING_RX_STASH_REG, 641600c3e5SJian Shen HCLGEVF_RING_RX_BD_ERR_REG, 651600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_L_REG, 661600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_H_REG, 671600c3e5SJian Shen HCLGEVF_RING_TX_BD_NUM_REG, 681600c3e5SJian Shen HCLGEVF_RING_TX_PRIORITY_REG, 691600c3e5SJian Shen HCLGEVF_RING_TX_TC_REG, 701600c3e5SJian Shen HCLGEVF_RING_TX_MERGE_EN_REG, 711600c3e5SJian Shen HCLGEVF_RING_TX_TAIL_REG, 721600c3e5SJian Shen HCLGEVF_RING_TX_HEAD_REG, 731600c3e5SJian Shen HCLGEVF_RING_TX_FBD_NUM_REG, 741600c3e5SJian Shen HCLGEVF_RING_TX_OFFSET_REG, 751600c3e5SJian Shen HCLGEVF_RING_TX_EBD_NUM_REG, 761600c3e5SJian Shen HCLGEVF_RING_TX_EBD_OFFSET_REG, 771600c3e5SJian Shen HCLGEVF_RING_TX_BD_ERR_REG, 781600c3e5SJian Shen HCLGEVF_RING_EN_REG}; 791600c3e5SJian Shen 801600c3e5SJian Shen static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 811600c3e5SJian Shen HCLGEVF_TQP_INTR_GL0_REG, 821600c3e5SJian Shen HCLGEVF_TQP_INTR_GL1_REG, 831600c3e5SJian Shen HCLGEVF_TQP_INTR_GL2_REG, 841600c3e5SJian Shen HCLGEVF_TQP_INTR_RL_REG}; 851600c3e5SJian Shen 86e2cb1decSSalil Mehta static inline struct hclgevf_dev *hclgevf_ae_get_hdev( 87e2cb1decSSalil Mehta struct hnae3_handle *handle) 88e2cb1decSSalil Mehta { 89eed9535fSPeng Li if (!handle->client) 90eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, nic); 91eed9535fSPeng Li else if (handle->client->type == HNAE3_CLIENT_ROCE) 92eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, roce); 93eed9535fSPeng Li else 94e2cb1decSSalil Mehta return container_of(handle, struct hclgevf_dev, nic); 95e2cb1decSSalil Mehta } 96e2cb1decSSalil Mehta 97e2cb1decSSalil Mehta static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 98e2cb1decSSalil Mehta { 99b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 100e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 101e2cb1decSSalil Mehta struct hclgevf_desc desc; 102e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 103e2cb1decSSalil Mehta int status; 104e2cb1decSSalil Mehta int i; 105e2cb1decSSalil Mehta 106b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 107b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 108e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 109e2cb1decSSalil Mehta HCLGEVF_OPC_QUERY_RX_STATUS, 110e2cb1decSSalil Mehta true); 111e2cb1decSSalil Mehta 112e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 113e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 114e2cb1decSSalil Mehta if (status) { 115e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 116e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 117e2cb1decSSalil Mehta status, i); 118e2cb1decSSalil Mehta return status; 119e2cb1decSSalil Mehta } 120e2cb1decSSalil Mehta tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 121cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 122e2cb1decSSalil Mehta 123e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 124e2cb1decSSalil Mehta true); 125e2cb1decSSalil Mehta 126e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 127e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 128e2cb1decSSalil Mehta if (status) { 129e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 130e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 131e2cb1decSSalil Mehta status, i); 132e2cb1decSSalil Mehta return status; 133e2cb1decSSalil Mehta } 134e2cb1decSSalil Mehta tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 135cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 136e2cb1decSSalil Mehta } 137e2cb1decSSalil Mehta 138e2cb1decSSalil Mehta return 0; 139e2cb1decSSalil Mehta } 140e2cb1decSSalil Mehta 141e2cb1decSSalil Mehta static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 142e2cb1decSSalil Mehta { 143e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo = &handle->kinfo; 144e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 145e2cb1decSSalil Mehta u64 *buff = data; 146e2cb1decSSalil Mehta int i; 147e2cb1decSSalil Mehta 148b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 149b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 150e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 151e2cb1decSSalil Mehta } 152e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 153b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 154e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 155e2cb1decSSalil Mehta } 156e2cb1decSSalil Mehta 157e2cb1decSSalil Mehta return buff; 158e2cb1decSSalil Mehta } 159e2cb1decSSalil Mehta 160e2cb1decSSalil Mehta static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 161e2cb1decSSalil Mehta { 162b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 163e2cb1decSSalil Mehta 164b4f1d303SJian Shen return kinfo->num_tqps * 2; 165e2cb1decSSalil Mehta } 166e2cb1decSSalil Mehta 167e2cb1decSSalil Mehta static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 168e2cb1decSSalil Mehta { 169b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 170e2cb1decSSalil Mehta u8 *buff = data; 171e2cb1decSSalil Mehta int i = 0; 172e2cb1decSSalil Mehta 173b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 174b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 175e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1760c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 177e2cb1decSSalil Mehta tqp->index); 178e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 179e2cb1decSSalil Mehta } 180e2cb1decSSalil Mehta 181b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 182b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 183e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1840c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 185e2cb1decSSalil Mehta tqp->index); 186e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 187e2cb1decSSalil Mehta } 188e2cb1decSSalil Mehta 189e2cb1decSSalil Mehta return buff; 190e2cb1decSSalil Mehta } 191e2cb1decSSalil Mehta 192e2cb1decSSalil Mehta static void hclgevf_update_stats(struct hnae3_handle *handle, 193e2cb1decSSalil Mehta struct net_device_stats *net_stats) 194e2cb1decSSalil Mehta { 195e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 196e2cb1decSSalil Mehta int status; 197e2cb1decSSalil Mehta 198e2cb1decSSalil Mehta status = hclgevf_tqps_update_stats(handle); 199e2cb1decSSalil Mehta if (status) 200e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 201e2cb1decSSalil Mehta "VF update of TQPS stats fail, status = %d.\n", 202e2cb1decSSalil Mehta status); 203e2cb1decSSalil Mehta } 204e2cb1decSSalil Mehta 205e2cb1decSSalil Mehta static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 206e2cb1decSSalil Mehta { 207e2cb1decSSalil Mehta if (strset == ETH_SS_TEST) 208e2cb1decSSalil Mehta return -EOPNOTSUPP; 209e2cb1decSSalil Mehta else if (strset == ETH_SS_STATS) 210e2cb1decSSalil Mehta return hclgevf_tqps_get_sset_count(handle, strset); 211e2cb1decSSalil Mehta 212e2cb1decSSalil Mehta return 0; 213e2cb1decSSalil Mehta } 214e2cb1decSSalil Mehta 215e2cb1decSSalil Mehta static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 216e2cb1decSSalil Mehta u8 *data) 217e2cb1decSSalil Mehta { 218e2cb1decSSalil Mehta u8 *p = (char *)data; 219e2cb1decSSalil Mehta 220e2cb1decSSalil Mehta if (strset == ETH_SS_STATS) 221e2cb1decSSalil Mehta p = hclgevf_tqps_get_strings(handle, p); 222e2cb1decSSalil Mehta } 223e2cb1decSSalil Mehta 224e2cb1decSSalil Mehta static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 225e2cb1decSSalil Mehta { 226e2cb1decSSalil Mehta hclgevf_tqps_get_stats(handle, data); 227e2cb1decSSalil Mehta } 228e2cb1decSSalil Mehta 229e2cb1decSSalil Mehta static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 230e2cb1decSSalil Mehta { 231e2cb1decSSalil Mehta u8 resp_msg; 232e2cb1decSSalil Mehta int status; 233e2cb1decSSalil Mehta 234e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 235e2cb1decSSalil Mehta true, &resp_msg, sizeof(u8)); 236e2cb1decSSalil Mehta if (status) { 237e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 238e2cb1decSSalil Mehta "VF request to get TC info from PF failed %d", 239e2cb1decSSalil Mehta status); 240e2cb1decSSalil Mehta return status; 241e2cb1decSSalil Mehta } 242e2cb1decSSalil Mehta 243e2cb1decSSalil Mehta hdev->hw_tc_map = resp_msg; 244e2cb1decSSalil Mehta 245e2cb1decSSalil Mehta return 0; 246e2cb1decSSalil Mehta } 247e2cb1decSSalil Mehta 24892f11ea1SJian Shen static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 24992f11ea1SJian Shen { 25092f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 25192f11ea1SJian Shen u8 resp_msg; 25292f11ea1SJian Shen int ret; 25392f11ea1SJian Shen 25492f11ea1SJian Shen ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 25592f11ea1SJian Shen HCLGE_MBX_GET_PORT_BASE_VLAN_STATE, 25692f11ea1SJian Shen NULL, 0, true, &resp_msg, sizeof(u8)); 25792f11ea1SJian Shen if (ret) { 25892f11ea1SJian Shen dev_err(&hdev->pdev->dev, 25992f11ea1SJian Shen "VF request to get port based vlan state failed %d", 26092f11ea1SJian Shen ret); 26192f11ea1SJian Shen return ret; 26292f11ea1SJian Shen } 26392f11ea1SJian Shen 26492f11ea1SJian Shen nic->port_base_vlan_state = resp_msg; 26592f11ea1SJian Shen 26692f11ea1SJian Shen return 0; 26792f11ea1SJian Shen } 26892f11ea1SJian Shen 2696cee6fc3SJian Shen static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 270e2cb1decSSalil Mehta { 271c0425944SPeng Li #define HCLGEVF_TQPS_RSS_INFO_LEN 6 272e2cb1decSSalil Mehta u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 273e2cb1decSSalil Mehta int status; 274e2cb1decSSalil Mehta 275e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 276e2cb1decSSalil Mehta true, resp_msg, 277e2cb1decSSalil Mehta HCLGEVF_TQPS_RSS_INFO_LEN); 278e2cb1decSSalil Mehta if (status) { 279e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 280e2cb1decSSalil Mehta "VF request to get tqp info from PF failed %d", 281e2cb1decSSalil Mehta status); 282e2cb1decSSalil Mehta return status; 283e2cb1decSSalil Mehta } 284e2cb1decSSalil Mehta 285e2cb1decSSalil Mehta memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 286e2cb1decSSalil Mehta memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 287c0425944SPeng Li memcpy(&hdev->rx_buf_len, &resp_msg[4], sizeof(u16)); 288c0425944SPeng Li 289c0425944SPeng Li return 0; 290c0425944SPeng Li } 291c0425944SPeng Li 292c0425944SPeng Li static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 293c0425944SPeng Li { 294c0425944SPeng Li #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 295c0425944SPeng Li u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 296c0425944SPeng Li int ret; 297c0425944SPeng Li 298c0425944SPeng Li ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QDEPTH, 0, NULL, 0, 299c0425944SPeng Li true, resp_msg, 300c0425944SPeng Li HCLGEVF_TQPS_DEPTH_INFO_LEN); 301c0425944SPeng Li if (ret) { 302c0425944SPeng Li dev_err(&hdev->pdev->dev, 303c0425944SPeng Li "VF request to get tqp depth info from PF failed %d", 304c0425944SPeng Li ret); 305c0425944SPeng Li return ret; 306c0425944SPeng Li } 307c0425944SPeng Li 308c0425944SPeng Li memcpy(&hdev->num_tx_desc, &resp_msg[0], sizeof(u16)); 309c0425944SPeng Li memcpy(&hdev->num_rx_desc, &resp_msg[2], sizeof(u16)); 310e2cb1decSSalil Mehta 311e2cb1decSSalil Mehta return 0; 312e2cb1decSSalil Mehta } 313e2cb1decSSalil Mehta 3140c29d191Sliuzhongzhu static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 3150c29d191Sliuzhongzhu { 3160c29d191Sliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3170c29d191Sliuzhongzhu u8 msg_data[2], resp_data[2]; 3180c29d191Sliuzhongzhu u16 qid_in_pf = 0; 3190c29d191Sliuzhongzhu int ret; 3200c29d191Sliuzhongzhu 3210c29d191Sliuzhongzhu memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 3220c29d191Sliuzhongzhu 3230c29d191Sliuzhongzhu ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data, 3240c29d191Sliuzhongzhu 2, true, resp_data, 2); 3250c29d191Sliuzhongzhu if (!ret) 3260c29d191Sliuzhongzhu qid_in_pf = *(u16 *)resp_data; 3270c29d191Sliuzhongzhu 3280c29d191Sliuzhongzhu return qid_in_pf; 3290c29d191Sliuzhongzhu } 3300c29d191Sliuzhongzhu 3319c3e7130Sliuzhongzhu static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 3329c3e7130Sliuzhongzhu { 33388d10bd6SJian Shen u8 resp_msg[2]; 3349c3e7130Sliuzhongzhu int ret; 3359c3e7130Sliuzhongzhu 3369c3e7130Sliuzhongzhu ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_MEDIA_TYPE, 0, NULL, 0, 33788d10bd6SJian Shen true, resp_msg, sizeof(resp_msg)); 3389c3e7130Sliuzhongzhu if (ret) { 3399c3e7130Sliuzhongzhu dev_err(&hdev->pdev->dev, 3409c3e7130Sliuzhongzhu "VF request to get the pf port media type failed %d", 3419c3e7130Sliuzhongzhu ret); 3429c3e7130Sliuzhongzhu return ret; 3439c3e7130Sliuzhongzhu } 3449c3e7130Sliuzhongzhu 34588d10bd6SJian Shen hdev->hw.mac.media_type = resp_msg[0]; 34688d10bd6SJian Shen hdev->hw.mac.module_type = resp_msg[1]; 3479c3e7130Sliuzhongzhu 3489c3e7130Sliuzhongzhu return 0; 3499c3e7130Sliuzhongzhu } 3509c3e7130Sliuzhongzhu 351e2cb1decSSalil Mehta static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 352e2cb1decSSalil Mehta { 353e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 354e2cb1decSSalil Mehta int i; 355e2cb1decSSalil Mehta 356e2cb1decSSalil Mehta hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 357e2cb1decSSalil Mehta sizeof(struct hclgevf_tqp), GFP_KERNEL); 358e2cb1decSSalil Mehta if (!hdev->htqp) 359e2cb1decSSalil Mehta return -ENOMEM; 360e2cb1decSSalil Mehta 361e2cb1decSSalil Mehta tqp = hdev->htqp; 362e2cb1decSSalil Mehta 363e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 364e2cb1decSSalil Mehta tqp->dev = &hdev->pdev->dev; 365e2cb1decSSalil Mehta tqp->index = i; 366e2cb1decSSalil Mehta 367e2cb1decSSalil Mehta tqp->q.ae_algo = &ae_algovf; 368e2cb1decSSalil Mehta tqp->q.buf_size = hdev->rx_buf_len; 369c0425944SPeng Li tqp->q.tx_desc_num = hdev->num_tx_desc; 370c0425944SPeng Li tqp->q.rx_desc_num = hdev->num_rx_desc; 371e2cb1decSSalil Mehta tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 372e2cb1decSSalil Mehta i * HCLGEVF_TQP_REG_SIZE; 373e2cb1decSSalil Mehta 374e2cb1decSSalil Mehta tqp++; 375e2cb1decSSalil Mehta } 376e2cb1decSSalil Mehta 377e2cb1decSSalil Mehta return 0; 378e2cb1decSSalil Mehta } 379e2cb1decSSalil Mehta 380e2cb1decSSalil Mehta static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 381e2cb1decSSalil Mehta { 382e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 383e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo; 384e2cb1decSSalil Mehta u16 new_tqps = hdev->num_tqps; 385e2cb1decSSalil Mehta int i; 386e2cb1decSSalil Mehta 387e2cb1decSSalil Mehta kinfo = &nic->kinfo; 388e2cb1decSSalil Mehta kinfo->num_tc = 0; 389c0425944SPeng Li kinfo->num_tx_desc = hdev->num_tx_desc; 390c0425944SPeng Li kinfo->num_rx_desc = hdev->num_rx_desc; 391e2cb1decSSalil Mehta kinfo->rx_buf_len = hdev->rx_buf_len; 392e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 393e2cb1decSSalil Mehta if (hdev->hw_tc_map & BIT(i)) 394e2cb1decSSalil Mehta kinfo->num_tc++; 395e2cb1decSSalil Mehta 396e2cb1decSSalil Mehta kinfo->rss_size 397e2cb1decSSalil Mehta = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 398e2cb1decSSalil Mehta new_tqps = kinfo->rss_size * kinfo->num_tc; 399e2cb1decSSalil Mehta kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 400e2cb1decSSalil Mehta 401e2cb1decSSalil Mehta kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 402e2cb1decSSalil Mehta sizeof(struct hnae3_queue *), GFP_KERNEL); 403e2cb1decSSalil Mehta if (!kinfo->tqp) 404e2cb1decSSalil Mehta return -ENOMEM; 405e2cb1decSSalil Mehta 406e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 407e2cb1decSSalil Mehta hdev->htqp[i].q.handle = &hdev->nic; 408e2cb1decSSalil Mehta hdev->htqp[i].q.tqp_index = i; 409e2cb1decSSalil Mehta kinfo->tqp[i] = &hdev->htqp[i].q; 410e2cb1decSSalil Mehta } 411e2cb1decSSalil Mehta 412e2cb1decSSalil Mehta return 0; 413e2cb1decSSalil Mehta } 414e2cb1decSSalil Mehta 415e2cb1decSSalil Mehta static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 416e2cb1decSSalil Mehta { 417e2cb1decSSalil Mehta int status; 418e2cb1decSSalil Mehta u8 resp_msg; 419e2cb1decSSalil Mehta 420e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 421e2cb1decSSalil Mehta 0, false, &resp_msg, sizeof(u8)); 422e2cb1decSSalil Mehta if (status) 423e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 424e2cb1decSSalil Mehta "VF failed to fetch link status(%d) from PF", status); 425e2cb1decSSalil Mehta } 426e2cb1decSSalil Mehta 427e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 428e2cb1decSSalil Mehta { 42945e92b7eSPeng Li struct hnae3_handle *rhandle = &hdev->roce; 430e2cb1decSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 43145e92b7eSPeng Li struct hnae3_client *rclient; 432e2cb1decSSalil Mehta struct hnae3_client *client; 433e2cb1decSSalil Mehta 434e2cb1decSSalil Mehta client = handle->client; 43545e92b7eSPeng Li rclient = hdev->roce_client; 436e2cb1decSSalil Mehta 437582d37bbSPeng Li link_state = 438582d37bbSPeng Li test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 439582d37bbSPeng Li 440e2cb1decSSalil Mehta if (link_state != hdev->hw.mac.link) { 441e2cb1decSSalil Mehta client->ops->link_status_change(handle, !!link_state); 44245e92b7eSPeng Li if (rclient && rclient->ops->link_status_change) 44345e92b7eSPeng Li rclient->ops->link_status_change(rhandle, !!link_state); 444e2cb1decSSalil Mehta hdev->hw.mac.link = link_state; 445e2cb1decSSalil Mehta } 446e2cb1decSSalil Mehta } 447e2cb1decSSalil Mehta 448538abaf3SYueHaibing static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 4499194d18bSliuzhongzhu { 4509194d18bSliuzhongzhu #define HCLGEVF_ADVERTISING 0 4519194d18bSliuzhongzhu #define HCLGEVF_SUPPORTED 1 4529194d18bSliuzhongzhu u8 send_msg; 4539194d18bSliuzhongzhu u8 resp_msg; 4549194d18bSliuzhongzhu 4559194d18bSliuzhongzhu send_msg = HCLGEVF_ADVERTISING; 4569194d18bSliuzhongzhu hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, &send_msg, 4579194d18bSliuzhongzhu sizeof(u8), false, &resp_msg, sizeof(u8)); 4589194d18bSliuzhongzhu send_msg = HCLGEVF_SUPPORTED; 4599194d18bSliuzhongzhu hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, &send_msg, 4609194d18bSliuzhongzhu sizeof(u8), false, &resp_msg, sizeof(u8)); 4619194d18bSliuzhongzhu } 4629194d18bSliuzhongzhu 463e2cb1decSSalil Mehta static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 464e2cb1decSSalil Mehta { 465e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 466e2cb1decSSalil Mehta int ret; 467e2cb1decSSalil Mehta 468e2cb1decSSalil Mehta nic->ae_algo = &ae_algovf; 469e2cb1decSSalil Mehta nic->pdev = hdev->pdev; 470e2cb1decSSalil Mehta nic->numa_node_mask = hdev->numa_node_mask; 471424eb834SSalil Mehta nic->flags |= HNAE3_SUPPORT_VF; 472e2cb1decSSalil Mehta 473e2cb1decSSalil Mehta ret = hclgevf_knic_setup(hdev); 474e2cb1decSSalil Mehta if (ret) 475e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 476e2cb1decSSalil Mehta ret); 477e2cb1decSSalil Mehta return ret; 478e2cb1decSSalil Mehta } 479e2cb1decSSalil Mehta 480e2cb1decSSalil Mehta static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 481e2cb1decSSalil Mehta { 48236cbbdf6SPeng Li if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 48336cbbdf6SPeng Li dev_warn(&hdev->pdev->dev, 48436cbbdf6SPeng Li "vector(vector_id %d) has been freed.\n", vector_id); 48536cbbdf6SPeng Li return; 48636cbbdf6SPeng Li } 48736cbbdf6SPeng Li 488e2cb1decSSalil Mehta hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 489e2cb1decSSalil Mehta hdev->num_msi_left += 1; 490e2cb1decSSalil Mehta hdev->num_msi_used -= 1; 491e2cb1decSSalil Mehta } 492e2cb1decSSalil Mehta 493e2cb1decSSalil Mehta static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 494e2cb1decSSalil Mehta struct hnae3_vector_info *vector_info) 495e2cb1decSSalil Mehta { 496e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 497e2cb1decSSalil Mehta struct hnae3_vector_info *vector = vector_info; 498e2cb1decSSalil Mehta int alloc = 0; 499e2cb1decSSalil Mehta int i, j; 500e2cb1decSSalil Mehta 501e2cb1decSSalil Mehta vector_num = min(hdev->num_msi_left, vector_num); 502e2cb1decSSalil Mehta 503e2cb1decSSalil Mehta for (j = 0; j < vector_num; j++) { 504e2cb1decSSalil Mehta for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 505e2cb1decSSalil Mehta if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 506e2cb1decSSalil Mehta vector->vector = pci_irq_vector(hdev->pdev, i); 507e2cb1decSSalil Mehta vector->io_addr = hdev->hw.io_base + 508e2cb1decSSalil Mehta HCLGEVF_VECTOR_REG_BASE + 509e2cb1decSSalil Mehta (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 510e2cb1decSSalil Mehta hdev->vector_status[i] = 0; 511e2cb1decSSalil Mehta hdev->vector_irq[i] = vector->vector; 512e2cb1decSSalil Mehta 513e2cb1decSSalil Mehta vector++; 514e2cb1decSSalil Mehta alloc++; 515e2cb1decSSalil Mehta 516e2cb1decSSalil Mehta break; 517e2cb1decSSalil Mehta } 518e2cb1decSSalil Mehta } 519e2cb1decSSalil Mehta } 520e2cb1decSSalil Mehta hdev->num_msi_left -= alloc; 521e2cb1decSSalil Mehta hdev->num_msi_used += alloc; 522e2cb1decSSalil Mehta 523e2cb1decSSalil Mehta return alloc; 524e2cb1decSSalil Mehta } 525e2cb1decSSalil Mehta 526e2cb1decSSalil Mehta static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 527e2cb1decSSalil Mehta { 528e2cb1decSSalil Mehta int i; 529e2cb1decSSalil Mehta 530e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 531e2cb1decSSalil Mehta if (vector == hdev->vector_irq[i]) 532e2cb1decSSalil Mehta return i; 533e2cb1decSSalil Mehta 534e2cb1decSSalil Mehta return -EINVAL; 535e2cb1decSSalil Mehta } 536e2cb1decSSalil Mehta 537374ad291SJian Shen static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 538374ad291SJian Shen const u8 hfunc, const u8 *key) 539374ad291SJian Shen { 540374ad291SJian Shen struct hclgevf_rss_config_cmd *req; 541374ad291SJian Shen struct hclgevf_desc desc; 542374ad291SJian Shen int key_offset; 543374ad291SJian Shen int key_size; 544374ad291SJian Shen int ret; 545374ad291SJian Shen 546374ad291SJian Shen req = (struct hclgevf_rss_config_cmd *)desc.data; 547374ad291SJian Shen 548374ad291SJian Shen for (key_offset = 0; key_offset < 3; key_offset++) { 549374ad291SJian Shen hclgevf_cmd_setup_basic_desc(&desc, 550374ad291SJian Shen HCLGEVF_OPC_RSS_GENERIC_CONFIG, 551374ad291SJian Shen false); 552374ad291SJian Shen 553374ad291SJian Shen req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 554374ad291SJian Shen req->hash_config |= 555374ad291SJian Shen (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 556374ad291SJian Shen 557374ad291SJian Shen if (key_offset == 2) 558374ad291SJian Shen key_size = 559374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE - HCLGEVF_RSS_HASH_KEY_NUM * 2; 560374ad291SJian Shen else 561374ad291SJian Shen key_size = HCLGEVF_RSS_HASH_KEY_NUM; 562374ad291SJian Shen 563374ad291SJian Shen memcpy(req->hash_key, 564374ad291SJian Shen key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 565374ad291SJian Shen 566374ad291SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 567374ad291SJian Shen if (ret) { 568374ad291SJian Shen dev_err(&hdev->pdev->dev, 569374ad291SJian Shen "Configure RSS config fail, status = %d\n", 570374ad291SJian Shen ret); 571374ad291SJian Shen return ret; 572374ad291SJian Shen } 573374ad291SJian Shen } 574374ad291SJian Shen 575374ad291SJian Shen return 0; 576374ad291SJian Shen } 577374ad291SJian Shen 578e2cb1decSSalil Mehta static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 579e2cb1decSSalil Mehta { 580e2cb1decSSalil Mehta return HCLGEVF_RSS_KEY_SIZE; 581e2cb1decSSalil Mehta } 582e2cb1decSSalil Mehta 583e2cb1decSSalil Mehta static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 584e2cb1decSSalil Mehta { 585e2cb1decSSalil Mehta return HCLGEVF_RSS_IND_TBL_SIZE; 586e2cb1decSSalil Mehta } 587e2cb1decSSalil Mehta 588e2cb1decSSalil Mehta static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 589e2cb1decSSalil Mehta { 590e2cb1decSSalil Mehta const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 591e2cb1decSSalil Mehta struct hclgevf_rss_indirection_table_cmd *req; 592e2cb1decSSalil Mehta struct hclgevf_desc desc; 593e2cb1decSSalil Mehta int status; 594e2cb1decSSalil Mehta int i, j; 595e2cb1decSSalil Mehta 596e2cb1decSSalil Mehta req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 597e2cb1decSSalil Mehta 598e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 599e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 600e2cb1decSSalil Mehta false); 601e2cb1decSSalil Mehta req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 602e2cb1decSSalil Mehta req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 603e2cb1decSSalil Mehta for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 604e2cb1decSSalil Mehta req->rss_result[j] = 605e2cb1decSSalil Mehta indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 606e2cb1decSSalil Mehta 607e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 608e2cb1decSSalil Mehta if (status) { 609e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 610e2cb1decSSalil Mehta "VF failed(=%d) to set RSS indirection table\n", 611e2cb1decSSalil Mehta status); 612e2cb1decSSalil Mehta return status; 613e2cb1decSSalil Mehta } 614e2cb1decSSalil Mehta } 615e2cb1decSSalil Mehta 616e2cb1decSSalil Mehta return 0; 617e2cb1decSSalil Mehta } 618e2cb1decSSalil Mehta 619e2cb1decSSalil Mehta static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 620e2cb1decSSalil Mehta { 621e2cb1decSSalil Mehta struct hclgevf_rss_tc_mode_cmd *req; 622e2cb1decSSalil Mehta u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 623e2cb1decSSalil Mehta u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 624e2cb1decSSalil Mehta u16 tc_size[HCLGEVF_MAX_TC_NUM]; 625e2cb1decSSalil Mehta struct hclgevf_desc desc; 626e2cb1decSSalil Mehta u16 roundup_size; 627e2cb1decSSalil Mehta int status; 628e2cb1decSSalil Mehta int i; 629e2cb1decSSalil Mehta 630e2cb1decSSalil Mehta req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 631e2cb1decSSalil Mehta 632e2cb1decSSalil Mehta roundup_size = roundup_pow_of_two(rss_size); 633e2cb1decSSalil Mehta roundup_size = ilog2(roundup_size); 634e2cb1decSSalil Mehta 635e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 636e2cb1decSSalil Mehta tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 637e2cb1decSSalil Mehta tc_size[i] = roundup_size; 638e2cb1decSSalil Mehta tc_offset[i] = rss_size * i; 639e2cb1decSSalil Mehta } 640e2cb1decSSalil Mehta 641e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 642e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 643e4e87715SPeng Li hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 644e2cb1decSSalil Mehta (tc_valid[i] & 0x1)); 645e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 646e2cb1decSSalil Mehta HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 647e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 648e2cb1decSSalil Mehta HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 649e2cb1decSSalil Mehta } 650e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 651e2cb1decSSalil Mehta if (status) 652e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 653e2cb1decSSalil Mehta "VF failed(=%d) to set rss tc mode\n", status); 654e2cb1decSSalil Mehta 655e2cb1decSSalil Mehta return status; 656e2cb1decSSalil Mehta } 657e2cb1decSSalil Mehta 658a638b1d8SJian Shen /* for revision 0x20, vf shared the same rss config with pf */ 659a638b1d8SJian Shen static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 660a638b1d8SJian Shen { 661a638b1d8SJian Shen #define HCLGEVF_RSS_MBX_RESP_LEN 8 662a638b1d8SJian Shen 663a638b1d8SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 664a638b1d8SJian Shen u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 665a638b1d8SJian Shen u16 msg_num, hash_key_index; 666a638b1d8SJian Shen u8 index; 667a638b1d8SJian Shen int ret; 668a638b1d8SJian Shen 669a638b1d8SJian Shen msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 670a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN; 671a638b1d8SJian Shen for (index = 0; index < msg_num; index++) { 672a638b1d8SJian Shen ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_RSS_KEY, 0, 673a638b1d8SJian Shen &index, sizeof(index), 674a638b1d8SJian Shen true, resp_msg, 675a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN); 676a638b1d8SJian Shen if (ret) { 677a638b1d8SJian Shen dev_err(&hdev->pdev->dev, 678a638b1d8SJian Shen "VF get rss hash key from PF failed, ret=%d", 679a638b1d8SJian Shen ret); 680a638b1d8SJian Shen return ret; 681a638b1d8SJian Shen } 682a638b1d8SJian Shen 683a638b1d8SJian Shen hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 684a638b1d8SJian Shen if (index == msg_num - 1) 685a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 686a638b1d8SJian Shen &resp_msg[0], 687a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE - hash_key_index); 688a638b1d8SJian Shen else 689a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 690a638b1d8SJian Shen &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 691a638b1d8SJian Shen } 692a638b1d8SJian Shen 693a638b1d8SJian Shen return 0; 694a638b1d8SJian Shen } 695a638b1d8SJian Shen 696e2cb1decSSalil Mehta static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 697e2cb1decSSalil Mehta u8 *hfunc) 698e2cb1decSSalil Mehta { 699e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 700e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 701a638b1d8SJian Shen int i, ret; 702e2cb1decSSalil Mehta 703374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 704374ad291SJian Shen /* Get hash algorithm */ 705374ad291SJian Shen if (hfunc) { 706374ad291SJian Shen switch (rss_cfg->hash_algo) { 707374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 708374ad291SJian Shen *hfunc = ETH_RSS_HASH_TOP; 709374ad291SJian Shen break; 710374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 711374ad291SJian Shen *hfunc = ETH_RSS_HASH_XOR; 712374ad291SJian Shen break; 713374ad291SJian Shen default: 714374ad291SJian Shen *hfunc = ETH_RSS_HASH_UNKNOWN; 715374ad291SJian Shen break; 716374ad291SJian Shen } 717374ad291SJian Shen } 718374ad291SJian Shen 719374ad291SJian Shen /* Get the RSS Key required by the user */ 720374ad291SJian Shen if (key) 721374ad291SJian Shen memcpy(key, rss_cfg->rss_hash_key, 722374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 723a638b1d8SJian Shen } else { 724a638b1d8SJian Shen if (hfunc) 725a638b1d8SJian Shen *hfunc = ETH_RSS_HASH_TOP; 726a638b1d8SJian Shen if (key) { 727a638b1d8SJian Shen ret = hclgevf_get_rss_hash_key(hdev); 728a638b1d8SJian Shen if (ret) 729a638b1d8SJian Shen return ret; 730a638b1d8SJian Shen memcpy(key, rss_cfg->rss_hash_key, 731a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE); 732a638b1d8SJian Shen } 733374ad291SJian Shen } 734374ad291SJian Shen 735e2cb1decSSalil Mehta if (indir) 736e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 737e2cb1decSSalil Mehta indir[i] = rss_cfg->rss_indirection_tbl[i]; 738e2cb1decSSalil Mehta 739374ad291SJian Shen return 0; 740e2cb1decSSalil Mehta } 741e2cb1decSSalil Mehta 742e2cb1decSSalil Mehta static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 743e2cb1decSSalil Mehta const u8 *key, const u8 hfunc) 744e2cb1decSSalil Mehta { 745e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 746e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 747374ad291SJian Shen int ret, i; 748374ad291SJian Shen 749374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 750374ad291SJian Shen /* Set the RSS Hash Key if specififed by the user */ 751374ad291SJian Shen if (key) { 752374ad291SJian Shen switch (hfunc) { 753374ad291SJian Shen case ETH_RSS_HASH_TOP: 754374ad291SJian Shen rss_cfg->hash_algo = 755374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 756374ad291SJian Shen break; 757374ad291SJian Shen case ETH_RSS_HASH_XOR: 758374ad291SJian Shen rss_cfg->hash_algo = 759374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_SIMPLE; 760374ad291SJian Shen break; 761374ad291SJian Shen case ETH_RSS_HASH_NO_CHANGE: 762374ad291SJian Shen break; 763374ad291SJian Shen default: 764374ad291SJian Shen return -EINVAL; 765374ad291SJian Shen } 766374ad291SJian Shen 767374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 768374ad291SJian Shen key); 769374ad291SJian Shen if (ret) 770374ad291SJian Shen return ret; 771374ad291SJian Shen 772374ad291SJian Shen /* Update the shadow RSS key with user specified qids */ 773374ad291SJian Shen memcpy(rss_cfg->rss_hash_key, key, 774374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 775374ad291SJian Shen } 776374ad291SJian Shen } 777e2cb1decSSalil Mehta 778e2cb1decSSalil Mehta /* update the shadow RSS table with user specified qids */ 779e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 780e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = indir[i]; 781e2cb1decSSalil Mehta 782e2cb1decSSalil Mehta /* update the hardware */ 783e2cb1decSSalil Mehta return hclgevf_set_rss_indir_table(hdev); 784e2cb1decSSalil Mehta } 785e2cb1decSSalil Mehta 786d97b3072SJian Shen static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 787d97b3072SJian Shen { 788d97b3072SJian Shen u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 789d97b3072SJian Shen 790d97b3072SJian Shen if (nfc->data & RXH_L4_B_2_3) 791d97b3072SJian Shen hash_sets |= HCLGEVF_D_PORT_BIT; 792d97b3072SJian Shen else 793d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_PORT_BIT; 794d97b3072SJian Shen 795d97b3072SJian Shen if (nfc->data & RXH_IP_SRC) 796d97b3072SJian Shen hash_sets |= HCLGEVF_S_IP_BIT; 797d97b3072SJian Shen else 798d97b3072SJian Shen hash_sets &= ~HCLGEVF_S_IP_BIT; 799d97b3072SJian Shen 800d97b3072SJian Shen if (nfc->data & RXH_IP_DST) 801d97b3072SJian Shen hash_sets |= HCLGEVF_D_IP_BIT; 802d97b3072SJian Shen else 803d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_IP_BIT; 804d97b3072SJian Shen 805d97b3072SJian Shen if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 806d97b3072SJian Shen hash_sets |= HCLGEVF_V_TAG_BIT; 807d97b3072SJian Shen 808d97b3072SJian Shen return hash_sets; 809d97b3072SJian Shen } 810d97b3072SJian Shen 811d97b3072SJian Shen static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 812d97b3072SJian Shen struct ethtool_rxnfc *nfc) 813d97b3072SJian Shen { 814d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 815d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 816d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 817d97b3072SJian Shen struct hclgevf_desc desc; 818d97b3072SJian Shen u8 tuple_sets; 819d97b3072SJian Shen int ret; 820d97b3072SJian Shen 821d97b3072SJian Shen if (handle->pdev->revision == 0x20) 822d97b3072SJian Shen return -EOPNOTSUPP; 823d97b3072SJian Shen 824d97b3072SJian Shen if (nfc->data & 825d97b3072SJian Shen ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 826d97b3072SJian Shen return -EINVAL; 827d97b3072SJian Shen 828d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 829d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 830d97b3072SJian Shen 831d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 832d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 833d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 834d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 835d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 836d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 837d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 838d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 839d97b3072SJian Shen 840d97b3072SJian Shen tuple_sets = hclgevf_get_rss_hash_bits(nfc); 841d97b3072SJian Shen switch (nfc->flow_type) { 842d97b3072SJian Shen case TCP_V4_FLOW: 843d97b3072SJian Shen req->ipv4_tcp_en = tuple_sets; 844d97b3072SJian Shen break; 845d97b3072SJian Shen case TCP_V6_FLOW: 846d97b3072SJian Shen req->ipv6_tcp_en = tuple_sets; 847d97b3072SJian Shen break; 848d97b3072SJian Shen case UDP_V4_FLOW: 849d97b3072SJian Shen req->ipv4_udp_en = tuple_sets; 850d97b3072SJian Shen break; 851d97b3072SJian Shen case UDP_V6_FLOW: 852d97b3072SJian Shen req->ipv6_udp_en = tuple_sets; 853d97b3072SJian Shen break; 854d97b3072SJian Shen case SCTP_V4_FLOW: 855d97b3072SJian Shen req->ipv4_sctp_en = tuple_sets; 856d97b3072SJian Shen break; 857d97b3072SJian Shen case SCTP_V6_FLOW: 858d97b3072SJian Shen if ((nfc->data & RXH_L4_B_0_1) || 859d97b3072SJian Shen (nfc->data & RXH_L4_B_2_3)) 860d97b3072SJian Shen return -EINVAL; 861d97b3072SJian Shen 862d97b3072SJian Shen req->ipv6_sctp_en = tuple_sets; 863d97b3072SJian Shen break; 864d97b3072SJian Shen case IPV4_FLOW: 865d97b3072SJian Shen req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 866d97b3072SJian Shen break; 867d97b3072SJian Shen case IPV6_FLOW: 868d97b3072SJian Shen req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 869d97b3072SJian Shen break; 870d97b3072SJian Shen default: 871d97b3072SJian Shen return -EINVAL; 872d97b3072SJian Shen } 873d97b3072SJian Shen 874d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 875d97b3072SJian Shen if (ret) { 876d97b3072SJian Shen dev_err(&hdev->pdev->dev, 877d97b3072SJian Shen "Set rss tuple fail, status = %d\n", ret); 878d97b3072SJian Shen return ret; 879d97b3072SJian Shen } 880d97b3072SJian Shen 881d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 882d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 883d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 884d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 885d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 886d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 887d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 888d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 889d97b3072SJian Shen return 0; 890d97b3072SJian Shen } 891d97b3072SJian Shen 892d97b3072SJian Shen static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 893d97b3072SJian Shen struct ethtool_rxnfc *nfc) 894d97b3072SJian Shen { 895d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 896d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 897d97b3072SJian Shen u8 tuple_sets; 898d97b3072SJian Shen 899d97b3072SJian Shen if (handle->pdev->revision == 0x20) 900d97b3072SJian Shen return -EOPNOTSUPP; 901d97b3072SJian Shen 902d97b3072SJian Shen nfc->data = 0; 903d97b3072SJian Shen 904d97b3072SJian Shen switch (nfc->flow_type) { 905d97b3072SJian Shen case TCP_V4_FLOW: 906d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 907d97b3072SJian Shen break; 908d97b3072SJian Shen case UDP_V4_FLOW: 909d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 910d97b3072SJian Shen break; 911d97b3072SJian Shen case TCP_V6_FLOW: 912d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 913d97b3072SJian Shen break; 914d97b3072SJian Shen case UDP_V6_FLOW: 915d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 916d97b3072SJian Shen break; 917d97b3072SJian Shen case SCTP_V4_FLOW: 918d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 919d97b3072SJian Shen break; 920d97b3072SJian Shen case SCTP_V6_FLOW: 921d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 922d97b3072SJian Shen break; 923d97b3072SJian Shen case IPV4_FLOW: 924d97b3072SJian Shen case IPV6_FLOW: 925d97b3072SJian Shen tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 926d97b3072SJian Shen break; 927d97b3072SJian Shen default: 928d97b3072SJian Shen return -EINVAL; 929d97b3072SJian Shen } 930d97b3072SJian Shen 931d97b3072SJian Shen if (!tuple_sets) 932d97b3072SJian Shen return 0; 933d97b3072SJian Shen 934d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_PORT_BIT) 935d97b3072SJian Shen nfc->data |= RXH_L4_B_2_3; 936d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_PORT_BIT) 937d97b3072SJian Shen nfc->data |= RXH_L4_B_0_1; 938d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_IP_BIT) 939d97b3072SJian Shen nfc->data |= RXH_IP_DST; 940d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_IP_BIT) 941d97b3072SJian Shen nfc->data |= RXH_IP_SRC; 942d97b3072SJian Shen 943d97b3072SJian Shen return 0; 944d97b3072SJian Shen } 945d97b3072SJian Shen 946d97b3072SJian Shen static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 947d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg) 948d97b3072SJian Shen { 949d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 950d97b3072SJian Shen struct hclgevf_desc desc; 951d97b3072SJian Shen int ret; 952d97b3072SJian Shen 953d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 954d97b3072SJian Shen 955d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 956d97b3072SJian Shen 957d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 958d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 959d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 960d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 961d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 962d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 963d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 964d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 965d97b3072SJian Shen 966d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 967d97b3072SJian Shen if (ret) 968d97b3072SJian Shen dev_err(&hdev->pdev->dev, 969d97b3072SJian Shen "Configure rss input fail, status = %d\n", ret); 970d97b3072SJian Shen return ret; 971d97b3072SJian Shen } 972d97b3072SJian Shen 973e2cb1decSSalil Mehta static int hclgevf_get_tc_size(struct hnae3_handle *handle) 974e2cb1decSSalil Mehta { 975e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 976e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 977e2cb1decSSalil Mehta 978e2cb1decSSalil Mehta return rss_cfg->rss_size; 979e2cb1decSSalil Mehta } 980e2cb1decSSalil Mehta 981e2cb1decSSalil Mehta static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 982b204bc74SPeng Li int vector_id, 983e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 984e2cb1decSSalil Mehta { 985e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 986e2cb1decSSalil Mehta struct hnae3_ring_chain_node *node; 987e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 988e2cb1decSSalil Mehta struct hclgevf_desc desc; 989b204bc74SPeng Li int i = 0; 990e2cb1decSSalil Mehta int status; 991e2cb1decSSalil Mehta u8 type; 992e2cb1decSSalil Mehta 993e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 994e2cb1decSSalil Mehta 995e2cb1decSSalil Mehta for (node = ring_chain; node; node = node->next) { 9965d02a58dSYunsheng Lin int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 9975d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 9985d02a58dSYunsheng Lin 9995d02a58dSYunsheng Lin if (i == 0) { 10005d02a58dSYunsheng Lin hclgevf_cmd_setup_basic_desc(&desc, 10015d02a58dSYunsheng Lin HCLGEVF_OPC_MBX_VF_TO_PF, 10025d02a58dSYunsheng Lin false); 10035d02a58dSYunsheng Lin type = en ? 10045d02a58dSYunsheng Lin HCLGE_MBX_MAP_RING_TO_VECTOR : 10055d02a58dSYunsheng Lin HCLGE_MBX_UNMAP_RING_TO_VECTOR; 10065d02a58dSYunsheng Lin req->msg[0] = type; 10075d02a58dSYunsheng Lin req->msg[1] = vector_id; 10085d02a58dSYunsheng Lin } 10095d02a58dSYunsheng Lin 10105d02a58dSYunsheng Lin req->msg[idx_offset] = 1011e4e87715SPeng Li hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 10125d02a58dSYunsheng Lin req->msg[idx_offset + 1] = node->tqp_index; 1013e4e87715SPeng Li req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 101479eee410SFuyun Liang HNAE3_RING_GL_IDX_M, 101579eee410SFuyun Liang HNAE3_RING_GL_IDX_S); 101679eee410SFuyun Liang 10175d02a58dSYunsheng Lin i++; 10185d02a58dSYunsheng Lin if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 10195d02a58dSYunsheng Lin HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 10205d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 10215d02a58dSYunsheng Lin !node->next) { 1022e2cb1decSSalil Mehta req->msg[2] = i; 1023e2cb1decSSalil Mehta 1024e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1025e2cb1decSSalil Mehta if (status) { 1026e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1027e2cb1decSSalil Mehta "Map TQP fail, status is %d.\n", 1028e2cb1decSSalil Mehta status); 1029e2cb1decSSalil Mehta return status; 1030e2cb1decSSalil Mehta } 1031e2cb1decSSalil Mehta i = 0; 1032e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 1033e2cb1decSSalil Mehta HCLGEVF_OPC_MBX_VF_TO_PF, 1034e2cb1decSSalil Mehta false); 1035e2cb1decSSalil Mehta req->msg[0] = type; 1036e2cb1decSSalil Mehta req->msg[1] = vector_id; 1037e2cb1decSSalil Mehta } 1038e2cb1decSSalil Mehta } 1039e2cb1decSSalil Mehta 1040e2cb1decSSalil Mehta return 0; 1041e2cb1decSSalil Mehta } 1042e2cb1decSSalil Mehta 1043e2cb1decSSalil Mehta static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1044e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1045e2cb1decSSalil Mehta { 1046b204bc74SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1047b204bc74SPeng Li int vector_id; 1048b204bc74SPeng Li 1049b204bc74SPeng Li vector_id = hclgevf_get_vector_index(hdev, vector); 1050b204bc74SPeng Li if (vector_id < 0) { 1051b204bc74SPeng Li dev_err(&handle->pdev->dev, 1052b204bc74SPeng Li "Get vector index fail. ret =%d\n", vector_id); 1053b204bc74SPeng Li return vector_id; 1054b204bc74SPeng Li } 1055b204bc74SPeng Li 1056b204bc74SPeng Li return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1057e2cb1decSSalil Mehta } 1058e2cb1decSSalil Mehta 1059e2cb1decSSalil Mehta static int hclgevf_unmap_ring_from_vector( 1060e2cb1decSSalil Mehta struct hnae3_handle *handle, 1061e2cb1decSSalil Mehta int vector, 1062e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1063e2cb1decSSalil Mehta { 1064e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1065e2cb1decSSalil Mehta int ret, vector_id; 1066e2cb1decSSalil Mehta 1067dea846e8SHuazhong Tan if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1068dea846e8SHuazhong Tan return 0; 1069dea846e8SHuazhong Tan 1070e2cb1decSSalil Mehta vector_id = hclgevf_get_vector_index(hdev, vector); 1071e2cb1decSSalil Mehta if (vector_id < 0) { 1072e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1073e2cb1decSSalil Mehta "Get vector index fail. ret =%d\n", vector_id); 1074e2cb1decSSalil Mehta return vector_id; 1075e2cb1decSSalil Mehta } 1076e2cb1decSSalil Mehta 1077b204bc74SPeng Li ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 10780d3e6631SYunsheng Lin if (ret) 1079e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1080e2cb1decSSalil Mehta "Unmap ring from vector fail. vector=%d, ret =%d\n", 1081e2cb1decSSalil Mehta vector_id, 1082e2cb1decSSalil Mehta ret); 10830d3e6631SYunsheng Lin 1084e2cb1decSSalil Mehta return ret; 1085e2cb1decSSalil Mehta } 1086e2cb1decSSalil Mehta 10870d3e6631SYunsheng Lin static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 10880d3e6631SYunsheng Lin { 10890d3e6631SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 109003718db9SYunsheng Lin int vector_id; 10910d3e6631SYunsheng Lin 109203718db9SYunsheng Lin vector_id = hclgevf_get_vector_index(hdev, vector); 109303718db9SYunsheng Lin if (vector_id < 0) { 109403718db9SYunsheng Lin dev_err(&handle->pdev->dev, 109503718db9SYunsheng Lin "hclgevf_put_vector get vector index fail. ret =%d\n", 109603718db9SYunsheng Lin vector_id); 109703718db9SYunsheng Lin return vector_id; 109803718db9SYunsheng Lin } 109903718db9SYunsheng Lin 110003718db9SYunsheng Lin hclgevf_free_vector(hdev, vector_id); 1101e2cb1decSSalil Mehta 1102e2cb1decSSalil Mehta return 0; 1103e2cb1decSSalil Mehta } 1104e2cb1decSSalil Mehta 11053b75c3dfSPeng Li static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1106f01f5559SJian Shen bool en_bc_pmc) 1107e2cb1decSSalil Mehta { 1108e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 1109e2cb1decSSalil Mehta struct hclgevf_desc desc; 1110f01f5559SJian Shen int ret; 1111e2cb1decSSalil Mehta 1112e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1113e2cb1decSSalil Mehta 1114e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 1115e2cb1decSSalil Mehta req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 1116f01f5559SJian Shen req->msg[1] = en_bc_pmc ? 1 : 0; 1117e2cb1decSSalil Mehta 1118f01f5559SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1119f01f5559SJian Shen if (ret) 1120e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1121f01f5559SJian Shen "Set promisc mode fail, status is %d.\n", ret); 1122e2cb1decSSalil Mehta 1123f01f5559SJian Shen return ret; 1124e2cb1decSSalil Mehta } 1125e2cb1decSSalil Mehta 1126f01f5559SJian Shen static int hclgevf_set_promisc_mode(struct hclgevf_dev *hdev, bool en_bc_pmc) 1127e2cb1decSSalil Mehta { 1128f01f5559SJian Shen return hclgevf_cmd_set_promisc_mode(hdev, en_bc_pmc); 1129e2cb1decSSalil Mehta } 1130e2cb1decSSalil Mehta 1131e2cb1decSSalil Mehta static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, int tqp_id, 1132e2cb1decSSalil Mehta int stream_id, bool enable) 1133e2cb1decSSalil Mehta { 1134e2cb1decSSalil Mehta struct hclgevf_cfg_com_tqp_queue_cmd *req; 1135e2cb1decSSalil Mehta struct hclgevf_desc desc; 1136e2cb1decSSalil Mehta int status; 1137e2cb1decSSalil Mehta 1138e2cb1decSSalil Mehta req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1139e2cb1decSSalil Mehta 1140e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1141e2cb1decSSalil Mehta false); 1142e2cb1decSSalil Mehta req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1143e2cb1decSSalil Mehta req->stream_id = cpu_to_le16(stream_id); 1144e2cb1decSSalil Mehta req->enable |= enable << HCLGEVF_TQP_ENABLE_B; 1145e2cb1decSSalil Mehta 1146e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1147e2cb1decSSalil Mehta if (status) 1148e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1149e2cb1decSSalil Mehta "TQP enable fail, status =%d.\n", status); 1150e2cb1decSSalil Mehta 1151e2cb1decSSalil Mehta return status; 1152e2cb1decSSalil Mehta } 1153e2cb1decSSalil Mehta 1154e2cb1decSSalil Mehta static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1155e2cb1decSSalil Mehta { 1156b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1157e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 1158e2cb1decSSalil Mehta int i; 1159e2cb1decSSalil Mehta 1160b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 1161b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1162e2cb1decSSalil Mehta memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1163e2cb1decSSalil Mehta } 1164e2cb1decSSalil Mehta } 1165e2cb1decSSalil Mehta 1166e2cb1decSSalil Mehta static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1167e2cb1decSSalil Mehta { 1168e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1169e2cb1decSSalil Mehta 1170e2cb1decSSalil Mehta ether_addr_copy(p, hdev->hw.mac.mac_addr); 1171e2cb1decSSalil Mehta } 1172e2cb1decSSalil Mehta 117359098055SFuyun Liang static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 117459098055SFuyun Liang bool is_first) 1175e2cb1decSSalil Mehta { 1176e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1177e2cb1decSSalil Mehta u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1178e2cb1decSSalil Mehta u8 *new_mac_addr = (u8 *)p; 1179e2cb1decSSalil Mehta u8 msg_data[ETH_ALEN * 2]; 118059098055SFuyun Liang u16 subcode; 1181e2cb1decSSalil Mehta int status; 1182e2cb1decSSalil Mehta 1183e2cb1decSSalil Mehta ether_addr_copy(msg_data, new_mac_addr); 1184e2cb1decSSalil Mehta ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 1185e2cb1decSSalil Mehta 118659098055SFuyun Liang subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 118759098055SFuyun Liang HCLGE_MBX_MAC_VLAN_UC_MODIFY; 118859098055SFuyun Liang 1189e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 119059098055SFuyun Liang subcode, msg_data, ETH_ALEN * 2, 11912097fdefSJian Shen true, NULL, 0); 1192e2cb1decSSalil Mehta if (!status) 1193e2cb1decSSalil Mehta ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1194e2cb1decSSalil Mehta 1195e2cb1decSSalil Mehta return status; 1196e2cb1decSSalil Mehta } 1197e2cb1decSSalil Mehta 1198e2cb1decSSalil Mehta static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1199e2cb1decSSalil Mehta const unsigned char *addr) 1200e2cb1decSSalil Mehta { 1201e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1202e2cb1decSSalil Mehta 1203e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1204e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_ADD, 1205e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1206e2cb1decSSalil Mehta } 1207e2cb1decSSalil Mehta 1208e2cb1decSSalil Mehta static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1209e2cb1decSSalil Mehta const unsigned char *addr) 1210e2cb1decSSalil Mehta { 1211e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1212e2cb1decSSalil Mehta 1213e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1214e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1215e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1216e2cb1decSSalil Mehta } 1217e2cb1decSSalil Mehta 1218e2cb1decSSalil Mehta static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1219e2cb1decSSalil Mehta const unsigned char *addr) 1220e2cb1decSSalil Mehta { 1221e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1222e2cb1decSSalil Mehta 1223e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1224e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_ADD, 1225e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1226e2cb1decSSalil Mehta } 1227e2cb1decSSalil Mehta 1228e2cb1decSSalil Mehta static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1229e2cb1decSSalil Mehta const unsigned char *addr) 1230e2cb1decSSalil Mehta { 1231e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1232e2cb1decSSalil Mehta 1233e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1234e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1235e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1236e2cb1decSSalil Mehta } 1237e2cb1decSSalil Mehta 1238e2cb1decSSalil Mehta static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1239e2cb1decSSalil Mehta __be16 proto, u16 vlan_id, 1240e2cb1decSSalil Mehta bool is_kill) 1241e2cb1decSSalil Mehta { 1242e2cb1decSSalil Mehta #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1243e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1244e2cb1decSSalil Mehta u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1245e2cb1decSSalil Mehta 1246b37ce587SYufeng Mo if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1247e2cb1decSSalil Mehta return -EINVAL; 1248e2cb1decSSalil Mehta 1249e2cb1decSSalil Mehta if (proto != htons(ETH_P_8021Q)) 1250e2cb1decSSalil Mehta return -EPROTONOSUPPORT; 1251e2cb1decSSalil Mehta 1252e2cb1decSSalil Mehta msg_data[0] = is_kill; 1253e2cb1decSSalil Mehta memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1254e2cb1decSSalil Mehta memcpy(&msg_data[3], &proto, sizeof(proto)); 1255e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1256e2cb1decSSalil Mehta HCLGE_MBX_VLAN_FILTER, msg_data, 1257e2cb1decSSalil Mehta HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 1258e2cb1decSSalil Mehta } 1259e2cb1decSSalil Mehta 1260b2641e2aSYunsheng Lin static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1261b2641e2aSYunsheng Lin { 1262b2641e2aSYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1263b2641e2aSYunsheng Lin u8 msg_data; 1264b2641e2aSYunsheng Lin 1265b2641e2aSYunsheng Lin msg_data = enable ? 1 : 0; 1266b2641e2aSYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1267b2641e2aSYunsheng Lin HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1268b2641e2aSYunsheng Lin 1, false, NULL, 0); 1269b2641e2aSYunsheng Lin } 1270b2641e2aSYunsheng Lin 12717fa6be4fSHuazhong Tan static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1272e2cb1decSSalil Mehta { 1273e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1274e2cb1decSSalil Mehta u8 msg_data[2]; 12751a426f8bSPeng Li int ret; 1276e2cb1decSSalil Mehta 1277e2cb1decSSalil Mehta memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 1278e2cb1decSSalil Mehta 12791a426f8bSPeng Li /* disable vf queue before send queue reset msg to PF */ 12801a426f8bSPeng Li ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 12811a426f8bSPeng Li if (ret) 12827fa6be4fSHuazhong Tan return ret; 12831a426f8bSPeng Li 12847fa6be4fSHuazhong Tan return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 12851a426f8bSPeng Li 2, true, NULL, 0); 1286e2cb1decSSalil Mehta } 1287e2cb1decSSalil Mehta 1288818f1675SYunsheng Lin static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1289818f1675SYunsheng Lin { 1290818f1675SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1291818f1675SYunsheng Lin 1292818f1675SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu, 1293818f1675SYunsheng Lin sizeof(new_mtu), true, NULL, 0); 1294818f1675SYunsheng Lin } 1295818f1675SYunsheng Lin 12966988eb2aSSalil Mehta static int hclgevf_notify_client(struct hclgevf_dev *hdev, 12976988eb2aSSalil Mehta enum hnae3_reset_notify_type type) 12986988eb2aSSalil Mehta { 12996988eb2aSSalil Mehta struct hnae3_client *client = hdev->nic_client; 13006988eb2aSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 13016a5f6fa3SHuazhong Tan int ret; 13026988eb2aSSalil Mehta 130325d1817cSHuazhong Tan if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 130425d1817cSHuazhong Tan !client) 130525d1817cSHuazhong Tan return 0; 130625d1817cSHuazhong Tan 13076988eb2aSSalil Mehta if (!client->ops->reset_notify) 13086988eb2aSSalil Mehta return -EOPNOTSUPP; 13096988eb2aSSalil Mehta 13106a5f6fa3SHuazhong Tan ret = client->ops->reset_notify(handle, type); 13116a5f6fa3SHuazhong Tan if (ret) 13126a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 13136a5f6fa3SHuazhong Tan type, ret); 13146a5f6fa3SHuazhong Tan 13156a5f6fa3SHuazhong Tan return ret; 13166988eb2aSSalil Mehta } 13176988eb2aSSalil Mehta 13186ff3cf07SHuazhong Tan static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 13196ff3cf07SHuazhong Tan { 13206ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 13216ff3cf07SHuazhong Tan 13226ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DONE, &hdev->flr_state); 13236ff3cf07SHuazhong Tan } 13246ff3cf07SHuazhong Tan 13256ff3cf07SHuazhong Tan static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev, 13266ff3cf07SHuazhong Tan unsigned long delay_us, 13276ff3cf07SHuazhong Tan unsigned long wait_cnt) 13286ff3cf07SHuazhong Tan { 13296ff3cf07SHuazhong Tan unsigned long cnt = 0; 13306ff3cf07SHuazhong Tan 13316ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) && 13326ff3cf07SHuazhong Tan cnt++ < wait_cnt) 13336ff3cf07SHuazhong Tan usleep_range(delay_us, delay_us * 2); 13346ff3cf07SHuazhong Tan 13356ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) { 13366ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 13376ff3cf07SHuazhong Tan "flr wait timeout\n"); 13386ff3cf07SHuazhong Tan return -ETIMEDOUT; 13396ff3cf07SHuazhong Tan } 13406ff3cf07SHuazhong Tan 13416ff3cf07SHuazhong Tan return 0; 13426ff3cf07SHuazhong Tan } 13436ff3cf07SHuazhong Tan 13446988eb2aSSalil Mehta static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 13456988eb2aSSalil Mehta { 1346aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_US 20000 1347aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_CNT 2000 1348aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1349aa5c4f17SHuazhong Tan (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1350aa5c4f17SHuazhong Tan 1351aa5c4f17SHuazhong Tan u32 val; 1352aa5c4f17SHuazhong Tan int ret; 13536988eb2aSSalil Mehta 13546988eb2aSSalil Mehta /* wait to check the hardware reset completion status */ 1355aa5c4f17SHuazhong Tan val = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1356aa5c4f17SHuazhong Tan dev_info(&hdev->pdev->dev, "checking vf resetting status: %x\n", val); 1357aa5c4f17SHuazhong Tan 13586ff3cf07SHuazhong Tan if (hdev->reset_type == HNAE3_FLR_RESET) 13596ff3cf07SHuazhong Tan return hclgevf_flr_poll_timeout(hdev, 13606ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_US, 13616ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_CNT); 13626ff3cf07SHuazhong Tan 1363aa5c4f17SHuazhong Tan ret = readl_poll_timeout(hdev->hw.io_base + HCLGEVF_RST_ING, val, 1364aa5c4f17SHuazhong Tan !(val & HCLGEVF_RST_ING_BITS), 1365aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_US, 1366aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 13676988eb2aSSalil Mehta 13686988eb2aSSalil Mehta /* hardware completion status should be available by this time */ 1369aa5c4f17SHuazhong Tan if (ret) { 1370aa5c4f17SHuazhong Tan dev_err(&hdev->pdev->dev, 13716988eb2aSSalil Mehta "could'nt get reset done status from h/w, timeout!\n"); 1372aa5c4f17SHuazhong Tan return ret; 13736988eb2aSSalil Mehta } 13746988eb2aSSalil Mehta 13756988eb2aSSalil Mehta /* we will wait a bit more to let reset of the stack to complete. This 13766988eb2aSSalil Mehta * might happen in case reset assertion was made by PF. Yes, this also 13776988eb2aSSalil Mehta * means we might end up waiting bit more even for VF reset. 13786988eb2aSSalil Mehta */ 13796988eb2aSSalil Mehta msleep(5000); 13806988eb2aSSalil Mehta 13816988eb2aSSalil Mehta return 0; 13826988eb2aSSalil Mehta } 13836988eb2aSSalil Mehta 13846988eb2aSSalil Mehta static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 13856988eb2aSSalil Mehta { 13867a01c897SSalil Mehta int ret; 13877a01c897SSalil Mehta 13886988eb2aSSalil Mehta /* uninitialize the nic client */ 13896a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 13906a5f6fa3SHuazhong Tan if (ret) 13916a5f6fa3SHuazhong Tan return ret; 13926988eb2aSSalil Mehta 13937a01c897SSalil Mehta /* re-initialize the hclge device */ 13949c6f7085SHuazhong Tan ret = hclgevf_reset_hdev(hdev); 13957a01c897SSalil Mehta if (ret) { 13967a01c897SSalil Mehta dev_err(&hdev->pdev->dev, 13977a01c897SSalil Mehta "hclge device re-init failed, VF is disabled!\n"); 13987a01c897SSalil Mehta return ret; 13997a01c897SSalil Mehta } 14006988eb2aSSalil Mehta 14016988eb2aSSalil Mehta /* bring up the nic client again */ 14026a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 14036a5f6fa3SHuazhong Tan if (ret) 14046a5f6fa3SHuazhong Tan return ret; 14056988eb2aSSalil Mehta 14061f609492SYunsheng Lin return hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT); 14076988eb2aSSalil Mehta } 14086988eb2aSSalil Mehta 1409dea846e8SHuazhong Tan static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1410dea846e8SHuazhong Tan { 1411ada13ee3SHuazhong Tan #define HCLGEVF_RESET_SYNC_TIME 100 1412ada13ee3SHuazhong Tan 1413dea846e8SHuazhong Tan int ret = 0; 1414dea846e8SHuazhong Tan 1415dea846e8SHuazhong Tan switch (hdev->reset_type) { 1416dea846e8SHuazhong Tan case HNAE3_VF_FUNC_RESET: 1417dea846e8SHuazhong Tan ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1418dea846e8SHuazhong Tan 0, true, NULL, sizeof(u8)); 1419c88a6e7dSHuazhong Tan hdev->rst_stats.vf_func_rst_cnt++; 1420dea846e8SHuazhong Tan break; 14216ff3cf07SHuazhong Tan case HNAE3_FLR_RESET: 14226ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1423c88a6e7dSHuazhong Tan hdev->rst_stats.flr_rst_cnt++; 14246ff3cf07SHuazhong Tan break; 1425dea846e8SHuazhong Tan default: 1426dea846e8SHuazhong Tan break; 1427dea846e8SHuazhong Tan } 1428dea846e8SHuazhong Tan 1429ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1430ada13ee3SHuazhong Tan /* inform hardware that preparatory work is done */ 1431ada13ee3SHuazhong Tan msleep(HCLGEVF_RESET_SYNC_TIME); 1432ada13ee3SHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 1433ada13ee3SHuazhong Tan HCLGEVF_NIC_CMQ_ENABLE); 1434dea846e8SHuazhong Tan dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1435dea846e8SHuazhong Tan hdev->reset_type, ret); 1436dea846e8SHuazhong Tan 1437dea846e8SHuazhong Tan return ret; 1438dea846e8SHuazhong Tan } 1439dea846e8SHuazhong Tan 14406988eb2aSSalil Mehta static int hclgevf_reset(struct hclgevf_dev *hdev) 14416988eb2aSSalil Mehta { 1442dea846e8SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 14436988eb2aSSalil Mehta int ret; 14446988eb2aSSalil Mehta 1445dea846e8SHuazhong Tan /* Initialize ae_dev reset status as well, in case enet layer wants to 1446dea846e8SHuazhong Tan * know if device is undergoing reset 1447dea846e8SHuazhong Tan */ 1448dea846e8SHuazhong Tan ae_dev->reset_type = hdev->reset_type; 1449c88a6e7dSHuazhong Tan hdev->rst_stats.rst_cnt++; 14506988eb2aSSalil Mehta rtnl_lock(); 14516988eb2aSSalil Mehta 14526988eb2aSSalil Mehta /* bring down the nic to stop any ongoing TX/RX */ 14536a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 14546a5f6fa3SHuazhong Tan if (ret) 14556a5f6fa3SHuazhong Tan goto err_reset_lock; 14566988eb2aSSalil Mehta 145729118ab9SHuazhong Tan rtnl_unlock(); 145829118ab9SHuazhong Tan 14596a5f6fa3SHuazhong Tan ret = hclgevf_reset_prepare_wait(hdev); 14606a5f6fa3SHuazhong Tan if (ret) 14616a5f6fa3SHuazhong Tan goto err_reset; 1462dea846e8SHuazhong Tan 14636988eb2aSSalil Mehta /* check if VF could successfully fetch the hardware reset completion 14646988eb2aSSalil Mehta * status from the hardware 14656988eb2aSSalil Mehta */ 14666988eb2aSSalil Mehta ret = hclgevf_reset_wait(hdev); 14676988eb2aSSalil Mehta if (ret) { 14686988eb2aSSalil Mehta /* can't do much in this situation, will disable VF */ 14696988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, 14706988eb2aSSalil Mehta "VF failed(=%d) to fetch H/W reset completion status\n", 14716988eb2aSSalil Mehta ret); 14726a5f6fa3SHuazhong Tan goto err_reset; 14736988eb2aSSalil Mehta } 14746988eb2aSSalil Mehta 1475c88a6e7dSHuazhong Tan hdev->rst_stats.hw_rst_done_cnt++; 1476c88a6e7dSHuazhong Tan 147729118ab9SHuazhong Tan rtnl_lock(); 147829118ab9SHuazhong Tan 14796988eb2aSSalil Mehta /* now, re-initialize the nic client and ae device*/ 14806988eb2aSSalil Mehta ret = hclgevf_reset_stack(hdev); 14816a5f6fa3SHuazhong Tan if (ret) { 14826988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 14836a5f6fa3SHuazhong Tan goto err_reset_lock; 14846a5f6fa3SHuazhong Tan } 14856988eb2aSSalil Mehta 14866988eb2aSSalil Mehta /* bring up the nic to enable TX/RX again */ 14876a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 14886a5f6fa3SHuazhong Tan if (ret) 14896a5f6fa3SHuazhong Tan goto err_reset_lock; 14906988eb2aSSalil Mehta 14916988eb2aSSalil Mehta rtnl_unlock(); 14926988eb2aSSalil Mehta 1493b644a8d4SHuazhong Tan hdev->last_reset_time = jiffies; 1494b644a8d4SHuazhong Tan ae_dev->reset_type = HNAE3_NONE_RESET; 1495c88a6e7dSHuazhong Tan hdev->rst_stats.rst_done_cnt++; 1496b644a8d4SHuazhong Tan 14976988eb2aSSalil Mehta return ret; 14986a5f6fa3SHuazhong Tan err_reset_lock: 14996a5f6fa3SHuazhong Tan rtnl_unlock(); 15006a5f6fa3SHuazhong Tan err_reset: 15016a5f6fa3SHuazhong Tan /* When VF reset failed, only the higher level reset asserted by PF 15026a5f6fa3SHuazhong Tan * can restore it, so re-initialize the command queue to receive 15036a5f6fa3SHuazhong Tan * this higher reset event. 15046a5f6fa3SHuazhong Tan */ 15056a5f6fa3SHuazhong Tan hclgevf_cmd_init(hdev); 15066a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "failed to reset VF\n"); 1507cf1f2129SHuazhong Tan if (hclgevf_is_reset_pending(hdev)) 1508cf1f2129SHuazhong Tan hclgevf_reset_task_schedule(hdev); 15096a5f6fa3SHuazhong Tan 15106a5f6fa3SHuazhong Tan return ret; 15116988eb2aSSalil Mehta } 15126988eb2aSSalil Mehta 1513720bd583SHuazhong Tan static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1514720bd583SHuazhong Tan unsigned long *addr) 1515720bd583SHuazhong Tan { 1516720bd583SHuazhong Tan enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1517720bd583SHuazhong Tan 1518dea846e8SHuazhong Tan /* return the highest priority reset level amongst all */ 1519b90fcc5bSHuazhong Tan if (test_bit(HNAE3_VF_RESET, addr)) { 1520b90fcc5bSHuazhong Tan rst_level = HNAE3_VF_RESET; 1521b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_RESET, addr); 1522b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1523b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1524b90fcc5bSHuazhong Tan } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1525dea846e8SHuazhong Tan rst_level = HNAE3_VF_FULL_RESET; 1526dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FULL_RESET, addr); 1527dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1528aa5c4f17SHuazhong Tan } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1529aa5c4f17SHuazhong Tan rst_level = HNAE3_VF_PF_FUNC_RESET; 1530aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1531aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1532dea846e8SHuazhong Tan } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1533dea846e8SHuazhong Tan rst_level = HNAE3_VF_FUNC_RESET; 1534dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 15356ff3cf07SHuazhong Tan } else if (test_bit(HNAE3_FLR_RESET, addr)) { 15366ff3cf07SHuazhong Tan rst_level = HNAE3_FLR_RESET; 15376ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_RESET, addr); 1538720bd583SHuazhong Tan } 1539720bd583SHuazhong Tan 1540720bd583SHuazhong Tan return rst_level; 1541720bd583SHuazhong Tan } 1542720bd583SHuazhong Tan 15436ae4e733SShiju Jose static void hclgevf_reset_event(struct pci_dev *pdev, 15446ae4e733SShiju Jose struct hnae3_handle *handle) 15456d4c3981SSalil Mehta { 15466ff3cf07SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 15476ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 15486d4c3981SSalil Mehta 15496d4c3981SSalil Mehta dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 15506d4c3981SSalil Mehta 15516ff3cf07SHuazhong Tan if (hdev->default_reset_request) 15520742ed7cSHuazhong Tan hdev->reset_level = 1553720bd583SHuazhong Tan hclgevf_get_reset_level(hdev, 1554720bd583SHuazhong Tan &hdev->default_reset_request); 1555720bd583SHuazhong Tan else 1556dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 15576d4c3981SSalil Mehta 1558436667d2SSalil Mehta /* reset of this VF requested */ 1559436667d2SSalil Mehta set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1560436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 15616d4c3981SSalil Mehta 15620742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 15636d4c3981SSalil Mehta } 15646d4c3981SSalil Mehta 1565720bd583SHuazhong Tan static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1566720bd583SHuazhong Tan enum hnae3_reset_type rst_type) 1567720bd583SHuazhong Tan { 1568720bd583SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1569720bd583SHuazhong Tan 1570720bd583SHuazhong Tan set_bit(rst_type, &hdev->default_reset_request); 1571720bd583SHuazhong Tan } 1572720bd583SHuazhong Tan 15736ff3cf07SHuazhong Tan static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 15746ff3cf07SHuazhong Tan { 15756ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_MS 100 15766ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_CNT 50 15776ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 15786ff3cf07SHuazhong Tan int cnt = 0; 15796ff3cf07SHuazhong Tan 15806ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 15816ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DONE, &hdev->flr_state); 15826ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request); 15836ff3cf07SHuazhong Tan hclgevf_reset_event(hdev->pdev, NULL); 15846ff3cf07SHuazhong Tan 15856ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) && 15866ff3cf07SHuazhong Tan cnt++ < HCLGEVF_FLR_WAIT_CNT) 15876ff3cf07SHuazhong Tan msleep(HCLGEVF_FLR_WAIT_MS); 15886ff3cf07SHuazhong Tan 15896ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state)) 15906ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 15916ff3cf07SHuazhong Tan "flr wait down timeout: %d\n", cnt); 15926ff3cf07SHuazhong Tan } 15936ff3cf07SHuazhong Tan 1594e2cb1decSSalil Mehta static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1595e2cb1decSSalil Mehta { 1596e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1597e2cb1decSSalil Mehta 1598e2cb1decSSalil Mehta return hdev->fw_version; 1599e2cb1decSSalil Mehta } 1600e2cb1decSSalil Mehta 1601e2cb1decSSalil Mehta static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1602e2cb1decSSalil Mehta { 1603e2cb1decSSalil Mehta struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1604e2cb1decSSalil Mehta 1605e2cb1decSSalil Mehta vector->vector_irq = pci_irq_vector(hdev->pdev, 1606e2cb1decSSalil Mehta HCLGEVF_MISC_VECTOR_NUM); 1607e2cb1decSSalil Mehta vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1608e2cb1decSSalil Mehta /* vector status always valid for Vector 0 */ 1609e2cb1decSSalil Mehta hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1610e2cb1decSSalil Mehta hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1611e2cb1decSSalil Mehta 1612e2cb1decSSalil Mehta hdev->num_msi_left -= 1; 1613e2cb1decSSalil Mehta hdev->num_msi_used += 1; 1614e2cb1decSSalil Mehta } 1615e2cb1decSSalil Mehta 161635a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 161735a1e503SSalil Mehta { 1618acfc3d55SHuazhong Tan if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) && 1619acfc3d55SHuazhong Tan !test_bit(HCLGEVF_STATE_REMOVING, &hdev->state)) { 162035a1e503SSalil Mehta set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 162135a1e503SSalil Mehta schedule_work(&hdev->rst_service_task); 162235a1e503SSalil Mehta } 162335a1e503SSalil Mehta } 162435a1e503SSalil Mehta 162507a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1626e2cb1decSSalil Mehta { 162707a0556aSSalil Mehta if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) && 162807a0556aSSalil Mehta !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) { 162907a0556aSSalil Mehta set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1630e2cb1decSSalil Mehta schedule_work(&hdev->mbx_service_task); 1631e2cb1decSSalil Mehta } 163207a0556aSSalil Mehta } 1633e2cb1decSSalil Mehta 1634e2cb1decSSalil Mehta static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 1635e2cb1decSSalil Mehta { 1636e2cb1decSSalil Mehta if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 1637e2cb1decSSalil Mehta !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 1638e2cb1decSSalil Mehta schedule_work(&hdev->service_task); 1639e2cb1decSSalil Mehta } 1640e2cb1decSSalil Mehta 1641436667d2SSalil Mehta static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev) 1642436667d2SSalil Mehta { 164307a0556aSSalil Mehta /* if we have any pending mailbox event then schedule the mbx task */ 164407a0556aSSalil Mehta if (hdev->mbx_event_pending) 164507a0556aSSalil Mehta hclgevf_mbx_task_schedule(hdev); 164607a0556aSSalil Mehta 1647436667d2SSalil Mehta if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state)) 1648436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 1649436667d2SSalil Mehta } 1650436667d2SSalil Mehta 1651e2cb1decSSalil Mehta static void hclgevf_service_timer(struct timer_list *t) 1652e2cb1decSSalil Mehta { 1653e2cb1decSSalil Mehta struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 1654e2cb1decSSalil Mehta 1655b37ce587SYufeng Mo mod_timer(&hdev->service_timer, jiffies + 1656b37ce587SYufeng Mo HCLGEVF_GENERAL_TASK_INTERVAL * HZ); 1657e2cb1decSSalil Mehta 1658db01afebSliuzhongzhu hdev->stats_timer++; 1659e2cb1decSSalil Mehta hclgevf_task_schedule(hdev); 1660e2cb1decSSalil Mehta } 1661e2cb1decSSalil Mehta 166235a1e503SSalil Mehta static void hclgevf_reset_service_task(struct work_struct *work) 166335a1e503SSalil Mehta { 166435a1e503SSalil Mehta struct hclgevf_dev *hdev = 166535a1e503SSalil Mehta container_of(work, struct hclgevf_dev, rst_service_task); 1666a8dedb65SSalil Mehta int ret; 166735a1e503SSalil Mehta 166835a1e503SSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 166935a1e503SSalil Mehta return; 167035a1e503SSalil Mehta 167135a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 167235a1e503SSalil Mehta 1673436667d2SSalil Mehta if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1674436667d2SSalil Mehta &hdev->reset_state)) { 1675436667d2SSalil Mehta /* PF has initmated that it is about to reset the hardware. 1676436667d2SSalil Mehta * We now have to poll & check if harware has actually completed 1677436667d2SSalil Mehta * the reset sequence. On hardware reset completion, VF needs to 1678436667d2SSalil Mehta * reset the client and ae device. 167935a1e503SSalil Mehta */ 1680436667d2SSalil Mehta hdev->reset_attempts = 0; 1681436667d2SSalil Mehta 1682dea846e8SHuazhong Tan hdev->last_reset_time = jiffies; 1683dea846e8SHuazhong Tan while ((hdev->reset_type = 1684dea846e8SHuazhong Tan hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 1685dea846e8SHuazhong Tan != HNAE3_NONE_RESET) { 16866988eb2aSSalil Mehta ret = hclgevf_reset(hdev); 16876988eb2aSSalil Mehta if (ret) 1688dea846e8SHuazhong Tan dev_err(&hdev->pdev->dev, 1689dea846e8SHuazhong Tan "VF stack reset failed %d.\n", ret); 1690dea846e8SHuazhong Tan } 1691436667d2SSalil Mehta } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1692436667d2SSalil Mehta &hdev->reset_state)) { 1693436667d2SSalil Mehta /* we could be here when either of below happens: 1694436667d2SSalil Mehta * 1. reset was initiated due to watchdog timeout due to 1695436667d2SSalil Mehta * a. IMP was earlier reset and our TX got choked down and 1696436667d2SSalil Mehta * which resulted in watchdog reacting and inducing VF 1697436667d2SSalil Mehta * reset. This also means our cmdq would be unreliable. 1698436667d2SSalil Mehta * b. problem in TX due to other lower layer(example link 1699436667d2SSalil Mehta * layer not functioning properly etc.) 1700436667d2SSalil Mehta * 2. VF reset might have been initiated due to some config 1701436667d2SSalil Mehta * change. 1702436667d2SSalil Mehta * 1703436667d2SSalil Mehta * NOTE: Theres no clear way to detect above cases than to react 1704436667d2SSalil Mehta * to the response of PF for this reset request. PF will ack the 1705436667d2SSalil Mehta * 1b and 2. cases but we will not get any intimation about 1a 1706436667d2SSalil Mehta * from PF as cmdq would be in unreliable state i.e. mailbox 1707436667d2SSalil Mehta * communication between PF and VF would be broken. 1708436667d2SSalil Mehta */ 1709436667d2SSalil Mehta 1710436667d2SSalil Mehta /* if we are never geting into pending state it means either: 1711436667d2SSalil Mehta * 1. PF is not receiving our request which could be due to IMP 1712436667d2SSalil Mehta * reset 1713436667d2SSalil Mehta * 2. PF is screwed 1714436667d2SSalil Mehta * We cannot do much for 2. but to check first we can try reset 1715436667d2SSalil Mehta * our PCIe + stack and see if it alleviates the problem. 1716436667d2SSalil Mehta */ 1717436667d2SSalil Mehta if (hdev->reset_attempts > 3) { 1718436667d2SSalil Mehta /* prepare for full reset of stack + pcie interface */ 1719dea846e8SHuazhong Tan set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1720436667d2SSalil Mehta 1721436667d2SSalil Mehta /* "defer" schedule the reset task again */ 1722436667d2SSalil Mehta set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1723436667d2SSalil Mehta } else { 1724436667d2SSalil Mehta hdev->reset_attempts++; 1725436667d2SSalil Mehta 1726dea846e8SHuazhong Tan set_bit(hdev->reset_level, &hdev->reset_pending); 1727dea846e8SHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1728436667d2SSalil Mehta } 1729dea846e8SHuazhong Tan hclgevf_reset_task_schedule(hdev); 1730436667d2SSalil Mehta } 173135a1e503SSalil Mehta 173235a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 173335a1e503SSalil Mehta } 173435a1e503SSalil Mehta 1735e2cb1decSSalil Mehta static void hclgevf_mailbox_service_task(struct work_struct *work) 1736e2cb1decSSalil Mehta { 1737e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1738e2cb1decSSalil Mehta 1739e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 1740e2cb1decSSalil Mehta 1741e2cb1decSSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1742e2cb1decSSalil Mehta return; 1743e2cb1decSSalil Mehta 1744e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1745e2cb1decSSalil Mehta 174607a0556aSSalil Mehta hclgevf_mbx_async_handler(hdev); 1747e2cb1decSSalil Mehta 1748e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1749e2cb1decSSalil Mehta } 1750e2cb1decSSalil Mehta 1751a6d818e3SYunsheng Lin static void hclgevf_keep_alive_timer(struct timer_list *t) 1752a6d818e3SYunsheng Lin { 1753a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = from_timer(hdev, t, keep_alive_timer); 1754a6d818e3SYunsheng Lin 1755a6d818e3SYunsheng Lin schedule_work(&hdev->keep_alive_task); 1756b37ce587SYufeng Mo mod_timer(&hdev->keep_alive_timer, jiffies + 1757b37ce587SYufeng Mo HCLGEVF_KEEP_ALIVE_TASK_INTERVAL * HZ); 1758a6d818e3SYunsheng Lin } 1759a6d818e3SYunsheng Lin 1760a6d818e3SYunsheng Lin static void hclgevf_keep_alive_task(struct work_struct *work) 1761a6d818e3SYunsheng Lin { 1762a6d818e3SYunsheng Lin struct hclgevf_dev *hdev; 1763a6d818e3SYunsheng Lin u8 respmsg; 1764a6d818e3SYunsheng Lin int ret; 1765a6d818e3SYunsheng Lin 1766a6d818e3SYunsheng Lin hdev = container_of(work, struct hclgevf_dev, keep_alive_task); 1767c59a85c0SJian Shen 17681416d333SHuazhong Tan if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 1769c59a85c0SJian Shen return; 1770c59a85c0SJian Shen 1771a6d818e3SYunsheng Lin ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL, 1772a6d818e3SYunsheng Lin 0, false, &respmsg, sizeof(u8)); 1773a6d818e3SYunsheng Lin if (ret) 1774a6d818e3SYunsheng Lin dev_err(&hdev->pdev->dev, 1775a6d818e3SYunsheng Lin "VF sends keep alive cmd failed(=%d)\n", ret); 1776a6d818e3SYunsheng Lin } 1777a6d818e3SYunsheng Lin 1778e2cb1decSSalil Mehta static void hclgevf_service_task(struct work_struct *work) 1779e2cb1decSSalil Mehta { 1780db01afebSliuzhongzhu struct hnae3_handle *handle; 1781e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1782e2cb1decSSalil Mehta 1783e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, service_task); 1784db01afebSliuzhongzhu handle = &hdev->nic; 1785db01afebSliuzhongzhu 1786db01afebSliuzhongzhu if (hdev->stats_timer >= HCLGEVF_STATS_TIMER_INTERVAL) { 1787db01afebSliuzhongzhu hclgevf_tqps_update_stats(handle); 1788db01afebSliuzhongzhu hdev->stats_timer = 0; 1789db01afebSliuzhongzhu } 1790e2cb1decSSalil Mehta 1791e2cb1decSSalil Mehta /* request the link status from the PF. PF would be able to tell VF 1792e2cb1decSSalil Mehta * about such updates in future so we might remove this later 1793e2cb1decSSalil Mehta */ 1794e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1795e2cb1decSSalil Mehta 17969194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 17979194d18bSliuzhongzhu 1798436667d2SSalil Mehta hclgevf_deferred_task_schedule(hdev); 1799436667d2SSalil Mehta 1800e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1801e2cb1decSSalil Mehta } 1802e2cb1decSSalil Mehta 1803e2cb1decSSalil Mehta static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1804e2cb1decSSalil Mehta { 1805e2cb1decSSalil Mehta hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1806e2cb1decSSalil Mehta } 1807e2cb1decSSalil Mehta 1808b90fcc5bSHuazhong Tan static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1809b90fcc5bSHuazhong Tan u32 *clearval) 1810e2cb1decSSalil Mehta { 1811b90fcc5bSHuazhong Tan u32 cmdq_src_reg, rst_ing_reg; 1812e2cb1decSSalil Mehta 1813e2cb1decSSalil Mehta /* fetch the events from their corresponding regs */ 1814e2cb1decSSalil Mehta cmdq_src_reg = hclgevf_read_dev(&hdev->hw, 1815e2cb1decSSalil Mehta HCLGEVF_VECTOR0_CMDQ_SRC_REG); 1816e2cb1decSSalil Mehta 1817b90fcc5bSHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_src_reg) { 1818b90fcc5bSHuazhong Tan rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1819b90fcc5bSHuazhong Tan dev_info(&hdev->pdev->dev, 1820b90fcc5bSHuazhong Tan "receive reset interrupt 0x%x!\n", rst_ing_reg); 1821b90fcc5bSHuazhong Tan set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1822b90fcc5bSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1823ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1824b90fcc5bSHuazhong Tan cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RST_INT_B); 1825b90fcc5bSHuazhong Tan *clearval = cmdq_src_reg; 1826c88a6e7dSHuazhong Tan hdev->rst_stats.vf_rst_cnt++; 1827b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_RST; 1828b90fcc5bSHuazhong Tan } 1829b90fcc5bSHuazhong Tan 1830e2cb1decSSalil Mehta /* check for vector0 mailbox(=CMDQ RX) event source */ 1831e2cb1decSSalil Mehta if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 1832e2cb1decSSalil Mehta cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1833e2cb1decSSalil Mehta *clearval = cmdq_src_reg; 1834b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_MBX; 1835e2cb1decSSalil Mehta } 1836e2cb1decSSalil Mehta 1837e2cb1decSSalil Mehta dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 1838e2cb1decSSalil Mehta 1839b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_OTHER; 1840e2cb1decSSalil Mehta } 1841e2cb1decSSalil Mehta 1842e2cb1decSSalil Mehta static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1843e2cb1decSSalil Mehta { 1844e2cb1decSSalil Mehta writel(en ? 1 : 0, vector->addr); 1845e2cb1decSSalil Mehta } 1846e2cb1decSSalil Mehta 1847e2cb1decSSalil Mehta static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1848e2cb1decSSalil Mehta { 1849b90fcc5bSHuazhong Tan enum hclgevf_evt_cause event_cause; 1850e2cb1decSSalil Mehta struct hclgevf_dev *hdev = data; 1851e2cb1decSSalil Mehta u32 clearval; 1852e2cb1decSSalil Mehta 1853e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 1854b90fcc5bSHuazhong Tan event_cause = hclgevf_check_evt_cause(hdev, &clearval); 1855e2cb1decSSalil Mehta 1856b90fcc5bSHuazhong Tan switch (event_cause) { 1857b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_RST: 1858b90fcc5bSHuazhong Tan hclgevf_reset_task_schedule(hdev); 1859b90fcc5bSHuazhong Tan break; 1860b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_MBX: 186107a0556aSSalil Mehta hclgevf_mbx_handler(hdev); 1862b90fcc5bSHuazhong Tan break; 1863b90fcc5bSHuazhong Tan default: 1864b90fcc5bSHuazhong Tan break; 1865b90fcc5bSHuazhong Tan } 1866e2cb1decSSalil Mehta 1867b90fcc5bSHuazhong Tan if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 1868e2cb1decSSalil Mehta hclgevf_clear_event_cause(hdev, clearval); 1869e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 1870b90fcc5bSHuazhong Tan } 1871e2cb1decSSalil Mehta 1872e2cb1decSSalil Mehta return IRQ_HANDLED; 1873e2cb1decSSalil Mehta } 1874e2cb1decSSalil Mehta 1875e2cb1decSSalil Mehta static int hclgevf_configure(struct hclgevf_dev *hdev) 1876e2cb1decSSalil Mehta { 1877e2cb1decSSalil Mehta int ret; 1878e2cb1decSSalil Mehta 187992f11ea1SJian Shen /* get current port based vlan state from PF */ 188092f11ea1SJian Shen ret = hclgevf_get_port_base_vlan_filter_state(hdev); 188192f11ea1SJian Shen if (ret) 188292f11ea1SJian Shen return ret; 188392f11ea1SJian Shen 1884e2cb1decSSalil Mehta /* get queue configuration from PF */ 18856cee6fc3SJian Shen ret = hclgevf_get_queue_info(hdev); 1886e2cb1decSSalil Mehta if (ret) 1887e2cb1decSSalil Mehta return ret; 1888c0425944SPeng Li 1889c0425944SPeng Li /* get queue depth info from PF */ 1890c0425944SPeng Li ret = hclgevf_get_queue_depth(hdev); 1891c0425944SPeng Li if (ret) 1892c0425944SPeng Li return ret; 1893c0425944SPeng Li 18949c3e7130Sliuzhongzhu ret = hclgevf_get_pf_media_type(hdev); 18959c3e7130Sliuzhongzhu if (ret) 18969c3e7130Sliuzhongzhu return ret; 18979c3e7130Sliuzhongzhu 1898e2cb1decSSalil Mehta /* get tc configuration from PF */ 1899e2cb1decSSalil Mehta return hclgevf_get_tc_info(hdev); 1900e2cb1decSSalil Mehta } 1901e2cb1decSSalil Mehta 19027a01c897SSalil Mehta static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 19037a01c897SSalil Mehta { 19047a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 19051154bb26SPeng Li struct hclgevf_dev *hdev; 19067a01c897SSalil Mehta 19077a01c897SSalil Mehta hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 19087a01c897SSalil Mehta if (!hdev) 19097a01c897SSalil Mehta return -ENOMEM; 19107a01c897SSalil Mehta 19117a01c897SSalil Mehta hdev->pdev = pdev; 19127a01c897SSalil Mehta hdev->ae_dev = ae_dev; 19137a01c897SSalil Mehta ae_dev->priv = hdev; 19147a01c897SSalil Mehta 19157a01c897SSalil Mehta return 0; 19167a01c897SSalil Mehta } 19177a01c897SSalil Mehta 1918e2cb1decSSalil Mehta static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 1919e2cb1decSSalil Mehta { 1920e2cb1decSSalil Mehta struct hnae3_handle *roce = &hdev->roce; 1921e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 1922e2cb1decSSalil Mehta 192307acf909SJian Shen roce->rinfo.num_vectors = hdev->num_roce_msix; 1924e2cb1decSSalil Mehta 1925e2cb1decSSalil Mehta if (hdev->num_msi_left < roce->rinfo.num_vectors || 1926e2cb1decSSalil Mehta hdev->num_msi_left == 0) 1927e2cb1decSSalil Mehta return -EINVAL; 1928e2cb1decSSalil Mehta 192907acf909SJian Shen roce->rinfo.base_vector = hdev->roce_base_vector; 1930e2cb1decSSalil Mehta 1931e2cb1decSSalil Mehta roce->rinfo.netdev = nic->kinfo.netdev; 1932e2cb1decSSalil Mehta roce->rinfo.roce_io_base = hdev->hw.io_base; 1933e2cb1decSSalil Mehta 1934e2cb1decSSalil Mehta roce->pdev = nic->pdev; 1935e2cb1decSSalil Mehta roce->ae_algo = nic->ae_algo; 1936e2cb1decSSalil Mehta roce->numa_node_mask = nic->numa_node_mask; 1937e2cb1decSSalil Mehta 1938e2cb1decSSalil Mehta return 0; 1939e2cb1decSSalil Mehta } 1940e2cb1decSSalil Mehta 1941b26a6feaSPeng Li static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 1942b26a6feaSPeng Li { 1943b26a6feaSPeng Li struct hclgevf_cfg_gro_status_cmd *req; 1944b26a6feaSPeng Li struct hclgevf_desc desc; 1945b26a6feaSPeng Li int ret; 1946b26a6feaSPeng Li 1947b26a6feaSPeng Li if (!hnae3_dev_gro_supported(hdev)) 1948b26a6feaSPeng Li return 0; 1949b26a6feaSPeng Li 1950b26a6feaSPeng Li hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 1951b26a6feaSPeng Li false); 1952b26a6feaSPeng Li req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 1953b26a6feaSPeng Li 1954b26a6feaSPeng Li req->gro_en = cpu_to_le16(en ? 1 : 0); 1955b26a6feaSPeng Li 1956b26a6feaSPeng Li ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1957b26a6feaSPeng Li if (ret) 1958b26a6feaSPeng Li dev_err(&hdev->pdev->dev, 1959b26a6feaSPeng Li "VF GRO hardware config cmd failed, ret = %d.\n", ret); 1960b26a6feaSPeng Li 1961b26a6feaSPeng Li return ret; 1962b26a6feaSPeng Li } 1963b26a6feaSPeng Li 1964e2cb1decSSalil Mehta static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 1965e2cb1decSSalil Mehta { 1966e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1967e2cb1decSSalil Mehta int i, ret; 1968e2cb1decSSalil Mehta 1969e2cb1decSSalil Mehta rss_cfg->rss_size = hdev->rss_size_max; 1970e2cb1decSSalil Mehta 1971374ad291SJian Shen if (hdev->pdev->revision >= 0x21) { 1972472d7eceSJian Shen rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 1973472d7eceSJian Shen memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 1974374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 1975374ad291SJian Shen 1976374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 1977374ad291SJian Shen rss_cfg->rss_hash_key); 1978374ad291SJian Shen if (ret) 1979374ad291SJian Shen return ret; 1980d97b3072SJian Shen 1981d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = 1982d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1983d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = 1984d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1985d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = 1986d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1987d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = 1988d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1989d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = 1990d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1991d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = 1992d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1993d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = 1994d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1995d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = 1996d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1997d97b3072SJian Shen 1998d97b3072SJian Shen ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 1999d97b3072SJian Shen if (ret) 2000d97b3072SJian Shen return ret; 2001d97b3072SJian Shen 2002374ad291SJian Shen } 2003374ad291SJian Shen 2004e2cb1decSSalil Mehta /* Initialize RSS indirect table for each vport */ 2005e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 2006e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max; 2007e2cb1decSSalil Mehta 2008e2cb1decSSalil Mehta ret = hclgevf_set_rss_indir_table(hdev); 2009e2cb1decSSalil Mehta if (ret) 2010e2cb1decSSalil Mehta return ret; 2011e2cb1decSSalil Mehta 2012e2cb1decSSalil Mehta return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max); 2013e2cb1decSSalil Mehta } 2014e2cb1decSSalil Mehta 2015e2cb1decSSalil Mehta static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2016e2cb1decSSalil Mehta { 2017e2cb1decSSalil Mehta /* other vlan config(like, VLAN TX/RX offload) would also be added 2018e2cb1decSSalil Mehta * here later 2019e2cb1decSSalil Mehta */ 2020e2cb1decSSalil Mehta return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2021e2cb1decSSalil Mehta false); 2022e2cb1decSSalil Mehta } 2023e2cb1decSSalil Mehta 20248cdb992fSJian Shen static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 20258cdb992fSJian Shen { 20268cdb992fSJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 20278cdb992fSJian Shen 20288cdb992fSJian Shen if (enable) { 20298cdb992fSJian Shen mod_timer(&hdev->service_timer, jiffies + HZ); 20308cdb992fSJian Shen } else { 20318cdb992fSJian Shen del_timer_sync(&hdev->service_timer); 20328cdb992fSJian Shen cancel_work_sync(&hdev->service_task); 20338cdb992fSJian Shen clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 20348cdb992fSJian Shen } 20358cdb992fSJian Shen } 20368cdb992fSJian Shen 2037e2cb1decSSalil Mehta static int hclgevf_ae_start(struct hnae3_handle *handle) 2038e2cb1decSSalil Mehta { 2039e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2040e2cb1decSSalil Mehta 2041e2cb1decSSalil Mehta /* reset tqp stats */ 2042e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 2043e2cb1decSSalil Mehta 2044e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 2045e2cb1decSSalil Mehta 20469194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 20479194d18bSliuzhongzhu 2048e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2049e2cb1decSSalil Mehta 2050e2cb1decSSalil Mehta return 0; 2051e2cb1decSSalil Mehta } 2052e2cb1decSSalil Mehta 2053e2cb1decSSalil Mehta static void hclgevf_ae_stop(struct hnae3_handle *handle) 2054e2cb1decSSalil Mehta { 2055e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 205639cfbc9cSHuazhong Tan int i; 2057e2cb1decSSalil Mehta 20582f7e4896SFuyun Liang set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 20592f7e4896SFuyun Liang 2060146e92c1SHuazhong Tan if (hdev->reset_type != HNAE3_VF_RESET) 206139cfbc9cSHuazhong Tan for (i = 0; i < handle->kinfo.num_tqps; i++) 2062146e92c1SHuazhong Tan if (hclgevf_reset_tqp(handle, i)) 2063146e92c1SHuazhong Tan break; 206439cfbc9cSHuazhong Tan 2065e2cb1decSSalil Mehta /* reset tqp stats */ 2066e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 20678cc6c1f7SFuyun Liang hclgevf_update_link_status(hdev, 0); 2068e2cb1decSSalil Mehta } 2069e2cb1decSSalil Mehta 2070a6d818e3SYunsheng Lin static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2071a6d818e3SYunsheng Lin { 2072a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2073a6d818e3SYunsheng Lin u8 msg_data; 2074a6d818e3SYunsheng Lin 2075a6d818e3SYunsheng Lin msg_data = alive ? 1 : 0; 2076a6d818e3SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE, 2077a6d818e3SYunsheng Lin 0, &msg_data, 1, false, NULL, 0); 2078a6d818e3SYunsheng Lin } 2079a6d818e3SYunsheng Lin 2080a6d818e3SYunsheng Lin static int hclgevf_client_start(struct hnae3_handle *handle) 2081a6d818e3SYunsheng Lin { 2082a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2083e233516eSHuazhong Tan int ret; 2084e233516eSHuazhong Tan 2085e233516eSHuazhong Tan ret = hclgevf_set_alive(handle, true); 2086e233516eSHuazhong Tan if (ret) 2087e233516eSHuazhong Tan return ret; 2088a6d818e3SYunsheng Lin 2089b37ce587SYufeng Mo mod_timer(&hdev->keep_alive_timer, jiffies + 2090b37ce587SYufeng Mo HCLGEVF_KEEP_ALIVE_TASK_INTERVAL * HZ); 2091e233516eSHuazhong Tan 2092e233516eSHuazhong Tan return 0; 2093a6d818e3SYunsheng Lin } 2094a6d818e3SYunsheng Lin 2095a6d818e3SYunsheng Lin static void hclgevf_client_stop(struct hnae3_handle *handle) 2096a6d818e3SYunsheng Lin { 2097a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2098a6d818e3SYunsheng Lin int ret; 2099a6d818e3SYunsheng Lin 2100a6d818e3SYunsheng Lin ret = hclgevf_set_alive(handle, false); 2101a6d818e3SYunsheng Lin if (ret) 2102a6d818e3SYunsheng Lin dev_warn(&hdev->pdev->dev, 2103a6d818e3SYunsheng Lin "%s failed %d\n", __func__, ret); 2104a6d818e3SYunsheng Lin 2105a6d818e3SYunsheng Lin del_timer_sync(&hdev->keep_alive_timer); 2106a6d818e3SYunsheng Lin cancel_work_sync(&hdev->keep_alive_task); 2107a6d818e3SYunsheng Lin } 2108a6d818e3SYunsheng Lin 2109e2cb1decSSalil Mehta static void hclgevf_state_init(struct hclgevf_dev *hdev) 2110e2cb1decSSalil Mehta { 2111e2cb1decSSalil Mehta /* setup tasks for the MBX */ 2112e2cb1decSSalil Mehta INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 2113e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2114e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2115e2cb1decSSalil Mehta 2116e2cb1decSSalil Mehta /* setup tasks for service timer */ 2117e2cb1decSSalil Mehta timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 2118e2cb1decSSalil Mehta 2119e2cb1decSSalil Mehta INIT_WORK(&hdev->service_task, hclgevf_service_task); 2120e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2121e2cb1decSSalil Mehta 212235a1e503SSalil Mehta INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task); 212335a1e503SSalil Mehta 2124e2cb1decSSalil Mehta mutex_init(&hdev->mbx_resp.mbx_mutex); 2125e2cb1decSSalil Mehta 2126e2cb1decSSalil Mehta /* bring the device down */ 2127e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2128e2cb1decSSalil Mehta } 2129e2cb1decSSalil Mehta 2130e2cb1decSSalil Mehta static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2131e2cb1decSSalil Mehta { 2132e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2133acfc3d55SHuazhong Tan set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2134e2cb1decSSalil Mehta 2135e233516eSHuazhong Tan if (hdev->keep_alive_timer.function) 2136e233516eSHuazhong Tan del_timer_sync(&hdev->keep_alive_timer); 2137e233516eSHuazhong Tan if (hdev->keep_alive_task.func) 2138e233516eSHuazhong Tan cancel_work_sync(&hdev->keep_alive_task); 2139e2cb1decSSalil Mehta if (hdev->service_timer.function) 2140e2cb1decSSalil Mehta del_timer_sync(&hdev->service_timer); 2141e2cb1decSSalil Mehta if (hdev->service_task.func) 2142e2cb1decSSalil Mehta cancel_work_sync(&hdev->service_task); 2143e2cb1decSSalil Mehta if (hdev->mbx_service_task.func) 2144e2cb1decSSalil Mehta cancel_work_sync(&hdev->mbx_service_task); 214535a1e503SSalil Mehta if (hdev->rst_service_task.func) 214635a1e503SSalil Mehta cancel_work_sync(&hdev->rst_service_task); 2147e2cb1decSSalil Mehta 2148e2cb1decSSalil Mehta mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2149e2cb1decSSalil Mehta } 2150e2cb1decSSalil Mehta 2151e2cb1decSSalil Mehta static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2152e2cb1decSSalil Mehta { 2153e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2154e2cb1decSSalil Mehta int vectors; 2155e2cb1decSSalil Mehta int i; 2156e2cb1decSSalil Mehta 215707acf909SJian Shen if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) 215807acf909SJian Shen vectors = pci_alloc_irq_vectors(pdev, 215907acf909SJian Shen hdev->roce_base_msix_offset + 1, 216007acf909SJian Shen hdev->num_msi, 216107acf909SJian Shen PCI_IRQ_MSIX); 216207acf909SJian Shen else 2163e2cb1decSSalil Mehta vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 2164e2cb1decSSalil Mehta PCI_IRQ_MSI | PCI_IRQ_MSIX); 216507acf909SJian Shen 2166e2cb1decSSalil Mehta if (vectors < 0) { 2167e2cb1decSSalil Mehta dev_err(&pdev->dev, 2168e2cb1decSSalil Mehta "failed(%d) to allocate MSI/MSI-X vectors\n", 2169e2cb1decSSalil Mehta vectors); 2170e2cb1decSSalil Mehta return vectors; 2171e2cb1decSSalil Mehta } 2172e2cb1decSSalil Mehta if (vectors < hdev->num_msi) 2173e2cb1decSSalil Mehta dev_warn(&hdev->pdev->dev, 2174e2cb1decSSalil Mehta "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2175e2cb1decSSalil Mehta hdev->num_msi, vectors); 2176e2cb1decSSalil Mehta 2177e2cb1decSSalil Mehta hdev->num_msi = vectors; 2178e2cb1decSSalil Mehta hdev->num_msi_left = vectors; 2179e2cb1decSSalil Mehta hdev->base_msi_vector = pdev->irq; 218007acf909SJian Shen hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2181e2cb1decSSalil Mehta 2182e2cb1decSSalil Mehta hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2183e2cb1decSSalil Mehta sizeof(u16), GFP_KERNEL); 2184e2cb1decSSalil Mehta if (!hdev->vector_status) { 2185e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2186e2cb1decSSalil Mehta return -ENOMEM; 2187e2cb1decSSalil Mehta } 2188e2cb1decSSalil Mehta 2189e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 2190e2cb1decSSalil Mehta hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2191e2cb1decSSalil Mehta 2192e2cb1decSSalil Mehta hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2193e2cb1decSSalil Mehta sizeof(int), GFP_KERNEL); 2194e2cb1decSSalil Mehta if (!hdev->vector_irq) { 2195862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2196e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2197e2cb1decSSalil Mehta return -ENOMEM; 2198e2cb1decSSalil Mehta } 2199e2cb1decSSalil Mehta 2200e2cb1decSSalil Mehta return 0; 2201e2cb1decSSalil Mehta } 2202e2cb1decSSalil Mehta 2203e2cb1decSSalil Mehta static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2204e2cb1decSSalil Mehta { 2205e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2206e2cb1decSSalil Mehta 2207862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2208862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_irq); 2209e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2210e2cb1decSSalil Mehta } 2211e2cb1decSSalil Mehta 2212e2cb1decSSalil Mehta static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2213e2cb1decSSalil Mehta { 2214e2cb1decSSalil Mehta int ret = 0; 2215e2cb1decSSalil Mehta 2216e2cb1decSSalil Mehta hclgevf_get_misc_vector(hdev); 2217e2cb1decSSalil Mehta 2218e2cb1decSSalil Mehta ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2219e2cb1decSSalil Mehta 0, "hclgevf_cmd", hdev); 2220e2cb1decSSalil Mehta if (ret) { 2221e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2222e2cb1decSSalil Mehta hdev->misc_vector.vector_irq); 2223e2cb1decSSalil Mehta return ret; 2224e2cb1decSSalil Mehta } 2225e2cb1decSSalil Mehta 22261819e409SXi Wang hclgevf_clear_event_cause(hdev, 0); 22271819e409SXi Wang 2228e2cb1decSSalil Mehta /* enable misc. vector(vector 0) */ 2229e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2230e2cb1decSSalil Mehta 2231e2cb1decSSalil Mehta return ret; 2232e2cb1decSSalil Mehta } 2233e2cb1decSSalil Mehta 2234e2cb1decSSalil Mehta static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2235e2cb1decSSalil Mehta { 2236e2cb1decSSalil Mehta /* disable misc vector(vector 0) */ 2237e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 22381819e409SXi Wang synchronize_irq(hdev->misc_vector.vector_irq); 2239e2cb1decSSalil Mehta free_irq(hdev->misc_vector.vector_irq, hdev); 2240e2cb1decSSalil Mehta hclgevf_free_vector(hdev, 0); 2241e2cb1decSSalil Mehta } 2242e2cb1decSSalil Mehta 2243bb87be87SYonglong Liu static void hclgevf_info_show(struct hclgevf_dev *hdev) 2244bb87be87SYonglong Liu { 2245bb87be87SYonglong Liu struct device *dev = &hdev->pdev->dev; 2246bb87be87SYonglong Liu 2247bb87be87SYonglong Liu dev_info(dev, "VF info begin:\n"); 2248bb87be87SYonglong Liu 2249bb87be87SYonglong Liu dev_info(dev, "Task queue pairs numbers: %d\n", hdev->num_tqps); 2250bb87be87SYonglong Liu dev_info(dev, "Desc num per TX queue: %d\n", hdev->num_tx_desc); 2251bb87be87SYonglong Liu dev_info(dev, "Desc num per RX queue: %d\n", hdev->num_rx_desc); 2252bb87be87SYonglong Liu dev_info(dev, "Numbers of vports: %d\n", hdev->num_alloc_vport); 2253bb87be87SYonglong Liu dev_info(dev, "HW tc map: %d\n", hdev->hw_tc_map); 2254bb87be87SYonglong Liu dev_info(dev, "PF media type of this VF: %d\n", 2255bb87be87SYonglong Liu hdev->hw.mac.media_type); 2256bb87be87SYonglong Liu 2257bb87be87SYonglong Liu dev_info(dev, "VF info end.\n"); 2258bb87be87SYonglong Liu } 2259bb87be87SYonglong Liu 22601db58f86SHuazhong Tan static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 22611db58f86SHuazhong Tan struct hnae3_client *client) 22621db58f86SHuazhong Tan { 22631db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 22641db58f86SHuazhong Tan int ret; 22651db58f86SHuazhong Tan 22661db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->nic); 22671db58f86SHuazhong Tan if (ret) 22681db58f86SHuazhong Tan return ret; 22691db58f86SHuazhong Tan 22701db58f86SHuazhong Tan set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 22711db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 22721db58f86SHuazhong Tan 22731db58f86SHuazhong Tan if (netif_msg_drv(&hdev->nic)) 22741db58f86SHuazhong Tan hclgevf_info_show(hdev); 22751db58f86SHuazhong Tan 22761db58f86SHuazhong Tan return 0; 22771db58f86SHuazhong Tan } 22781db58f86SHuazhong Tan 22791db58f86SHuazhong Tan static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 22801db58f86SHuazhong Tan struct hnae3_client *client) 22811db58f86SHuazhong Tan { 22821db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 22831db58f86SHuazhong Tan int ret; 22841db58f86SHuazhong Tan 22851db58f86SHuazhong Tan if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 22861db58f86SHuazhong Tan !hdev->nic_client) 22871db58f86SHuazhong Tan return 0; 22881db58f86SHuazhong Tan 22891db58f86SHuazhong Tan ret = hclgevf_init_roce_base_info(hdev); 22901db58f86SHuazhong Tan if (ret) 22911db58f86SHuazhong Tan return ret; 22921db58f86SHuazhong Tan 22931db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->roce); 22941db58f86SHuazhong Tan if (ret) 22951db58f86SHuazhong Tan return ret; 22961db58f86SHuazhong Tan 22971db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 22981db58f86SHuazhong Tan 22991db58f86SHuazhong Tan return 0; 23001db58f86SHuazhong Tan } 23011db58f86SHuazhong Tan 2302e718a93fSPeng Li static int hclgevf_init_client_instance(struct hnae3_client *client, 2303e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2304e2cb1decSSalil Mehta { 2305e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2306e2cb1decSSalil Mehta int ret; 2307e2cb1decSSalil Mehta 2308e2cb1decSSalil Mehta switch (client->type) { 2309e2cb1decSSalil Mehta case HNAE3_CLIENT_KNIC: 2310e2cb1decSSalil Mehta hdev->nic_client = client; 2311e2cb1decSSalil Mehta hdev->nic.client = client; 2312e2cb1decSSalil Mehta 23131db58f86SHuazhong Tan ret = hclgevf_init_nic_client_instance(ae_dev, client); 2314e2cb1decSSalil Mehta if (ret) 231549dd8054SJian Shen goto clear_nic; 2316e2cb1decSSalil Mehta 23171db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, 23181db58f86SHuazhong Tan hdev->roce_client); 2319e2cb1decSSalil Mehta if (ret) 232049dd8054SJian Shen goto clear_roce; 2321d9f28fc2SJian Shen 2322e2cb1decSSalil Mehta break; 2323e2cb1decSSalil Mehta case HNAE3_CLIENT_ROCE: 2324544a7bcdSLijun Ou if (hnae3_dev_roce_supported(hdev)) { 2325e2cb1decSSalil Mehta hdev->roce_client = client; 2326e2cb1decSSalil Mehta hdev->roce.client = client; 2327544a7bcdSLijun Ou } 2328e2cb1decSSalil Mehta 23291db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, client); 2330e2cb1decSSalil Mehta if (ret) 233149dd8054SJian Shen goto clear_roce; 2332e2cb1decSSalil Mehta 2333fa7a4bd5SJian Shen break; 2334fa7a4bd5SJian Shen default: 2335fa7a4bd5SJian Shen return -EINVAL; 2336e2cb1decSSalil Mehta } 2337e2cb1decSSalil Mehta 2338e2cb1decSSalil Mehta return 0; 233949dd8054SJian Shen 234049dd8054SJian Shen clear_nic: 234149dd8054SJian Shen hdev->nic_client = NULL; 234249dd8054SJian Shen hdev->nic.client = NULL; 234349dd8054SJian Shen return ret; 234449dd8054SJian Shen clear_roce: 234549dd8054SJian Shen hdev->roce_client = NULL; 234649dd8054SJian Shen hdev->roce.client = NULL; 234749dd8054SJian Shen return ret; 2348e2cb1decSSalil Mehta } 2349e2cb1decSSalil Mehta 2350e718a93fSPeng Li static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2351e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2352e2cb1decSSalil Mehta { 2353e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2354e718a93fSPeng Li 2355e2cb1decSSalil Mehta /* un-init roce, if it exists */ 235649dd8054SJian Shen if (hdev->roce_client) { 2357e2cb1decSSalil Mehta hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 235849dd8054SJian Shen hdev->roce_client = NULL; 235949dd8054SJian Shen hdev->roce.client = NULL; 236049dd8054SJian Shen } 2361e2cb1decSSalil Mehta 2362e2cb1decSSalil Mehta /* un-init nic/unic, if this was not called by roce client */ 236349dd8054SJian Shen if (client->ops->uninit_instance && hdev->nic_client && 236449dd8054SJian Shen client->type != HNAE3_CLIENT_ROCE) { 236525d1817cSHuazhong Tan clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 236625d1817cSHuazhong Tan 2367e2cb1decSSalil Mehta client->ops->uninit_instance(&hdev->nic, 0); 236849dd8054SJian Shen hdev->nic_client = NULL; 236949dd8054SJian Shen hdev->nic.client = NULL; 237049dd8054SJian Shen } 2371e2cb1decSSalil Mehta } 2372e2cb1decSSalil Mehta 2373e2cb1decSSalil Mehta static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2374e2cb1decSSalil Mehta { 2375e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2376e2cb1decSSalil Mehta struct hclgevf_hw *hw; 2377e2cb1decSSalil Mehta int ret; 2378e2cb1decSSalil Mehta 2379e2cb1decSSalil Mehta ret = pci_enable_device(pdev); 2380e2cb1decSSalil Mehta if (ret) { 2381e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed to enable PCI device\n"); 23823e249d3bSFuyun Liang return ret; 2383e2cb1decSSalil Mehta } 2384e2cb1decSSalil Mehta 2385e2cb1decSSalil Mehta ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2386e2cb1decSSalil Mehta if (ret) { 2387e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2388e2cb1decSSalil Mehta goto err_disable_device; 2389e2cb1decSSalil Mehta } 2390e2cb1decSSalil Mehta 2391e2cb1decSSalil Mehta ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2392e2cb1decSSalil Mehta if (ret) { 2393e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2394e2cb1decSSalil Mehta goto err_disable_device; 2395e2cb1decSSalil Mehta } 2396e2cb1decSSalil Mehta 2397e2cb1decSSalil Mehta pci_set_master(pdev); 2398e2cb1decSSalil Mehta hw = &hdev->hw; 2399e2cb1decSSalil Mehta hw->hdev = hdev; 24002e1ea493SPeng Li hw->io_base = pci_iomap(pdev, 2, 0); 2401e2cb1decSSalil Mehta if (!hw->io_base) { 2402e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't map configuration register space\n"); 2403e2cb1decSSalil Mehta ret = -ENOMEM; 2404e2cb1decSSalil Mehta goto err_clr_master; 2405e2cb1decSSalil Mehta } 2406e2cb1decSSalil Mehta 2407e2cb1decSSalil Mehta return 0; 2408e2cb1decSSalil Mehta 2409e2cb1decSSalil Mehta err_clr_master: 2410e2cb1decSSalil Mehta pci_clear_master(pdev); 2411e2cb1decSSalil Mehta pci_release_regions(pdev); 2412e2cb1decSSalil Mehta err_disable_device: 2413e2cb1decSSalil Mehta pci_disable_device(pdev); 24143e249d3bSFuyun Liang 2415e2cb1decSSalil Mehta return ret; 2416e2cb1decSSalil Mehta } 2417e2cb1decSSalil Mehta 2418e2cb1decSSalil Mehta static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2419e2cb1decSSalil Mehta { 2420e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2421e2cb1decSSalil Mehta 2422e2cb1decSSalil Mehta pci_iounmap(pdev, hdev->hw.io_base); 2423e2cb1decSSalil Mehta pci_clear_master(pdev); 2424e2cb1decSSalil Mehta pci_release_regions(pdev); 2425e2cb1decSSalil Mehta pci_disable_device(pdev); 2426e2cb1decSSalil Mehta } 2427e2cb1decSSalil Mehta 242807acf909SJian Shen static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 242907acf909SJian Shen { 243007acf909SJian Shen struct hclgevf_query_res_cmd *req; 243107acf909SJian Shen struct hclgevf_desc desc; 243207acf909SJian Shen int ret; 243307acf909SJian Shen 243407acf909SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 243507acf909SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 243607acf909SJian Shen if (ret) { 243707acf909SJian Shen dev_err(&hdev->pdev->dev, 243807acf909SJian Shen "query vf resource failed, ret = %d.\n", ret); 243907acf909SJian Shen return ret; 244007acf909SJian Shen } 244107acf909SJian Shen 244207acf909SJian Shen req = (struct hclgevf_query_res_cmd *)desc.data; 244307acf909SJian Shen 244407acf909SJian Shen if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) { 244507acf909SJian Shen hdev->roce_base_msix_offset = 244607acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 244707acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_M, 244807acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_S); 244907acf909SJian Shen hdev->num_roce_msix = 245007acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 245107acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 245207acf909SJian Shen 245307acf909SJian Shen /* VF should have NIC vectors and Roce vectors, NIC vectors 245407acf909SJian Shen * are queued before Roce vectors. The offset is fixed to 64. 245507acf909SJian Shen */ 245607acf909SJian Shen hdev->num_msi = hdev->num_roce_msix + 245707acf909SJian Shen hdev->roce_base_msix_offset; 245807acf909SJian Shen } else { 245907acf909SJian Shen hdev->num_msi = 246007acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 246107acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 246207acf909SJian Shen } 246307acf909SJian Shen 246407acf909SJian Shen return 0; 246507acf909SJian Shen } 246607acf909SJian Shen 2467862d969aSHuazhong Tan static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2468862d969aSHuazhong Tan { 2469862d969aSHuazhong Tan struct pci_dev *pdev = hdev->pdev; 2470862d969aSHuazhong Tan int ret = 0; 2471862d969aSHuazhong Tan 2472862d969aSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2473862d969aSHuazhong Tan test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2474862d969aSHuazhong Tan hclgevf_misc_irq_uninit(hdev); 2475862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2476862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2477862d969aSHuazhong Tan } 2478862d969aSHuazhong Tan 2479862d969aSHuazhong Tan if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2480862d969aSHuazhong Tan pci_set_master(pdev); 2481862d969aSHuazhong Tan ret = hclgevf_init_msi(hdev); 2482862d969aSHuazhong Tan if (ret) { 2483862d969aSHuazhong Tan dev_err(&pdev->dev, 2484862d969aSHuazhong Tan "failed(%d) to init MSI/MSI-X\n", ret); 2485862d969aSHuazhong Tan return ret; 2486862d969aSHuazhong Tan } 2487862d969aSHuazhong Tan 2488862d969aSHuazhong Tan ret = hclgevf_misc_irq_init(hdev); 2489862d969aSHuazhong Tan if (ret) { 2490862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2491862d969aSHuazhong Tan dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2492862d969aSHuazhong Tan ret); 2493862d969aSHuazhong Tan return ret; 2494862d969aSHuazhong Tan } 2495862d969aSHuazhong Tan 2496862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2497862d969aSHuazhong Tan } 2498862d969aSHuazhong Tan 2499862d969aSHuazhong Tan return ret; 2500862d969aSHuazhong Tan } 2501862d969aSHuazhong Tan 25029c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2503e2cb1decSSalil Mehta { 25047a01c897SSalil Mehta struct pci_dev *pdev = hdev->pdev; 2505e2cb1decSSalil Mehta int ret; 2506e2cb1decSSalil Mehta 2507862d969aSHuazhong Tan ret = hclgevf_pci_reset(hdev); 2508862d969aSHuazhong Tan if (ret) { 2509862d969aSHuazhong Tan dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2510862d969aSHuazhong Tan return ret; 2511862d969aSHuazhong Tan } 2512862d969aSHuazhong Tan 25139c6f7085SHuazhong Tan ret = hclgevf_cmd_init(hdev); 25149c6f7085SHuazhong Tan if (ret) { 25159c6f7085SHuazhong Tan dev_err(&pdev->dev, "cmd failed %d\n", ret); 25169c6f7085SHuazhong Tan return ret; 25177a01c897SSalil Mehta } 2518e2cb1decSSalil Mehta 25199c6f7085SHuazhong Tan ret = hclgevf_rss_init_hw(hdev); 25209c6f7085SHuazhong Tan if (ret) { 25219c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 25229c6f7085SHuazhong Tan "failed(%d) to initialize RSS\n", ret); 25239c6f7085SHuazhong Tan return ret; 25249c6f7085SHuazhong Tan } 25259c6f7085SHuazhong Tan 2526b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2527b26a6feaSPeng Li if (ret) 2528b26a6feaSPeng Li return ret; 2529b26a6feaSPeng Li 25309c6f7085SHuazhong Tan ret = hclgevf_init_vlan_config(hdev); 25319c6f7085SHuazhong Tan if (ret) { 25329c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 25339c6f7085SHuazhong Tan "failed(%d) to initialize VLAN config\n", ret); 25349c6f7085SHuazhong Tan return ret; 25359c6f7085SHuazhong Tan } 25369c6f7085SHuazhong Tan 25379c6f7085SHuazhong Tan dev_info(&hdev->pdev->dev, "Reset done\n"); 25389c6f7085SHuazhong Tan 25399c6f7085SHuazhong Tan return 0; 25409c6f7085SHuazhong Tan } 25419c6f7085SHuazhong Tan 25429c6f7085SHuazhong Tan static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 25439c6f7085SHuazhong Tan { 25449c6f7085SHuazhong Tan struct pci_dev *pdev = hdev->pdev; 25459c6f7085SHuazhong Tan int ret; 25469c6f7085SHuazhong Tan 2547e2cb1decSSalil Mehta ret = hclgevf_pci_init(hdev); 2548e2cb1decSSalil Mehta if (ret) { 2549e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI initialization failed\n"); 2550e2cb1decSSalil Mehta return ret; 2551e2cb1decSSalil Mehta } 2552e2cb1decSSalil Mehta 25538b0195a3SHuazhong Tan ret = hclgevf_cmd_queue_init(hdev); 25548b0195a3SHuazhong Tan if (ret) { 25558b0195a3SHuazhong Tan dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret); 25568b0195a3SHuazhong Tan goto err_cmd_queue_init; 25578b0195a3SHuazhong Tan } 25588b0195a3SHuazhong Tan 2559eddf0462SYunsheng Lin ret = hclgevf_cmd_init(hdev); 2560eddf0462SYunsheng Lin if (ret) 2561eddf0462SYunsheng Lin goto err_cmd_init; 2562eddf0462SYunsheng Lin 256307acf909SJian Shen /* Get vf resource */ 256407acf909SJian Shen ret = hclgevf_query_vf_resource(hdev); 256507acf909SJian Shen if (ret) { 256607acf909SJian Shen dev_err(&hdev->pdev->dev, 256707acf909SJian Shen "Query vf status error, ret = %d.\n", ret); 25688b0195a3SHuazhong Tan goto err_cmd_init; 256907acf909SJian Shen } 257007acf909SJian Shen 257107acf909SJian Shen ret = hclgevf_init_msi(hdev); 257207acf909SJian Shen if (ret) { 257307acf909SJian Shen dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 25748b0195a3SHuazhong Tan goto err_cmd_init; 257507acf909SJian Shen } 257607acf909SJian Shen 257707acf909SJian Shen hclgevf_state_init(hdev); 2578dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 257907acf909SJian Shen 2580e2cb1decSSalil Mehta ret = hclgevf_misc_irq_init(hdev); 2581e2cb1decSSalil Mehta if (ret) { 2582e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2583e2cb1decSSalil Mehta ret); 2584e2cb1decSSalil Mehta goto err_misc_irq_init; 2585e2cb1decSSalil Mehta } 2586e2cb1decSSalil Mehta 2587862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2588862d969aSHuazhong Tan 2589e2cb1decSSalil Mehta ret = hclgevf_configure(hdev); 2590e2cb1decSSalil Mehta if (ret) { 2591e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2592e2cb1decSSalil Mehta goto err_config; 2593e2cb1decSSalil Mehta } 2594e2cb1decSSalil Mehta 2595e2cb1decSSalil Mehta ret = hclgevf_alloc_tqps(hdev); 2596e2cb1decSSalil Mehta if (ret) { 2597e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2598e2cb1decSSalil Mehta goto err_config; 2599e2cb1decSSalil Mehta } 2600e2cb1decSSalil Mehta 2601e2cb1decSSalil Mehta ret = hclgevf_set_handle_info(hdev); 2602e2cb1decSSalil Mehta if (ret) { 2603e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 2604e2cb1decSSalil Mehta goto err_config; 2605e2cb1decSSalil Mehta } 2606e2cb1decSSalil Mehta 2607b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2608b26a6feaSPeng Li if (ret) 2609b26a6feaSPeng Li goto err_config; 2610b26a6feaSPeng Li 2611f01f5559SJian Shen /* vf is not allowed to enable unicast/multicast promisc mode. 2612f01f5559SJian Shen * For revision 0x20, default to disable broadcast promisc mode, 2613f01f5559SJian Shen * firmware makes sure broadcast packets can be accepted. 2614f01f5559SJian Shen * For revision 0x21, default to enable broadcast promisc mode. 2615f01f5559SJian Shen */ 2616f01f5559SJian Shen ret = hclgevf_set_promisc_mode(hdev, true); 2617f01f5559SJian Shen if (ret) 2618f01f5559SJian Shen goto err_config; 2619f01f5559SJian Shen 2620e2cb1decSSalil Mehta /* Initialize RSS for this VF */ 2621e2cb1decSSalil Mehta ret = hclgevf_rss_init_hw(hdev); 2622e2cb1decSSalil Mehta if (ret) { 2623e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2624e2cb1decSSalil Mehta "failed(%d) to initialize RSS\n", ret); 2625e2cb1decSSalil Mehta goto err_config; 2626e2cb1decSSalil Mehta } 2627e2cb1decSSalil Mehta 2628e2cb1decSSalil Mehta ret = hclgevf_init_vlan_config(hdev); 2629e2cb1decSSalil Mehta if (ret) { 2630e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2631e2cb1decSSalil Mehta "failed(%d) to initialize VLAN config\n", ret); 2632e2cb1decSSalil Mehta goto err_config; 2633e2cb1decSSalil Mehta } 2634e2cb1decSSalil Mehta 26350742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 2636e2cb1decSSalil Mehta pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME); 2637e2cb1decSSalil Mehta 2638e2cb1decSSalil Mehta return 0; 2639e2cb1decSSalil Mehta 2640e2cb1decSSalil Mehta err_config: 2641e2cb1decSSalil Mehta hclgevf_misc_irq_uninit(hdev); 2642e2cb1decSSalil Mehta err_misc_irq_init: 2643e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2644e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 264507acf909SJian Shen err_cmd_init: 26468b0195a3SHuazhong Tan hclgevf_cmd_uninit(hdev); 26478b0195a3SHuazhong Tan err_cmd_queue_init: 2648e2cb1decSSalil Mehta hclgevf_pci_uninit(hdev); 2649862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2650e2cb1decSSalil Mehta return ret; 2651e2cb1decSSalil Mehta } 2652e2cb1decSSalil Mehta 26537a01c897SSalil Mehta static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2654e2cb1decSSalil Mehta { 2655e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2656862d969aSHuazhong Tan 2657862d969aSHuazhong Tan if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2658eddf0462SYunsheng Lin hclgevf_misc_irq_uninit(hdev); 2659e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 26607a01c897SSalil Mehta } 26617a01c897SSalil Mehta 2662e3338205SHuazhong Tan hclgevf_pci_uninit(hdev); 2663862d969aSHuazhong Tan hclgevf_cmd_uninit(hdev); 2664862d969aSHuazhong Tan } 2665862d969aSHuazhong Tan 26667a01c897SSalil Mehta static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 26677a01c897SSalil Mehta { 26687a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 2669a6d818e3SYunsheng Lin struct hclgevf_dev *hdev; 26707a01c897SSalil Mehta int ret; 26717a01c897SSalil Mehta 26727a01c897SSalil Mehta ret = hclgevf_alloc_hdev(ae_dev); 26737a01c897SSalil Mehta if (ret) { 26747a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device allocation failed\n"); 26757a01c897SSalil Mehta return ret; 26767a01c897SSalil Mehta } 26777a01c897SSalil Mehta 26787a01c897SSalil Mehta ret = hclgevf_init_hdev(ae_dev->priv); 2679a6d818e3SYunsheng Lin if (ret) { 26807a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device initialization failed\n"); 26817a01c897SSalil Mehta return ret; 26827a01c897SSalil Mehta } 26837a01c897SSalil Mehta 2684a6d818e3SYunsheng Lin hdev = ae_dev->priv; 2685a6d818e3SYunsheng Lin timer_setup(&hdev->keep_alive_timer, hclgevf_keep_alive_timer, 0); 2686a6d818e3SYunsheng Lin INIT_WORK(&hdev->keep_alive_task, hclgevf_keep_alive_task); 2687a6d818e3SYunsheng Lin 2688a6d818e3SYunsheng Lin return 0; 2689a6d818e3SYunsheng Lin } 2690a6d818e3SYunsheng Lin 26917a01c897SSalil Mehta static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 26927a01c897SSalil Mehta { 26937a01c897SSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 26947a01c897SSalil Mehta 26957a01c897SSalil Mehta hclgevf_uninit_hdev(hdev); 2696e2cb1decSSalil Mehta ae_dev->priv = NULL; 2697e2cb1decSSalil Mehta } 2698e2cb1decSSalil Mehta 2699849e4607SPeng Li static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2700849e4607SPeng Li { 2701849e4607SPeng Li struct hnae3_handle *nic = &hdev->nic; 2702849e4607SPeng Li struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2703849e4607SPeng Li 27048be73621SHuazhong Tan return min_t(u32, hdev->rss_size_max, 27058be73621SHuazhong Tan hdev->num_tqps / kinfo->num_tc); 2706849e4607SPeng Li } 2707849e4607SPeng Li 2708849e4607SPeng Li /** 2709849e4607SPeng Li * hclgevf_get_channels - Get the current channels enabled and max supported. 2710849e4607SPeng Li * @handle: hardware information for network interface 2711849e4607SPeng Li * @ch: ethtool channels structure 2712849e4607SPeng Li * 2713849e4607SPeng Li * We don't support separate tx and rx queues as channels. The other count 2714849e4607SPeng Li * represents how many queues are being used for control. max_combined counts 2715849e4607SPeng Li * how many queue pairs we can support. They may not be mapped 1 to 1 with 2716849e4607SPeng Li * q_vectors since we support a lot more queue pairs than q_vectors. 2717849e4607SPeng Li **/ 2718849e4607SPeng Li static void hclgevf_get_channels(struct hnae3_handle *handle, 2719849e4607SPeng Li struct ethtool_channels *ch) 2720849e4607SPeng Li { 2721849e4607SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2722849e4607SPeng Li 2723849e4607SPeng Li ch->max_combined = hclgevf_get_max_channels(hdev); 2724849e4607SPeng Li ch->other_count = 0; 2725849e4607SPeng Li ch->max_other = 0; 27268be73621SHuazhong Tan ch->combined_count = handle->kinfo.rss_size; 2727849e4607SPeng Li } 2728849e4607SPeng Li 2729cc719218SPeng Li static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 27300d43bf45SHuazhong Tan u16 *alloc_tqps, u16 *max_rss_size) 2731cc719218SPeng Li { 2732cc719218SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2733cc719218SPeng Li 27340d43bf45SHuazhong Tan *alloc_tqps = hdev->num_tqps; 2735cc719218SPeng Li *max_rss_size = hdev->rss_size_max; 2736cc719218SPeng Li } 2737cc719218SPeng Li 2738175ec96bSFuyun Liang static int hclgevf_get_status(struct hnae3_handle *handle) 2739175ec96bSFuyun Liang { 2740175ec96bSFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2741175ec96bSFuyun Liang 2742175ec96bSFuyun Liang return hdev->hw.mac.link; 2743175ec96bSFuyun Liang } 2744175ec96bSFuyun Liang 27454a152de9SFuyun Liang static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 27464a152de9SFuyun Liang u8 *auto_neg, u32 *speed, 27474a152de9SFuyun Liang u8 *duplex) 27484a152de9SFuyun Liang { 27494a152de9SFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27504a152de9SFuyun Liang 27514a152de9SFuyun Liang if (speed) 27524a152de9SFuyun Liang *speed = hdev->hw.mac.speed; 27534a152de9SFuyun Liang if (duplex) 27544a152de9SFuyun Liang *duplex = hdev->hw.mac.duplex; 27554a152de9SFuyun Liang if (auto_neg) 27564a152de9SFuyun Liang *auto_neg = AUTONEG_DISABLE; 27574a152de9SFuyun Liang } 27584a152de9SFuyun Liang 27594a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 27604a152de9SFuyun Liang u8 duplex) 27614a152de9SFuyun Liang { 27624a152de9SFuyun Liang hdev->hw.mac.speed = speed; 27634a152de9SFuyun Liang hdev->hw.mac.duplex = duplex; 27644a152de9SFuyun Liang } 27654a152de9SFuyun Liang 27661731be4cSYonglong Liu static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 27675c9f6b39SPeng Li { 27685c9f6b39SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27695c9f6b39SPeng Li 27705c9f6b39SPeng Li return hclgevf_config_gro(hdev, enable); 27715c9f6b39SPeng Li } 27725c9f6b39SPeng Li 277388d10bd6SJian Shen static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 277488d10bd6SJian Shen u8 *module_type) 2775c136b884SPeng Li { 2776c136b884SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 277788d10bd6SJian Shen 2778c136b884SPeng Li if (media_type) 2779c136b884SPeng Li *media_type = hdev->hw.mac.media_type; 278088d10bd6SJian Shen 278188d10bd6SJian Shen if (module_type) 278288d10bd6SJian Shen *module_type = hdev->hw.mac.module_type; 2783c136b884SPeng Li } 2784c136b884SPeng Li 27854d60291bSHuazhong Tan static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 27864d60291bSHuazhong Tan { 27874d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27884d60291bSHuazhong Tan 2789aa5c4f17SHuazhong Tan return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 27904d60291bSHuazhong Tan } 27914d60291bSHuazhong Tan 27924d60291bSHuazhong Tan static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 27934d60291bSHuazhong Tan { 27944d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27954d60291bSHuazhong Tan 27964d60291bSHuazhong Tan return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 27974d60291bSHuazhong Tan } 27984d60291bSHuazhong Tan 27994d60291bSHuazhong Tan static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 28004d60291bSHuazhong Tan { 28014d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 28024d60291bSHuazhong Tan 2803c88a6e7dSHuazhong Tan return hdev->rst_stats.hw_rst_done_cnt; 28044d60291bSHuazhong Tan } 28054d60291bSHuazhong Tan 28069194d18bSliuzhongzhu static void hclgevf_get_link_mode(struct hnae3_handle *handle, 28079194d18bSliuzhongzhu unsigned long *supported, 28089194d18bSliuzhongzhu unsigned long *advertising) 28099194d18bSliuzhongzhu { 28109194d18bSliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 28119194d18bSliuzhongzhu 28129194d18bSliuzhongzhu *supported = hdev->hw.mac.supported; 28139194d18bSliuzhongzhu *advertising = hdev->hw.mac.advertising; 28149194d18bSliuzhongzhu } 28159194d18bSliuzhongzhu 28161600c3e5SJian Shen #define MAX_SEPARATE_NUM 4 28171600c3e5SJian Shen #define SEPARATOR_VALUE 0xFFFFFFFF 28181600c3e5SJian Shen #define REG_NUM_PER_LINE 4 28191600c3e5SJian Shen #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 28201600c3e5SJian Shen 28211600c3e5SJian Shen static int hclgevf_get_regs_len(struct hnae3_handle *handle) 28221600c3e5SJian Shen { 28231600c3e5SJian Shen int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 28241600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 28251600c3e5SJian Shen 28261600c3e5SJian Shen cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 28271600c3e5SJian Shen common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 28281600c3e5SJian Shen ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 28291600c3e5SJian Shen tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 28301600c3e5SJian Shen 28311600c3e5SJian Shen return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 28321600c3e5SJian Shen tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 28331600c3e5SJian Shen } 28341600c3e5SJian Shen 28351600c3e5SJian Shen static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 28361600c3e5SJian Shen void *data) 28371600c3e5SJian Shen { 28381600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 28391600c3e5SJian Shen int i, j, reg_um, separator_num; 28401600c3e5SJian Shen u32 *reg = data; 28411600c3e5SJian Shen 28421600c3e5SJian Shen *version = hdev->fw_version; 28431600c3e5SJian Shen 28441600c3e5SJian Shen /* fetching per-VF registers values from VF PCIe register space */ 28451600c3e5SJian Shen reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 28461600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 28471600c3e5SJian Shen for (i = 0; i < reg_um; i++) 28481600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 28491600c3e5SJian Shen for (i = 0; i < separator_num; i++) 28501600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 28511600c3e5SJian Shen 28521600c3e5SJian Shen reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 28531600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 28541600c3e5SJian Shen for (i = 0; i < reg_um; i++) 28551600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 28561600c3e5SJian Shen for (i = 0; i < separator_num; i++) 28571600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 28581600c3e5SJian Shen 28591600c3e5SJian Shen reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 28601600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 28611600c3e5SJian Shen for (j = 0; j < hdev->num_tqps; j++) { 28621600c3e5SJian Shen for (i = 0; i < reg_um; i++) 28631600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 28641600c3e5SJian Shen ring_reg_addr_list[i] + 28651600c3e5SJian Shen 0x200 * j); 28661600c3e5SJian Shen for (i = 0; i < separator_num; i++) 28671600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 28681600c3e5SJian Shen } 28691600c3e5SJian Shen 28701600c3e5SJian Shen reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 28711600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 28721600c3e5SJian Shen for (j = 0; j < hdev->num_msi_used - 1; j++) { 28731600c3e5SJian Shen for (i = 0; i < reg_um; i++) 28741600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 28751600c3e5SJian Shen tqp_intr_reg_addr_list[i] + 28761600c3e5SJian Shen 4 * j); 28771600c3e5SJian Shen for (i = 0; i < separator_num; i++) 28781600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 28791600c3e5SJian Shen } 28801600c3e5SJian Shen } 28811600c3e5SJian Shen 288292f11ea1SJian Shen void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 288392f11ea1SJian Shen u8 *port_base_vlan_info, u8 data_size) 288492f11ea1SJian Shen { 288592f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 288692f11ea1SJian Shen 288792f11ea1SJian Shen rtnl_lock(); 288892f11ea1SJian Shen hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 288992f11ea1SJian Shen rtnl_unlock(); 289092f11ea1SJian Shen 289192f11ea1SJian Shen /* send msg to PF and wait update port based vlan info */ 289292f11ea1SJian Shen hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 289392f11ea1SJian Shen HCLGE_MBX_PORT_BASE_VLAN_CFG, 289492f11ea1SJian Shen port_base_vlan_info, data_size, 289592f11ea1SJian Shen false, NULL, 0); 289692f11ea1SJian Shen 289792f11ea1SJian Shen if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 289892f11ea1SJian Shen nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 289992f11ea1SJian Shen else 290092f11ea1SJian Shen nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 290192f11ea1SJian Shen 290292f11ea1SJian Shen rtnl_lock(); 290392f11ea1SJian Shen hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 290492f11ea1SJian Shen rtnl_unlock(); 290592f11ea1SJian Shen } 290692f11ea1SJian Shen 2907e2cb1decSSalil Mehta static const struct hnae3_ae_ops hclgevf_ops = { 2908e2cb1decSSalil Mehta .init_ae_dev = hclgevf_init_ae_dev, 2909e2cb1decSSalil Mehta .uninit_ae_dev = hclgevf_uninit_ae_dev, 29106ff3cf07SHuazhong Tan .flr_prepare = hclgevf_flr_prepare, 29116ff3cf07SHuazhong Tan .flr_done = hclgevf_flr_done, 2912e718a93fSPeng Li .init_client_instance = hclgevf_init_client_instance, 2913e718a93fSPeng Li .uninit_client_instance = hclgevf_uninit_client_instance, 2914e2cb1decSSalil Mehta .start = hclgevf_ae_start, 2915e2cb1decSSalil Mehta .stop = hclgevf_ae_stop, 2916a6d818e3SYunsheng Lin .client_start = hclgevf_client_start, 2917a6d818e3SYunsheng Lin .client_stop = hclgevf_client_stop, 2918e2cb1decSSalil Mehta .map_ring_to_vector = hclgevf_map_ring_to_vector, 2919e2cb1decSSalil Mehta .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 2920e2cb1decSSalil Mehta .get_vector = hclgevf_get_vector, 29210d3e6631SYunsheng Lin .put_vector = hclgevf_put_vector, 2922e2cb1decSSalil Mehta .reset_queue = hclgevf_reset_tqp, 2923e2cb1decSSalil Mehta .get_mac_addr = hclgevf_get_mac_addr, 2924e2cb1decSSalil Mehta .set_mac_addr = hclgevf_set_mac_addr, 2925e2cb1decSSalil Mehta .add_uc_addr = hclgevf_add_uc_addr, 2926e2cb1decSSalil Mehta .rm_uc_addr = hclgevf_rm_uc_addr, 2927e2cb1decSSalil Mehta .add_mc_addr = hclgevf_add_mc_addr, 2928e2cb1decSSalil Mehta .rm_mc_addr = hclgevf_rm_mc_addr, 2929e2cb1decSSalil Mehta .get_stats = hclgevf_get_stats, 2930e2cb1decSSalil Mehta .update_stats = hclgevf_update_stats, 2931e2cb1decSSalil Mehta .get_strings = hclgevf_get_strings, 2932e2cb1decSSalil Mehta .get_sset_count = hclgevf_get_sset_count, 2933e2cb1decSSalil Mehta .get_rss_key_size = hclgevf_get_rss_key_size, 2934e2cb1decSSalil Mehta .get_rss_indir_size = hclgevf_get_rss_indir_size, 2935e2cb1decSSalil Mehta .get_rss = hclgevf_get_rss, 2936e2cb1decSSalil Mehta .set_rss = hclgevf_set_rss, 2937d97b3072SJian Shen .get_rss_tuple = hclgevf_get_rss_tuple, 2938d97b3072SJian Shen .set_rss_tuple = hclgevf_set_rss_tuple, 2939e2cb1decSSalil Mehta .get_tc_size = hclgevf_get_tc_size, 2940e2cb1decSSalil Mehta .get_fw_version = hclgevf_get_fw_version, 2941e2cb1decSSalil Mehta .set_vlan_filter = hclgevf_set_vlan_filter, 2942b2641e2aSYunsheng Lin .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 29436d4c3981SSalil Mehta .reset_event = hclgevf_reset_event, 2944720bd583SHuazhong Tan .set_default_reset_request = hclgevf_set_def_reset_request, 2945849e4607SPeng Li .get_channels = hclgevf_get_channels, 2946cc719218SPeng Li .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 29471600c3e5SJian Shen .get_regs_len = hclgevf_get_regs_len, 29481600c3e5SJian Shen .get_regs = hclgevf_get_regs, 2949175ec96bSFuyun Liang .get_status = hclgevf_get_status, 29504a152de9SFuyun Liang .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 2951c136b884SPeng Li .get_media_type = hclgevf_get_media_type, 29524d60291bSHuazhong Tan .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 29534d60291bSHuazhong Tan .ae_dev_resetting = hclgevf_ae_dev_resetting, 29544d60291bSHuazhong Tan .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 29555c9f6b39SPeng Li .set_gro_en = hclgevf_gro_en, 2956818f1675SYunsheng Lin .set_mtu = hclgevf_set_mtu, 29570c29d191Sliuzhongzhu .get_global_queue_id = hclgevf_get_qid_global, 29588cdb992fSJian Shen .set_timer_task = hclgevf_set_timer_task, 29599194d18bSliuzhongzhu .get_link_mode = hclgevf_get_link_mode, 2960e2cb1decSSalil Mehta }; 2961e2cb1decSSalil Mehta 2962e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf = { 2963e2cb1decSSalil Mehta .ops = &hclgevf_ops, 2964e2cb1decSSalil Mehta .pdev_id_table = ae_algovf_pci_tbl, 2965e2cb1decSSalil Mehta }; 2966e2cb1decSSalil Mehta 2967e2cb1decSSalil Mehta static int hclgevf_init(void) 2968e2cb1decSSalil Mehta { 2969e2cb1decSSalil Mehta pr_info("%s is initializing\n", HCLGEVF_NAME); 2970e2cb1decSSalil Mehta 2971854cf33aSFuyun Liang hnae3_register_ae_algo(&ae_algovf); 2972854cf33aSFuyun Liang 2973854cf33aSFuyun Liang return 0; 2974e2cb1decSSalil Mehta } 2975e2cb1decSSalil Mehta 2976e2cb1decSSalil Mehta static void hclgevf_exit(void) 2977e2cb1decSSalil Mehta { 2978e2cb1decSSalil Mehta hnae3_unregister_ae_algo(&ae_algovf); 2979e2cb1decSSalil Mehta } 2980e2cb1decSSalil Mehta module_init(hclgevf_init); 2981e2cb1decSSalil Mehta module_exit(hclgevf_exit); 2982e2cb1decSSalil Mehta 2983e2cb1decSSalil Mehta MODULE_LICENSE("GPL"); 2984e2cb1decSSalil Mehta MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 2985e2cb1decSSalil Mehta MODULE_DESCRIPTION("HCLGEVF Driver"); 2986e2cb1decSSalil Mehta MODULE_VERSION(HCLGEVF_MOD_VERSION); 2987