1e2cb1decSSalil Mehta // SPDX-License-Identifier: GPL-2.0+ 2e2cb1decSSalil Mehta // Copyright (c) 2016-2017 Hisilicon Limited. 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #include <linux/etherdevice.h> 5aa5c4f17SHuazhong Tan #include <linux/iopoll.h> 66988eb2aSSalil Mehta #include <net/rtnetlink.h> 7e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 8e2cb1decSSalil Mehta #include "hclgevf_main.h" 9e2cb1decSSalil Mehta #include "hclge_mbx.h" 10e2cb1decSSalil Mehta #include "hnae3.h" 11e2cb1decSSalil Mehta 12e2cb1decSSalil Mehta #define HCLGEVF_NAME "hclgevf" 13e2cb1decSSalil Mehta 149c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 15e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf; 16e2cb1decSSalil Mehta 17e2cb1decSSalil Mehta static const struct pci_device_id ae_algovf_pci_tbl[] = { 18e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 19e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 20e2cb1decSSalil Mehta /* required last entry */ 21e2cb1decSSalil Mehta {0, } 22e2cb1decSSalil Mehta }; 23e2cb1decSSalil Mehta 242f550a46SYunsheng Lin MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 252f550a46SYunsheng Lin 26e2cb1decSSalil Mehta static inline struct hclgevf_dev *hclgevf_ae_get_hdev( 27e2cb1decSSalil Mehta struct hnae3_handle *handle) 28e2cb1decSSalil Mehta { 29e2cb1decSSalil Mehta return container_of(handle, struct hclgevf_dev, nic); 30e2cb1decSSalil Mehta } 31e2cb1decSSalil Mehta 32e2cb1decSSalil Mehta static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 33e2cb1decSSalil Mehta { 34b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 35e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 36e2cb1decSSalil Mehta struct hclgevf_desc desc; 37e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 38e2cb1decSSalil Mehta int status; 39e2cb1decSSalil Mehta int i; 40e2cb1decSSalil Mehta 41b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 42b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 43e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 44e2cb1decSSalil Mehta HCLGEVF_OPC_QUERY_RX_STATUS, 45e2cb1decSSalil Mehta true); 46e2cb1decSSalil Mehta 47e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 48e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 49e2cb1decSSalil Mehta if (status) { 50e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 51e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 52e2cb1decSSalil Mehta status, i); 53e2cb1decSSalil Mehta return status; 54e2cb1decSSalil Mehta } 55e2cb1decSSalil Mehta tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 56cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 57e2cb1decSSalil Mehta 58e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 59e2cb1decSSalil Mehta true); 60e2cb1decSSalil Mehta 61e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 62e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 63e2cb1decSSalil Mehta if (status) { 64e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 65e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 66e2cb1decSSalil Mehta status, i); 67e2cb1decSSalil Mehta return status; 68e2cb1decSSalil Mehta } 69e2cb1decSSalil Mehta tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 70cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 71e2cb1decSSalil Mehta } 72e2cb1decSSalil Mehta 73e2cb1decSSalil Mehta return 0; 74e2cb1decSSalil Mehta } 75e2cb1decSSalil Mehta 76e2cb1decSSalil Mehta static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 77e2cb1decSSalil Mehta { 78e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo = &handle->kinfo; 79e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 80e2cb1decSSalil Mehta u64 *buff = data; 81e2cb1decSSalil Mehta int i; 82e2cb1decSSalil Mehta 83b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 84b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 85e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 86e2cb1decSSalil Mehta } 87e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 88b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 89e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 90e2cb1decSSalil Mehta } 91e2cb1decSSalil Mehta 92e2cb1decSSalil Mehta return buff; 93e2cb1decSSalil Mehta } 94e2cb1decSSalil Mehta 95e2cb1decSSalil Mehta static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 96e2cb1decSSalil Mehta { 97b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 98e2cb1decSSalil Mehta 99b4f1d303SJian Shen return kinfo->num_tqps * 2; 100e2cb1decSSalil Mehta } 101e2cb1decSSalil Mehta 102e2cb1decSSalil Mehta static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 103e2cb1decSSalil Mehta { 104b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 105e2cb1decSSalil Mehta u8 *buff = data; 106e2cb1decSSalil Mehta int i = 0; 107e2cb1decSSalil Mehta 108b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 109b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 110e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1110c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 112e2cb1decSSalil Mehta tqp->index); 113e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 114e2cb1decSSalil Mehta } 115e2cb1decSSalil Mehta 116b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 117b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 118e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1190c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 120e2cb1decSSalil Mehta tqp->index); 121e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 122e2cb1decSSalil Mehta } 123e2cb1decSSalil Mehta 124e2cb1decSSalil Mehta return buff; 125e2cb1decSSalil Mehta } 126e2cb1decSSalil Mehta 127e2cb1decSSalil Mehta static void hclgevf_update_stats(struct hnae3_handle *handle, 128e2cb1decSSalil Mehta struct net_device_stats *net_stats) 129e2cb1decSSalil Mehta { 130e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 131e2cb1decSSalil Mehta int status; 132e2cb1decSSalil Mehta 133e2cb1decSSalil Mehta status = hclgevf_tqps_update_stats(handle); 134e2cb1decSSalil Mehta if (status) 135e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 136e2cb1decSSalil Mehta "VF update of TQPS stats fail, status = %d.\n", 137e2cb1decSSalil Mehta status); 138e2cb1decSSalil Mehta } 139e2cb1decSSalil Mehta 140e2cb1decSSalil Mehta static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 141e2cb1decSSalil Mehta { 142e2cb1decSSalil Mehta if (strset == ETH_SS_TEST) 143e2cb1decSSalil Mehta return -EOPNOTSUPP; 144e2cb1decSSalil Mehta else if (strset == ETH_SS_STATS) 145e2cb1decSSalil Mehta return hclgevf_tqps_get_sset_count(handle, strset); 146e2cb1decSSalil Mehta 147e2cb1decSSalil Mehta return 0; 148e2cb1decSSalil Mehta } 149e2cb1decSSalil Mehta 150e2cb1decSSalil Mehta static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 151e2cb1decSSalil Mehta u8 *data) 152e2cb1decSSalil Mehta { 153e2cb1decSSalil Mehta u8 *p = (char *)data; 154e2cb1decSSalil Mehta 155e2cb1decSSalil Mehta if (strset == ETH_SS_STATS) 156e2cb1decSSalil Mehta p = hclgevf_tqps_get_strings(handle, p); 157e2cb1decSSalil Mehta } 158e2cb1decSSalil Mehta 159e2cb1decSSalil Mehta static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 160e2cb1decSSalil Mehta { 161e2cb1decSSalil Mehta hclgevf_tqps_get_stats(handle, data); 162e2cb1decSSalil Mehta } 163e2cb1decSSalil Mehta 164e2cb1decSSalil Mehta static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 165e2cb1decSSalil Mehta { 166e2cb1decSSalil Mehta u8 resp_msg; 167e2cb1decSSalil Mehta int status; 168e2cb1decSSalil Mehta 169e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 170e2cb1decSSalil Mehta true, &resp_msg, sizeof(u8)); 171e2cb1decSSalil Mehta if (status) { 172e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 173e2cb1decSSalil Mehta "VF request to get TC info from PF failed %d", 174e2cb1decSSalil Mehta status); 175e2cb1decSSalil Mehta return status; 176e2cb1decSSalil Mehta } 177e2cb1decSSalil Mehta 178e2cb1decSSalil Mehta hdev->hw_tc_map = resp_msg; 179e2cb1decSSalil Mehta 180e2cb1decSSalil Mehta return 0; 181e2cb1decSSalil Mehta } 182e2cb1decSSalil Mehta 1836cee6fc3SJian Shen static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 184e2cb1decSSalil Mehta { 185e2cb1decSSalil Mehta #define HCLGEVF_TQPS_RSS_INFO_LEN 8 186e2cb1decSSalil Mehta u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 187e2cb1decSSalil Mehta int status; 188e2cb1decSSalil Mehta 189e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 190e2cb1decSSalil Mehta true, resp_msg, 191e2cb1decSSalil Mehta HCLGEVF_TQPS_RSS_INFO_LEN); 192e2cb1decSSalil Mehta if (status) { 193e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 194e2cb1decSSalil Mehta "VF request to get tqp info from PF failed %d", 195e2cb1decSSalil Mehta status); 196e2cb1decSSalil Mehta return status; 197e2cb1decSSalil Mehta } 198e2cb1decSSalil Mehta 199e2cb1decSSalil Mehta memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 200e2cb1decSSalil Mehta memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 201e2cb1decSSalil Mehta memcpy(&hdev->num_desc, &resp_msg[4], sizeof(u16)); 202e2cb1decSSalil Mehta memcpy(&hdev->rx_buf_len, &resp_msg[6], sizeof(u16)); 203e2cb1decSSalil Mehta 204e2cb1decSSalil Mehta return 0; 205e2cb1decSSalil Mehta } 206e2cb1decSSalil Mehta 207e2cb1decSSalil Mehta static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 208e2cb1decSSalil Mehta { 209e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 210e2cb1decSSalil Mehta int i; 211e2cb1decSSalil Mehta 212e2cb1decSSalil Mehta hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 213e2cb1decSSalil Mehta sizeof(struct hclgevf_tqp), GFP_KERNEL); 214e2cb1decSSalil Mehta if (!hdev->htqp) 215e2cb1decSSalil Mehta return -ENOMEM; 216e2cb1decSSalil Mehta 217e2cb1decSSalil Mehta tqp = hdev->htqp; 218e2cb1decSSalil Mehta 219e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 220e2cb1decSSalil Mehta tqp->dev = &hdev->pdev->dev; 221e2cb1decSSalil Mehta tqp->index = i; 222e2cb1decSSalil Mehta 223e2cb1decSSalil Mehta tqp->q.ae_algo = &ae_algovf; 224e2cb1decSSalil Mehta tqp->q.buf_size = hdev->rx_buf_len; 225e2cb1decSSalil Mehta tqp->q.desc_num = hdev->num_desc; 226e2cb1decSSalil Mehta tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 227e2cb1decSSalil Mehta i * HCLGEVF_TQP_REG_SIZE; 228e2cb1decSSalil Mehta 229e2cb1decSSalil Mehta tqp++; 230e2cb1decSSalil Mehta } 231e2cb1decSSalil Mehta 232e2cb1decSSalil Mehta return 0; 233e2cb1decSSalil Mehta } 234e2cb1decSSalil Mehta 235e2cb1decSSalil Mehta static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 236e2cb1decSSalil Mehta { 237e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 238e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo; 239e2cb1decSSalil Mehta u16 new_tqps = hdev->num_tqps; 240e2cb1decSSalil Mehta int i; 241e2cb1decSSalil Mehta 242e2cb1decSSalil Mehta kinfo = &nic->kinfo; 243e2cb1decSSalil Mehta kinfo->num_tc = 0; 244e2cb1decSSalil Mehta kinfo->num_desc = hdev->num_desc; 245e2cb1decSSalil Mehta kinfo->rx_buf_len = hdev->rx_buf_len; 246e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 247e2cb1decSSalil Mehta if (hdev->hw_tc_map & BIT(i)) 248e2cb1decSSalil Mehta kinfo->num_tc++; 249e2cb1decSSalil Mehta 250e2cb1decSSalil Mehta kinfo->rss_size 251e2cb1decSSalil Mehta = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 252e2cb1decSSalil Mehta new_tqps = kinfo->rss_size * kinfo->num_tc; 253e2cb1decSSalil Mehta kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 254e2cb1decSSalil Mehta 255e2cb1decSSalil Mehta kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 256e2cb1decSSalil Mehta sizeof(struct hnae3_queue *), GFP_KERNEL); 257e2cb1decSSalil Mehta if (!kinfo->tqp) 258e2cb1decSSalil Mehta return -ENOMEM; 259e2cb1decSSalil Mehta 260e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 261e2cb1decSSalil Mehta hdev->htqp[i].q.handle = &hdev->nic; 262e2cb1decSSalil Mehta hdev->htqp[i].q.tqp_index = i; 263e2cb1decSSalil Mehta kinfo->tqp[i] = &hdev->htqp[i].q; 264e2cb1decSSalil Mehta } 265e2cb1decSSalil Mehta 266e2cb1decSSalil Mehta return 0; 267e2cb1decSSalil Mehta } 268e2cb1decSSalil Mehta 269e2cb1decSSalil Mehta static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 270e2cb1decSSalil Mehta { 271e2cb1decSSalil Mehta int status; 272e2cb1decSSalil Mehta u8 resp_msg; 273e2cb1decSSalil Mehta 274e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 275e2cb1decSSalil Mehta 0, false, &resp_msg, sizeof(u8)); 276e2cb1decSSalil Mehta if (status) 277e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 278e2cb1decSSalil Mehta "VF failed to fetch link status(%d) from PF", status); 279e2cb1decSSalil Mehta } 280e2cb1decSSalil Mehta 281e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 282e2cb1decSSalil Mehta { 283e2cb1decSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 284e2cb1decSSalil Mehta struct hnae3_client *client; 285e2cb1decSSalil Mehta 286e2cb1decSSalil Mehta client = handle->client; 287e2cb1decSSalil Mehta 288582d37bbSPeng Li link_state = 289582d37bbSPeng Li test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 290582d37bbSPeng Li 291e2cb1decSSalil Mehta if (link_state != hdev->hw.mac.link) { 292e2cb1decSSalil Mehta client->ops->link_status_change(handle, !!link_state); 293e2cb1decSSalil Mehta hdev->hw.mac.link = link_state; 294e2cb1decSSalil Mehta } 295e2cb1decSSalil Mehta } 296e2cb1decSSalil Mehta 297e2cb1decSSalil Mehta static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 298e2cb1decSSalil Mehta { 299e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 300e2cb1decSSalil Mehta int ret; 301e2cb1decSSalil Mehta 302e2cb1decSSalil Mehta nic->ae_algo = &ae_algovf; 303e2cb1decSSalil Mehta nic->pdev = hdev->pdev; 304e2cb1decSSalil Mehta nic->numa_node_mask = hdev->numa_node_mask; 305424eb834SSalil Mehta nic->flags |= HNAE3_SUPPORT_VF; 306e2cb1decSSalil Mehta 307e2cb1decSSalil Mehta if (hdev->ae_dev->dev_type != HNAE3_DEV_KNIC) { 308e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "unsupported device type %d\n", 309e2cb1decSSalil Mehta hdev->ae_dev->dev_type); 310e2cb1decSSalil Mehta return -EINVAL; 311e2cb1decSSalil Mehta } 312e2cb1decSSalil Mehta 313e2cb1decSSalil Mehta ret = hclgevf_knic_setup(hdev); 314e2cb1decSSalil Mehta if (ret) 315e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 316e2cb1decSSalil Mehta ret); 317e2cb1decSSalil Mehta return ret; 318e2cb1decSSalil Mehta } 319e2cb1decSSalil Mehta 320e2cb1decSSalil Mehta static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 321e2cb1decSSalil Mehta { 32236cbbdf6SPeng Li if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 32336cbbdf6SPeng Li dev_warn(&hdev->pdev->dev, 32436cbbdf6SPeng Li "vector(vector_id %d) has been freed.\n", vector_id); 32536cbbdf6SPeng Li return; 32636cbbdf6SPeng Li } 32736cbbdf6SPeng Li 328e2cb1decSSalil Mehta hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 329e2cb1decSSalil Mehta hdev->num_msi_left += 1; 330e2cb1decSSalil Mehta hdev->num_msi_used -= 1; 331e2cb1decSSalil Mehta } 332e2cb1decSSalil Mehta 333e2cb1decSSalil Mehta static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 334e2cb1decSSalil Mehta struct hnae3_vector_info *vector_info) 335e2cb1decSSalil Mehta { 336e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 337e2cb1decSSalil Mehta struct hnae3_vector_info *vector = vector_info; 338e2cb1decSSalil Mehta int alloc = 0; 339e2cb1decSSalil Mehta int i, j; 340e2cb1decSSalil Mehta 341e2cb1decSSalil Mehta vector_num = min(hdev->num_msi_left, vector_num); 342e2cb1decSSalil Mehta 343e2cb1decSSalil Mehta for (j = 0; j < vector_num; j++) { 344e2cb1decSSalil Mehta for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 345e2cb1decSSalil Mehta if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 346e2cb1decSSalil Mehta vector->vector = pci_irq_vector(hdev->pdev, i); 347e2cb1decSSalil Mehta vector->io_addr = hdev->hw.io_base + 348e2cb1decSSalil Mehta HCLGEVF_VECTOR_REG_BASE + 349e2cb1decSSalil Mehta (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 350e2cb1decSSalil Mehta hdev->vector_status[i] = 0; 351e2cb1decSSalil Mehta hdev->vector_irq[i] = vector->vector; 352e2cb1decSSalil Mehta 353e2cb1decSSalil Mehta vector++; 354e2cb1decSSalil Mehta alloc++; 355e2cb1decSSalil Mehta 356e2cb1decSSalil Mehta break; 357e2cb1decSSalil Mehta } 358e2cb1decSSalil Mehta } 359e2cb1decSSalil Mehta } 360e2cb1decSSalil Mehta hdev->num_msi_left -= alloc; 361e2cb1decSSalil Mehta hdev->num_msi_used += alloc; 362e2cb1decSSalil Mehta 363e2cb1decSSalil Mehta return alloc; 364e2cb1decSSalil Mehta } 365e2cb1decSSalil Mehta 366e2cb1decSSalil Mehta static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 367e2cb1decSSalil Mehta { 368e2cb1decSSalil Mehta int i; 369e2cb1decSSalil Mehta 370e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 371e2cb1decSSalil Mehta if (vector == hdev->vector_irq[i]) 372e2cb1decSSalil Mehta return i; 373e2cb1decSSalil Mehta 374e2cb1decSSalil Mehta return -EINVAL; 375e2cb1decSSalil Mehta } 376e2cb1decSSalil Mehta 377374ad291SJian Shen static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 378374ad291SJian Shen const u8 hfunc, const u8 *key) 379374ad291SJian Shen { 380374ad291SJian Shen struct hclgevf_rss_config_cmd *req; 381374ad291SJian Shen struct hclgevf_desc desc; 382374ad291SJian Shen int key_offset; 383374ad291SJian Shen int key_size; 384374ad291SJian Shen int ret; 385374ad291SJian Shen 386374ad291SJian Shen req = (struct hclgevf_rss_config_cmd *)desc.data; 387374ad291SJian Shen 388374ad291SJian Shen for (key_offset = 0; key_offset < 3; key_offset++) { 389374ad291SJian Shen hclgevf_cmd_setup_basic_desc(&desc, 390374ad291SJian Shen HCLGEVF_OPC_RSS_GENERIC_CONFIG, 391374ad291SJian Shen false); 392374ad291SJian Shen 393374ad291SJian Shen req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 394374ad291SJian Shen req->hash_config |= 395374ad291SJian Shen (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 396374ad291SJian Shen 397374ad291SJian Shen if (key_offset == 2) 398374ad291SJian Shen key_size = 399374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE - HCLGEVF_RSS_HASH_KEY_NUM * 2; 400374ad291SJian Shen else 401374ad291SJian Shen key_size = HCLGEVF_RSS_HASH_KEY_NUM; 402374ad291SJian Shen 403374ad291SJian Shen memcpy(req->hash_key, 404374ad291SJian Shen key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 405374ad291SJian Shen 406374ad291SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 407374ad291SJian Shen if (ret) { 408374ad291SJian Shen dev_err(&hdev->pdev->dev, 409374ad291SJian Shen "Configure RSS config fail, status = %d\n", 410374ad291SJian Shen ret); 411374ad291SJian Shen return ret; 412374ad291SJian Shen } 413374ad291SJian Shen } 414374ad291SJian Shen 415374ad291SJian Shen return 0; 416374ad291SJian Shen } 417374ad291SJian Shen 418e2cb1decSSalil Mehta static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 419e2cb1decSSalil Mehta { 420e2cb1decSSalil Mehta return HCLGEVF_RSS_KEY_SIZE; 421e2cb1decSSalil Mehta } 422e2cb1decSSalil Mehta 423e2cb1decSSalil Mehta static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 424e2cb1decSSalil Mehta { 425e2cb1decSSalil Mehta return HCLGEVF_RSS_IND_TBL_SIZE; 426e2cb1decSSalil Mehta } 427e2cb1decSSalil Mehta 428e2cb1decSSalil Mehta static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 429e2cb1decSSalil Mehta { 430e2cb1decSSalil Mehta const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 431e2cb1decSSalil Mehta struct hclgevf_rss_indirection_table_cmd *req; 432e2cb1decSSalil Mehta struct hclgevf_desc desc; 433e2cb1decSSalil Mehta int status; 434e2cb1decSSalil Mehta int i, j; 435e2cb1decSSalil Mehta 436e2cb1decSSalil Mehta req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 437e2cb1decSSalil Mehta 438e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 439e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 440e2cb1decSSalil Mehta false); 441e2cb1decSSalil Mehta req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 442e2cb1decSSalil Mehta req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 443e2cb1decSSalil Mehta for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 444e2cb1decSSalil Mehta req->rss_result[j] = 445e2cb1decSSalil Mehta indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 446e2cb1decSSalil Mehta 447e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 448e2cb1decSSalil Mehta if (status) { 449e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 450e2cb1decSSalil Mehta "VF failed(=%d) to set RSS indirection table\n", 451e2cb1decSSalil Mehta status); 452e2cb1decSSalil Mehta return status; 453e2cb1decSSalil Mehta } 454e2cb1decSSalil Mehta } 455e2cb1decSSalil Mehta 456e2cb1decSSalil Mehta return 0; 457e2cb1decSSalil Mehta } 458e2cb1decSSalil Mehta 459e2cb1decSSalil Mehta static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 460e2cb1decSSalil Mehta { 461e2cb1decSSalil Mehta struct hclgevf_rss_tc_mode_cmd *req; 462e2cb1decSSalil Mehta u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 463e2cb1decSSalil Mehta u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 464e2cb1decSSalil Mehta u16 tc_size[HCLGEVF_MAX_TC_NUM]; 465e2cb1decSSalil Mehta struct hclgevf_desc desc; 466e2cb1decSSalil Mehta u16 roundup_size; 467e2cb1decSSalil Mehta int status; 468e2cb1decSSalil Mehta int i; 469e2cb1decSSalil Mehta 470e2cb1decSSalil Mehta req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 471e2cb1decSSalil Mehta 472e2cb1decSSalil Mehta roundup_size = roundup_pow_of_two(rss_size); 473e2cb1decSSalil Mehta roundup_size = ilog2(roundup_size); 474e2cb1decSSalil Mehta 475e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 476e2cb1decSSalil Mehta tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 477e2cb1decSSalil Mehta tc_size[i] = roundup_size; 478e2cb1decSSalil Mehta tc_offset[i] = rss_size * i; 479e2cb1decSSalil Mehta } 480e2cb1decSSalil Mehta 481e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 482e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 483e4e87715SPeng Li hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 484e2cb1decSSalil Mehta (tc_valid[i] & 0x1)); 485e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 486e2cb1decSSalil Mehta HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 487e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 488e2cb1decSSalil Mehta HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 489e2cb1decSSalil Mehta } 490e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 491e2cb1decSSalil Mehta if (status) 492e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 493e2cb1decSSalil Mehta "VF failed(=%d) to set rss tc mode\n", status); 494e2cb1decSSalil Mehta 495e2cb1decSSalil Mehta return status; 496e2cb1decSSalil Mehta } 497e2cb1decSSalil Mehta 498e2cb1decSSalil Mehta static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 499e2cb1decSSalil Mehta u8 *hfunc) 500e2cb1decSSalil Mehta { 501e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 502e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 503e2cb1decSSalil Mehta int i; 504e2cb1decSSalil Mehta 505374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 506374ad291SJian Shen /* Get hash algorithm */ 507374ad291SJian Shen if (hfunc) { 508374ad291SJian Shen switch (rss_cfg->hash_algo) { 509374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 510374ad291SJian Shen *hfunc = ETH_RSS_HASH_TOP; 511374ad291SJian Shen break; 512374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 513374ad291SJian Shen *hfunc = ETH_RSS_HASH_XOR; 514374ad291SJian Shen break; 515374ad291SJian Shen default: 516374ad291SJian Shen *hfunc = ETH_RSS_HASH_UNKNOWN; 517374ad291SJian Shen break; 518374ad291SJian Shen } 519374ad291SJian Shen } 520374ad291SJian Shen 521374ad291SJian Shen /* Get the RSS Key required by the user */ 522374ad291SJian Shen if (key) 523374ad291SJian Shen memcpy(key, rss_cfg->rss_hash_key, 524374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 525374ad291SJian Shen } 526374ad291SJian Shen 527e2cb1decSSalil Mehta if (indir) 528e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 529e2cb1decSSalil Mehta indir[i] = rss_cfg->rss_indirection_tbl[i]; 530e2cb1decSSalil Mehta 531374ad291SJian Shen return 0; 532e2cb1decSSalil Mehta } 533e2cb1decSSalil Mehta 534e2cb1decSSalil Mehta static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 535e2cb1decSSalil Mehta const u8 *key, const u8 hfunc) 536e2cb1decSSalil Mehta { 537e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 538e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 539374ad291SJian Shen int ret, i; 540374ad291SJian Shen 541374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 542374ad291SJian Shen /* Set the RSS Hash Key if specififed by the user */ 543374ad291SJian Shen if (key) { 544374ad291SJian Shen switch (hfunc) { 545374ad291SJian Shen case ETH_RSS_HASH_TOP: 546374ad291SJian Shen rss_cfg->hash_algo = 547374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 548374ad291SJian Shen break; 549374ad291SJian Shen case ETH_RSS_HASH_XOR: 550374ad291SJian Shen rss_cfg->hash_algo = 551374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_SIMPLE; 552374ad291SJian Shen break; 553374ad291SJian Shen case ETH_RSS_HASH_NO_CHANGE: 554374ad291SJian Shen break; 555374ad291SJian Shen default: 556374ad291SJian Shen return -EINVAL; 557374ad291SJian Shen } 558374ad291SJian Shen 559374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 560374ad291SJian Shen key); 561374ad291SJian Shen if (ret) 562374ad291SJian Shen return ret; 563374ad291SJian Shen 564374ad291SJian Shen /* Update the shadow RSS key with user specified qids */ 565374ad291SJian Shen memcpy(rss_cfg->rss_hash_key, key, 566374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 567374ad291SJian Shen } 568374ad291SJian Shen } 569e2cb1decSSalil Mehta 570e2cb1decSSalil Mehta /* update the shadow RSS table with user specified qids */ 571e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 572e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = indir[i]; 573e2cb1decSSalil Mehta 574e2cb1decSSalil Mehta /* update the hardware */ 575e2cb1decSSalil Mehta return hclgevf_set_rss_indir_table(hdev); 576e2cb1decSSalil Mehta } 577e2cb1decSSalil Mehta 578d97b3072SJian Shen static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 579d97b3072SJian Shen { 580d97b3072SJian Shen u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 581d97b3072SJian Shen 582d97b3072SJian Shen if (nfc->data & RXH_L4_B_2_3) 583d97b3072SJian Shen hash_sets |= HCLGEVF_D_PORT_BIT; 584d97b3072SJian Shen else 585d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_PORT_BIT; 586d97b3072SJian Shen 587d97b3072SJian Shen if (nfc->data & RXH_IP_SRC) 588d97b3072SJian Shen hash_sets |= HCLGEVF_S_IP_BIT; 589d97b3072SJian Shen else 590d97b3072SJian Shen hash_sets &= ~HCLGEVF_S_IP_BIT; 591d97b3072SJian Shen 592d97b3072SJian Shen if (nfc->data & RXH_IP_DST) 593d97b3072SJian Shen hash_sets |= HCLGEVF_D_IP_BIT; 594d97b3072SJian Shen else 595d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_IP_BIT; 596d97b3072SJian Shen 597d97b3072SJian Shen if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 598d97b3072SJian Shen hash_sets |= HCLGEVF_V_TAG_BIT; 599d97b3072SJian Shen 600d97b3072SJian Shen return hash_sets; 601d97b3072SJian Shen } 602d97b3072SJian Shen 603d97b3072SJian Shen static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 604d97b3072SJian Shen struct ethtool_rxnfc *nfc) 605d97b3072SJian Shen { 606d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 607d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 608d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 609d97b3072SJian Shen struct hclgevf_desc desc; 610d97b3072SJian Shen u8 tuple_sets; 611d97b3072SJian Shen int ret; 612d97b3072SJian Shen 613d97b3072SJian Shen if (handle->pdev->revision == 0x20) 614d97b3072SJian Shen return -EOPNOTSUPP; 615d97b3072SJian Shen 616d97b3072SJian Shen if (nfc->data & 617d97b3072SJian Shen ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 618d97b3072SJian Shen return -EINVAL; 619d97b3072SJian Shen 620d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 621d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 622d97b3072SJian Shen 623d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 624d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 625d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 626d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 627d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 628d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 629d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 630d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 631d97b3072SJian Shen 632d97b3072SJian Shen tuple_sets = hclgevf_get_rss_hash_bits(nfc); 633d97b3072SJian Shen switch (nfc->flow_type) { 634d97b3072SJian Shen case TCP_V4_FLOW: 635d97b3072SJian Shen req->ipv4_tcp_en = tuple_sets; 636d97b3072SJian Shen break; 637d97b3072SJian Shen case TCP_V6_FLOW: 638d97b3072SJian Shen req->ipv6_tcp_en = tuple_sets; 639d97b3072SJian Shen break; 640d97b3072SJian Shen case UDP_V4_FLOW: 641d97b3072SJian Shen req->ipv4_udp_en = tuple_sets; 642d97b3072SJian Shen break; 643d97b3072SJian Shen case UDP_V6_FLOW: 644d97b3072SJian Shen req->ipv6_udp_en = tuple_sets; 645d97b3072SJian Shen break; 646d97b3072SJian Shen case SCTP_V4_FLOW: 647d97b3072SJian Shen req->ipv4_sctp_en = tuple_sets; 648d97b3072SJian Shen break; 649d97b3072SJian Shen case SCTP_V6_FLOW: 650d97b3072SJian Shen if ((nfc->data & RXH_L4_B_0_1) || 651d97b3072SJian Shen (nfc->data & RXH_L4_B_2_3)) 652d97b3072SJian Shen return -EINVAL; 653d97b3072SJian Shen 654d97b3072SJian Shen req->ipv6_sctp_en = tuple_sets; 655d97b3072SJian Shen break; 656d97b3072SJian Shen case IPV4_FLOW: 657d97b3072SJian Shen req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 658d97b3072SJian Shen break; 659d97b3072SJian Shen case IPV6_FLOW: 660d97b3072SJian Shen req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 661d97b3072SJian Shen break; 662d97b3072SJian Shen default: 663d97b3072SJian Shen return -EINVAL; 664d97b3072SJian Shen } 665d97b3072SJian Shen 666d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 667d97b3072SJian Shen if (ret) { 668d97b3072SJian Shen dev_err(&hdev->pdev->dev, 669d97b3072SJian Shen "Set rss tuple fail, status = %d\n", ret); 670d97b3072SJian Shen return ret; 671d97b3072SJian Shen } 672d97b3072SJian Shen 673d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 674d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 675d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 676d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 677d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 678d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 679d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 680d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 681d97b3072SJian Shen return 0; 682d97b3072SJian Shen } 683d97b3072SJian Shen 684d97b3072SJian Shen static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 685d97b3072SJian Shen struct ethtool_rxnfc *nfc) 686d97b3072SJian Shen { 687d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 688d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 689d97b3072SJian Shen u8 tuple_sets; 690d97b3072SJian Shen 691d97b3072SJian Shen if (handle->pdev->revision == 0x20) 692d97b3072SJian Shen return -EOPNOTSUPP; 693d97b3072SJian Shen 694d97b3072SJian Shen nfc->data = 0; 695d97b3072SJian Shen 696d97b3072SJian Shen switch (nfc->flow_type) { 697d97b3072SJian Shen case TCP_V4_FLOW: 698d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 699d97b3072SJian Shen break; 700d97b3072SJian Shen case UDP_V4_FLOW: 701d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 702d97b3072SJian Shen break; 703d97b3072SJian Shen case TCP_V6_FLOW: 704d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 705d97b3072SJian Shen break; 706d97b3072SJian Shen case UDP_V6_FLOW: 707d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 708d97b3072SJian Shen break; 709d97b3072SJian Shen case SCTP_V4_FLOW: 710d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 711d97b3072SJian Shen break; 712d97b3072SJian Shen case SCTP_V6_FLOW: 713d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 714d97b3072SJian Shen break; 715d97b3072SJian Shen case IPV4_FLOW: 716d97b3072SJian Shen case IPV6_FLOW: 717d97b3072SJian Shen tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 718d97b3072SJian Shen break; 719d97b3072SJian Shen default: 720d97b3072SJian Shen return -EINVAL; 721d97b3072SJian Shen } 722d97b3072SJian Shen 723d97b3072SJian Shen if (!tuple_sets) 724d97b3072SJian Shen return 0; 725d97b3072SJian Shen 726d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_PORT_BIT) 727d97b3072SJian Shen nfc->data |= RXH_L4_B_2_3; 728d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_PORT_BIT) 729d97b3072SJian Shen nfc->data |= RXH_L4_B_0_1; 730d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_IP_BIT) 731d97b3072SJian Shen nfc->data |= RXH_IP_DST; 732d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_IP_BIT) 733d97b3072SJian Shen nfc->data |= RXH_IP_SRC; 734d97b3072SJian Shen 735d97b3072SJian Shen return 0; 736d97b3072SJian Shen } 737d97b3072SJian Shen 738d97b3072SJian Shen static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 739d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg) 740d97b3072SJian Shen { 741d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 742d97b3072SJian Shen struct hclgevf_desc desc; 743d97b3072SJian Shen int ret; 744d97b3072SJian Shen 745d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 746d97b3072SJian Shen 747d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 748d97b3072SJian Shen 749d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 750d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 751d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 752d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 753d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 754d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 755d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 756d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 757d97b3072SJian Shen 758d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 759d97b3072SJian Shen if (ret) 760d97b3072SJian Shen dev_err(&hdev->pdev->dev, 761d97b3072SJian Shen "Configure rss input fail, status = %d\n", ret); 762d97b3072SJian Shen return ret; 763d97b3072SJian Shen } 764d97b3072SJian Shen 765e2cb1decSSalil Mehta static int hclgevf_get_tc_size(struct hnae3_handle *handle) 766e2cb1decSSalil Mehta { 767e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 768e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 769e2cb1decSSalil Mehta 770e2cb1decSSalil Mehta return rss_cfg->rss_size; 771e2cb1decSSalil Mehta } 772e2cb1decSSalil Mehta 773e2cb1decSSalil Mehta static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 774b204bc74SPeng Li int vector_id, 775e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 776e2cb1decSSalil Mehta { 777e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 778e2cb1decSSalil Mehta struct hnae3_ring_chain_node *node; 779e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 780e2cb1decSSalil Mehta struct hclgevf_desc desc; 781b204bc74SPeng Li int i = 0; 782e2cb1decSSalil Mehta int status; 783e2cb1decSSalil Mehta u8 type; 784e2cb1decSSalil Mehta 785e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 786e2cb1decSSalil Mehta 787e2cb1decSSalil Mehta for (node = ring_chain; node; node = node->next) { 7885d02a58dSYunsheng Lin int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 7895d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 7905d02a58dSYunsheng Lin 7915d02a58dSYunsheng Lin if (i == 0) { 7925d02a58dSYunsheng Lin hclgevf_cmd_setup_basic_desc(&desc, 7935d02a58dSYunsheng Lin HCLGEVF_OPC_MBX_VF_TO_PF, 7945d02a58dSYunsheng Lin false); 7955d02a58dSYunsheng Lin type = en ? 7965d02a58dSYunsheng Lin HCLGE_MBX_MAP_RING_TO_VECTOR : 7975d02a58dSYunsheng Lin HCLGE_MBX_UNMAP_RING_TO_VECTOR; 7985d02a58dSYunsheng Lin req->msg[0] = type; 7995d02a58dSYunsheng Lin req->msg[1] = vector_id; 8005d02a58dSYunsheng Lin } 8015d02a58dSYunsheng Lin 8025d02a58dSYunsheng Lin req->msg[idx_offset] = 803e4e87715SPeng Li hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 8045d02a58dSYunsheng Lin req->msg[idx_offset + 1] = node->tqp_index; 805e4e87715SPeng Li req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 80679eee410SFuyun Liang HNAE3_RING_GL_IDX_M, 80779eee410SFuyun Liang HNAE3_RING_GL_IDX_S); 80879eee410SFuyun Liang 8095d02a58dSYunsheng Lin i++; 8105d02a58dSYunsheng Lin if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 8115d02a58dSYunsheng Lin HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 8125d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 8135d02a58dSYunsheng Lin !node->next) { 814e2cb1decSSalil Mehta req->msg[2] = i; 815e2cb1decSSalil Mehta 816e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 817e2cb1decSSalil Mehta if (status) { 818e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 819e2cb1decSSalil Mehta "Map TQP fail, status is %d.\n", 820e2cb1decSSalil Mehta status); 821e2cb1decSSalil Mehta return status; 822e2cb1decSSalil Mehta } 823e2cb1decSSalil Mehta i = 0; 824e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 825e2cb1decSSalil Mehta HCLGEVF_OPC_MBX_VF_TO_PF, 826e2cb1decSSalil Mehta false); 827e2cb1decSSalil Mehta req->msg[0] = type; 828e2cb1decSSalil Mehta req->msg[1] = vector_id; 829e2cb1decSSalil Mehta } 830e2cb1decSSalil Mehta } 831e2cb1decSSalil Mehta 832e2cb1decSSalil Mehta return 0; 833e2cb1decSSalil Mehta } 834e2cb1decSSalil Mehta 835e2cb1decSSalil Mehta static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 836e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 837e2cb1decSSalil Mehta { 838b204bc74SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 839b204bc74SPeng Li int vector_id; 840b204bc74SPeng Li 841b204bc74SPeng Li vector_id = hclgevf_get_vector_index(hdev, vector); 842b204bc74SPeng Li if (vector_id < 0) { 843b204bc74SPeng Li dev_err(&handle->pdev->dev, 844b204bc74SPeng Li "Get vector index fail. ret =%d\n", vector_id); 845b204bc74SPeng Li return vector_id; 846b204bc74SPeng Li } 847b204bc74SPeng Li 848b204bc74SPeng Li return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 849e2cb1decSSalil Mehta } 850e2cb1decSSalil Mehta 851e2cb1decSSalil Mehta static int hclgevf_unmap_ring_from_vector( 852e2cb1decSSalil Mehta struct hnae3_handle *handle, 853e2cb1decSSalil Mehta int vector, 854e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 855e2cb1decSSalil Mehta { 856e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 857e2cb1decSSalil Mehta int ret, vector_id; 858e2cb1decSSalil Mehta 859dea846e8SHuazhong Tan if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 860dea846e8SHuazhong Tan return 0; 861dea846e8SHuazhong Tan 862e2cb1decSSalil Mehta vector_id = hclgevf_get_vector_index(hdev, vector); 863e2cb1decSSalil Mehta if (vector_id < 0) { 864e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 865e2cb1decSSalil Mehta "Get vector index fail. ret =%d\n", vector_id); 866e2cb1decSSalil Mehta return vector_id; 867e2cb1decSSalil Mehta } 868e2cb1decSSalil Mehta 869b204bc74SPeng Li ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 8700d3e6631SYunsheng Lin if (ret) 871e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 872e2cb1decSSalil Mehta "Unmap ring from vector fail. vector=%d, ret =%d\n", 873e2cb1decSSalil Mehta vector_id, 874e2cb1decSSalil Mehta ret); 8750d3e6631SYunsheng Lin 876e2cb1decSSalil Mehta return ret; 877e2cb1decSSalil Mehta } 878e2cb1decSSalil Mehta 8790d3e6631SYunsheng Lin static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 8800d3e6631SYunsheng Lin { 8810d3e6631SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 88203718db9SYunsheng Lin int vector_id; 8830d3e6631SYunsheng Lin 88403718db9SYunsheng Lin vector_id = hclgevf_get_vector_index(hdev, vector); 88503718db9SYunsheng Lin if (vector_id < 0) { 88603718db9SYunsheng Lin dev_err(&handle->pdev->dev, 88703718db9SYunsheng Lin "hclgevf_put_vector get vector index fail. ret =%d\n", 88803718db9SYunsheng Lin vector_id); 88903718db9SYunsheng Lin return vector_id; 89003718db9SYunsheng Lin } 89103718db9SYunsheng Lin 89203718db9SYunsheng Lin hclgevf_free_vector(hdev, vector_id); 893e2cb1decSSalil Mehta 894e2cb1decSSalil Mehta return 0; 895e2cb1decSSalil Mehta } 896e2cb1decSSalil Mehta 8973b75c3dfSPeng Li static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 8983b75c3dfSPeng Li bool en_uc_pmc, bool en_mc_pmc) 899e2cb1decSSalil Mehta { 900e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 901e2cb1decSSalil Mehta struct hclgevf_desc desc; 902e2cb1decSSalil Mehta int status; 903e2cb1decSSalil Mehta 904e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 905e2cb1decSSalil Mehta 906e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 907e2cb1decSSalil Mehta req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 9083b75c3dfSPeng Li req->msg[1] = en_uc_pmc ? 1 : 0; 9093b75c3dfSPeng Li req->msg[2] = en_mc_pmc ? 1 : 0; 910e2cb1decSSalil Mehta 911e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 912e2cb1decSSalil Mehta if (status) 913e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 914e2cb1decSSalil Mehta "Set promisc mode fail, status is %d.\n", status); 915e2cb1decSSalil Mehta 916e2cb1decSSalil Mehta return status; 917e2cb1decSSalil Mehta } 918e2cb1decSSalil Mehta 9197fa6be4fSHuazhong Tan static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, 9203b75c3dfSPeng Li bool en_uc_pmc, bool en_mc_pmc) 921e2cb1decSSalil Mehta { 922e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 923e2cb1decSSalil Mehta 9247fa6be4fSHuazhong Tan return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc); 925e2cb1decSSalil Mehta } 926e2cb1decSSalil Mehta 927e2cb1decSSalil Mehta static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, int tqp_id, 928e2cb1decSSalil Mehta int stream_id, bool enable) 929e2cb1decSSalil Mehta { 930e2cb1decSSalil Mehta struct hclgevf_cfg_com_tqp_queue_cmd *req; 931e2cb1decSSalil Mehta struct hclgevf_desc desc; 932e2cb1decSSalil Mehta int status; 933e2cb1decSSalil Mehta 934e2cb1decSSalil Mehta req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 935e2cb1decSSalil Mehta 936e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 937e2cb1decSSalil Mehta false); 938e2cb1decSSalil Mehta req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 939e2cb1decSSalil Mehta req->stream_id = cpu_to_le16(stream_id); 940e2cb1decSSalil Mehta req->enable |= enable << HCLGEVF_TQP_ENABLE_B; 941e2cb1decSSalil Mehta 942e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 943e2cb1decSSalil Mehta if (status) 944e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 945e2cb1decSSalil Mehta "TQP enable fail, status =%d.\n", status); 946e2cb1decSSalil Mehta 947e2cb1decSSalil Mehta return status; 948e2cb1decSSalil Mehta } 949e2cb1decSSalil Mehta 950e2cb1decSSalil Mehta static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 951e2cb1decSSalil Mehta { 952b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 953e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 954e2cb1decSSalil Mehta int i; 955e2cb1decSSalil Mehta 956b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 957b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 958e2cb1decSSalil Mehta memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 959e2cb1decSSalil Mehta } 960e2cb1decSSalil Mehta } 961e2cb1decSSalil Mehta 962e2cb1decSSalil Mehta static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 963e2cb1decSSalil Mehta { 964e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 965e2cb1decSSalil Mehta 966e2cb1decSSalil Mehta ether_addr_copy(p, hdev->hw.mac.mac_addr); 967e2cb1decSSalil Mehta } 968e2cb1decSSalil Mehta 96959098055SFuyun Liang static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 97059098055SFuyun Liang bool is_first) 971e2cb1decSSalil Mehta { 972e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 973e2cb1decSSalil Mehta u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 974e2cb1decSSalil Mehta u8 *new_mac_addr = (u8 *)p; 975e2cb1decSSalil Mehta u8 msg_data[ETH_ALEN * 2]; 97659098055SFuyun Liang u16 subcode; 977e2cb1decSSalil Mehta int status; 978e2cb1decSSalil Mehta 979e2cb1decSSalil Mehta ether_addr_copy(msg_data, new_mac_addr); 980e2cb1decSSalil Mehta ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 981e2cb1decSSalil Mehta 98259098055SFuyun Liang subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 98359098055SFuyun Liang HCLGE_MBX_MAC_VLAN_UC_MODIFY; 98459098055SFuyun Liang 985e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 98659098055SFuyun Liang subcode, msg_data, ETH_ALEN * 2, 9872097fdefSJian Shen true, NULL, 0); 988e2cb1decSSalil Mehta if (!status) 989e2cb1decSSalil Mehta ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 990e2cb1decSSalil Mehta 991e2cb1decSSalil Mehta return status; 992e2cb1decSSalil Mehta } 993e2cb1decSSalil Mehta 994e2cb1decSSalil Mehta static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 995e2cb1decSSalil Mehta const unsigned char *addr) 996e2cb1decSSalil Mehta { 997e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 998e2cb1decSSalil Mehta 999e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1000e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_ADD, 1001e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1002e2cb1decSSalil Mehta } 1003e2cb1decSSalil Mehta 1004e2cb1decSSalil Mehta static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1005e2cb1decSSalil Mehta const unsigned char *addr) 1006e2cb1decSSalil Mehta { 1007e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1008e2cb1decSSalil Mehta 1009e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1010e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1011e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1012e2cb1decSSalil Mehta } 1013e2cb1decSSalil Mehta 1014e2cb1decSSalil Mehta static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1015e2cb1decSSalil Mehta const unsigned char *addr) 1016e2cb1decSSalil Mehta { 1017e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1018e2cb1decSSalil Mehta 1019e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1020e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_ADD, 1021e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1022e2cb1decSSalil Mehta } 1023e2cb1decSSalil Mehta 1024e2cb1decSSalil Mehta static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1025e2cb1decSSalil Mehta const unsigned char *addr) 1026e2cb1decSSalil Mehta { 1027e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1028e2cb1decSSalil Mehta 1029e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1030e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1031e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1032e2cb1decSSalil Mehta } 1033e2cb1decSSalil Mehta 1034e2cb1decSSalil Mehta static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1035e2cb1decSSalil Mehta __be16 proto, u16 vlan_id, 1036e2cb1decSSalil Mehta bool is_kill) 1037e2cb1decSSalil Mehta { 1038e2cb1decSSalil Mehta #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1039e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1040e2cb1decSSalil Mehta u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1041e2cb1decSSalil Mehta 1042e2cb1decSSalil Mehta if (vlan_id > 4095) 1043e2cb1decSSalil Mehta return -EINVAL; 1044e2cb1decSSalil Mehta 1045e2cb1decSSalil Mehta if (proto != htons(ETH_P_8021Q)) 1046e2cb1decSSalil Mehta return -EPROTONOSUPPORT; 1047e2cb1decSSalil Mehta 1048e2cb1decSSalil Mehta msg_data[0] = is_kill; 1049e2cb1decSSalil Mehta memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1050e2cb1decSSalil Mehta memcpy(&msg_data[3], &proto, sizeof(proto)); 1051e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1052e2cb1decSSalil Mehta HCLGE_MBX_VLAN_FILTER, msg_data, 1053e2cb1decSSalil Mehta HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 1054e2cb1decSSalil Mehta } 1055e2cb1decSSalil Mehta 1056b2641e2aSYunsheng Lin static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1057b2641e2aSYunsheng Lin { 1058b2641e2aSYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1059b2641e2aSYunsheng Lin u8 msg_data; 1060b2641e2aSYunsheng Lin 1061b2641e2aSYunsheng Lin msg_data = enable ? 1 : 0; 1062b2641e2aSYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1063b2641e2aSYunsheng Lin HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1064b2641e2aSYunsheng Lin 1, false, NULL, 0); 1065b2641e2aSYunsheng Lin } 1066b2641e2aSYunsheng Lin 10677fa6be4fSHuazhong Tan static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1068e2cb1decSSalil Mehta { 1069e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1070e2cb1decSSalil Mehta u8 msg_data[2]; 10711a426f8bSPeng Li int ret; 1072e2cb1decSSalil Mehta 1073e2cb1decSSalil Mehta memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 1074e2cb1decSSalil Mehta 10751a426f8bSPeng Li /* disable vf queue before send queue reset msg to PF */ 10761a426f8bSPeng Li ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 10771a426f8bSPeng Li if (ret) 10787fa6be4fSHuazhong Tan return ret; 10791a426f8bSPeng Li 10807fa6be4fSHuazhong Tan return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 10811a426f8bSPeng Li 2, true, NULL, 0); 1082e2cb1decSSalil Mehta } 1083e2cb1decSSalil Mehta 10846988eb2aSSalil Mehta static int hclgevf_notify_client(struct hclgevf_dev *hdev, 10856988eb2aSSalil Mehta enum hnae3_reset_notify_type type) 10866988eb2aSSalil Mehta { 10876988eb2aSSalil Mehta struct hnae3_client *client = hdev->nic_client; 10886988eb2aSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 10896a5f6fa3SHuazhong Tan int ret; 10906988eb2aSSalil Mehta 10916988eb2aSSalil Mehta if (!client->ops->reset_notify) 10926988eb2aSSalil Mehta return -EOPNOTSUPP; 10936988eb2aSSalil Mehta 10946a5f6fa3SHuazhong Tan ret = client->ops->reset_notify(handle, type); 10956a5f6fa3SHuazhong Tan if (ret) 10966a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 10976a5f6fa3SHuazhong Tan type, ret); 10986a5f6fa3SHuazhong Tan 10996a5f6fa3SHuazhong Tan return ret; 11006988eb2aSSalil Mehta } 11016988eb2aSSalil Mehta 11026ff3cf07SHuazhong Tan static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 11036ff3cf07SHuazhong Tan { 11046ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 11056ff3cf07SHuazhong Tan 11066ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DONE, &hdev->flr_state); 11076ff3cf07SHuazhong Tan } 11086ff3cf07SHuazhong Tan 11096ff3cf07SHuazhong Tan static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev, 11106ff3cf07SHuazhong Tan unsigned long delay_us, 11116ff3cf07SHuazhong Tan unsigned long wait_cnt) 11126ff3cf07SHuazhong Tan { 11136ff3cf07SHuazhong Tan unsigned long cnt = 0; 11146ff3cf07SHuazhong Tan 11156ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) && 11166ff3cf07SHuazhong Tan cnt++ < wait_cnt) 11176ff3cf07SHuazhong Tan usleep_range(delay_us, delay_us * 2); 11186ff3cf07SHuazhong Tan 11196ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) { 11206ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 11216ff3cf07SHuazhong Tan "flr wait timeout\n"); 11226ff3cf07SHuazhong Tan return -ETIMEDOUT; 11236ff3cf07SHuazhong Tan } 11246ff3cf07SHuazhong Tan 11256ff3cf07SHuazhong Tan return 0; 11266ff3cf07SHuazhong Tan } 11276ff3cf07SHuazhong Tan 11286988eb2aSSalil Mehta static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 11296988eb2aSSalil Mehta { 1130aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_US 20000 1131aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_CNT 2000 1132aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1133aa5c4f17SHuazhong Tan (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1134aa5c4f17SHuazhong Tan 1135aa5c4f17SHuazhong Tan u32 val; 1136aa5c4f17SHuazhong Tan int ret; 11376988eb2aSSalil Mehta 11386988eb2aSSalil Mehta /* wait to check the hardware reset completion status */ 1139aa5c4f17SHuazhong Tan val = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1140aa5c4f17SHuazhong Tan dev_info(&hdev->pdev->dev, "checking vf resetting status: %x\n", val); 1141aa5c4f17SHuazhong Tan 11426ff3cf07SHuazhong Tan if (hdev->reset_type == HNAE3_FLR_RESET) 11436ff3cf07SHuazhong Tan return hclgevf_flr_poll_timeout(hdev, 11446ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_US, 11456ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_CNT); 11466ff3cf07SHuazhong Tan 1147aa5c4f17SHuazhong Tan ret = readl_poll_timeout(hdev->hw.io_base + HCLGEVF_RST_ING, val, 1148aa5c4f17SHuazhong Tan !(val & HCLGEVF_RST_ING_BITS), 1149aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_US, 1150aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 11516988eb2aSSalil Mehta 11526988eb2aSSalil Mehta /* hardware completion status should be available by this time */ 1153aa5c4f17SHuazhong Tan if (ret) { 1154aa5c4f17SHuazhong Tan dev_err(&hdev->pdev->dev, 11556988eb2aSSalil Mehta "could'nt get reset done status from h/w, timeout!\n"); 1156aa5c4f17SHuazhong Tan return ret; 11576988eb2aSSalil Mehta } 11586988eb2aSSalil Mehta 11596988eb2aSSalil Mehta /* we will wait a bit more to let reset of the stack to complete. This 11606988eb2aSSalil Mehta * might happen in case reset assertion was made by PF. Yes, this also 11616988eb2aSSalil Mehta * means we might end up waiting bit more even for VF reset. 11626988eb2aSSalil Mehta */ 11636988eb2aSSalil Mehta msleep(5000); 11646988eb2aSSalil Mehta 11656988eb2aSSalil Mehta return 0; 11666988eb2aSSalil Mehta } 11676988eb2aSSalil Mehta 11686988eb2aSSalil Mehta static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 11696988eb2aSSalil Mehta { 11707a01c897SSalil Mehta int ret; 11717a01c897SSalil Mehta 11726988eb2aSSalil Mehta /* uninitialize the nic client */ 11736a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 11746a5f6fa3SHuazhong Tan if (ret) 11756a5f6fa3SHuazhong Tan return ret; 11766988eb2aSSalil Mehta 11777a01c897SSalil Mehta /* re-initialize the hclge device */ 11789c6f7085SHuazhong Tan ret = hclgevf_reset_hdev(hdev); 11797a01c897SSalil Mehta if (ret) { 11807a01c897SSalil Mehta dev_err(&hdev->pdev->dev, 11817a01c897SSalil Mehta "hclge device re-init failed, VF is disabled!\n"); 11827a01c897SSalil Mehta return ret; 11837a01c897SSalil Mehta } 11846988eb2aSSalil Mehta 11856988eb2aSSalil Mehta /* bring up the nic client again */ 11866a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 11876a5f6fa3SHuazhong Tan if (ret) 11886a5f6fa3SHuazhong Tan return ret; 11896988eb2aSSalil Mehta 11906988eb2aSSalil Mehta return 0; 11916988eb2aSSalil Mehta } 11926988eb2aSSalil Mehta 1193dea846e8SHuazhong Tan static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1194dea846e8SHuazhong Tan { 1195dea846e8SHuazhong Tan int ret = 0; 1196dea846e8SHuazhong Tan 1197dea846e8SHuazhong Tan switch (hdev->reset_type) { 1198dea846e8SHuazhong Tan case HNAE3_VF_FUNC_RESET: 1199dea846e8SHuazhong Tan ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1200dea846e8SHuazhong Tan 0, true, NULL, sizeof(u8)); 1201dea846e8SHuazhong Tan break; 12026ff3cf07SHuazhong Tan case HNAE3_FLR_RESET: 12036ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 12046ff3cf07SHuazhong Tan break; 1205dea846e8SHuazhong Tan default: 1206dea846e8SHuazhong Tan break; 1207dea846e8SHuazhong Tan } 1208dea846e8SHuazhong Tan 1209ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1210ef5f8e50SHuazhong Tan 1211dea846e8SHuazhong Tan dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1212dea846e8SHuazhong Tan hdev->reset_type, ret); 1213dea846e8SHuazhong Tan 1214dea846e8SHuazhong Tan return ret; 1215dea846e8SHuazhong Tan } 1216dea846e8SHuazhong Tan 12176988eb2aSSalil Mehta static int hclgevf_reset(struct hclgevf_dev *hdev) 12186988eb2aSSalil Mehta { 1219dea846e8SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 12206988eb2aSSalil Mehta int ret; 12216988eb2aSSalil Mehta 1222dea846e8SHuazhong Tan /* Initialize ae_dev reset status as well, in case enet layer wants to 1223dea846e8SHuazhong Tan * know if device is undergoing reset 1224dea846e8SHuazhong Tan */ 1225dea846e8SHuazhong Tan ae_dev->reset_type = hdev->reset_type; 12264d60291bSHuazhong Tan hdev->reset_count++; 12276988eb2aSSalil Mehta rtnl_lock(); 12286988eb2aSSalil Mehta 12296988eb2aSSalil Mehta /* bring down the nic to stop any ongoing TX/RX */ 12306a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 12316a5f6fa3SHuazhong Tan if (ret) 12326a5f6fa3SHuazhong Tan goto err_reset_lock; 12336988eb2aSSalil Mehta 123429118ab9SHuazhong Tan rtnl_unlock(); 123529118ab9SHuazhong Tan 12366a5f6fa3SHuazhong Tan ret = hclgevf_reset_prepare_wait(hdev); 12376a5f6fa3SHuazhong Tan if (ret) 12386a5f6fa3SHuazhong Tan goto err_reset; 1239dea846e8SHuazhong Tan 12406988eb2aSSalil Mehta /* check if VF could successfully fetch the hardware reset completion 12416988eb2aSSalil Mehta * status from the hardware 12426988eb2aSSalil Mehta */ 12436988eb2aSSalil Mehta ret = hclgevf_reset_wait(hdev); 12446988eb2aSSalil Mehta if (ret) { 12456988eb2aSSalil Mehta /* can't do much in this situation, will disable VF */ 12466988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, 12476988eb2aSSalil Mehta "VF failed(=%d) to fetch H/W reset completion status\n", 12486988eb2aSSalil Mehta ret); 12496a5f6fa3SHuazhong Tan goto err_reset; 12506988eb2aSSalil Mehta } 12516988eb2aSSalil Mehta 125229118ab9SHuazhong Tan rtnl_lock(); 125329118ab9SHuazhong Tan 12546988eb2aSSalil Mehta /* now, re-initialize the nic client and ae device*/ 12556988eb2aSSalil Mehta ret = hclgevf_reset_stack(hdev); 12566a5f6fa3SHuazhong Tan if (ret) { 12576988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 12586a5f6fa3SHuazhong Tan goto err_reset_lock; 12596a5f6fa3SHuazhong Tan } 12606988eb2aSSalil Mehta 12616988eb2aSSalil Mehta /* bring up the nic to enable TX/RX again */ 12626a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 12636a5f6fa3SHuazhong Tan if (ret) 12646a5f6fa3SHuazhong Tan goto err_reset_lock; 12656988eb2aSSalil Mehta 12666988eb2aSSalil Mehta rtnl_unlock(); 12676988eb2aSSalil Mehta 12686988eb2aSSalil Mehta return ret; 12696a5f6fa3SHuazhong Tan err_reset_lock: 12706a5f6fa3SHuazhong Tan rtnl_unlock(); 12716a5f6fa3SHuazhong Tan err_reset: 12726a5f6fa3SHuazhong Tan /* When VF reset failed, only the higher level reset asserted by PF 12736a5f6fa3SHuazhong Tan * can restore it, so re-initialize the command queue to receive 12746a5f6fa3SHuazhong Tan * this higher reset event. 12756a5f6fa3SHuazhong Tan */ 12766a5f6fa3SHuazhong Tan hclgevf_cmd_init(hdev); 12776a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "failed to reset VF\n"); 12786a5f6fa3SHuazhong Tan 12796a5f6fa3SHuazhong Tan return ret; 12806988eb2aSSalil Mehta } 12816988eb2aSSalil Mehta 1282720bd583SHuazhong Tan static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1283720bd583SHuazhong Tan unsigned long *addr) 1284720bd583SHuazhong Tan { 1285720bd583SHuazhong Tan enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1286720bd583SHuazhong Tan 1287dea846e8SHuazhong Tan /* return the highest priority reset level amongst all */ 1288b90fcc5bSHuazhong Tan if (test_bit(HNAE3_VF_RESET, addr)) { 1289b90fcc5bSHuazhong Tan rst_level = HNAE3_VF_RESET; 1290b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_RESET, addr); 1291b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1292b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1293b90fcc5bSHuazhong Tan } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1294dea846e8SHuazhong Tan rst_level = HNAE3_VF_FULL_RESET; 1295dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FULL_RESET, addr); 1296dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1297aa5c4f17SHuazhong Tan } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1298aa5c4f17SHuazhong Tan rst_level = HNAE3_VF_PF_FUNC_RESET; 1299aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1300aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1301dea846e8SHuazhong Tan } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1302dea846e8SHuazhong Tan rst_level = HNAE3_VF_FUNC_RESET; 1303dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 13046ff3cf07SHuazhong Tan } else if (test_bit(HNAE3_FLR_RESET, addr)) { 13056ff3cf07SHuazhong Tan rst_level = HNAE3_FLR_RESET; 13066ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_RESET, addr); 1307720bd583SHuazhong Tan } 1308720bd583SHuazhong Tan 1309720bd583SHuazhong Tan return rst_level; 1310720bd583SHuazhong Tan } 1311720bd583SHuazhong Tan 13126ae4e733SShiju Jose static void hclgevf_reset_event(struct pci_dev *pdev, 13136ae4e733SShiju Jose struct hnae3_handle *handle) 13146d4c3981SSalil Mehta { 13156ff3cf07SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 13166ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 13176d4c3981SSalil Mehta 13186d4c3981SSalil Mehta dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 13196d4c3981SSalil Mehta 13206ff3cf07SHuazhong Tan if (hdev->default_reset_request) 13210742ed7cSHuazhong Tan hdev->reset_level = 1322720bd583SHuazhong Tan hclgevf_get_reset_level(hdev, 1323720bd583SHuazhong Tan &hdev->default_reset_request); 1324720bd583SHuazhong Tan else 1325dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 13266d4c3981SSalil Mehta 1327436667d2SSalil Mehta /* reset of this VF requested */ 1328436667d2SSalil Mehta set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1329436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 13306d4c3981SSalil Mehta 13310742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 13326d4c3981SSalil Mehta } 13336d4c3981SSalil Mehta 1334720bd583SHuazhong Tan static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1335720bd583SHuazhong Tan enum hnae3_reset_type rst_type) 1336720bd583SHuazhong Tan { 1337720bd583SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1338720bd583SHuazhong Tan 1339720bd583SHuazhong Tan set_bit(rst_type, &hdev->default_reset_request); 1340720bd583SHuazhong Tan } 1341720bd583SHuazhong Tan 13426ff3cf07SHuazhong Tan static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 13436ff3cf07SHuazhong Tan { 13446ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_MS 100 13456ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_CNT 50 13466ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 13476ff3cf07SHuazhong Tan int cnt = 0; 13486ff3cf07SHuazhong Tan 13496ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 13506ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DONE, &hdev->flr_state); 13516ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request); 13526ff3cf07SHuazhong Tan hclgevf_reset_event(hdev->pdev, NULL); 13536ff3cf07SHuazhong Tan 13546ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) && 13556ff3cf07SHuazhong Tan cnt++ < HCLGEVF_FLR_WAIT_CNT) 13566ff3cf07SHuazhong Tan msleep(HCLGEVF_FLR_WAIT_MS); 13576ff3cf07SHuazhong Tan 13586ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state)) 13596ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 13606ff3cf07SHuazhong Tan "flr wait down timeout: %d\n", cnt); 13616ff3cf07SHuazhong Tan } 13626ff3cf07SHuazhong Tan 1363e2cb1decSSalil Mehta static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1364e2cb1decSSalil Mehta { 1365e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1366e2cb1decSSalil Mehta 1367e2cb1decSSalil Mehta return hdev->fw_version; 1368e2cb1decSSalil Mehta } 1369e2cb1decSSalil Mehta 1370e2cb1decSSalil Mehta static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1371e2cb1decSSalil Mehta { 1372e2cb1decSSalil Mehta struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1373e2cb1decSSalil Mehta 1374e2cb1decSSalil Mehta vector->vector_irq = pci_irq_vector(hdev->pdev, 1375e2cb1decSSalil Mehta HCLGEVF_MISC_VECTOR_NUM); 1376e2cb1decSSalil Mehta vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1377e2cb1decSSalil Mehta /* vector status always valid for Vector 0 */ 1378e2cb1decSSalil Mehta hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1379e2cb1decSSalil Mehta hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1380e2cb1decSSalil Mehta 1381e2cb1decSSalil Mehta hdev->num_msi_left -= 1; 1382e2cb1decSSalil Mehta hdev->num_msi_used += 1; 1383e2cb1decSSalil Mehta } 1384e2cb1decSSalil Mehta 138535a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 138635a1e503SSalil Mehta { 138735a1e503SSalil Mehta if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) && 138835a1e503SSalil Mehta !test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) { 138935a1e503SSalil Mehta set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 139035a1e503SSalil Mehta schedule_work(&hdev->rst_service_task); 139135a1e503SSalil Mehta } 139235a1e503SSalil Mehta } 139335a1e503SSalil Mehta 139407a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1395e2cb1decSSalil Mehta { 139607a0556aSSalil Mehta if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) && 139707a0556aSSalil Mehta !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) { 139807a0556aSSalil Mehta set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1399e2cb1decSSalil Mehta schedule_work(&hdev->mbx_service_task); 1400e2cb1decSSalil Mehta } 140107a0556aSSalil Mehta } 1402e2cb1decSSalil Mehta 1403e2cb1decSSalil Mehta static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 1404e2cb1decSSalil Mehta { 1405e2cb1decSSalil Mehta if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 1406e2cb1decSSalil Mehta !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 1407e2cb1decSSalil Mehta schedule_work(&hdev->service_task); 1408e2cb1decSSalil Mehta } 1409e2cb1decSSalil Mehta 1410436667d2SSalil Mehta static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev) 1411436667d2SSalil Mehta { 141207a0556aSSalil Mehta /* if we have any pending mailbox event then schedule the mbx task */ 141307a0556aSSalil Mehta if (hdev->mbx_event_pending) 141407a0556aSSalil Mehta hclgevf_mbx_task_schedule(hdev); 141507a0556aSSalil Mehta 1416436667d2SSalil Mehta if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state)) 1417436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 1418436667d2SSalil Mehta } 1419436667d2SSalil Mehta 1420e2cb1decSSalil Mehta static void hclgevf_service_timer(struct timer_list *t) 1421e2cb1decSSalil Mehta { 1422e2cb1decSSalil Mehta struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 1423e2cb1decSSalil Mehta 1424e2cb1decSSalil Mehta mod_timer(&hdev->service_timer, jiffies + 5 * HZ); 1425e2cb1decSSalil Mehta 1426e2cb1decSSalil Mehta hclgevf_task_schedule(hdev); 1427e2cb1decSSalil Mehta } 1428e2cb1decSSalil Mehta 142935a1e503SSalil Mehta static void hclgevf_reset_service_task(struct work_struct *work) 143035a1e503SSalil Mehta { 143135a1e503SSalil Mehta struct hclgevf_dev *hdev = 143235a1e503SSalil Mehta container_of(work, struct hclgevf_dev, rst_service_task); 1433a8dedb65SSalil Mehta int ret; 143435a1e503SSalil Mehta 143535a1e503SSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 143635a1e503SSalil Mehta return; 143735a1e503SSalil Mehta 143835a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 143935a1e503SSalil Mehta 1440436667d2SSalil Mehta if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1441436667d2SSalil Mehta &hdev->reset_state)) { 1442436667d2SSalil Mehta /* PF has initmated that it is about to reset the hardware. 1443436667d2SSalil Mehta * We now have to poll & check if harware has actually completed 1444436667d2SSalil Mehta * the reset sequence. On hardware reset completion, VF needs to 1445436667d2SSalil Mehta * reset the client and ae device. 144635a1e503SSalil Mehta */ 1447436667d2SSalil Mehta hdev->reset_attempts = 0; 1448436667d2SSalil Mehta 1449dea846e8SHuazhong Tan hdev->last_reset_time = jiffies; 1450dea846e8SHuazhong Tan while ((hdev->reset_type = 1451dea846e8SHuazhong Tan hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 1452dea846e8SHuazhong Tan != HNAE3_NONE_RESET) { 14536988eb2aSSalil Mehta ret = hclgevf_reset(hdev); 14546988eb2aSSalil Mehta if (ret) 1455dea846e8SHuazhong Tan dev_err(&hdev->pdev->dev, 1456dea846e8SHuazhong Tan "VF stack reset failed %d.\n", ret); 1457dea846e8SHuazhong Tan } 1458436667d2SSalil Mehta } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1459436667d2SSalil Mehta &hdev->reset_state)) { 1460436667d2SSalil Mehta /* we could be here when either of below happens: 1461436667d2SSalil Mehta * 1. reset was initiated due to watchdog timeout due to 1462436667d2SSalil Mehta * a. IMP was earlier reset and our TX got choked down and 1463436667d2SSalil Mehta * which resulted in watchdog reacting and inducing VF 1464436667d2SSalil Mehta * reset. This also means our cmdq would be unreliable. 1465436667d2SSalil Mehta * b. problem in TX due to other lower layer(example link 1466436667d2SSalil Mehta * layer not functioning properly etc.) 1467436667d2SSalil Mehta * 2. VF reset might have been initiated due to some config 1468436667d2SSalil Mehta * change. 1469436667d2SSalil Mehta * 1470436667d2SSalil Mehta * NOTE: Theres no clear way to detect above cases than to react 1471436667d2SSalil Mehta * to the response of PF for this reset request. PF will ack the 1472436667d2SSalil Mehta * 1b and 2. cases but we will not get any intimation about 1a 1473436667d2SSalil Mehta * from PF as cmdq would be in unreliable state i.e. mailbox 1474436667d2SSalil Mehta * communication between PF and VF would be broken. 1475436667d2SSalil Mehta */ 1476436667d2SSalil Mehta 1477436667d2SSalil Mehta /* if we are never geting into pending state it means either: 1478436667d2SSalil Mehta * 1. PF is not receiving our request which could be due to IMP 1479436667d2SSalil Mehta * reset 1480436667d2SSalil Mehta * 2. PF is screwed 1481436667d2SSalil Mehta * We cannot do much for 2. but to check first we can try reset 1482436667d2SSalil Mehta * our PCIe + stack and see if it alleviates the problem. 1483436667d2SSalil Mehta */ 1484436667d2SSalil Mehta if (hdev->reset_attempts > 3) { 1485436667d2SSalil Mehta /* prepare for full reset of stack + pcie interface */ 1486dea846e8SHuazhong Tan set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1487436667d2SSalil Mehta 1488436667d2SSalil Mehta /* "defer" schedule the reset task again */ 1489436667d2SSalil Mehta set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1490436667d2SSalil Mehta } else { 1491436667d2SSalil Mehta hdev->reset_attempts++; 1492436667d2SSalil Mehta 1493dea846e8SHuazhong Tan set_bit(hdev->reset_level, &hdev->reset_pending); 1494dea846e8SHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1495436667d2SSalil Mehta } 1496dea846e8SHuazhong Tan hclgevf_reset_task_schedule(hdev); 1497436667d2SSalil Mehta } 149835a1e503SSalil Mehta 149935a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 150035a1e503SSalil Mehta } 150135a1e503SSalil Mehta 1502e2cb1decSSalil Mehta static void hclgevf_mailbox_service_task(struct work_struct *work) 1503e2cb1decSSalil Mehta { 1504e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1505e2cb1decSSalil Mehta 1506e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 1507e2cb1decSSalil Mehta 1508e2cb1decSSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1509e2cb1decSSalil Mehta return; 1510e2cb1decSSalil Mehta 1511e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1512e2cb1decSSalil Mehta 151307a0556aSSalil Mehta hclgevf_mbx_async_handler(hdev); 1514e2cb1decSSalil Mehta 1515e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1516e2cb1decSSalil Mehta } 1517e2cb1decSSalil Mehta 1518e2cb1decSSalil Mehta static void hclgevf_service_task(struct work_struct *work) 1519e2cb1decSSalil Mehta { 1520e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1521e2cb1decSSalil Mehta 1522e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, service_task); 1523e2cb1decSSalil Mehta 1524e2cb1decSSalil Mehta /* request the link status from the PF. PF would be able to tell VF 1525e2cb1decSSalil Mehta * about such updates in future so we might remove this later 1526e2cb1decSSalil Mehta */ 1527e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1528e2cb1decSSalil Mehta 1529436667d2SSalil Mehta hclgevf_deferred_task_schedule(hdev); 1530436667d2SSalil Mehta 1531e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1532e2cb1decSSalil Mehta } 1533e2cb1decSSalil Mehta 1534e2cb1decSSalil Mehta static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1535e2cb1decSSalil Mehta { 1536e2cb1decSSalil Mehta hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1537e2cb1decSSalil Mehta } 1538e2cb1decSSalil Mehta 1539b90fcc5bSHuazhong Tan static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1540b90fcc5bSHuazhong Tan u32 *clearval) 1541e2cb1decSSalil Mehta { 1542b90fcc5bSHuazhong Tan u32 cmdq_src_reg, rst_ing_reg; 1543e2cb1decSSalil Mehta 1544e2cb1decSSalil Mehta /* fetch the events from their corresponding regs */ 1545e2cb1decSSalil Mehta cmdq_src_reg = hclgevf_read_dev(&hdev->hw, 1546e2cb1decSSalil Mehta HCLGEVF_VECTOR0_CMDQ_SRC_REG); 1547e2cb1decSSalil Mehta 1548b90fcc5bSHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_src_reg) { 1549b90fcc5bSHuazhong Tan rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1550b90fcc5bSHuazhong Tan dev_info(&hdev->pdev->dev, 1551b90fcc5bSHuazhong Tan "receive reset interrupt 0x%x!\n", rst_ing_reg); 1552b90fcc5bSHuazhong Tan set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1553b90fcc5bSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1554ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1555b90fcc5bSHuazhong Tan cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RST_INT_B); 1556b90fcc5bSHuazhong Tan *clearval = cmdq_src_reg; 1557b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_RST; 1558b90fcc5bSHuazhong Tan } 1559b90fcc5bSHuazhong Tan 1560e2cb1decSSalil Mehta /* check for vector0 mailbox(=CMDQ RX) event source */ 1561e2cb1decSSalil Mehta if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 1562e2cb1decSSalil Mehta cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1563e2cb1decSSalil Mehta *clearval = cmdq_src_reg; 1564b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_MBX; 1565e2cb1decSSalil Mehta } 1566e2cb1decSSalil Mehta 1567e2cb1decSSalil Mehta dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 1568e2cb1decSSalil Mehta 1569b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_OTHER; 1570e2cb1decSSalil Mehta } 1571e2cb1decSSalil Mehta 1572e2cb1decSSalil Mehta static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1573e2cb1decSSalil Mehta { 1574e2cb1decSSalil Mehta writel(en ? 1 : 0, vector->addr); 1575e2cb1decSSalil Mehta } 1576e2cb1decSSalil Mehta 1577e2cb1decSSalil Mehta static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1578e2cb1decSSalil Mehta { 1579b90fcc5bSHuazhong Tan enum hclgevf_evt_cause event_cause; 1580e2cb1decSSalil Mehta struct hclgevf_dev *hdev = data; 1581e2cb1decSSalil Mehta u32 clearval; 1582e2cb1decSSalil Mehta 1583e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 1584b90fcc5bSHuazhong Tan event_cause = hclgevf_check_evt_cause(hdev, &clearval); 1585e2cb1decSSalil Mehta 1586b90fcc5bSHuazhong Tan switch (event_cause) { 1587b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_RST: 1588b90fcc5bSHuazhong Tan hclgevf_reset_task_schedule(hdev); 1589b90fcc5bSHuazhong Tan break; 1590b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_MBX: 159107a0556aSSalil Mehta hclgevf_mbx_handler(hdev); 1592b90fcc5bSHuazhong Tan break; 1593b90fcc5bSHuazhong Tan default: 1594b90fcc5bSHuazhong Tan break; 1595b90fcc5bSHuazhong Tan } 1596e2cb1decSSalil Mehta 1597b90fcc5bSHuazhong Tan if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 1598e2cb1decSSalil Mehta hclgevf_clear_event_cause(hdev, clearval); 1599e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 1600b90fcc5bSHuazhong Tan } 1601e2cb1decSSalil Mehta 1602e2cb1decSSalil Mehta return IRQ_HANDLED; 1603e2cb1decSSalil Mehta } 1604e2cb1decSSalil Mehta 1605e2cb1decSSalil Mehta static int hclgevf_configure(struct hclgevf_dev *hdev) 1606e2cb1decSSalil Mehta { 1607e2cb1decSSalil Mehta int ret; 1608e2cb1decSSalil Mehta 1609c136b884SPeng Li hdev->hw.mac.media_type = HNAE3_MEDIA_TYPE_NONE; 1610c136b884SPeng Li 1611e2cb1decSSalil Mehta /* get queue configuration from PF */ 16126cee6fc3SJian Shen ret = hclgevf_get_queue_info(hdev); 1613e2cb1decSSalil Mehta if (ret) 1614e2cb1decSSalil Mehta return ret; 1615e2cb1decSSalil Mehta /* get tc configuration from PF */ 1616e2cb1decSSalil Mehta return hclgevf_get_tc_info(hdev); 1617e2cb1decSSalil Mehta } 1618e2cb1decSSalil Mehta 16197a01c897SSalil Mehta static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 16207a01c897SSalil Mehta { 16217a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 16227a01c897SSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 16237a01c897SSalil Mehta 16247a01c897SSalil Mehta hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 16257a01c897SSalil Mehta if (!hdev) 16267a01c897SSalil Mehta return -ENOMEM; 16277a01c897SSalil Mehta 16287a01c897SSalil Mehta hdev->pdev = pdev; 16297a01c897SSalil Mehta hdev->ae_dev = ae_dev; 16307a01c897SSalil Mehta ae_dev->priv = hdev; 16317a01c897SSalil Mehta 16327a01c897SSalil Mehta return 0; 16337a01c897SSalil Mehta } 16347a01c897SSalil Mehta 1635e2cb1decSSalil Mehta static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 1636e2cb1decSSalil Mehta { 1637e2cb1decSSalil Mehta struct hnae3_handle *roce = &hdev->roce; 1638e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 1639e2cb1decSSalil Mehta 164007acf909SJian Shen roce->rinfo.num_vectors = hdev->num_roce_msix; 1641e2cb1decSSalil Mehta 1642e2cb1decSSalil Mehta if (hdev->num_msi_left < roce->rinfo.num_vectors || 1643e2cb1decSSalil Mehta hdev->num_msi_left == 0) 1644e2cb1decSSalil Mehta return -EINVAL; 1645e2cb1decSSalil Mehta 164607acf909SJian Shen roce->rinfo.base_vector = hdev->roce_base_vector; 1647e2cb1decSSalil Mehta 1648e2cb1decSSalil Mehta roce->rinfo.netdev = nic->kinfo.netdev; 1649e2cb1decSSalil Mehta roce->rinfo.roce_io_base = hdev->hw.io_base; 1650e2cb1decSSalil Mehta 1651e2cb1decSSalil Mehta roce->pdev = nic->pdev; 1652e2cb1decSSalil Mehta roce->ae_algo = nic->ae_algo; 1653e2cb1decSSalil Mehta roce->numa_node_mask = nic->numa_node_mask; 1654e2cb1decSSalil Mehta 1655e2cb1decSSalil Mehta return 0; 1656e2cb1decSSalil Mehta } 1657e2cb1decSSalil Mehta 1658b26a6feaSPeng Li static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 1659b26a6feaSPeng Li { 1660b26a6feaSPeng Li struct hclgevf_cfg_gro_status_cmd *req; 1661b26a6feaSPeng Li struct hclgevf_desc desc; 1662b26a6feaSPeng Li int ret; 1663b26a6feaSPeng Li 1664b26a6feaSPeng Li if (!hnae3_dev_gro_supported(hdev)) 1665b26a6feaSPeng Li return 0; 1666b26a6feaSPeng Li 1667b26a6feaSPeng Li hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 1668b26a6feaSPeng Li false); 1669b26a6feaSPeng Li req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 1670b26a6feaSPeng Li 1671b26a6feaSPeng Li req->gro_en = cpu_to_le16(en ? 1 : 0); 1672b26a6feaSPeng Li 1673b26a6feaSPeng Li ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1674b26a6feaSPeng Li if (ret) 1675b26a6feaSPeng Li dev_err(&hdev->pdev->dev, 1676b26a6feaSPeng Li "VF GRO hardware config cmd failed, ret = %d.\n", ret); 1677b26a6feaSPeng Li 1678b26a6feaSPeng Li return ret; 1679b26a6feaSPeng Li } 1680b26a6feaSPeng Li 1681e2cb1decSSalil Mehta static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 1682e2cb1decSSalil Mehta { 1683e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1684e2cb1decSSalil Mehta int i, ret; 1685e2cb1decSSalil Mehta 1686e2cb1decSSalil Mehta rss_cfg->rss_size = hdev->rss_size_max; 1687e2cb1decSSalil Mehta 1688374ad291SJian Shen if (hdev->pdev->revision >= 0x21) { 1689374ad291SJian Shen rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 1690374ad291SJian Shen netdev_rss_key_fill(rss_cfg->rss_hash_key, 1691374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 1692374ad291SJian Shen 1693374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 1694374ad291SJian Shen rss_cfg->rss_hash_key); 1695374ad291SJian Shen if (ret) 1696374ad291SJian Shen return ret; 1697d97b3072SJian Shen 1698d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = 1699d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1700d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = 1701d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1702d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = 1703d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1704d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = 1705d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1706d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = 1707d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1708d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = 1709d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1710d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = 1711d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1712d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = 1713d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1714d97b3072SJian Shen 1715d97b3072SJian Shen ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 1716d97b3072SJian Shen if (ret) 1717d97b3072SJian Shen return ret; 1718d97b3072SJian Shen 1719374ad291SJian Shen } 1720374ad291SJian Shen 1721e2cb1decSSalil Mehta /* Initialize RSS indirect table for each vport */ 1722e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 1723e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max; 1724e2cb1decSSalil Mehta 1725e2cb1decSSalil Mehta ret = hclgevf_set_rss_indir_table(hdev); 1726e2cb1decSSalil Mehta if (ret) 1727e2cb1decSSalil Mehta return ret; 1728e2cb1decSSalil Mehta 1729e2cb1decSSalil Mehta return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max); 1730e2cb1decSSalil Mehta } 1731e2cb1decSSalil Mehta 1732e2cb1decSSalil Mehta static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 1733e2cb1decSSalil Mehta { 1734e2cb1decSSalil Mehta /* other vlan config(like, VLAN TX/RX offload) would also be added 1735e2cb1decSSalil Mehta * here later 1736e2cb1decSSalil Mehta */ 1737e2cb1decSSalil Mehta return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 1738e2cb1decSSalil Mehta false); 1739e2cb1decSSalil Mehta } 1740e2cb1decSSalil Mehta 1741e2cb1decSSalil Mehta static int hclgevf_ae_start(struct hnae3_handle *handle) 1742e2cb1decSSalil Mehta { 1743e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1744e2cb1decSSalil Mehta 1745e2cb1decSSalil Mehta /* reset tqp stats */ 1746e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 1747e2cb1decSSalil Mehta 1748e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1749e2cb1decSSalil Mehta 1750e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1751e2cb1decSSalil Mehta mod_timer(&hdev->service_timer, jiffies + HZ); 1752e2cb1decSSalil Mehta 1753e2cb1decSSalil Mehta return 0; 1754e2cb1decSSalil Mehta } 1755e2cb1decSSalil Mehta 1756e2cb1decSSalil Mehta static void hclgevf_ae_stop(struct hnae3_handle *handle) 1757e2cb1decSSalil Mehta { 1758e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1759e2cb1decSSalil Mehta 17602f7e4896SFuyun Liang set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 17612f7e4896SFuyun Liang 1762e2cb1decSSalil Mehta /* reset tqp stats */ 1763e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 17648cc6c1f7SFuyun Liang del_timer_sync(&hdev->service_timer); 17658cc6c1f7SFuyun Liang cancel_work_sync(&hdev->service_task); 1766f5be7967SYunsheng Lin clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 17678cc6c1f7SFuyun Liang hclgevf_update_link_status(hdev, 0); 1768e2cb1decSSalil Mehta } 1769e2cb1decSSalil Mehta 1770e2cb1decSSalil Mehta static void hclgevf_state_init(struct hclgevf_dev *hdev) 1771e2cb1decSSalil Mehta { 1772e2cb1decSSalil Mehta /* setup tasks for the MBX */ 1773e2cb1decSSalil Mehta INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 1774e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1775e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1776e2cb1decSSalil Mehta 1777e2cb1decSSalil Mehta /* setup tasks for service timer */ 1778e2cb1decSSalil Mehta timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 1779e2cb1decSSalil Mehta 1780e2cb1decSSalil Mehta INIT_WORK(&hdev->service_task, hclgevf_service_task); 1781e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1782e2cb1decSSalil Mehta 178335a1e503SSalil Mehta INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task); 178435a1e503SSalil Mehta 1785e2cb1decSSalil Mehta mutex_init(&hdev->mbx_resp.mbx_mutex); 1786e2cb1decSSalil Mehta 1787e2cb1decSSalil Mehta /* bring the device down */ 1788e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1789e2cb1decSSalil Mehta } 1790e2cb1decSSalil Mehta 1791e2cb1decSSalil Mehta static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 1792e2cb1decSSalil Mehta { 1793e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1794e2cb1decSSalil Mehta 1795e2cb1decSSalil Mehta if (hdev->service_timer.function) 1796e2cb1decSSalil Mehta del_timer_sync(&hdev->service_timer); 1797e2cb1decSSalil Mehta if (hdev->service_task.func) 1798e2cb1decSSalil Mehta cancel_work_sync(&hdev->service_task); 1799e2cb1decSSalil Mehta if (hdev->mbx_service_task.func) 1800e2cb1decSSalil Mehta cancel_work_sync(&hdev->mbx_service_task); 180135a1e503SSalil Mehta if (hdev->rst_service_task.func) 180235a1e503SSalil Mehta cancel_work_sync(&hdev->rst_service_task); 1803e2cb1decSSalil Mehta 1804e2cb1decSSalil Mehta mutex_destroy(&hdev->mbx_resp.mbx_mutex); 1805e2cb1decSSalil Mehta } 1806e2cb1decSSalil Mehta 1807e2cb1decSSalil Mehta static int hclgevf_init_msi(struct hclgevf_dev *hdev) 1808e2cb1decSSalil Mehta { 1809e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 1810e2cb1decSSalil Mehta int vectors; 1811e2cb1decSSalil Mehta int i; 1812e2cb1decSSalil Mehta 181307acf909SJian Shen if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) 181407acf909SJian Shen vectors = pci_alloc_irq_vectors(pdev, 181507acf909SJian Shen hdev->roce_base_msix_offset + 1, 181607acf909SJian Shen hdev->num_msi, 181707acf909SJian Shen PCI_IRQ_MSIX); 181807acf909SJian Shen else 1819e2cb1decSSalil Mehta vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 1820e2cb1decSSalil Mehta PCI_IRQ_MSI | PCI_IRQ_MSIX); 182107acf909SJian Shen 1822e2cb1decSSalil Mehta if (vectors < 0) { 1823e2cb1decSSalil Mehta dev_err(&pdev->dev, 1824e2cb1decSSalil Mehta "failed(%d) to allocate MSI/MSI-X vectors\n", 1825e2cb1decSSalil Mehta vectors); 1826e2cb1decSSalil Mehta return vectors; 1827e2cb1decSSalil Mehta } 1828e2cb1decSSalil Mehta if (vectors < hdev->num_msi) 1829e2cb1decSSalil Mehta dev_warn(&hdev->pdev->dev, 1830e2cb1decSSalil Mehta "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 1831e2cb1decSSalil Mehta hdev->num_msi, vectors); 1832e2cb1decSSalil Mehta 1833e2cb1decSSalil Mehta hdev->num_msi = vectors; 1834e2cb1decSSalil Mehta hdev->num_msi_left = vectors; 1835e2cb1decSSalil Mehta hdev->base_msi_vector = pdev->irq; 183607acf909SJian Shen hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 1837e2cb1decSSalil Mehta 1838e2cb1decSSalil Mehta hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 1839e2cb1decSSalil Mehta sizeof(u16), GFP_KERNEL); 1840e2cb1decSSalil Mehta if (!hdev->vector_status) { 1841e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 1842e2cb1decSSalil Mehta return -ENOMEM; 1843e2cb1decSSalil Mehta } 1844e2cb1decSSalil Mehta 1845e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 1846e2cb1decSSalil Mehta hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 1847e2cb1decSSalil Mehta 1848e2cb1decSSalil Mehta hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 1849e2cb1decSSalil Mehta sizeof(int), GFP_KERNEL); 1850e2cb1decSSalil Mehta if (!hdev->vector_irq) { 1851862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 1852e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 1853e2cb1decSSalil Mehta return -ENOMEM; 1854e2cb1decSSalil Mehta } 1855e2cb1decSSalil Mehta 1856e2cb1decSSalil Mehta return 0; 1857e2cb1decSSalil Mehta } 1858e2cb1decSSalil Mehta 1859e2cb1decSSalil Mehta static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 1860e2cb1decSSalil Mehta { 1861e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 1862e2cb1decSSalil Mehta 1863862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 1864862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_irq); 1865e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 1866e2cb1decSSalil Mehta } 1867e2cb1decSSalil Mehta 1868e2cb1decSSalil Mehta static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 1869e2cb1decSSalil Mehta { 1870e2cb1decSSalil Mehta int ret = 0; 1871e2cb1decSSalil Mehta 1872e2cb1decSSalil Mehta hclgevf_get_misc_vector(hdev); 1873e2cb1decSSalil Mehta 1874e2cb1decSSalil Mehta ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 1875e2cb1decSSalil Mehta 0, "hclgevf_cmd", hdev); 1876e2cb1decSSalil Mehta if (ret) { 1877e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 1878e2cb1decSSalil Mehta hdev->misc_vector.vector_irq); 1879e2cb1decSSalil Mehta return ret; 1880e2cb1decSSalil Mehta } 1881e2cb1decSSalil Mehta 18821819e409SXi Wang hclgevf_clear_event_cause(hdev, 0); 18831819e409SXi Wang 1884e2cb1decSSalil Mehta /* enable misc. vector(vector 0) */ 1885e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 1886e2cb1decSSalil Mehta 1887e2cb1decSSalil Mehta return ret; 1888e2cb1decSSalil Mehta } 1889e2cb1decSSalil Mehta 1890e2cb1decSSalil Mehta static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 1891e2cb1decSSalil Mehta { 1892e2cb1decSSalil Mehta /* disable misc vector(vector 0) */ 1893e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 18941819e409SXi Wang synchronize_irq(hdev->misc_vector.vector_irq); 1895e2cb1decSSalil Mehta free_irq(hdev->misc_vector.vector_irq, hdev); 1896e2cb1decSSalil Mehta hclgevf_free_vector(hdev, 0); 1897e2cb1decSSalil Mehta } 1898e2cb1decSSalil Mehta 1899e718a93fSPeng Li static int hclgevf_init_client_instance(struct hnae3_client *client, 1900e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 1901e2cb1decSSalil Mehta { 1902e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 1903e2cb1decSSalil Mehta int ret; 1904e2cb1decSSalil Mehta 1905e2cb1decSSalil Mehta switch (client->type) { 1906e2cb1decSSalil Mehta case HNAE3_CLIENT_KNIC: 1907e2cb1decSSalil Mehta hdev->nic_client = client; 1908e2cb1decSSalil Mehta hdev->nic.client = client; 1909e2cb1decSSalil Mehta 1910e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->nic); 1911e2cb1decSSalil Mehta if (ret) 191249dd8054SJian Shen goto clear_nic; 1913e2cb1decSSalil Mehta 1914d9f28fc2SJian Shen hnae3_set_client_init_flag(client, ae_dev, 1); 1915d9f28fc2SJian Shen 1916e2cb1decSSalil Mehta if (hdev->roce_client && hnae3_dev_roce_supported(hdev)) { 1917e2cb1decSSalil Mehta struct hnae3_client *rc = hdev->roce_client; 1918e2cb1decSSalil Mehta 1919e2cb1decSSalil Mehta ret = hclgevf_init_roce_base_info(hdev); 1920e2cb1decSSalil Mehta if (ret) 192149dd8054SJian Shen goto clear_roce; 1922e2cb1decSSalil Mehta ret = rc->ops->init_instance(&hdev->roce); 1923e2cb1decSSalil Mehta if (ret) 192449dd8054SJian Shen goto clear_roce; 1925d9f28fc2SJian Shen 1926d9f28fc2SJian Shen hnae3_set_client_init_flag(hdev->roce_client, ae_dev, 1927d9f28fc2SJian Shen 1); 1928e2cb1decSSalil Mehta } 1929e2cb1decSSalil Mehta break; 1930e2cb1decSSalil Mehta case HNAE3_CLIENT_UNIC: 1931e2cb1decSSalil Mehta hdev->nic_client = client; 1932e2cb1decSSalil Mehta hdev->nic.client = client; 1933e2cb1decSSalil Mehta 1934e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->nic); 1935e2cb1decSSalil Mehta if (ret) 193649dd8054SJian Shen goto clear_nic; 1937d9f28fc2SJian Shen 1938d9f28fc2SJian Shen hnae3_set_client_init_flag(client, ae_dev, 1); 1939e2cb1decSSalil Mehta break; 1940e2cb1decSSalil Mehta case HNAE3_CLIENT_ROCE: 1941544a7bcdSLijun Ou if (hnae3_dev_roce_supported(hdev)) { 1942e2cb1decSSalil Mehta hdev->roce_client = client; 1943e2cb1decSSalil Mehta hdev->roce.client = client; 1944544a7bcdSLijun Ou } 1945e2cb1decSSalil Mehta 1946544a7bcdSLijun Ou if (hdev->roce_client && hdev->nic_client) { 1947e2cb1decSSalil Mehta ret = hclgevf_init_roce_base_info(hdev); 1948e2cb1decSSalil Mehta if (ret) 194949dd8054SJian Shen goto clear_roce; 1950e2cb1decSSalil Mehta 1951e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->roce); 1952e2cb1decSSalil Mehta if (ret) 195349dd8054SJian Shen goto clear_roce; 1954e2cb1decSSalil Mehta } 1955d9f28fc2SJian Shen 1956d9f28fc2SJian Shen hnae3_set_client_init_flag(client, ae_dev, 1); 1957fa7a4bd5SJian Shen break; 1958fa7a4bd5SJian Shen default: 1959fa7a4bd5SJian Shen return -EINVAL; 1960e2cb1decSSalil Mehta } 1961e2cb1decSSalil Mehta 1962e2cb1decSSalil Mehta return 0; 196349dd8054SJian Shen 196449dd8054SJian Shen clear_nic: 196549dd8054SJian Shen hdev->nic_client = NULL; 196649dd8054SJian Shen hdev->nic.client = NULL; 196749dd8054SJian Shen return ret; 196849dd8054SJian Shen clear_roce: 196949dd8054SJian Shen hdev->roce_client = NULL; 197049dd8054SJian Shen hdev->roce.client = NULL; 197149dd8054SJian Shen return ret; 1972e2cb1decSSalil Mehta } 1973e2cb1decSSalil Mehta 1974e718a93fSPeng Li static void hclgevf_uninit_client_instance(struct hnae3_client *client, 1975e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 1976e2cb1decSSalil Mehta { 1977e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 1978e718a93fSPeng Li 1979e2cb1decSSalil Mehta /* un-init roce, if it exists */ 198049dd8054SJian Shen if (hdev->roce_client) { 1981e2cb1decSSalil Mehta hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 198249dd8054SJian Shen hdev->roce_client = NULL; 198349dd8054SJian Shen hdev->roce.client = NULL; 198449dd8054SJian Shen } 1985e2cb1decSSalil Mehta 1986e2cb1decSSalil Mehta /* un-init nic/unic, if this was not called by roce client */ 198749dd8054SJian Shen if (client->ops->uninit_instance && hdev->nic_client && 198849dd8054SJian Shen client->type != HNAE3_CLIENT_ROCE) { 1989e2cb1decSSalil Mehta client->ops->uninit_instance(&hdev->nic, 0); 199049dd8054SJian Shen hdev->nic_client = NULL; 199149dd8054SJian Shen hdev->nic.client = NULL; 199249dd8054SJian Shen } 1993e2cb1decSSalil Mehta } 1994e2cb1decSSalil Mehta 1995e2cb1decSSalil Mehta static int hclgevf_pci_init(struct hclgevf_dev *hdev) 1996e2cb1decSSalil Mehta { 1997e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 1998e2cb1decSSalil Mehta struct hclgevf_hw *hw; 1999e2cb1decSSalil Mehta int ret; 2000e2cb1decSSalil Mehta 2001e2cb1decSSalil Mehta ret = pci_enable_device(pdev); 2002e2cb1decSSalil Mehta if (ret) { 2003e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed to enable PCI device\n"); 20043e249d3bSFuyun Liang return ret; 2005e2cb1decSSalil Mehta } 2006e2cb1decSSalil Mehta 2007e2cb1decSSalil Mehta ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2008e2cb1decSSalil Mehta if (ret) { 2009e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2010e2cb1decSSalil Mehta goto err_disable_device; 2011e2cb1decSSalil Mehta } 2012e2cb1decSSalil Mehta 2013e2cb1decSSalil Mehta ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2014e2cb1decSSalil Mehta if (ret) { 2015e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2016e2cb1decSSalil Mehta goto err_disable_device; 2017e2cb1decSSalil Mehta } 2018e2cb1decSSalil Mehta 2019e2cb1decSSalil Mehta pci_set_master(pdev); 2020e2cb1decSSalil Mehta hw = &hdev->hw; 2021e2cb1decSSalil Mehta hw->hdev = hdev; 20222e1ea493SPeng Li hw->io_base = pci_iomap(pdev, 2, 0); 2023e2cb1decSSalil Mehta if (!hw->io_base) { 2024e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't map configuration register space\n"); 2025e2cb1decSSalil Mehta ret = -ENOMEM; 2026e2cb1decSSalil Mehta goto err_clr_master; 2027e2cb1decSSalil Mehta } 2028e2cb1decSSalil Mehta 2029e2cb1decSSalil Mehta return 0; 2030e2cb1decSSalil Mehta 2031e2cb1decSSalil Mehta err_clr_master: 2032e2cb1decSSalil Mehta pci_clear_master(pdev); 2033e2cb1decSSalil Mehta pci_release_regions(pdev); 2034e2cb1decSSalil Mehta err_disable_device: 2035e2cb1decSSalil Mehta pci_disable_device(pdev); 20363e249d3bSFuyun Liang 2037e2cb1decSSalil Mehta return ret; 2038e2cb1decSSalil Mehta } 2039e2cb1decSSalil Mehta 2040e2cb1decSSalil Mehta static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2041e2cb1decSSalil Mehta { 2042e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2043e2cb1decSSalil Mehta 2044e2cb1decSSalil Mehta pci_iounmap(pdev, hdev->hw.io_base); 2045e2cb1decSSalil Mehta pci_clear_master(pdev); 2046e2cb1decSSalil Mehta pci_release_regions(pdev); 2047e2cb1decSSalil Mehta pci_disable_device(pdev); 2048e2cb1decSSalil Mehta } 2049e2cb1decSSalil Mehta 205007acf909SJian Shen static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 205107acf909SJian Shen { 205207acf909SJian Shen struct hclgevf_query_res_cmd *req; 205307acf909SJian Shen struct hclgevf_desc desc; 205407acf909SJian Shen int ret; 205507acf909SJian Shen 205607acf909SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 205707acf909SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 205807acf909SJian Shen if (ret) { 205907acf909SJian Shen dev_err(&hdev->pdev->dev, 206007acf909SJian Shen "query vf resource failed, ret = %d.\n", ret); 206107acf909SJian Shen return ret; 206207acf909SJian Shen } 206307acf909SJian Shen 206407acf909SJian Shen req = (struct hclgevf_query_res_cmd *)desc.data; 206507acf909SJian Shen 206607acf909SJian Shen if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) { 206707acf909SJian Shen hdev->roce_base_msix_offset = 206807acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 206907acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_M, 207007acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_S); 207107acf909SJian Shen hdev->num_roce_msix = 207207acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 207307acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 207407acf909SJian Shen 207507acf909SJian Shen /* VF should have NIC vectors and Roce vectors, NIC vectors 207607acf909SJian Shen * are queued before Roce vectors. The offset is fixed to 64. 207707acf909SJian Shen */ 207807acf909SJian Shen hdev->num_msi = hdev->num_roce_msix + 207907acf909SJian Shen hdev->roce_base_msix_offset; 208007acf909SJian Shen } else { 208107acf909SJian Shen hdev->num_msi = 208207acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 208307acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 208407acf909SJian Shen } 208507acf909SJian Shen 208607acf909SJian Shen return 0; 208707acf909SJian Shen } 208807acf909SJian Shen 2089862d969aSHuazhong Tan static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2090862d969aSHuazhong Tan { 2091862d969aSHuazhong Tan struct pci_dev *pdev = hdev->pdev; 2092862d969aSHuazhong Tan int ret = 0; 2093862d969aSHuazhong Tan 2094862d969aSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2095862d969aSHuazhong Tan test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2096862d969aSHuazhong Tan hclgevf_misc_irq_uninit(hdev); 2097862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2098862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2099862d969aSHuazhong Tan } 2100862d969aSHuazhong Tan 2101862d969aSHuazhong Tan if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2102862d969aSHuazhong Tan pci_set_master(pdev); 2103862d969aSHuazhong Tan ret = hclgevf_init_msi(hdev); 2104862d969aSHuazhong Tan if (ret) { 2105862d969aSHuazhong Tan dev_err(&pdev->dev, 2106862d969aSHuazhong Tan "failed(%d) to init MSI/MSI-X\n", ret); 2107862d969aSHuazhong Tan return ret; 2108862d969aSHuazhong Tan } 2109862d969aSHuazhong Tan 2110862d969aSHuazhong Tan ret = hclgevf_misc_irq_init(hdev); 2111862d969aSHuazhong Tan if (ret) { 2112862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2113862d969aSHuazhong Tan dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2114862d969aSHuazhong Tan ret); 2115862d969aSHuazhong Tan return ret; 2116862d969aSHuazhong Tan } 2117862d969aSHuazhong Tan 2118862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2119862d969aSHuazhong Tan } 2120862d969aSHuazhong Tan 2121862d969aSHuazhong Tan return ret; 2122862d969aSHuazhong Tan } 2123862d969aSHuazhong Tan 21249c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2125e2cb1decSSalil Mehta { 21267a01c897SSalil Mehta struct pci_dev *pdev = hdev->pdev; 2127e2cb1decSSalil Mehta int ret; 2128e2cb1decSSalil Mehta 2129862d969aSHuazhong Tan ret = hclgevf_pci_reset(hdev); 2130862d969aSHuazhong Tan if (ret) { 2131862d969aSHuazhong Tan dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2132862d969aSHuazhong Tan return ret; 2133862d969aSHuazhong Tan } 2134862d969aSHuazhong Tan 21359c6f7085SHuazhong Tan ret = hclgevf_cmd_init(hdev); 21369c6f7085SHuazhong Tan if (ret) { 21379c6f7085SHuazhong Tan dev_err(&pdev->dev, "cmd failed %d\n", ret); 21389c6f7085SHuazhong Tan return ret; 21397a01c897SSalil Mehta } 2140e2cb1decSSalil Mehta 21419c6f7085SHuazhong Tan ret = hclgevf_rss_init_hw(hdev); 21429c6f7085SHuazhong Tan if (ret) { 21439c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 21449c6f7085SHuazhong Tan "failed(%d) to initialize RSS\n", ret); 21459c6f7085SHuazhong Tan return ret; 21469c6f7085SHuazhong Tan } 21479c6f7085SHuazhong Tan 2148b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2149b26a6feaSPeng Li if (ret) 2150b26a6feaSPeng Li return ret; 2151b26a6feaSPeng Li 21529c6f7085SHuazhong Tan ret = hclgevf_init_vlan_config(hdev); 21539c6f7085SHuazhong Tan if (ret) { 21549c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 21559c6f7085SHuazhong Tan "failed(%d) to initialize VLAN config\n", ret); 21569c6f7085SHuazhong Tan return ret; 21579c6f7085SHuazhong Tan } 21589c6f7085SHuazhong Tan 21599c6f7085SHuazhong Tan dev_info(&hdev->pdev->dev, "Reset done\n"); 21609c6f7085SHuazhong Tan 21619c6f7085SHuazhong Tan return 0; 21629c6f7085SHuazhong Tan } 21639c6f7085SHuazhong Tan 21649c6f7085SHuazhong Tan static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 21659c6f7085SHuazhong Tan { 21669c6f7085SHuazhong Tan struct pci_dev *pdev = hdev->pdev; 21679c6f7085SHuazhong Tan int ret; 21689c6f7085SHuazhong Tan 2169e2cb1decSSalil Mehta ret = hclgevf_pci_init(hdev); 2170e2cb1decSSalil Mehta if (ret) { 2171e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI initialization failed\n"); 2172e2cb1decSSalil Mehta return ret; 2173e2cb1decSSalil Mehta } 2174e2cb1decSSalil Mehta 21758b0195a3SHuazhong Tan ret = hclgevf_cmd_queue_init(hdev); 21768b0195a3SHuazhong Tan if (ret) { 21778b0195a3SHuazhong Tan dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret); 21788b0195a3SHuazhong Tan goto err_cmd_queue_init; 21798b0195a3SHuazhong Tan } 21808b0195a3SHuazhong Tan 2181eddf0462SYunsheng Lin ret = hclgevf_cmd_init(hdev); 2182eddf0462SYunsheng Lin if (ret) 2183eddf0462SYunsheng Lin goto err_cmd_init; 2184eddf0462SYunsheng Lin 218507acf909SJian Shen /* Get vf resource */ 218607acf909SJian Shen ret = hclgevf_query_vf_resource(hdev); 218707acf909SJian Shen if (ret) { 218807acf909SJian Shen dev_err(&hdev->pdev->dev, 218907acf909SJian Shen "Query vf status error, ret = %d.\n", ret); 21908b0195a3SHuazhong Tan goto err_cmd_init; 219107acf909SJian Shen } 219207acf909SJian Shen 219307acf909SJian Shen ret = hclgevf_init_msi(hdev); 219407acf909SJian Shen if (ret) { 219507acf909SJian Shen dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 21968b0195a3SHuazhong Tan goto err_cmd_init; 219707acf909SJian Shen } 219807acf909SJian Shen 219907acf909SJian Shen hclgevf_state_init(hdev); 2200dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 220107acf909SJian Shen 2202e2cb1decSSalil Mehta ret = hclgevf_misc_irq_init(hdev); 2203e2cb1decSSalil Mehta if (ret) { 2204e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2205e2cb1decSSalil Mehta ret); 2206e2cb1decSSalil Mehta goto err_misc_irq_init; 2207e2cb1decSSalil Mehta } 2208e2cb1decSSalil Mehta 2209862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2210862d969aSHuazhong Tan 2211e2cb1decSSalil Mehta ret = hclgevf_configure(hdev); 2212e2cb1decSSalil Mehta if (ret) { 2213e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2214e2cb1decSSalil Mehta goto err_config; 2215e2cb1decSSalil Mehta } 2216e2cb1decSSalil Mehta 2217e2cb1decSSalil Mehta ret = hclgevf_alloc_tqps(hdev); 2218e2cb1decSSalil Mehta if (ret) { 2219e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2220e2cb1decSSalil Mehta goto err_config; 2221e2cb1decSSalil Mehta } 2222e2cb1decSSalil Mehta 2223e2cb1decSSalil Mehta ret = hclgevf_set_handle_info(hdev); 2224e2cb1decSSalil Mehta if (ret) { 2225e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 2226e2cb1decSSalil Mehta goto err_config; 2227e2cb1decSSalil Mehta } 2228e2cb1decSSalil Mehta 2229b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2230b26a6feaSPeng Li if (ret) 2231b26a6feaSPeng Li goto err_config; 2232b26a6feaSPeng Li 2233e2cb1decSSalil Mehta /* Initialize RSS for this VF */ 2234e2cb1decSSalil Mehta ret = hclgevf_rss_init_hw(hdev); 2235e2cb1decSSalil Mehta if (ret) { 2236e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2237e2cb1decSSalil Mehta "failed(%d) to initialize RSS\n", ret); 2238e2cb1decSSalil Mehta goto err_config; 2239e2cb1decSSalil Mehta } 2240e2cb1decSSalil Mehta 2241e2cb1decSSalil Mehta ret = hclgevf_init_vlan_config(hdev); 2242e2cb1decSSalil Mehta if (ret) { 2243e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2244e2cb1decSSalil Mehta "failed(%d) to initialize VLAN config\n", ret); 2245e2cb1decSSalil Mehta goto err_config; 2246e2cb1decSSalil Mehta } 2247e2cb1decSSalil Mehta 22480742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 2249e2cb1decSSalil Mehta pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME); 2250e2cb1decSSalil Mehta 2251e2cb1decSSalil Mehta return 0; 2252e2cb1decSSalil Mehta 2253e2cb1decSSalil Mehta err_config: 2254e2cb1decSSalil Mehta hclgevf_misc_irq_uninit(hdev); 2255e2cb1decSSalil Mehta err_misc_irq_init: 2256e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2257e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 225807acf909SJian Shen err_cmd_init: 22598b0195a3SHuazhong Tan hclgevf_cmd_uninit(hdev); 22608b0195a3SHuazhong Tan err_cmd_queue_init: 2261e2cb1decSSalil Mehta hclgevf_pci_uninit(hdev); 2262862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2263e2cb1decSSalil Mehta return ret; 2264e2cb1decSSalil Mehta } 2265e2cb1decSSalil Mehta 22667a01c897SSalil Mehta static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2267e2cb1decSSalil Mehta { 2268e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2269862d969aSHuazhong Tan 2270862d969aSHuazhong Tan if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2271eddf0462SYunsheng Lin hclgevf_misc_irq_uninit(hdev); 2272e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 2273e2cb1decSSalil Mehta hclgevf_pci_uninit(hdev); 22747a01c897SSalil Mehta } 22757a01c897SSalil Mehta 2276862d969aSHuazhong Tan hclgevf_cmd_uninit(hdev); 2277862d969aSHuazhong Tan } 2278862d969aSHuazhong Tan 22797a01c897SSalil Mehta static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 22807a01c897SSalil Mehta { 22817a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 22827a01c897SSalil Mehta int ret; 22837a01c897SSalil Mehta 22847a01c897SSalil Mehta ret = hclgevf_alloc_hdev(ae_dev); 22857a01c897SSalil Mehta if (ret) { 22867a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device allocation failed\n"); 22877a01c897SSalil Mehta return ret; 22887a01c897SSalil Mehta } 22897a01c897SSalil Mehta 22907a01c897SSalil Mehta ret = hclgevf_init_hdev(ae_dev->priv); 22917a01c897SSalil Mehta if (ret) 22927a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device initialization failed\n"); 22937a01c897SSalil Mehta 22947a01c897SSalil Mehta return ret; 22957a01c897SSalil Mehta } 22967a01c897SSalil Mehta 22977a01c897SSalil Mehta static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 22987a01c897SSalil Mehta { 22997a01c897SSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 23007a01c897SSalil Mehta 23017a01c897SSalil Mehta hclgevf_uninit_hdev(hdev); 2302e2cb1decSSalil Mehta ae_dev->priv = NULL; 2303e2cb1decSSalil Mehta } 2304e2cb1decSSalil Mehta 2305849e4607SPeng Li static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2306849e4607SPeng Li { 2307849e4607SPeng Li struct hnae3_handle *nic = &hdev->nic; 2308849e4607SPeng Li struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2309849e4607SPeng Li 2310849e4607SPeng Li return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps); 2311849e4607SPeng Li } 2312849e4607SPeng Li 2313849e4607SPeng Li /** 2314849e4607SPeng Li * hclgevf_get_channels - Get the current channels enabled and max supported. 2315849e4607SPeng Li * @handle: hardware information for network interface 2316849e4607SPeng Li * @ch: ethtool channels structure 2317849e4607SPeng Li * 2318849e4607SPeng Li * We don't support separate tx and rx queues as channels. The other count 2319849e4607SPeng Li * represents how many queues are being used for control. max_combined counts 2320849e4607SPeng Li * how many queue pairs we can support. They may not be mapped 1 to 1 with 2321849e4607SPeng Li * q_vectors since we support a lot more queue pairs than q_vectors. 2322849e4607SPeng Li **/ 2323849e4607SPeng Li static void hclgevf_get_channels(struct hnae3_handle *handle, 2324849e4607SPeng Li struct ethtool_channels *ch) 2325849e4607SPeng Li { 2326849e4607SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2327849e4607SPeng Li 2328849e4607SPeng Li ch->max_combined = hclgevf_get_max_channels(hdev); 2329849e4607SPeng Li ch->other_count = 0; 2330849e4607SPeng Li ch->max_other = 0; 2331849e4607SPeng Li ch->combined_count = hdev->num_tqps; 2332849e4607SPeng Li } 2333849e4607SPeng Li 2334cc719218SPeng Li static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 23350d43bf45SHuazhong Tan u16 *alloc_tqps, u16 *max_rss_size) 2336cc719218SPeng Li { 2337cc719218SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2338cc719218SPeng Li 23390d43bf45SHuazhong Tan *alloc_tqps = hdev->num_tqps; 2340cc719218SPeng Li *max_rss_size = hdev->rss_size_max; 2341cc719218SPeng Li } 2342cc719218SPeng Li 2343175ec96bSFuyun Liang static int hclgevf_get_status(struct hnae3_handle *handle) 2344175ec96bSFuyun Liang { 2345175ec96bSFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2346175ec96bSFuyun Liang 2347175ec96bSFuyun Liang return hdev->hw.mac.link; 2348175ec96bSFuyun Liang } 2349175ec96bSFuyun Liang 23504a152de9SFuyun Liang static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 23514a152de9SFuyun Liang u8 *auto_neg, u32 *speed, 23524a152de9SFuyun Liang u8 *duplex) 23534a152de9SFuyun Liang { 23544a152de9SFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 23554a152de9SFuyun Liang 23564a152de9SFuyun Liang if (speed) 23574a152de9SFuyun Liang *speed = hdev->hw.mac.speed; 23584a152de9SFuyun Liang if (duplex) 23594a152de9SFuyun Liang *duplex = hdev->hw.mac.duplex; 23604a152de9SFuyun Liang if (auto_neg) 23614a152de9SFuyun Liang *auto_neg = AUTONEG_DISABLE; 23624a152de9SFuyun Liang } 23634a152de9SFuyun Liang 23644a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 23654a152de9SFuyun Liang u8 duplex) 23664a152de9SFuyun Liang { 23674a152de9SFuyun Liang hdev->hw.mac.speed = speed; 23684a152de9SFuyun Liang hdev->hw.mac.duplex = duplex; 23694a152de9SFuyun Liang } 23704a152de9SFuyun Liang 2371c136b884SPeng Li static void hclgevf_get_media_type(struct hnae3_handle *handle, 2372c136b884SPeng Li u8 *media_type) 2373c136b884SPeng Li { 2374c136b884SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2375c136b884SPeng Li if (media_type) 2376c136b884SPeng Li *media_type = hdev->hw.mac.media_type; 2377c136b884SPeng Li } 2378c136b884SPeng Li 23794d60291bSHuazhong Tan static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 23804d60291bSHuazhong Tan { 23814d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 23824d60291bSHuazhong Tan 2383aa5c4f17SHuazhong Tan return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 23844d60291bSHuazhong Tan } 23854d60291bSHuazhong Tan 23864d60291bSHuazhong Tan static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 23874d60291bSHuazhong Tan { 23884d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 23894d60291bSHuazhong Tan 23904d60291bSHuazhong Tan return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 23914d60291bSHuazhong Tan } 23924d60291bSHuazhong Tan 23934d60291bSHuazhong Tan static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 23944d60291bSHuazhong Tan { 23954d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 23964d60291bSHuazhong Tan 23974d60291bSHuazhong Tan return hdev->reset_count; 23984d60291bSHuazhong Tan } 23994d60291bSHuazhong Tan 2400e2cb1decSSalil Mehta static const struct hnae3_ae_ops hclgevf_ops = { 2401e2cb1decSSalil Mehta .init_ae_dev = hclgevf_init_ae_dev, 2402e2cb1decSSalil Mehta .uninit_ae_dev = hclgevf_uninit_ae_dev, 24036ff3cf07SHuazhong Tan .flr_prepare = hclgevf_flr_prepare, 24046ff3cf07SHuazhong Tan .flr_done = hclgevf_flr_done, 2405e718a93fSPeng Li .init_client_instance = hclgevf_init_client_instance, 2406e718a93fSPeng Li .uninit_client_instance = hclgevf_uninit_client_instance, 2407e2cb1decSSalil Mehta .start = hclgevf_ae_start, 2408e2cb1decSSalil Mehta .stop = hclgevf_ae_stop, 2409e2cb1decSSalil Mehta .map_ring_to_vector = hclgevf_map_ring_to_vector, 2410e2cb1decSSalil Mehta .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 2411e2cb1decSSalil Mehta .get_vector = hclgevf_get_vector, 24120d3e6631SYunsheng Lin .put_vector = hclgevf_put_vector, 2413e2cb1decSSalil Mehta .reset_queue = hclgevf_reset_tqp, 2414e2cb1decSSalil Mehta .set_promisc_mode = hclgevf_set_promisc_mode, 2415e2cb1decSSalil Mehta .get_mac_addr = hclgevf_get_mac_addr, 2416e2cb1decSSalil Mehta .set_mac_addr = hclgevf_set_mac_addr, 2417e2cb1decSSalil Mehta .add_uc_addr = hclgevf_add_uc_addr, 2418e2cb1decSSalil Mehta .rm_uc_addr = hclgevf_rm_uc_addr, 2419e2cb1decSSalil Mehta .add_mc_addr = hclgevf_add_mc_addr, 2420e2cb1decSSalil Mehta .rm_mc_addr = hclgevf_rm_mc_addr, 2421e2cb1decSSalil Mehta .get_stats = hclgevf_get_stats, 2422e2cb1decSSalil Mehta .update_stats = hclgevf_update_stats, 2423e2cb1decSSalil Mehta .get_strings = hclgevf_get_strings, 2424e2cb1decSSalil Mehta .get_sset_count = hclgevf_get_sset_count, 2425e2cb1decSSalil Mehta .get_rss_key_size = hclgevf_get_rss_key_size, 2426e2cb1decSSalil Mehta .get_rss_indir_size = hclgevf_get_rss_indir_size, 2427e2cb1decSSalil Mehta .get_rss = hclgevf_get_rss, 2428e2cb1decSSalil Mehta .set_rss = hclgevf_set_rss, 2429d97b3072SJian Shen .get_rss_tuple = hclgevf_get_rss_tuple, 2430d97b3072SJian Shen .set_rss_tuple = hclgevf_set_rss_tuple, 2431e2cb1decSSalil Mehta .get_tc_size = hclgevf_get_tc_size, 2432e2cb1decSSalil Mehta .get_fw_version = hclgevf_get_fw_version, 2433e2cb1decSSalil Mehta .set_vlan_filter = hclgevf_set_vlan_filter, 2434b2641e2aSYunsheng Lin .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 24356d4c3981SSalil Mehta .reset_event = hclgevf_reset_event, 2436720bd583SHuazhong Tan .set_default_reset_request = hclgevf_set_def_reset_request, 2437849e4607SPeng Li .get_channels = hclgevf_get_channels, 2438cc719218SPeng Li .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 2439175ec96bSFuyun Liang .get_status = hclgevf_get_status, 24404a152de9SFuyun Liang .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 2441c136b884SPeng Li .get_media_type = hclgevf_get_media_type, 24424d60291bSHuazhong Tan .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 24434d60291bSHuazhong Tan .ae_dev_resetting = hclgevf_ae_dev_resetting, 24444d60291bSHuazhong Tan .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 2445e2cb1decSSalil Mehta }; 2446e2cb1decSSalil Mehta 2447e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf = { 2448e2cb1decSSalil Mehta .ops = &hclgevf_ops, 2449e2cb1decSSalil Mehta .pdev_id_table = ae_algovf_pci_tbl, 2450e2cb1decSSalil Mehta }; 2451e2cb1decSSalil Mehta 2452e2cb1decSSalil Mehta static int hclgevf_init(void) 2453e2cb1decSSalil Mehta { 2454e2cb1decSSalil Mehta pr_info("%s is initializing\n", HCLGEVF_NAME); 2455e2cb1decSSalil Mehta 2456854cf33aSFuyun Liang hnae3_register_ae_algo(&ae_algovf); 2457854cf33aSFuyun Liang 2458854cf33aSFuyun Liang return 0; 2459e2cb1decSSalil Mehta } 2460e2cb1decSSalil Mehta 2461e2cb1decSSalil Mehta static void hclgevf_exit(void) 2462e2cb1decSSalil Mehta { 2463e2cb1decSSalil Mehta hnae3_unregister_ae_algo(&ae_algovf); 2464e2cb1decSSalil Mehta } 2465e2cb1decSSalil Mehta module_init(hclgevf_init); 2466e2cb1decSSalil Mehta module_exit(hclgevf_exit); 2467e2cb1decSSalil Mehta 2468e2cb1decSSalil Mehta MODULE_LICENSE("GPL"); 2469e2cb1decSSalil Mehta MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 2470e2cb1decSSalil Mehta MODULE_DESCRIPTION("HCLGEVF Driver"); 2471e2cb1decSSalil Mehta MODULE_VERSION(HCLGEVF_MOD_VERSION); 2472