1e2cb1decSSalil Mehta // SPDX-License-Identifier: GPL-2.0+ 2e2cb1decSSalil Mehta // Copyright (c) 2016-2017 Hisilicon Limited. 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #include <linux/etherdevice.h> 56988eb2aSSalil Mehta #include <net/rtnetlink.h> 6e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 7e2cb1decSSalil Mehta #include "hclgevf_main.h" 8e2cb1decSSalil Mehta #include "hclge_mbx.h" 9e2cb1decSSalil Mehta #include "hnae3.h" 10e2cb1decSSalil Mehta 11e2cb1decSSalil Mehta #define HCLGEVF_NAME "hclgevf" 12e2cb1decSSalil Mehta 137a01c897SSalil Mehta static int hclgevf_init_hdev(struct hclgevf_dev *hdev); 147a01c897SSalil Mehta static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev); 15e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf; 16e2cb1decSSalil Mehta 17e2cb1decSSalil Mehta static const struct pci_device_id ae_algovf_pci_tbl[] = { 18e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 19e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 20e2cb1decSSalil Mehta /* required last entry */ 21e2cb1decSSalil Mehta {0, } 22e2cb1decSSalil Mehta }; 23e2cb1decSSalil Mehta 242f550a46SYunsheng Lin MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 252f550a46SYunsheng Lin 26e2cb1decSSalil Mehta static inline struct hclgevf_dev *hclgevf_ae_get_hdev( 27e2cb1decSSalil Mehta struct hnae3_handle *handle) 28e2cb1decSSalil Mehta { 29e2cb1decSSalil Mehta return container_of(handle, struct hclgevf_dev, nic); 30e2cb1decSSalil Mehta } 31e2cb1decSSalil Mehta 32e2cb1decSSalil Mehta static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 33e2cb1decSSalil Mehta { 34e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 35e2cb1decSSalil Mehta struct hnae3_queue *queue; 36e2cb1decSSalil Mehta struct hclgevf_desc desc; 37e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 38e2cb1decSSalil Mehta int status; 39e2cb1decSSalil Mehta int i; 40e2cb1decSSalil Mehta 41e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 42e2cb1decSSalil Mehta queue = handle->kinfo.tqp[i]; 43e2cb1decSSalil Mehta tqp = container_of(queue, struct hclgevf_tqp, q); 44e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 45e2cb1decSSalil Mehta HCLGEVF_OPC_QUERY_RX_STATUS, 46e2cb1decSSalil Mehta true); 47e2cb1decSSalil Mehta 48e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 49e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 50e2cb1decSSalil Mehta if (status) { 51e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 52e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 53e2cb1decSSalil Mehta status, i); 54e2cb1decSSalil Mehta return status; 55e2cb1decSSalil Mehta } 56e2cb1decSSalil Mehta tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 57cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 58e2cb1decSSalil Mehta 59e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 60e2cb1decSSalil Mehta true); 61e2cb1decSSalil Mehta 62e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 63e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 64e2cb1decSSalil Mehta if (status) { 65e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 66e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 67e2cb1decSSalil Mehta status, i); 68e2cb1decSSalil Mehta return status; 69e2cb1decSSalil Mehta } 70e2cb1decSSalil Mehta tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 71cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 72e2cb1decSSalil Mehta } 73e2cb1decSSalil Mehta 74e2cb1decSSalil Mehta return 0; 75e2cb1decSSalil Mehta } 76e2cb1decSSalil Mehta 77e2cb1decSSalil Mehta static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 78e2cb1decSSalil Mehta { 79e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo = &handle->kinfo; 80e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 81e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 82e2cb1decSSalil Mehta u64 *buff = data; 83e2cb1decSSalil Mehta int i; 84e2cb1decSSalil Mehta 85e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 86e2cb1decSSalil Mehta tqp = container_of(handle->kinfo.tqp[i], struct hclgevf_tqp, q); 87e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 88e2cb1decSSalil Mehta } 89e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 90e2cb1decSSalil Mehta tqp = container_of(handle->kinfo.tqp[i], struct hclgevf_tqp, q); 91e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 92e2cb1decSSalil Mehta } 93e2cb1decSSalil Mehta 94e2cb1decSSalil Mehta return buff; 95e2cb1decSSalil Mehta } 96e2cb1decSSalil Mehta 97e2cb1decSSalil Mehta static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 98e2cb1decSSalil Mehta { 99e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 100e2cb1decSSalil Mehta 101e2cb1decSSalil Mehta return hdev->num_tqps * 2; 102e2cb1decSSalil Mehta } 103e2cb1decSSalil Mehta 104e2cb1decSSalil Mehta static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 105e2cb1decSSalil Mehta { 106e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 107e2cb1decSSalil Mehta u8 *buff = data; 108e2cb1decSSalil Mehta int i = 0; 109e2cb1decSSalil Mehta 110e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 111e2cb1decSSalil Mehta struct hclgevf_tqp *tqp = container_of(handle->kinfo.tqp[i], 112e2cb1decSSalil Mehta struct hclgevf_tqp, q); 113a6c51c26SJian Shen snprintf(buff, ETH_GSTRING_LEN, "txq#%d_pktnum_rcd", 114e2cb1decSSalil Mehta tqp->index); 115e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 116e2cb1decSSalil Mehta } 117e2cb1decSSalil Mehta 118e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 119e2cb1decSSalil Mehta struct hclgevf_tqp *tqp = container_of(handle->kinfo.tqp[i], 120e2cb1decSSalil Mehta struct hclgevf_tqp, q); 121a6c51c26SJian Shen snprintf(buff, ETH_GSTRING_LEN, "rxq#%d_pktnum_rcd", 122e2cb1decSSalil Mehta tqp->index); 123e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 124e2cb1decSSalil Mehta } 125e2cb1decSSalil Mehta 126e2cb1decSSalil Mehta return buff; 127e2cb1decSSalil Mehta } 128e2cb1decSSalil Mehta 129e2cb1decSSalil Mehta static void hclgevf_update_stats(struct hnae3_handle *handle, 130e2cb1decSSalil Mehta struct net_device_stats *net_stats) 131e2cb1decSSalil Mehta { 132e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 133e2cb1decSSalil Mehta int status; 134e2cb1decSSalil Mehta 135e2cb1decSSalil Mehta status = hclgevf_tqps_update_stats(handle); 136e2cb1decSSalil Mehta if (status) 137e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 138e2cb1decSSalil Mehta "VF update of TQPS stats fail, status = %d.\n", 139e2cb1decSSalil Mehta status); 140e2cb1decSSalil Mehta } 141e2cb1decSSalil Mehta 142e2cb1decSSalil Mehta static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 143e2cb1decSSalil Mehta { 144e2cb1decSSalil Mehta if (strset == ETH_SS_TEST) 145e2cb1decSSalil Mehta return -EOPNOTSUPP; 146e2cb1decSSalil Mehta else if (strset == ETH_SS_STATS) 147e2cb1decSSalil Mehta return hclgevf_tqps_get_sset_count(handle, strset); 148e2cb1decSSalil Mehta 149e2cb1decSSalil Mehta return 0; 150e2cb1decSSalil Mehta } 151e2cb1decSSalil Mehta 152e2cb1decSSalil Mehta static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 153e2cb1decSSalil Mehta u8 *data) 154e2cb1decSSalil Mehta { 155e2cb1decSSalil Mehta u8 *p = (char *)data; 156e2cb1decSSalil Mehta 157e2cb1decSSalil Mehta if (strset == ETH_SS_STATS) 158e2cb1decSSalil Mehta p = hclgevf_tqps_get_strings(handle, p); 159e2cb1decSSalil Mehta } 160e2cb1decSSalil Mehta 161e2cb1decSSalil Mehta static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 162e2cb1decSSalil Mehta { 163e2cb1decSSalil Mehta hclgevf_tqps_get_stats(handle, data); 164e2cb1decSSalil Mehta } 165e2cb1decSSalil Mehta 166e2cb1decSSalil Mehta static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 167e2cb1decSSalil Mehta { 168e2cb1decSSalil Mehta u8 resp_msg; 169e2cb1decSSalil Mehta int status; 170e2cb1decSSalil Mehta 171e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 172e2cb1decSSalil Mehta true, &resp_msg, sizeof(u8)); 173e2cb1decSSalil Mehta if (status) { 174e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 175e2cb1decSSalil Mehta "VF request to get TC info from PF failed %d", 176e2cb1decSSalil Mehta status); 177e2cb1decSSalil Mehta return status; 178e2cb1decSSalil Mehta } 179e2cb1decSSalil Mehta 180e2cb1decSSalil Mehta hdev->hw_tc_map = resp_msg; 181e2cb1decSSalil Mehta 182e2cb1decSSalil Mehta return 0; 183e2cb1decSSalil Mehta } 184e2cb1decSSalil Mehta 185e2cb1decSSalil Mehta static int hclge_get_queue_info(struct hclgevf_dev *hdev) 186e2cb1decSSalil Mehta { 187e2cb1decSSalil Mehta #define HCLGEVF_TQPS_RSS_INFO_LEN 8 188e2cb1decSSalil Mehta u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 189e2cb1decSSalil Mehta int status; 190e2cb1decSSalil Mehta 191e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 192e2cb1decSSalil Mehta true, resp_msg, 193e2cb1decSSalil Mehta HCLGEVF_TQPS_RSS_INFO_LEN); 194e2cb1decSSalil Mehta if (status) { 195e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 196e2cb1decSSalil Mehta "VF request to get tqp info from PF failed %d", 197e2cb1decSSalil Mehta status); 198e2cb1decSSalil Mehta return status; 199e2cb1decSSalil Mehta } 200e2cb1decSSalil Mehta 201e2cb1decSSalil Mehta memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 202e2cb1decSSalil Mehta memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 203e2cb1decSSalil Mehta memcpy(&hdev->num_desc, &resp_msg[4], sizeof(u16)); 204e2cb1decSSalil Mehta memcpy(&hdev->rx_buf_len, &resp_msg[6], sizeof(u16)); 205e2cb1decSSalil Mehta 206e2cb1decSSalil Mehta return 0; 207e2cb1decSSalil Mehta } 208e2cb1decSSalil Mehta 209e2cb1decSSalil Mehta static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 210e2cb1decSSalil Mehta { 211e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 212e2cb1decSSalil Mehta int i; 213e2cb1decSSalil Mehta 2147a01c897SSalil Mehta /* if this is on going reset then we need to re-allocate the TPQs 2157a01c897SSalil Mehta * since we cannot assume we would get same number of TPQs back from PF 2167a01c897SSalil Mehta */ 2177a01c897SSalil Mehta if (hclgevf_dev_ongoing_reset(hdev)) 2187a01c897SSalil Mehta devm_kfree(&hdev->pdev->dev, hdev->htqp); 2197a01c897SSalil Mehta 220e2cb1decSSalil Mehta hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 221e2cb1decSSalil Mehta sizeof(struct hclgevf_tqp), GFP_KERNEL); 222e2cb1decSSalil Mehta if (!hdev->htqp) 223e2cb1decSSalil Mehta return -ENOMEM; 224e2cb1decSSalil Mehta 225e2cb1decSSalil Mehta tqp = hdev->htqp; 226e2cb1decSSalil Mehta 227e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 228e2cb1decSSalil Mehta tqp->dev = &hdev->pdev->dev; 229e2cb1decSSalil Mehta tqp->index = i; 230e2cb1decSSalil Mehta 231e2cb1decSSalil Mehta tqp->q.ae_algo = &ae_algovf; 232e2cb1decSSalil Mehta tqp->q.buf_size = hdev->rx_buf_len; 233e2cb1decSSalil Mehta tqp->q.desc_num = hdev->num_desc; 234e2cb1decSSalil Mehta tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 235e2cb1decSSalil Mehta i * HCLGEVF_TQP_REG_SIZE; 236e2cb1decSSalil Mehta 237e2cb1decSSalil Mehta tqp++; 238e2cb1decSSalil Mehta } 239e2cb1decSSalil Mehta 240e2cb1decSSalil Mehta return 0; 241e2cb1decSSalil Mehta } 242e2cb1decSSalil Mehta 243e2cb1decSSalil Mehta static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 244e2cb1decSSalil Mehta { 245e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 246e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo; 247e2cb1decSSalil Mehta u16 new_tqps = hdev->num_tqps; 248e2cb1decSSalil Mehta int i; 249e2cb1decSSalil Mehta 250e2cb1decSSalil Mehta kinfo = &nic->kinfo; 251e2cb1decSSalil Mehta kinfo->num_tc = 0; 252e2cb1decSSalil Mehta kinfo->num_desc = hdev->num_desc; 253e2cb1decSSalil Mehta kinfo->rx_buf_len = hdev->rx_buf_len; 254e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 255e2cb1decSSalil Mehta if (hdev->hw_tc_map & BIT(i)) 256e2cb1decSSalil Mehta kinfo->num_tc++; 257e2cb1decSSalil Mehta 258e2cb1decSSalil Mehta kinfo->rss_size 259e2cb1decSSalil Mehta = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 260e2cb1decSSalil Mehta new_tqps = kinfo->rss_size * kinfo->num_tc; 261e2cb1decSSalil Mehta kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 262e2cb1decSSalil Mehta 2637a01c897SSalil Mehta /* if this is on going reset then we need to re-allocate the hnae queues 2647a01c897SSalil Mehta * as well since number of TPQs from PF might have changed. 2657a01c897SSalil Mehta */ 2667a01c897SSalil Mehta if (hclgevf_dev_ongoing_reset(hdev)) 2677a01c897SSalil Mehta devm_kfree(&hdev->pdev->dev, kinfo->tqp); 2687a01c897SSalil Mehta 269e2cb1decSSalil Mehta kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 270e2cb1decSSalil Mehta sizeof(struct hnae3_queue *), GFP_KERNEL); 271e2cb1decSSalil Mehta if (!kinfo->tqp) 272e2cb1decSSalil Mehta return -ENOMEM; 273e2cb1decSSalil Mehta 274e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 275e2cb1decSSalil Mehta hdev->htqp[i].q.handle = &hdev->nic; 276e2cb1decSSalil Mehta hdev->htqp[i].q.tqp_index = i; 277e2cb1decSSalil Mehta kinfo->tqp[i] = &hdev->htqp[i].q; 278e2cb1decSSalil Mehta } 279e2cb1decSSalil Mehta 280e2cb1decSSalil Mehta return 0; 281e2cb1decSSalil Mehta } 282e2cb1decSSalil Mehta 283e2cb1decSSalil Mehta static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 284e2cb1decSSalil Mehta { 285e2cb1decSSalil Mehta int status; 286e2cb1decSSalil Mehta u8 resp_msg; 287e2cb1decSSalil Mehta 288e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 289e2cb1decSSalil Mehta 0, false, &resp_msg, sizeof(u8)); 290e2cb1decSSalil Mehta if (status) 291e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 292e2cb1decSSalil Mehta "VF failed to fetch link status(%d) from PF", status); 293e2cb1decSSalil Mehta } 294e2cb1decSSalil Mehta 295e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 296e2cb1decSSalil Mehta { 297e2cb1decSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 298e2cb1decSSalil Mehta struct hnae3_client *client; 299e2cb1decSSalil Mehta 300e2cb1decSSalil Mehta client = handle->client; 301e2cb1decSSalil Mehta 302e2cb1decSSalil Mehta if (link_state != hdev->hw.mac.link) { 303e2cb1decSSalil Mehta client->ops->link_status_change(handle, !!link_state); 304e2cb1decSSalil Mehta hdev->hw.mac.link = link_state; 305e2cb1decSSalil Mehta } 306e2cb1decSSalil Mehta } 307e2cb1decSSalil Mehta 308e2cb1decSSalil Mehta static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 309e2cb1decSSalil Mehta { 310e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 311e2cb1decSSalil Mehta int ret; 312e2cb1decSSalil Mehta 313e2cb1decSSalil Mehta nic->ae_algo = &ae_algovf; 314e2cb1decSSalil Mehta nic->pdev = hdev->pdev; 315e2cb1decSSalil Mehta nic->numa_node_mask = hdev->numa_node_mask; 316424eb834SSalil Mehta nic->flags |= HNAE3_SUPPORT_VF; 317e2cb1decSSalil Mehta 318e2cb1decSSalil Mehta if (hdev->ae_dev->dev_type != HNAE3_DEV_KNIC) { 319e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "unsupported device type %d\n", 320e2cb1decSSalil Mehta hdev->ae_dev->dev_type); 321e2cb1decSSalil Mehta return -EINVAL; 322e2cb1decSSalil Mehta } 323e2cb1decSSalil Mehta 324e2cb1decSSalil Mehta ret = hclgevf_knic_setup(hdev); 325e2cb1decSSalil Mehta if (ret) 326e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 327e2cb1decSSalil Mehta ret); 328e2cb1decSSalil Mehta return ret; 329e2cb1decSSalil Mehta } 330e2cb1decSSalil Mehta 331e2cb1decSSalil Mehta static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 332e2cb1decSSalil Mehta { 333e2cb1decSSalil Mehta hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 334e2cb1decSSalil Mehta hdev->num_msi_left += 1; 335e2cb1decSSalil Mehta hdev->num_msi_used -= 1; 336e2cb1decSSalil Mehta } 337e2cb1decSSalil Mehta 338e2cb1decSSalil Mehta static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 339e2cb1decSSalil Mehta struct hnae3_vector_info *vector_info) 340e2cb1decSSalil Mehta { 341e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 342e2cb1decSSalil Mehta struct hnae3_vector_info *vector = vector_info; 343e2cb1decSSalil Mehta int alloc = 0; 344e2cb1decSSalil Mehta int i, j; 345e2cb1decSSalil Mehta 346e2cb1decSSalil Mehta vector_num = min(hdev->num_msi_left, vector_num); 347e2cb1decSSalil Mehta 348e2cb1decSSalil Mehta for (j = 0; j < vector_num; j++) { 349e2cb1decSSalil Mehta for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 350e2cb1decSSalil Mehta if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 351e2cb1decSSalil Mehta vector->vector = pci_irq_vector(hdev->pdev, i); 352e2cb1decSSalil Mehta vector->io_addr = hdev->hw.io_base + 353e2cb1decSSalil Mehta HCLGEVF_VECTOR_REG_BASE + 354e2cb1decSSalil Mehta (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 355e2cb1decSSalil Mehta hdev->vector_status[i] = 0; 356e2cb1decSSalil Mehta hdev->vector_irq[i] = vector->vector; 357e2cb1decSSalil Mehta 358e2cb1decSSalil Mehta vector++; 359e2cb1decSSalil Mehta alloc++; 360e2cb1decSSalil Mehta 361e2cb1decSSalil Mehta break; 362e2cb1decSSalil Mehta } 363e2cb1decSSalil Mehta } 364e2cb1decSSalil Mehta } 365e2cb1decSSalil Mehta hdev->num_msi_left -= alloc; 366e2cb1decSSalil Mehta hdev->num_msi_used += alloc; 367e2cb1decSSalil Mehta 368e2cb1decSSalil Mehta return alloc; 369e2cb1decSSalil Mehta } 370e2cb1decSSalil Mehta 371e2cb1decSSalil Mehta static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 372e2cb1decSSalil Mehta { 373e2cb1decSSalil Mehta int i; 374e2cb1decSSalil Mehta 375e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 376e2cb1decSSalil Mehta if (vector == hdev->vector_irq[i]) 377e2cb1decSSalil Mehta return i; 378e2cb1decSSalil Mehta 379e2cb1decSSalil Mehta return -EINVAL; 380e2cb1decSSalil Mehta } 381e2cb1decSSalil Mehta 382e2cb1decSSalil Mehta static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 383e2cb1decSSalil Mehta { 384e2cb1decSSalil Mehta return HCLGEVF_RSS_KEY_SIZE; 385e2cb1decSSalil Mehta } 386e2cb1decSSalil Mehta 387e2cb1decSSalil Mehta static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 388e2cb1decSSalil Mehta { 389e2cb1decSSalil Mehta return HCLGEVF_RSS_IND_TBL_SIZE; 390e2cb1decSSalil Mehta } 391e2cb1decSSalil Mehta 392e2cb1decSSalil Mehta static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 393e2cb1decSSalil Mehta { 394e2cb1decSSalil Mehta const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 395e2cb1decSSalil Mehta struct hclgevf_rss_indirection_table_cmd *req; 396e2cb1decSSalil Mehta struct hclgevf_desc desc; 397e2cb1decSSalil Mehta int status; 398e2cb1decSSalil Mehta int i, j; 399e2cb1decSSalil Mehta 400e2cb1decSSalil Mehta req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 401e2cb1decSSalil Mehta 402e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 403e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 404e2cb1decSSalil Mehta false); 405e2cb1decSSalil Mehta req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 406e2cb1decSSalil Mehta req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 407e2cb1decSSalil Mehta for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 408e2cb1decSSalil Mehta req->rss_result[j] = 409e2cb1decSSalil Mehta indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 410e2cb1decSSalil Mehta 411e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 412e2cb1decSSalil Mehta if (status) { 413e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 414e2cb1decSSalil Mehta "VF failed(=%d) to set RSS indirection table\n", 415e2cb1decSSalil Mehta status); 416e2cb1decSSalil Mehta return status; 417e2cb1decSSalil Mehta } 418e2cb1decSSalil Mehta } 419e2cb1decSSalil Mehta 420e2cb1decSSalil Mehta return 0; 421e2cb1decSSalil Mehta } 422e2cb1decSSalil Mehta 423e2cb1decSSalil Mehta static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 424e2cb1decSSalil Mehta { 425e2cb1decSSalil Mehta struct hclgevf_rss_tc_mode_cmd *req; 426e2cb1decSSalil Mehta u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 427e2cb1decSSalil Mehta u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 428e2cb1decSSalil Mehta u16 tc_size[HCLGEVF_MAX_TC_NUM]; 429e2cb1decSSalil Mehta struct hclgevf_desc desc; 430e2cb1decSSalil Mehta u16 roundup_size; 431e2cb1decSSalil Mehta int status; 432e2cb1decSSalil Mehta int i; 433e2cb1decSSalil Mehta 434e2cb1decSSalil Mehta req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 435e2cb1decSSalil Mehta 436e2cb1decSSalil Mehta roundup_size = roundup_pow_of_two(rss_size); 437e2cb1decSSalil Mehta roundup_size = ilog2(roundup_size); 438e2cb1decSSalil Mehta 439e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 440e2cb1decSSalil Mehta tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 441e2cb1decSSalil Mehta tc_size[i] = roundup_size; 442e2cb1decSSalil Mehta tc_offset[i] = rss_size * i; 443e2cb1decSSalil Mehta } 444e2cb1decSSalil Mehta 445e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 446e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 447e2cb1decSSalil Mehta hnae_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 448e2cb1decSSalil Mehta (tc_valid[i] & 0x1)); 449e2cb1decSSalil Mehta hnae_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 450e2cb1decSSalil Mehta HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 451e2cb1decSSalil Mehta hnae_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 452e2cb1decSSalil Mehta HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 453e2cb1decSSalil Mehta } 454e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 455e2cb1decSSalil Mehta if (status) 456e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 457e2cb1decSSalil Mehta "VF failed(=%d) to set rss tc mode\n", status); 458e2cb1decSSalil Mehta 459e2cb1decSSalil Mehta return status; 460e2cb1decSSalil Mehta } 461e2cb1decSSalil Mehta 462e2cb1decSSalil Mehta static int hclgevf_get_rss_hw_cfg(struct hnae3_handle *handle, u8 *hash, 463e2cb1decSSalil Mehta u8 *key) 464e2cb1decSSalil Mehta { 465e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 466e2cb1decSSalil Mehta struct hclgevf_rss_config_cmd *req; 467e2cb1decSSalil Mehta int lkup_times = key ? 3 : 1; 468e2cb1decSSalil Mehta struct hclgevf_desc desc; 469e2cb1decSSalil Mehta int key_offset; 470e2cb1decSSalil Mehta int key_size; 471e2cb1decSSalil Mehta int status; 472e2cb1decSSalil Mehta 473e2cb1decSSalil Mehta req = (struct hclgevf_rss_config_cmd *)desc.data; 474e2cb1decSSalil Mehta lkup_times = (lkup_times == 3) ? 3 : ((hash) ? 1 : 0); 475e2cb1decSSalil Mehta 476e2cb1decSSalil Mehta for (key_offset = 0; key_offset < lkup_times; key_offset++) { 477e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 478e2cb1decSSalil Mehta HCLGEVF_OPC_RSS_GENERIC_CONFIG, 479e2cb1decSSalil Mehta true); 480e2cb1decSSalil Mehta req->hash_config |= (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET); 481e2cb1decSSalil Mehta 482e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 483e2cb1decSSalil Mehta if (status) { 484e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 485e2cb1decSSalil Mehta "failed to get hardware RSS cfg, status = %d\n", 486e2cb1decSSalil Mehta status); 487e2cb1decSSalil Mehta return status; 488e2cb1decSSalil Mehta } 489e2cb1decSSalil Mehta 490e2cb1decSSalil Mehta if (key_offset == 2) 491e2cb1decSSalil Mehta key_size = 492e2cb1decSSalil Mehta HCLGEVF_RSS_KEY_SIZE - HCLGEVF_RSS_HASH_KEY_NUM * 2; 493e2cb1decSSalil Mehta else 494e2cb1decSSalil Mehta key_size = HCLGEVF_RSS_HASH_KEY_NUM; 495e2cb1decSSalil Mehta 496e2cb1decSSalil Mehta if (key) 497e2cb1decSSalil Mehta memcpy(key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, 498e2cb1decSSalil Mehta req->hash_key, 499e2cb1decSSalil Mehta key_size); 500e2cb1decSSalil Mehta } 501e2cb1decSSalil Mehta 502e2cb1decSSalil Mehta if (hash) { 503e2cb1decSSalil Mehta if ((req->hash_config & 0xf) == HCLGEVF_RSS_HASH_ALGO_TOEPLITZ) 504e2cb1decSSalil Mehta *hash = ETH_RSS_HASH_TOP; 505e2cb1decSSalil Mehta else 506e2cb1decSSalil Mehta *hash = ETH_RSS_HASH_UNKNOWN; 507e2cb1decSSalil Mehta } 508e2cb1decSSalil Mehta 509e2cb1decSSalil Mehta return 0; 510e2cb1decSSalil Mehta } 511e2cb1decSSalil Mehta 512e2cb1decSSalil Mehta static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 513e2cb1decSSalil Mehta u8 *hfunc) 514e2cb1decSSalil Mehta { 515e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 516e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 517e2cb1decSSalil Mehta int i; 518e2cb1decSSalil Mehta 519e2cb1decSSalil Mehta if (indir) 520e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 521e2cb1decSSalil Mehta indir[i] = rss_cfg->rss_indirection_tbl[i]; 522e2cb1decSSalil Mehta 523e2cb1decSSalil Mehta return hclgevf_get_rss_hw_cfg(handle, hfunc, key); 524e2cb1decSSalil Mehta } 525e2cb1decSSalil Mehta 526e2cb1decSSalil Mehta static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 527e2cb1decSSalil Mehta const u8 *key, const u8 hfunc) 528e2cb1decSSalil Mehta { 529e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 530e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 531e2cb1decSSalil Mehta int i; 532e2cb1decSSalil Mehta 533e2cb1decSSalil Mehta /* update the shadow RSS table with user specified qids */ 534e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 535e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = indir[i]; 536e2cb1decSSalil Mehta 537e2cb1decSSalil Mehta /* update the hardware */ 538e2cb1decSSalil Mehta return hclgevf_set_rss_indir_table(hdev); 539e2cb1decSSalil Mehta } 540e2cb1decSSalil Mehta 541e2cb1decSSalil Mehta static int hclgevf_get_tc_size(struct hnae3_handle *handle) 542e2cb1decSSalil Mehta { 543e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 544e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 545e2cb1decSSalil Mehta 546e2cb1decSSalil Mehta return rss_cfg->rss_size; 547e2cb1decSSalil Mehta } 548e2cb1decSSalil Mehta 549e2cb1decSSalil Mehta static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 550b204bc74SPeng Li int vector_id, 551e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 552e2cb1decSSalil Mehta { 553e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 554e2cb1decSSalil Mehta struct hnae3_ring_chain_node *node; 555e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 556e2cb1decSSalil Mehta struct hclgevf_desc desc; 557b204bc74SPeng Li int i = 0; 558e2cb1decSSalil Mehta int status; 559e2cb1decSSalil Mehta u8 type; 560e2cb1decSSalil Mehta 561e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 562e2cb1decSSalil Mehta 563e2cb1decSSalil Mehta for (node = ring_chain; node; node = node->next) { 5645d02a58dSYunsheng Lin int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 5655d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 5665d02a58dSYunsheng Lin 5675d02a58dSYunsheng Lin if (i == 0) { 5685d02a58dSYunsheng Lin hclgevf_cmd_setup_basic_desc(&desc, 5695d02a58dSYunsheng Lin HCLGEVF_OPC_MBX_VF_TO_PF, 5705d02a58dSYunsheng Lin false); 5715d02a58dSYunsheng Lin type = en ? 5725d02a58dSYunsheng Lin HCLGE_MBX_MAP_RING_TO_VECTOR : 5735d02a58dSYunsheng Lin HCLGE_MBX_UNMAP_RING_TO_VECTOR; 5745d02a58dSYunsheng Lin req->msg[0] = type; 5755d02a58dSYunsheng Lin req->msg[1] = vector_id; 5765d02a58dSYunsheng Lin } 5775d02a58dSYunsheng Lin 5785d02a58dSYunsheng Lin req->msg[idx_offset] = 579e2cb1decSSalil Mehta hnae_get_bit(node->flag, HNAE3_RING_TYPE_B); 5805d02a58dSYunsheng Lin req->msg[idx_offset + 1] = node->tqp_index; 5815d02a58dSYunsheng Lin req->msg[idx_offset + 2] = hnae_get_field(node->int_gl_idx, 58279eee410SFuyun Liang HNAE3_RING_GL_IDX_M, 58379eee410SFuyun Liang HNAE3_RING_GL_IDX_S); 58479eee410SFuyun Liang 5855d02a58dSYunsheng Lin i++; 5865d02a58dSYunsheng Lin if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 5875d02a58dSYunsheng Lin HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 5885d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 5895d02a58dSYunsheng Lin !node->next) { 590e2cb1decSSalil Mehta req->msg[2] = i; 591e2cb1decSSalil Mehta 592e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 593e2cb1decSSalil Mehta if (status) { 594e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 595e2cb1decSSalil Mehta "Map TQP fail, status is %d.\n", 596e2cb1decSSalil Mehta status); 597e2cb1decSSalil Mehta return status; 598e2cb1decSSalil Mehta } 599e2cb1decSSalil Mehta i = 0; 600e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 601e2cb1decSSalil Mehta HCLGEVF_OPC_MBX_VF_TO_PF, 602e2cb1decSSalil Mehta false); 603e2cb1decSSalil Mehta req->msg[0] = type; 604e2cb1decSSalil Mehta req->msg[1] = vector_id; 605e2cb1decSSalil Mehta } 606e2cb1decSSalil Mehta } 607e2cb1decSSalil Mehta 608e2cb1decSSalil Mehta return 0; 609e2cb1decSSalil Mehta } 610e2cb1decSSalil Mehta 611e2cb1decSSalil Mehta static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 612e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 613e2cb1decSSalil Mehta { 614b204bc74SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 615b204bc74SPeng Li int vector_id; 616b204bc74SPeng Li 617b204bc74SPeng Li vector_id = hclgevf_get_vector_index(hdev, vector); 618b204bc74SPeng Li if (vector_id < 0) { 619b204bc74SPeng Li dev_err(&handle->pdev->dev, 620b204bc74SPeng Li "Get vector index fail. ret =%d\n", vector_id); 621b204bc74SPeng Li return vector_id; 622b204bc74SPeng Li } 623b204bc74SPeng Li 624b204bc74SPeng Li return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 625e2cb1decSSalil Mehta } 626e2cb1decSSalil Mehta 627e2cb1decSSalil Mehta static int hclgevf_unmap_ring_from_vector( 628e2cb1decSSalil Mehta struct hnae3_handle *handle, 629e2cb1decSSalil Mehta int vector, 630e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 631e2cb1decSSalil Mehta { 632e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 633e2cb1decSSalil Mehta int ret, vector_id; 634e2cb1decSSalil Mehta 635e2cb1decSSalil Mehta vector_id = hclgevf_get_vector_index(hdev, vector); 636e2cb1decSSalil Mehta if (vector_id < 0) { 637e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 638e2cb1decSSalil Mehta "Get vector index fail. ret =%d\n", vector_id); 639e2cb1decSSalil Mehta return vector_id; 640e2cb1decSSalil Mehta } 641e2cb1decSSalil Mehta 642b204bc74SPeng Li ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 6430d3e6631SYunsheng Lin if (ret) 644e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 645e2cb1decSSalil Mehta "Unmap ring from vector fail. vector=%d, ret =%d\n", 646e2cb1decSSalil Mehta vector_id, 647e2cb1decSSalil Mehta ret); 6480d3e6631SYunsheng Lin 649e2cb1decSSalil Mehta return ret; 650e2cb1decSSalil Mehta } 651e2cb1decSSalil Mehta 6520d3e6631SYunsheng Lin static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 6530d3e6631SYunsheng Lin { 6540d3e6631SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 6550d3e6631SYunsheng Lin 656e2cb1decSSalil Mehta hclgevf_free_vector(hdev, vector); 657e2cb1decSSalil Mehta 658e2cb1decSSalil Mehta return 0; 659e2cb1decSSalil Mehta } 660e2cb1decSSalil Mehta 6613b75c3dfSPeng Li static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 6623b75c3dfSPeng Li bool en_uc_pmc, bool en_mc_pmc) 663e2cb1decSSalil Mehta { 664e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 665e2cb1decSSalil Mehta struct hclgevf_desc desc; 666e2cb1decSSalil Mehta int status; 667e2cb1decSSalil Mehta 668e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 669e2cb1decSSalil Mehta 670e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 671e2cb1decSSalil Mehta req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 6723b75c3dfSPeng Li req->msg[1] = en_uc_pmc ? 1 : 0; 6733b75c3dfSPeng Li req->msg[2] = en_mc_pmc ? 1 : 0; 674e2cb1decSSalil Mehta 675e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 676e2cb1decSSalil Mehta if (status) 677e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 678e2cb1decSSalil Mehta "Set promisc mode fail, status is %d.\n", status); 679e2cb1decSSalil Mehta 680e2cb1decSSalil Mehta return status; 681e2cb1decSSalil Mehta } 682e2cb1decSSalil Mehta 6833b75c3dfSPeng Li static void hclgevf_set_promisc_mode(struct hnae3_handle *handle, 6843b75c3dfSPeng Li bool en_uc_pmc, bool en_mc_pmc) 685e2cb1decSSalil Mehta { 686e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 687e2cb1decSSalil Mehta 6883b75c3dfSPeng Li hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc); 689e2cb1decSSalil Mehta } 690e2cb1decSSalil Mehta 691e2cb1decSSalil Mehta static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, int tqp_id, 692e2cb1decSSalil Mehta int stream_id, bool enable) 693e2cb1decSSalil Mehta { 694e2cb1decSSalil Mehta struct hclgevf_cfg_com_tqp_queue_cmd *req; 695e2cb1decSSalil Mehta struct hclgevf_desc desc; 696e2cb1decSSalil Mehta int status; 697e2cb1decSSalil Mehta 698e2cb1decSSalil Mehta req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 699e2cb1decSSalil Mehta 700e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 701e2cb1decSSalil Mehta false); 702e2cb1decSSalil Mehta req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 703e2cb1decSSalil Mehta req->stream_id = cpu_to_le16(stream_id); 704e2cb1decSSalil Mehta req->enable |= enable << HCLGEVF_TQP_ENABLE_B; 705e2cb1decSSalil Mehta 706e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 707e2cb1decSSalil Mehta if (status) 708e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 709e2cb1decSSalil Mehta "TQP enable fail, status =%d.\n", status); 710e2cb1decSSalil Mehta 711e2cb1decSSalil Mehta return status; 712e2cb1decSSalil Mehta } 713e2cb1decSSalil Mehta 714e2cb1decSSalil Mehta static int hclgevf_get_queue_id(struct hnae3_queue *queue) 715e2cb1decSSalil Mehta { 716e2cb1decSSalil Mehta struct hclgevf_tqp *tqp = container_of(queue, struct hclgevf_tqp, q); 717e2cb1decSSalil Mehta 718e2cb1decSSalil Mehta return tqp->index; 719e2cb1decSSalil Mehta } 720e2cb1decSSalil Mehta 721e2cb1decSSalil Mehta static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 722e2cb1decSSalil Mehta { 723e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 724e2cb1decSSalil Mehta struct hnae3_queue *queue; 725e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 726e2cb1decSSalil Mehta int i; 727e2cb1decSSalil Mehta 728e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 729e2cb1decSSalil Mehta queue = handle->kinfo.tqp[i]; 730e2cb1decSSalil Mehta tqp = container_of(queue, struct hclgevf_tqp, q); 731e2cb1decSSalil Mehta memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 732e2cb1decSSalil Mehta } 733e2cb1decSSalil Mehta } 734e2cb1decSSalil Mehta 7353a678b58SXi Wang static int hclgevf_cfg_func_mta_type(struct hclgevf_dev *hdev) 7363a678b58SXi Wang { 7373a678b58SXi Wang u8 resp_msg = HCLGEVF_MTA_TYPE_SEL_MAX; 7383a678b58SXi Wang int ret; 7393a678b58SXi Wang 7403a678b58SXi Wang ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 7413a678b58SXi Wang HCLGE_MBX_MAC_VLAN_MTA_TYPE_READ, 7423a678b58SXi Wang NULL, 0, true, &resp_msg, sizeof(u8)); 7433a678b58SXi Wang 7443a678b58SXi Wang if (ret) { 7453a678b58SXi Wang dev_err(&hdev->pdev->dev, 7463a678b58SXi Wang "Read mta type fail, ret=%d.\n", ret); 7473a678b58SXi Wang return ret; 7483a678b58SXi Wang } 7493a678b58SXi Wang 7503a678b58SXi Wang if (resp_msg > HCLGEVF_MTA_TYPE_SEL_MAX) { 7513a678b58SXi Wang dev_err(&hdev->pdev->dev, 7523a678b58SXi Wang "Read mta type invalid, resp=%d.\n", resp_msg); 7533a678b58SXi Wang return -EINVAL; 7543a678b58SXi Wang } 7553a678b58SXi Wang 7563a678b58SXi Wang hdev->mta_mac_sel_type = resp_msg; 7573a678b58SXi Wang 7583a678b58SXi Wang return 0; 7593a678b58SXi Wang } 7603a678b58SXi Wang 7613a678b58SXi Wang static u16 hclgevf_get_mac_addr_to_mta_index(struct hclgevf_dev *hdev, 7623a678b58SXi Wang const u8 *addr) 7633a678b58SXi Wang { 7643a678b58SXi Wang u32 rsh = HCLGEVF_MTA_TYPE_SEL_MAX - hdev->mta_mac_sel_type; 7653a678b58SXi Wang u16 high_val = addr[1] | (addr[0] << 8); 7663a678b58SXi Wang 7673a678b58SXi Wang return (high_val >> rsh) & 0xfff; 7683a678b58SXi Wang } 7693a678b58SXi Wang 7703a678b58SXi Wang static int hclgevf_do_update_mta_status(struct hclgevf_dev *hdev, 7713a678b58SXi Wang unsigned long *status) 7723a678b58SXi Wang { 7733a678b58SXi Wang #define HCLGEVF_MTA_STATUS_MSG_SIZE 13 7743a678b58SXi Wang #define HCLGEVF_MTA_STATUS_MSG_BITS \ 7753a678b58SXi Wang (HCLGEVF_MTA_STATUS_MSG_SIZE * BITS_PER_BYTE) 7763a678b58SXi Wang #define HCLGEVF_MTA_STATUS_MSG_END_BITS \ 7773a678b58SXi Wang (HCLGEVF_MTA_TBL_SIZE % HCLGEVF_MTA_STATUS_MSG_BITS) 7783a678b58SXi Wang u16 tbl_cnt; 7793a678b58SXi Wang u16 tbl_idx; 7803a678b58SXi Wang u8 msg_cnt; 7813a678b58SXi Wang u8 msg_idx; 7823a678b58SXi Wang int ret; 7833a678b58SXi Wang 7843a678b58SXi Wang msg_cnt = DIV_ROUND_UP(HCLGEVF_MTA_TBL_SIZE, 7853a678b58SXi Wang HCLGEVF_MTA_STATUS_MSG_BITS); 7863a678b58SXi Wang tbl_idx = 0; 7873a678b58SXi Wang msg_idx = 0; 7883a678b58SXi Wang while (msg_cnt--) { 7893a678b58SXi Wang u8 msg[HCLGEVF_MTA_STATUS_MSG_SIZE + 1]; 7903a678b58SXi Wang u8 *p = &msg[1]; 7913a678b58SXi Wang u8 msg_ofs; 7923a678b58SXi Wang u8 msg_bit; 7933a678b58SXi Wang 7943a678b58SXi Wang memset(msg, 0, sizeof(msg)); 7953a678b58SXi Wang 7963a678b58SXi Wang /* set index field */ 7973a678b58SXi Wang msg[0] = 0x7F & msg_idx; 7983a678b58SXi Wang 7993a678b58SXi Wang /* set end flag field */ 8003a678b58SXi Wang if (msg_cnt == 0) { 8013a678b58SXi Wang msg[0] |= 0x80; 8023a678b58SXi Wang tbl_cnt = HCLGEVF_MTA_STATUS_MSG_END_BITS; 8033a678b58SXi Wang } else { 8043a678b58SXi Wang tbl_cnt = HCLGEVF_MTA_STATUS_MSG_BITS; 8053a678b58SXi Wang } 8063a678b58SXi Wang 8073a678b58SXi Wang /* set status field */ 8083a678b58SXi Wang msg_ofs = 0; 8093a678b58SXi Wang msg_bit = 0; 8103a678b58SXi Wang while (tbl_cnt--) { 8113a678b58SXi Wang if (test_bit(tbl_idx, status)) 8123a678b58SXi Wang p[msg_ofs] |= BIT(msg_bit); 8133a678b58SXi Wang 8143a678b58SXi Wang tbl_idx++; 8153a678b58SXi Wang 8163a678b58SXi Wang msg_bit++; 8173a678b58SXi Wang if (msg_bit == BITS_PER_BYTE) { 8183a678b58SXi Wang msg_bit = 0; 8193a678b58SXi Wang msg_ofs++; 8203a678b58SXi Wang } 8213a678b58SXi Wang } 8223a678b58SXi Wang 8233a678b58SXi Wang ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 8243a678b58SXi Wang HCLGE_MBX_MAC_VLAN_MTA_STATUS_UPDATE, 8253a678b58SXi Wang msg, sizeof(msg), false, NULL, 0); 8263a678b58SXi Wang if (ret) 8273a678b58SXi Wang break; 8283a678b58SXi Wang 8293a678b58SXi Wang msg_idx++; 8303a678b58SXi Wang } 8313a678b58SXi Wang 8323a678b58SXi Wang return ret; 8333a678b58SXi Wang } 8343a678b58SXi Wang 8353a678b58SXi Wang static int hclgevf_update_mta_status(struct hnae3_handle *handle) 8363a678b58SXi Wang { 8373a678b58SXi Wang unsigned long mta_status[BITS_TO_LONGS(HCLGEVF_MTA_TBL_SIZE)]; 8383a678b58SXi Wang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 8393a678b58SXi Wang struct net_device *netdev = hdev->nic.kinfo.netdev; 8403a678b58SXi Wang struct netdev_hw_addr *ha; 8413a678b58SXi Wang u16 tbl_idx; 8423a678b58SXi Wang 8433a678b58SXi Wang /* clear status */ 8443a678b58SXi Wang memset(mta_status, 0, sizeof(mta_status)); 8453a678b58SXi Wang 8463a678b58SXi Wang /* update status from mc addr list */ 8473a678b58SXi Wang netdev_for_each_mc_addr(ha, netdev) { 8483a678b58SXi Wang tbl_idx = hclgevf_get_mac_addr_to_mta_index(hdev, ha->addr); 8493a678b58SXi Wang set_bit(tbl_idx, mta_status); 8503a678b58SXi Wang } 8513a678b58SXi Wang 8523a678b58SXi Wang return hclgevf_do_update_mta_status(hdev, mta_status); 8533a678b58SXi Wang } 8543a678b58SXi Wang 855e2cb1decSSalil Mehta static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 856e2cb1decSSalil Mehta { 857e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 858e2cb1decSSalil Mehta 859e2cb1decSSalil Mehta ether_addr_copy(p, hdev->hw.mac.mac_addr); 860e2cb1decSSalil Mehta } 861e2cb1decSSalil Mehta 86259098055SFuyun Liang static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 86359098055SFuyun Liang bool is_first) 864e2cb1decSSalil Mehta { 865e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 866e2cb1decSSalil Mehta u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 867e2cb1decSSalil Mehta u8 *new_mac_addr = (u8 *)p; 868e2cb1decSSalil Mehta u8 msg_data[ETH_ALEN * 2]; 86959098055SFuyun Liang u16 subcode; 870e2cb1decSSalil Mehta int status; 871e2cb1decSSalil Mehta 872e2cb1decSSalil Mehta ether_addr_copy(msg_data, new_mac_addr); 873e2cb1decSSalil Mehta ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 874e2cb1decSSalil Mehta 87559098055SFuyun Liang subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 87659098055SFuyun Liang HCLGE_MBX_MAC_VLAN_UC_MODIFY; 87759098055SFuyun Liang 878e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 87959098055SFuyun Liang subcode, msg_data, ETH_ALEN * 2, 8802097fdefSJian Shen true, NULL, 0); 881e2cb1decSSalil Mehta if (!status) 882e2cb1decSSalil Mehta ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 883e2cb1decSSalil Mehta 884e2cb1decSSalil Mehta return status; 885e2cb1decSSalil Mehta } 886e2cb1decSSalil Mehta 887e2cb1decSSalil Mehta static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 888e2cb1decSSalil Mehta const unsigned char *addr) 889e2cb1decSSalil Mehta { 890e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 891e2cb1decSSalil Mehta 892e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 893e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_ADD, 894e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 895e2cb1decSSalil Mehta } 896e2cb1decSSalil Mehta 897e2cb1decSSalil Mehta static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 898e2cb1decSSalil Mehta const unsigned char *addr) 899e2cb1decSSalil Mehta { 900e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 901e2cb1decSSalil Mehta 902e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 903e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_REMOVE, 904e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 905e2cb1decSSalil Mehta } 906e2cb1decSSalil Mehta 907e2cb1decSSalil Mehta static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 908e2cb1decSSalil Mehta const unsigned char *addr) 909e2cb1decSSalil Mehta { 910e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 911e2cb1decSSalil Mehta 912e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 913e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_ADD, 914e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 915e2cb1decSSalil Mehta } 916e2cb1decSSalil Mehta 917e2cb1decSSalil Mehta static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 918e2cb1decSSalil Mehta const unsigned char *addr) 919e2cb1decSSalil Mehta { 920e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 921e2cb1decSSalil Mehta 922e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 923e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_REMOVE, 924e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 925e2cb1decSSalil Mehta } 926e2cb1decSSalil Mehta 927e2cb1decSSalil Mehta static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 928e2cb1decSSalil Mehta __be16 proto, u16 vlan_id, 929e2cb1decSSalil Mehta bool is_kill) 930e2cb1decSSalil Mehta { 931e2cb1decSSalil Mehta #define HCLGEVF_VLAN_MBX_MSG_LEN 5 932e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 933e2cb1decSSalil Mehta u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 934e2cb1decSSalil Mehta 935e2cb1decSSalil Mehta if (vlan_id > 4095) 936e2cb1decSSalil Mehta return -EINVAL; 937e2cb1decSSalil Mehta 938e2cb1decSSalil Mehta if (proto != htons(ETH_P_8021Q)) 939e2cb1decSSalil Mehta return -EPROTONOSUPPORT; 940e2cb1decSSalil Mehta 941e2cb1decSSalil Mehta msg_data[0] = is_kill; 942e2cb1decSSalil Mehta memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 943e2cb1decSSalil Mehta memcpy(&msg_data[3], &proto, sizeof(proto)); 944e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 945e2cb1decSSalil Mehta HCLGE_MBX_VLAN_FILTER, msg_data, 946e2cb1decSSalil Mehta HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 947e2cb1decSSalil Mehta } 948e2cb1decSSalil Mehta 949b2641e2aSYunsheng Lin static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 950b2641e2aSYunsheng Lin { 951b2641e2aSYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 952b2641e2aSYunsheng Lin u8 msg_data; 953b2641e2aSYunsheng Lin 954b2641e2aSYunsheng Lin msg_data = enable ? 1 : 0; 955b2641e2aSYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 956b2641e2aSYunsheng Lin HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 957b2641e2aSYunsheng Lin 1, false, NULL, 0); 958b2641e2aSYunsheng Lin } 959b2641e2aSYunsheng Lin 960e2cb1decSSalil Mehta static void hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 961e2cb1decSSalil Mehta { 962e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 963e2cb1decSSalil Mehta u8 msg_data[2]; 9641a426f8bSPeng Li int ret; 965e2cb1decSSalil Mehta 966e2cb1decSSalil Mehta memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 967e2cb1decSSalil Mehta 9681a426f8bSPeng Li /* disable vf queue before send queue reset msg to PF */ 9691a426f8bSPeng Li ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 9701a426f8bSPeng Li if (ret) 9711a426f8bSPeng Li return; 9721a426f8bSPeng Li 9731a426f8bSPeng Li hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 9741a426f8bSPeng Li 2, true, NULL, 0); 975e2cb1decSSalil Mehta } 976e2cb1decSSalil Mehta 9776988eb2aSSalil Mehta static int hclgevf_notify_client(struct hclgevf_dev *hdev, 9786988eb2aSSalil Mehta enum hnae3_reset_notify_type type) 9796988eb2aSSalil Mehta { 9806988eb2aSSalil Mehta struct hnae3_client *client = hdev->nic_client; 9816988eb2aSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 9826988eb2aSSalil Mehta 9836988eb2aSSalil Mehta if (!client->ops->reset_notify) 9846988eb2aSSalil Mehta return -EOPNOTSUPP; 9856988eb2aSSalil Mehta 9866988eb2aSSalil Mehta return client->ops->reset_notify(handle, type); 9876988eb2aSSalil Mehta } 9886988eb2aSSalil Mehta 9896988eb2aSSalil Mehta static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 9906988eb2aSSalil Mehta { 9916988eb2aSSalil Mehta #define HCLGEVF_RESET_WAIT_MS 500 9926988eb2aSSalil Mehta #define HCLGEVF_RESET_WAIT_CNT 20 9936988eb2aSSalil Mehta u32 val, cnt = 0; 9946988eb2aSSalil Mehta 9956988eb2aSSalil Mehta /* wait to check the hardware reset completion status */ 9966988eb2aSSalil Mehta val = hclgevf_read_dev(&hdev->hw, HCLGEVF_FUN_RST_ING); 9976988eb2aSSalil Mehta while (hnae_get_bit(val, HCLGEVF_FUN_RST_ING_B) && 9986988eb2aSSalil Mehta (cnt < HCLGEVF_RESET_WAIT_CNT)) { 9996988eb2aSSalil Mehta msleep(HCLGEVF_RESET_WAIT_MS); 10006988eb2aSSalil Mehta val = hclgevf_read_dev(&hdev->hw, HCLGEVF_FUN_RST_ING); 10016988eb2aSSalil Mehta cnt++; 10026988eb2aSSalil Mehta } 10036988eb2aSSalil Mehta 10046988eb2aSSalil Mehta /* hardware completion status should be available by this time */ 10056988eb2aSSalil Mehta if (cnt >= HCLGEVF_RESET_WAIT_CNT) { 10066988eb2aSSalil Mehta dev_warn(&hdev->pdev->dev, 10076988eb2aSSalil Mehta "could'nt get reset done status from h/w, timeout!\n"); 10086988eb2aSSalil Mehta return -EBUSY; 10096988eb2aSSalil Mehta } 10106988eb2aSSalil Mehta 10116988eb2aSSalil Mehta /* we will wait a bit more to let reset of the stack to complete. This 10126988eb2aSSalil Mehta * might happen in case reset assertion was made by PF. Yes, this also 10136988eb2aSSalil Mehta * means we might end up waiting bit more even for VF reset. 10146988eb2aSSalil Mehta */ 10156988eb2aSSalil Mehta msleep(5000); 10166988eb2aSSalil Mehta 10176988eb2aSSalil Mehta return 0; 10186988eb2aSSalil Mehta } 10196988eb2aSSalil Mehta 10206988eb2aSSalil Mehta static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 10216988eb2aSSalil Mehta { 10227a01c897SSalil Mehta int ret; 10237a01c897SSalil Mehta 10246988eb2aSSalil Mehta /* uninitialize the nic client */ 10256988eb2aSSalil Mehta hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 10266988eb2aSSalil Mehta 10277a01c897SSalil Mehta /* re-initialize the hclge device */ 10287a01c897SSalil Mehta ret = hclgevf_init_hdev(hdev); 10297a01c897SSalil Mehta if (ret) { 10307a01c897SSalil Mehta dev_err(&hdev->pdev->dev, 10317a01c897SSalil Mehta "hclge device re-init failed, VF is disabled!\n"); 10327a01c897SSalil Mehta return ret; 10337a01c897SSalil Mehta } 10346988eb2aSSalil Mehta 10356988eb2aSSalil Mehta /* bring up the nic client again */ 10366988eb2aSSalil Mehta hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 10376988eb2aSSalil Mehta 10386988eb2aSSalil Mehta return 0; 10396988eb2aSSalil Mehta } 10406988eb2aSSalil Mehta 10416988eb2aSSalil Mehta static int hclgevf_reset(struct hclgevf_dev *hdev) 10426988eb2aSSalil Mehta { 10436988eb2aSSalil Mehta int ret; 10446988eb2aSSalil Mehta 10456988eb2aSSalil Mehta rtnl_lock(); 10466988eb2aSSalil Mehta 10476988eb2aSSalil Mehta /* bring down the nic to stop any ongoing TX/RX */ 10486988eb2aSSalil Mehta hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 10496988eb2aSSalil Mehta 10506988eb2aSSalil Mehta /* check if VF could successfully fetch the hardware reset completion 10516988eb2aSSalil Mehta * status from the hardware 10526988eb2aSSalil Mehta */ 10536988eb2aSSalil Mehta ret = hclgevf_reset_wait(hdev); 10546988eb2aSSalil Mehta if (ret) { 10556988eb2aSSalil Mehta /* can't do much in this situation, will disable VF */ 10566988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, 10576988eb2aSSalil Mehta "VF failed(=%d) to fetch H/W reset completion status\n", 10586988eb2aSSalil Mehta ret); 10596988eb2aSSalil Mehta 10606988eb2aSSalil Mehta dev_warn(&hdev->pdev->dev, "VF reset failed, disabling VF!\n"); 10616988eb2aSSalil Mehta hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 10626988eb2aSSalil Mehta 10636988eb2aSSalil Mehta rtnl_unlock(); 10646988eb2aSSalil Mehta return ret; 10656988eb2aSSalil Mehta } 10666988eb2aSSalil Mehta 10676988eb2aSSalil Mehta /* now, re-initialize the nic client and ae device*/ 10686988eb2aSSalil Mehta ret = hclgevf_reset_stack(hdev); 10696988eb2aSSalil Mehta if (ret) 10706988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 10716988eb2aSSalil Mehta 10726988eb2aSSalil Mehta /* bring up the nic to enable TX/RX again */ 10736988eb2aSSalil Mehta hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 10746988eb2aSSalil Mehta 10756988eb2aSSalil Mehta rtnl_unlock(); 10766988eb2aSSalil Mehta 10776988eb2aSSalil Mehta return ret; 10786988eb2aSSalil Mehta } 10796988eb2aSSalil Mehta 1080a8dedb65SSalil Mehta static int hclgevf_do_reset(struct hclgevf_dev *hdev) 1081a8dedb65SSalil Mehta { 1082a8dedb65SSalil Mehta int status; 1083a8dedb65SSalil Mehta u8 respmsg; 1084a8dedb65SSalil Mehta 1085a8dedb65SSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1086a8dedb65SSalil Mehta 0, false, &respmsg, sizeof(u8)); 1087a8dedb65SSalil Mehta if (status) 1088a8dedb65SSalil Mehta dev_err(&hdev->pdev->dev, 1089a8dedb65SSalil Mehta "VF reset request to PF failed(=%d)\n", status); 1090a8dedb65SSalil Mehta 1091a8dedb65SSalil Mehta return status; 1092a8dedb65SSalil Mehta } 1093a8dedb65SSalil Mehta 10946d4c3981SSalil Mehta static void hclgevf_reset_event(struct hnae3_handle *handle) 10956d4c3981SSalil Mehta { 10966d4c3981SSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 10976d4c3981SSalil Mehta 10986d4c3981SSalil Mehta dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 10996d4c3981SSalil Mehta 11006d4c3981SSalil Mehta handle->reset_level = HNAE3_VF_RESET; 11016d4c3981SSalil Mehta 1102436667d2SSalil Mehta /* reset of this VF requested */ 1103436667d2SSalil Mehta set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1104436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 11056d4c3981SSalil Mehta 11066d4c3981SSalil Mehta handle->last_reset_time = jiffies; 11076d4c3981SSalil Mehta } 11086d4c3981SSalil Mehta 1109e2cb1decSSalil Mehta static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1110e2cb1decSSalil Mehta { 1111e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1112e2cb1decSSalil Mehta 1113e2cb1decSSalil Mehta return hdev->fw_version; 1114e2cb1decSSalil Mehta } 1115e2cb1decSSalil Mehta 1116e2cb1decSSalil Mehta static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1117e2cb1decSSalil Mehta { 1118e2cb1decSSalil Mehta struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1119e2cb1decSSalil Mehta 1120e2cb1decSSalil Mehta vector->vector_irq = pci_irq_vector(hdev->pdev, 1121e2cb1decSSalil Mehta HCLGEVF_MISC_VECTOR_NUM); 1122e2cb1decSSalil Mehta vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1123e2cb1decSSalil Mehta /* vector status always valid for Vector 0 */ 1124e2cb1decSSalil Mehta hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1125e2cb1decSSalil Mehta hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1126e2cb1decSSalil Mehta 1127e2cb1decSSalil Mehta hdev->num_msi_left -= 1; 1128e2cb1decSSalil Mehta hdev->num_msi_used += 1; 1129e2cb1decSSalil Mehta } 1130e2cb1decSSalil Mehta 113135a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 113235a1e503SSalil Mehta { 113335a1e503SSalil Mehta if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) && 113435a1e503SSalil Mehta !test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) { 113535a1e503SSalil Mehta set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 113635a1e503SSalil Mehta schedule_work(&hdev->rst_service_task); 113735a1e503SSalil Mehta } 113835a1e503SSalil Mehta } 113935a1e503SSalil Mehta 114007a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1141e2cb1decSSalil Mehta { 114207a0556aSSalil Mehta if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) && 114307a0556aSSalil Mehta !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) { 114407a0556aSSalil Mehta set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1145e2cb1decSSalil Mehta schedule_work(&hdev->mbx_service_task); 1146e2cb1decSSalil Mehta } 114707a0556aSSalil Mehta } 1148e2cb1decSSalil Mehta 1149e2cb1decSSalil Mehta static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 1150e2cb1decSSalil Mehta { 1151e2cb1decSSalil Mehta if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 1152e2cb1decSSalil Mehta !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 1153e2cb1decSSalil Mehta schedule_work(&hdev->service_task); 1154e2cb1decSSalil Mehta } 1155e2cb1decSSalil Mehta 1156436667d2SSalil Mehta static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev) 1157436667d2SSalil Mehta { 115807a0556aSSalil Mehta /* if we have any pending mailbox event then schedule the mbx task */ 115907a0556aSSalil Mehta if (hdev->mbx_event_pending) 116007a0556aSSalil Mehta hclgevf_mbx_task_schedule(hdev); 116107a0556aSSalil Mehta 1162436667d2SSalil Mehta if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state)) 1163436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 1164436667d2SSalil Mehta } 1165436667d2SSalil Mehta 1166e2cb1decSSalil Mehta static void hclgevf_service_timer(struct timer_list *t) 1167e2cb1decSSalil Mehta { 1168e2cb1decSSalil Mehta struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 1169e2cb1decSSalil Mehta 1170e2cb1decSSalil Mehta mod_timer(&hdev->service_timer, jiffies + 5 * HZ); 1171e2cb1decSSalil Mehta 1172e2cb1decSSalil Mehta hclgevf_task_schedule(hdev); 1173e2cb1decSSalil Mehta } 1174e2cb1decSSalil Mehta 117535a1e503SSalil Mehta static void hclgevf_reset_service_task(struct work_struct *work) 117635a1e503SSalil Mehta { 117735a1e503SSalil Mehta struct hclgevf_dev *hdev = 117835a1e503SSalil Mehta container_of(work, struct hclgevf_dev, rst_service_task); 1179a8dedb65SSalil Mehta int ret; 118035a1e503SSalil Mehta 118135a1e503SSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 118235a1e503SSalil Mehta return; 118335a1e503SSalil Mehta 118435a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 118535a1e503SSalil Mehta 1186436667d2SSalil Mehta if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1187436667d2SSalil Mehta &hdev->reset_state)) { 1188436667d2SSalil Mehta /* PF has initmated that it is about to reset the hardware. 1189436667d2SSalil Mehta * We now have to poll & check if harware has actually completed 1190436667d2SSalil Mehta * the reset sequence. On hardware reset completion, VF needs to 1191436667d2SSalil Mehta * reset the client and ae device. 119235a1e503SSalil Mehta */ 1193436667d2SSalil Mehta hdev->reset_attempts = 0; 1194436667d2SSalil Mehta 11956988eb2aSSalil Mehta ret = hclgevf_reset(hdev); 11966988eb2aSSalil Mehta if (ret) 11976988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, "VF stack reset failed.\n"); 1198436667d2SSalil Mehta } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1199436667d2SSalil Mehta &hdev->reset_state)) { 1200436667d2SSalil Mehta /* we could be here when either of below happens: 1201436667d2SSalil Mehta * 1. reset was initiated due to watchdog timeout due to 1202436667d2SSalil Mehta * a. IMP was earlier reset and our TX got choked down and 1203436667d2SSalil Mehta * which resulted in watchdog reacting and inducing VF 1204436667d2SSalil Mehta * reset. This also means our cmdq would be unreliable. 1205436667d2SSalil Mehta * b. problem in TX due to other lower layer(example link 1206436667d2SSalil Mehta * layer not functioning properly etc.) 1207436667d2SSalil Mehta * 2. VF reset might have been initiated due to some config 1208436667d2SSalil Mehta * change. 1209436667d2SSalil Mehta * 1210436667d2SSalil Mehta * NOTE: Theres no clear way to detect above cases than to react 1211436667d2SSalil Mehta * to the response of PF for this reset request. PF will ack the 1212436667d2SSalil Mehta * 1b and 2. cases but we will not get any intimation about 1a 1213436667d2SSalil Mehta * from PF as cmdq would be in unreliable state i.e. mailbox 1214436667d2SSalil Mehta * communication between PF and VF would be broken. 1215436667d2SSalil Mehta */ 1216436667d2SSalil Mehta 1217436667d2SSalil Mehta /* if we are never geting into pending state it means either: 1218436667d2SSalil Mehta * 1. PF is not receiving our request which could be due to IMP 1219436667d2SSalil Mehta * reset 1220436667d2SSalil Mehta * 2. PF is screwed 1221436667d2SSalil Mehta * We cannot do much for 2. but to check first we can try reset 1222436667d2SSalil Mehta * our PCIe + stack and see if it alleviates the problem. 1223436667d2SSalil Mehta */ 1224436667d2SSalil Mehta if (hdev->reset_attempts > 3) { 1225436667d2SSalil Mehta /* prepare for full reset of stack + pcie interface */ 1226436667d2SSalil Mehta hdev->nic.reset_level = HNAE3_VF_FULL_RESET; 1227436667d2SSalil Mehta 1228436667d2SSalil Mehta /* "defer" schedule the reset task again */ 1229436667d2SSalil Mehta set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1230436667d2SSalil Mehta } else { 1231436667d2SSalil Mehta hdev->reset_attempts++; 1232436667d2SSalil Mehta 1233436667d2SSalil Mehta /* request PF for resetting this VF via mailbox */ 1234a8dedb65SSalil Mehta ret = hclgevf_do_reset(hdev); 1235a8dedb65SSalil Mehta if (ret) 1236a8dedb65SSalil Mehta dev_warn(&hdev->pdev->dev, 1237a8dedb65SSalil Mehta "VF rst fail, stack will call\n"); 1238436667d2SSalil Mehta } 1239436667d2SSalil Mehta } 124035a1e503SSalil Mehta 124135a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 124235a1e503SSalil Mehta } 124335a1e503SSalil Mehta 1244e2cb1decSSalil Mehta static void hclgevf_mailbox_service_task(struct work_struct *work) 1245e2cb1decSSalil Mehta { 1246e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1247e2cb1decSSalil Mehta 1248e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 1249e2cb1decSSalil Mehta 1250e2cb1decSSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1251e2cb1decSSalil Mehta return; 1252e2cb1decSSalil Mehta 1253e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1254e2cb1decSSalil Mehta 125507a0556aSSalil Mehta hclgevf_mbx_async_handler(hdev); 1256e2cb1decSSalil Mehta 1257e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1258e2cb1decSSalil Mehta } 1259e2cb1decSSalil Mehta 1260e2cb1decSSalil Mehta static void hclgevf_service_task(struct work_struct *work) 1261e2cb1decSSalil Mehta { 1262e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1263e2cb1decSSalil Mehta 1264e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, service_task); 1265e2cb1decSSalil Mehta 1266e2cb1decSSalil Mehta /* request the link status from the PF. PF would be able to tell VF 1267e2cb1decSSalil Mehta * about such updates in future so we might remove this later 1268e2cb1decSSalil Mehta */ 1269e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1270e2cb1decSSalil Mehta 1271436667d2SSalil Mehta hclgevf_deferred_task_schedule(hdev); 1272436667d2SSalil Mehta 1273e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1274e2cb1decSSalil Mehta } 1275e2cb1decSSalil Mehta 1276e2cb1decSSalil Mehta static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1277e2cb1decSSalil Mehta { 1278e2cb1decSSalil Mehta hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1279e2cb1decSSalil Mehta } 1280e2cb1decSSalil Mehta 1281e2cb1decSSalil Mehta static bool hclgevf_check_event_cause(struct hclgevf_dev *hdev, u32 *clearval) 1282e2cb1decSSalil Mehta { 1283e2cb1decSSalil Mehta u32 cmdq_src_reg; 1284e2cb1decSSalil Mehta 1285e2cb1decSSalil Mehta /* fetch the events from their corresponding regs */ 1286e2cb1decSSalil Mehta cmdq_src_reg = hclgevf_read_dev(&hdev->hw, 1287e2cb1decSSalil Mehta HCLGEVF_VECTOR0_CMDQ_SRC_REG); 1288e2cb1decSSalil Mehta 1289e2cb1decSSalil Mehta /* check for vector0 mailbox(=CMDQ RX) event source */ 1290e2cb1decSSalil Mehta if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 1291e2cb1decSSalil Mehta cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1292e2cb1decSSalil Mehta *clearval = cmdq_src_reg; 1293e2cb1decSSalil Mehta return true; 1294e2cb1decSSalil Mehta } 1295e2cb1decSSalil Mehta 1296e2cb1decSSalil Mehta dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 1297e2cb1decSSalil Mehta 1298e2cb1decSSalil Mehta return false; 1299e2cb1decSSalil Mehta } 1300e2cb1decSSalil Mehta 1301e2cb1decSSalil Mehta static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1302e2cb1decSSalil Mehta { 1303e2cb1decSSalil Mehta writel(en ? 1 : 0, vector->addr); 1304e2cb1decSSalil Mehta } 1305e2cb1decSSalil Mehta 1306e2cb1decSSalil Mehta static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1307e2cb1decSSalil Mehta { 1308e2cb1decSSalil Mehta struct hclgevf_dev *hdev = data; 1309e2cb1decSSalil Mehta u32 clearval; 1310e2cb1decSSalil Mehta 1311e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 1312e2cb1decSSalil Mehta if (!hclgevf_check_event_cause(hdev, &clearval)) 1313e2cb1decSSalil Mehta goto skip_sched; 1314e2cb1decSSalil Mehta 131507a0556aSSalil Mehta hclgevf_mbx_handler(hdev); 1316e2cb1decSSalil Mehta 1317e2cb1decSSalil Mehta hclgevf_clear_event_cause(hdev, clearval); 1318e2cb1decSSalil Mehta 1319e2cb1decSSalil Mehta skip_sched: 1320e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 1321e2cb1decSSalil Mehta 1322e2cb1decSSalil Mehta return IRQ_HANDLED; 1323e2cb1decSSalil Mehta } 1324e2cb1decSSalil Mehta 1325e2cb1decSSalil Mehta static int hclgevf_configure(struct hclgevf_dev *hdev) 1326e2cb1decSSalil Mehta { 1327e2cb1decSSalil Mehta int ret; 1328e2cb1decSSalil Mehta 1329e2cb1decSSalil Mehta /* get queue configuration from PF */ 1330e2cb1decSSalil Mehta ret = hclge_get_queue_info(hdev); 1331e2cb1decSSalil Mehta if (ret) 1332e2cb1decSSalil Mehta return ret; 1333e2cb1decSSalil Mehta /* get tc configuration from PF */ 1334e2cb1decSSalil Mehta return hclgevf_get_tc_info(hdev); 1335e2cb1decSSalil Mehta } 1336e2cb1decSSalil Mehta 13377a01c897SSalil Mehta static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 13387a01c897SSalil Mehta { 13397a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 13407a01c897SSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 13417a01c897SSalil Mehta 13427a01c897SSalil Mehta hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 13437a01c897SSalil Mehta if (!hdev) 13447a01c897SSalil Mehta return -ENOMEM; 13457a01c897SSalil Mehta 13467a01c897SSalil Mehta hdev->pdev = pdev; 13477a01c897SSalil Mehta hdev->ae_dev = ae_dev; 13487a01c897SSalil Mehta ae_dev->priv = hdev; 13497a01c897SSalil Mehta 13507a01c897SSalil Mehta return 0; 13517a01c897SSalil Mehta } 13527a01c897SSalil Mehta 1353e2cb1decSSalil Mehta static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 1354e2cb1decSSalil Mehta { 1355e2cb1decSSalil Mehta struct hnae3_handle *roce = &hdev->roce; 1356e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 1357e2cb1decSSalil Mehta 1358e2cb1decSSalil Mehta roce->rinfo.num_vectors = HCLGEVF_ROCEE_VECTOR_NUM; 1359e2cb1decSSalil Mehta 1360e2cb1decSSalil Mehta if (hdev->num_msi_left < roce->rinfo.num_vectors || 1361e2cb1decSSalil Mehta hdev->num_msi_left == 0) 1362e2cb1decSSalil Mehta return -EINVAL; 1363e2cb1decSSalil Mehta 1364e2cb1decSSalil Mehta roce->rinfo.base_vector = 1365e2cb1decSSalil Mehta hdev->vector_status[hdev->num_msi_used]; 1366e2cb1decSSalil Mehta 1367e2cb1decSSalil Mehta roce->rinfo.netdev = nic->kinfo.netdev; 1368e2cb1decSSalil Mehta roce->rinfo.roce_io_base = hdev->hw.io_base; 1369e2cb1decSSalil Mehta 1370e2cb1decSSalil Mehta roce->pdev = nic->pdev; 1371e2cb1decSSalil Mehta roce->ae_algo = nic->ae_algo; 1372e2cb1decSSalil Mehta roce->numa_node_mask = nic->numa_node_mask; 1373e2cb1decSSalil Mehta 1374e2cb1decSSalil Mehta return 0; 1375e2cb1decSSalil Mehta } 1376e2cb1decSSalil Mehta 1377e2cb1decSSalil Mehta static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 1378e2cb1decSSalil Mehta { 1379e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1380e2cb1decSSalil Mehta int i, ret; 1381e2cb1decSSalil Mehta 1382e2cb1decSSalil Mehta rss_cfg->rss_size = hdev->rss_size_max; 1383e2cb1decSSalil Mehta 1384e2cb1decSSalil Mehta /* Initialize RSS indirect table for each vport */ 1385e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 1386e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max; 1387e2cb1decSSalil Mehta 1388e2cb1decSSalil Mehta ret = hclgevf_set_rss_indir_table(hdev); 1389e2cb1decSSalil Mehta if (ret) 1390e2cb1decSSalil Mehta return ret; 1391e2cb1decSSalil Mehta 1392e2cb1decSSalil Mehta return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max); 1393e2cb1decSSalil Mehta } 1394e2cb1decSSalil Mehta 1395e2cb1decSSalil Mehta static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 1396e2cb1decSSalil Mehta { 1397e2cb1decSSalil Mehta /* other vlan config(like, VLAN TX/RX offload) would also be added 1398e2cb1decSSalil Mehta * here later 1399e2cb1decSSalil Mehta */ 1400e2cb1decSSalil Mehta return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 1401e2cb1decSSalil Mehta false); 1402e2cb1decSSalil Mehta } 1403e2cb1decSSalil Mehta 1404e2cb1decSSalil Mehta static int hclgevf_ae_start(struct hnae3_handle *handle) 1405e2cb1decSSalil Mehta { 1406e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1407e2cb1decSSalil Mehta int i, queue_id; 1408e2cb1decSSalil Mehta 1409e2cb1decSSalil Mehta for (i = 0; i < handle->kinfo.num_tqps; i++) { 1410e2cb1decSSalil Mehta /* ring enable */ 1411e2cb1decSSalil Mehta queue_id = hclgevf_get_queue_id(handle->kinfo.tqp[i]); 1412e2cb1decSSalil Mehta if (queue_id < 0) { 1413e2cb1decSSalil Mehta dev_warn(&hdev->pdev->dev, 1414e2cb1decSSalil Mehta "Get invalid queue id, ignore it\n"); 1415e2cb1decSSalil Mehta continue; 1416e2cb1decSSalil Mehta } 1417e2cb1decSSalil Mehta 1418e2cb1decSSalil Mehta hclgevf_tqp_enable(hdev, queue_id, 0, true); 1419e2cb1decSSalil Mehta } 1420e2cb1decSSalil Mehta 1421e2cb1decSSalil Mehta /* reset tqp stats */ 1422e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 1423e2cb1decSSalil Mehta 1424e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1425e2cb1decSSalil Mehta 1426e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1427e2cb1decSSalil Mehta mod_timer(&hdev->service_timer, jiffies + HZ); 1428e2cb1decSSalil Mehta 1429e2cb1decSSalil Mehta return 0; 1430e2cb1decSSalil Mehta } 1431e2cb1decSSalil Mehta 1432e2cb1decSSalil Mehta static void hclgevf_ae_stop(struct hnae3_handle *handle) 1433e2cb1decSSalil Mehta { 1434e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1435e2cb1decSSalil Mehta int i, queue_id; 1436e2cb1decSSalil Mehta 1437e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 1438e2cb1decSSalil Mehta /* Ring disable */ 1439e2cb1decSSalil Mehta queue_id = hclgevf_get_queue_id(handle->kinfo.tqp[i]); 1440e2cb1decSSalil Mehta if (queue_id < 0) { 1441e2cb1decSSalil Mehta dev_warn(&hdev->pdev->dev, 1442e2cb1decSSalil Mehta "Get invalid queue id, ignore it\n"); 1443e2cb1decSSalil Mehta continue; 1444e2cb1decSSalil Mehta } 1445e2cb1decSSalil Mehta 1446e2cb1decSSalil Mehta hclgevf_tqp_enable(hdev, queue_id, 0, false); 1447e2cb1decSSalil Mehta } 1448e2cb1decSSalil Mehta 1449e2cb1decSSalil Mehta /* reset tqp stats */ 1450e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 14518cc6c1f7SFuyun Liang del_timer_sync(&hdev->service_timer); 14528cc6c1f7SFuyun Liang cancel_work_sync(&hdev->service_task); 1453f5be7967SYunsheng Lin clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 14548cc6c1f7SFuyun Liang hclgevf_update_link_status(hdev, 0); 1455e2cb1decSSalil Mehta } 1456e2cb1decSSalil Mehta 1457e2cb1decSSalil Mehta static void hclgevf_state_init(struct hclgevf_dev *hdev) 1458e2cb1decSSalil Mehta { 14597a01c897SSalil Mehta /* if this is on going reset then skip this initialization */ 14607a01c897SSalil Mehta if (hclgevf_dev_ongoing_reset(hdev)) 14617a01c897SSalil Mehta return; 14627a01c897SSalil Mehta 1463e2cb1decSSalil Mehta /* setup tasks for the MBX */ 1464e2cb1decSSalil Mehta INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 1465e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1466e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1467e2cb1decSSalil Mehta 1468e2cb1decSSalil Mehta /* setup tasks for service timer */ 1469e2cb1decSSalil Mehta timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 1470e2cb1decSSalil Mehta 1471e2cb1decSSalil Mehta INIT_WORK(&hdev->service_task, hclgevf_service_task); 1472e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1473e2cb1decSSalil Mehta 147435a1e503SSalil Mehta INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task); 147535a1e503SSalil Mehta 1476e2cb1decSSalil Mehta mutex_init(&hdev->mbx_resp.mbx_mutex); 1477e2cb1decSSalil Mehta 1478e2cb1decSSalil Mehta /* bring the device down */ 1479e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1480e2cb1decSSalil Mehta } 1481e2cb1decSSalil Mehta 1482e2cb1decSSalil Mehta static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 1483e2cb1decSSalil Mehta { 1484e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1485e2cb1decSSalil Mehta 1486e2cb1decSSalil Mehta if (hdev->service_timer.function) 1487e2cb1decSSalil Mehta del_timer_sync(&hdev->service_timer); 1488e2cb1decSSalil Mehta if (hdev->service_task.func) 1489e2cb1decSSalil Mehta cancel_work_sync(&hdev->service_task); 1490e2cb1decSSalil Mehta if (hdev->mbx_service_task.func) 1491e2cb1decSSalil Mehta cancel_work_sync(&hdev->mbx_service_task); 149235a1e503SSalil Mehta if (hdev->rst_service_task.func) 149335a1e503SSalil Mehta cancel_work_sync(&hdev->rst_service_task); 1494e2cb1decSSalil Mehta 1495e2cb1decSSalil Mehta mutex_destroy(&hdev->mbx_resp.mbx_mutex); 1496e2cb1decSSalil Mehta } 1497e2cb1decSSalil Mehta 1498e2cb1decSSalil Mehta static int hclgevf_init_msi(struct hclgevf_dev *hdev) 1499e2cb1decSSalil Mehta { 1500e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 1501e2cb1decSSalil Mehta int vectors; 1502e2cb1decSSalil Mehta int i; 1503e2cb1decSSalil Mehta 15047a01c897SSalil Mehta /* if this is on going reset then skip this initialization */ 15057a01c897SSalil Mehta if (hclgevf_dev_ongoing_reset(hdev)) 15067a01c897SSalil Mehta return 0; 15077a01c897SSalil Mehta 1508e2cb1decSSalil Mehta hdev->num_msi = HCLGEVF_MAX_VF_VECTOR_NUM; 1509e2cb1decSSalil Mehta 1510e2cb1decSSalil Mehta vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 1511e2cb1decSSalil Mehta PCI_IRQ_MSI | PCI_IRQ_MSIX); 1512e2cb1decSSalil Mehta if (vectors < 0) { 1513e2cb1decSSalil Mehta dev_err(&pdev->dev, 1514e2cb1decSSalil Mehta "failed(%d) to allocate MSI/MSI-X vectors\n", 1515e2cb1decSSalil Mehta vectors); 1516e2cb1decSSalil Mehta return vectors; 1517e2cb1decSSalil Mehta } 1518e2cb1decSSalil Mehta if (vectors < hdev->num_msi) 1519e2cb1decSSalil Mehta dev_warn(&hdev->pdev->dev, 1520e2cb1decSSalil Mehta "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 1521e2cb1decSSalil Mehta hdev->num_msi, vectors); 1522e2cb1decSSalil Mehta 1523e2cb1decSSalil Mehta hdev->num_msi = vectors; 1524e2cb1decSSalil Mehta hdev->num_msi_left = vectors; 1525e2cb1decSSalil Mehta hdev->base_msi_vector = pdev->irq; 1526e2cb1decSSalil Mehta 1527e2cb1decSSalil Mehta hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 1528e2cb1decSSalil Mehta sizeof(u16), GFP_KERNEL); 1529e2cb1decSSalil Mehta if (!hdev->vector_status) { 1530e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 1531e2cb1decSSalil Mehta return -ENOMEM; 1532e2cb1decSSalil Mehta } 1533e2cb1decSSalil Mehta 1534e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 1535e2cb1decSSalil Mehta hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 1536e2cb1decSSalil Mehta 1537e2cb1decSSalil Mehta hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 1538e2cb1decSSalil Mehta sizeof(int), GFP_KERNEL); 1539e2cb1decSSalil Mehta if (!hdev->vector_irq) { 1540e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 1541e2cb1decSSalil Mehta return -ENOMEM; 1542e2cb1decSSalil Mehta } 1543e2cb1decSSalil Mehta 1544e2cb1decSSalil Mehta return 0; 1545e2cb1decSSalil Mehta } 1546e2cb1decSSalil Mehta 1547e2cb1decSSalil Mehta static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 1548e2cb1decSSalil Mehta { 1549e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 1550e2cb1decSSalil Mehta 1551e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 1552e2cb1decSSalil Mehta } 1553e2cb1decSSalil Mehta 1554e2cb1decSSalil Mehta static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 1555e2cb1decSSalil Mehta { 1556e2cb1decSSalil Mehta int ret = 0; 1557e2cb1decSSalil Mehta 15587a01c897SSalil Mehta /* if this is on going reset then skip this initialization */ 15597a01c897SSalil Mehta if (hclgevf_dev_ongoing_reset(hdev)) 15607a01c897SSalil Mehta return 0; 15617a01c897SSalil Mehta 1562e2cb1decSSalil Mehta hclgevf_get_misc_vector(hdev); 1563e2cb1decSSalil Mehta 1564e2cb1decSSalil Mehta ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 1565e2cb1decSSalil Mehta 0, "hclgevf_cmd", hdev); 1566e2cb1decSSalil Mehta if (ret) { 1567e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 1568e2cb1decSSalil Mehta hdev->misc_vector.vector_irq); 1569e2cb1decSSalil Mehta return ret; 1570e2cb1decSSalil Mehta } 1571e2cb1decSSalil Mehta 15721819e409SXi Wang hclgevf_clear_event_cause(hdev, 0); 15731819e409SXi Wang 1574e2cb1decSSalil Mehta /* enable misc. vector(vector 0) */ 1575e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 1576e2cb1decSSalil Mehta 1577e2cb1decSSalil Mehta return ret; 1578e2cb1decSSalil Mehta } 1579e2cb1decSSalil Mehta 1580e2cb1decSSalil Mehta static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 1581e2cb1decSSalil Mehta { 1582e2cb1decSSalil Mehta /* disable misc vector(vector 0) */ 1583e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 15841819e409SXi Wang synchronize_irq(hdev->misc_vector.vector_irq); 1585e2cb1decSSalil Mehta free_irq(hdev->misc_vector.vector_irq, hdev); 1586e2cb1decSSalil Mehta hclgevf_free_vector(hdev, 0); 1587e2cb1decSSalil Mehta } 1588e2cb1decSSalil Mehta 1589e2cb1decSSalil Mehta static int hclgevf_init_instance(struct hclgevf_dev *hdev, 1590e2cb1decSSalil Mehta struct hnae3_client *client) 1591e2cb1decSSalil Mehta { 1592e2cb1decSSalil Mehta int ret; 1593e2cb1decSSalil Mehta 1594e2cb1decSSalil Mehta switch (client->type) { 1595e2cb1decSSalil Mehta case HNAE3_CLIENT_KNIC: 1596e2cb1decSSalil Mehta hdev->nic_client = client; 1597e2cb1decSSalil Mehta hdev->nic.client = client; 1598e2cb1decSSalil Mehta 1599e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->nic); 1600e2cb1decSSalil Mehta if (ret) 1601e2cb1decSSalil Mehta return ret; 1602e2cb1decSSalil Mehta 1603e2cb1decSSalil Mehta if (hdev->roce_client && hnae3_dev_roce_supported(hdev)) { 1604e2cb1decSSalil Mehta struct hnae3_client *rc = hdev->roce_client; 1605e2cb1decSSalil Mehta 1606e2cb1decSSalil Mehta ret = hclgevf_init_roce_base_info(hdev); 1607e2cb1decSSalil Mehta if (ret) 1608e2cb1decSSalil Mehta return ret; 1609e2cb1decSSalil Mehta ret = rc->ops->init_instance(&hdev->roce); 1610e2cb1decSSalil Mehta if (ret) 1611e2cb1decSSalil Mehta return ret; 1612e2cb1decSSalil Mehta } 1613e2cb1decSSalil Mehta break; 1614e2cb1decSSalil Mehta case HNAE3_CLIENT_UNIC: 1615e2cb1decSSalil Mehta hdev->nic_client = client; 1616e2cb1decSSalil Mehta hdev->nic.client = client; 1617e2cb1decSSalil Mehta 1618e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->nic); 1619e2cb1decSSalil Mehta if (ret) 1620e2cb1decSSalil Mehta return ret; 1621e2cb1decSSalil Mehta break; 1622e2cb1decSSalil Mehta case HNAE3_CLIENT_ROCE: 1623544a7bcdSLijun Ou if (hnae3_dev_roce_supported(hdev)) { 1624e2cb1decSSalil Mehta hdev->roce_client = client; 1625e2cb1decSSalil Mehta hdev->roce.client = client; 1626544a7bcdSLijun Ou } 1627e2cb1decSSalil Mehta 1628544a7bcdSLijun Ou if (hdev->roce_client && hdev->nic_client) { 1629e2cb1decSSalil Mehta ret = hclgevf_init_roce_base_info(hdev); 1630e2cb1decSSalil Mehta if (ret) 1631e2cb1decSSalil Mehta return ret; 1632e2cb1decSSalil Mehta 1633e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->roce); 1634e2cb1decSSalil Mehta if (ret) 1635e2cb1decSSalil Mehta return ret; 1636e2cb1decSSalil Mehta } 1637e2cb1decSSalil Mehta } 1638e2cb1decSSalil Mehta 1639e2cb1decSSalil Mehta return 0; 1640e2cb1decSSalil Mehta } 1641e2cb1decSSalil Mehta 1642e2cb1decSSalil Mehta static void hclgevf_uninit_instance(struct hclgevf_dev *hdev, 1643e2cb1decSSalil Mehta struct hnae3_client *client) 1644e2cb1decSSalil Mehta { 1645e2cb1decSSalil Mehta /* un-init roce, if it exists */ 1646e2cb1decSSalil Mehta if (hdev->roce_client) 1647e2cb1decSSalil Mehta hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 1648e2cb1decSSalil Mehta 1649e2cb1decSSalil Mehta /* un-init nic/unic, if this was not called by roce client */ 1650e2cb1decSSalil Mehta if ((client->ops->uninit_instance) && 1651e2cb1decSSalil Mehta (client->type != HNAE3_CLIENT_ROCE)) 1652e2cb1decSSalil Mehta client->ops->uninit_instance(&hdev->nic, 0); 1653e2cb1decSSalil Mehta } 1654e2cb1decSSalil Mehta 1655e2cb1decSSalil Mehta static int hclgevf_register_client(struct hnae3_client *client, 1656e2cb1decSSalil Mehta struct hnae3_ae_dev *ae_dev) 1657e2cb1decSSalil Mehta { 1658e2cb1decSSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 1659e2cb1decSSalil Mehta 1660e2cb1decSSalil Mehta return hclgevf_init_instance(hdev, client); 1661e2cb1decSSalil Mehta } 1662e2cb1decSSalil Mehta 1663e2cb1decSSalil Mehta static void hclgevf_unregister_client(struct hnae3_client *client, 1664e2cb1decSSalil Mehta struct hnae3_ae_dev *ae_dev) 1665e2cb1decSSalil Mehta { 1666e2cb1decSSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 1667e2cb1decSSalil Mehta 1668e2cb1decSSalil Mehta hclgevf_uninit_instance(hdev, client); 1669e2cb1decSSalil Mehta } 1670e2cb1decSSalil Mehta 1671e2cb1decSSalil Mehta static int hclgevf_pci_init(struct hclgevf_dev *hdev) 1672e2cb1decSSalil Mehta { 1673e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 1674e2cb1decSSalil Mehta struct hclgevf_hw *hw; 1675e2cb1decSSalil Mehta int ret; 1676e2cb1decSSalil Mehta 16777a01c897SSalil Mehta /* check if we need to skip initialization of pci. This will happen if 16787a01c897SSalil Mehta * device is undergoing VF reset. Otherwise, we would need to 16797a01c897SSalil Mehta * re-initialize pci interface again i.e. when device is not going 16807a01c897SSalil Mehta * through *any* reset or actually undergoing full reset. 16817a01c897SSalil Mehta */ 16827a01c897SSalil Mehta if (hclgevf_dev_ongoing_reset(hdev)) 16837a01c897SSalil Mehta return 0; 16847a01c897SSalil Mehta 1685e2cb1decSSalil Mehta ret = pci_enable_device(pdev); 1686e2cb1decSSalil Mehta if (ret) { 1687e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed to enable PCI device\n"); 16883e249d3bSFuyun Liang return ret; 1689e2cb1decSSalil Mehta } 1690e2cb1decSSalil Mehta 1691e2cb1decSSalil Mehta ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 1692e2cb1decSSalil Mehta if (ret) { 1693e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 1694e2cb1decSSalil Mehta goto err_disable_device; 1695e2cb1decSSalil Mehta } 1696e2cb1decSSalil Mehta 1697e2cb1decSSalil Mehta ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 1698e2cb1decSSalil Mehta if (ret) { 1699e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 1700e2cb1decSSalil Mehta goto err_disable_device; 1701e2cb1decSSalil Mehta } 1702e2cb1decSSalil Mehta 1703e2cb1decSSalil Mehta pci_set_master(pdev); 1704e2cb1decSSalil Mehta hw = &hdev->hw; 1705e2cb1decSSalil Mehta hw->hdev = hdev; 17062e1ea493SPeng Li hw->io_base = pci_iomap(pdev, 2, 0); 1707e2cb1decSSalil Mehta if (!hw->io_base) { 1708e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't map configuration register space\n"); 1709e2cb1decSSalil Mehta ret = -ENOMEM; 1710e2cb1decSSalil Mehta goto err_clr_master; 1711e2cb1decSSalil Mehta } 1712e2cb1decSSalil Mehta 1713e2cb1decSSalil Mehta return 0; 1714e2cb1decSSalil Mehta 1715e2cb1decSSalil Mehta err_clr_master: 1716e2cb1decSSalil Mehta pci_clear_master(pdev); 1717e2cb1decSSalil Mehta pci_release_regions(pdev); 1718e2cb1decSSalil Mehta err_disable_device: 1719e2cb1decSSalil Mehta pci_disable_device(pdev); 17203e249d3bSFuyun Liang 1721e2cb1decSSalil Mehta return ret; 1722e2cb1decSSalil Mehta } 1723e2cb1decSSalil Mehta 1724e2cb1decSSalil Mehta static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 1725e2cb1decSSalil Mehta { 1726e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 1727e2cb1decSSalil Mehta 1728e2cb1decSSalil Mehta pci_iounmap(pdev, hdev->hw.io_base); 1729e2cb1decSSalil Mehta pci_clear_master(pdev); 1730e2cb1decSSalil Mehta pci_release_regions(pdev); 1731e2cb1decSSalil Mehta pci_disable_device(pdev); 1732e2cb1decSSalil Mehta } 1733e2cb1decSSalil Mehta 17347a01c897SSalil Mehta static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 1735e2cb1decSSalil Mehta { 17367a01c897SSalil Mehta struct pci_dev *pdev = hdev->pdev; 1737e2cb1decSSalil Mehta int ret; 1738e2cb1decSSalil Mehta 17397a01c897SSalil Mehta /* check if device is on-going full reset(i.e. pcie as well) */ 17407a01c897SSalil Mehta if (hclgevf_dev_ongoing_full_reset(hdev)) { 17417a01c897SSalil Mehta dev_warn(&pdev->dev, "device is going full reset\n"); 17427a01c897SSalil Mehta hclgevf_uninit_hdev(hdev); 17437a01c897SSalil Mehta } 1744e2cb1decSSalil Mehta 1745e2cb1decSSalil Mehta ret = hclgevf_pci_init(hdev); 1746e2cb1decSSalil Mehta if (ret) { 1747e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI initialization failed\n"); 1748e2cb1decSSalil Mehta return ret; 1749e2cb1decSSalil Mehta } 1750e2cb1decSSalil Mehta 1751e2cb1decSSalil Mehta ret = hclgevf_init_msi(hdev); 1752e2cb1decSSalil Mehta if (ret) { 1753e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 1754e2cb1decSSalil Mehta goto err_irq_init; 1755e2cb1decSSalil Mehta } 1756e2cb1decSSalil Mehta 1757e2cb1decSSalil Mehta hclgevf_state_init(hdev); 1758e2cb1decSSalil Mehta 1759eddf0462SYunsheng Lin ret = hclgevf_cmd_init(hdev); 1760eddf0462SYunsheng Lin if (ret) 1761eddf0462SYunsheng Lin goto err_cmd_init; 1762eddf0462SYunsheng Lin 1763e2cb1decSSalil Mehta ret = hclgevf_misc_irq_init(hdev); 1764e2cb1decSSalil Mehta if (ret) { 1765e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 1766e2cb1decSSalil Mehta ret); 1767e2cb1decSSalil Mehta goto err_misc_irq_init; 1768e2cb1decSSalil Mehta } 1769e2cb1decSSalil Mehta 1770e2cb1decSSalil Mehta ret = hclgevf_configure(hdev); 1771e2cb1decSSalil Mehta if (ret) { 1772e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 1773e2cb1decSSalil Mehta goto err_config; 1774e2cb1decSSalil Mehta } 1775e2cb1decSSalil Mehta 1776e2cb1decSSalil Mehta ret = hclgevf_alloc_tqps(hdev); 1777e2cb1decSSalil Mehta if (ret) { 1778e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 1779e2cb1decSSalil Mehta goto err_config; 1780e2cb1decSSalil Mehta } 1781e2cb1decSSalil Mehta 1782e2cb1decSSalil Mehta ret = hclgevf_set_handle_info(hdev); 1783e2cb1decSSalil Mehta if (ret) { 1784e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 1785e2cb1decSSalil Mehta goto err_config; 1786e2cb1decSSalil Mehta } 1787e2cb1decSSalil Mehta 17883a678b58SXi Wang /* Initialize mta type for this VF */ 17893a678b58SXi Wang ret = hclgevf_cfg_func_mta_type(hdev); 1790e2cb1decSSalil Mehta if (ret) { 1791e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 17923a678b58SXi Wang "failed(%d) to initialize MTA type\n", ret); 1793e2cb1decSSalil Mehta goto err_config; 1794e2cb1decSSalil Mehta } 1795e2cb1decSSalil Mehta 1796e2cb1decSSalil Mehta /* Initialize RSS for this VF */ 1797e2cb1decSSalil Mehta ret = hclgevf_rss_init_hw(hdev); 1798e2cb1decSSalil Mehta if (ret) { 1799e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1800e2cb1decSSalil Mehta "failed(%d) to initialize RSS\n", ret); 1801e2cb1decSSalil Mehta goto err_config; 1802e2cb1decSSalil Mehta } 1803e2cb1decSSalil Mehta 1804e2cb1decSSalil Mehta ret = hclgevf_init_vlan_config(hdev); 1805e2cb1decSSalil Mehta if (ret) { 1806e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1807e2cb1decSSalil Mehta "failed(%d) to initialize VLAN config\n", ret); 1808e2cb1decSSalil Mehta goto err_config; 1809e2cb1decSSalil Mehta } 1810e2cb1decSSalil Mehta 1811e2cb1decSSalil Mehta pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME); 1812e2cb1decSSalil Mehta 1813e2cb1decSSalil Mehta return 0; 1814e2cb1decSSalil Mehta 1815e2cb1decSSalil Mehta err_config: 1816e2cb1decSSalil Mehta hclgevf_misc_irq_uninit(hdev); 1817e2cb1decSSalil Mehta err_misc_irq_init: 1818eddf0462SYunsheng Lin hclgevf_cmd_uninit(hdev); 1819eddf0462SYunsheng Lin err_cmd_init: 1820e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 1821e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 1822e2cb1decSSalil Mehta err_irq_init: 1823e2cb1decSSalil Mehta hclgevf_pci_uninit(hdev); 1824e2cb1decSSalil Mehta return ret; 1825e2cb1decSSalil Mehta } 1826e2cb1decSSalil Mehta 18277a01c897SSalil Mehta static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 1828e2cb1decSSalil Mehta { 1829e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 1830eddf0462SYunsheng Lin hclgevf_misc_irq_uninit(hdev); 1831eddf0462SYunsheng Lin hclgevf_cmd_uninit(hdev); 1832e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 1833e2cb1decSSalil Mehta hclgevf_pci_uninit(hdev); 18347a01c897SSalil Mehta } 18357a01c897SSalil Mehta 18367a01c897SSalil Mehta static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 18377a01c897SSalil Mehta { 18387a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 18397a01c897SSalil Mehta int ret; 18407a01c897SSalil Mehta 18417a01c897SSalil Mehta ret = hclgevf_alloc_hdev(ae_dev); 18427a01c897SSalil Mehta if (ret) { 18437a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device allocation failed\n"); 18447a01c897SSalil Mehta return ret; 18457a01c897SSalil Mehta } 18467a01c897SSalil Mehta 18477a01c897SSalil Mehta ret = hclgevf_init_hdev(ae_dev->priv); 18487a01c897SSalil Mehta if (ret) 18497a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device initialization failed\n"); 18507a01c897SSalil Mehta 18517a01c897SSalil Mehta return ret; 18527a01c897SSalil Mehta } 18537a01c897SSalil Mehta 18547a01c897SSalil Mehta static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 18557a01c897SSalil Mehta { 18567a01c897SSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 18577a01c897SSalil Mehta 18587a01c897SSalil Mehta hclgevf_uninit_hdev(hdev); 1859e2cb1decSSalil Mehta ae_dev->priv = NULL; 1860e2cb1decSSalil Mehta } 1861e2cb1decSSalil Mehta 1862849e4607SPeng Li static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 1863849e4607SPeng Li { 1864849e4607SPeng Li struct hnae3_handle *nic = &hdev->nic; 1865849e4607SPeng Li struct hnae3_knic_private_info *kinfo = &nic->kinfo; 1866849e4607SPeng Li 1867849e4607SPeng Li return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps); 1868849e4607SPeng Li } 1869849e4607SPeng Li 1870849e4607SPeng Li /** 1871849e4607SPeng Li * hclgevf_get_channels - Get the current channels enabled and max supported. 1872849e4607SPeng Li * @handle: hardware information for network interface 1873849e4607SPeng Li * @ch: ethtool channels structure 1874849e4607SPeng Li * 1875849e4607SPeng Li * We don't support separate tx and rx queues as channels. The other count 1876849e4607SPeng Li * represents how many queues are being used for control. max_combined counts 1877849e4607SPeng Li * how many queue pairs we can support. They may not be mapped 1 to 1 with 1878849e4607SPeng Li * q_vectors since we support a lot more queue pairs than q_vectors. 1879849e4607SPeng Li **/ 1880849e4607SPeng Li static void hclgevf_get_channels(struct hnae3_handle *handle, 1881849e4607SPeng Li struct ethtool_channels *ch) 1882849e4607SPeng Li { 1883849e4607SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1884849e4607SPeng Li 1885849e4607SPeng Li ch->max_combined = hclgevf_get_max_channels(hdev); 1886849e4607SPeng Li ch->other_count = 0; 1887849e4607SPeng Li ch->max_other = 0; 1888849e4607SPeng Li ch->combined_count = hdev->num_tqps; 1889849e4607SPeng Li } 1890849e4607SPeng Li 1891cc719218SPeng Li static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 1892cc719218SPeng Li u16 *free_tqps, u16 *max_rss_size) 1893cc719218SPeng Li { 1894cc719218SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1895cc719218SPeng Li 1896cc719218SPeng Li *free_tqps = 0; 1897cc719218SPeng Li *max_rss_size = hdev->rss_size_max; 1898cc719218SPeng Li } 1899cc719218SPeng Li 1900175ec96bSFuyun Liang static int hclgevf_get_status(struct hnae3_handle *handle) 1901175ec96bSFuyun Liang { 1902175ec96bSFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1903175ec96bSFuyun Liang 1904175ec96bSFuyun Liang return hdev->hw.mac.link; 1905175ec96bSFuyun Liang } 1906175ec96bSFuyun Liang 19074a152de9SFuyun Liang static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 19084a152de9SFuyun Liang u8 *auto_neg, u32 *speed, 19094a152de9SFuyun Liang u8 *duplex) 19104a152de9SFuyun Liang { 19114a152de9SFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 19124a152de9SFuyun Liang 19134a152de9SFuyun Liang if (speed) 19144a152de9SFuyun Liang *speed = hdev->hw.mac.speed; 19154a152de9SFuyun Liang if (duplex) 19164a152de9SFuyun Liang *duplex = hdev->hw.mac.duplex; 19174a152de9SFuyun Liang if (auto_neg) 19184a152de9SFuyun Liang *auto_neg = AUTONEG_DISABLE; 19194a152de9SFuyun Liang } 19204a152de9SFuyun Liang 19214a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 19224a152de9SFuyun Liang u8 duplex) 19234a152de9SFuyun Liang { 19244a152de9SFuyun Liang hdev->hw.mac.speed = speed; 19254a152de9SFuyun Liang hdev->hw.mac.duplex = duplex; 19264a152de9SFuyun Liang } 19274a152de9SFuyun Liang 1928e2cb1decSSalil Mehta static const struct hnae3_ae_ops hclgevf_ops = { 1929e2cb1decSSalil Mehta .init_ae_dev = hclgevf_init_ae_dev, 1930e2cb1decSSalil Mehta .uninit_ae_dev = hclgevf_uninit_ae_dev, 1931e2cb1decSSalil Mehta .init_client_instance = hclgevf_register_client, 1932e2cb1decSSalil Mehta .uninit_client_instance = hclgevf_unregister_client, 1933e2cb1decSSalil Mehta .start = hclgevf_ae_start, 1934e2cb1decSSalil Mehta .stop = hclgevf_ae_stop, 1935e2cb1decSSalil Mehta .map_ring_to_vector = hclgevf_map_ring_to_vector, 1936e2cb1decSSalil Mehta .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 1937e2cb1decSSalil Mehta .get_vector = hclgevf_get_vector, 19380d3e6631SYunsheng Lin .put_vector = hclgevf_put_vector, 1939e2cb1decSSalil Mehta .reset_queue = hclgevf_reset_tqp, 1940e2cb1decSSalil Mehta .set_promisc_mode = hclgevf_set_promisc_mode, 1941e2cb1decSSalil Mehta .get_mac_addr = hclgevf_get_mac_addr, 1942e2cb1decSSalil Mehta .set_mac_addr = hclgevf_set_mac_addr, 1943e2cb1decSSalil Mehta .add_uc_addr = hclgevf_add_uc_addr, 1944e2cb1decSSalil Mehta .rm_uc_addr = hclgevf_rm_uc_addr, 1945e2cb1decSSalil Mehta .add_mc_addr = hclgevf_add_mc_addr, 1946e2cb1decSSalil Mehta .rm_mc_addr = hclgevf_rm_mc_addr, 19473a678b58SXi Wang .update_mta_status = hclgevf_update_mta_status, 1948e2cb1decSSalil Mehta .get_stats = hclgevf_get_stats, 1949e2cb1decSSalil Mehta .update_stats = hclgevf_update_stats, 1950e2cb1decSSalil Mehta .get_strings = hclgevf_get_strings, 1951e2cb1decSSalil Mehta .get_sset_count = hclgevf_get_sset_count, 1952e2cb1decSSalil Mehta .get_rss_key_size = hclgevf_get_rss_key_size, 1953e2cb1decSSalil Mehta .get_rss_indir_size = hclgevf_get_rss_indir_size, 1954e2cb1decSSalil Mehta .get_rss = hclgevf_get_rss, 1955e2cb1decSSalil Mehta .set_rss = hclgevf_set_rss, 1956e2cb1decSSalil Mehta .get_tc_size = hclgevf_get_tc_size, 1957e2cb1decSSalil Mehta .get_fw_version = hclgevf_get_fw_version, 1958e2cb1decSSalil Mehta .set_vlan_filter = hclgevf_set_vlan_filter, 1959b2641e2aSYunsheng Lin .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 19606d4c3981SSalil Mehta .reset_event = hclgevf_reset_event, 1961849e4607SPeng Li .get_channels = hclgevf_get_channels, 1962cc719218SPeng Li .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 1963175ec96bSFuyun Liang .get_status = hclgevf_get_status, 19644a152de9SFuyun Liang .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 1965e2cb1decSSalil Mehta }; 1966e2cb1decSSalil Mehta 1967e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf = { 1968e2cb1decSSalil Mehta .ops = &hclgevf_ops, 1969e2cb1decSSalil Mehta .name = HCLGEVF_NAME, 1970e2cb1decSSalil Mehta .pdev_id_table = ae_algovf_pci_tbl, 1971e2cb1decSSalil Mehta }; 1972e2cb1decSSalil Mehta 1973e2cb1decSSalil Mehta static int hclgevf_init(void) 1974e2cb1decSSalil Mehta { 1975e2cb1decSSalil Mehta pr_info("%s is initializing\n", HCLGEVF_NAME); 1976e2cb1decSSalil Mehta 1977854cf33aSFuyun Liang hnae3_register_ae_algo(&ae_algovf); 1978854cf33aSFuyun Liang 1979854cf33aSFuyun Liang return 0; 1980e2cb1decSSalil Mehta } 1981e2cb1decSSalil Mehta 1982e2cb1decSSalil Mehta static void hclgevf_exit(void) 1983e2cb1decSSalil Mehta { 1984e2cb1decSSalil Mehta hnae3_unregister_ae_algo(&ae_algovf); 1985e2cb1decSSalil Mehta } 1986e2cb1decSSalil Mehta module_init(hclgevf_init); 1987e2cb1decSSalil Mehta module_exit(hclgevf_exit); 1988e2cb1decSSalil Mehta 1989e2cb1decSSalil Mehta MODULE_LICENSE("GPL"); 1990e2cb1decSSalil Mehta MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 1991e2cb1decSSalil Mehta MODULE_DESCRIPTION("HCLGEVF Driver"); 1992e2cb1decSSalil Mehta MODULE_VERSION(HCLGEVF_MOD_VERSION); 1993