1e2cb1decSSalil Mehta // SPDX-License-Identifier: GPL-2.0+ 2e2cb1decSSalil Mehta // Copyright (c) 2016-2017 Hisilicon Limited. 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #include <linux/etherdevice.h> 5aa5c4f17SHuazhong Tan #include <linux/iopoll.h> 66988eb2aSSalil Mehta #include <net/rtnetlink.h> 7e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 8e2cb1decSSalil Mehta #include "hclgevf_main.h" 9e2cb1decSSalil Mehta #include "hclge_mbx.h" 10e2cb1decSSalil Mehta #include "hnae3.h" 11e2cb1decSSalil Mehta 12e2cb1decSSalil Mehta #define HCLGEVF_NAME "hclgevf" 13e2cb1decSSalil Mehta 14bbe6540eSHuazhong Tan #define HCLGEVF_RESET_MAX_FAIL_CNT 5 15bbe6540eSHuazhong Tan 169c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 17e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf; 18e2cb1decSSalil Mehta 190ea68902SYunsheng Lin static struct workqueue_struct *hclgevf_wq; 200ea68902SYunsheng Lin 21e2cb1decSSalil Mehta static const struct pci_device_id ae_algovf_pci_tbl[] = { 22c155e22bSGuangbin Huang {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0}, 23c155e22bSGuangbin Huang {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 24c155e22bSGuangbin Huang HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 25e2cb1decSSalil Mehta /* required last entry */ 26e2cb1decSSalil Mehta {0, } 27e2cb1decSSalil Mehta }; 28e2cb1decSSalil Mehta 29472d7eceSJian Shen static const u8 hclgevf_hash_key[] = { 30472d7eceSJian Shen 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 31472d7eceSJian Shen 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 32472d7eceSJian Shen 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 33472d7eceSJian Shen 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 34472d7eceSJian Shen 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 35472d7eceSJian Shen }; 36472d7eceSJian Shen 372f550a46SYunsheng Lin MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 382f550a46SYunsheng Lin 391600c3e5SJian Shen static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 401600c3e5SJian Shen HCLGEVF_CMDQ_TX_ADDR_H_REG, 411600c3e5SJian Shen HCLGEVF_CMDQ_TX_DEPTH_REG, 421600c3e5SJian Shen HCLGEVF_CMDQ_TX_TAIL_REG, 431600c3e5SJian Shen HCLGEVF_CMDQ_TX_HEAD_REG, 441600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_L_REG, 451600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_H_REG, 461600c3e5SJian Shen HCLGEVF_CMDQ_RX_DEPTH_REG, 471600c3e5SJian Shen HCLGEVF_CMDQ_RX_TAIL_REG, 481600c3e5SJian Shen HCLGEVF_CMDQ_RX_HEAD_REG, 491600c3e5SJian Shen HCLGEVF_VECTOR0_CMDQ_SRC_REG, 509cee2e8dSHuazhong Tan HCLGEVF_VECTOR0_CMDQ_STATE_REG, 511600c3e5SJian Shen HCLGEVF_CMDQ_INTR_EN_REG, 521600c3e5SJian Shen HCLGEVF_CMDQ_INTR_GEN_REG}; 531600c3e5SJian Shen 541600c3e5SJian Shen static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 551600c3e5SJian Shen HCLGEVF_RST_ING, 561600c3e5SJian Shen HCLGEVF_GRO_EN_REG}; 571600c3e5SJian Shen 581600c3e5SJian Shen static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 591600c3e5SJian Shen HCLGEVF_RING_RX_ADDR_H_REG, 601600c3e5SJian Shen HCLGEVF_RING_RX_BD_NUM_REG, 611600c3e5SJian Shen HCLGEVF_RING_RX_BD_LENGTH_REG, 621600c3e5SJian Shen HCLGEVF_RING_RX_MERGE_EN_REG, 631600c3e5SJian Shen HCLGEVF_RING_RX_TAIL_REG, 641600c3e5SJian Shen HCLGEVF_RING_RX_HEAD_REG, 651600c3e5SJian Shen HCLGEVF_RING_RX_FBD_NUM_REG, 661600c3e5SJian Shen HCLGEVF_RING_RX_OFFSET_REG, 671600c3e5SJian Shen HCLGEVF_RING_RX_FBD_OFFSET_REG, 681600c3e5SJian Shen HCLGEVF_RING_RX_STASH_REG, 691600c3e5SJian Shen HCLGEVF_RING_RX_BD_ERR_REG, 701600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_L_REG, 711600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_H_REG, 721600c3e5SJian Shen HCLGEVF_RING_TX_BD_NUM_REG, 731600c3e5SJian Shen HCLGEVF_RING_TX_PRIORITY_REG, 741600c3e5SJian Shen HCLGEVF_RING_TX_TC_REG, 751600c3e5SJian Shen HCLGEVF_RING_TX_MERGE_EN_REG, 761600c3e5SJian Shen HCLGEVF_RING_TX_TAIL_REG, 771600c3e5SJian Shen HCLGEVF_RING_TX_HEAD_REG, 781600c3e5SJian Shen HCLGEVF_RING_TX_FBD_NUM_REG, 791600c3e5SJian Shen HCLGEVF_RING_TX_OFFSET_REG, 801600c3e5SJian Shen HCLGEVF_RING_TX_EBD_NUM_REG, 811600c3e5SJian Shen HCLGEVF_RING_TX_EBD_OFFSET_REG, 821600c3e5SJian Shen HCLGEVF_RING_TX_BD_ERR_REG, 831600c3e5SJian Shen HCLGEVF_RING_EN_REG}; 841600c3e5SJian Shen 851600c3e5SJian Shen static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 861600c3e5SJian Shen HCLGEVF_TQP_INTR_GL0_REG, 871600c3e5SJian Shen HCLGEVF_TQP_INTR_GL1_REG, 881600c3e5SJian Shen HCLGEVF_TQP_INTR_GL2_REG, 891600c3e5SJian Shen HCLGEVF_TQP_INTR_RL_REG}; 901600c3e5SJian Shen 919b2f3477SWeihang Li static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 92e2cb1decSSalil Mehta { 93eed9535fSPeng Li if (!handle->client) 94eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, nic); 95eed9535fSPeng Li else if (handle->client->type == HNAE3_CLIENT_ROCE) 96eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, roce); 97eed9535fSPeng Li else 98e2cb1decSSalil Mehta return container_of(handle, struct hclgevf_dev, nic); 99e2cb1decSSalil Mehta } 100e2cb1decSSalil Mehta 101e2cb1decSSalil Mehta static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 102e2cb1decSSalil Mehta { 103b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 104e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 105e2cb1decSSalil Mehta struct hclgevf_desc desc; 106e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 107e2cb1decSSalil Mehta int status; 108e2cb1decSSalil Mehta int i; 109e2cb1decSSalil Mehta 110b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 111b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 112e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 113e2cb1decSSalil Mehta HCLGEVF_OPC_QUERY_RX_STATUS, 114e2cb1decSSalil Mehta true); 115e2cb1decSSalil Mehta 116e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 117e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 118e2cb1decSSalil Mehta if (status) { 119e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 120e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 121e2cb1decSSalil Mehta status, i); 122e2cb1decSSalil Mehta return status; 123e2cb1decSSalil Mehta } 124e2cb1decSSalil Mehta tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 125cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 126e2cb1decSSalil Mehta 127e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 128e2cb1decSSalil Mehta true); 129e2cb1decSSalil Mehta 130e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 131e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 132e2cb1decSSalil Mehta if (status) { 133e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 134e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 135e2cb1decSSalil Mehta status, i); 136e2cb1decSSalil Mehta return status; 137e2cb1decSSalil Mehta } 138e2cb1decSSalil Mehta tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 139cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 140e2cb1decSSalil Mehta } 141e2cb1decSSalil Mehta 142e2cb1decSSalil Mehta return 0; 143e2cb1decSSalil Mehta } 144e2cb1decSSalil Mehta 145e2cb1decSSalil Mehta static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 146e2cb1decSSalil Mehta { 147e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo = &handle->kinfo; 148e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 149e2cb1decSSalil Mehta u64 *buff = data; 150e2cb1decSSalil Mehta int i; 151e2cb1decSSalil Mehta 152b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 153b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 154e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 155e2cb1decSSalil Mehta } 156e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 157b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 158e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 159e2cb1decSSalil Mehta } 160e2cb1decSSalil Mehta 161e2cb1decSSalil Mehta return buff; 162e2cb1decSSalil Mehta } 163e2cb1decSSalil Mehta 164e2cb1decSSalil Mehta static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 165e2cb1decSSalil Mehta { 166b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 167e2cb1decSSalil Mehta 168b4f1d303SJian Shen return kinfo->num_tqps * 2; 169e2cb1decSSalil Mehta } 170e2cb1decSSalil Mehta 171e2cb1decSSalil Mehta static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 172e2cb1decSSalil Mehta { 173b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 174e2cb1decSSalil Mehta u8 *buff = data; 1759d8d5a36SYufeng Mo int i; 176e2cb1decSSalil Mehta 177b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 178b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 179e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1800c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 181e2cb1decSSalil Mehta tqp->index); 182e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 183e2cb1decSSalil Mehta } 184e2cb1decSSalil Mehta 185b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 186b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 187e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1880c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 189e2cb1decSSalil Mehta tqp->index); 190e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 191e2cb1decSSalil Mehta } 192e2cb1decSSalil Mehta 193e2cb1decSSalil Mehta return buff; 194e2cb1decSSalil Mehta } 195e2cb1decSSalil Mehta 196e2cb1decSSalil Mehta static void hclgevf_update_stats(struct hnae3_handle *handle, 197e2cb1decSSalil Mehta struct net_device_stats *net_stats) 198e2cb1decSSalil Mehta { 199e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 200e2cb1decSSalil Mehta int status; 201e2cb1decSSalil Mehta 202e2cb1decSSalil Mehta status = hclgevf_tqps_update_stats(handle); 203e2cb1decSSalil Mehta if (status) 204e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 205e2cb1decSSalil Mehta "VF update of TQPS stats fail, status = %d.\n", 206e2cb1decSSalil Mehta status); 207e2cb1decSSalil Mehta } 208e2cb1decSSalil Mehta 209e2cb1decSSalil Mehta static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 210e2cb1decSSalil Mehta { 211e2cb1decSSalil Mehta if (strset == ETH_SS_TEST) 212e2cb1decSSalil Mehta return -EOPNOTSUPP; 213e2cb1decSSalil Mehta else if (strset == ETH_SS_STATS) 214e2cb1decSSalil Mehta return hclgevf_tqps_get_sset_count(handle, strset); 215e2cb1decSSalil Mehta 216e2cb1decSSalil Mehta return 0; 217e2cb1decSSalil Mehta } 218e2cb1decSSalil Mehta 219e2cb1decSSalil Mehta static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 220e2cb1decSSalil Mehta u8 *data) 221e2cb1decSSalil Mehta { 222e2cb1decSSalil Mehta u8 *p = (char *)data; 223e2cb1decSSalil Mehta 224e2cb1decSSalil Mehta if (strset == ETH_SS_STATS) 225e2cb1decSSalil Mehta p = hclgevf_tqps_get_strings(handle, p); 226e2cb1decSSalil Mehta } 227e2cb1decSSalil Mehta 228e2cb1decSSalil Mehta static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 229e2cb1decSSalil Mehta { 230e2cb1decSSalil Mehta hclgevf_tqps_get_stats(handle, data); 231e2cb1decSSalil Mehta } 232e2cb1decSSalil Mehta 233d3410018SYufeng Mo static void hclgevf_build_send_msg(struct hclge_vf_to_pf_msg *msg, u8 code, 234d3410018SYufeng Mo u8 subcode) 235d3410018SYufeng Mo { 236d3410018SYufeng Mo if (msg) { 237d3410018SYufeng Mo memset(msg, 0, sizeof(struct hclge_vf_to_pf_msg)); 238d3410018SYufeng Mo msg->code = code; 239d3410018SYufeng Mo msg->subcode = subcode; 240d3410018SYufeng Mo } 241d3410018SYufeng Mo } 242d3410018SYufeng Mo 243e2cb1decSSalil Mehta static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 244e2cb1decSSalil Mehta { 245d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 246e2cb1decSSalil Mehta u8 resp_msg; 247e2cb1decSSalil Mehta int status; 248e2cb1decSSalil Mehta 249d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_TCINFO, 0); 250d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg, 251d3410018SYufeng Mo sizeof(resp_msg)); 252e2cb1decSSalil Mehta if (status) { 253e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 254e2cb1decSSalil Mehta "VF request to get TC info from PF failed %d", 255e2cb1decSSalil Mehta status); 256e2cb1decSSalil Mehta return status; 257e2cb1decSSalil Mehta } 258e2cb1decSSalil Mehta 259e2cb1decSSalil Mehta hdev->hw_tc_map = resp_msg; 260e2cb1decSSalil Mehta 261e2cb1decSSalil Mehta return 0; 262e2cb1decSSalil Mehta } 263e2cb1decSSalil Mehta 26492f11ea1SJian Shen static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 26592f11ea1SJian Shen { 26692f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 267d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 26892f11ea1SJian Shen u8 resp_msg; 26992f11ea1SJian Shen int ret; 27092f11ea1SJian Shen 271d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 272d3410018SYufeng Mo HCLGE_MBX_GET_PORT_BASE_VLAN_STATE); 273d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg, 274d3410018SYufeng Mo sizeof(u8)); 27592f11ea1SJian Shen if (ret) { 27692f11ea1SJian Shen dev_err(&hdev->pdev->dev, 27792f11ea1SJian Shen "VF request to get port based vlan state failed %d", 27892f11ea1SJian Shen ret); 27992f11ea1SJian Shen return ret; 28092f11ea1SJian Shen } 28192f11ea1SJian Shen 28292f11ea1SJian Shen nic->port_base_vlan_state = resp_msg; 28392f11ea1SJian Shen 28492f11ea1SJian Shen return 0; 28592f11ea1SJian Shen } 28692f11ea1SJian Shen 2876cee6fc3SJian Shen static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 288e2cb1decSSalil Mehta { 289c0425944SPeng Li #define HCLGEVF_TQPS_RSS_INFO_LEN 6 290d3410018SYufeng Mo #define HCLGEVF_TQPS_ALLOC_OFFSET 0 291d3410018SYufeng Mo #define HCLGEVF_TQPS_RSS_SIZE_OFFSET 2 292d3410018SYufeng Mo #define HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET 4 293d3410018SYufeng Mo 294e2cb1decSSalil Mehta u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 295d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 296e2cb1decSSalil Mehta int status; 297e2cb1decSSalil Mehta 298d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QINFO, 0); 299d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 300e2cb1decSSalil Mehta HCLGEVF_TQPS_RSS_INFO_LEN); 301e2cb1decSSalil Mehta if (status) { 302e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 303e2cb1decSSalil Mehta "VF request to get tqp info from PF failed %d", 304e2cb1decSSalil Mehta status); 305e2cb1decSSalil Mehta return status; 306e2cb1decSSalil Mehta } 307e2cb1decSSalil Mehta 308d3410018SYufeng Mo memcpy(&hdev->num_tqps, &resp_msg[HCLGEVF_TQPS_ALLOC_OFFSET], 309d3410018SYufeng Mo sizeof(u16)); 310d3410018SYufeng Mo memcpy(&hdev->rss_size_max, &resp_msg[HCLGEVF_TQPS_RSS_SIZE_OFFSET], 311d3410018SYufeng Mo sizeof(u16)); 312d3410018SYufeng Mo memcpy(&hdev->rx_buf_len, &resp_msg[HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET], 313d3410018SYufeng Mo sizeof(u16)); 314c0425944SPeng Li 315c0425944SPeng Li return 0; 316c0425944SPeng Li } 317c0425944SPeng Li 318c0425944SPeng Li static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 319c0425944SPeng Li { 320c0425944SPeng Li #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 321d3410018SYufeng Mo #define HCLGEVF_TQPS_NUM_TX_DESC_OFFSET 0 322d3410018SYufeng Mo #define HCLGEVF_TQPS_NUM_RX_DESC_OFFSET 2 323d3410018SYufeng Mo 324c0425944SPeng Li u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 325d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 326c0425944SPeng Li int ret; 327c0425944SPeng Li 328d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QDEPTH, 0); 329d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 330c0425944SPeng Li HCLGEVF_TQPS_DEPTH_INFO_LEN); 331c0425944SPeng Li if (ret) { 332c0425944SPeng Li dev_err(&hdev->pdev->dev, 333c0425944SPeng Li "VF request to get tqp depth info from PF failed %d", 334c0425944SPeng Li ret); 335c0425944SPeng Li return ret; 336c0425944SPeng Li } 337c0425944SPeng Li 338d3410018SYufeng Mo memcpy(&hdev->num_tx_desc, &resp_msg[HCLGEVF_TQPS_NUM_TX_DESC_OFFSET], 339d3410018SYufeng Mo sizeof(u16)); 340d3410018SYufeng Mo memcpy(&hdev->num_rx_desc, &resp_msg[HCLGEVF_TQPS_NUM_RX_DESC_OFFSET], 341d3410018SYufeng Mo sizeof(u16)); 342e2cb1decSSalil Mehta 343e2cb1decSSalil Mehta return 0; 344e2cb1decSSalil Mehta } 345e2cb1decSSalil Mehta 3460c29d191Sliuzhongzhu static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 3470c29d191Sliuzhongzhu { 3480c29d191Sliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 349d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 3500c29d191Sliuzhongzhu u16 qid_in_pf = 0; 351d3410018SYufeng Mo u8 resp_data[2]; 3520c29d191Sliuzhongzhu int ret; 3530c29d191Sliuzhongzhu 354d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QID_IN_PF, 0); 355d3410018SYufeng Mo memcpy(send_msg.data, &queue_id, sizeof(queue_id)); 356d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_data, 35763cbf7a9SYufeng Mo sizeof(resp_data)); 3580c29d191Sliuzhongzhu if (!ret) 3590c29d191Sliuzhongzhu qid_in_pf = *(u16 *)resp_data; 3600c29d191Sliuzhongzhu 3610c29d191Sliuzhongzhu return qid_in_pf; 3620c29d191Sliuzhongzhu } 3630c29d191Sliuzhongzhu 3649c3e7130Sliuzhongzhu static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 3659c3e7130Sliuzhongzhu { 366d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 36788d10bd6SJian Shen u8 resp_msg[2]; 3689c3e7130Sliuzhongzhu int ret; 3699c3e7130Sliuzhongzhu 370d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MEDIA_TYPE, 0); 371d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 372d3410018SYufeng Mo sizeof(resp_msg)); 3739c3e7130Sliuzhongzhu if (ret) { 3749c3e7130Sliuzhongzhu dev_err(&hdev->pdev->dev, 3759c3e7130Sliuzhongzhu "VF request to get the pf port media type failed %d", 3769c3e7130Sliuzhongzhu ret); 3779c3e7130Sliuzhongzhu return ret; 3789c3e7130Sliuzhongzhu } 3799c3e7130Sliuzhongzhu 38088d10bd6SJian Shen hdev->hw.mac.media_type = resp_msg[0]; 38188d10bd6SJian Shen hdev->hw.mac.module_type = resp_msg[1]; 3829c3e7130Sliuzhongzhu 3839c3e7130Sliuzhongzhu return 0; 3849c3e7130Sliuzhongzhu } 3859c3e7130Sliuzhongzhu 386e2cb1decSSalil Mehta static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 387e2cb1decSSalil Mehta { 388e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 389e2cb1decSSalil Mehta int i; 390e2cb1decSSalil Mehta 391e2cb1decSSalil Mehta hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 392e2cb1decSSalil Mehta sizeof(struct hclgevf_tqp), GFP_KERNEL); 393e2cb1decSSalil Mehta if (!hdev->htqp) 394e2cb1decSSalil Mehta return -ENOMEM; 395e2cb1decSSalil Mehta 396e2cb1decSSalil Mehta tqp = hdev->htqp; 397e2cb1decSSalil Mehta 398e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 399e2cb1decSSalil Mehta tqp->dev = &hdev->pdev->dev; 400e2cb1decSSalil Mehta tqp->index = i; 401e2cb1decSSalil Mehta 402e2cb1decSSalil Mehta tqp->q.ae_algo = &ae_algovf; 403e2cb1decSSalil Mehta tqp->q.buf_size = hdev->rx_buf_len; 404c0425944SPeng Li tqp->q.tx_desc_num = hdev->num_tx_desc; 405c0425944SPeng Li tqp->q.rx_desc_num = hdev->num_rx_desc; 406e2cb1decSSalil Mehta tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 407e2cb1decSSalil Mehta i * HCLGEVF_TQP_REG_SIZE; 408e2cb1decSSalil Mehta 409e2cb1decSSalil Mehta tqp++; 410e2cb1decSSalil Mehta } 411e2cb1decSSalil Mehta 412e2cb1decSSalil Mehta return 0; 413e2cb1decSSalil Mehta } 414e2cb1decSSalil Mehta 415e2cb1decSSalil Mehta static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 416e2cb1decSSalil Mehta { 417e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 418e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo; 419e2cb1decSSalil Mehta u16 new_tqps = hdev->num_tqps; 420ebaf1908SWeihang Li unsigned int i; 421e2cb1decSSalil Mehta 422e2cb1decSSalil Mehta kinfo = &nic->kinfo; 423e2cb1decSSalil Mehta kinfo->num_tc = 0; 424c0425944SPeng Li kinfo->num_tx_desc = hdev->num_tx_desc; 425c0425944SPeng Li kinfo->num_rx_desc = hdev->num_rx_desc; 426e2cb1decSSalil Mehta kinfo->rx_buf_len = hdev->rx_buf_len; 427e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 428e2cb1decSSalil Mehta if (hdev->hw_tc_map & BIT(i)) 429e2cb1decSSalil Mehta kinfo->num_tc++; 430e2cb1decSSalil Mehta 431e2cb1decSSalil Mehta kinfo->rss_size 432e2cb1decSSalil Mehta = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 433e2cb1decSSalil Mehta new_tqps = kinfo->rss_size * kinfo->num_tc; 434e2cb1decSSalil Mehta kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 435e2cb1decSSalil Mehta 436e2cb1decSSalil Mehta kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 437e2cb1decSSalil Mehta sizeof(struct hnae3_queue *), GFP_KERNEL); 438e2cb1decSSalil Mehta if (!kinfo->tqp) 439e2cb1decSSalil Mehta return -ENOMEM; 440e2cb1decSSalil Mehta 441e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 442e2cb1decSSalil Mehta hdev->htqp[i].q.handle = &hdev->nic; 443e2cb1decSSalil Mehta hdev->htqp[i].q.tqp_index = i; 444e2cb1decSSalil Mehta kinfo->tqp[i] = &hdev->htqp[i].q; 445e2cb1decSSalil Mehta } 446e2cb1decSSalil Mehta 447580a05f9SYonglong Liu /* after init the max rss_size and tqps, adjust the default tqp numbers 448580a05f9SYonglong Liu * and rss size with the actual vector numbers 449580a05f9SYonglong Liu */ 450580a05f9SYonglong Liu kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps); 451580a05f9SYonglong Liu kinfo->rss_size = min_t(u16, kinfo->num_tqps / kinfo->num_tc, 452580a05f9SYonglong Liu kinfo->rss_size); 453580a05f9SYonglong Liu 454e2cb1decSSalil Mehta return 0; 455e2cb1decSSalil Mehta } 456e2cb1decSSalil Mehta 457e2cb1decSSalil Mehta static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 458e2cb1decSSalil Mehta { 459d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 460e2cb1decSSalil Mehta int status; 461e2cb1decSSalil Mehta 462d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_STATUS, 0); 463d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 464e2cb1decSSalil Mehta if (status) 465e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 466e2cb1decSSalil Mehta "VF failed to fetch link status(%d) from PF", status); 467e2cb1decSSalil Mehta } 468e2cb1decSSalil Mehta 469e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 470e2cb1decSSalil Mehta { 47145e92b7eSPeng Li struct hnae3_handle *rhandle = &hdev->roce; 472e2cb1decSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 47345e92b7eSPeng Li struct hnae3_client *rclient; 474e2cb1decSSalil Mehta struct hnae3_client *client; 475e2cb1decSSalil Mehta 476ff200099SYunsheng Lin if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state)) 477ff200099SYunsheng Lin return; 478ff200099SYunsheng Lin 479e2cb1decSSalil Mehta client = handle->client; 48045e92b7eSPeng Li rclient = hdev->roce_client; 481e2cb1decSSalil Mehta 482582d37bbSPeng Li link_state = 483582d37bbSPeng Li test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 484582d37bbSPeng Li 485e2cb1decSSalil Mehta if (link_state != hdev->hw.mac.link) { 486e2cb1decSSalil Mehta client->ops->link_status_change(handle, !!link_state); 48745e92b7eSPeng Li if (rclient && rclient->ops->link_status_change) 48845e92b7eSPeng Li rclient->ops->link_status_change(rhandle, !!link_state); 489e2cb1decSSalil Mehta hdev->hw.mac.link = link_state; 490e2cb1decSSalil Mehta } 491ff200099SYunsheng Lin 492ff200099SYunsheng Lin clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state); 493e2cb1decSSalil Mehta } 494e2cb1decSSalil Mehta 495538abaf3SYueHaibing static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 4969194d18bSliuzhongzhu { 4979194d18bSliuzhongzhu #define HCLGEVF_ADVERTISING 0 4989194d18bSliuzhongzhu #define HCLGEVF_SUPPORTED 1 4999194d18bSliuzhongzhu 500d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 501d3410018SYufeng Mo 502d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_MODE, 0); 503d3410018SYufeng Mo send_msg.data[0] = HCLGEVF_ADVERTISING; 504d3410018SYufeng Mo hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 505d3410018SYufeng Mo send_msg.data[0] = HCLGEVF_SUPPORTED; 506d3410018SYufeng Mo hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 5079194d18bSliuzhongzhu } 5089194d18bSliuzhongzhu 509e2cb1decSSalil Mehta static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 510e2cb1decSSalil Mehta { 511e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 512e2cb1decSSalil Mehta int ret; 513e2cb1decSSalil Mehta 514e2cb1decSSalil Mehta nic->ae_algo = &ae_algovf; 515e2cb1decSSalil Mehta nic->pdev = hdev->pdev; 516e2cb1decSSalil Mehta nic->numa_node_mask = hdev->numa_node_mask; 517424eb834SSalil Mehta nic->flags |= HNAE3_SUPPORT_VF; 518e2cb1decSSalil Mehta 519e2cb1decSSalil Mehta ret = hclgevf_knic_setup(hdev); 520e2cb1decSSalil Mehta if (ret) 521e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 522e2cb1decSSalil Mehta ret); 523e2cb1decSSalil Mehta return ret; 524e2cb1decSSalil Mehta } 525e2cb1decSSalil Mehta 526e2cb1decSSalil Mehta static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 527e2cb1decSSalil Mehta { 52836cbbdf6SPeng Li if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 52936cbbdf6SPeng Li dev_warn(&hdev->pdev->dev, 53036cbbdf6SPeng Li "vector(vector_id %d) has been freed.\n", vector_id); 53136cbbdf6SPeng Li return; 53236cbbdf6SPeng Li } 53336cbbdf6SPeng Li 534e2cb1decSSalil Mehta hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 535e2cb1decSSalil Mehta hdev->num_msi_left += 1; 536e2cb1decSSalil Mehta hdev->num_msi_used -= 1; 537e2cb1decSSalil Mehta } 538e2cb1decSSalil Mehta 539e2cb1decSSalil Mehta static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 540e2cb1decSSalil Mehta struct hnae3_vector_info *vector_info) 541e2cb1decSSalil Mehta { 542e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 543e2cb1decSSalil Mehta struct hnae3_vector_info *vector = vector_info; 544e2cb1decSSalil Mehta int alloc = 0; 545e2cb1decSSalil Mehta int i, j; 546e2cb1decSSalil Mehta 547580a05f9SYonglong Liu vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num); 548e2cb1decSSalil Mehta vector_num = min(hdev->num_msi_left, vector_num); 549e2cb1decSSalil Mehta 550e2cb1decSSalil Mehta for (j = 0; j < vector_num; j++) { 551e2cb1decSSalil Mehta for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 552e2cb1decSSalil Mehta if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 553e2cb1decSSalil Mehta vector->vector = pci_irq_vector(hdev->pdev, i); 554e2cb1decSSalil Mehta vector->io_addr = hdev->hw.io_base + 555e2cb1decSSalil Mehta HCLGEVF_VECTOR_REG_BASE + 556e2cb1decSSalil Mehta (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 557e2cb1decSSalil Mehta hdev->vector_status[i] = 0; 558e2cb1decSSalil Mehta hdev->vector_irq[i] = vector->vector; 559e2cb1decSSalil Mehta 560e2cb1decSSalil Mehta vector++; 561e2cb1decSSalil Mehta alloc++; 562e2cb1decSSalil Mehta 563e2cb1decSSalil Mehta break; 564e2cb1decSSalil Mehta } 565e2cb1decSSalil Mehta } 566e2cb1decSSalil Mehta } 567e2cb1decSSalil Mehta hdev->num_msi_left -= alloc; 568e2cb1decSSalil Mehta hdev->num_msi_used += alloc; 569e2cb1decSSalil Mehta 570e2cb1decSSalil Mehta return alloc; 571e2cb1decSSalil Mehta } 572e2cb1decSSalil Mehta 573e2cb1decSSalil Mehta static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 574e2cb1decSSalil Mehta { 575e2cb1decSSalil Mehta int i; 576e2cb1decSSalil Mehta 577e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 578e2cb1decSSalil Mehta if (vector == hdev->vector_irq[i]) 579e2cb1decSSalil Mehta return i; 580e2cb1decSSalil Mehta 581e2cb1decSSalil Mehta return -EINVAL; 582e2cb1decSSalil Mehta } 583e2cb1decSSalil Mehta 584374ad291SJian Shen static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 585374ad291SJian Shen const u8 hfunc, const u8 *key) 586374ad291SJian Shen { 587374ad291SJian Shen struct hclgevf_rss_config_cmd *req; 588ebaf1908SWeihang Li unsigned int key_offset = 0; 589374ad291SJian Shen struct hclgevf_desc desc; 5903caf772bSYufeng Mo int key_counts; 591374ad291SJian Shen int key_size; 592374ad291SJian Shen int ret; 593374ad291SJian Shen 5943caf772bSYufeng Mo key_counts = HCLGEVF_RSS_KEY_SIZE; 595374ad291SJian Shen req = (struct hclgevf_rss_config_cmd *)desc.data; 596374ad291SJian Shen 5973caf772bSYufeng Mo while (key_counts) { 598374ad291SJian Shen hclgevf_cmd_setup_basic_desc(&desc, 599374ad291SJian Shen HCLGEVF_OPC_RSS_GENERIC_CONFIG, 600374ad291SJian Shen false); 601374ad291SJian Shen 602374ad291SJian Shen req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 603374ad291SJian Shen req->hash_config |= 604374ad291SJian Shen (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 605374ad291SJian Shen 6063caf772bSYufeng Mo key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts); 607374ad291SJian Shen memcpy(req->hash_key, 608374ad291SJian Shen key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 609374ad291SJian Shen 6103caf772bSYufeng Mo key_counts -= key_size; 6113caf772bSYufeng Mo key_offset++; 612374ad291SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 613374ad291SJian Shen if (ret) { 614374ad291SJian Shen dev_err(&hdev->pdev->dev, 615374ad291SJian Shen "Configure RSS config fail, status = %d\n", 616374ad291SJian Shen ret); 617374ad291SJian Shen return ret; 618374ad291SJian Shen } 619374ad291SJian Shen } 620374ad291SJian Shen 621374ad291SJian Shen return 0; 622374ad291SJian Shen } 623374ad291SJian Shen 624e2cb1decSSalil Mehta static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 625e2cb1decSSalil Mehta { 626e2cb1decSSalil Mehta return HCLGEVF_RSS_KEY_SIZE; 627e2cb1decSSalil Mehta } 628e2cb1decSSalil Mehta 629e2cb1decSSalil Mehta static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 630e2cb1decSSalil Mehta { 631e2cb1decSSalil Mehta return HCLGEVF_RSS_IND_TBL_SIZE; 632e2cb1decSSalil Mehta } 633e2cb1decSSalil Mehta 634e2cb1decSSalil Mehta static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 635e2cb1decSSalil Mehta { 636e2cb1decSSalil Mehta const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 637e2cb1decSSalil Mehta struct hclgevf_rss_indirection_table_cmd *req; 638e2cb1decSSalil Mehta struct hclgevf_desc desc; 639e2cb1decSSalil Mehta int status; 640e2cb1decSSalil Mehta int i, j; 641e2cb1decSSalil Mehta 642e2cb1decSSalil Mehta req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 643e2cb1decSSalil Mehta 644e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 645e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 646e2cb1decSSalil Mehta false); 647e2cb1decSSalil Mehta req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 648e2cb1decSSalil Mehta req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 649e2cb1decSSalil Mehta for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 650e2cb1decSSalil Mehta req->rss_result[j] = 651e2cb1decSSalil Mehta indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 652e2cb1decSSalil Mehta 653e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 654e2cb1decSSalil Mehta if (status) { 655e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 656e2cb1decSSalil Mehta "VF failed(=%d) to set RSS indirection table\n", 657e2cb1decSSalil Mehta status); 658e2cb1decSSalil Mehta return status; 659e2cb1decSSalil Mehta } 660e2cb1decSSalil Mehta } 661e2cb1decSSalil Mehta 662e2cb1decSSalil Mehta return 0; 663e2cb1decSSalil Mehta } 664e2cb1decSSalil Mehta 665e2cb1decSSalil Mehta static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 666e2cb1decSSalil Mehta { 667e2cb1decSSalil Mehta struct hclgevf_rss_tc_mode_cmd *req; 668e2cb1decSSalil Mehta u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 669e2cb1decSSalil Mehta u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 670e2cb1decSSalil Mehta u16 tc_size[HCLGEVF_MAX_TC_NUM]; 671e2cb1decSSalil Mehta struct hclgevf_desc desc; 672e2cb1decSSalil Mehta u16 roundup_size; 673ebaf1908SWeihang Li unsigned int i; 6742adb8187SHuazhong Tan int status; 675e2cb1decSSalil Mehta 676e2cb1decSSalil Mehta req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 677e2cb1decSSalil Mehta 678e2cb1decSSalil Mehta roundup_size = roundup_pow_of_two(rss_size); 679e2cb1decSSalil Mehta roundup_size = ilog2(roundup_size); 680e2cb1decSSalil Mehta 681e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 682e2cb1decSSalil Mehta tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 683e2cb1decSSalil Mehta tc_size[i] = roundup_size; 684e2cb1decSSalil Mehta tc_offset[i] = rss_size * i; 685e2cb1decSSalil Mehta } 686e2cb1decSSalil Mehta 687e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 688e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 689e4e87715SPeng Li hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 690e2cb1decSSalil Mehta (tc_valid[i] & 0x1)); 691e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 692e2cb1decSSalil Mehta HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 693e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 694e2cb1decSSalil Mehta HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 695e2cb1decSSalil Mehta } 696e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 697e2cb1decSSalil Mehta if (status) 698e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 699e2cb1decSSalil Mehta "VF failed(=%d) to set rss tc mode\n", status); 700e2cb1decSSalil Mehta 701e2cb1decSSalil Mehta return status; 702e2cb1decSSalil Mehta } 703e2cb1decSSalil Mehta 704a638b1d8SJian Shen /* for revision 0x20, vf shared the same rss config with pf */ 705a638b1d8SJian Shen static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 706a638b1d8SJian Shen { 707a638b1d8SJian Shen #define HCLGEVF_RSS_MBX_RESP_LEN 8 708a638b1d8SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 709a638b1d8SJian Shen u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 710d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 711a638b1d8SJian Shen u16 msg_num, hash_key_index; 712a638b1d8SJian Shen u8 index; 713a638b1d8SJian Shen int ret; 714a638b1d8SJian Shen 715d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_RSS_KEY, 0); 716a638b1d8SJian Shen msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 717a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN; 718a638b1d8SJian Shen for (index = 0; index < msg_num; index++) { 719d3410018SYufeng Mo send_msg.data[0] = index; 720d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 721a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN); 722a638b1d8SJian Shen if (ret) { 723a638b1d8SJian Shen dev_err(&hdev->pdev->dev, 724a638b1d8SJian Shen "VF get rss hash key from PF failed, ret=%d", 725a638b1d8SJian Shen ret); 726a638b1d8SJian Shen return ret; 727a638b1d8SJian Shen } 728a638b1d8SJian Shen 729a638b1d8SJian Shen hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 730a638b1d8SJian Shen if (index == msg_num - 1) 731a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 732a638b1d8SJian Shen &resp_msg[0], 733a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE - hash_key_index); 734a638b1d8SJian Shen else 735a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 736a638b1d8SJian Shen &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 737a638b1d8SJian Shen } 738a638b1d8SJian Shen 739a638b1d8SJian Shen return 0; 740a638b1d8SJian Shen } 741a638b1d8SJian Shen 742e2cb1decSSalil Mehta static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 743e2cb1decSSalil Mehta u8 *hfunc) 744e2cb1decSSalil Mehta { 745e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 746e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 747a638b1d8SJian Shen int i, ret; 748e2cb1decSSalil Mehta 749295ba232SGuangbin Huang if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 750374ad291SJian Shen /* Get hash algorithm */ 751374ad291SJian Shen if (hfunc) { 752374ad291SJian Shen switch (rss_cfg->hash_algo) { 753374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 754374ad291SJian Shen *hfunc = ETH_RSS_HASH_TOP; 755374ad291SJian Shen break; 756374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 757374ad291SJian Shen *hfunc = ETH_RSS_HASH_XOR; 758374ad291SJian Shen break; 759374ad291SJian Shen default: 760374ad291SJian Shen *hfunc = ETH_RSS_HASH_UNKNOWN; 761374ad291SJian Shen break; 762374ad291SJian Shen } 763374ad291SJian Shen } 764374ad291SJian Shen 765374ad291SJian Shen /* Get the RSS Key required by the user */ 766374ad291SJian Shen if (key) 767374ad291SJian Shen memcpy(key, rss_cfg->rss_hash_key, 768374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 769a638b1d8SJian Shen } else { 770a638b1d8SJian Shen if (hfunc) 771a638b1d8SJian Shen *hfunc = ETH_RSS_HASH_TOP; 772a638b1d8SJian Shen if (key) { 773a638b1d8SJian Shen ret = hclgevf_get_rss_hash_key(hdev); 774a638b1d8SJian Shen if (ret) 775a638b1d8SJian Shen return ret; 776a638b1d8SJian Shen memcpy(key, rss_cfg->rss_hash_key, 777a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE); 778a638b1d8SJian Shen } 779374ad291SJian Shen } 780374ad291SJian Shen 781e2cb1decSSalil Mehta if (indir) 782e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 783e2cb1decSSalil Mehta indir[i] = rss_cfg->rss_indirection_tbl[i]; 784e2cb1decSSalil Mehta 785374ad291SJian Shen return 0; 786e2cb1decSSalil Mehta } 787e2cb1decSSalil Mehta 788e2cb1decSSalil Mehta static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 789e2cb1decSSalil Mehta const u8 *key, const u8 hfunc) 790e2cb1decSSalil Mehta { 791e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 792e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 793374ad291SJian Shen int ret, i; 794374ad291SJian Shen 795295ba232SGuangbin Huang if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 796374ad291SJian Shen /* Set the RSS Hash Key if specififed by the user */ 797374ad291SJian Shen if (key) { 798374ad291SJian Shen switch (hfunc) { 799374ad291SJian Shen case ETH_RSS_HASH_TOP: 800374ad291SJian Shen rss_cfg->hash_algo = 801374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 802374ad291SJian Shen break; 803374ad291SJian Shen case ETH_RSS_HASH_XOR: 804374ad291SJian Shen rss_cfg->hash_algo = 805374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_SIMPLE; 806374ad291SJian Shen break; 807374ad291SJian Shen case ETH_RSS_HASH_NO_CHANGE: 808374ad291SJian Shen break; 809374ad291SJian Shen default: 810374ad291SJian Shen return -EINVAL; 811374ad291SJian Shen } 812374ad291SJian Shen 813374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 814374ad291SJian Shen key); 815374ad291SJian Shen if (ret) 816374ad291SJian Shen return ret; 817374ad291SJian Shen 818374ad291SJian Shen /* Update the shadow RSS key with user specified qids */ 819374ad291SJian Shen memcpy(rss_cfg->rss_hash_key, key, 820374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 821374ad291SJian Shen } 822374ad291SJian Shen } 823e2cb1decSSalil Mehta 824e2cb1decSSalil Mehta /* update the shadow RSS table with user specified qids */ 825e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 826e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = indir[i]; 827e2cb1decSSalil Mehta 828e2cb1decSSalil Mehta /* update the hardware */ 829e2cb1decSSalil Mehta return hclgevf_set_rss_indir_table(hdev); 830e2cb1decSSalil Mehta } 831e2cb1decSSalil Mehta 832d97b3072SJian Shen static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 833d97b3072SJian Shen { 834d97b3072SJian Shen u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 835d97b3072SJian Shen 836d97b3072SJian Shen if (nfc->data & RXH_L4_B_2_3) 837d97b3072SJian Shen hash_sets |= HCLGEVF_D_PORT_BIT; 838d97b3072SJian Shen else 839d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_PORT_BIT; 840d97b3072SJian Shen 841d97b3072SJian Shen if (nfc->data & RXH_IP_SRC) 842d97b3072SJian Shen hash_sets |= HCLGEVF_S_IP_BIT; 843d97b3072SJian Shen else 844d97b3072SJian Shen hash_sets &= ~HCLGEVF_S_IP_BIT; 845d97b3072SJian Shen 846d97b3072SJian Shen if (nfc->data & RXH_IP_DST) 847d97b3072SJian Shen hash_sets |= HCLGEVF_D_IP_BIT; 848d97b3072SJian Shen else 849d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_IP_BIT; 850d97b3072SJian Shen 851d97b3072SJian Shen if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 852d97b3072SJian Shen hash_sets |= HCLGEVF_V_TAG_BIT; 853d97b3072SJian Shen 854d97b3072SJian Shen return hash_sets; 855d97b3072SJian Shen } 856d97b3072SJian Shen 857d97b3072SJian Shen static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 858d97b3072SJian Shen struct ethtool_rxnfc *nfc) 859d97b3072SJian Shen { 860d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 861d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 862d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 863d97b3072SJian Shen struct hclgevf_desc desc; 864d97b3072SJian Shen u8 tuple_sets; 865d97b3072SJian Shen int ret; 866d97b3072SJian Shen 867295ba232SGuangbin Huang if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 868d97b3072SJian Shen return -EOPNOTSUPP; 869d97b3072SJian Shen 870d97b3072SJian Shen if (nfc->data & 871d97b3072SJian Shen ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 872d97b3072SJian Shen return -EINVAL; 873d97b3072SJian Shen 874d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 875d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 876d97b3072SJian Shen 877d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 878d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 879d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 880d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 881d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 882d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 883d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 884d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 885d97b3072SJian Shen 886d97b3072SJian Shen tuple_sets = hclgevf_get_rss_hash_bits(nfc); 887d97b3072SJian Shen switch (nfc->flow_type) { 888d97b3072SJian Shen case TCP_V4_FLOW: 889d97b3072SJian Shen req->ipv4_tcp_en = tuple_sets; 890d97b3072SJian Shen break; 891d97b3072SJian Shen case TCP_V6_FLOW: 892d97b3072SJian Shen req->ipv6_tcp_en = tuple_sets; 893d97b3072SJian Shen break; 894d97b3072SJian Shen case UDP_V4_FLOW: 895d97b3072SJian Shen req->ipv4_udp_en = tuple_sets; 896d97b3072SJian Shen break; 897d97b3072SJian Shen case UDP_V6_FLOW: 898d97b3072SJian Shen req->ipv6_udp_en = tuple_sets; 899d97b3072SJian Shen break; 900d97b3072SJian Shen case SCTP_V4_FLOW: 901d97b3072SJian Shen req->ipv4_sctp_en = tuple_sets; 902d97b3072SJian Shen break; 903d97b3072SJian Shen case SCTP_V6_FLOW: 904d97b3072SJian Shen if ((nfc->data & RXH_L4_B_0_1) || 905d97b3072SJian Shen (nfc->data & RXH_L4_B_2_3)) 906d97b3072SJian Shen return -EINVAL; 907d97b3072SJian Shen 908d97b3072SJian Shen req->ipv6_sctp_en = tuple_sets; 909d97b3072SJian Shen break; 910d97b3072SJian Shen case IPV4_FLOW: 911d97b3072SJian Shen req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 912d97b3072SJian Shen break; 913d97b3072SJian Shen case IPV6_FLOW: 914d97b3072SJian Shen req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 915d97b3072SJian Shen break; 916d97b3072SJian Shen default: 917d97b3072SJian Shen return -EINVAL; 918d97b3072SJian Shen } 919d97b3072SJian Shen 920d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 921d97b3072SJian Shen if (ret) { 922d97b3072SJian Shen dev_err(&hdev->pdev->dev, 923d97b3072SJian Shen "Set rss tuple fail, status = %d\n", ret); 924d97b3072SJian Shen return ret; 925d97b3072SJian Shen } 926d97b3072SJian Shen 927d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 928d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 929d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 930d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 931d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 932d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 933d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 934d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 935d97b3072SJian Shen return 0; 936d97b3072SJian Shen } 937d97b3072SJian Shen 938d97b3072SJian Shen static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 939d97b3072SJian Shen struct ethtool_rxnfc *nfc) 940d97b3072SJian Shen { 941d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 942d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 943d97b3072SJian Shen u8 tuple_sets; 944d97b3072SJian Shen 945295ba232SGuangbin Huang if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 946d97b3072SJian Shen return -EOPNOTSUPP; 947d97b3072SJian Shen 948d97b3072SJian Shen nfc->data = 0; 949d97b3072SJian Shen 950d97b3072SJian Shen switch (nfc->flow_type) { 951d97b3072SJian Shen case TCP_V4_FLOW: 952d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 953d97b3072SJian Shen break; 954d97b3072SJian Shen case UDP_V4_FLOW: 955d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 956d97b3072SJian Shen break; 957d97b3072SJian Shen case TCP_V6_FLOW: 958d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 959d97b3072SJian Shen break; 960d97b3072SJian Shen case UDP_V6_FLOW: 961d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 962d97b3072SJian Shen break; 963d97b3072SJian Shen case SCTP_V4_FLOW: 964d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 965d97b3072SJian Shen break; 966d97b3072SJian Shen case SCTP_V6_FLOW: 967d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 968d97b3072SJian Shen break; 969d97b3072SJian Shen case IPV4_FLOW: 970d97b3072SJian Shen case IPV6_FLOW: 971d97b3072SJian Shen tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 972d97b3072SJian Shen break; 973d97b3072SJian Shen default: 974d97b3072SJian Shen return -EINVAL; 975d97b3072SJian Shen } 976d97b3072SJian Shen 977d97b3072SJian Shen if (!tuple_sets) 978d97b3072SJian Shen return 0; 979d97b3072SJian Shen 980d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_PORT_BIT) 981d97b3072SJian Shen nfc->data |= RXH_L4_B_2_3; 982d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_PORT_BIT) 983d97b3072SJian Shen nfc->data |= RXH_L4_B_0_1; 984d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_IP_BIT) 985d97b3072SJian Shen nfc->data |= RXH_IP_DST; 986d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_IP_BIT) 987d97b3072SJian Shen nfc->data |= RXH_IP_SRC; 988d97b3072SJian Shen 989d97b3072SJian Shen return 0; 990d97b3072SJian Shen } 991d97b3072SJian Shen 992d97b3072SJian Shen static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 993d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg) 994d97b3072SJian Shen { 995d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 996d97b3072SJian Shen struct hclgevf_desc desc; 997d97b3072SJian Shen int ret; 998d97b3072SJian Shen 999d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 1000d97b3072SJian Shen 1001d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 1002d97b3072SJian Shen 1003d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 1004d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 1005d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 1006d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 1007d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 1008d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 1009d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 1010d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 1011d97b3072SJian Shen 1012d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1013d97b3072SJian Shen if (ret) 1014d97b3072SJian Shen dev_err(&hdev->pdev->dev, 1015d97b3072SJian Shen "Configure rss input fail, status = %d\n", ret); 1016d97b3072SJian Shen return ret; 1017d97b3072SJian Shen } 1018d97b3072SJian Shen 1019e2cb1decSSalil Mehta static int hclgevf_get_tc_size(struct hnae3_handle *handle) 1020e2cb1decSSalil Mehta { 1021e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1022e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1023e2cb1decSSalil Mehta 1024e2cb1decSSalil Mehta return rss_cfg->rss_size; 1025e2cb1decSSalil Mehta } 1026e2cb1decSSalil Mehta 1027e2cb1decSSalil Mehta static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 1028b204bc74SPeng Li int vector_id, 1029e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1030e2cb1decSSalil Mehta { 1031e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1032d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1033e2cb1decSSalil Mehta struct hnae3_ring_chain_node *node; 1034e2cb1decSSalil Mehta int status; 1035d3410018SYufeng Mo int i = 0; 1036e2cb1decSSalil Mehta 1037d3410018SYufeng Mo memset(&send_msg, 0, sizeof(send_msg)); 1038d3410018SYufeng Mo send_msg.code = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 1039c09ba484SPeng Li HCLGE_MBX_UNMAP_RING_TO_VECTOR; 1040d3410018SYufeng Mo send_msg.vector_id = vector_id; 1041e2cb1decSSalil Mehta 1042e2cb1decSSalil Mehta for (node = ring_chain; node; node = node->next) { 1043d3410018SYufeng Mo send_msg.param[i].ring_type = 1044e4e87715SPeng Li hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 1045d3410018SYufeng Mo 1046d3410018SYufeng Mo send_msg.param[i].tqp_index = node->tqp_index; 1047d3410018SYufeng Mo send_msg.param[i].int_gl_index = 1048d3410018SYufeng Mo hnae3_get_field(node->int_gl_idx, 104979eee410SFuyun Liang HNAE3_RING_GL_IDX_M, 105079eee410SFuyun Liang HNAE3_RING_GL_IDX_S); 105179eee410SFuyun Liang 10525d02a58dSYunsheng Lin i++; 1053d3410018SYufeng Mo if (i == HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM || !node->next) { 1054d3410018SYufeng Mo send_msg.ring_num = i; 1055e2cb1decSSalil Mehta 1056d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, false, 1057d3410018SYufeng Mo NULL, 0); 1058e2cb1decSSalil Mehta if (status) { 1059e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1060e2cb1decSSalil Mehta "Map TQP fail, status is %d.\n", 1061e2cb1decSSalil Mehta status); 1062e2cb1decSSalil Mehta return status; 1063e2cb1decSSalil Mehta } 1064e2cb1decSSalil Mehta i = 0; 1065e2cb1decSSalil Mehta } 1066e2cb1decSSalil Mehta } 1067e2cb1decSSalil Mehta 1068e2cb1decSSalil Mehta return 0; 1069e2cb1decSSalil Mehta } 1070e2cb1decSSalil Mehta 1071e2cb1decSSalil Mehta static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1072e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1073e2cb1decSSalil Mehta { 1074b204bc74SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1075b204bc74SPeng Li int vector_id; 1076b204bc74SPeng Li 1077b204bc74SPeng Li vector_id = hclgevf_get_vector_index(hdev, vector); 1078b204bc74SPeng Li if (vector_id < 0) { 1079b204bc74SPeng Li dev_err(&handle->pdev->dev, 1080b204bc74SPeng Li "Get vector index fail. ret =%d\n", vector_id); 1081b204bc74SPeng Li return vector_id; 1082b204bc74SPeng Li } 1083b204bc74SPeng Li 1084b204bc74SPeng Li return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1085e2cb1decSSalil Mehta } 1086e2cb1decSSalil Mehta 1087e2cb1decSSalil Mehta static int hclgevf_unmap_ring_from_vector( 1088e2cb1decSSalil Mehta struct hnae3_handle *handle, 1089e2cb1decSSalil Mehta int vector, 1090e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1091e2cb1decSSalil Mehta { 1092e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1093e2cb1decSSalil Mehta int ret, vector_id; 1094e2cb1decSSalil Mehta 1095dea846e8SHuazhong Tan if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1096dea846e8SHuazhong Tan return 0; 1097dea846e8SHuazhong Tan 1098e2cb1decSSalil Mehta vector_id = hclgevf_get_vector_index(hdev, vector); 1099e2cb1decSSalil Mehta if (vector_id < 0) { 1100e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1101e2cb1decSSalil Mehta "Get vector index fail. ret =%d\n", vector_id); 1102e2cb1decSSalil Mehta return vector_id; 1103e2cb1decSSalil Mehta } 1104e2cb1decSSalil Mehta 1105b204bc74SPeng Li ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 11060d3e6631SYunsheng Lin if (ret) 1107e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1108e2cb1decSSalil Mehta "Unmap ring from vector fail. vector=%d, ret =%d\n", 1109e2cb1decSSalil Mehta vector_id, 1110e2cb1decSSalil Mehta ret); 11110d3e6631SYunsheng Lin 1112e2cb1decSSalil Mehta return ret; 1113e2cb1decSSalil Mehta } 1114e2cb1decSSalil Mehta 11150d3e6631SYunsheng Lin static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 11160d3e6631SYunsheng Lin { 11170d3e6631SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 111803718db9SYunsheng Lin int vector_id; 11190d3e6631SYunsheng Lin 112003718db9SYunsheng Lin vector_id = hclgevf_get_vector_index(hdev, vector); 112103718db9SYunsheng Lin if (vector_id < 0) { 112203718db9SYunsheng Lin dev_err(&handle->pdev->dev, 112303718db9SYunsheng Lin "hclgevf_put_vector get vector index fail. ret =%d\n", 112403718db9SYunsheng Lin vector_id); 112503718db9SYunsheng Lin return vector_id; 112603718db9SYunsheng Lin } 112703718db9SYunsheng Lin 112803718db9SYunsheng Lin hclgevf_free_vector(hdev, vector_id); 1129e2cb1decSSalil Mehta 1130e2cb1decSSalil Mehta return 0; 1131e2cb1decSSalil Mehta } 1132e2cb1decSSalil Mehta 11333b75c3dfSPeng Li static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1134e196ec75SJian Shen bool en_uc_pmc, bool en_mc_pmc, 1135f01f5559SJian Shen bool en_bc_pmc) 1136e2cb1decSSalil Mehta { 1137d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1138f01f5559SJian Shen int ret; 1139e2cb1decSSalil Mehta 1140d3410018SYufeng Mo memset(&send_msg, 0, sizeof(send_msg)); 1141d3410018SYufeng Mo send_msg.code = HCLGE_MBX_SET_PROMISC_MODE; 1142d3410018SYufeng Mo send_msg.en_bc = en_bc_pmc ? 1 : 0; 1143d3410018SYufeng Mo send_msg.en_uc = en_uc_pmc ? 1 : 0; 1144d3410018SYufeng Mo send_msg.en_mc = en_mc_pmc ? 1 : 0; 1145e2cb1decSSalil Mehta 1146d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1147f01f5559SJian Shen if (ret) 1148e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1149f01f5559SJian Shen "Set promisc mode fail, status is %d.\n", ret); 1150e2cb1decSSalil Mehta 1151f01f5559SJian Shen return ret; 1152e2cb1decSSalil Mehta } 1153e2cb1decSSalil Mehta 1154e196ec75SJian Shen static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 1155e196ec75SJian Shen bool en_mc_pmc) 1156e2cb1decSSalil Mehta { 1157e196ec75SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1158e196ec75SJian Shen bool en_bc_pmc; 1159e196ec75SJian Shen 1160295ba232SGuangbin Huang en_bc_pmc = hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2; 1161e196ec75SJian Shen 1162e196ec75SJian Shen return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc, 1163e196ec75SJian Shen en_bc_pmc); 1164e2cb1decSSalil Mehta } 1165e2cb1decSSalil Mehta 1166c631c696SJian Shen static void hclgevf_request_update_promisc_mode(struct hnae3_handle *handle) 1167c631c696SJian Shen { 1168c631c696SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1169c631c696SJian Shen 1170c631c696SJian Shen set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 1171c631c696SJian Shen } 1172c631c696SJian Shen 1173c631c696SJian Shen static void hclgevf_sync_promisc_mode(struct hclgevf_dev *hdev) 1174c631c696SJian Shen { 1175c631c696SJian Shen struct hnae3_handle *handle = &hdev->nic; 1176c631c696SJian Shen bool en_uc_pmc = handle->netdev_flags & HNAE3_UPE; 1177c631c696SJian Shen bool en_mc_pmc = handle->netdev_flags & HNAE3_MPE; 1178c631c696SJian Shen int ret; 1179c631c696SJian Shen 1180c631c696SJian Shen if (test_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state)) { 1181c631c696SJian Shen ret = hclgevf_set_promisc_mode(handle, en_uc_pmc, en_mc_pmc); 1182c631c696SJian Shen if (!ret) 1183c631c696SJian Shen clear_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 1184c631c696SJian Shen } 1185c631c696SJian Shen } 1186c631c696SJian Shen 1187ebaf1908SWeihang Li static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, unsigned int tqp_id, 1188e2cb1decSSalil Mehta int stream_id, bool enable) 1189e2cb1decSSalil Mehta { 1190e2cb1decSSalil Mehta struct hclgevf_cfg_com_tqp_queue_cmd *req; 1191e2cb1decSSalil Mehta struct hclgevf_desc desc; 1192e2cb1decSSalil Mehta int status; 1193e2cb1decSSalil Mehta 1194e2cb1decSSalil Mehta req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1195e2cb1decSSalil Mehta 1196e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1197e2cb1decSSalil Mehta false); 1198e2cb1decSSalil Mehta req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1199e2cb1decSSalil Mehta req->stream_id = cpu_to_le16(stream_id); 1200ebaf1908SWeihang Li if (enable) 1201ebaf1908SWeihang Li req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 1202e2cb1decSSalil Mehta 1203e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1204e2cb1decSSalil Mehta if (status) 1205e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1206e2cb1decSSalil Mehta "TQP enable fail, status =%d.\n", status); 1207e2cb1decSSalil Mehta 1208e2cb1decSSalil Mehta return status; 1209e2cb1decSSalil Mehta } 1210e2cb1decSSalil Mehta 1211e2cb1decSSalil Mehta static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1212e2cb1decSSalil Mehta { 1213b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1214e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 1215e2cb1decSSalil Mehta int i; 1216e2cb1decSSalil Mehta 1217b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 1218b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1219e2cb1decSSalil Mehta memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1220e2cb1decSSalil Mehta } 1221e2cb1decSSalil Mehta } 1222e2cb1decSSalil Mehta 12238e6de441SHuazhong Tan static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p) 12248e6de441SHuazhong Tan { 1225d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 12268e6de441SHuazhong Tan u8 host_mac[ETH_ALEN]; 12278e6de441SHuazhong Tan int status; 12288e6de441SHuazhong Tan 1229d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MAC_ADDR, 0); 1230d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, true, host_mac, 1231d3410018SYufeng Mo ETH_ALEN); 12328e6de441SHuazhong Tan if (status) { 12338e6de441SHuazhong Tan dev_err(&hdev->pdev->dev, 12348e6de441SHuazhong Tan "fail to get VF MAC from host %d", status); 12358e6de441SHuazhong Tan return status; 12368e6de441SHuazhong Tan } 12378e6de441SHuazhong Tan 12388e6de441SHuazhong Tan ether_addr_copy(p, host_mac); 12398e6de441SHuazhong Tan 12408e6de441SHuazhong Tan return 0; 12418e6de441SHuazhong Tan } 12428e6de441SHuazhong Tan 1243e2cb1decSSalil Mehta static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1244e2cb1decSSalil Mehta { 1245e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 12468e6de441SHuazhong Tan u8 host_mac_addr[ETH_ALEN]; 1247e2cb1decSSalil Mehta 12488e6de441SHuazhong Tan if (hclgevf_get_host_mac_addr(hdev, host_mac_addr)) 12498e6de441SHuazhong Tan return; 12508e6de441SHuazhong Tan 12518e6de441SHuazhong Tan hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr); 12528e6de441SHuazhong Tan if (hdev->has_pf_mac) 12538e6de441SHuazhong Tan ether_addr_copy(p, host_mac_addr); 12548e6de441SHuazhong Tan else 1255e2cb1decSSalil Mehta ether_addr_copy(p, hdev->hw.mac.mac_addr); 1256e2cb1decSSalil Mehta } 1257e2cb1decSSalil Mehta 125859098055SFuyun Liang static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 125959098055SFuyun Liang bool is_first) 1260e2cb1decSSalil Mehta { 1261e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1262e2cb1decSSalil Mehta u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1263d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1264e2cb1decSSalil Mehta u8 *new_mac_addr = (u8 *)p; 1265e2cb1decSSalil Mehta int status; 1266e2cb1decSSalil Mehta 1267d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 0); 1268ee4bcd3bSJian Shen send_msg.subcode = HCLGE_MBX_MAC_VLAN_UC_MODIFY; 1269d3410018SYufeng Mo ether_addr_copy(send_msg.data, new_mac_addr); 1270ee4bcd3bSJian Shen if (is_first && !hdev->has_pf_mac) 1271ee4bcd3bSJian Shen eth_zero_addr(&send_msg.data[ETH_ALEN]); 1272ee4bcd3bSJian Shen else 1273d3410018SYufeng Mo ether_addr_copy(&send_msg.data[ETH_ALEN], old_mac_addr); 1274d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1275e2cb1decSSalil Mehta if (!status) 1276e2cb1decSSalil Mehta ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1277e2cb1decSSalil Mehta 1278e2cb1decSSalil Mehta return status; 1279e2cb1decSSalil Mehta } 1280e2cb1decSSalil Mehta 1281ee4bcd3bSJian Shen static struct hclgevf_mac_addr_node * 1282ee4bcd3bSJian Shen hclgevf_find_mac_node(struct list_head *list, const u8 *mac_addr) 1283ee4bcd3bSJian Shen { 1284ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp; 1285ee4bcd3bSJian Shen 1286ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, list, node) 1287ee4bcd3bSJian Shen if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 1288ee4bcd3bSJian Shen return mac_node; 1289ee4bcd3bSJian Shen 1290ee4bcd3bSJian Shen return NULL; 1291ee4bcd3bSJian Shen } 1292ee4bcd3bSJian Shen 1293ee4bcd3bSJian Shen static void hclgevf_update_mac_node(struct hclgevf_mac_addr_node *mac_node, 1294ee4bcd3bSJian Shen enum HCLGEVF_MAC_NODE_STATE state) 1295ee4bcd3bSJian Shen { 1296ee4bcd3bSJian Shen switch (state) { 1297ee4bcd3bSJian Shen /* from set_rx_mode or tmp_add_list */ 1298ee4bcd3bSJian Shen case HCLGEVF_MAC_TO_ADD: 1299ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_DEL) 1300ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_ACTIVE; 1301ee4bcd3bSJian Shen break; 1302ee4bcd3bSJian Shen /* only from set_rx_mode */ 1303ee4bcd3bSJian Shen case HCLGEVF_MAC_TO_DEL: 1304ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1305ee4bcd3bSJian Shen list_del(&mac_node->node); 1306ee4bcd3bSJian Shen kfree(mac_node); 1307ee4bcd3bSJian Shen } else { 1308ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_TO_DEL; 1309ee4bcd3bSJian Shen } 1310ee4bcd3bSJian Shen break; 1311ee4bcd3bSJian Shen /* only from tmp_add_list, the mac_node->state won't be 1312ee4bcd3bSJian Shen * HCLGEVF_MAC_ACTIVE 1313ee4bcd3bSJian Shen */ 1314ee4bcd3bSJian Shen case HCLGEVF_MAC_ACTIVE: 1315ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1316ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_ACTIVE; 1317ee4bcd3bSJian Shen break; 1318ee4bcd3bSJian Shen } 1319ee4bcd3bSJian Shen } 1320ee4bcd3bSJian Shen 1321ee4bcd3bSJian Shen static int hclgevf_update_mac_list(struct hnae3_handle *handle, 1322ee4bcd3bSJian Shen enum HCLGEVF_MAC_NODE_STATE state, 1323ee4bcd3bSJian Shen enum HCLGEVF_MAC_ADDR_TYPE mac_type, 1324e2cb1decSSalil Mehta const unsigned char *addr) 1325e2cb1decSSalil Mehta { 1326e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1327ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node; 1328ee4bcd3bSJian Shen struct list_head *list; 1329e2cb1decSSalil Mehta 1330ee4bcd3bSJian Shen list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1331ee4bcd3bSJian Shen &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1332ee4bcd3bSJian Shen 1333ee4bcd3bSJian Shen spin_lock_bh(&hdev->mac_table.mac_list_lock); 1334ee4bcd3bSJian Shen 1335ee4bcd3bSJian Shen /* if the mac addr is already in the mac list, no need to add a new 1336ee4bcd3bSJian Shen * one into it, just check the mac addr state, convert it to a new 1337ee4bcd3bSJian Shen * new state, or just remove it, or do nothing. 1338ee4bcd3bSJian Shen */ 1339ee4bcd3bSJian Shen mac_node = hclgevf_find_mac_node(list, addr); 1340ee4bcd3bSJian Shen if (mac_node) { 1341ee4bcd3bSJian Shen hclgevf_update_mac_node(mac_node, state); 1342ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1343ee4bcd3bSJian Shen return 0; 1344ee4bcd3bSJian Shen } 1345ee4bcd3bSJian Shen /* if this address is never added, unnecessary to delete */ 1346ee4bcd3bSJian Shen if (state == HCLGEVF_MAC_TO_DEL) { 1347ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1348ee4bcd3bSJian Shen return -ENOENT; 1349ee4bcd3bSJian Shen } 1350ee4bcd3bSJian Shen 1351ee4bcd3bSJian Shen mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 1352ee4bcd3bSJian Shen if (!mac_node) { 1353ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1354ee4bcd3bSJian Shen return -ENOMEM; 1355ee4bcd3bSJian Shen } 1356ee4bcd3bSJian Shen 1357ee4bcd3bSJian Shen mac_node->state = state; 1358ee4bcd3bSJian Shen ether_addr_copy(mac_node->mac_addr, addr); 1359ee4bcd3bSJian Shen list_add_tail(&mac_node->node, list); 1360ee4bcd3bSJian Shen 1361ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1362ee4bcd3bSJian Shen return 0; 1363ee4bcd3bSJian Shen } 1364ee4bcd3bSJian Shen 1365ee4bcd3bSJian Shen static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1366ee4bcd3bSJian Shen const unsigned char *addr) 1367ee4bcd3bSJian Shen { 1368ee4bcd3bSJian Shen return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1369ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_UC, addr); 1370e2cb1decSSalil Mehta } 1371e2cb1decSSalil Mehta 1372e2cb1decSSalil Mehta static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1373e2cb1decSSalil Mehta const unsigned char *addr) 1374e2cb1decSSalil Mehta { 1375ee4bcd3bSJian Shen return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1376ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_UC, addr); 1377e2cb1decSSalil Mehta } 1378e2cb1decSSalil Mehta 1379e2cb1decSSalil Mehta static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1380e2cb1decSSalil Mehta const unsigned char *addr) 1381e2cb1decSSalil Mehta { 1382ee4bcd3bSJian Shen return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1383ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_MC, addr); 1384e2cb1decSSalil Mehta } 1385e2cb1decSSalil Mehta 1386e2cb1decSSalil Mehta static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1387e2cb1decSSalil Mehta const unsigned char *addr) 1388e2cb1decSSalil Mehta { 1389ee4bcd3bSJian Shen return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1390ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_MC, addr); 1391ee4bcd3bSJian Shen } 1392e2cb1decSSalil Mehta 1393ee4bcd3bSJian Shen static int hclgevf_add_del_mac_addr(struct hclgevf_dev *hdev, 1394ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, 1395ee4bcd3bSJian Shen enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1396ee4bcd3bSJian Shen { 1397ee4bcd3bSJian Shen struct hclge_vf_to_pf_msg send_msg; 1398ee4bcd3bSJian Shen u8 code, subcode; 1399ee4bcd3bSJian Shen 1400ee4bcd3bSJian Shen if (mac_type == HCLGEVF_MAC_ADDR_UC) { 1401ee4bcd3bSJian Shen code = HCLGE_MBX_SET_UNICAST; 1402ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1403ee4bcd3bSJian Shen subcode = HCLGE_MBX_MAC_VLAN_UC_ADD; 1404ee4bcd3bSJian Shen else 1405ee4bcd3bSJian Shen subcode = HCLGE_MBX_MAC_VLAN_UC_REMOVE; 1406ee4bcd3bSJian Shen } else { 1407ee4bcd3bSJian Shen code = HCLGE_MBX_SET_MULTICAST; 1408ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1409ee4bcd3bSJian Shen subcode = HCLGE_MBX_MAC_VLAN_MC_ADD; 1410ee4bcd3bSJian Shen else 1411ee4bcd3bSJian Shen subcode = HCLGE_MBX_MAC_VLAN_MC_REMOVE; 1412ee4bcd3bSJian Shen } 1413ee4bcd3bSJian Shen 1414ee4bcd3bSJian Shen hclgevf_build_send_msg(&send_msg, code, subcode); 1415ee4bcd3bSJian Shen ether_addr_copy(send_msg.data, mac_node->mac_addr); 1416d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1417e2cb1decSSalil Mehta } 1418e2cb1decSSalil Mehta 1419ee4bcd3bSJian Shen static void hclgevf_config_mac_list(struct hclgevf_dev *hdev, 1420ee4bcd3bSJian Shen struct list_head *list, 1421ee4bcd3bSJian Shen enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1422ee4bcd3bSJian Shen { 1423ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp; 1424ee4bcd3bSJian Shen int ret; 1425ee4bcd3bSJian Shen 1426ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, list, node) { 1427ee4bcd3bSJian Shen ret = hclgevf_add_del_mac_addr(hdev, mac_node, mac_type); 1428ee4bcd3bSJian Shen if (ret) { 1429ee4bcd3bSJian Shen dev_err(&hdev->pdev->dev, 1430ee4bcd3bSJian Shen "failed to configure mac %pM, state = %d, ret = %d\n", 1431ee4bcd3bSJian Shen mac_node->mac_addr, mac_node->state, ret); 1432ee4bcd3bSJian Shen return; 1433ee4bcd3bSJian Shen } 1434ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1435ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_ACTIVE; 1436ee4bcd3bSJian Shen } else { 1437ee4bcd3bSJian Shen list_del(&mac_node->node); 1438ee4bcd3bSJian Shen kfree(mac_node); 1439ee4bcd3bSJian Shen } 1440ee4bcd3bSJian Shen } 1441ee4bcd3bSJian Shen } 1442ee4bcd3bSJian Shen 1443ee4bcd3bSJian Shen static void hclgevf_sync_from_add_list(struct list_head *add_list, 1444ee4bcd3bSJian Shen struct list_head *mac_list) 1445ee4bcd3bSJian Shen { 1446ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1447ee4bcd3bSJian Shen 1448ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, add_list, node) { 1449ee4bcd3bSJian Shen /* if the mac address from tmp_add_list is not in the 1450ee4bcd3bSJian Shen * uc/mc_mac_list, it means have received a TO_DEL request 1451ee4bcd3bSJian Shen * during the time window of sending mac config request to PF 1452ee4bcd3bSJian Shen * If mac_node state is ACTIVE, then change its state to TO_DEL, 1453ee4bcd3bSJian Shen * then it will be removed at next time. If is TO_ADD, it means 1454ee4bcd3bSJian Shen * send TO_ADD request failed, so just remove the mac node. 1455ee4bcd3bSJian Shen */ 1456ee4bcd3bSJian Shen new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1457ee4bcd3bSJian Shen if (new_node) { 1458ee4bcd3bSJian Shen hclgevf_update_mac_node(new_node, mac_node->state); 1459ee4bcd3bSJian Shen list_del(&mac_node->node); 1460ee4bcd3bSJian Shen kfree(mac_node); 1461ee4bcd3bSJian Shen } else if (mac_node->state == HCLGEVF_MAC_ACTIVE) { 1462ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_TO_DEL; 1463ee4bcd3bSJian Shen list_del(&mac_node->node); 1464ee4bcd3bSJian Shen list_add_tail(&mac_node->node, mac_list); 1465ee4bcd3bSJian Shen } else { 1466ee4bcd3bSJian Shen list_del(&mac_node->node); 1467ee4bcd3bSJian Shen kfree(mac_node); 1468ee4bcd3bSJian Shen } 1469ee4bcd3bSJian Shen } 1470ee4bcd3bSJian Shen } 1471ee4bcd3bSJian Shen 1472ee4bcd3bSJian Shen static void hclgevf_sync_from_del_list(struct list_head *del_list, 1473ee4bcd3bSJian Shen struct list_head *mac_list) 1474ee4bcd3bSJian Shen { 1475ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1476ee4bcd3bSJian Shen 1477ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, del_list, node) { 1478ee4bcd3bSJian Shen new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1479ee4bcd3bSJian Shen if (new_node) { 1480ee4bcd3bSJian Shen /* If the mac addr is exist in the mac list, it means 1481ee4bcd3bSJian Shen * received a new request TO_ADD during the time window 1482ee4bcd3bSJian Shen * of sending mac addr configurrequest to PF, so just 1483ee4bcd3bSJian Shen * change the mac state to ACTIVE. 1484ee4bcd3bSJian Shen */ 1485ee4bcd3bSJian Shen new_node->state = HCLGEVF_MAC_ACTIVE; 1486ee4bcd3bSJian Shen list_del(&mac_node->node); 1487ee4bcd3bSJian Shen kfree(mac_node); 1488ee4bcd3bSJian Shen } else { 1489ee4bcd3bSJian Shen list_del(&mac_node->node); 1490ee4bcd3bSJian Shen list_add_tail(&mac_node->node, mac_list); 1491ee4bcd3bSJian Shen } 1492ee4bcd3bSJian Shen } 1493ee4bcd3bSJian Shen } 1494ee4bcd3bSJian Shen 1495ee4bcd3bSJian Shen static void hclgevf_clear_list(struct list_head *list) 1496ee4bcd3bSJian Shen { 1497ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp; 1498ee4bcd3bSJian Shen 1499ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, list, node) { 1500ee4bcd3bSJian Shen list_del(&mac_node->node); 1501ee4bcd3bSJian Shen kfree(mac_node); 1502ee4bcd3bSJian Shen } 1503ee4bcd3bSJian Shen } 1504ee4bcd3bSJian Shen 1505ee4bcd3bSJian Shen static void hclgevf_sync_mac_list(struct hclgevf_dev *hdev, 1506ee4bcd3bSJian Shen enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1507ee4bcd3bSJian Shen { 1508ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1509ee4bcd3bSJian Shen struct list_head tmp_add_list, tmp_del_list; 1510ee4bcd3bSJian Shen struct list_head *list; 1511ee4bcd3bSJian Shen 1512ee4bcd3bSJian Shen INIT_LIST_HEAD(&tmp_add_list); 1513ee4bcd3bSJian Shen INIT_LIST_HEAD(&tmp_del_list); 1514ee4bcd3bSJian Shen 1515ee4bcd3bSJian Shen /* move the mac addr to the tmp_add_list and tmp_del_list, then 1516ee4bcd3bSJian Shen * we can add/delete these mac addr outside the spin lock 1517ee4bcd3bSJian Shen */ 1518ee4bcd3bSJian Shen list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1519ee4bcd3bSJian Shen &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1520ee4bcd3bSJian Shen 1521ee4bcd3bSJian Shen spin_lock_bh(&hdev->mac_table.mac_list_lock); 1522ee4bcd3bSJian Shen 1523ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, list, node) { 1524ee4bcd3bSJian Shen switch (mac_node->state) { 1525ee4bcd3bSJian Shen case HCLGEVF_MAC_TO_DEL: 1526ee4bcd3bSJian Shen list_del(&mac_node->node); 1527ee4bcd3bSJian Shen list_add_tail(&mac_node->node, &tmp_del_list); 1528ee4bcd3bSJian Shen break; 1529ee4bcd3bSJian Shen case HCLGEVF_MAC_TO_ADD: 1530ee4bcd3bSJian Shen new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 1531ee4bcd3bSJian Shen if (!new_node) 1532ee4bcd3bSJian Shen goto stop_traverse; 1533ee4bcd3bSJian Shen 1534ee4bcd3bSJian Shen ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 1535ee4bcd3bSJian Shen new_node->state = mac_node->state; 1536ee4bcd3bSJian Shen list_add_tail(&new_node->node, &tmp_add_list); 1537ee4bcd3bSJian Shen break; 1538ee4bcd3bSJian Shen default: 1539ee4bcd3bSJian Shen break; 1540ee4bcd3bSJian Shen } 1541ee4bcd3bSJian Shen } 1542ee4bcd3bSJian Shen 1543ee4bcd3bSJian Shen stop_traverse: 1544ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1545ee4bcd3bSJian Shen 1546ee4bcd3bSJian Shen /* delete first, in order to get max mac table space for adding */ 1547ee4bcd3bSJian Shen hclgevf_config_mac_list(hdev, &tmp_del_list, mac_type); 1548ee4bcd3bSJian Shen hclgevf_config_mac_list(hdev, &tmp_add_list, mac_type); 1549ee4bcd3bSJian Shen 1550ee4bcd3bSJian Shen /* if some mac addresses were added/deleted fail, move back to the 1551ee4bcd3bSJian Shen * mac_list, and retry at next time. 1552ee4bcd3bSJian Shen */ 1553ee4bcd3bSJian Shen spin_lock_bh(&hdev->mac_table.mac_list_lock); 1554ee4bcd3bSJian Shen 1555ee4bcd3bSJian Shen hclgevf_sync_from_del_list(&tmp_del_list, list); 1556ee4bcd3bSJian Shen hclgevf_sync_from_add_list(&tmp_add_list, list); 1557ee4bcd3bSJian Shen 1558ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1559ee4bcd3bSJian Shen } 1560ee4bcd3bSJian Shen 1561ee4bcd3bSJian Shen static void hclgevf_sync_mac_table(struct hclgevf_dev *hdev) 1562ee4bcd3bSJian Shen { 1563ee4bcd3bSJian Shen hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_UC); 1564ee4bcd3bSJian Shen hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_MC); 1565ee4bcd3bSJian Shen } 1566ee4bcd3bSJian Shen 1567ee4bcd3bSJian Shen static void hclgevf_uninit_mac_list(struct hclgevf_dev *hdev) 1568ee4bcd3bSJian Shen { 1569ee4bcd3bSJian Shen spin_lock_bh(&hdev->mac_table.mac_list_lock); 1570ee4bcd3bSJian Shen 1571ee4bcd3bSJian Shen hclgevf_clear_list(&hdev->mac_table.uc_mac_list); 1572ee4bcd3bSJian Shen hclgevf_clear_list(&hdev->mac_table.mc_mac_list); 1573ee4bcd3bSJian Shen 1574ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1575ee4bcd3bSJian Shen } 1576ee4bcd3bSJian Shen 1577e2cb1decSSalil Mehta static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1578e2cb1decSSalil Mehta __be16 proto, u16 vlan_id, 1579e2cb1decSSalil Mehta bool is_kill) 1580e2cb1decSSalil Mehta { 1581d3410018SYufeng Mo #define HCLGEVF_VLAN_MBX_IS_KILL_OFFSET 0 1582d3410018SYufeng Mo #define HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET 1 1583d3410018SYufeng Mo #define HCLGEVF_VLAN_MBX_PROTO_OFFSET 3 1584d3410018SYufeng Mo 1585e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1586d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1587fe4144d4SJian Shen int ret; 1588e2cb1decSSalil Mehta 1589b37ce587SYufeng Mo if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1590e2cb1decSSalil Mehta return -EINVAL; 1591e2cb1decSSalil Mehta 1592e2cb1decSSalil Mehta if (proto != htons(ETH_P_8021Q)) 1593e2cb1decSSalil Mehta return -EPROTONOSUPPORT; 1594e2cb1decSSalil Mehta 1595b7b5d25bSGuojia Liao /* When device is resetting or reset failed, firmware is unable to 1596b7b5d25bSGuojia Liao * handle mailbox. Just record the vlan id, and remove it after 1597fe4144d4SJian Shen * reset finished. 1598fe4144d4SJian Shen */ 1599b7b5d25bSGuojia Liao if ((test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 1600b7b5d25bSGuojia Liao test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) && is_kill) { 1601fe4144d4SJian Shen set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1602fe4144d4SJian Shen return -EBUSY; 1603fe4144d4SJian Shen } 1604fe4144d4SJian Shen 1605d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1606d3410018SYufeng Mo HCLGE_MBX_VLAN_FILTER); 1607d3410018SYufeng Mo send_msg.data[HCLGEVF_VLAN_MBX_IS_KILL_OFFSET] = is_kill; 1608d3410018SYufeng Mo memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET], &vlan_id, 1609d3410018SYufeng Mo sizeof(vlan_id)); 1610d3410018SYufeng Mo memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_PROTO_OFFSET], &proto, 1611d3410018SYufeng Mo sizeof(proto)); 161246ee7350SGuojia Liao /* when remove hw vlan filter failed, record the vlan id, 1613fe4144d4SJian Shen * and try to remove it from hw later, to be consistence 1614fe4144d4SJian Shen * with stack. 1615fe4144d4SJian Shen */ 1616d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1617fe4144d4SJian Shen if (is_kill && ret) 1618fe4144d4SJian Shen set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1619fe4144d4SJian Shen 1620fe4144d4SJian Shen return ret; 1621fe4144d4SJian Shen } 1622fe4144d4SJian Shen 1623fe4144d4SJian Shen static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1624fe4144d4SJian Shen { 1625fe4144d4SJian Shen #define HCLGEVF_MAX_SYNC_COUNT 60 1626fe4144d4SJian Shen struct hnae3_handle *handle = &hdev->nic; 1627fe4144d4SJian Shen int ret, sync_cnt = 0; 1628fe4144d4SJian Shen u16 vlan_id; 1629fe4144d4SJian Shen 1630fe4144d4SJian Shen vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1631fe4144d4SJian Shen while (vlan_id != VLAN_N_VID) { 1632fe4144d4SJian Shen ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1633fe4144d4SJian Shen vlan_id, true); 1634fe4144d4SJian Shen if (ret) 1635fe4144d4SJian Shen return; 1636fe4144d4SJian Shen 1637fe4144d4SJian Shen clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1638fe4144d4SJian Shen sync_cnt++; 1639fe4144d4SJian Shen if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1640fe4144d4SJian Shen return; 1641fe4144d4SJian Shen 1642fe4144d4SJian Shen vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1643fe4144d4SJian Shen } 1644e2cb1decSSalil Mehta } 1645e2cb1decSSalil Mehta 1646b2641e2aSYunsheng Lin static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1647b2641e2aSYunsheng Lin { 1648b2641e2aSYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1649d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1650b2641e2aSYunsheng Lin 1651d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1652d3410018SYufeng Mo HCLGE_MBX_VLAN_RX_OFF_CFG); 1653d3410018SYufeng Mo send_msg.data[0] = enable ? 1 : 0; 1654d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1655b2641e2aSYunsheng Lin } 1656b2641e2aSYunsheng Lin 16577fa6be4fSHuazhong Tan static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1658e2cb1decSSalil Mehta { 1659e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1660d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 16611a426f8bSPeng Li int ret; 1662e2cb1decSSalil Mehta 16631a426f8bSPeng Li /* disable vf queue before send queue reset msg to PF */ 16641a426f8bSPeng Li ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 16651a426f8bSPeng Li if (ret) 16667fa6be4fSHuazhong Tan return ret; 16671a426f8bSPeng Li 1668d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 1669d3410018SYufeng Mo memcpy(send_msg.data, &queue_id, sizeof(queue_id)); 1670d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1671e2cb1decSSalil Mehta } 1672e2cb1decSSalil Mehta 1673818f1675SYunsheng Lin static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1674818f1675SYunsheng Lin { 1675818f1675SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1676d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1677818f1675SYunsheng Lin 1678d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MTU, 0); 1679d3410018SYufeng Mo memcpy(send_msg.data, &new_mtu, sizeof(new_mtu)); 1680d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1681818f1675SYunsheng Lin } 1682818f1675SYunsheng Lin 16836988eb2aSSalil Mehta static int hclgevf_notify_client(struct hclgevf_dev *hdev, 16846988eb2aSSalil Mehta enum hnae3_reset_notify_type type) 16856988eb2aSSalil Mehta { 16866988eb2aSSalil Mehta struct hnae3_client *client = hdev->nic_client; 16876988eb2aSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 16886a5f6fa3SHuazhong Tan int ret; 16896988eb2aSSalil Mehta 169025d1817cSHuazhong Tan if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 169125d1817cSHuazhong Tan !client) 169225d1817cSHuazhong Tan return 0; 169325d1817cSHuazhong Tan 16946988eb2aSSalil Mehta if (!client->ops->reset_notify) 16956988eb2aSSalil Mehta return -EOPNOTSUPP; 16966988eb2aSSalil Mehta 16976a5f6fa3SHuazhong Tan ret = client->ops->reset_notify(handle, type); 16986a5f6fa3SHuazhong Tan if (ret) 16996a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 17006a5f6fa3SHuazhong Tan type, ret); 17016a5f6fa3SHuazhong Tan 17026a5f6fa3SHuazhong Tan return ret; 17036988eb2aSSalil Mehta } 17046988eb2aSSalil Mehta 1705fe735c84SHuazhong Tan static int hclgevf_notify_roce_client(struct hclgevf_dev *hdev, 1706fe735c84SHuazhong Tan enum hnae3_reset_notify_type type) 1707fe735c84SHuazhong Tan { 1708fe735c84SHuazhong Tan struct hnae3_client *client = hdev->roce_client; 1709fe735c84SHuazhong Tan struct hnae3_handle *handle = &hdev->roce; 1710fe735c84SHuazhong Tan int ret; 1711fe735c84SHuazhong Tan 1712fe735c84SHuazhong Tan if (!test_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state) || !client) 1713fe735c84SHuazhong Tan return 0; 1714fe735c84SHuazhong Tan 1715fe735c84SHuazhong Tan if (!client->ops->reset_notify) 1716fe735c84SHuazhong Tan return -EOPNOTSUPP; 1717fe735c84SHuazhong Tan 1718fe735c84SHuazhong Tan ret = client->ops->reset_notify(handle, type); 1719fe735c84SHuazhong Tan if (ret) 1720fe735c84SHuazhong Tan dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 1721fe735c84SHuazhong Tan type, ret); 1722fe735c84SHuazhong Tan return ret; 1723fe735c84SHuazhong Tan } 1724fe735c84SHuazhong Tan 17256988eb2aSSalil Mehta static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 17266988eb2aSSalil Mehta { 1727aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_US 20000 1728aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_CNT 2000 1729aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1730aa5c4f17SHuazhong Tan (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1731aa5c4f17SHuazhong Tan 1732aa5c4f17SHuazhong Tan u32 val; 1733aa5c4f17SHuazhong Tan int ret; 17346988eb2aSSalil Mehta 1735f28368bbSHuazhong Tan if (hdev->reset_type == HNAE3_VF_RESET) 173672e2fb07SHuazhong Tan ret = readl_poll_timeout(hdev->hw.io_base + 173772e2fb07SHuazhong Tan HCLGEVF_VF_RST_ING, val, 173872e2fb07SHuazhong Tan !(val & HCLGEVF_VF_RST_ING_BIT), 173972e2fb07SHuazhong Tan HCLGEVF_RESET_WAIT_US, 174072e2fb07SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 174172e2fb07SHuazhong Tan else 174272e2fb07SHuazhong Tan ret = readl_poll_timeout(hdev->hw.io_base + 174372e2fb07SHuazhong Tan HCLGEVF_RST_ING, val, 1744aa5c4f17SHuazhong Tan !(val & HCLGEVF_RST_ING_BITS), 1745aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_US, 1746aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 17476988eb2aSSalil Mehta 17486988eb2aSSalil Mehta /* hardware completion status should be available by this time */ 1749aa5c4f17SHuazhong Tan if (ret) { 1750aa5c4f17SHuazhong Tan dev_err(&hdev->pdev->dev, 17518912fd6aSColin Ian King "couldn't get reset done status from h/w, timeout!\n"); 1752aa5c4f17SHuazhong Tan return ret; 17536988eb2aSSalil Mehta } 17546988eb2aSSalil Mehta 17556988eb2aSSalil Mehta /* we will wait a bit more to let reset of the stack to complete. This 17566988eb2aSSalil Mehta * might happen in case reset assertion was made by PF. Yes, this also 17576988eb2aSSalil Mehta * means we might end up waiting bit more even for VF reset. 17586988eb2aSSalil Mehta */ 17596988eb2aSSalil Mehta msleep(5000); 17606988eb2aSSalil Mehta 17616988eb2aSSalil Mehta return 0; 17626988eb2aSSalil Mehta } 17636988eb2aSSalil Mehta 17646b428b4fSHuazhong Tan static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable) 17656b428b4fSHuazhong Tan { 17666b428b4fSHuazhong Tan u32 reg_val; 17676b428b4fSHuazhong Tan 17686b428b4fSHuazhong Tan reg_val = hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG); 17696b428b4fSHuazhong Tan if (enable) 17706b428b4fSHuazhong Tan reg_val |= HCLGEVF_NIC_SW_RST_RDY; 17716b428b4fSHuazhong Tan else 17726b428b4fSHuazhong Tan reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; 17736b428b4fSHuazhong Tan 17746b428b4fSHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 17756b428b4fSHuazhong Tan reg_val); 17766b428b4fSHuazhong Tan } 17776b428b4fSHuazhong Tan 17786988eb2aSSalil Mehta static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 17796988eb2aSSalil Mehta { 17807a01c897SSalil Mehta int ret; 17817a01c897SSalil Mehta 17826988eb2aSSalil Mehta /* uninitialize the nic client */ 17836a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 17846a5f6fa3SHuazhong Tan if (ret) 17856a5f6fa3SHuazhong Tan return ret; 17866988eb2aSSalil Mehta 17877a01c897SSalil Mehta /* re-initialize the hclge device */ 17889c6f7085SHuazhong Tan ret = hclgevf_reset_hdev(hdev); 17897a01c897SSalil Mehta if (ret) { 17907a01c897SSalil Mehta dev_err(&hdev->pdev->dev, 17917a01c897SSalil Mehta "hclge device re-init failed, VF is disabled!\n"); 17927a01c897SSalil Mehta return ret; 17937a01c897SSalil Mehta } 17946988eb2aSSalil Mehta 17956988eb2aSSalil Mehta /* bring up the nic client again */ 17966a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 17976a5f6fa3SHuazhong Tan if (ret) 17986a5f6fa3SHuazhong Tan return ret; 17996988eb2aSSalil Mehta 18006b428b4fSHuazhong Tan /* clear handshake status with IMP */ 18016b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, false); 18026b428b4fSHuazhong Tan 18031cc9bc6eSHuazhong Tan /* bring up the nic to enable TX/RX again */ 18041cc9bc6eSHuazhong Tan return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 18056988eb2aSSalil Mehta } 18066988eb2aSSalil Mehta 1807dea846e8SHuazhong Tan static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1808dea846e8SHuazhong Tan { 1809ada13ee3SHuazhong Tan #define HCLGEVF_RESET_SYNC_TIME 100 1810ada13ee3SHuazhong Tan 1811f28368bbSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FUNC_RESET) { 1812d41884eeSHuazhong Tan struct hclge_vf_to_pf_msg send_msg; 1813d41884eeSHuazhong Tan int ret; 1814d41884eeSHuazhong Tan 1815d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_RESET, 0); 1816d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1817cddd5648SHuazhong Tan if (ret) { 1818cddd5648SHuazhong Tan dev_err(&hdev->pdev->dev, 1819cddd5648SHuazhong Tan "failed to assert VF reset, ret = %d\n", ret); 1820cddd5648SHuazhong Tan return ret; 1821cddd5648SHuazhong Tan } 1822c88a6e7dSHuazhong Tan hdev->rst_stats.vf_func_rst_cnt++; 1823dea846e8SHuazhong Tan } 1824dea846e8SHuazhong Tan 1825ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1826ada13ee3SHuazhong Tan /* inform hardware that preparatory work is done */ 1827ada13ee3SHuazhong Tan msleep(HCLGEVF_RESET_SYNC_TIME); 18286b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, true); 1829d41884eeSHuazhong Tan dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done\n", 1830d41884eeSHuazhong Tan hdev->reset_type); 1831dea846e8SHuazhong Tan 1832d41884eeSHuazhong Tan return 0; 1833dea846e8SHuazhong Tan } 1834dea846e8SHuazhong Tan 18353d77d0cbSHuazhong Tan static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev) 18363d77d0cbSHuazhong Tan { 18373d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "VF function reset count: %u\n", 18383d77d0cbSHuazhong Tan hdev->rst_stats.vf_func_rst_cnt); 18393d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "FLR reset count: %u\n", 18403d77d0cbSHuazhong Tan hdev->rst_stats.flr_rst_cnt); 18413d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "VF reset count: %u\n", 18423d77d0cbSHuazhong Tan hdev->rst_stats.vf_rst_cnt); 18433d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "reset done count: %u\n", 18443d77d0cbSHuazhong Tan hdev->rst_stats.rst_done_cnt); 18453d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "HW reset done count: %u\n", 18463d77d0cbSHuazhong Tan hdev->rst_stats.hw_rst_done_cnt); 18473d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "reset count: %u\n", 18483d77d0cbSHuazhong Tan hdev->rst_stats.rst_cnt); 18493d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "reset fail count: %u\n", 18503d77d0cbSHuazhong Tan hdev->rst_stats.rst_fail_cnt); 18513d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n", 18523d77d0cbSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE)); 18533d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n", 18549cee2e8dSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_STATE_REG)); 18553d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n", 18563d77d0cbSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_CMDQ_TX_DEPTH_REG)); 18573d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n", 18583d77d0cbSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING)); 18593d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state); 18603d77d0cbSHuazhong Tan } 18613d77d0cbSHuazhong Tan 1862bbe6540eSHuazhong Tan static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1863bbe6540eSHuazhong Tan { 18646b428b4fSHuazhong Tan /* recover handshake status with IMP when reset fail */ 18656b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, true); 1866bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt++; 1867adcf738bSGuojia Liao dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n", 1868bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt); 1869bbe6540eSHuazhong Tan 1870bbe6540eSHuazhong Tan if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1871bbe6540eSHuazhong Tan set_bit(hdev->reset_type, &hdev->reset_pending); 1872bbe6540eSHuazhong Tan 1873bbe6540eSHuazhong Tan if (hclgevf_is_reset_pending(hdev)) { 1874bbe6540eSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1875bbe6540eSHuazhong Tan hclgevf_reset_task_schedule(hdev); 18763d77d0cbSHuazhong Tan } else { 1877d5432455SGuojia Liao set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 18783d77d0cbSHuazhong Tan hclgevf_dump_rst_info(hdev); 1879bbe6540eSHuazhong Tan } 1880bbe6540eSHuazhong Tan } 1881bbe6540eSHuazhong Tan 18821cc9bc6eSHuazhong Tan static int hclgevf_reset_prepare(struct hclgevf_dev *hdev) 18836988eb2aSSalil Mehta { 18846988eb2aSSalil Mehta int ret; 18856988eb2aSSalil Mehta 1886c88a6e7dSHuazhong Tan hdev->rst_stats.rst_cnt++; 18876988eb2aSSalil Mehta 1888fe735c84SHuazhong Tan /* perform reset of the stack & ae device for a client */ 1889fe735c84SHuazhong Tan ret = hclgevf_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 1890fe735c84SHuazhong Tan if (ret) 1891fe735c84SHuazhong Tan return ret; 1892fe735c84SHuazhong Tan 18931cc9bc6eSHuazhong Tan rtnl_lock(); 18946988eb2aSSalil Mehta /* bring down the nic to stop any ongoing TX/RX */ 18956a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 189629118ab9SHuazhong Tan rtnl_unlock(); 18976a5f6fa3SHuazhong Tan if (ret) 18981cc9bc6eSHuazhong Tan return ret; 1899dea846e8SHuazhong Tan 19001cc9bc6eSHuazhong Tan return hclgevf_reset_prepare_wait(hdev); 19016988eb2aSSalil Mehta } 19026988eb2aSSalil Mehta 19031cc9bc6eSHuazhong Tan static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev) 19041cc9bc6eSHuazhong Tan { 19051cc9bc6eSHuazhong Tan int ret; 19061cc9bc6eSHuazhong Tan 1907c88a6e7dSHuazhong Tan hdev->rst_stats.hw_rst_done_cnt++; 1908fe735c84SHuazhong Tan ret = hclgevf_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 1909fe735c84SHuazhong Tan if (ret) 1910fe735c84SHuazhong Tan return ret; 1911c88a6e7dSHuazhong Tan 191229118ab9SHuazhong Tan rtnl_lock(); 19136988eb2aSSalil Mehta /* now, re-initialize the nic client and ae device */ 19146988eb2aSSalil Mehta ret = hclgevf_reset_stack(hdev); 19151cc9bc6eSHuazhong Tan rtnl_unlock(); 19166a5f6fa3SHuazhong Tan if (ret) { 19176988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 19181cc9bc6eSHuazhong Tan return ret; 19196a5f6fa3SHuazhong Tan } 19206988eb2aSSalil Mehta 1921fe735c84SHuazhong Tan ret = hclgevf_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 1922fe735c84SHuazhong Tan /* ignore RoCE notify error if it fails HCLGEVF_RESET_MAX_FAIL_CNT - 1 1923fe735c84SHuazhong Tan * times 1924fe735c84SHuazhong Tan */ 1925fe735c84SHuazhong Tan if (ret && 1926fe735c84SHuazhong Tan hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT - 1) 1927fe735c84SHuazhong Tan return ret; 1928fe735c84SHuazhong Tan 1929fe735c84SHuazhong Tan ret = hclgevf_notify_roce_client(hdev, HNAE3_UP_CLIENT); 1930fe735c84SHuazhong Tan if (ret) 1931fe735c84SHuazhong Tan return ret; 1932fe735c84SHuazhong Tan 1933b644a8d4SHuazhong Tan hdev->last_reset_time = jiffies; 1934c88a6e7dSHuazhong Tan hdev->rst_stats.rst_done_cnt++; 1935bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt = 0; 1936d5432455SGuojia Liao clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1937b644a8d4SHuazhong Tan 19381cc9bc6eSHuazhong Tan return 0; 19391cc9bc6eSHuazhong Tan } 19401cc9bc6eSHuazhong Tan 19411cc9bc6eSHuazhong Tan static void hclgevf_reset(struct hclgevf_dev *hdev) 19421cc9bc6eSHuazhong Tan { 19431cc9bc6eSHuazhong Tan if (hclgevf_reset_prepare(hdev)) 19441cc9bc6eSHuazhong Tan goto err_reset; 19451cc9bc6eSHuazhong Tan 19461cc9bc6eSHuazhong Tan /* check if VF could successfully fetch the hardware reset completion 19471cc9bc6eSHuazhong Tan * status from the hardware 19481cc9bc6eSHuazhong Tan */ 19491cc9bc6eSHuazhong Tan if (hclgevf_reset_wait(hdev)) { 19501cc9bc6eSHuazhong Tan /* can't do much in this situation, will disable VF */ 19511cc9bc6eSHuazhong Tan dev_err(&hdev->pdev->dev, 19521cc9bc6eSHuazhong Tan "failed to fetch H/W reset completion status\n"); 19531cc9bc6eSHuazhong Tan goto err_reset; 19541cc9bc6eSHuazhong Tan } 19551cc9bc6eSHuazhong Tan 19561cc9bc6eSHuazhong Tan if (hclgevf_reset_rebuild(hdev)) 19571cc9bc6eSHuazhong Tan goto err_reset; 19581cc9bc6eSHuazhong Tan 19591cc9bc6eSHuazhong Tan return; 19601cc9bc6eSHuazhong Tan 19616a5f6fa3SHuazhong Tan err_reset: 1962bbe6540eSHuazhong Tan hclgevf_reset_err_handle(hdev); 19636988eb2aSSalil Mehta } 19646988eb2aSSalil Mehta 1965720bd583SHuazhong Tan static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1966720bd583SHuazhong Tan unsigned long *addr) 1967720bd583SHuazhong Tan { 1968720bd583SHuazhong Tan enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1969720bd583SHuazhong Tan 1970dea846e8SHuazhong Tan /* return the highest priority reset level amongst all */ 1971b90fcc5bSHuazhong Tan if (test_bit(HNAE3_VF_RESET, addr)) { 1972b90fcc5bSHuazhong Tan rst_level = HNAE3_VF_RESET; 1973b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_RESET, addr); 1974b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1975b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1976b90fcc5bSHuazhong Tan } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1977dea846e8SHuazhong Tan rst_level = HNAE3_VF_FULL_RESET; 1978dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FULL_RESET, addr); 1979dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1980aa5c4f17SHuazhong Tan } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1981aa5c4f17SHuazhong Tan rst_level = HNAE3_VF_PF_FUNC_RESET; 1982aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1983aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1984dea846e8SHuazhong Tan } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1985dea846e8SHuazhong Tan rst_level = HNAE3_VF_FUNC_RESET; 1986dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 19876ff3cf07SHuazhong Tan } else if (test_bit(HNAE3_FLR_RESET, addr)) { 19886ff3cf07SHuazhong Tan rst_level = HNAE3_FLR_RESET; 19896ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_RESET, addr); 1990720bd583SHuazhong Tan } 1991720bd583SHuazhong Tan 1992720bd583SHuazhong Tan return rst_level; 1993720bd583SHuazhong Tan } 1994720bd583SHuazhong Tan 19956ae4e733SShiju Jose static void hclgevf_reset_event(struct pci_dev *pdev, 19966ae4e733SShiju Jose struct hnae3_handle *handle) 19976d4c3981SSalil Mehta { 19986ff3cf07SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 19996ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 20006d4c3981SSalil Mehta 20016d4c3981SSalil Mehta dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 20026d4c3981SSalil Mehta 20036ff3cf07SHuazhong Tan if (hdev->default_reset_request) 20040742ed7cSHuazhong Tan hdev->reset_level = 2005720bd583SHuazhong Tan hclgevf_get_reset_level(hdev, 2006720bd583SHuazhong Tan &hdev->default_reset_request); 2007720bd583SHuazhong Tan else 2008dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 20096d4c3981SSalil Mehta 2010436667d2SSalil Mehta /* reset of this VF requested */ 2011436667d2SSalil Mehta set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 2012436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 20136d4c3981SSalil Mehta 20140742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 20156d4c3981SSalil Mehta } 20166d4c3981SSalil Mehta 2017720bd583SHuazhong Tan static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 2018720bd583SHuazhong Tan enum hnae3_reset_type rst_type) 2019720bd583SHuazhong Tan { 2020720bd583SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 2021720bd583SHuazhong Tan 2022720bd583SHuazhong Tan set_bit(rst_type, &hdev->default_reset_request); 2023720bd583SHuazhong Tan } 2024720bd583SHuazhong Tan 2025f28368bbSHuazhong Tan static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 2026f28368bbSHuazhong Tan { 2027f28368bbSHuazhong Tan writel(en ? 1 : 0, vector->addr); 2028f28368bbSHuazhong Tan } 2029f28368bbSHuazhong Tan 20306ff3cf07SHuazhong Tan static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 20316ff3cf07SHuazhong Tan { 2032f28368bbSHuazhong Tan #define HCLGEVF_FLR_RETRY_WAIT_MS 500 2033f28368bbSHuazhong Tan #define HCLGEVF_FLR_RETRY_CNT 5 2034f28368bbSHuazhong Tan 20356ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 2036f28368bbSHuazhong Tan int retry_cnt = 0; 2037f28368bbSHuazhong Tan int ret; 20386ff3cf07SHuazhong Tan 2039f28368bbSHuazhong Tan retry: 2040f28368bbSHuazhong Tan down(&hdev->reset_sem); 2041f28368bbSHuazhong Tan set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2042f28368bbSHuazhong Tan hdev->reset_type = HNAE3_FLR_RESET; 2043f28368bbSHuazhong Tan ret = hclgevf_reset_prepare(hdev); 2044f28368bbSHuazhong Tan if (ret) { 2045f28368bbSHuazhong Tan dev_err(&hdev->pdev->dev, "fail to prepare FLR, ret=%d\n", 2046f28368bbSHuazhong Tan ret); 2047f28368bbSHuazhong Tan if (hdev->reset_pending || 2048f28368bbSHuazhong Tan retry_cnt++ < HCLGEVF_FLR_RETRY_CNT) { 20496ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 2050f28368bbSHuazhong Tan "reset_pending:0x%lx, retry_cnt:%d\n", 2051f28368bbSHuazhong Tan hdev->reset_pending, retry_cnt); 2052f28368bbSHuazhong Tan clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2053f28368bbSHuazhong Tan up(&hdev->reset_sem); 2054f28368bbSHuazhong Tan msleep(HCLGEVF_FLR_RETRY_WAIT_MS); 2055f28368bbSHuazhong Tan goto retry; 2056f28368bbSHuazhong Tan } 2057f28368bbSHuazhong Tan } 2058f28368bbSHuazhong Tan 2059f28368bbSHuazhong Tan /* disable misc vector before FLR done */ 2060f28368bbSHuazhong Tan hclgevf_enable_vector(&hdev->misc_vector, false); 2061f28368bbSHuazhong Tan hdev->rst_stats.flr_rst_cnt++; 2062f28368bbSHuazhong Tan } 2063f28368bbSHuazhong Tan 2064f28368bbSHuazhong Tan static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 2065f28368bbSHuazhong Tan { 2066f28368bbSHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 2067f28368bbSHuazhong Tan int ret; 2068f28368bbSHuazhong Tan 2069f28368bbSHuazhong Tan hclgevf_enable_vector(&hdev->misc_vector, true); 2070f28368bbSHuazhong Tan 2071f28368bbSHuazhong Tan ret = hclgevf_reset_rebuild(hdev); 2072f28368bbSHuazhong Tan if (ret) 2073f28368bbSHuazhong Tan dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", 2074f28368bbSHuazhong Tan ret); 2075f28368bbSHuazhong Tan 2076f28368bbSHuazhong Tan hdev->reset_type = HNAE3_NONE_RESET; 2077f28368bbSHuazhong Tan clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2078f28368bbSHuazhong Tan up(&hdev->reset_sem); 20796ff3cf07SHuazhong Tan } 20806ff3cf07SHuazhong Tan 2081e2cb1decSSalil Mehta static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 2082e2cb1decSSalil Mehta { 2083e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2084e2cb1decSSalil Mehta 2085e2cb1decSSalil Mehta return hdev->fw_version; 2086e2cb1decSSalil Mehta } 2087e2cb1decSSalil Mehta 2088e2cb1decSSalil Mehta static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 2089e2cb1decSSalil Mehta { 2090e2cb1decSSalil Mehta struct hclgevf_misc_vector *vector = &hdev->misc_vector; 2091e2cb1decSSalil Mehta 2092e2cb1decSSalil Mehta vector->vector_irq = pci_irq_vector(hdev->pdev, 2093e2cb1decSSalil Mehta HCLGEVF_MISC_VECTOR_NUM); 2094e2cb1decSSalil Mehta vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 2095e2cb1decSSalil Mehta /* vector status always valid for Vector 0 */ 2096e2cb1decSSalil Mehta hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 2097e2cb1decSSalil Mehta hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 2098e2cb1decSSalil Mehta 2099e2cb1decSSalil Mehta hdev->num_msi_left -= 1; 2100e2cb1decSSalil Mehta hdev->num_msi_used += 1; 2101e2cb1decSSalil Mehta } 2102e2cb1decSSalil Mehta 210335a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 210435a1e503SSalil Mehta { 2105ff200099SYunsheng Lin if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2106ff200099SYunsheng Lin !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, 2107ff200099SYunsheng Lin &hdev->state)) 21080ea68902SYunsheng Lin mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 210935a1e503SSalil Mehta } 211035a1e503SSalil Mehta 211107a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 2112e2cb1decSSalil Mehta { 2113ff200099SYunsheng Lin if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2114ff200099SYunsheng Lin !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, 2115ff200099SYunsheng Lin &hdev->state)) 21160ea68902SYunsheng Lin mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 211707a0556aSSalil Mehta } 2118e2cb1decSSalil Mehta 2119ff200099SYunsheng Lin static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 2120ff200099SYunsheng Lin unsigned long delay) 2121e2cb1decSSalil Mehta { 2122d5432455SGuojia Liao if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2123d5432455SGuojia Liao !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 21240ea68902SYunsheng Lin mod_delayed_work(hclgevf_wq, &hdev->service_task, delay); 2125e2cb1decSSalil Mehta } 2126e2cb1decSSalil Mehta 2127ff200099SYunsheng Lin static void hclgevf_reset_service_task(struct hclgevf_dev *hdev) 212835a1e503SSalil Mehta { 2129d6ad7c53SGuojia Liao #define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3 2130d6ad7c53SGuojia Liao 2131ff200099SYunsheng Lin if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state)) 2132ff200099SYunsheng Lin return; 2133ff200099SYunsheng Lin 2134f28368bbSHuazhong Tan down(&hdev->reset_sem); 2135f28368bbSHuazhong Tan set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 213635a1e503SSalil Mehta 2137436667d2SSalil Mehta if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 2138436667d2SSalil Mehta &hdev->reset_state)) { 2139436667d2SSalil Mehta /* PF has initmated that it is about to reset the hardware. 21409b2f3477SWeihang Li * We now have to poll & check if hardware has actually 21419b2f3477SWeihang Li * completed the reset sequence. On hardware reset completion, 21429b2f3477SWeihang Li * VF needs to reset the client and ae device. 214335a1e503SSalil Mehta */ 2144436667d2SSalil Mehta hdev->reset_attempts = 0; 2145436667d2SSalil Mehta 2146dea846e8SHuazhong Tan hdev->last_reset_time = jiffies; 2147dea846e8SHuazhong Tan while ((hdev->reset_type = 2148dea846e8SHuazhong Tan hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 21491cc9bc6eSHuazhong Tan != HNAE3_NONE_RESET) 21501cc9bc6eSHuazhong Tan hclgevf_reset(hdev); 2151436667d2SSalil Mehta } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 2152436667d2SSalil Mehta &hdev->reset_state)) { 2153436667d2SSalil Mehta /* we could be here when either of below happens: 21549b2f3477SWeihang Li * 1. reset was initiated due to watchdog timeout caused by 2155436667d2SSalil Mehta * a. IMP was earlier reset and our TX got choked down and 2156436667d2SSalil Mehta * which resulted in watchdog reacting and inducing VF 2157436667d2SSalil Mehta * reset. This also means our cmdq would be unreliable. 2158436667d2SSalil Mehta * b. problem in TX due to other lower layer(example link 2159436667d2SSalil Mehta * layer not functioning properly etc.) 2160436667d2SSalil Mehta * 2. VF reset might have been initiated due to some config 2161436667d2SSalil Mehta * change. 2162436667d2SSalil Mehta * 2163436667d2SSalil Mehta * NOTE: Theres no clear way to detect above cases than to react 2164436667d2SSalil Mehta * to the response of PF for this reset request. PF will ack the 2165436667d2SSalil Mehta * 1b and 2. cases but we will not get any intimation about 1a 2166436667d2SSalil Mehta * from PF as cmdq would be in unreliable state i.e. mailbox 2167436667d2SSalil Mehta * communication between PF and VF would be broken. 216846ee7350SGuojia Liao * 216946ee7350SGuojia Liao * if we are never geting into pending state it means either: 2170436667d2SSalil Mehta * 1. PF is not receiving our request which could be due to IMP 2171436667d2SSalil Mehta * reset 2172436667d2SSalil Mehta * 2. PF is screwed 2173436667d2SSalil Mehta * We cannot do much for 2. but to check first we can try reset 2174436667d2SSalil Mehta * our PCIe + stack and see if it alleviates the problem. 2175436667d2SSalil Mehta */ 2176d6ad7c53SGuojia Liao if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) { 2177436667d2SSalil Mehta /* prepare for full reset of stack + pcie interface */ 2178dea846e8SHuazhong Tan set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 2179436667d2SSalil Mehta 2180436667d2SSalil Mehta /* "defer" schedule the reset task again */ 2181436667d2SSalil Mehta set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2182436667d2SSalil Mehta } else { 2183436667d2SSalil Mehta hdev->reset_attempts++; 2184436667d2SSalil Mehta 2185dea846e8SHuazhong Tan set_bit(hdev->reset_level, &hdev->reset_pending); 2186dea846e8SHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2187436667d2SSalil Mehta } 2188dea846e8SHuazhong Tan hclgevf_reset_task_schedule(hdev); 2189436667d2SSalil Mehta } 219035a1e503SSalil Mehta 2191afb6afdbSHuazhong Tan hdev->reset_type = HNAE3_NONE_RESET; 219235a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2193f28368bbSHuazhong Tan up(&hdev->reset_sem); 219435a1e503SSalil Mehta } 219535a1e503SSalil Mehta 2196ff200099SYunsheng Lin static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev) 2197e2cb1decSSalil Mehta { 2198ff200099SYunsheng Lin if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state)) 2199ff200099SYunsheng Lin return; 2200e2cb1decSSalil Mehta 2201e2cb1decSSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 2202e2cb1decSSalil Mehta return; 2203e2cb1decSSalil Mehta 220407a0556aSSalil Mehta hclgevf_mbx_async_handler(hdev); 2205e2cb1decSSalil Mehta 2206e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2207e2cb1decSSalil Mehta } 2208e2cb1decSSalil Mehta 2209ff200099SYunsheng Lin static void hclgevf_keep_alive(struct hclgevf_dev *hdev) 2210a6d818e3SYunsheng Lin { 2211d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 2212a6d818e3SYunsheng Lin int ret; 2213a6d818e3SYunsheng Lin 22141416d333SHuazhong Tan if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 2215c59a85c0SJian Shen return; 2216c59a85c0SJian Shen 2217d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_KEEP_ALIVE, 0); 2218d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2219a6d818e3SYunsheng Lin if (ret) 2220a6d818e3SYunsheng Lin dev_err(&hdev->pdev->dev, 2221a6d818e3SYunsheng Lin "VF sends keep alive cmd failed(=%d)\n", ret); 2222a6d818e3SYunsheng Lin } 2223a6d818e3SYunsheng Lin 2224ff200099SYunsheng Lin static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev) 2225e2cb1decSSalil Mehta { 2226ff200099SYunsheng Lin unsigned long delta = round_jiffies_relative(HZ); 2227ff200099SYunsheng Lin struct hnae3_handle *handle = &hdev->nic; 2228e2cb1decSSalil Mehta 2229e6394363SGuangbin Huang if (test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 2230e6394363SGuangbin Huang return; 2231e6394363SGuangbin Huang 2232ff200099SYunsheng Lin if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 2233ff200099SYunsheng Lin delta = jiffies - hdev->last_serv_processed; 2234db01afebSliuzhongzhu 2235ff200099SYunsheng Lin if (delta < round_jiffies_relative(HZ)) { 2236ff200099SYunsheng Lin delta = round_jiffies_relative(HZ) - delta; 2237ff200099SYunsheng Lin goto out; 2238db01afebSliuzhongzhu } 2239ff200099SYunsheng Lin } 2240ff200099SYunsheng Lin 2241ff200099SYunsheng Lin hdev->serv_processed_cnt++; 2242ff200099SYunsheng Lin if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL)) 2243ff200099SYunsheng Lin hclgevf_keep_alive(hdev); 2244ff200099SYunsheng Lin 2245ff200099SYunsheng Lin if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) { 2246ff200099SYunsheng Lin hdev->last_serv_processed = jiffies; 2247ff200099SYunsheng Lin goto out; 2248ff200099SYunsheng Lin } 2249ff200099SYunsheng Lin 2250ff200099SYunsheng Lin if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL)) 2251ff200099SYunsheng Lin hclgevf_tqps_update_stats(handle); 2252e2cb1decSSalil Mehta 2253e2cb1decSSalil Mehta /* request the link status from the PF. PF would be able to tell VF 2254e2cb1decSSalil Mehta * about such updates in future so we might remove this later 2255e2cb1decSSalil Mehta */ 2256e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 2257e2cb1decSSalil Mehta 22589194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 22599194d18bSliuzhongzhu 2260fe4144d4SJian Shen hclgevf_sync_vlan_filter(hdev); 2261fe4144d4SJian Shen 2262ee4bcd3bSJian Shen hclgevf_sync_mac_table(hdev); 2263ee4bcd3bSJian Shen 2264c631c696SJian Shen hclgevf_sync_promisc_mode(hdev); 2265c631c696SJian Shen 2266ff200099SYunsheng Lin hdev->last_serv_processed = jiffies; 2267436667d2SSalil Mehta 2268ff200099SYunsheng Lin out: 2269ff200099SYunsheng Lin hclgevf_task_schedule(hdev, delta); 2270ff200099SYunsheng Lin } 2271b3c3fe8eSYunsheng Lin 2272ff200099SYunsheng Lin static void hclgevf_service_task(struct work_struct *work) 2273ff200099SYunsheng Lin { 2274ff200099SYunsheng Lin struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev, 2275ff200099SYunsheng Lin service_task.work); 2276ff200099SYunsheng Lin 2277ff200099SYunsheng Lin hclgevf_reset_service_task(hdev); 2278ff200099SYunsheng Lin hclgevf_mailbox_service_task(hdev); 2279ff200099SYunsheng Lin hclgevf_periodic_service_task(hdev); 2280ff200099SYunsheng Lin 2281ff200099SYunsheng Lin /* Handle reset and mbx again in case periodical task delays the 2282ff200099SYunsheng Lin * handling by calling hclgevf_task_schedule() in 2283ff200099SYunsheng Lin * hclgevf_periodic_service_task() 2284ff200099SYunsheng Lin */ 2285ff200099SYunsheng Lin hclgevf_reset_service_task(hdev); 2286ff200099SYunsheng Lin hclgevf_mailbox_service_task(hdev); 2287e2cb1decSSalil Mehta } 2288e2cb1decSSalil Mehta 2289e2cb1decSSalil Mehta static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 2290e2cb1decSSalil Mehta { 2291e2cb1decSSalil Mehta hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 2292e2cb1decSSalil Mehta } 2293e2cb1decSSalil Mehta 2294b90fcc5bSHuazhong Tan static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 2295b90fcc5bSHuazhong Tan u32 *clearval) 2296e2cb1decSSalil Mehta { 229713050921SHuazhong Tan u32 val, cmdq_stat_reg, rst_ing_reg; 2298e2cb1decSSalil Mehta 2299e2cb1decSSalil Mehta /* fetch the events from their corresponding regs */ 230013050921SHuazhong Tan cmdq_stat_reg = hclgevf_read_dev(&hdev->hw, 23019cee2e8dSHuazhong Tan HCLGEVF_VECTOR0_CMDQ_STATE_REG); 2302e2cb1decSSalil Mehta 230313050921SHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 2304b90fcc5bSHuazhong Tan rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 2305b90fcc5bSHuazhong Tan dev_info(&hdev->pdev->dev, 2306b90fcc5bSHuazhong Tan "receive reset interrupt 0x%x!\n", rst_ing_reg); 2307b90fcc5bSHuazhong Tan set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 2308b90fcc5bSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2309ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 231013050921SHuazhong Tan *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B); 2311c88a6e7dSHuazhong Tan hdev->rst_stats.vf_rst_cnt++; 231272e2fb07SHuazhong Tan /* set up VF hardware reset status, its PF will clear 231372e2fb07SHuazhong Tan * this status when PF has initialized done. 231472e2fb07SHuazhong Tan */ 231572e2fb07SHuazhong Tan val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING); 231672e2fb07SHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING, 231772e2fb07SHuazhong Tan val | HCLGEVF_VF_RST_ING_BIT); 2318b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_RST; 2319b90fcc5bSHuazhong Tan } 2320b90fcc5bSHuazhong Tan 2321e2cb1decSSalil Mehta /* check for vector0 mailbox(=CMDQ RX) event source */ 232213050921SHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 232313050921SHuazhong Tan /* for revision 0x21, clearing interrupt is writing bit 0 232413050921SHuazhong Tan * to the clear register, writing bit 1 means to keep the 232513050921SHuazhong Tan * old value. 232613050921SHuazhong Tan * for revision 0x20, the clear register is a read & write 232713050921SHuazhong Tan * register, so we should just write 0 to the bit we are 232813050921SHuazhong Tan * handling, and keep other bits as cmdq_stat_reg. 232913050921SHuazhong Tan */ 2330295ba232SGuangbin Huang if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) 233113050921SHuazhong Tan *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 233213050921SHuazhong Tan else 233313050921SHuazhong Tan *clearval = cmdq_stat_reg & 233413050921SHuazhong Tan ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 233513050921SHuazhong Tan 2336b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_MBX; 2337e2cb1decSSalil Mehta } 2338e2cb1decSSalil Mehta 2339e45afb39SHuazhong Tan /* print other vector0 event source */ 2340e45afb39SHuazhong Tan dev_info(&hdev->pdev->dev, 2341e45afb39SHuazhong Tan "vector 0 interrupt from unknown source, cmdq_src = %#x\n", 2342e45afb39SHuazhong Tan cmdq_stat_reg); 2343e2cb1decSSalil Mehta 2344b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_OTHER; 2345e2cb1decSSalil Mehta } 2346e2cb1decSSalil Mehta 2347e2cb1decSSalil Mehta static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 2348e2cb1decSSalil Mehta { 2349b90fcc5bSHuazhong Tan enum hclgevf_evt_cause event_cause; 2350e2cb1decSSalil Mehta struct hclgevf_dev *hdev = data; 2351e2cb1decSSalil Mehta u32 clearval; 2352e2cb1decSSalil Mehta 2353e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 2354b90fcc5bSHuazhong Tan event_cause = hclgevf_check_evt_cause(hdev, &clearval); 2355e2cb1decSSalil Mehta 2356b90fcc5bSHuazhong Tan switch (event_cause) { 2357b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_RST: 2358b90fcc5bSHuazhong Tan hclgevf_reset_task_schedule(hdev); 2359b90fcc5bSHuazhong Tan break; 2360b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_MBX: 236107a0556aSSalil Mehta hclgevf_mbx_handler(hdev); 2362b90fcc5bSHuazhong Tan break; 2363b90fcc5bSHuazhong Tan default: 2364b90fcc5bSHuazhong Tan break; 2365b90fcc5bSHuazhong Tan } 2366e2cb1decSSalil Mehta 2367b90fcc5bSHuazhong Tan if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 2368e2cb1decSSalil Mehta hclgevf_clear_event_cause(hdev, clearval); 2369e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2370b90fcc5bSHuazhong Tan } 2371e2cb1decSSalil Mehta 2372e2cb1decSSalil Mehta return IRQ_HANDLED; 2373e2cb1decSSalil Mehta } 2374e2cb1decSSalil Mehta 2375e2cb1decSSalil Mehta static int hclgevf_configure(struct hclgevf_dev *hdev) 2376e2cb1decSSalil Mehta { 2377e2cb1decSSalil Mehta int ret; 2378e2cb1decSSalil Mehta 237992f11ea1SJian Shen /* get current port based vlan state from PF */ 238092f11ea1SJian Shen ret = hclgevf_get_port_base_vlan_filter_state(hdev); 238192f11ea1SJian Shen if (ret) 238292f11ea1SJian Shen return ret; 238392f11ea1SJian Shen 2384e2cb1decSSalil Mehta /* get queue configuration from PF */ 23856cee6fc3SJian Shen ret = hclgevf_get_queue_info(hdev); 2386e2cb1decSSalil Mehta if (ret) 2387e2cb1decSSalil Mehta return ret; 2388c0425944SPeng Li 2389c0425944SPeng Li /* get queue depth info from PF */ 2390c0425944SPeng Li ret = hclgevf_get_queue_depth(hdev); 2391c0425944SPeng Li if (ret) 2392c0425944SPeng Li return ret; 2393c0425944SPeng Li 23949c3e7130Sliuzhongzhu ret = hclgevf_get_pf_media_type(hdev); 23959c3e7130Sliuzhongzhu if (ret) 23969c3e7130Sliuzhongzhu return ret; 23979c3e7130Sliuzhongzhu 2398e2cb1decSSalil Mehta /* get tc configuration from PF */ 2399e2cb1decSSalil Mehta return hclgevf_get_tc_info(hdev); 2400e2cb1decSSalil Mehta } 2401e2cb1decSSalil Mehta 24027a01c897SSalil Mehta static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 24037a01c897SSalil Mehta { 24047a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 24051154bb26SPeng Li struct hclgevf_dev *hdev; 24067a01c897SSalil Mehta 24077a01c897SSalil Mehta hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 24087a01c897SSalil Mehta if (!hdev) 24097a01c897SSalil Mehta return -ENOMEM; 24107a01c897SSalil Mehta 24117a01c897SSalil Mehta hdev->pdev = pdev; 24127a01c897SSalil Mehta hdev->ae_dev = ae_dev; 24137a01c897SSalil Mehta ae_dev->priv = hdev; 24147a01c897SSalil Mehta 24157a01c897SSalil Mehta return 0; 24167a01c897SSalil Mehta } 24177a01c897SSalil Mehta 2418e2cb1decSSalil Mehta static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 2419e2cb1decSSalil Mehta { 2420e2cb1decSSalil Mehta struct hnae3_handle *roce = &hdev->roce; 2421e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 2422e2cb1decSSalil Mehta 242307acf909SJian Shen roce->rinfo.num_vectors = hdev->num_roce_msix; 2424e2cb1decSSalil Mehta 2425e2cb1decSSalil Mehta if (hdev->num_msi_left < roce->rinfo.num_vectors || 2426e2cb1decSSalil Mehta hdev->num_msi_left == 0) 2427e2cb1decSSalil Mehta return -EINVAL; 2428e2cb1decSSalil Mehta 242907acf909SJian Shen roce->rinfo.base_vector = hdev->roce_base_vector; 2430e2cb1decSSalil Mehta 2431e2cb1decSSalil Mehta roce->rinfo.netdev = nic->kinfo.netdev; 2432e2cb1decSSalil Mehta roce->rinfo.roce_io_base = hdev->hw.io_base; 2433e2cb1decSSalil Mehta 2434e2cb1decSSalil Mehta roce->pdev = nic->pdev; 2435e2cb1decSSalil Mehta roce->ae_algo = nic->ae_algo; 2436e2cb1decSSalil Mehta roce->numa_node_mask = nic->numa_node_mask; 2437e2cb1decSSalil Mehta 2438e2cb1decSSalil Mehta return 0; 2439e2cb1decSSalil Mehta } 2440e2cb1decSSalil Mehta 2441b26a6feaSPeng Li static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 2442b26a6feaSPeng Li { 2443b26a6feaSPeng Li struct hclgevf_cfg_gro_status_cmd *req; 2444b26a6feaSPeng Li struct hclgevf_desc desc; 2445b26a6feaSPeng Li int ret; 2446b26a6feaSPeng Li 2447b26a6feaSPeng Li if (!hnae3_dev_gro_supported(hdev)) 2448b26a6feaSPeng Li return 0; 2449b26a6feaSPeng Li 2450b26a6feaSPeng Li hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 2451b26a6feaSPeng Li false); 2452b26a6feaSPeng Li req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2453b26a6feaSPeng Li 2454fb9e44d6SHuazhong Tan req->gro_en = en ? 1 : 0; 2455b26a6feaSPeng Li 2456b26a6feaSPeng Li ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2457b26a6feaSPeng Li if (ret) 2458b26a6feaSPeng Li dev_err(&hdev->pdev->dev, 2459b26a6feaSPeng Li "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2460b26a6feaSPeng Li 2461b26a6feaSPeng Li return ret; 2462b26a6feaSPeng Li } 2463b26a6feaSPeng Li 2464944de484SGuojia Liao static void hclgevf_rss_init_cfg(struct hclgevf_dev *hdev) 2465e2cb1decSSalil Mehta { 2466e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2467944de484SGuojia Liao struct hclgevf_rss_tuple_cfg *tuple_sets; 24684093d1a2SGuangbin Huang u32 i; 2469e2cb1decSSalil Mehta 2470944de484SGuojia Liao rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 24714093d1a2SGuangbin Huang rss_cfg->rss_size = hdev->nic.kinfo.rss_size; 2472944de484SGuojia Liao tuple_sets = &rss_cfg->rss_tuple_sets; 2473295ba232SGuangbin Huang if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 2474472d7eceSJian Shen rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 2475472d7eceSJian Shen memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 2476374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 2477374ad291SJian Shen 2478944de484SGuojia Liao tuple_sets->ipv4_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2479944de484SGuojia Liao tuple_sets->ipv4_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2480944de484SGuojia Liao tuple_sets->ipv4_sctp_en = HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2481944de484SGuojia Liao tuple_sets->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2482944de484SGuojia Liao tuple_sets->ipv6_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2483944de484SGuojia Liao tuple_sets->ipv6_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2484944de484SGuojia Liao tuple_sets->ipv6_sctp_en = HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2485944de484SGuojia Liao tuple_sets->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2486374ad291SJian Shen } 2487374ad291SJian Shen 24889b2f3477SWeihang Li /* Initialize RSS indirect table */ 2489e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 24904093d1a2SGuangbin Huang rss_cfg->rss_indirection_tbl[i] = i % rss_cfg->rss_size; 2491944de484SGuojia Liao } 2492944de484SGuojia Liao 2493944de484SGuojia Liao static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2494944de484SGuojia Liao { 2495944de484SGuojia Liao struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2496944de484SGuojia Liao int ret; 2497944de484SGuojia Liao 2498295ba232SGuangbin Huang if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 2499944de484SGuojia Liao ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 2500944de484SGuojia Liao rss_cfg->rss_hash_key); 2501944de484SGuojia Liao if (ret) 2502944de484SGuojia Liao return ret; 2503944de484SGuojia Liao 2504944de484SGuojia Liao ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 2505944de484SGuojia Liao if (ret) 2506944de484SGuojia Liao return ret; 2507944de484SGuojia Liao } 2508e2cb1decSSalil Mehta 2509e2cb1decSSalil Mehta ret = hclgevf_set_rss_indir_table(hdev); 2510e2cb1decSSalil Mehta if (ret) 2511e2cb1decSSalil Mehta return ret; 2512e2cb1decSSalil Mehta 25134093d1a2SGuangbin Huang return hclgevf_set_rss_tc_mode(hdev, rss_cfg->rss_size); 2514e2cb1decSSalil Mehta } 2515e2cb1decSSalil Mehta 2516e2cb1decSSalil Mehta static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2517e2cb1decSSalil Mehta { 2518e2cb1decSSalil Mehta return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2519e2cb1decSSalil Mehta false); 2520e2cb1decSSalil Mehta } 2521e2cb1decSSalil Mehta 2522ff200099SYunsheng Lin static void hclgevf_flush_link_update(struct hclgevf_dev *hdev) 2523ff200099SYunsheng Lin { 2524ff200099SYunsheng Lin #define HCLGEVF_FLUSH_LINK_TIMEOUT 100000 2525ff200099SYunsheng Lin 2526ff200099SYunsheng Lin unsigned long last = hdev->serv_processed_cnt; 2527ff200099SYunsheng Lin int i = 0; 2528ff200099SYunsheng Lin 2529ff200099SYunsheng Lin while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) && 2530ff200099SYunsheng Lin i++ < HCLGEVF_FLUSH_LINK_TIMEOUT && 2531ff200099SYunsheng Lin last == hdev->serv_processed_cnt) 2532ff200099SYunsheng Lin usleep_range(1, 1); 2533ff200099SYunsheng Lin } 2534ff200099SYunsheng Lin 25358cdb992fSJian Shen static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 25368cdb992fSJian Shen { 25378cdb992fSJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 25388cdb992fSJian Shen 25398cdb992fSJian Shen if (enable) { 2540ff200099SYunsheng Lin hclgevf_task_schedule(hdev, 0); 25418cdb992fSJian Shen } else { 2542b3c3fe8eSYunsheng Lin set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2543ff200099SYunsheng Lin 2544ff200099SYunsheng Lin /* flush memory to make sure DOWN is seen by service task */ 2545ff200099SYunsheng Lin smp_mb__before_atomic(); 2546ff200099SYunsheng Lin hclgevf_flush_link_update(hdev); 25478cdb992fSJian Shen } 25488cdb992fSJian Shen } 25498cdb992fSJian Shen 2550e2cb1decSSalil Mehta static int hclgevf_ae_start(struct hnae3_handle *handle) 2551e2cb1decSSalil Mehta { 2552e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2553e2cb1decSSalil Mehta 2554e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 2555e2cb1decSSalil Mehta 2556e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 2557e2cb1decSSalil Mehta 25589194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 25599194d18bSliuzhongzhu 2560e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2561e2cb1decSSalil Mehta 2562e2cb1decSSalil Mehta return 0; 2563e2cb1decSSalil Mehta } 2564e2cb1decSSalil Mehta 2565e2cb1decSSalil Mehta static void hclgevf_ae_stop(struct hnae3_handle *handle) 2566e2cb1decSSalil Mehta { 2567e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 256839cfbc9cSHuazhong Tan int i; 2569e2cb1decSSalil Mehta 25702f7e4896SFuyun Liang set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 25712f7e4896SFuyun Liang 2572146e92c1SHuazhong Tan if (hdev->reset_type != HNAE3_VF_RESET) 257339cfbc9cSHuazhong Tan for (i = 0; i < handle->kinfo.num_tqps; i++) 2574146e92c1SHuazhong Tan if (hclgevf_reset_tqp(handle, i)) 2575146e92c1SHuazhong Tan break; 257639cfbc9cSHuazhong Tan 2577e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 25788cc6c1f7SFuyun Liang hclgevf_update_link_status(hdev, 0); 2579e2cb1decSSalil Mehta } 2580e2cb1decSSalil Mehta 2581a6d818e3SYunsheng Lin static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2582a6d818e3SYunsheng Lin { 2583d3410018SYufeng Mo #define HCLGEVF_STATE_ALIVE 1 2584d3410018SYufeng Mo #define HCLGEVF_STATE_NOT_ALIVE 0 2585a6d818e3SYunsheng Lin 2586d3410018SYufeng Mo struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2587d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 2588d3410018SYufeng Mo 2589d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_ALIVE, 0); 2590d3410018SYufeng Mo send_msg.data[0] = alive ? HCLGEVF_STATE_ALIVE : 2591d3410018SYufeng Mo HCLGEVF_STATE_NOT_ALIVE; 2592d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2593a6d818e3SYunsheng Lin } 2594a6d818e3SYunsheng Lin 2595a6d818e3SYunsheng Lin static int hclgevf_client_start(struct hnae3_handle *handle) 2596a6d818e3SYunsheng Lin { 2597f621df96SQinglang Miao return hclgevf_set_alive(handle, true); 2598a6d818e3SYunsheng Lin } 2599a6d818e3SYunsheng Lin 2600a6d818e3SYunsheng Lin static void hclgevf_client_stop(struct hnae3_handle *handle) 2601a6d818e3SYunsheng Lin { 2602a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2603a6d818e3SYunsheng Lin int ret; 2604a6d818e3SYunsheng Lin 2605a6d818e3SYunsheng Lin ret = hclgevf_set_alive(handle, false); 2606a6d818e3SYunsheng Lin if (ret) 2607a6d818e3SYunsheng Lin dev_warn(&hdev->pdev->dev, 2608a6d818e3SYunsheng Lin "%s failed %d\n", __func__, ret); 2609a6d818e3SYunsheng Lin } 2610a6d818e3SYunsheng Lin 2611e2cb1decSSalil Mehta static void hclgevf_state_init(struct hclgevf_dev *hdev) 2612e2cb1decSSalil Mehta { 2613e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2614e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2615d5432455SGuojia Liao clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 2616e2cb1decSSalil Mehta 2617b3c3fe8eSYunsheng Lin INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task); 261835a1e503SSalil Mehta 2619e2cb1decSSalil Mehta mutex_init(&hdev->mbx_resp.mbx_mutex); 2620f28368bbSHuazhong Tan sema_init(&hdev->reset_sem, 1); 2621e2cb1decSSalil Mehta 2622ee4bcd3bSJian Shen spin_lock_init(&hdev->mac_table.mac_list_lock); 2623ee4bcd3bSJian Shen INIT_LIST_HEAD(&hdev->mac_table.uc_mac_list); 2624ee4bcd3bSJian Shen INIT_LIST_HEAD(&hdev->mac_table.mc_mac_list); 2625ee4bcd3bSJian Shen 2626e2cb1decSSalil Mehta /* bring the device down */ 2627e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2628e2cb1decSSalil Mehta } 2629e2cb1decSSalil Mehta 2630e2cb1decSSalil Mehta static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2631e2cb1decSSalil Mehta { 2632e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2633acfc3d55SHuazhong Tan set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2634e2cb1decSSalil Mehta 2635b3c3fe8eSYunsheng Lin if (hdev->service_task.work.func) 2636b3c3fe8eSYunsheng Lin cancel_delayed_work_sync(&hdev->service_task); 2637e2cb1decSSalil Mehta 2638e2cb1decSSalil Mehta mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2639e2cb1decSSalil Mehta } 2640e2cb1decSSalil Mehta 2641e2cb1decSSalil Mehta static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2642e2cb1decSSalil Mehta { 2643e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2644e2cb1decSSalil Mehta int vectors; 2645e2cb1decSSalil Mehta int i; 2646e2cb1decSSalil Mehta 2647580a05f9SYonglong Liu if (hnae3_dev_roce_supported(hdev)) 264807acf909SJian Shen vectors = pci_alloc_irq_vectors(pdev, 264907acf909SJian Shen hdev->roce_base_msix_offset + 1, 265007acf909SJian Shen hdev->num_msi, 265107acf909SJian Shen PCI_IRQ_MSIX); 265207acf909SJian Shen else 2653580a05f9SYonglong Liu vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2654580a05f9SYonglong Liu hdev->num_msi, 2655e2cb1decSSalil Mehta PCI_IRQ_MSI | PCI_IRQ_MSIX); 265607acf909SJian Shen 2657e2cb1decSSalil Mehta if (vectors < 0) { 2658e2cb1decSSalil Mehta dev_err(&pdev->dev, 2659e2cb1decSSalil Mehta "failed(%d) to allocate MSI/MSI-X vectors\n", 2660e2cb1decSSalil Mehta vectors); 2661e2cb1decSSalil Mehta return vectors; 2662e2cb1decSSalil Mehta } 2663e2cb1decSSalil Mehta if (vectors < hdev->num_msi) 2664e2cb1decSSalil Mehta dev_warn(&hdev->pdev->dev, 2665adcf738bSGuojia Liao "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2666e2cb1decSSalil Mehta hdev->num_msi, vectors); 2667e2cb1decSSalil Mehta 2668e2cb1decSSalil Mehta hdev->num_msi = vectors; 2669e2cb1decSSalil Mehta hdev->num_msi_left = vectors; 2670580a05f9SYonglong Liu 2671e2cb1decSSalil Mehta hdev->base_msi_vector = pdev->irq; 267207acf909SJian Shen hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2673e2cb1decSSalil Mehta 2674e2cb1decSSalil Mehta hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2675e2cb1decSSalil Mehta sizeof(u16), GFP_KERNEL); 2676e2cb1decSSalil Mehta if (!hdev->vector_status) { 2677e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2678e2cb1decSSalil Mehta return -ENOMEM; 2679e2cb1decSSalil Mehta } 2680e2cb1decSSalil Mehta 2681e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 2682e2cb1decSSalil Mehta hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2683e2cb1decSSalil Mehta 2684e2cb1decSSalil Mehta hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2685e2cb1decSSalil Mehta sizeof(int), GFP_KERNEL); 2686e2cb1decSSalil Mehta if (!hdev->vector_irq) { 2687862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2688e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2689e2cb1decSSalil Mehta return -ENOMEM; 2690e2cb1decSSalil Mehta } 2691e2cb1decSSalil Mehta 2692e2cb1decSSalil Mehta return 0; 2693e2cb1decSSalil Mehta } 2694e2cb1decSSalil Mehta 2695e2cb1decSSalil Mehta static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2696e2cb1decSSalil Mehta { 2697e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2698e2cb1decSSalil Mehta 2699862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2700862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_irq); 2701e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2702e2cb1decSSalil Mehta } 2703e2cb1decSSalil Mehta 2704e2cb1decSSalil Mehta static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2705e2cb1decSSalil Mehta { 2706cdd332acSGuojia Liao int ret; 2707e2cb1decSSalil Mehta 2708e2cb1decSSalil Mehta hclgevf_get_misc_vector(hdev); 2709e2cb1decSSalil Mehta 2710f97c4d82SYonglong Liu snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 2711f97c4d82SYonglong Liu HCLGEVF_NAME, pci_name(hdev->pdev)); 2712e2cb1decSSalil Mehta ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2713f97c4d82SYonglong Liu 0, hdev->misc_vector.name, hdev); 2714e2cb1decSSalil Mehta if (ret) { 2715e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2716e2cb1decSSalil Mehta hdev->misc_vector.vector_irq); 2717e2cb1decSSalil Mehta return ret; 2718e2cb1decSSalil Mehta } 2719e2cb1decSSalil Mehta 27201819e409SXi Wang hclgevf_clear_event_cause(hdev, 0); 27211819e409SXi Wang 2722e2cb1decSSalil Mehta /* enable misc. vector(vector 0) */ 2723e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2724e2cb1decSSalil Mehta 2725e2cb1decSSalil Mehta return ret; 2726e2cb1decSSalil Mehta } 2727e2cb1decSSalil Mehta 2728e2cb1decSSalil Mehta static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2729e2cb1decSSalil Mehta { 2730e2cb1decSSalil Mehta /* disable misc vector(vector 0) */ 2731e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 27321819e409SXi Wang synchronize_irq(hdev->misc_vector.vector_irq); 2733e2cb1decSSalil Mehta free_irq(hdev->misc_vector.vector_irq, hdev); 2734e2cb1decSSalil Mehta hclgevf_free_vector(hdev, 0); 2735e2cb1decSSalil Mehta } 2736e2cb1decSSalil Mehta 2737bb87be87SYonglong Liu static void hclgevf_info_show(struct hclgevf_dev *hdev) 2738bb87be87SYonglong Liu { 2739bb87be87SYonglong Liu struct device *dev = &hdev->pdev->dev; 2740bb87be87SYonglong Liu 2741bb87be87SYonglong Liu dev_info(dev, "VF info begin:\n"); 2742bb87be87SYonglong Liu 2743adcf738bSGuojia Liao dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 2744adcf738bSGuojia Liao dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 2745adcf738bSGuojia Liao dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 2746adcf738bSGuojia Liao dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 2747adcf738bSGuojia Liao dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 2748adcf738bSGuojia Liao dev_info(dev, "PF media type of this VF: %u\n", 2749bb87be87SYonglong Liu hdev->hw.mac.media_type); 2750bb87be87SYonglong Liu 2751bb87be87SYonglong Liu dev_info(dev, "VF info end.\n"); 2752bb87be87SYonglong Liu } 2753bb87be87SYonglong Liu 27541db58f86SHuazhong Tan static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 27551db58f86SHuazhong Tan struct hnae3_client *client) 27561db58f86SHuazhong Tan { 27571db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 27584cd5beaaSGuangbin Huang int rst_cnt = hdev->rst_stats.rst_cnt; 27591db58f86SHuazhong Tan int ret; 27601db58f86SHuazhong Tan 27611db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->nic); 27621db58f86SHuazhong Tan if (ret) 27631db58f86SHuazhong Tan return ret; 27641db58f86SHuazhong Tan 27651db58f86SHuazhong Tan set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 27664cd5beaaSGuangbin Huang if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 27674cd5beaaSGuangbin Huang rst_cnt != hdev->rst_stats.rst_cnt) { 27684cd5beaaSGuangbin Huang clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 27694cd5beaaSGuangbin Huang 27704cd5beaaSGuangbin Huang client->ops->uninit_instance(&hdev->nic, 0); 27714cd5beaaSGuangbin Huang return -EBUSY; 27724cd5beaaSGuangbin Huang } 27734cd5beaaSGuangbin Huang 27741db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 27751db58f86SHuazhong Tan 27761db58f86SHuazhong Tan if (netif_msg_drv(&hdev->nic)) 27771db58f86SHuazhong Tan hclgevf_info_show(hdev); 27781db58f86SHuazhong Tan 27791db58f86SHuazhong Tan return 0; 27801db58f86SHuazhong Tan } 27811db58f86SHuazhong Tan 27821db58f86SHuazhong Tan static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 27831db58f86SHuazhong Tan struct hnae3_client *client) 27841db58f86SHuazhong Tan { 27851db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 27861db58f86SHuazhong Tan int ret; 27871db58f86SHuazhong Tan 27881db58f86SHuazhong Tan if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 27891db58f86SHuazhong Tan !hdev->nic_client) 27901db58f86SHuazhong Tan return 0; 27911db58f86SHuazhong Tan 27921db58f86SHuazhong Tan ret = hclgevf_init_roce_base_info(hdev); 27931db58f86SHuazhong Tan if (ret) 27941db58f86SHuazhong Tan return ret; 27951db58f86SHuazhong Tan 27961db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->roce); 27971db58f86SHuazhong Tan if (ret) 27981db58f86SHuazhong Tan return ret; 27991db58f86SHuazhong Tan 2800fe735c84SHuazhong Tan set_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 28011db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 28021db58f86SHuazhong Tan 28031db58f86SHuazhong Tan return 0; 28041db58f86SHuazhong Tan } 28051db58f86SHuazhong Tan 2806e718a93fSPeng Li static int hclgevf_init_client_instance(struct hnae3_client *client, 2807e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2808e2cb1decSSalil Mehta { 2809e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2810e2cb1decSSalil Mehta int ret; 2811e2cb1decSSalil Mehta 2812e2cb1decSSalil Mehta switch (client->type) { 2813e2cb1decSSalil Mehta case HNAE3_CLIENT_KNIC: 2814e2cb1decSSalil Mehta hdev->nic_client = client; 2815e2cb1decSSalil Mehta hdev->nic.client = client; 2816e2cb1decSSalil Mehta 28171db58f86SHuazhong Tan ret = hclgevf_init_nic_client_instance(ae_dev, client); 2818e2cb1decSSalil Mehta if (ret) 281949dd8054SJian Shen goto clear_nic; 2820e2cb1decSSalil Mehta 28211db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, 28221db58f86SHuazhong Tan hdev->roce_client); 2823e2cb1decSSalil Mehta if (ret) 282449dd8054SJian Shen goto clear_roce; 2825d9f28fc2SJian Shen 2826e2cb1decSSalil Mehta break; 2827e2cb1decSSalil Mehta case HNAE3_CLIENT_ROCE: 2828544a7bcdSLijun Ou if (hnae3_dev_roce_supported(hdev)) { 2829e2cb1decSSalil Mehta hdev->roce_client = client; 2830e2cb1decSSalil Mehta hdev->roce.client = client; 2831544a7bcdSLijun Ou } 2832e2cb1decSSalil Mehta 28331db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, client); 2834e2cb1decSSalil Mehta if (ret) 283549dd8054SJian Shen goto clear_roce; 2836e2cb1decSSalil Mehta 2837fa7a4bd5SJian Shen break; 2838fa7a4bd5SJian Shen default: 2839fa7a4bd5SJian Shen return -EINVAL; 2840e2cb1decSSalil Mehta } 2841e2cb1decSSalil Mehta 2842e2cb1decSSalil Mehta return 0; 284349dd8054SJian Shen 284449dd8054SJian Shen clear_nic: 284549dd8054SJian Shen hdev->nic_client = NULL; 284649dd8054SJian Shen hdev->nic.client = NULL; 284749dd8054SJian Shen return ret; 284849dd8054SJian Shen clear_roce: 284949dd8054SJian Shen hdev->roce_client = NULL; 285049dd8054SJian Shen hdev->roce.client = NULL; 285149dd8054SJian Shen return ret; 2852e2cb1decSSalil Mehta } 2853e2cb1decSSalil Mehta 2854e718a93fSPeng Li static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2855e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2856e2cb1decSSalil Mehta { 2857e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2858e718a93fSPeng Li 2859e2cb1decSSalil Mehta /* un-init roce, if it exists */ 286049dd8054SJian Shen if (hdev->roce_client) { 2861fe735c84SHuazhong Tan clear_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 2862e2cb1decSSalil Mehta hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 286349dd8054SJian Shen hdev->roce_client = NULL; 286449dd8054SJian Shen hdev->roce.client = NULL; 286549dd8054SJian Shen } 2866e2cb1decSSalil Mehta 2867e2cb1decSSalil Mehta /* un-init nic/unic, if this was not called by roce client */ 286849dd8054SJian Shen if (client->ops->uninit_instance && hdev->nic_client && 286949dd8054SJian Shen client->type != HNAE3_CLIENT_ROCE) { 287025d1817cSHuazhong Tan clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 287125d1817cSHuazhong Tan 2872e2cb1decSSalil Mehta client->ops->uninit_instance(&hdev->nic, 0); 287349dd8054SJian Shen hdev->nic_client = NULL; 287449dd8054SJian Shen hdev->nic.client = NULL; 287549dd8054SJian Shen } 2876e2cb1decSSalil Mehta } 2877e2cb1decSSalil Mehta 2878e2cb1decSSalil Mehta static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2879e2cb1decSSalil Mehta { 2880e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2881e2cb1decSSalil Mehta struct hclgevf_hw *hw; 2882e2cb1decSSalil Mehta int ret; 2883e2cb1decSSalil Mehta 2884e2cb1decSSalil Mehta ret = pci_enable_device(pdev); 2885e2cb1decSSalil Mehta if (ret) { 2886e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed to enable PCI device\n"); 28873e249d3bSFuyun Liang return ret; 2888e2cb1decSSalil Mehta } 2889e2cb1decSSalil Mehta 2890e2cb1decSSalil Mehta ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2891e2cb1decSSalil Mehta if (ret) { 2892e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2893e2cb1decSSalil Mehta goto err_disable_device; 2894e2cb1decSSalil Mehta } 2895e2cb1decSSalil Mehta 2896e2cb1decSSalil Mehta ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2897e2cb1decSSalil Mehta if (ret) { 2898e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2899e2cb1decSSalil Mehta goto err_disable_device; 2900e2cb1decSSalil Mehta } 2901e2cb1decSSalil Mehta 2902e2cb1decSSalil Mehta pci_set_master(pdev); 2903e2cb1decSSalil Mehta hw = &hdev->hw; 2904e2cb1decSSalil Mehta hw->hdev = hdev; 29052e1ea493SPeng Li hw->io_base = pci_iomap(pdev, 2, 0); 2906e2cb1decSSalil Mehta if (!hw->io_base) { 2907e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't map configuration register space\n"); 2908e2cb1decSSalil Mehta ret = -ENOMEM; 2909e2cb1decSSalil Mehta goto err_clr_master; 2910e2cb1decSSalil Mehta } 2911e2cb1decSSalil Mehta 2912e2cb1decSSalil Mehta return 0; 2913e2cb1decSSalil Mehta 2914e2cb1decSSalil Mehta err_clr_master: 2915e2cb1decSSalil Mehta pci_clear_master(pdev); 2916e2cb1decSSalil Mehta pci_release_regions(pdev); 2917e2cb1decSSalil Mehta err_disable_device: 2918e2cb1decSSalil Mehta pci_disable_device(pdev); 29193e249d3bSFuyun Liang 2920e2cb1decSSalil Mehta return ret; 2921e2cb1decSSalil Mehta } 2922e2cb1decSSalil Mehta 2923e2cb1decSSalil Mehta static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2924e2cb1decSSalil Mehta { 2925e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2926e2cb1decSSalil Mehta 2927e2cb1decSSalil Mehta pci_iounmap(pdev, hdev->hw.io_base); 2928e2cb1decSSalil Mehta pci_clear_master(pdev); 2929e2cb1decSSalil Mehta pci_release_regions(pdev); 2930e2cb1decSSalil Mehta pci_disable_device(pdev); 2931e2cb1decSSalil Mehta } 2932e2cb1decSSalil Mehta 293307acf909SJian Shen static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 293407acf909SJian Shen { 293507acf909SJian Shen struct hclgevf_query_res_cmd *req; 293607acf909SJian Shen struct hclgevf_desc desc; 293707acf909SJian Shen int ret; 293807acf909SJian Shen 293907acf909SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 294007acf909SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 294107acf909SJian Shen if (ret) { 294207acf909SJian Shen dev_err(&hdev->pdev->dev, 294307acf909SJian Shen "query vf resource failed, ret = %d.\n", ret); 294407acf909SJian Shen return ret; 294507acf909SJian Shen } 294607acf909SJian Shen 294707acf909SJian Shen req = (struct hclgevf_query_res_cmd *)desc.data; 294807acf909SJian Shen 2949580a05f9SYonglong Liu if (hnae3_dev_roce_supported(hdev)) { 295007acf909SJian Shen hdev->roce_base_msix_offset = 295160df7e91SHuazhong Tan hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee), 295207acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_M, 295307acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_S); 295407acf909SJian Shen hdev->num_roce_msix = 295560df7e91SHuazhong Tan hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 295607acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 295707acf909SJian Shen 2958580a05f9SYonglong Liu /* nic's msix numbers is always equals to the roce's. */ 2959580a05f9SYonglong Liu hdev->num_nic_msix = hdev->num_roce_msix; 2960580a05f9SYonglong Liu 296107acf909SJian Shen /* VF should have NIC vectors and Roce vectors, NIC vectors 296207acf909SJian Shen * are queued before Roce vectors. The offset is fixed to 64. 296307acf909SJian Shen */ 296407acf909SJian Shen hdev->num_msi = hdev->num_roce_msix + 296507acf909SJian Shen hdev->roce_base_msix_offset; 296607acf909SJian Shen } else { 296707acf909SJian Shen hdev->num_msi = 296860df7e91SHuazhong Tan hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 296907acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2970580a05f9SYonglong Liu 2971580a05f9SYonglong Liu hdev->num_nic_msix = hdev->num_msi; 2972580a05f9SYonglong Liu } 2973580a05f9SYonglong Liu 2974580a05f9SYonglong Liu if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) { 2975580a05f9SYonglong Liu dev_err(&hdev->pdev->dev, 2976580a05f9SYonglong Liu "Just %u msi resources, not enough for vf(min:2).\n", 2977580a05f9SYonglong Liu hdev->num_nic_msix); 2978580a05f9SYonglong Liu return -EINVAL; 297907acf909SJian Shen } 298007acf909SJian Shen 298107acf909SJian Shen return 0; 298207acf909SJian Shen } 298307acf909SJian Shen 2984af2aedc5SGuangbin Huang static void hclgevf_set_default_dev_specs(struct hclgevf_dev *hdev) 2985af2aedc5SGuangbin Huang { 2986af2aedc5SGuangbin Huang #define HCLGEVF_MAX_NON_TSO_BD_NUM 8U 2987af2aedc5SGuangbin Huang 2988af2aedc5SGuangbin Huang struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2989af2aedc5SGuangbin Huang 2990af2aedc5SGuangbin Huang ae_dev->dev_specs.max_non_tso_bd_num = 2991af2aedc5SGuangbin Huang HCLGEVF_MAX_NON_TSO_BD_NUM; 2992af2aedc5SGuangbin Huang ae_dev->dev_specs.rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 2993af2aedc5SGuangbin Huang ae_dev->dev_specs.rss_key_size = HCLGEVF_RSS_KEY_SIZE; 2994*ab16b49cSHuazhong Tan ae_dev->dev_specs.max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 2995af2aedc5SGuangbin Huang } 2996af2aedc5SGuangbin Huang 2997af2aedc5SGuangbin Huang static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev, 2998af2aedc5SGuangbin Huang struct hclgevf_desc *desc) 2999af2aedc5SGuangbin Huang { 3000af2aedc5SGuangbin Huang struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 3001af2aedc5SGuangbin Huang struct hclgevf_dev_specs_0_cmd *req0; 3002*ab16b49cSHuazhong Tan struct hclgevf_dev_specs_1_cmd *req1; 3003af2aedc5SGuangbin Huang 3004af2aedc5SGuangbin Huang req0 = (struct hclgevf_dev_specs_0_cmd *)desc[0].data; 3005*ab16b49cSHuazhong Tan req1 = (struct hclgevf_dev_specs_1_cmd *)desc[1].data; 3006af2aedc5SGuangbin Huang 3007af2aedc5SGuangbin Huang ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 3008af2aedc5SGuangbin Huang ae_dev->dev_specs.rss_ind_tbl_size = 3009af2aedc5SGuangbin Huang le16_to_cpu(req0->rss_ind_tbl_size); 301091bfae25SHuazhong Tan ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 3011af2aedc5SGuangbin Huang ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 3012*ab16b49cSHuazhong Tan ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 3013af2aedc5SGuangbin Huang } 3014af2aedc5SGuangbin Huang 301513297028SGuangbin Huang static void hclgevf_check_dev_specs(struct hclgevf_dev *hdev) 301613297028SGuangbin Huang { 301713297028SGuangbin Huang struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 301813297028SGuangbin Huang 301913297028SGuangbin Huang if (!dev_specs->max_non_tso_bd_num) 302013297028SGuangbin Huang dev_specs->max_non_tso_bd_num = HCLGEVF_MAX_NON_TSO_BD_NUM; 302113297028SGuangbin Huang if (!dev_specs->rss_ind_tbl_size) 302213297028SGuangbin Huang dev_specs->rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 302313297028SGuangbin Huang if (!dev_specs->rss_key_size) 302413297028SGuangbin Huang dev_specs->rss_key_size = HCLGEVF_RSS_KEY_SIZE; 3025*ab16b49cSHuazhong Tan if (!dev_specs->max_int_gl) 3026*ab16b49cSHuazhong Tan dev_specs->max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 302713297028SGuangbin Huang } 302813297028SGuangbin Huang 3029af2aedc5SGuangbin Huang static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev) 3030af2aedc5SGuangbin Huang { 3031af2aedc5SGuangbin Huang struct hclgevf_desc desc[HCLGEVF_QUERY_DEV_SPECS_BD_NUM]; 3032af2aedc5SGuangbin Huang int ret; 3033af2aedc5SGuangbin Huang int i; 3034af2aedc5SGuangbin Huang 3035af2aedc5SGuangbin Huang /* set default specifications as devices lower than version V3 do not 3036af2aedc5SGuangbin Huang * support querying specifications from firmware. 3037af2aedc5SGuangbin Huang */ 3038af2aedc5SGuangbin Huang if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 3039af2aedc5SGuangbin Huang hclgevf_set_default_dev_specs(hdev); 3040af2aedc5SGuangbin Huang return 0; 3041af2aedc5SGuangbin Huang } 3042af2aedc5SGuangbin Huang 3043af2aedc5SGuangbin Huang for (i = 0; i < HCLGEVF_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 3044af2aedc5SGuangbin Huang hclgevf_cmd_setup_basic_desc(&desc[i], 3045af2aedc5SGuangbin Huang HCLGEVF_OPC_QUERY_DEV_SPECS, true); 3046af2aedc5SGuangbin Huang desc[i].flag |= cpu_to_le16(HCLGEVF_CMD_FLAG_NEXT); 3047af2aedc5SGuangbin Huang } 3048af2aedc5SGuangbin Huang hclgevf_cmd_setup_basic_desc(&desc[i], HCLGEVF_OPC_QUERY_DEV_SPECS, 3049af2aedc5SGuangbin Huang true); 3050af2aedc5SGuangbin Huang 3051af2aedc5SGuangbin Huang ret = hclgevf_cmd_send(&hdev->hw, desc, HCLGEVF_QUERY_DEV_SPECS_BD_NUM); 3052af2aedc5SGuangbin Huang if (ret) 3053af2aedc5SGuangbin Huang return ret; 3054af2aedc5SGuangbin Huang 3055af2aedc5SGuangbin Huang hclgevf_parse_dev_specs(hdev, desc); 305613297028SGuangbin Huang hclgevf_check_dev_specs(hdev); 3057af2aedc5SGuangbin Huang 3058af2aedc5SGuangbin Huang return 0; 3059af2aedc5SGuangbin Huang } 3060af2aedc5SGuangbin Huang 3061862d969aSHuazhong Tan static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 3062862d969aSHuazhong Tan { 3063862d969aSHuazhong Tan struct pci_dev *pdev = hdev->pdev; 3064862d969aSHuazhong Tan int ret = 0; 3065862d969aSHuazhong Tan 3066862d969aSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FULL_RESET && 3067862d969aSHuazhong Tan test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3068862d969aSHuazhong Tan hclgevf_misc_irq_uninit(hdev); 3069862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 3070862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3071862d969aSHuazhong Tan } 3072862d969aSHuazhong Tan 3073862d969aSHuazhong Tan if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3074862d969aSHuazhong Tan pci_set_master(pdev); 3075862d969aSHuazhong Tan ret = hclgevf_init_msi(hdev); 3076862d969aSHuazhong Tan if (ret) { 3077862d969aSHuazhong Tan dev_err(&pdev->dev, 3078862d969aSHuazhong Tan "failed(%d) to init MSI/MSI-X\n", ret); 3079862d969aSHuazhong Tan return ret; 3080862d969aSHuazhong Tan } 3081862d969aSHuazhong Tan 3082862d969aSHuazhong Tan ret = hclgevf_misc_irq_init(hdev); 3083862d969aSHuazhong Tan if (ret) { 3084862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 3085862d969aSHuazhong Tan dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 3086862d969aSHuazhong Tan ret); 3087862d969aSHuazhong Tan return ret; 3088862d969aSHuazhong Tan } 3089862d969aSHuazhong Tan 3090862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3091862d969aSHuazhong Tan } 3092862d969aSHuazhong Tan 3093862d969aSHuazhong Tan return ret; 3094862d969aSHuazhong Tan } 3095862d969aSHuazhong Tan 3096039ba863SJian Shen static int hclgevf_clear_vport_list(struct hclgevf_dev *hdev) 3097039ba863SJian Shen { 3098039ba863SJian Shen struct hclge_vf_to_pf_msg send_msg; 3099039ba863SJian Shen 3100039ba863SJian Shen hclgevf_build_send_msg(&send_msg, HCLGE_MBX_HANDLE_VF_TBL, 3101039ba863SJian Shen HCLGE_MBX_VPORT_LIST_CLEAR); 3102039ba863SJian Shen return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3103039ba863SJian Shen } 3104039ba863SJian Shen 31059c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 3106e2cb1decSSalil Mehta { 31077a01c897SSalil Mehta struct pci_dev *pdev = hdev->pdev; 3108e2cb1decSSalil Mehta int ret; 3109e2cb1decSSalil Mehta 3110862d969aSHuazhong Tan ret = hclgevf_pci_reset(hdev); 3111862d969aSHuazhong Tan if (ret) { 3112862d969aSHuazhong Tan dev_err(&pdev->dev, "pci reset failed %d\n", ret); 3113862d969aSHuazhong Tan return ret; 3114862d969aSHuazhong Tan } 3115862d969aSHuazhong Tan 31169c6f7085SHuazhong Tan ret = hclgevf_cmd_init(hdev); 31179c6f7085SHuazhong Tan if (ret) { 31189c6f7085SHuazhong Tan dev_err(&pdev->dev, "cmd failed %d\n", ret); 31199c6f7085SHuazhong Tan return ret; 31207a01c897SSalil Mehta } 3121e2cb1decSSalil Mehta 31229c6f7085SHuazhong Tan ret = hclgevf_rss_init_hw(hdev); 31239c6f7085SHuazhong Tan if (ret) { 31249c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 31259c6f7085SHuazhong Tan "failed(%d) to initialize RSS\n", ret); 31269c6f7085SHuazhong Tan return ret; 31279c6f7085SHuazhong Tan } 31289c6f7085SHuazhong Tan 3129b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 3130b26a6feaSPeng Li if (ret) 3131b26a6feaSPeng Li return ret; 3132b26a6feaSPeng Li 31339c6f7085SHuazhong Tan ret = hclgevf_init_vlan_config(hdev); 31349c6f7085SHuazhong Tan if (ret) { 31359c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 31369c6f7085SHuazhong Tan "failed(%d) to initialize VLAN config\n", ret); 31379c6f7085SHuazhong Tan return ret; 31389c6f7085SHuazhong Tan } 31399c6f7085SHuazhong Tan 3140c631c696SJian Shen set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 3141c631c696SJian Shen 31429c6f7085SHuazhong Tan dev_info(&hdev->pdev->dev, "Reset done\n"); 31439c6f7085SHuazhong Tan 31449c6f7085SHuazhong Tan return 0; 31459c6f7085SHuazhong Tan } 31469c6f7085SHuazhong Tan 31479c6f7085SHuazhong Tan static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 31489c6f7085SHuazhong Tan { 31499c6f7085SHuazhong Tan struct pci_dev *pdev = hdev->pdev; 31509c6f7085SHuazhong Tan int ret; 31519c6f7085SHuazhong Tan 3152e2cb1decSSalil Mehta ret = hclgevf_pci_init(hdev); 315360df7e91SHuazhong Tan if (ret) 3154e2cb1decSSalil Mehta return ret; 3155e2cb1decSSalil Mehta 31568b0195a3SHuazhong Tan ret = hclgevf_cmd_queue_init(hdev); 315760df7e91SHuazhong Tan if (ret) 31588b0195a3SHuazhong Tan goto err_cmd_queue_init; 31598b0195a3SHuazhong Tan 3160eddf0462SYunsheng Lin ret = hclgevf_cmd_init(hdev); 3161eddf0462SYunsheng Lin if (ret) 3162eddf0462SYunsheng Lin goto err_cmd_init; 3163eddf0462SYunsheng Lin 316407acf909SJian Shen /* Get vf resource */ 316507acf909SJian Shen ret = hclgevf_query_vf_resource(hdev); 316660df7e91SHuazhong Tan if (ret) 31678b0195a3SHuazhong Tan goto err_cmd_init; 316807acf909SJian Shen 3169af2aedc5SGuangbin Huang ret = hclgevf_query_dev_specs(hdev); 3170af2aedc5SGuangbin Huang if (ret) { 3171af2aedc5SGuangbin Huang dev_err(&pdev->dev, 3172af2aedc5SGuangbin Huang "failed to query dev specifications, ret = %d\n", ret); 3173af2aedc5SGuangbin Huang goto err_cmd_init; 3174af2aedc5SGuangbin Huang } 3175af2aedc5SGuangbin Huang 317607acf909SJian Shen ret = hclgevf_init_msi(hdev); 317707acf909SJian Shen if (ret) { 317807acf909SJian Shen dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 31798b0195a3SHuazhong Tan goto err_cmd_init; 318007acf909SJian Shen } 318107acf909SJian Shen 318207acf909SJian Shen hclgevf_state_init(hdev); 3183dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 3184afb6afdbSHuazhong Tan hdev->reset_type = HNAE3_NONE_RESET; 318507acf909SJian Shen 3186e2cb1decSSalil Mehta ret = hclgevf_misc_irq_init(hdev); 318760df7e91SHuazhong Tan if (ret) 3188e2cb1decSSalil Mehta goto err_misc_irq_init; 3189e2cb1decSSalil Mehta 3190862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3191862d969aSHuazhong Tan 3192e2cb1decSSalil Mehta ret = hclgevf_configure(hdev); 3193e2cb1decSSalil Mehta if (ret) { 3194e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 3195e2cb1decSSalil Mehta goto err_config; 3196e2cb1decSSalil Mehta } 3197e2cb1decSSalil Mehta 3198e2cb1decSSalil Mehta ret = hclgevf_alloc_tqps(hdev); 3199e2cb1decSSalil Mehta if (ret) { 3200e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 3201e2cb1decSSalil Mehta goto err_config; 3202e2cb1decSSalil Mehta } 3203e2cb1decSSalil Mehta 3204e2cb1decSSalil Mehta ret = hclgevf_set_handle_info(hdev); 320560df7e91SHuazhong Tan if (ret) 3206e2cb1decSSalil Mehta goto err_config; 3207e2cb1decSSalil Mehta 3208b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 3209b26a6feaSPeng Li if (ret) 3210b26a6feaSPeng Li goto err_config; 3211b26a6feaSPeng Li 3212e2cb1decSSalil Mehta /* Initialize RSS for this VF */ 3213944de484SGuojia Liao hclgevf_rss_init_cfg(hdev); 3214e2cb1decSSalil Mehta ret = hclgevf_rss_init_hw(hdev); 3215e2cb1decSSalil Mehta if (ret) { 3216e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 3217e2cb1decSSalil Mehta "failed(%d) to initialize RSS\n", ret); 3218e2cb1decSSalil Mehta goto err_config; 3219e2cb1decSSalil Mehta } 3220e2cb1decSSalil Mehta 3221039ba863SJian Shen /* ensure vf tbl list as empty before init*/ 3222039ba863SJian Shen ret = hclgevf_clear_vport_list(hdev); 3223039ba863SJian Shen if (ret) { 3224039ba863SJian Shen dev_err(&pdev->dev, 3225039ba863SJian Shen "failed to clear tbl list configuration, ret = %d.\n", 3226039ba863SJian Shen ret); 3227039ba863SJian Shen goto err_config; 3228039ba863SJian Shen } 3229039ba863SJian Shen 3230e2cb1decSSalil Mehta ret = hclgevf_init_vlan_config(hdev); 3231e2cb1decSSalil Mehta if (ret) { 3232e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 3233e2cb1decSSalil Mehta "failed(%d) to initialize VLAN config\n", ret); 3234e2cb1decSSalil Mehta goto err_config; 3235e2cb1decSSalil Mehta } 3236e2cb1decSSalil Mehta 32370742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 323808d80a4cSHuazhong Tan dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 323908d80a4cSHuazhong Tan HCLGEVF_DRIVER_NAME); 3240e2cb1decSSalil Mehta 3241ff200099SYunsheng Lin hclgevf_task_schedule(hdev, round_jiffies_relative(HZ)); 3242ff200099SYunsheng Lin 3243e2cb1decSSalil Mehta return 0; 3244e2cb1decSSalil Mehta 3245e2cb1decSSalil Mehta err_config: 3246e2cb1decSSalil Mehta hclgevf_misc_irq_uninit(hdev); 3247e2cb1decSSalil Mehta err_misc_irq_init: 3248e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 3249e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 325007acf909SJian Shen err_cmd_init: 32518b0195a3SHuazhong Tan hclgevf_cmd_uninit(hdev); 32528b0195a3SHuazhong Tan err_cmd_queue_init: 3253e2cb1decSSalil Mehta hclgevf_pci_uninit(hdev); 3254862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3255e2cb1decSSalil Mehta return ret; 3256e2cb1decSSalil Mehta } 3257e2cb1decSSalil Mehta 32587a01c897SSalil Mehta static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 3259e2cb1decSSalil Mehta { 3260d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 3261d3410018SYufeng Mo 3262e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 3263862d969aSHuazhong Tan 3264d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_VF_UNINIT, 0); 3265d3410018SYufeng Mo hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 326623b4201dSJian Shen 3267862d969aSHuazhong Tan if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3268eddf0462SYunsheng Lin hclgevf_misc_irq_uninit(hdev); 3269e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 32707a01c897SSalil Mehta } 32717a01c897SSalil Mehta 3272862d969aSHuazhong Tan hclgevf_cmd_uninit(hdev); 3273e3364c5fSZenghui Yu hclgevf_pci_uninit(hdev); 3274ee4bcd3bSJian Shen hclgevf_uninit_mac_list(hdev); 3275862d969aSHuazhong Tan } 3276862d969aSHuazhong Tan 32777a01c897SSalil Mehta static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 32787a01c897SSalil Mehta { 32797a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 32807a01c897SSalil Mehta int ret; 32817a01c897SSalil Mehta 32827a01c897SSalil Mehta ret = hclgevf_alloc_hdev(ae_dev); 32837a01c897SSalil Mehta if (ret) { 32847a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device allocation failed\n"); 32857a01c897SSalil Mehta return ret; 32867a01c897SSalil Mehta } 32877a01c897SSalil Mehta 32887a01c897SSalil Mehta ret = hclgevf_init_hdev(ae_dev->priv); 3289a6d818e3SYunsheng Lin if (ret) { 32907a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device initialization failed\n"); 32917a01c897SSalil Mehta return ret; 32927a01c897SSalil Mehta } 32937a01c897SSalil Mehta 3294a6d818e3SYunsheng Lin return 0; 3295a6d818e3SYunsheng Lin } 3296a6d818e3SYunsheng Lin 32977a01c897SSalil Mehta static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 32987a01c897SSalil Mehta { 32997a01c897SSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 33007a01c897SSalil Mehta 33017a01c897SSalil Mehta hclgevf_uninit_hdev(hdev); 3302e2cb1decSSalil Mehta ae_dev->priv = NULL; 3303e2cb1decSSalil Mehta } 3304e2cb1decSSalil Mehta 3305849e4607SPeng Li static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 3306849e4607SPeng Li { 3307849e4607SPeng Li struct hnae3_handle *nic = &hdev->nic; 3308849e4607SPeng Li struct hnae3_knic_private_info *kinfo = &nic->kinfo; 3309849e4607SPeng Li 33108be73621SHuazhong Tan return min_t(u32, hdev->rss_size_max, 33118be73621SHuazhong Tan hdev->num_tqps / kinfo->num_tc); 3312849e4607SPeng Li } 3313849e4607SPeng Li 3314849e4607SPeng Li /** 3315849e4607SPeng Li * hclgevf_get_channels - Get the current channels enabled and max supported. 3316849e4607SPeng Li * @handle: hardware information for network interface 3317849e4607SPeng Li * @ch: ethtool channels structure 3318849e4607SPeng Li * 3319849e4607SPeng Li * We don't support separate tx and rx queues as channels. The other count 3320849e4607SPeng Li * represents how many queues are being used for control. max_combined counts 3321849e4607SPeng Li * how many queue pairs we can support. They may not be mapped 1 to 1 with 3322849e4607SPeng Li * q_vectors since we support a lot more queue pairs than q_vectors. 3323849e4607SPeng Li **/ 3324849e4607SPeng Li static void hclgevf_get_channels(struct hnae3_handle *handle, 3325849e4607SPeng Li struct ethtool_channels *ch) 3326849e4607SPeng Li { 3327849e4607SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3328849e4607SPeng Li 3329849e4607SPeng Li ch->max_combined = hclgevf_get_max_channels(hdev); 3330849e4607SPeng Li ch->other_count = 0; 3331849e4607SPeng Li ch->max_other = 0; 33328be73621SHuazhong Tan ch->combined_count = handle->kinfo.rss_size; 3333849e4607SPeng Li } 3334849e4607SPeng Li 3335cc719218SPeng Li static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 33360d43bf45SHuazhong Tan u16 *alloc_tqps, u16 *max_rss_size) 3337cc719218SPeng Li { 3338cc719218SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3339cc719218SPeng Li 33400d43bf45SHuazhong Tan *alloc_tqps = hdev->num_tqps; 3341cc719218SPeng Li *max_rss_size = hdev->rss_size_max; 3342cc719218SPeng Li } 3343cc719218SPeng Li 33444093d1a2SGuangbin Huang static void hclgevf_update_rss_size(struct hnae3_handle *handle, 33454093d1a2SGuangbin Huang u32 new_tqps_num) 33464093d1a2SGuangbin Huang { 33474093d1a2SGuangbin Huang struct hnae3_knic_private_info *kinfo = &handle->kinfo; 33484093d1a2SGuangbin Huang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 33494093d1a2SGuangbin Huang u16 max_rss_size; 33504093d1a2SGuangbin Huang 33514093d1a2SGuangbin Huang kinfo->req_rss_size = new_tqps_num; 33524093d1a2SGuangbin Huang 33534093d1a2SGuangbin Huang max_rss_size = min_t(u16, hdev->rss_size_max, 33544093d1a2SGuangbin Huang hdev->num_tqps / kinfo->num_tc); 33554093d1a2SGuangbin Huang 33564093d1a2SGuangbin Huang /* Use the user's configuration when it is not larger than 33574093d1a2SGuangbin Huang * max_rss_size, otherwise, use the maximum specification value. 33584093d1a2SGuangbin Huang */ 33594093d1a2SGuangbin Huang if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 33604093d1a2SGuangbin Huang kinfo->req_rss_size <= max_rss_size) 33614093d1a2SGuangbin Huang kinfo->rss_size = kinfo->req_rss_size; 33624093d1a2SGuangbin Huang else if (kinfo->rss_size > max_rss_size || 33634093d1a2SGuangbin Huang (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) 33644093d1a2SGuangbin Huang kinfo->rss_size = max_rss_size; 33654093d1a2SGuangbin Huang 33664093d1a2SGuangbin Huang kinfo->num_tqps = kinfo->num_tc * kinfo->rss_size; 33674093d1a2SGuangbin Huang } 33684093d1a2SGuangbin Huang 33694093d1a2SGuangbin Huang static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 33704093d1a2SGuangbin Huang bool rxfh_configured) 33714093d1a2SGuangbin Huang { 33724093d1a2SGuangbin Huang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 33734093d1a2SGuangbin Huang struct hnae3_knic_private_info *kinfo = &handle->kinfo; 33744093d1a2SGuangbin Huang u16 cur_rss_size = kinfo->rss_size; 33754093d1a2SGuangbin Huang u16 cur_tqps = kinfo->num_tqps; 33764093d1a2SGuangbin Huang u32 *rss_indir; 33774093d1a2SGuangbin Huang unsigned int i; 33784093d1a2SGuangbin Huang int ret; 33794093d1a2SGuangbin Huang 33804093d1a2SGuangbin Huang hclgevf_update_rss_size(handle, new_tqps_num); 33814093d1a2SGuangbin Huang 33824093d1a2SGuangbin Huang ret = hclgevf_set_rss_tc_mode(hdev, kinfo->rss_size); 33834093d1a2SGuangbin Huang if (ret) 33844093d1a2SGuangbin Huang return ret; 33854093d1a2SGuangbin Huang 33864093d1a2SGuangbin Huang /* RSS indirection table has been configuared by user */ 33874093d1a2SGuangbin Huang if (rxfh_configured) 33884093d1a2SGuangbin Huang goto out; 33894093d1a2SGuangbin Huang 33904093d1a2SGuangbin Huang /* Reinitializes the rss indirect table according to the new RSS size */ 33914093d1a2SGuangbin Huang rss_indir = kcalloc(HCLGEVF_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL); 33924093d1a2SGuangbin Huang if (!rss_indir) 33934093d1a2SGuangbin Huang return -ENOMEM; 33944093d1a2SGuangbin Huang 33954093d1a2SGuangbin Huang for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 33964093d1a2SGuangbin Huang rss_indir[i] = i % kinfo->rss_size; 33974093d1a2SGuangbin Huang 3398944de484SGuojia Liao hdev->rss_cfg.rss_size = kinfo->rss_size; 3399944de484SGuojia Liao 34004093d1a2SGuangbin Huang ret = hclgevf_set_rss(handle, rss_indir, NULL, 0); 34014093d1a2SGuangbin Huang if (ret) 34024093d1a2SGuangbin Huang dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 34034093d1a2SGuangbin Huang ret); 34044093d1a2SGuangbin Huang 34054093d1a2SGuangbin Huang kfree(rss_indir); 34064093d1a2SGuangbin Huang 34074093d1a2SGuangbin Huang out: 34084093d1a2SGuangbin Huang if (!ret) 34094093d1a2SGuangbin Huang dev_info(&hdev->pdev->dev, 34104093d1a2SGuangbin Huang "Channels changed, rss_size from %u to %u, tqps from %u to %u", 34114093d1a2SGuangbin Huang cur_rss_size, kinfo->rss_size, 34124093d1a2SGuangbin Huang cur_tqps, kinfo->rss_size * kinfo->num_tc); 34134093d1a2SGuangbin Huang 34144093d1a2SGuangbin Huang return ret; 34154093d1a2SGuangbin Huang } 34164093d1a2SGuangbin Huang 3417175ec96bSFuyun Liang static int hclgevf_get_status(struct hnae3_handle *handle) 3418175ec96bSFuyun Liang { 3419175ec96bSFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3420175ec96bSFuyun Liang 3421175ec96bSFuyun Liang return hdev->hw.mac.link; 3422175ec96bSFuyun Liang } 3423175ec96bSFuyun Liang 34244a152de9SFuyun Liang static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 34254a152de9SFuyun Liang u8 *auto_neg, u32 *speed, 34264a152de9SFuyun Liang u8 *duplex) 34274a152de9SFuyun Liang { 34284a152de9SFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 34294a152de9SFuyun Liang 34304a152de9SFuyun Liang if (speed) 34314a152de9SFuyun Liang *speed = hdev->hw.mac.speed; 34324a152de9SFuyun Liang if (duplex) 34334a152de9SFuyun Liang *duplex = hdev->hw.mac.duplex; 34344a152de9SFuyun Liang if (auto_neg) 34354a152de9SFuyun Liang *auto_neg = AUTONEG_DISABLE; 34364a152de9SFuyun Liang } 34374a152de9SFuyun Liang 34384a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 34394a152de9SFuyun Liang u8 duplex) 34404a152de9SFuyun Liang { 34414a152de9SFuyun Liang hdev->hw.mac.speed = speed; 34424a152de9SFuyun Liang hdev->hw.mac.duplex = duplex; 34434a152de9SFuyun Liang } 34444a152de9SFuyun Liang 34451731be4cSYonglong Liu static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 34465c9f6b39SPeng Li { 34475c9f6b39SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 34485c9f6b39SPeng Li 34495c9f6b39SPeng Li return hclgevf_config_gro(hdev, enable); 34505c9f6b39SPeng Li } 34515c9f6b39SPeng Li 345288d10bd6SJian Shen static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 345388d10bd6SJian Shen u8 *module_type) 3454c136b884SPeng Li { 3455c136b884SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 345688d10bd6SJian Shen 3457c136b884SPeng Li if (media_type) 3458c136b884SPeng Li *media_type = hdev->hw.mac.media_type; 345988d10bd6SJian Shen 346088d10bd6SJian Shen if (module_type) 346188d10bd6SJian Shen *module_type = hdev->hw.mac.module_type; 3462c136b884SPeng Li } 3463c136b884SPeng Li 34644d60291bSHuazhong Tan static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 34654d60291bSHuazhong Tan { 34664d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 34674d60291bSHuazhong Tan 3468aa5c4f17SHuazhong Tan return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 34694d60291bSHuazhong Tan } 34704d60291bSHuazhong Tan 3471fe735c84SHuazhong Tan static bool hclgevf_get_cmdq_stat(struct hnae3_handle *handle) 3472fe735c84SHuazhong Tan { 3473fe735c84SHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3474fe735c84SHuazhong Tan 3475fe735c84SHuazhong Tan return test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 3476fe735c84SHuazhong Tan } 3477fe735c84SHuazhong Tan 34784d60291bSHuazhong Tan static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 34794d60291bSHuazhong Tan { 34804d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 34814d60291bSHuazhong Tan 34824d60291bSHuazhong Tan return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 34834d60291bSHuazhong Tan } 34844d60291bSHuazhong Tan 34854d60291bSHuazhong Tan static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 34864d60291bSHuazhong Tan { 34874d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 34884d60291bSHuazhong Tan 3489c88a6e7dSHuazhong Tan return hdev->rst_stats.hw_rst_done_cnt; 34904d60291bSHuazhong Tan } 34914d60291bSHuazhong Tan 34929194d18bSliuzhongzhu static void hclgevf_get_link_mode(struct hnae3_handle *handle, 34939194d18bSliuzhongzhu unsigned long *supported, 34949194d18bSliuzhongzhu unsigned long *advertising) 34959194d18bSliuzhongzhu { 34969194d18bSliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 34979194d18bSliuzhongzhu 34989194d18bSliuzhongzhu *supported = hdev->hw.mac.supported; 34999194d18bSliuzhongzhu *advertising = hdev->hw.mac.advertising; 35009194d18bSliuzhongzhu } 35019194d18bSliuzhongzhu 35021600c3e5SJian Shen #define MAX_SEPARATE_NUM 4 35031600c3e5SJian Shen #define SEPARATOR_VALUE 0xFFFFFFFF 35041600c3e5SJian Shen #define REG_NUM_PER_LINE 4 35051600c3e5SJian Shen #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 35061600c3e5SJian Shen 35071600c3e5SJian Shen static int hclgevf_get_regs_len(struct hnae3_handle *handle) 35081600c3e5SJian Shen { 35091600c3e5SJian Shen int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 35101600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 35111600c3e5SJian Shen 35121600c3e5SJian Shen cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 35131600c3e5SJian Shen common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 35141600c3e5SJian Shen ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 35151600c3e5SJian Shen tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 35161600c3e5SJian Shen 35171600c3e5SJian Shen return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 35181600c3e5SJian Shen tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 35191600c3e5SJian Shen } 35201600c3e5SJian Shen 35211600c3e5SJian Shen static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 35221600c3e5SJian Shen void *data) 35231600c3e5SJian Shen { 35241600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 35251600c3e5SJian Shen int i, j, reg_um, separator_num; 35261600c3e5SJian Shen u32 *reg = data; 35271600c3e5SJian Shen 35281600c3e5SJian Shen *version = hdev->fw_version; 35291600c3e5SJian Shen 35301600c3e5SJian Shen /* fetching per-VF registers values from VF PCIe register space */ 35311600c3e5SJian Shen reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 35321600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 35331600c3e5SJian Shen for (i = 0; i < reg_um; i++) 35341600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 35351600c3e5SJian Shen for (i = 0; i < separator_num; i++) 35361600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 35371600c3e5SJian Shen 35381600c3e5SJian Shen reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 35391600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 35401600c3e5SJian Shen for (i = 0; i < reg_um; i++) 35411600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 35421600c3e5SJian Shen for (i = 0; i < separator_num; i++) 35431600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 35441600c3e5SJian Shen 35451600c3e5SJian Shen reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 35461600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 35471600c3e5SJian Shen for (j = 0; j < hdev->num_tqps; j++) { 35481600c3e5SJian Shen for (i = 0; i < reg_um; i++) 35491600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 35501600c3e5SJian Shen ring_reg_addr_list[i] + 35511600c3e5SJian Shen 0x200 * j); 35521600c3e5SJian Shen for (i = 0; i < separator_num; i++) 35531600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 35541600c3e5SJian Shen } 35551600c3e5SJian Shen 35561600c3e5SJian Shen reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 35571600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 35581600c3e5SJian Shen for (j = 0; j < hdev->num_msi_used - 1; j++) { 35591600c3e5SJian Shen for (i = 0; i < reg_um; i++) 35601600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 35611600c3e5SJian Shen tqp_intr_reg_addr_list[i] + 35621600c3e5SJian Shen 4 * j); 35631600c3e5SJian Shen for (i = 0; i < separator_num; i++) 35641600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 35651600c3e5SJian Shen } 35661600c3e5SJian Shen } 35671600c3e5SJian Shen 356892f11ea1SJian Shen void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 356992f11ea1SJian Shen u8 *port_base_vlan_info, u8 data_size) 357092f11ea1SJian Shen { 357192f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 3572d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 3573a6f7bfdcSJian Shen int ret; 357492f11ea1SJian Shen 357592f11ea1SJian Shen rtnl_lock(); 3576a6f7bfdcSJian Shen 3577b7b5d25bSGuojia Liao if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 3578b7b5d25bSGuojia Liao test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) { 3579a6f7bfdcSJian Shen dev_warn(&hdev->pdev->dev, 3580a6f7bfdcSJian Shen "is resetting when updating port based vlan info\n"); 358192f11ea1SJian Shen rtnl_unlock(); 3582a6f7bfdcSJian Shen return; 3583a6f7bfdcSJian Shen } 3584a6f7bfdcSJian Shen 3585a6f7bfdcSJian Shen ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 3586a6f7bfdcSJian Shen if (ret) { 3587a6f7bfdcSJian Shen rtnl_unlock(); 3588a6f7bfdcSJian Shen return; 3589a6f7bfdcSJian Shen } 359092f11ea1SJian Shen 359192f11ea1SJian Shen /* send msg to PF and wait update port based vlan info */ 3592d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 3593d3410018SYufeng Mo HCLGE_MBX_PORT_BASE_VLAN_CFG); 3594d3410018SYufeng Mo memcpy(send_msg.data, port_base_vlan_info, data_size); 3595a6f7bfdcSJian Shen ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3596a6f7bfdcSJian Shen if (!ret) { 359792f11ea1SJian Shen if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 3598a6f7bfdcSJian Shen nic->port_base_vlan_state = state; 359992f11ea1SJian Shen else 360092f11ea1SJian Shen nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 3601a6f7bfdcSJian Shen } 360292f11ea1SJian Shen 360392f11ea1SJian Shen hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 360492f11ea1SJian Shen rtnl_unlock(); 360592f11ea1SJian Shen } 360692f11ea1SJian Shen 3607e2cb1decSSalil Mehta static const struct hnae3_ae_ops hclgevf_ops = { 3608e2cb1decSSalil Mehta .init_ae_dev = hclgevf_init_ae_dev, 3609e2cb1decSSalil Mehta .uninit_ae_dev = hclgevf_uninit_ae_dev, 36106ff3cf07SHuazhong Tan .flr_prepare = hclgevf_flr_prepare, 36116ff3cf07SHuazhong Tan .flr_done = hclgevf_flr_done, 3612e718a93fSPeng Li .init_client_instance = hclgevf_init_client_instance, 3613e718a93fSPeng Li .uninit_client_instance = hclgevf_uninit_client_instance, 3614e2cb1decSSalil Mehta .start = hclgevf_ae_start, 3615e2cb1decSSalil Mehta .stop = hclgevf_ae_stop, 3616a6d818e3SYunsheng Lin .client_start = hclgevf_client_start, 3617a6d818e3SYunsheng Lin .client_stop = hclgevf_client_stop, 3618e2cb1decSSalil Mehta .map_ring_to_vector = hclgevf_map_ring_to_vector, 3619e2cb1decSSalil Mehta .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 3620e2cb1decSSalil Mehta .get_vector = hclgevf_get_vector, 36210d3e6631SYunsheng Lin .put_vector = hclgevf_put_vector, 3622e2cb1decSSalil Mehta .reset_queue = hclgevf_reset_tqp, 3623e2cb1decSSalil Mehta .get_mac_addr = hclgevf_get_mac_addr, 3624e2cb1decSSalil Mehta .set_mac_addr = hclgevf_set_mac_addr, 3625e2cb1decSSalil Mehta .add_uc_addr = hclgevf_add_uc_addr, 3626e2cb1decSSalil Mehta .rm_uc_addr = hclgevf_rm_uc_addr, 3627e2cb1decSSalil Mehta .add_mc_addr = hclgevf_add_mc_addr, 3628e2cb1decSSalil Mehta .rm_mc_addr = hclgevf_rm_mc_addr, 3629e2cb1decSSalil Mehta .get_stats = hclgevf_get_stats, 3630e2cb1decSSalil Mehta .update_stats = hclgevf_update_stats, 3631e2cb1decSSalil Mehta .get_strings = hclgevf_get_strings, 3632e2cb1decSSalil Mehta .get_sset_count = hclgevf_get_sset_count, 3633e2cb1decSSalil Mehta .get_rss_key_size = hclgevf_get_rss_key_size, 3634e2cb1decSSalil Mehta .get_rss_indir_size = hclgevf_get_rss_indir_size, 3635e2cb1decSSalil Mehta .get_rss = hclgevf_get_rss, 3636e2cb1decSSalil Mehta .set_rss = hclgevf_set_rss, 3637d97b3072SJian Shen .get_rss_tuple = hclgevf_get_rss_tuple, 3638d97b3072SJian Shen .set_rss_tuple = hclgevf_set_rss_tuple, 3639e2cb1decSSalil Mehta .get_tc_size = hclgevf_get_tc_size, 3640e2cb1decSSalil Mehta .get_fw_version = hclgevf_get_fw_version, 3641e2cb1decSSalil Mehta .set_vlan_filter = hclgevf_set_vlan_filter, 3642b2641e2aSYunsheng Lin .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 36436d4c3981SSalil Mehta .reset_event = hclgevf_reset_event, 3644720bd583SHuazhong Tan .set_default_reset_request = hclgevf_set_def_reset_request, 36454093d1a2SGuangbin Huang .set_channels = hclgevf_set_channels, 3646849e4607SPeng Li .get_channels = hclgevf_get_channels, 3647cc719218SPeng Li .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 36481600c3e5SJian Shen .get_regs_len = hclgevf_get_regs_len, 36491600c3e5SJian Shen .get_regs = hclgevf_get_regs, 3650175ec96bSFuyun Liang .get_status = hclgevf_get_status, 36514a152de9SFuyun Liang .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3652c136b884SPeng Li .get_media_type = hclgevf_get_media_type, 36534d60291bSHuazhong Tan .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 36544d60291bSHuazhong Tan .ae_dev_resetting = hclgevf_ae_dev_resetting, 36554d60291bSHuazhong Tan .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 36565c9f6b39SPeng Li .set_gro_en = hclgevf_gro_en, 3657818f1675SYunsheng Lin .set_mtu = hclgevf_set_mtu, 36580c29d191Sliuzhongzhu .get_global_queue_id = hclgevf_get_qid_global, 36598cdb992fSJian Shen .set_timer_task = hclgevf_set_timer_task, 36609194d18bSliuzhongzhu .get_link_mode = hclgevf_get_link_mode, 3661e196ec75SJian Shen .set_promisc_mode = hclgevf_set_promisc_mode, 3662c631c696SJian Shen .request_update_promisc_mode = hclgevf_request_update_promisc_mode, 3663fe735c84SHuazhong Tan .get_cmdq_stat = hclgevf_get_cmdq_stat, 3664e2cb1decSSalil Mehta }; 3665e2cb1decSSalil Mehta 3666e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf = { 3667e2cb1decSSalil Mehta .ops = &hclgevf_ops, 3668e2cb1decSSalil Mehta .pdev_id_table = ae_algovf_pci_tbl, 3669e2cb1decSSalil Mehta }; 3670e2cb1decSSalil Mehta 3671e2cb1decSSalil Mehta static int hclgevf_init(void) 3672e2cb1decSSalil Mehta { 3673e2cb1decSSalil Mehta pr_info("%s is initializing\n", HCLGEVF_NAME); 3674e2cb1decSSalil Mehta 367516deaef2SYunsheng Lin hclgevf_wq = alloc_workqueue("%s", 0, 0, HCLGEVF_NAME); 36760ea68902SYunsheng Lin if (!hclgevf_wq) { 36770ea68902SYunsheng Lin pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME); 36780ea68902SYunsheng Lin return -ENOMEM; 36790ea68902SYunsheng Lin } 36800ea68902SYunsheng Lin 3681854cf33aSFuyun Liang hnae3_register_ae_algo(&ae_algovf); 3682854cf33aSFuyun Liang 3683854cf33aSFuyun Liang return 0; 3684e2cb1decSSalil Mehta } 3685e2cb1decSSalil Mehta 3686e2cb1decSSalil Mehta static void hclgevf_exit(void) 3687e2cb1decSSalil Mehta { 3688e2cb1decSSalil Mehta hnae3_unregister_ae_algo(&ae_algovf); 36890ea68902SYunsheng Lin destroy_workqueue(hclgevf_wq); 3690e2cb1decSSalil Mehta } 3691e2cb1decSSalil Mehta module_init(hclgevf_init); 3692e2cb1decSSalil Mehta module_exit(hclgevf_exit); 3693e2cb1decSSalil Mehta 3694e2cb1decSSalil Mehta MODULE_LICENSE("GPL"); 3695e2cb1decSSalil Mehta MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3696e2cb1decSSalil Mehta MODULE_DESCRIPTION("HCLGEVF Driver"); 3697e2cb1decSSalil Mehta MODULE_VERSION(HCLGEVF_MOD_VERSION); 3698