1e2cb1decSSalil Mehta // SPDX-License-Identifier: GPL-2.0+ 2e2cb1decSSalil Mehta // Copyright (c) 2016-2017 Hisilicon Limited. 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #include <linux/etherdevice.h> 5aa5c4f17SHuazhong Tan #include <linux/iopoll.h> 66988eb2aSSalil Mehta #include <net/rtnetlink.h> 7e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 8e2cb1decSSalil Mehta #include "hclgevf_main.h" 9e2cb1decSSalil Mehta #include "hclge_mbx.h" 10e2cb1decSSalil Mehta #include "hnae3.h" 11e2cb1decSSalil Mehta 12e2cb1decSSalil Mehta #define HCLGEVF_NAME "hclgevf" 13e2cb1decSSalil Mehta 149c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 15e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf; 16e2cb1decSSalil Mehta 17e2cb1decSSalil Mehta static const struct pci_device_id ae_algovf_pci_tbl[] = { 18e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 19e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 20e2cb1decSSalil Mehta /* required last entry */ 21e2cb1decSSalil Mehta {0, } 22e2cb1decSSalil Mehta }; 23e2cb1decSSalil Mehta 24472d7eceSJian Shen static const u8 hclgevf_hash_key[] = { 25472d7eceSJian Shen 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 26472d7eceSJian Shen 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 27472d7eceSJian Shen 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 28472d7eceSJian Shen 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 29472d7eceSJian Shen 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 30472d7eceSJian Shen }; 31472d7eceSJian Shen 322f550a46SYunsheng Lin MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 332f550a46SYunsheng Lin 341600c3e5SJian Shen static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 351600c3e5SJian Shen HCLGEVF_CMDQ_TX_ADDR_H_REG, 361600c3e5SJian Shen HCLGEVF_CMDQ_TX_DEPTH_REG, 371600c3e5SJian Shen HCLGEVF_CMDQ_TX_TAIL_REG, 381600c3e5SJian Shen HCLGEVF_CMDQ_TX_HEAD_REG, 391600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_L_REG, 401600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_H_REG, 411600c3e5SJian Shen HCLGEVF_CMDQ_RX_DEPTH_REG, 421600c3e5SJian Shen HCLGEVF_CMDQ_RX_TAIL_REG, 431600c3e5SJian Shen HCLGEVF_CMDQ_RX_HEAD_REG, 441600c3e5SJian Shen HCLGEVF_VECTOR0_CMDQ_SRC_REG, 451600c3e5SJian Shen HCLGEVF_CMDQ_INTR_STS_REG, 461600c3e5SJian Shen HCLGEVF_CMDQ_INTR_EN_REG, 471600c3e5SJian Shen HCLGEVF_CMDQ_INTR_GEN_REG}; 481600c3e5SJian Shen 491600c3e5SJian Shen static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 501600c3e5SJian Shen HCLGEVF_RST_ING, 511600c3e5SJian Shen HCLGEVF_GRO_EN_REG}; 521600c3e5SJian Shen 531600c3e5SJian Shen static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 541600c3e5SJian Shen HCLGEVF_RING_RX_ADDR_H_REG, 551600c3e5SJian Shen HCLGEVF_RING_RX_BD_NUM_REG, 561600c3e5SJian Shen HCLGEVF_RING_RX_BD_LENGTH_REG, 571600c3e5SJian Shen HCLGEVF_RING_RX_MERGE_EN_REG, 581600c3e5SJian Shen HCLGEVF_RING_RX_TAIL_REG, 591600c3e5SJian Shen HCLGEVF_RING_RX_HEAD_REG, 601600c3e5SJian Shen HCLGEVF_RING_RX_FBD_NUM_REG, 611600c3e5SJian Shen HCLGEVF_RING_RX_OFFSET_REG, 621600c3e5SJian Shen HCLGEVF_RING_RX_FBD_OFFSET_REG, 631600c3e5SJian Shen HCLGEVF_RING_RX_STASH_REG, 641600c3e5SJian Shen HCLGEVF_RING_RX_BD_ERR_REG, 651600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_L_REG, 661600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_H_REG, 671600c3e5SJian Shen HCLGEVF_RING_TX_BD_NUM_REG, 681600c3e5SJian Shen HCLGEVF_RING_TX_PRIORITY_REG, 691600c3e5SJian Shen HCLGEVF_RING_TX_TC_REG, 701600c3e5SJian Shen HCLGEVF_RING_TX_MERGE_EN_REG, 711600c3e5SJian Shen HCLGEVF_RING_TX_TAIL_REG, 721600c3e5SJian Shen HCLGEVF_RING_TX_HEAD_REG, 731600c3e5SJian Shen HCLGEVF_RING_TX_FBD_NUM_REG, 741600c3e5SJian Shen HCLGEVF_RING_TX_OFFSET_REG, 751600c3e5SJian Shen HCLGEVF_RING_TX_EBD_NUM_REG, 761600c3e5SJian Shen HCLGEVF_RING_TX_EBD_OFFSET_REG, 771600c3e5SJian Shen HCLGEVF_RING_TX_BD_ERR_REG, 781600c3e5SJian Shen HCLGEVF_RING_EN_REG}; 791600c3e5SJian Shen 801600c3e5SJian Shen static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 811600c3e5SJian Shen HCLGEVF_TQP_INTR_GL0_REG, 821600c3e5SJian Shen HCLGEVF_TQP_INTR_GL1_REG, 831600c3e5SJian Shen HCLGEVF_TQP_INTR_GL2_REG, 841600c3e5SJian Shen HCLGEVF_TQP_INTR_RL_REG}; 851600c3e5SJian Shen 86e2cb1decSSalil Mehta static inline struct hclgevf_dev *hclgevf_ae_get_hdev( 87e2cb1decSSalil Mehta struct hnae3_handle *handle) 88e2cb1decSSalil Mehta { 89eed9535fSPeng Li if (!handle->client) 90eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, nic); 91eed9535fSPeng Li else if (handle->client->type == HNAE3_CLIENT_ROCE) 92eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, roce); 93eed9535fSPeng Li else 94e2cb1decSSalil Mehta return container_of(handle, struct hclgevf_dev, nic); 95e2cb1decSSalil Mehta } 96e2cb1decSSalil Mehta 97e2cb1decSSalil Mehta static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 98e2cb1decSSalil Mehta { 99b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 100e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 101e2cb1decSSalil Mehta struct hclgevf_desc desc; 102e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 103e2cb1decSSalil Mehta int status; 104e2cb1decSSalil Mehta int i; 105e2cb1decSSalil Mehta 106b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 107b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 108e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 109e2cb1decSSalil Mehta HCLGEVF_OPC_QUERY_RX_STATUS, 110e2cb1decSSalil Mehta true); 111e2cb1decSSalil Mehta 112e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 113e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 114e2cb1decSSalil Mehta if (status) { 115e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 116e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 117e2cb1decSSalil Mehta status, i); 118e2cb1decSSalil Mehta return status; 119e2cb1decSSalil Mehta } 120e2cb1decSSalil Mehta tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 121cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 122e2cb1decSSalil Mehta 123e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 124e2cb1decSSalil Mehta true); 125e2cb1decSSalil Mehta 126e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 127e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 128e2cb1decSSalil Mehta if (status) { 129e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 130e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 131e2cb1decSSalil Mehta status, i); 132e2cb1decSSalil Mehta return status; 133e2cb1decSSalil Mehta } 134e2cb1decSSalil Mehta tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 135cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 136e2cb1decSSalil Mehta } 137e2cb1decSSalil Mehta 138e2cb1decSSalil Mehta return 0; 139e2cb1decSSalil Mehta } 140e2cb1decSSalil Mehta 141e2cb1decSSalil Mehta static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 142e2cb1decSSalil Mehta { 143e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo = &handle->kinfo; 144e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 145e2cb1decSSalil Mehta u64 *buff = data; 146e2cb1decSSalil Mehta int i; 147e2cb1decSSalil Mehta 148b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 149b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 150e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 151e2cb1decSSalil Mehta } 152e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 153b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 154e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 155e2cb1decSSalil Mehta } 156e2cb1decSSalil Mehta 157e2cb1decSSalil Mehta return buff; 158e2cb1decSSalil Mehta } 159e2cb1decSSalil Mehta 160e2cb1decSSalil Mehta static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 161e2cb1decSSalil Mehta { 162b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 163e2cb1decSSalil Mehta 164b4f1d303SJian Shen return kinfo->num_tqps * 2; 165e2cb1decSSalil Mehta } 166e2cb1decSSalil Mehta 167e2cb1decSSalil Mehta static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 168e2cb1decSSalil Mehta { 169b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 170e2cb1decSSalil Mehta u8 *buff = data; 171e2cb1decSSalil Mehta int i = 0; 172e2cb1decSSalil Mehta 173b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 174b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 175e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1760c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 177e2cb1decSSalil Mehta tqp->index); 178e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 179e2cb1decSSalil Mehta } 180e2cb1decSSalil Mehta 181b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 182b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 183e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1840c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 185e2cb1decSSalil Mehta tqp->index); 186e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 187e2cb1decSSalil Mehta } 188e2cb1decSSalil Mehta 189e2cb1decSSalil Mehta return buff; 190e2cb1decSSalil Mehta } 191e2cb1decSSalil Mehta 192e2cb1decSSalil Mehta static void hclgevf_update_stats(struct hnae3_handle *handle, 193e2cb1decSSalil Mehta struct net_device_stats *net_stats) 194e2cb1decSSalil Mehta { 195e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 196e2cb1decSSalil Mehta int status; 197e2cb1decSSalil Mehta 198e2cb1decSSalil Mehta status = hclgevf_tqps_update_stats(handle); 199e2cb1decSSalil Mehta if (status) 200e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 201e2cb1decSSalil Mehta "VF update of TQPS stats fail, status = %d.\n", 202e2cb1decSSalil Mehta status); 203e2cb1decSSalil Mehta } 204e2cb1decSSalil Mehta 205e2cb1decSSalil Mehta static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 206e2cb1decSSalil Mehta { 207e2cb1decSSalil Mehta if (strset == ETH_SS_TEST) 208e2cb1decSSalil Mehta return -EOPNOTSUPP; 209e2cb1decSSalil Mehta else if (strset == ETH_SS_STATS) 210e2cb1decSSalil Mehta return hclgevf_tqps_get_sset_count(handle, strset); 211e2cb1decSSalil Mehta 212e2cb1decSSalil Mehta return 0; 213e2cb1decSSalil Mehta } 214e2cb1decSSalil Mehta 215e2cb1decSSalil Mehta static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 216e2cb1decSSalil Mehta u8 *data) 217e2cb1decSSalil Mehta { 218e2cb1decSSalil Mehta u8 *p = (char *)data; 219e2cb1decSSalil Mehta 220e2cb1decSSalil Mehta if (strset == ETH_SS_STATS) 221e2cb1decSSalil Mehta p = hclgevf_tqps_get_strings(handle, p); 222e2cb1decSSalil Mehta } 223e2cb1decSSalil Mehta 224e2cb1decSSalil Mehta static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 225e2cb1decSSalil Mehta { 226e2cb1decSSalil Mehta hclgevf_tqps_get_stats(handle, data); 227e2cb1decSSalil Mehta } 228e2cb1decSSalil Mehta 229e2cb1decSSalil Mehta static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 230e2cb1decSSalil Mehta { 231e2cb1decSSalil Mehta u8 resp_msg; 232e2cb1decSSalil Mehta int status; 233e2cb1decSSalil Mehta 234e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 235e2cb1decSSalil Mehta true, &resp_msg, sizeof(u8)); 236e2cb1decSSalil Mehta if (status) { 237e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 238e2cb1decSSalil Mehta "VF request to get TC info from PF failed %d", 239e2cb1decSSalil Mehta status); 240e2cb1decSSalil Mehta return status; 241e2cb1decSSalil Mehta } 242e2cb1decSSalil Mehta 243e2cb1decSSalil Mehta hdev->hw_tc_map = resp_msg; 244e2cb1decSSalil Mehta 245e2cb1decSSalil Mehta return 0; 246e2cb1decSSalil Mehta } 247e2cb1decSSalil Mehta 2486cee6fc3SJian Shen static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 249e2cb1decSSalil Mehta { 250c0425944SPeng Li #define HCLGEVF_TQPS_RSS_INFO_LEN 6 251e2cb1decSSalil Mehta u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 252e2cb1decSSalil Mehta int status; 253e2cb1decSSalil Mehta 254e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 255e2cb1decSSalil Mehta true, resp_msg, 256e2cb1decSSalil Mehta HCLGEVF_TQPS_RSS_INFO_LEN); 257e2cb1decSSalil Mehta if (status) { 258e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 259e2cb1decSSalil Mehta "VF request to get tqp info from PF failed %d", 260e2cb1decSSalil Mehta status); 261e2cb1decSSalil Mehta return status; 262e2cb1decSSalil Mehta } 263e2cb1decSSalil Mehta 264e2cb1decSSalil Mehta memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 265e2cb1decSSalil Mehta memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 266c0425944SPeng Li memcpy(&hdev->rx_buf_len, &resp_msg[4], sizeof(u16)); 267c0425944SPeng Li 268c0425944SPeng Li return 0; 269c0425944SPeng Li } 270c0425944SPeng Li 271c0425944SPeng Li static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 272c0425944SPeng Li { 273c0425944SPeng Li #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 274c0425944SPeng Li u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 275c0425944SPeng Li int ret; 276c0425944SPeng Li 277c0425944SPeng Li ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QDEPTH, 0, NULL, 0, 278c0425944SPeng Li true, resp_msg, 279c0425944SPeng Li HCLGEVF_TQPS_DEPTH_INFO_LEN); 280c0425944SPeng Li if (ret) { 281c0425944SPeng Li dev_err(&hdev->pdev->dev, 282c0425944SPeng Li "VF request to get tqp depth info from PF failed %d", 283c0425944SPeng Li ret); 284c0425944SPeng Li return ret; 285c0425944SPeng Li } 286c0425944SPeng Li 287c0425944SPeng Li memcpy(&hdev->num_tx_desc, &resp_msg[0], sizeof(u16)); 288c0425944SPeng Li memcpy(&hdev->num_rx_desc, &resp_msg[2], sizeof(u16)); 289e2cb1decSSalil Mehta 290e2cb1decSSalil Mehta return 0; 291e2cb1decSSalil Mehta } 292e2cb1decSSalil Mehta 2930c29d191Sliuzhongzhu static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 2940c29d191Sliuzhongzhu { 2950c29d191Sliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2960c29d191Sliuzhongzhu u8 msg_data[2], resp_data[2]; 2970c29d191Sliuzhongzhu u16 qid_in_pf = 0; 2980c29d191Sliuzhongzhu int ret; 2990c29d191Sliuzhongzhu 3000c29d191Sliuzhongzhu memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 3010c29d191Sliuzhongzhu 3020c29d191Sliuzhongzhu ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data, 3030c29d191Sliuzhongzhu 2, true, resp_data, 2); 3040c29d191Sliuzhongzhu if (!ret) 3050c29d191Sliuzhongzhu qid_in_pf = *(u16 *)resp_data; 3060c29d191Sliuzhongzhu 3070c29d191Sliuzhongzhu return qid_in_pf; 3080c29d191Sliuzhongzhu } 3090c29d191Sliuzhongzhu 310e2cb1decSSalil Mehta static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 311e2cb1decSSalil Mehta { 312e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 313e2cb1decSSalil Mehta int i; 314e2cb1decSSalil Mehta 315e2cb1decSSalil Mehta hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 316e2cb1decSSalil Mehta sizeof(struct hclgevf_tqp), GFP_KERNEL); 317e2cb1decSSalil Mehta if (!hdev->htqp) 318e2cb1decSSalil Mehta return -ENOMEM; 319e2cb1decSSalil Mehta 320e2cb1decSSalil Mehta tqp = hdev->htqp; 321e2cb1decSSalil Mehta 322e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 323e2cb1decSSalil Mehta tqp->dev = &hdev->pdev->dev; 324e2cb1decSSalil Mehta tqp->index = i; 325e2cb1decSSalil Mehta 326e2cb1decSSalil Mehta tqp->q.ae_algo = &ae_algovf; 327e2cb1decSSalil Mehta tqp->q.buf_size = hdev->rx_buf_len; 328c0425944SPeng Li tqp->q.tx_desc_num = hdev->num_tx_desc; 329c0425944SPeng Li tqp->q.rx_desc_num = hdev->num_rx_desc; 330e2cb1decSSalil Mehta tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 331e2cb1decSSalil Mehta i * HCLGEVF_TQP_REG_SIZE; 332e2cb1decSSalil Mehta 333e2cb1decSSalil Mehta tqp++; 334e2cb1decSSalil Mehta } 335e2cb1decSSalil Mehta 336e2cb1decSSalil Mehta return 0; 337e2cb1decSSalil Mehta } 338e2cb1decSSalil Mehta 339e2cb1decSSalil Mehta static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 340e2cb1decSSalil Mehta { 341e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 342e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo; 343e2cb1decSSalil Mehta u16 new_tqps = hdev->num_tqps; 344e2cb1decSSalil Mehta int i; 345e2cb1decSSalil Mehta 346e2cb1decSSalil Mehta kinfo = &nic->kinfo; 347e2cb1decSSalil Mehta kinfo->num_tc = 0; 348c0425944SPeng Li kinfo->num_tx_desc = hdev->num_tx_desc; 349c0425944SPeng Li kinfo->num_rx_desc = hdev->num_rx_desc; 350e2cb1decSSalil Mehta kinfo->rx_buf_len = hdev->rx_buf_len; 351e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 352e2cb1decSSalil Mehta if (hdev->hw_tc_map & BIT(i)) 353e2cb1decSSalil Mehta kinfo->num_tc++; 354e2cb1decSSalil Mehta 355e2cb1decSSalil Mehta kinfo->rss_size 356e2cb1decSSalil Mehta = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 357e2cb1decSSalil Mehta new_tqps = kinfo->rss_size * kinfo->num_tc; 358e2cb1decSSalil Mehta kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 359e2cb1decSSalil Mehta 360e2cb1decSSalil Mehta kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 361e2cb1decSSalil Mehta sizeof(struct hnae3_queue *), GFP_KERNEL); 362e2cb1decSSalil Mehta if (!kinfo->tqp) 363e2cb1decSSalil Mehta return -ENOMEM; 364e2cb1decSSalil Mehta 365e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 366e2cb1decSSalil Mehta hdev->htqp[i].q.handle = &hdev->nic; 367e2cb1decSSalil Mehta hdev->htqp[i].q.tqp_index = i; 368e2cb1decSSalil Mehta kinfo->tqp[i] = &hdev->htqp[i].q; 369e2cb1decSSalil Mehta } 370e2cb1decSSalil Mehta 371e2cb1decSSalil Mehta return 0; 372e2cb1decSSalil Mehta } 373e2cb1decSSalil Mehta 374e2cb1decSSalil Mehta static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 375e2cb1decSSalil Mehta { 376e2cb1decSSalil Mehta int status; 377e2cb1decSSalil Mehta u8 resp_msg; 378e2cb1decSSalil Mehta 379e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 380e2cb1decSSalil Mehta 0, false, &resp_msg, sizeof(u8)); 381e2cb1decSSalil Mehta if (status) 382e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 383e2cb1decSSalil Mehta "VF failed to fetch link status(%d) from PF", status); 384e2cb1decSSalil Mehta } 385e2cb1decSSalil Mehta 386e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 387e2cb1decSSalil Mehta { 38845e92b7eSPeng Li struct hnae3_handle *rhandle = &hdev->roce; 389e2cb1decSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 39045e92b7eSPeng Li struct hnae3_client *rclient; 391e2cb1decSSalil Mehta struct hnae3_client *client; 392e2cb1decSSalil Mehta 393e2cb1decSSalil Mehta client = handle->client; 39445e92b7eSPeng Li rclient = hdev->roce_client; 395e2cb1decSSalil Mehta 396582d37bbSPeng Li link_state = 397582d37bbSPeng Li test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 398582d37bbSPeng Li 399e2cb1decSSalil Mehta if (link_state != hdev->hw.mac.link) { 400e2cb1decSSalil Mehta client->ops->link_status_change(handle, !!link_state); 40145e92b7eSPeng Li if (rclient && rclient->ops->link_status_change) 40245e92b7eSPeng Li rclient->ops->link_status_change(rhandle, !!link_state); 403e2cb1decSSalil Mehta hdev->hw.mac.link = link_state; 404e2cb1decSSalil Mehta } 405e2cb1decSSalil Mehta } 406e2cb1decSSalil Mehta 4079194d18bSliuzhongzhu void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 4089194d18bSliuzhongzhu { 4099194d18bSliuzhongzhu #define HCLGEVF_ADVERTISING 0 4109194d18bSliuzhongzhu #define HCLGEVF_SUPPORTED 1 4119194d18bSliuzhongzhu u8 send_msg; 4129194d18bSliuzhongzhu u8 resp_msg; 4139194d18bSliuzhongzhu 4149194d18bSliuzhongzhu send_msg = HCLGEVF_ADVERTISING; 4159194d18bSliuzhongzhu hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, &send_msg, 4169194d18bSliuzhongzhu sizeof(u8), false, &resp_msg, sizeof(u8)); 4179194d18bSliuzhongzhu send_msg = HCLGEVF_SUPPORTED; 4189194d18bSliuzhongzhu hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, &send_msg, 4199194d18bSliuzhongzhu sizeof(u8), false, &resp_msg, sizeof(u8)); 4209194d18bSliuzhongzhu } 4219194d18bSliuzhongzhu 422e2cb1decSSalil Mehta static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 423e2cb1decSSalil Mehta { 424e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 425e2cb1decSSalil Mehta int ret; 426e2cb1decSSalil Mehta 427e2cb1decSSalil Mehta nic->ae_algo = &ae_algovf; 428e2cb1decSSalil Mehta nic->pdev = hdev->pdev; 429e2cb1decSSalil Mehta nic->numa_node_mask = hdev->numa_node_mask; 430424eb834SSalil Mehta nic->flags |= HNAE3_SUPPORT_VF; 431e2cb1decSSalil Mehta 432e2cb1decSSalil Mehta if (hdev->ae_dev->dev_type != HNAE3_DEV_KNIC) { 433e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "unsupported device type %d\n", 434e2cb1decSSalil Mehta hdev->ae_dev->dev_type); 435e2cb1decSSalil Mehta return -EINVAL; 436e2cb1decSSalil Mehta } 437e2cb1decSSalil Mehta 438e2cb1decSSalil Mehta ret = hclgevf_knic_setup(hdev); 439e2cb1decSSalil Mehta if (ret) 440e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 441e2cb1decSSalil Mehta ret); 442e2cb1decSSalil Mehta return ret; 443e2cb1decSSalil Mehta } 444e2cb1decSSalil Mehta 445e2cb1decSSalil Mehta static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 446e2cb1decSSalil Mehta { 44736cbbdf6SPeng Li if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 44836cbbdf6SPeng Li dev_warn(&hdev->pdev->dev, 44936cbbdf6SPeng Li "vector(vector_id %d) has been freed.\n", vector_id); 45036cbbdf6SPeng Li return; 45136cbbdf6SPeng Li } 45236cbbdf6SPeng Li 453e2cb1decSSalil Mehta hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 454e2cb1decSSalil Mehta hdev->num_msi_left += 1; 455e2cb1decSSalil Mehta hdev->num_msi_used -= 1; 456e2cb1decSSalil Mehta } 457e2cb1decSSalil Mehta 458e2cb1decSSalil Mehta static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 459e2cb1decSSalil Mehta struct hnae3_vector_info *vector_info) 460e2cb1decSSalil Mehta { 461e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 462e2cb1decSSalil Mehta struct hnae3_vector_info *vector = vector_info; 463e2cb1decSSalil Mehta int alloc = 0; 464e2cb1decSSalil Mehta int i, j; 465e2cb1decSSalil Mehta 466e2cb1decSSalil Mehta vector_num = min(hdev->num_msi_left, vector_num); 467e2cb1decSSalil Mehta 468e2cb1decSSalil Mehta for (j = 0; j < vector_num; j++) { 469e2cb1decSSalil Mehta for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 470e2cb1decSSalil Mehta if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 471e2cb1decSSalil Mehta vector->vector = pci_irq_vector(hdev->pdev, i); 472e2cb1decSSalil Mehta vector->io_addr = hdev->hw.io_base + 473e2cb1decSSalil Mehta HCLGEVF_VECTOR_REG_BASE + 474e2cb1decSSalil Mehta (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 475e2cb1decSSalil Mehta hdev->vector_status[i] = 0; 476e2cb1decSSalil Mehta hdev->vector_irq[i] = vector->vector; 477e2cb1decSSalil Mehta 478e2cb1decSSalil Mehta vector++; 479e2cb1decSSalil Mehta alloc++; 480e2cb1decSSalil Mehta 481e2cb1decSSalil Mehta break; 482e2cb1decSSalil Mehta } 483e2cb1decSSalil Mehta } 484e2cb1decSSalil Mehta } 485e2cb1decSSalil Mehta hdev->num_msi_left -= alloc; 486e2cb1decSSalil Mehta hdev->num_msi_used += alloc; 487e2cb1decSSalil Mehta 488e2cb1decSSalil Mehta return alloc; 489e2cb1decSSalil Mehta } 490e2cb1decSSalil Mehta 491e2cb1decSSalil Mehta static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 492e2cb1decSSalil Mehta { 493e2cb1decSSalil Mehta int i; 494e2cb1decSSalil Mehta 495e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 496e2cb1decSSalil Mehta if (vector == hdev->vector_irq[i]) 497e2cb1decSSalil Mehta return i; 498e2cb1decSSalil Mehta 499e2cb1decSSalil Mehta return -EINVAL; 500e2cb1decSSalil Mehta } 501e2cb1decSSalil Mehta 502374ad291SJian Shen static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 503374ad291SJian Shen const u8 hfunc, const u8 *key) 504374ad291SJian Shen { 505374ad291SJian Shen struct hclgevf_rss_config_cmd *req; 506374ad291SJian Shen struct hclgevf_desc desc; 507374ad291SJian Shen int key_offset; 508374ad291SJian Shen int key_size; 509374ad291SJian Shen int ret; 510374ad291SJian Shen 511374ad291SJian Shen req = (struct hclgevf_rss_config_cmd *)desc.data; 512374ad291SJian Shen 513374ad291SJian Shen for (key_offset = 0; key_offset < 3; key_offset++) { 514374ad291SJian Shen hclgevf_cmd_setup_basic_desc(&desc, 515374ad291SJian Shen HCLGEVF_OPC_RSS_GENERIC_CONFIG, 516374ad291SJian Shen false); 517374ad291SJian Shen 518374ad291SJian Shen req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 519374ad291SJian Shen req->hash_config |= 520374ad291SJian Shen (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 521374ad291SJian Shen 522374ad291SJian Shen if (key_offset == 2) 523374ad291SJian Shen key_size = 524374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE - HCLGEVF_RSS_HASH_KEY_NUM * 2; 525374ad291SJian Shen else 526374ad291SJian Shen key_size = HCLGEVF_RSS_HASH_KEY_NUM; 527374ad291SJian Shen 528374ad291SJian Shen memcpy(req->hash_key, 529374ad291SJian Shen key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 530374ad291SJian Shen 531374ad291SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 532374ad291SJian Shen if (ret) { 533374ad291SJian Shen dev_err(&hdev->pdev->dev, 534374ad291SJian Shen "Configure RSS config fail, status = %d\n", 535374ad291SJian Shen ret); 536374ad291SJian Shen return ret; 537374ad291SJian Shen } 538374ad291SJian Shen } 539374ad291SJian Shen 540374ad291SJian Shen return 0; 541374ad291SJian Shen } 542374ad291SJian Shen 543e2cb1decSSalil Mehta static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 544e2cb1decSSalil Mehta { 545e2cb1decSSalil Mehta return HCLGEVF_RSS_KEY_SIZE; 546e2cb1decSSalil Mehta } 547e2cb1decSSalil Mehta 548e2cb1decSSalil Mehta static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 549e2cb1decSSalil Mehta { 550e2cb1decSSalil Mehta return HCLGEVF_RSS_IND_TBL_SIZE; 551e2cb1decSSalil Mehta } 552e2cb1decSSalil Mehta 553e2cb1decSSalil Mehta static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 554e2cb1decSSalil Mehta { 555e2cb1decSSalil Mehta const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 556e2cb1decSSalil Mehta struct hclgevf_rss_indirection_table_cmd *req; 557e2cb1decSSalil Mehta struct hclgevf_desc desc; 558e2cb1decSSalil Mehta int status; 559e2cb1decSSalil Mehta int i, j; 560e2cb1decSSalil Mehta 561e2cb1decSSalil Mehta req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 562e2cb1decSSalil Mehta 563e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 564e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 565e2cb1decSSalil Mehta false); 566e2cb1decSSalil Mehta req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 567e2cb1decSSalil Mehta req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 568e2cb1decSSalil Mehta for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 569e2cb1decSSalil Mehta req->rss_result[j] = 570e2cb1decSSalil Mehta indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 571e2cb1decSSalil Mehta 572e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 573e2cb1decSSalil Mehta if (status) { 574e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 575e2cb1decSSalil Mehta "VF failed(=%d) to set RSS indirection table\n", 576e2cb1decSSalil Mehta status); 577e2cb1decSSalil Mehta return status; 578e2cb1decSSalil Mehta } 579e2cb1decSSalil Mehta } 580e2cb1decSSalil Mehta 581e2cb1decSSalil Mehta return 0; 582e2cb1decSSalil Mehta } 583e2cb1decSSalil Mehta 584e2cb1decSSalil Mehta static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 585e2cb1decSSalil Mehta { 586e2cb1decSSalil Mehta struct hclgevf_rss_tc_mode_cmd *req; 587e2cb1decSSalil Mehta u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 588e2cb1decSSalil Mehta u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 589e2cb1decSSalil Mehta u16 tc_size[HCLGEVF_MAX_TC_NUM]; 590e2cb1decSSalil Mehta struct hclgevf_desc desc; 591e2cb1decSSalil Mehta u16 roundup_size; 592e2cb1decSSalil Mehta int status; 593e2cb1decSSalil Mehta int i; 594e2cb1decSSalil Mehta 595e2cb1decSSalil Mehta req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 596e2cb1decSSalil Mehta 597e2cb1decSSalil Mehta roundup_size = roundup_pow_of_two(rss_size); 598e2cb1decSSalil Mehta roundup_size = ilog2(roundup_size); 599e2cb1decSSalil Mehta 600e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 601e2cb1decSSalil Mehta tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 602e2cb1decSSalil Mehta tc_size[i] = roundup_size; 603e2cb1decSSalil Mehta tc_offset[i] = rss_size * i; 604e2cb1decSSalil Mehta } 605e2cb1decSSalil Mehta 606e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 607e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 608e4e87715SPeng Li hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 609e2cb1decSSalil Mehta (tc_valid[i] & 0x1)); 610e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 611e2cb1decSSalil Mehta HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 612e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 613e2cb1decSSalil Mehta HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 614e2cb1decSSalil Mehta } 615e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 616e2cb1decSSalil Mehta if (status) 617e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 618e2cb1decSSalil Mehta "VF failed(=%d) to set rss tc mode\n", status); 619e2cb1decSSalil Mehta 620e2cb1decSSalil Mehta return status; 621e2cb1decSSalil Mehta } 622e2cb1decSSalil Mehta 623a638b1d8SJian Shen /* for revision 0x20, vf shared the same rss config with pf */ 624a638b1d8SJian Shen static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 625a638b1d8SJian Shen { 626a638b1d8SJian Shen #define HCLGEVF_RSS_MBX_RESP_LEN 8 627a638b1d8SJian Shen 628a638b1d8SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 629a638b1d8SJian Shen u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 630a638b1d8SJian Shen u16 msg_num, hash_key_index; 631a638b1d8SJian Shen u8 index; 632a638b1d8SJian Shen int ret; 633a638b1d8SJian Shen 634a638b1d8SJian Shen msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 635a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN; 636a638b1d8SJian Shen for (index = 0; index < msg_num; index++) { 637a638b1d8SJian Shen ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_RSS_KEY, 0, 638a638b1d8SJian Shen &index, sizeof(index), 639a638b1d8SJian Shen true, resp_msg, 640a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN); 641a638b1d8SJian Shen if (ret) { 642a638b1d8SJian Shen dev_err(&hdev->pdev->dev, 643a638b1d8SJian Shen "VF get rss hash key from PF failed, ret=%d", 644a638b1d8SJian Shen ret); 645a638b1d8SJian Shen return ret; 646a638b1d8SJian Shen } 647a638b1d8SJian Shen 648a638b1d8SJian Shen hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 649a638b1d8SJian Shen if (index == msg_num - 1) 650a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 651a638b1d8SJian Shen &resp_msg[0], 652a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE - hash_key_index); 653a638b1d8SJian Shen else 654a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 655a638b1d8SJian Shen &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 656a638b1d8SJian Shen } 657a638b1d8SJian Shen 658a638b1d8SJian Shen return 0; 659a638b1d8SJian Shen } 660a638b1d8SJian Shen 661e2cb1decSSalil Mehta static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 662e2cb1decSSalil Mehta u8 *hfunc) 663e2cb1decSSalil Mehta { 664e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 665e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 666a638b1d8SJian Shen int i, ret; 667e2cb1decSSalil Mehta 668374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 669374ad291SJian Shen /* Get hash algorithm */ 670374ad291SJian Shen if (hfunc) { 671374ad291SJian Shen switch (rss_cfg->hash_algo) { 672374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 673374ad291SJian Shen *hfunc = ETH_RSS_HASH_TOP; 674374ad291SJian Shen break; 675374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 676374ad291SJian Shen *hfunc = ETH_RSS_HASH_XOR; 677374ad291SJian Shen break; 678374ad291SJian Shen default: 679374ad291SJian Shen *hfunc = ETH_RSS_HASH_UNKNOWN; 680374ad291SJian Shen break; 681374ad291SJian Shen } 682374ad291SJian Shen } 683374ad291SJian Shen 684374ad291SJian Shen /* Get the RSS Key required by the user */ 685374ad291SJian Shen if (key) 686374ad291SJian Shen memcpy(key, rss_cfg->rss_hash_key, 687374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 688a638b1d8SJian Shen } else { 689a638b1d8SJian Shen if (hfunc) 690a638b1d8SJian Shen *hfunc = ETH_RSS_HASH_TOP; 691a638b1d8SJian Shen if (key) { 692a638b1d8SJian Shen ret = hclgevf_get_rss_hash_key(hdev); 693a638b1d8SJian Shen if (ret) 694a638b1d8SJian Shen return ret; 695a638b1d8SJian Shen memcpy(key, rss_cfg->rss_hash_key, 696a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE); 697a638b1d8SJian Shen } 698374ad291SJian Shen } 699374ad291SJian Shen 700e2cb1decSSalil Mehta if (indir) 701e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 702e2cb1decSSalil Mehta indir[i] = rss_cfg->rss_indirection_tbl[i]; 703e2cb1decSSalil Mehta 704374ad291SJian Shen return 0; 705e2cb1decSSalil Mehta } 706e2cb1decSSalil Mehta 707e2cb1decSSalil Mehta static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 708e2cb1decSSalil Mehta const u8 *key, const u8 hfunc) 709e2cb1decSSalil Mehta { 710e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 711e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 712374ad291SJian Shen int ret, i; 713374ad291SJian Shen 714374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 715374ad291SJian Shen /* Set the RSS Hash Key if specififed by the user */ 716374ad291SJian Shen if (key) { 717374ad291SJian Shen switch (hfunc) { 718374ad291SJian Shen case ETH_RSS_HASH_TOP: 719374ad291SJian Shen rss_cfg->hash_algo = 720374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 721374ad291SJian Shen break; 722374ad291SJian Shen case ETH_RSS_HASH_XOR: 723374ad291SJian Shen rss_cfg->hash_algo = 724374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_SIMPLE; 725374ad291SJian Shen break; 726374ad291SJian Shen case ETH_RSS_HASH_NO_CHANGE: 727374ad291SJian Shen break; 728374ad291SJian Shen default: 729374ad291SJian Shen return -EINVAL; 730374ad291SJian Shen } 731374ad291SJian Shen 732374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 733374ad291SJian Shen key); 734374ad291SJian Shen if (ret) 735374ad291SJian Shen return ret; 736374ad291SJian Shen 737374ad291SJian Shen /* Update the shadow RSS key with user specified qids */ 738374ad291SJian Shen memcpy(rss_cfg->rss_hash_key, key, 739374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 740374ad291SJian Shen } 741374ad291SJian Shen } 742e2cb1decSSalil Mehta 743e2cb1decSSalil Mehta /* update the shadow RSS table with user specified qids */ 744e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 745e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = indir[i]; 746e2cb1decSSalil Mehta 747e2cb1decSSalil Mehta /* update the hardware */ 748e2cb1decSSalil Mehta return hclgevf_set_rss_indir_table(hdev); 749e2cb1decSSalil Mehta } 750e2cb1decSSalil Mehta 751d97b3072SJian Shen static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 752d97b3072SJian Shen { 753d97b3072SJian Shen u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 754d97b3072SJian Shen 755d97b3072SJian Shen if (nfc->data & RXH_L4_B_2_3) 756d97b3072SJian Shen hash_sets |= HCLGEVF_D_PORT_BIT; 757d97b3072SJian Shen else 758d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_PORT_BIT; 759d97b3072SJian Shen 760d97b3072SJian Shen if (nfc->data & RXH_IP_SRC) 761d97b3072SJian Shen hash_sets |= HCLGEVF_S_IP_BIT; 762d97b3072SJian Shen else 763d97b3072SJian Shen hash_sets &= ~HCLGEVF_S_IP_BIT; 764d97b3072SJian Shen 765d97b3072SJian Shen if (nfc->data & RXH_IP_DST) 766d97b3072SJian Shen hash_sets |= HCLGEVF_D_IP_BIT; 767d97b3072SJian Shen else 768d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_IP_BIT; 769d97b3072SJian Shen 770d97b3072SJian Shen if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 771d97b3072SJian Shen hash_sets |= HCLGEVF_V_TAG_BIT; 772d97b3072SJian Shen 773d97b3072SJian Shen return hash_sets; 774d97b3072SJian Shen } 775d97b3072SJian Shen 776d97b3072SJian Shen static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 777d97b3072SJian Shen struct ethtool_rxnfc *nfc) 778d97b3072SJian Shen { 779d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 780d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 781d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 782d97b3072SJian Shen struct hclgevf_desc desc; 783d97b3072SJian Shen u8 tuple_sets; 784d97b3072SJian Shen int ret; 785d97b3072SJian Shen 786d97b3072SJian Shen if (handle->pdev->revision == 0x20) 787d97b3072SJian Shen return -EOPNOTSUPP; 788d97b3072SJian Shen 789d97b3072SJian Shen if (nfc->data & 790d97b3072SJian Shen ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 791d97b3072SJian Shen return -EINVAL; 792d97b3072SJian Shen 793d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 794d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 795d97b3072SJian Shen 796d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 797d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 798d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 799d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 800d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 801d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 802d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 803d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 804d97b3072SJian Shen 805d97b3072SJian Shen tuple_sets = hclgevf_get_rss_hash_bits(nfc); 806d97b3072SJian Shen switch (nfc->flow_type) { 807d97b3072SJian Shen case TCP_V4_FLOW: 808d97b3072SJian Shen req->ipv4_tcp_en = tuple_sets; 809d97b3072SJian Shen break; 810d97b3072SJian Shen case TCP_V6_FLOW: 811d97b3072SJian Shen req->ipv6_tcp_en = tuple_sets; 812d97b3072SJian Shen break; 813d97b3072SJian Shen case UDP_V4_FLOW: 814d97b3072SJian Shen req->ipv4_udp_en = tuple_sets; 815d97b3072SJian Shen break; 816d97b3072SJian Shen case UDP_V6_FLOW: 817d97b3072SJian Shen req->ipv6_udp_en = tuple_sets; 818d97b3072SJian Shen break; 819d97b3072SJian Shen case SCTP_V4_FLOW: 820d97b3072SJian Shen req->ipv4_sctp_en = tuple_sets; 821d97b3072SJian Shen break; 822d97b3072SJian Shen case SCTP_V6_FLOW: 823d97b3072SJian Shen if ((nfc->data & RXH_L4_B_0_1) || 824d97b3072SJian Shen (nfc->data & RXH_L4_B_2_3)) 825d97b3072SJian Shen return -EINVAL; 826d97b3072SJian Shen 827d97b3072SJian Shen req->ipv6_sctp_en = tuple_sets; 828d97b3072SJian Shen break; 829d97b3072SJian Shen case IPV4_FLOW: 830d97b3072SJian Shen req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 831d97b3072SJian Shen break; 832d97b3072SJian Shen case IPV6_FLOW: 833d97b3072SJian Shen req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 834d97b3072SJian Shen break; 835d97b3072SJian Shen default: 836d97b3072SJian Shen return -EINVAL; 837d97b3072SJian Shen } 838d97b3072SJian Shen 839d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 840d97b3072SJian Shen if (ret) { 841d97b3072SJian Shen dev_err(&hdev->pdev->dev, 842d97b3072SJian Shen "Set rss tuple fail, status = %d\n", ret); 843d97b3072SJian Shen return ret; 844d97b3072SJian Shen } 845d97b3072SJian Shen 846d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 847d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 848d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 849d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 850d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 851d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 852d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 853d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 854d97b3072SJian Shen return 0; 855d97b3072SJian Shen } 856d97b3072SJian Shen 857d97b3072SJian Shen static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 858d97b3072SJian Shen struct ethtool_rxnfc *nfc) 859d97b3072SJian Shen { 860d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 861d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 862d97b3072SJian Shen u8 tuple_sets; 863d97b3072SJian Shen 864d97b3072SJian Shen if (handle->pdev->revision == 0x20) 865d97b3072SJian Shen return -EOPNOTSUPP; 866d97b3072SJian Shen 867d97b3072SJian Shen nfc->data = 0; 868d97b3072SJian Shen 869d97b3072SJian Shen switch (nfc->flow_type) { 870d97b3072SJian Shen case TCP_V4_FLOW: 871d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 872d97b3072SJian Shen break; 873d97b3072SJian Shen case UDP_V4_FLOW: 874d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 875d97b3072SJian Shen break; 876d97b3072SJian Shen case TCP_V6_FLOW: 877d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 878d97b3072SJian Shen break; 879d97b3072SJian Shen case UDP_V6_FLOW: 880d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 881d97b3072SJian Shen break; 882d97b3072SJian Shen case SCTP_V4_FLOW: 883d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 884d97b3072SJian Shen break; 885d97b3072SJian Shen case SCTP_V6_FLOW: 886d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 887d97b3072SJian Shen break; 888d97b3072SJian Shen case IPV4_FLOW: 889d97b3072SJian Shen case IPV6_FLOW: 890d97b3072SJian Shen tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 891d97b3072SJian Shen break; 892d97b3072SJian Shen default: 893d97b3072SJian Shen return -EINVAL; 894d97b3072SJian Shen } 895d97b3072SJian Shen 896d97b3072SJian Shen if (!tuple_sets) 897d97b3072SJian Shen return 0; 898d97b3072SJian Shen 899d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_PORT_BIT) 900d97b3072SJian Shen nfc->data |= RXH_L4_B_2_3; 901d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_PORT_BIT) 902d97b3072SJian Shen nfc->data |= RXH_L4_B_0_1; 903d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_IP_BIT) 904d97b3072SJian Shen nfc->data |= RXH_IP_DST; 905d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_IP_BIT) 906d97b3072SJian Shen nfc->data |= RXH_IP_SRC; 907d97b3072SJian Shen 908d97b3072SJian Shen return 0; 909d97b3072SJian Shen } 910d97b3072SJian Shen 911d97b3072SJian Shen static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 912d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg) 913d97b3072SJian Shen { 914d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 915d97b3072SJian Shen struct hclgevf_desc desc; 916d97b3072SJian Shen int ret; 917d97b3072SJian Shen 918d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 919d97b3072SJian Shen 920d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 921d97b3072SJian Shen 922d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 923d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 924d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 925d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 926d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 927d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 928d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 929d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 930d97b3072SJian Shen 931d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 932d97b3072SJian Shen if (ret) 933d97b3072SJian Shen dev_err(&hdev->pdev->dev, 934d97b3072SJian Shen "Configure rss input fail, status = %d\n", ret); 935d97b3072SJian Shen return ret; 936d97b3072SJian Shen } 937d97b3072SJian Shen 938e2cb1decSSalil Mehta static int hclgevf_get_tc_size(struct hnae3_handle *handle) 939e2cb1decSSalil Mehta { 940e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 941e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 942e2cb1decSSalil Mehta 943e2cb1decSSalil Mehta return rss_cfg->rss_size; 944e2cb1decSSalil Mehta } 945e2cb1decSSalil Mehta 946e2cb1decSSalil Mehta static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 947b204bc74SPeng Li int vector_id, 948e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 949e2cb1decSSalil Mehta { 950e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 951e2cb1decSSalil Mehta struct hnae3_ring_chain_node *node; 952e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 953e2cb1decSSalil Mehta struct hclgevf_desc desc; 954b204bc74SPeng Li int i = 0; 955e2cb1decSSalil Mehta int status; 956e2cb1decSSalil Mehta u8 type; 957e2cb1decSSalil Mehta 958e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 959e2cb1decSSalil Mehta 960e2cb1decSSalil Mehta for (node = ring_chain; node; node = node->next) { 9615d02a58dSYunsheng Lin int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 9625d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 9635d02a58dSYunsheng Lin 9645d02a58dSYunsheng Lin if (i == 0) { 9655d02a58dSYunsheng Lin hclgevf_cmd_setup_basic_desc(&desc, 9665d02a58dSYunsheng Lin HCLGEVF_OPC_MBX_VF_TO_PF, 9675d02a58dSYunsheng Lin false); 9685d02a58dSYunsheng Lin type = en ? 9695d02a58dSYunsheng Lin HCLGE_MBX_MAP_RING_TO_VECTOR : 9705d02a58dSYunsheng Lin HCLGE_MBX_UNMAP_RING_TO_VECTOR; 9715d02a58dSYunsheng Lin req->msg[0] = type; 9725d02a58dSYunsheng Lin req->msg[1] = vector_id; 9735d02a58dSYunsheng Lin } 9745d02a58dSYunsheng Lin 9755d02a58dSYunsheng Lin req->msg[idx_offset] = 976e4e87715SPeng Li hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 9775d02a58dSYunsheng Lin req->msg[idx_offset + 1] = node->tqp_index; 978e4e87715SPeng Li req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 97979eee410SFuyun Liang HNAE3_RING_GL_IDX_M, 98079eee410SFuyun Liang HNAE3_RING_GL_IDX_S); 98179eee410SFuyun Liang 9825d02a58dSYunsheng Lin i++; 9835d02a58dSYunsheng Lin if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 9845d02a58dSYunsheng Lin HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 9855d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 9865d02a58dSYunsheng Lin !node->next) { 987e2cb1decSSalil Mehta req->msg[2] = i; 988e2cb1decSSalil Mehta 989e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 990e2cb1decSSalil Mehta if (status) { 991e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 992e2cb1decSSalil Mehta "Map TQP fail, status is %d.\n", 993e2cb1decSSalil Mehta status); 994e2cb1decSSalil Mehta return status; 995e2cb1decSSalil Mehta } 996e2cb1decSSalil Mehta i = 0; 997e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 998e2cb1decSSalil Mehta HCLGEVF_OPC_MBX_VF_TO_PF, 999e2cb1decSSalil Mehta false); 1000e2cb1decSSalil Mehta req->msg[0] = type; 1001e2cb1decSSalil Mehta req->msg[1] = vector_id; 1002e2cb1decSSalil Mehta } 1003e2cb1decSSalil Mehta } 1004e2cb1decSSalil Mehta 1005e2cb1decSSalil Mehta return 0; 1006e2cb1decSSalil Mehta } 1007e2cb1decSSalil Mehta 1008e2cb1decSSalil Mehta static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1009e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1010e2cb1decSSalil Mehta { 1011b204bc74SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1012b204bc74SPeng Li int vector_id; 1013b204bc74SPeng Li 1014b204bc74SPeng Li vector_id = hclgevf_get_vector_index(hdev, vector); 1015b204bc74SPeng Li if (vector_id < 0) { 1016b204bc74SPeng Li dev_err(&handle->pdev->dev, 1017b204bc74SPeng Li "Get vector index fail. ret =%d\n", vector_id); 1018b204bc74SPeng Li return vector_id; 1019b204bc74SPeng Li } 1020b204bc74SPeng Li 1021b204bc74SPeng Li return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1022e2cb1decSSalil Mehta } 1023e2cb1decSSalil Mehta 1024e2cb1decSSalil Mehta static int hclgevf_unmap_ring_from_vector( 1025e2cb1decSSalil Mehta struct hnae3_handle *handle, 1026e2cb1decSSalil Mehta int vector, 1027e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1028e2cb1decSSalil Mehta { 1029e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1030e2cb1decSSalil Mehta int ret, vector_id; 1031e2cb1decSSalil Mehta 1032dea846e8SHuazhong Tan if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1033dea846e8SHuazhong Tan return 0; 1034dea846e8SHuazhong Tan 1035e2cb1decSSalil Mehta vector_id = hclgevf_get_vector_index(hdev, vector); 1036e2cb1decSSalil Mehta if (vector_id < 0) { 1037e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1038e2cb1decSSalil Mehta "Get vector index fail. ret =%d\n", vector_id); 1039e2cb1decSSalil Mehta return vector_id; 1040e2cb1decSSalil Mehta } 1041e2cb1decSSalil Mehta 1042b204bc74SPeng Li ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 10430d3e6631SYunsheng Lin if (ret) 1044e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1045e2cb1decSSalil Mehta "Unmap ring from vector fail. vector=%d, ret =%d\n", 1046e2cb1decSSalil Mehta vector_id, 1047e2cb1decSSalil Mehta ret); 10480d3e6631SYunsheng Lin 1049e2cb1decSSalil Mehta return ret; 1050e2cb1decSSalil Mehta } 1051e2cb1decSSalil Mehta 10520d3e6631SYunsheng Lin static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 10530d3e6631SYunsheng Lin { 10540d3e6631SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 105503718db9SYunsheng Lin int vector_id; 10560d3e6631SYunsheng Lin 105703718db9SYunsheng Lin vector_id = hclgevf_get_vector_index(hdev, vector); 105803718db9SYunsheng Lin if (vector_id < 0) { 105903718db9SYunsheng Lin dev_err(&handle->pdev->dev, 106003718db9SYunsheng Lin "hclgevf_put_vector get vector index fail. ret =%d\n", 106103718db9SYunsheng Lin vector_id); 106203718db9SYunsheng Lin return vector_id; 106303718db9SYunsheng Lin } 106403718db9SYunsheng Lin 106503718db9SYunsheng Lin hclgevf_free_vector(hdev, vector_id); 1066e2cb1decSSalil Mehta 1067e2cb1decSSalil Mehta return 0; 1068e2cb1decSSalil Mehta } 1069e2cb1decSSalil Mehta 10703b75c3dfSPeng Li static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1071f01f5559SJian Shen bool en_bc_pmc) 1072e2cb1decSSalil Mehta { 1073e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 1074e2cb1decSSalil Mehta struct hclgevf_desc desc; 1075f01f5559SJian Shen int ret; 1076e2cb1decSSalil Mehta 1077e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1078e2cb1decSSalil Mehta 1079e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 1080e2cb1decSSalil Mehta req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 1081f01f5559SJian Shen req->msg[1] = en_bc_pmc ? 1 : 0; 1082e2cb1decSSalil Mehta 1083f01f5559SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1084f01f5559SJian Shen if (ret) 1085e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1086f01f5559SJian Shen "Set promisc mode fail, status is %d.\n", ret); 1087e2cb1decSSalil Mehta 1088f01f5559SJian Shen return ret; 1089e2cb1decSSalil Mehta } 1090e2cb1decSSalil Mehta 1091f01f5559SJian Shen static int hclgevf_set_promisc_mode(struct hclgevf_dev *hdev, bool en_bc_pmc) 1092e2cb1decSSalil Mehta { 1093f01f5559SJian Shen return hclgevf_cmd_set_promisc_mode(hdev, en_bc_pmc); 1094e2cb1decSSalil Mehta } 1095e2cb1decSSalil Mehta 1096e2cb1decSSalil Mehta static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, int tqp_id, 1097e2cb1decSSalil Mehta int stream_id, bool enable) 1098e2cb1decSSalil Mehta { 1099e2cb1decSSalil Mehta struct hclgevf_cfg_com_tqp_queue_cmd *req; 1100e2cb1decSSalil Mehta struct hclgevf_desc desc; 1101e2cb1decSSalil Mehta int status; 1102e2cb1decSSalil Mehta 1103e2cb1decSSalil Mehta req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1104e2cb1decSSalil Mehta 1105e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1106e2cb1decSSalil Mehta false); 1107e2cb1decSSalil Mehta req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1108e2cb1decSSalil Mehta req->stream_id = cpu_to_le16(stream_id); 1109e2cb1decSSalil Mehta req->enable |= enable << HCLGEVF_TQP_ENABLE_B; 1110e2cb1decSSalil Mehta 1111e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1112e2cb1decSSalil Mehta if (status) 1113e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1114e2cb1decSSalil Mehta "TQP enable fail, status =%d.\n", status); 1115e2cb1decSSalil Mehta 1116e2cb1decSSalil Mehta return status; 1117e2cb1decSSalil Mehta } 1118e2cb1decSSalil Mehta 1119e2cb1decSSalil Mehta static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1120e2cb1decSSalil Mehta { 1121b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1122e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 1123e2cb1decSSalil Mehta int i; 1124e2cb1decSSalil Mehta 1125b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 1126b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1127e2cb1decSSalil Mehta memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1128e2cb1decSSalil Mehta } 1129e2cb1decSSalil Mehta } 1130e2cb1decSSalil Mehta 1131e2cb1decSSalil Mehta static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1132e2cb1decSSalil Mehta { 1133e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1134e2cb1decSSalil Mehta 1135e2cb1decSSalil Mehta ether_addr_copy(p, hdev->hw.mac.mac_addr); 1136e2cb1decSSalil Mehta } 1137e2cb1decSSalil Mehta 113859098055SFuyun Liang static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 113959098055SFuyun Liang bool is_first) 1140e2cb1decSSalil Mehta { 1141e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1142e2cb1decSSalil Mehta u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1143e2cb1decSSalil Mehta u8 *new_mac_addr = (u8 *)p; 1144e2cb1decSSalil Mehta u8 msg_data[ETH_ALEN * 2]; 114559098055SFuyun Liang u16 subcode; 1146e2cb1decSSalil Mehta int status; 1147e2cb1decSSalil Mehta 1148e2cb1decSSalil Mehta ether_addr_copy(msg_data, new_mac_addr); 1149e2cb1decSSalil Mehta ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 1150e2cb1decSSalil Mehta 115159098055SFuyun Liang subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 115259098055SFuyun Liang HCLGE_MBX_MAC_VLAN_UC_MODIFY; 115359098055SFuyun Liang 1154e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 115559098055SFuyun Liang subcode, msg_data, ETH_ALEN * 2, 11562097fdefSJian Shen true, NULL, 0); 1157e2cb1decSSalil Mehta if (!status) 1158e2cb1decSSalil Mehta ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1159e2cb1decSSalil Mehta 1160e2cb1decSSalil Mehta return status; 1161e2cb1decSSalil Mehta } 1162e2cb1decSSalil Mehta 1163e2cb1decSSalil Mehta static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1164e2cb1decSSalil Mehta const unsigned char *addr) 1165e2cb1decSSalil Mehta { 1166e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1167e2cb1decSSalil Mehta 1168e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1169e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_ADD, 1170e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1171e2cb1decSSalil Mehta } 1172e2cb1decSSalil Mehta 1173e2cb1decSSalil Mehta static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1174e2cb1decSSalil Mehta const unsigned char *addr) 1175e2cb1decSSalil Mehta { 1176e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1177e2cb1decSSalil Mehta 1178e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1179e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1180e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1181e2cb1decSSalil Mehta } 1182e2cb1decSSalil Mehta 1183e2cb1decSSalil Mehta static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1184e2cb1decSSalil Mehta const unsigned char *addr) 1185e2cb1decSSalil Mehta { 1186e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1187e2cb1decSSalil Mehta 1188e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1189e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_ADD, 1190e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1191e2cb1decSSalil Mehta } 1192e2cb1decSSalil Mehta 1193e2cb1decSSalil Mehta static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1194e2cb1decSSalil Mehta const unsigned char *addr) 1195e2cb1decSSalil Mehta { 1196e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1197e2cb1decSSalil Mehta 1198e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1199e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1200e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1201e2cb1decSSalil Mehta } 1202e2cb1decSSalil Mehta 1203e2cb1decSSalil Mehta static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1204e2cb1decSSalil Mehta __be16 proto, u16 vlan_id, 1205e2cb1decSSalil Mehta bool is_kill) 1206e2cb1decSSalil Mehta { 1207e2cb1decSSalil Mehta #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1208e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1209e2cb1decSSalil Mehta u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1210e2cb1decSSalil Mehta 1211e2cb1decSSalil Mehta if (vlan_id > 4095) 1212e2cb1decSSalil Mehta return -EINVAL; 1213e2cb1decSSalil Mehta 1214e2cb1decSSalil Mehta if (proto != htons(ETH_P_8021Q)) 1215e2cb1decSSalil Mehta return -EPROTONOSUPPORT; 1216e2cb1decSSalil Mehta 1217e2cb1decSSalil Mehta msg_data[0] = is_kill; 1218e2cb1decSSalil Mehta memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1219e2cb1decSSalil Mehta memcpy(&msg_data[3], &proto, sizeof(proto)); 1220e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1221e2cb1decSSalil Mehta HCLGE_MBX_VLAN_FILTER, msg_data, 1222e2cb1decSSalil Mehta HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 1223e2cb1decSSalil Mehta } 1224e2cb1decSSalil Mehta 1225b2641e2aSYunsheng Lin static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1226b2641e2aSYunsheng Lin { 1227b2641e2aSYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1228b2641e2aSYunsheng Lin u8 msg_data; 1229b2641e2aSYunsheng Lin 1230b2641e2aSYunsheng Lin msg_data = enable ? 1 : 0; 1231b2641e2aSYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1232b2641e2aSYunsheng Lin HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1233b2641e2aSYunsheng Lin 1, false, NULL, 0); 1234b2641e2aSYunsheng Lin } 1235b2641e2aSYunsheng Lin 12367fa6be4fSHuazhong Tan static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1237e2cb1decSSalil Mehta { 1238e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1239e2cb1decSSalil Mehta u8 msg_data[2]; 12401a426f8bSPeng Li int ret; 1241e2cb1decSSalil Mehta 1242e2cb1decSSalil Mehta memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 1243e2cb1decSSalil Mehta 12441a426f8bSPeng Li /* disable vf queue before send queue reset msg to PF */ 12451a426f8bSPeng Li ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 12461a426f8bSPeng Li if (ret) 12477fa6be4fSHuazhong Tan return ret; 12481a426f8bSPeng Li 12497fa6be4fSHuazhong Tan return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 12501a426f8bSPeng Li 2, true, NULL, 0); 1251e2cb1decSSalil Mehta } 1252e2cb1decSSalil Mehta 1253818f1675SYunsheng Lin static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1254818f1675SYunsheng Lin { 1255818f1675SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1256818f1675SYunsheng Lin 1257818f1675SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu, 1258818f1675SYunsheng Lin sizeof(new_mtu), true, NULL, 0); 1259818f1675SYunsheng Lin } 1260818f1675SYunsheng Lin 12616988eb2aSSalil Mehta static int hclgevf_notify_client(struct hclgevf_dev *hdev, 12626988eb2aSSalil Mehta enum hnae3_reset_notify_type type) 12636988eb2aSSalil Mehta { 12646988eb2aSSalil Mehta struct hnae3_client *client = hdev->nic_client; 12656988eb2aSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 12666a5f6fa3SHuazhong Tan int ret; 12676988eb2aSSalil Mehta 12686988eb2aSSalil Mehta if (!client->ops->reset_notify) 12696988eb2aSSalil Mehta return -EOPNOTSUPP; 12706988eb2aSSalil Mehta 12716a5f6fa3SHuazhong Tan ret = client->ops->reset_notify(handle, type); 12726a5f6fa3SHuazhong Tan if (ret) 12736a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 12746a5f6fa3SHuazhong Tan type, ret); 12756a5f6fa3SHuazhong Tan 12766a5f6fa3SHuazhong Tan return ret; 12776988eb2aSSalil Mehta } 12786988eb2aSSalil Mehta 12796ff3cf07SHuazhong Tan static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 12806ff3cf07SHuazhong Tan { 12816ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 12826ff3cf07SHuazhong Tan 12836ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DONE, &hdev->flr_state); 12846ff3cf07SHuazhong Tan } 12856ff3cf07SHuazhong Tan 12866ff3cf07SHuazhong Tan static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev, 12876ff3cf07SHuazhong Tan unsigned long delay_us, 12886ff3cf07SHuazhong Tan unsigned long wait_cnt) 12896ff3cf07SHuazhong Tan { 12906ff3cf07SHuazhong Tan unsigned long cnt = 0; 12916ff3cf07SHuazhong Tan 12926ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) && 12936ff3cf07SHuazhong Tan cnt++ < wait_cnt) 12946ff3cf07SHuazhong Tan usleep_range(delay_us, delay_us * 2); 12956ff3cf07SHuazhong Tan 12966ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) { 12976ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 12986ff3cf07SHuazhong Tan "flr wait timeout\n"); 12996ff3cf07SHuazhong Tan return -ETIMEDOUT; 13006ff3cf07SHuazhong Tan } 13016ff3cf07SHuazhong Tan 13026ff3cf07SHuazhong Tan return 0; 13036ff3cf07SHuazhong Tan } 13046ff3cf07SHuazhong Tan 13056988eb2aSSalil Mehta static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 13066988eb2aSSalil Mehta { 1307aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_US 20000 1308aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_CNT 2000 1309aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1310aa5c4f17SHuazhong Tan (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1311aa5c4f17SHuazhong Tan 1312aa5c4f17SHuazhong Tan u32 val; 1313aa5c4f17SHuazhong Tan int ret; 13146988eb2aSSalil Mehta 13156988eb2aSSalil Mehta /* wait to check the hardware reset completion status */ 1316aa5c4f17SHuazhong Tan val = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1317aa5c4f17SHuazhong Tan dev_info(&hdev->pdev->dev, "checking vf resetting status: %x\n", val); 1318aa5c4f17SHuazhong Tan 13196ff3cf07SHuazhong Tan if (hdev->reset_type == HNAE3_FLR_RESET) 13206ff3cf07SHuazhong Tan return hclgevf_flr_poll_timeout(hdev, 13216ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_US, 13226ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_CNT); 13236ff3cf07SHuazhong Tan 1324aa5c4f17SHuazhong Tan ret = readl_poll_timeout(hdev->hw.io_base + HCLGEVF_RST_ING, val, 1325aa5c4f17SHuazhong Tan !(val & HCLGEVF_RST_ING_BITS), 1326aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_US, 1327aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 13286988eb2aSSalil Mehta 13296988eb2aSSalil Mehta /* hardware completion status should be available by this time */ 1330aa5c4f17SHuazhong Tan if (ret) { 1331aa5c4f17SHuazhong Tan dev_err(&hdev->pdev->dev, 13326988eb2aSSalil Mehta "could'nt get reset done status from h/w, timeout!\n"); 1333aa5c4f17SHuazhong Tan return ret; 13346988eb2aSSalil Mehta } 13356988eb2aSSalil Mehta 13366988eb2aSSalil Mehta /* we will wait a bit more to let reset of the stack to complete. This 13376988eb2aSSalil Mehta * might happen in case reset assertion was made by PF. Yes, this also 13386988eb2aSSalil Mehta * means we might end up waiting bit more even for VF reset. 13396988eb2aSSalil Mehta */ 13406988eb2aSSalil Mehta msleep(5000); 13416988eb2aSSalil Mehta 13426988eb2aSSalil Mehta return 0; 13436988eb2aSSalil Mehta } 13446988eb2aSSalil Mehta 13456988eb2aSSalil Mehta static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 13466988eb2aSSalil Mehta { 13477a01c897SSalil Mehta int ret; 13487a01c897SSalil Mehta 13496988eb2aSSalil Mehta /* uninitialize the nic client */ 13506a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 13516a5f6fa3SHuazhong Tan if (ret) 13526a5f6fa3SHuazhong Tan return ret; 13536988eb2aSSalil Mehta 13547a01c897SSalil Mehta /* re-initialize the hclge device */ 13559c6f7085SHuazhong Tan ret = hclgevf_reset_hdev(hdev); 13567a01c897SSalil Mehta if (ret) { 13577a01c897SSalil Mehta dev_err(&hdev->pdev->dev, 13587a01c897SSalil Mehta "hclge device re-init failed, VF is disabled!\n"); 13597a01c897SSalil Mehta return ret; 13607a01c897SSalil Mehta } 13616988eb2aSSalil Mehta 13626988eb2aSSalil Mehta /* bring up the nic client again */ 13636a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 13646a5f6fa3SHuazhong Tan if (ret) 13656a5f6fa3SHuazhong Tan return ret; 13666988eb2aSSalil Mehta 13671f609492SYunsheng Lin return hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT); 13686988eb2aSSalil Mehta } 13696988eb2aSSalil Mehta 1370dea846e8SHuazhong Tan static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1371dea846e8SHuazhong Tan { 1372dea846e8SHuazhong Tan int ret = 0; 1373dea846e8SHuazhong Tan 1374dea846e8SHuazhong Tan switch (hdev->reset_type) { 1375dea846e8SHuazhong Tan case HNAE3_VF_FUNC_RESET: 1376dea846e8SHuazhong Tan ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1377dea846e8SHuazhong Tan 0, true, NULL, sizeof(u8)); 1378dea846e8SHuazhong Tan break; 13796ff3cf07SHuazhong Tan case HNAE3_FLR_RESET: 13806ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 13816ff3cf07SHuazhong Tan break; 1382dea846e8SHuazhong Tan default: 1383dea846e8SHuazhong Tan break; 1384dea846e8SHuazhong Tan } 1385dea846e8SHuazhong Tan 1386ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1387ef5f8e50SHuazhong Tan 1388dea846e8SHuazhong Tan dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1389dea846e8SHuazhong Tan hdev->reset_type, ret); 1390dea846e8SHuazhong Tan 1391dea846e8SHuazhong Tan return ret; 1392dea846e8SHuazhong Tan } 1393dea846e8SHuazhong Tan 13946988eb2aSSalil Mehta static int hclgevf_reset(struct hclgevf_dev *hdev) 13956988eb2aSSalil Mehta { 1396dea846e8SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 13976988eb2aSSalil Mehta int ret; 13986988eb2aSSalil Mehta 1399dea846e8SHuazhong Tan /* Initialize ae_dev reset status as well, in case enet layer wants to 1400dea846e8SHuazhong Tan * know if device is undergoing reset 1401dea846e8SHuazhong Tan */ 1402dea846e8SHuazhong Tan ae_dev->reset_type = hdev->reset_type; 14034d60291bSHuazhong Tan hdev->reset_count++; 14046988eb2aSSalil Mehta rtnl_lock(); 14056988eb2aSSalil Mehta 14066988eb2aSSalil Mehta /* bring down the nic to stop any ongoing TX/RX */ 14076a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 14086a5f6fa3SHuazhong Tan if (ret) 14096a5f6fa3SHuazhong Tan goto err_reset_lock; 14106988eb2aSSalil Mehta 141129118ab9SHuazhong Tan rtnl_unlock(); 141229118ab9SHuazhong Tan 14136a5f6fa3SHuazhong Tan ret = hclgevf_reset_prepare_wait(hdev); 14146a5f6fa3SHuazhong Tan if (ret) 14156a5f6fa3SHuazhong Tan goto err_reset; 1416dea846e8SHuazhong Tan 14176988eb2aSSalil Mehta /* check if VF could successfully fetch the hardware reset completion 14186988eb2aSSalil Mehta * status from the hardware 14196988eb2aSSalil Mehta */ 14206988eb2aSSalil Mehta ret = hclgevf_reset_wait(hdev); 14216988eb2aSSalil Mehta if (ret) { 14226988eb2aSSalil Mehta /* can't do much in this situation, will disable VF */ 14236988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, 14246988eb2aSSalil Mehta "VF failed(=%d) to fetch H/W reset completion status\n", 14256988eb2aSSalil Mehta ret); 14266a5f6fa3SHuazhong Tan goto err_reset; 14276988eb2aSSalil Mehta } 14286988eb2aSSalil Mehta 142929118ab9SHuazhong Tan rtnl_lock(); 143029118ab9SHuazhong Tan 14316988eb2aSSalil Mehta /* now, re-initialize the nic client and ae device*/ 14326988eb2aSSalil Mehta ret = hclgevf_reset_stack(hdev); 14336a5f6fa3SHuazhong Tan if (ret) { 14346988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 14356a5f6fa3SHuazhong Tan goto err_reset_lock; 14366a5f6fa3SHuazhong Tan } 14376988eb2aSSalil Mehta 14386988eb2aSSalil Mehta /* bring up the nic to enable TX/RX again */ 14396a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 14406a5f6fa3SHuazhong Tan if (ret) 14416a5f6fa3SHuazhong Tan goto err_reset_lock; 14426988eb2aSSalil Mehta 14436988eb2aSSalil Mehta rtnl_unlock(); 14446988eb2aSSalil Mehta 1445b644a8d4SHuazhong Tan hdev->last_reset_time = jiffies; 1446b644a8d4SHuazhong Tan ae_dev->reset_type = HNAE3_NONE_RESET; 1447b644a8d4SHuazhong Tan 14486988eb2aSSalil Mehta return ret; 14496a5f6fa3SHuazhong Tan err_reset_lock: 14506a5f6fa3SHuazhong Tan rtnl_unlock(); 14516a5f6fa3SHuazhong Tan err_reset: 14526a5f6fa3SHuazhong Tan /* When VF reset failed, only the higher level reset asserted by PF 14536a5f6fa3SHuazhong Tan * can restore it, so re-initialize the command queue to receive 14546a5f6fa3SHuazhong Tan * this higher reset event. 14556a5f6fa3SHuazhong Tan */ 14566a5f6fa3SHuazhong Tan hclgevf_cmd_init(hdev); 14576a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "failed to reset VF\n"); 14586a5f6fa3SHuazhong Tan 14596a5f6fa3SHuazhong Tan return ret; 14606988eb2aSSalil Mehta } 14616988eb2aSSalil Mehta 1462720bd583SHuazhong Tan static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1463720bd583SHuazhong Tan unsigned long *addr) 1464720bd583SHuazhong Tan { 1465720bd583SHuazhong Tan enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1466720bd583SHuazhong Tan 1467dea846e8SHuazhong Tan /* return the highest priority reset level amongst all */ 1468b90fcc5bSHuazhong Tan if (test_bit(HNAE3_VF_RESET, addr)) { 1469b90fcc5bSHuazhong Tan rst_level = HNAE3_VF_RESET; 1470b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_RESET, addr); 1471b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1472b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1473b90fcc5bSHuazhong Tan } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1474dea846e8SHuazhong Tan rst_level = HNAE3_VF_FULL_RESET; 1475dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FULL_RESET, addr); 1476dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1477aa5c4f17SHuazhong Tan } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1478aa5c4f17SHuazhong Tan rst_level = HNAE3_VF_PF_FUNC_RESET; 1479aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1480aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1481dea846e8SHuazhong Tan } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1482dea846e8SHuazhong Tan rst_level = HNAE3_VF_FUNC_RESET; 1483dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 14846ff3cf07SHuazhong Tan } else if (test_bit(HNAE3_FLR_RESET, addr)) { 14856ff3cf07SHuazhong Tan rst_level = HNAE3_FLR_RESET; 14866ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_RESET, addr); 1487720bd583SHuazhong Tan } 1488720bd583SHuazhong Tan 1489720bd583SHuazhong Tan return rst_level; 1490720bd583SHuazhong Tan } 1491720bd583SHuazhong Tan 14926ae4e733SShiju Jose static void hclgevf_reset_event(struct pci_dev *pdev, 14936ae4e733SShiju Jose struct hnae3_handle *handle) 14946d4c3981SSalil Mehta { 14956ff3cf07SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 14966ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 14976d4c3981SSalil Mehta 14986d4c3981SSalil Mehta dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 14996d4c3981SSalil Mehta 15006ff3cf07SHuazhong Tan if (hdev->default_reset_request) 15010742ed7cSHuazhong Tan hdev->reset_level = 1502720bd583SHuazhong Tan hclgevf_get_reset_level(hdev, 1503720bd583SHuazhong Tan &hdev->default_reset_request); 1504720bd583SHuazhong Tan else 1505dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 15066d4c3981SSalil Mehta 1507436667d2SSalil Mehta /* reset of this VF requested */ 1508436667d2SSalil Mehta set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1509436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 15106d4c3981SSalil Mehta 15110742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 15126d4c3981SSalil Mehta } 15136d4c3981SSalil Mehta 1514720bd583SHuazhong Tan static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1515720bd583SHuazhong Tan enum hnae3_reset_type rst_type) 1516720bd583SHuazhong Tan { 1517720bd583SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1518720bd583SHuazhong Tan 1519720bd583SHuazhong Tan set_bit(rst_type, &hdev->default_reset_request); 1520720bd583SHuazhong Tan } 1521720bd583SHuazhong Tan 15226ff3cf07SHuazhong Tan static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 15236ff3cf07SHuazhong Tan { 15246ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_MS 100 15256ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_CNT 50 15266ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 15276ff3cf07SHuazhong Tan int cnt = 0; 15286ff3cf07SHuazhong Tan 15296ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 15306ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DONE, &hdev->flr_state); 15316ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request); 15326ff3cf07SHuazhong Tan hclgevf_reset_event(hdev->pdev, NULL); 15336ff3cf07SHuazhong Tan 15346ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) && 15356ff3cf07SHuazhong Tan cnt++ < HCLGEVF_FLR_WAIT_CNT) 15366ff3cf07SHuazhong Tan msleep(HCLGEVF_FLR_WAIT_MS); 15376ff3cf07SHuazhong Tan 15386ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state)) 15396ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 15406ff3cf07SHuazhong Tan "flr wait down timeout: %d\n", cnt); 15416ff3cf07SHuazhong Tan } 15426ff3cf07SHuazhong Tan 1543e2cb1decSSalil Mehta static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1544e2cb1decSSalil Mehta { 1545e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1546e2cb1decSSalil Mehta 1547e2cb1decSSalil Mehta return hdev->fw_version; 1548e2cb1decSSalil Mehta } 1549e2cb1decSSalil Mehta 1550e2cb1decSSalil Mehta static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1551e2cb1decSSalil Mehta { 1552e2cb1decSSalil Mehta struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1553e2cb1decSSalil Mehta 1554e2cb1decSSalil Mehta vector->vector_irq = pci_irq_vector(hdev->pdev, 1555e2cb1decSSalil Mehta HCLGEVF_MISC_VECTOR_NUM); 1556e2cb1decSSalil Mehta vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1557e2cb1decSSalil Mehta /* vector status always valid for Vector 0 */ 1558e2cb1decSSalil Mehta hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1559e2cb1decSSalil Mehta hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1560e2cb1decSSalil Mehta 1561e2cb1decSSalil Mehta hdev->num_msi_left -= 1; 1562e2cb1decSSalil Mehta hdev->num_msi_used += 1; 1563e2cb1decSSalil Mehta } 1564e2cb1decSSalil Mehta 156535a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 156635a1e503SSalil Mehta { 156735a1e503SSalil Mehta if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) && 156835a1e503SSalil Mehta !test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) { 156935a1e503SSalil Mehta set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 157035a1e503SSalil Mehta schedule_work(&hdev->rst_service_task); 157135a1e503SSalil Mehta } 157235a1e503SSalil Mehta } 157335a1e503SSalil Mehta 157407a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1575e2cb1decSSalil Mehta { 157607a0556aSSalil Mehta if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) && 157707a0556aSSalil Mehta !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) { 157807a0556aSSalil Mehta set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1579e2cb1decSSalil Mehta schedule_work(&hdev->mbx_service_task); 1580e2cb1decSSalil Mehta } 158107a0556aSSalil Mehta } 1582e2cb1decSSalil Mehta 1583e2cb1decSSalil Mehta static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 1584e2cb1decSSalil Mehta { 1585e2cb1decSSalil Mehta if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 1586e2cb1decSSalil Mehta !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 1587e2cb1decSSalil Mehta schedule_work(&hdev->service_task); 1588e2cb1decSSalil Mehta } 1589e2cb1decSSalil Mehta 1590436667d2SSalil Mehta static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev) 1591436667d2SSalil Mehta { 159207a0556aSSalil Mehta /* if we have any pending mailbox event then schedule the mbx task */ 159307a0556aSSalil Mehta if (hdev->mbx_event_pending) 159407a0556aSSalil Mehta hclgevf_mbx_task_schedule(hdev); 159507a0556aSSalil Mehta 1596436667d2SSalil Mehta if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state)) 1597436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 1598436667d2SSalil Mehta } 1599436667d2SSalil Mehta 1600e2cb1decSSalil Mehta static void hclgevf_service_timer(struct timer_list *t) 1601e2cb1decSSalil Mehta { 1602e2cb1decSSalil Mehta struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 1603e2cb1decSSalil Mehta 1604e2cb1decSSalil Mehta mod_timer(&hdev->service_timer, jiffies + 5 * HZ); 1605e2cb1decSSalil Mehta 1606e2cb1decSSalil Mehta hclgevf_task_schedule(hdev); 1607e2cb1decSSalil Mehta } 1608e2cb1decSSalil Mehta 160935a1e503SSalil Mehta static void hclgevf_reset_service_task(struct work_struct *work) 161035a1e503SSalil Mehta { 161135a1e503SSalil Mehta struct hclgevf_dev *hdev = 161235a1e503SSalil Mehta container_of(work, struct hclgevf_dev, rst_service_task); 1613a8dedb65SSalil Mehta int ret; 161435a1e503SSalil Mehta 161535a1e503SSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 161635a1e503SSalil Mehta return; 161735a1e503SSalil Mehta 161835a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 161935a1e503SSalil Mehta 1620436667d2SSalil Mehta if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1621436667d2SSalil Mehta &hdev->reset_state)) { 1622436667d2SSalil Mehta /* PF has initmated that it is about to reset the hardware. 1623436667d2SSalil Mehta * We now have to poll & check if harware has actually completed 1624436667d2SSalil Mehta * the reset sequence. On hardware reset completion, VF needs to 1625436667d2SSalil Mehta * reset the client and ae device. 162635a1e503SSalil Mehta */ 1627436667d2SSalil Mehta hdev->reset_attempts = 0; 1628436667d2SSalil Mehta 1629dea846e8SHuazhong Tan hdev->last_reset_time = jiffies; 1630dea846e8SHuazhong Tan while ((hdev->reset_type = 1631dea846e8SHuazhong Tan hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 1632dea846e8SHuazhong Tan != HNAE3_NONE_RESET) { 16336988eb2aSSalil Mehta ret = hclgevf_reset(hdev); 16346988eb2aSSalil Mehta if (ret) 1635dea846e8SHuazhong Tan dev_err(&hdev->pdev->dev, 1636dea846e8SHuazhong Tan "VF stack reset failed %d.\n", ret); 1637dea846e8SHuazhong Tan } 1638436667d2SSalil Mehta } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1639436667d2SSalil Mehta &hdev->reset_state)) { 1640436667d2SSalil Mehta /* we could be here when either of below happens: 1641436667d2SSalil Mehta * 1. reset was initiated due to watchdog timeout due to 1642436667d2SSalil Mehta * a. IMP was earlier reset and our TX got choked down and 1643436667d2SSalil Mehta * which resulted in watchdog reacting and inducing VF 1644436667d2SSalil Mehta * reset. This also means our cmdq would be unreliable. 1645436667d2SSalil Mehta * b. problem in TX due to other lower layer(example link 1646436667d2SSalil Mehta * layer not functioning properly etc.) 1647436667d2SSalil Mehta * 2. VF reset might have been initiated due to some config 1648436667d2SSalil Mehta * change. 1649436667d2SSalil Mehta * 1650436667d2SSalil Mehta * NOTE: Theres no clear way to detect above cases than to react 1651436667d2SSalil Mehta * to the response of PF for this reset request. PF will ack the 1652436667d2SSalil Mehta * 1b and 2. cases but we will not get any intimation about 1a 1653436667d2SSalil Mehta * from PF as cmdq would be in unreliable state i.e. mailbox 1654436667d2SSalil Mehta * communication between PF and VF would be broken. 1655436667d2SSalil Mehta */ 1656436667d2SSalil Mehta 1657436667d2SSalil Mehta /* if we are never geting into pending state it means either: 1658436667d2SSalil Mehta * 1. PF is not receiving our request which could be due to IMP 1659436667d2SSalil Mehta * reset 1660436667d2SSalil Mehta * 2. PF is screwed 1661436667d2SSalil Mehta * We cannot do much for 2. but to check first we can try reset 1662436667d2SSalil Mehta * our PCIe + stack and see if it alleviates the problem. 1663436667d2SSalil Mehta */ 1664436667d2SSalil Mehta if (hdev->reset_attempts > 3) { 1665436667d2SSalil Mehta /* prepare for full reset of stack + pcie interface */ 1666dea846e8SHuazhong Tan set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1667436667d2SSalil Mehta 1668436667d2SSalil Mehta /* "defer" schedule the reset task again */ 1669436667d2SSalil Mehta set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1670436667d2SSalil Mehta } else { 1671436667d2SSalil Mehta hdev->reset_attempts++; 1672436667d2SSalil Mehta 1673dea846e8SHuazhong Tan set_bit(hdev->reset_level, &hdev->reset_pending); 1674dea846e8SHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1675436667d2SSalil Mehta } 1676dea846e8SHuazhong Tan hclgevf_reset_task_schedule(hdev); 1677436667d2SSalil Mehta } 167835a1e503SSalil Mehta 167935a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 168035a1e503SSalil Mehta } 168135a1e503SSalil Mehta 1682e2cb1decSSalil Mehta static void hclgevf_mailbox_service_task(struct work_struct *work) 1683e2cb1decSSalil Mehta { 1684e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1685e2cb1decSSalil Mehta 1686e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 1687e2cb1decSSalil Mehta 1688e2cb1decSSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1689e2cb1decSSalil Mehta return; 1690e2cb1decSSalil Mehta 1691e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1692e2cb1decSSalil Mehta 169307a0556aSSalil Mehta hclgevf_mbx_async_handler(hdev); 1694e2cb1decSSalil Mehta 1695e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1696e2cb1decSSalil Mehta } 1697e2cb1decSSalil Mehta 1698a6d818e3SYunsheng Lin static void hclgevf_keep_alive_timer(struct timer_list *t) 1699a6d818e3SYunsheng Lin { 1700a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = from_timer(hdev, t, keep_alive_timer); 1701a6d818e3SYunsheng Lin 1702a6d818e3SYunsheng Lin schedule_work(&hdev->keep_alive_task); 1703a6d818e3SYunsheng Lin mod_timer(&hdev->keep_alive_timer, jiffies + 2 * HZ); 1704a6d818e3SYunsheng Lin } 1705a6d818e3SYunsheng Lin 1706a6d818e3SYunsheng Lin static void hclgevf_keep_alive_task(struct work_struct *work) 1707a6d818e3SYunsheng Lin { 1708a6d818e3SYunsheng Lin struct hclgevf_dev *hdev; 1709a6d818e3SYunsheng Lin u8 respmsg; 1710a6d818e3SYunsheng Lin int ret; 1711a6d818e3SYunsheng Lin 1712a6d818e3SYunsheng Lin hdev = container_of(work, struct hclgevf_dev, keep_alive_task); 1713c59a85c0SJian Shen 1714c59a85c0SJian Shen if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1715c59a85c0SJian Shen return; 1716c59a85c0SJian Shen 1717a6d818e3SYunsheng Lin ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL, 1718a6d818e3SYunsheng Lin 0, false, &respmsg, sizeof(u8)); 1719a6d818e3SYunsheng Lin if (ret) 1720a6d818e3SYunsheng Lin dev_err(&hdev->pdev->dev, 1721a6d818e3SYunsheng Lin "VF sends keep alive cmd failed(=%d)\n", ret); 1722a6d818e3SYunsheng Lin } 1723a6d818e3SYunsheng Lin 1724e2cb1decSSalil Mehta static void hclgevf_service_task(struct work_struct *work) 1725e2cb1decSSalil Mehta { 1726e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1727e2cb1decSSalil Mehta 1728e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, service_task); 1729e2cb1decSSalil Mehta 1730e2cb1decSSalil Mehta /* request the link status from the PF. PF would be able to tell VF 1731e2cb1decSSalil Mehta * about such updates in future so we might remove this later 1732e2cb1decSSalil Mehta */ 1733e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1734e2cb1decSSalil Mehta 17359194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 17369194d18bSliuzhongzhu 1737436667d2SSalil Mehta hclgevf_deferred_task_schedule(hdev); 1738436667d2SSalil Mehta 1739e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1740e2cb1decSSalil Mehta } 1741e2cb1decSSalil Mehta 1742e2cb1decSSalil Mehta static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1743e2cb1decSSalil Mehta { 1744e2cb1decSSalil Mehta hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1745e2cb1decSSalil Mehta } 1746e2cb1decSSalil Mehta 1747b90fcc5bSHuazhong Tan static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1748b90fcc5bSHuazhong Tan u32 *clearval) 1749e2cb1decSSalil Mehta { 1750b90fcc5bSHuazhong Tan u32 cmdq_src_reg, rst_ing_reg; 1751e2cb1decSSalil Mehta 1752e2cb1decSSalil Mehta /* fetch the events from their corresponding regs */ 1753e2cb1decSSalil Mehta cmdq_src_reg = hclgevf_read_dev(&hdev->hw, 1754e2cb1decSSalil Mehta HCLGEVF_VECTOR0_CMDQ_SRC_REG); 1755e2cb1decSSalil Mehta 1756b90fcc5bSHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_src_reg) { 1757b90fcc5bSHuazhong Tan rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1758b90fcc5bSHuazhong Tan dev_info(&hdev->pdev->dev, 1759b90fcc5bSHuazhong Tan "receive reset interrupt 0x%x!\n", rst_ing_reg); 1760b90fcc5bSHuazhong Tan set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1761b90fcc5bSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1762ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1763b90fcc5bSHuazhong Tan cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RST_INT_B); 1764b90fcc5bSHuazhong Tan *clearval = cmdq_src_reg; 1765b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_RST; 1766b90fcc5bSHuazhong Tan } 1767b90fcc5bSHuazhong Tan 1768e2cb1decSSalil Mehta /* check for vector0 mailbox(=CMDQ RX) event source */ 1769e2cb1decSSalil Mehta if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 1770e2cb1decSSalil Mehta cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1771e2cb1decSSalil Mehta *clearval = cmdq_src_reg; 1772b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_MBX; 1773e2cb1decSSalil Mehta } 1774e2cb1decSSalil Mehta 1775e2cb1decSSalil Mehta dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 1776e2cb1decSSalil Mehta 1777b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_OTHER; 1778e2cb1decSSalil Mehta } 1779e2cb1decSSalil Mehta 1780e2cb1decSSalil Mehta static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1781e2cb1decSSalil Mehta { 1782e2cb1decSSalil Mehta writel(en ? 1 : 0, vector->addr); 1783e2cb1decSSalil Mehta } 1784e2cb1decSSalil Mehta 1785e2cb1decSSalil Mehta static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1786e2cb1decSSalil Mehta { 1787b90fcc5bSHuazhong Tan enum hclgevf_evt_cause event_cause; 1788e2cb1decSSalil Mehta struct hclgevf_dev *hdev = data; 1789e2cb1decSSalil Mehta u32 clearval; 1790e2cb1decSSalil Mehta 1791e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 1792b90fcc5bSHuazhong Tan event_cause = hclgevf_check_evt_cause(hdev, &clearval); 1793e2cb1decSSalil Mehta 1794b90fcc5bSHuazhong Tan switch (event_cause) { 1795b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_RST: 1796b90fcc5bSHuazhong Tan hclgevf_reset_task_schedule(hdev); 1797b90fcc5bSHuazhong Tan break; 1798b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_MBX: 179907a0556aSSalil Mehta hclgevf_mbx_handler(hdev); 1800b90fcc5bSHuazhong Tan break; 1801b90fcc5bSHuazhong Tan default: 1802b90fcc5bSHuazhong Tan break; 1803b90fcc5bSHuazhong Tan } 1804e2cb1decSSalil Mehta 1805b90fcc5bSHuazhong Tan if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 1806e2cb1decSSalil Mehta hclgevf_clear_event_cause(hdev, clearval); 1807e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 1808b90fcc5bSHuazhong Tan } 1809e2cb1decSSalil Mehta 1810e2cb1decSSalil Mehta return IRQ_HANDLED; 1811e2cb1decSSalil Mehta } 1812e2cb1decSSalil Mehta 1813e2cb1decSSalil Mehta static int hclgevf_configure(struct hclgevf_dev *hdev) 1814e2cb1decSSalil Mehta { 1815e2cb1decSSalil Mehta int ret; 1816e2cb1decSSalil Mehta 1817e2cb1decSSalil Mehta /* get queue configuration from PF */ 18186cee6fc3SJian Shen ret = hclgevf_get_queue_info(hdev); 1819e2cb1decSSalil Mehta if (ret) 1820e2cb1decSSalil Mehta return ret; 1821c0425944SPeng Li 1822c0425944SPeng Li /* get queue depth info from PF */ 1823c0425944SPeng Li ret = hclgevf_get_queue_depth(hdev); 1824c0425944SPeng Li if (ret) 1825c0425944SPeng Li return ret; 1826c0425944SPeng Li 1827e2cb1decSSalil Mehta /* get tc configuration from PF */ 1828e2cb1decSSalil Mehta return hclgevf_get_tc_info(hdev); 1829e2cb1decSSalil Mehta } 1830e2cb1decSSalil Mehta 18317a01c897SSalil Mehta static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 18327a01c897SSalil Mehta { 18337a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 18341154bb26SPeng Li struct hclgevf_dev *hdev; 18357a01c897SSalil Mehta 18367a01c897SSalil Mehta hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 18377a01c897SSalil Mehta if (!hdev) 18387a01c897SSalil Mehta return -ENOMEM; 18397a01c897SSalil Mehta 18407a01c897SSalil Mehta hdev->pdev = pdev; 18417a01c897SSalil Mehta hdev->ae_dev = ae_dev; 18427a01c897SSalil Mehta ae_dev->priv = hdev; 18437a01c897SSalil Mehta 18447a01c897SSalil Mehta return 0; 18457a01c897SSalil Mehta } 18467a01c897SSalil Mehta 1847e2cb1decSSalil Mehta static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 1848e2cb1decSSalil Mehta { 1849e2cb1decSSalil Mehta struct hnae3_handle *roce = &hdev->roce; 1850e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 1851e2cb1decSSalil Mehta 185207acf909SJian Shen roce->rinfo.num_vectors = hdev->num_roce_msix; 1853e2cb1decSSalil Mehta 1854e2cb1decSSalil Mehta if (hdev->num_msi_left < roce->rinfo.num_vectors || 1855e2cb1decSSalil Mehta hdev->num_msi_left == 0) 1856e2cb1decSSalil Mehta return -EINVAL; 1857e2cb1decSSalil Mehta 185807acf909SJian Shen roce->rinfo.base_vector = hdev->roce_base_vector; 1859e2cb1decSSalil Mehta 1860e2cb1decSSalil Mehta roce->rinfo.netdev = nic->kinfo.netdev; 1861e2cb1decSSalil Mehta roce->rinfo.roce_io_base = hdev->hw.io_base; 1862e2cb1decSSalil Mehta 1863e2cb1decSSalil Mehta roce->pdev = nic->pdev; 1864e2cb1decSSalil Mehta roce->ae_algo = nic->ae_algo; 1865e2cb1decSSalil Mehta roce->numa_node_mask = nic->numa_node_mask; 1866e2cb1decSSalil Mehta 1867e2cb1decSSalil Mehta return 0; 1868e2cb1decSSalil Mehta } 1869e2cb1decSSalil Mehta 1870b26a6feaSPeng Li static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 1871b26a6feaSPeng Li { 1872b26a6feaSPeng Li struct hclgevf_cfg_gro_status_cmd *req; 1873b26a6feaSPeng Li struct hclgevf_desc desc; 1874b26a6feaSPeng Li int ret; 1875b26a6feaSPeng Li 1876b26a6feaSPeng Li if (!hnae3_dev_gro_supported(hdev)) 1877b26a6feaSPeng Li return 0; 1878b26a6feaSPeng Li 1879b26a6feaSPeng Li hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 1880b26a6feaSPeng Li false); 1881b26a6feaSPeng Li req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 1882b26a6feaSPeng Li 1883b26a6feaSPeng Li req->gro_en = cpu_to_le16(en ? 1 : 0); 1884b26a6feaSPeng Li 1885b26a6feaSPeng Li ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1886b26a6feaSPeng Li if (ret) 1887b26a6feaSPeng Li dev_err(&hdev->pdev->dev, 1888b26a6feaSPeng Li "VF GRO hardware config cmd failed, ret = %d.\n", ret); 1889b26a6feaSPeng Li 1890b26a6feaSPeng Li return ret; 1891b26a6feaSPeng Li } 1892b26a6feaSPeng Li 1893e2cb1decSSalil Mehta static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 1894e2cb1decSSalil Mehta { 1895e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1896e2cb1decSSalil Mehta int i, ret; 1897e2cb1decSSalil Mehta 1898e2cb1decSSalil Mehta rss_cfg->rss_size = hdev->rss_size_max; 1899e2cb1decSSalil Mehta 1900374ad291SJian Shen if (hdev->pdev->revision >= 0x21) { 1901472d7eceSJian Shen rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 1902472d7eceSJian Shen memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 1903374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 1904374ad291SJian Shen 1905374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 1906374ad291SJian Shen rss_cfg->rss_hash_key); 1907374ad291SJian Shen if (ret) 1908374ad291SJian Shen return ret; 1909d97b3072SJian Shen 1910d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = 1911d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1912d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = 1913d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1914d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = 1915d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1916d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = 1917d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1918d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = 1919d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1920d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = 1921d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1922d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = 1923d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1924d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = 1925d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1926d97b3072SJian Shen 1927d97b3072SJian Shen ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 1928d97b3072SJian Shen if (ret) 1929d97b3072SJian Shen return ret; 1930d97b3072SJian Shen 1931374ad291SJian Shen } 1932374ad291SJian Shen 1933e2cb1decSSalil Mehta /* Initialize RSS indirect table for each vport */ 1934e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 1935e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max; 1936e2cb1decSSalil Mehta 1937e2cb1decSSalil Mehta ret = hclgevf_set_rss_indir_table(hdev); 1938e2cb1decSSalil Mehta if (ret) 1939e2cb1decSSalil Mehta return ret; 1940e2cb1decSSalil Mehta 1941e2cb1decSSalil Mehta return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max); 1942e2cb1decSSalil Mehta } 1943e2cb1decSSalil Mehta 1944e2cb1decSSalil Mehta static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 1945e2cb1decSSalil Mehta { 1946e2cb1decSSalil Mehta /* other vlan config(like, VLAN TX/RX offload) would also be added 1947e2cb1decSSalil Mehta * here later 1948e2cb1decSSalil Mehta */ 1949e2cb1decSSalil Mehta return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 1950e2cb1decSSalil Mehta false); 1951e2cb1decSSalil Mehta } 1952e2cb1decSSalil Mehta 19538cdb992fSJian Shen static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 19548cdb992fSJian Shen { 19558cdb992fSJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 19568cdb992fSJian Shen 19578cdb992fSJian Shen if (enable) { 19588cdb992fSJian Shen mod_timer(&hdev->service_timer, jiffies + HZ); 19598cdb992fSJian Shen } else { 19608cdb992fSJian Shen del_timer_sync(&hdev->service_timer); 19618cdb992fSJian Shen cancel_work_sync(&hdev->service_task); 19628cdb992fSJian Shen clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 19638cdb992fSJian Shen } 19648cdb992fSJian Shen } 19658cdb992fSJian Shen 1966e2cb1decSSalil Mehta static int hclgevf_ae_start(struct hnae3_handle *handle) 1967e2cb1decSSalil Mehta { 1968e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1969e2cb1decSSalil Mehta 1970e2cb1decSSalil Mehta /* reset tqp stats */ 1971e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 1972e2cb1decSSalil Mehta 1973e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1974e2cb1decSSalil Mehta 19759194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 19769194d18bSliuzhongzhu 1977e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1978e2cb1decSSalil Mehta 1979e2cb1decSSalil Mehta return 0; 1980e2cb1decSSalil Mehta } 1981e2cb1decSSalil Mehta 1982e2cb1decSSalil Mehta static void hclgevf_ae_stop(struct hnae3_handle *handle) 1983e2cb1decSSalil Mehta { 1984e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 198539cfbc9cSHuazhong Tan int i; 1986e2cb1decSSalil Mehta 19872f7e4896SFuyun Liang set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 19882f7e4896SFuyun Liang 198939cfbc9cSHuazhong Tan for (i = 0; i < handle->kinfo.num_tqps; i++) 199039cfbc9cSHuazhong Tan hclgevf_reset_tqp(handle, i); 199139cfbc9cSHuazhong Tan 1992e2cb1decSSalil Mehta /* reset tqp stats */ 1993e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 19948cc6c1f7SFuyun Liang hclgevf_update_link_status(hdev, 0); 1995e2cb1decSSalil Mehta } 1996e2cb1decSSalil Mehta 1997a6d818e3SYunsheng Lin static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 1998a6d818e3SYunsheng Lin { 1999a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2000a6d818e3SYunsheng Lin u8 msg_data; 2001a6d818e3SYunsheng Lin 2002a6d818e3SYunsheng Lin msg_data = alive ? 1 : 0; 2003a6d818e3SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE, 2004a6d818e3SYunsheng Lin 0, &msg_data, 1, false, NULL, 0); 2005a6d818e3SYunsheng Lin } 2006a6d818e3SYunsheng Lin 2007a6d818e3SYunsheng Lin static int hclgevf_client_start(struct hnae3_handle *handle) 2008a6d818e3SYunsheng Lin { 2009a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2010a6d818e3SYunsheng Lin 2011a6d818e3SYunsheng Lin mod_timer(&hdev->keep_alive_timer, jiffies + 2 * HZ); 2012a6d818e3SYunsheng Lin return hclgevf_set_alive(handle, true); 2013a6d818e3SYunsheng Lin } 2014a6d818e3SYunsheng Lin 2015a6d818e3SYunsheng Lin static void hclgevf_client_stop(struct hnae3_handle *handle) 2016a6d818e3SYunsheng Lin { 2017a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2018a6d818e3SYunsheng Lin int ret; 2019a6d818e3SYunsheng Lin 2020a6d818e3SYunsheng Lin ret = hclgevf_set_alive(handle, false); 2021a6d818e3SYunsheng Lin if (ret) 2022a6d818e3SYunsheng Lin dev_warn(&hdev->pdev->dev, 2023a6d818e3SYunsheng Lin "%s failed %d\n", __func__, ret); 2024a6d818e3SYunsheng Lin 2025a6d818e3SYunsheng Lin del_timer_sync(&hdev->keep_alive_timer); 2026a6d818e3SYunsheng Lin cancel_work_sync(&hdev->keep_alive_task); 2027a6d818e3SYunsheng Lin } 2028a6d818e3SYunsheng Lin 2029e2cb1decSSalil Mehta static void hclgevf_state_init(struct hclgevf_dev *hdev) 2030e2cb1decSSalil Mehta { 2031e2cb1decSSalil Mehta /* setup tasks for the MBX */ 2032e2cb1decSSalil Mehta INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 2033e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2034e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2035e2cb1decSSalil Mehta 2036e2cb1decSSalil Mehta /* setup tasks for service timer */ 2037e2cb1decSSalil Mehta timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 2038e2cb1decSSalil Mehta 2039e2cb1decSSalil Mehta INIT_WORK(&hdev->service_task, hclgevf_service_task); 2040e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2041e2cb1decSSalil Mehta 204235a1e503SSalil Mehta INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task); 204335a1e503SSalil Mehta 2044e2cb1decSSalil Mehta mutex_init(&hdev->mbx_resp.mbx_mutex); 2045e2cb1decSSalil Mehta 2046e2cb1decSSalil Mehta /* bring the device down */ 2047e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2048e2cb1decSSalil Mehta } 2049e2cb1decSSalil Mehta 2050e2cb1decSSalil Mehta static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2051e2cb1decSSalil Mehta { 2052e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2053e2cb1decSSalil Mehta 2054e2cb1decSSalil Mehta if (hdev->service_timer.function) 2055e2cb1decSSalil Mehta del_timer_sync(&hdev->service_timer); 2056e2cb1decSSalil Mehta if (hdev->service_task.func) 2057e2cb1decSSalil Mehta cancel_work_sync(&hdev->service_task); 2058e2cb1decSSalil Mehta if (hdev->mbx_service_task.func) 2059e2cb1decSSalil Mehta cancel_work_sync(&hdev->mbx_service_task); 206035a1e503SSalil Mehta if (hdev->rst_service_task.func) 206135a1e503SSalil Mehta cancel_work_sync(&hdev->rst_service_task); 2062e2cb1decSSalil Mehta 2063e2cb1decSSalil Mehta mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2064e2cb1decSSalil Mehta } 2065e2cb1decSSalil Mehta 2066e2cb1decSSalil Mehta static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2067e2cb1decSSalil Mehta { 2068e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2069e2cb1decSSalil Mehta int vectors; 2070e2cb1decSSalil Mehta int i; 2071e2cb1decSSalil Mehta 207207acf909SJian Shen if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) 207307acf909SJian Shen vectors = pci_alloc_irq_vectors(pdev, 207407acf909SJian Shen hdev->roce_base_msix_offset + 1, 207507acf909SJian Shen hdev->num_msi, 207607acf909SJian Shen PCI_IRQ_MSIX); 207707acf909SJian Shen else 2078e2cb1decSSalil Mehta vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 2079e2cb1decSSalil Mehta PCI_IRQ_MSI | PCI_IRQ_MSIX); 208007acf909SJian Shen 2081e2cb1decSSalil Mehta if (vectors < 0) { 2082e2cb1decSSalil Mehta dev_err(&pdev->dev, 2083e2cb1decSSalil Mehta "failed(%d) to allocate MSI/MSI-X vectors\n", 2084e2cb1decSSalil Mehta vectors); 2085e2cb1decSSalil Mehta return vectors; 2086e2cb1decSSalil Mehta } 2087e2cb1decSSalil Mehta if (vectors < hdev->num_msi) 2088e2cb1decSSalil Mehta dev_warn(&hdev->pdev->dev, 2089e2cb1decSSalil Mehta "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2090e2cb1decSSalil Mehta hdev->num_msi, vectors); 2091e2cb1decSSalil Mehta 2092e2cb1decSSalil Mehta hdev->num_msi = vectors; 2093e2cb1decSSalil Mehta hdev->num_msi_left = vectors; 2094e2cb1decSSalil Mehta hdev->base_msi_vector = pdev->irq; 209507acf909SJian Shen hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2096e2cb1decSSalil Mehta 2097e2cb1decSSalil Mehta hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2098e2cb1decSSalil Mehta sizeof(u16), GFP_KERNEL); 2099e2cb1decSSalil Mehta if (!hdev->vector_status) { 2100e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2101e2cb1decSSalil Mehta return -ENOMEM; 2102e2cb1decSSalil Mehta } 2103e2cb1decSSalil Mehta 2104e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 2105e2cb1decSSalil Mehta hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2106e2cb1decSSalil Mehta 2107e2cb1decSSalil Mehta hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2108e2cb1decSSalil Mehta sizeof(int), GFP_KERNEL); 2109e2cb1decSSalil Mehta if (!hdev->vector_irq) { 2110862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2111e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2112e2cb1decSSalil Mehta return -ENOMEM; 2113e2cb1decSSalil Mehta } 2114e2cb1decSSalil Mehta 2115e2cb1decSSalil Mehta return 0; 2116e2cb1decSSalil Mehta } 2117e2cb1decSSalil Mehta 2118e2cb1decSSalil Mehta static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2119e2cb1decSSalil Mehta { 2120e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2121e2cb1decSSalil Mehta 2122862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2123862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_irq); 2124e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2125e2cb1decSSalil Mehta } 2126e2cb1decSSalil Mehta 2127e2cb1decSSalil Mehta static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2128e2cb1decSSalil Mehta { 2129e2cb1decSSalil Mehta int ret = 0; 2130e2cb1decSSalil Mehta 2131e2cb1decSSalil Mehta hclgevf_get_misc_vector(hdev); 2132e2cb1decSSalil Mehta 2133e2cb1decSSalil Mehta ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2134e2cb1decSSalil Mehta 0, "hclgevf_cmd", hdev); 2135e2cb1decSSalil Mehta if (ret) { 2136e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2137e2cb1decSSalil Mehta hdev->misc_vector.vector_irq); 2138e2cb1decSSalil Mehta return ret; 2139e2cb1decSSalil Mehta } 2140e2cb1decSSalil Mehta 21411819e409SXi Wang hclgevf_clear_event_cause(hdev, 0); 21421819e409SXi Wang 2143e2cb1decSSalil Mehta /* enable misc. vector(vector 0) */ 2144e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2145e2cb1decSSalil Mehta 2146e2cb1decSSalil Mehta return ret; 2147e2cb1decSSalil Mehta } 2148e2cb1decSSalil Mehta 2149e2cb1decSSalil Mehta static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2150e2cb1decSSalil Mehta { 2151e2cb1decSSalil Mehta /* disable misc vector(vector 0) */ 2152e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 21531819e409SXi Wang synchronize_irq(hdev->misc_vector.vector_irq); 2154e2cb1decSSalil Mehta free_irq(hdev->misc_vector.vector_irq, hdev); 2155e2cb1decSSalil Mehta hclgevf_free_vector(hdev, 0); 2156e2cb1decSSalil Mehta } 2157e2cb1decSSalil Mehta 2158e718a93fSPeng Li static int hclgevf_init_client_instance(struct hnae3_client *client, 2159e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2160e2cb1decSSalil Mehta { 2161e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2162e2cb1decSSalil Mehta int ret; 2163e2cb1decSSalil Mehta 2164e2cb1decSSalil Mehta switch (client->type) { 2165e2cb1decSSalil Mehta case HNAE3_CLIENT_KNIC: 2166e2cb1decSSalil Mehta hdev->nic_client = client; 2167e2cb1decSSalil Mehta hdev->nic.client = client; 2168e2cb1decSSalil Mehta 2169e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->nic); 2170e2cb1decSSalil Mehta if (ret) 217149dd8054SJian Shen goto clear_nic; 2172e2cb1decSSalil Mehta 2173d9f28fc2SJian Shen hnae3_set_client_init_flag(client, ae_dev, 1); 2174d9f28fc2SJian Shen 2175e2cb1decSSalil Mehta if (hdev->roce_client && hnae3_dev_roce_supported(hdev)) { 2176e2cb1decSSalil Mehta struct hnae3_client *rc = hdev->roce_client; 2177e2cb1decSSalil Mehta 2178e2cb1decSSalil Mehta ret = hclgevf_init_roce_base_info(hdev); 2179e2cb1decSSalil Mehta if (ret) 218049dd8054SJian Shen goto clear_roce; 2181e2cb1decSSalil Mehta ret = rc->ops->init_instance(&hdev->roce); 2182e2cb1decSSalil Mehta if (ret) 218349dd8054SJian Shen goto clear_roce; 2184d9f28fc2SJian Shen 2185d9f28fc2SJian Shen hnae3_set_client_init_flag(hdev->roce_client, ae_dev, 2186d9f28fc2SJian Shen 1); 2187e2cb1decSSalil Mehta } 2188e2cb1decSSalil Mehta break; 2189e2cb1decSSalil Mehta case HNAE3_CLIENT_UNIC: 2190e2cb1decSSalil Mehta hdev->nic_client = client; 2191e2cb1decSSalil Mehta hdev->nic.client = client; 2192e2cb1decSSalil Mehta 2193e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->nic); 2194e2cb1decSSalil Mehta if (ret) 219549dd8054SJian Shen goto clear_nic; 2196d9f28fc2SJian Shen 2197d9f28fc2SJian Shen hnae3_set_client_init_flag(client, ae_dev, 1); 2198e2cb1decSSalil Mehta break; 2199e2cb1decSSalil Mehta case HNAE3_CLIENT_ROCE: 2200544a7bcdSLijun Ou if (hnae3_dev_roce_supported(hdev)) { 2201e2cb1decSSalil Mehta hdev->roce_client = client; 2202e2cb1decSSalil Mehta hdev->roce.client = client; 2203544a7bcdSLijun Ou } 2204e2cb1decSSalil Mehta 2205544a7bcdSLijun Ou if (hdev->roce_client && hdev->nic_client) { 2206e2cb1decSSalil Mehta ret = hclgevf_init_roce_base_info(hdev); 2207e2cb1decSSalil Mehta if (ret) 220849dd8054SJian Shen goto clear_roce; 2209e2cb1decSSalil Mehta 2210e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->roce); 2211e2cb1decSSalil Mehta if (ret) 221249dd8054SJian Shen goto clear_roce; 2213e2cb1decSSalil Mehta } 2214d9f28fc2SJian Shen 2215d9f28fc2SJian Shen hnae3_set_client_init_flag(client, ae_dev, 1); 2216fa7a4bd5SJian Shen break; 2217fa7a4bd5SJian Shen default: 2218fa7a4bd5SJian Shen return -EINVAL; 2219e2cb1decSSalil Mehta } 2220e2cb1decSSalil Mehta 2221e2cb1decSSalil Mehta return 0; 222249dd8054SJian Shen 222349dd8054SJian Shen clear_nic: 222449dd8054SJian Shen hdev->nic_client = NULL; 222549dd8054SJian Shen hdev->nic.client = NULL; 222649dd8054SJian Shen return ret; 222749dd8054SJian Shen clear_roce: 222849dd8054SJian Shen hdev->roce_client = NULL; 222949dd8054SJian Shen hdev->roce.client = NULL; 223049dd8054SJian Shen return ret; 2231e2cb1decSSalil Mehta } 2232e2cb1decSSalil Mehta 2233e718a93fSPeng Li static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2234e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2235e2cb1decSSalil Mehta { 2236e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2237e718a93fSPeng Li 2238e2cb1decSSalil Mehta /* un-init roce, if it exists */ 223949dd8054SJian Shen if (hdev->roce_client) { 2240e2cb1decSSalil Mehta hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 224149dd8054SJian Shen hdev->roce_client = NULL; 224249dd8054SJian Shen hdev->roce.client = NULL; 224349dd8054SJian Shen } 2244e2cb1decSSalil Mehta 2245e2cb1decSSalil Mehta /* un-init nic/unic, if this was not called by roce client */ 224649dd8054SJian Shen if (client->ops->uninit_instance && hdev->nic_client && 224749dd8054SJian Shen client->type != HNAE3_CLIENT_ROCE) { 2248e2cb1decSSalil Mehta client->ops->uninit_instance(&hdev->nic, 0); 224949dd8054SJian Shen hdev->nic_client = NULL; 225049dd8054SJian Shen hdev->nic.client = NULL; 225149dd8054SJian Shen } 2252e2cb1decSSalil Mehta } 2253e2cb1decSSalil Mehta 2254e2cb1decSSalil Mehta static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2255e2cb1decSSalil Mehta { 2256e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2257e2cb1decSSalil Mehta struct hclgevf_hw *hw; 2258e2cb1decSSalil Mehta int ret; 2259e2cb1decSSalil Mehta 2260e2cb1decSSalil Mehta ret = pci_enable_device(pdev); 2261e2cb1decSSalil Mehta if (ret) { 2262e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed to enable PCI device\n"); 22633e249d3bSFuyun Liang return ret; 2264e2cb1decSSalil Mehta } 2265e2cb1decSSalil Mehta 2266e2cb1decSSalil Mehta ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2267e2cb1decSSalil Mehta if (ret) { 2268e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2269e2cb1decSSalil Mehta goto err_disable_device; 2270e2cb1decSSalil Mehta } 2271e2cb1decSSalil Mehta 2272e2cb1decSSalil Mehta ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2273e2cb1decSSalil Mehta if (ret) { 2274e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2275e2cb1decSSalil Mehta goto err_disable_device; 2276e2cb1decSSalil Mehta } 2277e2cb1decSSalil Mehta 2278e2cb1decSSalil Mehta pci_set_master(pdev); 2279e2cb1decSSalil Mehta hw = &hdev->hw; 2280e2cb1decSSalil Mehta hw->hdev = hdev; 22812e1ea493SPeng Li hw->io_base = pci_iomap(pdev, 2, 0); 2282e2cb1decSSalil Mehta if (!hw->io_base) { 2283e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't map configuration register space\n"); 2284e2cb1decSSalil Mehta ret = -ENOMEM; 2285e2cb1decSSalil Mehta goto err_clr_master; 2286e2cb1decSSalil Mehta } 2287e2cb1decSSalil Mehta 2288e2cb1decSSalil Mehta return 0; 2289e2cb1decSSalil Mehta 2290e2cb1decSSalil Mehta err_clr_master: 2291e2cb1decSSalil Mehta pci_clear_master(pdev); 2292e2cb1decSSalil Mehta pci_release_regions(pdev); 2293e2cb1decSSalil Mehta err_disable_device: 2294e2cb1decSSalil Mehta pci_disable_device(pdev); 22953e249d3bSFuyun Liang 2296e2cb1decSSalil Mehta return ret; 2297e2cb1decSSalil Mehta } 2298e2cb1decSSalil Mehta 2299e2cb1decSSalil Mehta static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2300e2cb1decSSalil Mehta { 2301e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2302e2cb1decSSalil Mehta 2303e2cb1decSSalil Mehta pci_iounmap(pdev, hdev->hw.io_base); 2304e2cb1decSSalil Mehta pci_clear_master(pdev); 2305e2cb1decSSalil Mehta pci_release_regions(pdev); 2306e2cb1decSSalil Mehta pci_disable_device(pdev); 2307e2cb1decSSalil Mehta } 2308e2cb1decSSalil Mehta 230907acf909SJian Shen static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 231007acf909SJian Shen { 231107acf909SJian Shen struct hclgevf_query_res_cmd *req; 231207acf909SJian Shen struct hclgevf_desc desc; 231307acf909SJian Shen int ret; 231407acf909SJian Shen 231507acf909SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 231607acf909SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 231707acf909SJian Shen if (ret) { 231807acf909SJian Shen dev_err(&hdev->pdev->dev, 231907acf909SJian Shen "query vf resource failed, ret = %d.\n", ret); 232007acf909SJian Shen return ret; 232107acf909SJian Shen } 232207acf909SJian Shen 232307acf909SJian Shen req = (struct hclgevf_query_res_cmd *)desc.data; 232407acf909SJian Shen 232507acf909SJian Shen if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) { 232607acf909SJian Shen hdev->roce_base_msix_offset = 232707acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 232807acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_M, 232907acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_S); 233007acf909SJian Shen hdev->num_roce_msix = 233107acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 233207acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 233307acf909SJian Shen 233407acf909SJian Shen /* VF should have NIC vectors and Roce vectors, NIC vectors 233507acf909SJian Shen * are queued before Roce vectors. The offset is fixed to 64. 233607acf909SJian Shen */ 233707acf909SJian Shen hdev->num_msi = hdev->num_roce_msix + 233807acf909SJian Shen hdev->roce_base_msix_offset; 233907acf909SJian Shen } else { 234007acf909SJian Shen hdev->num_msi = 234107acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 234207acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 234307acf909SJian Shen } 234407acf909SJian Shen 234507acf909SJian Shen return 0; 234607acf909SJian Shen } 234707acf909SJian Shen 2348862d969aSHuazhong Tan static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2349862d969aSHuazhong Tan { 2350862d969aSHuazhong Tan struct pci_dev *pdev = hdev->pdev; 2351862d969aSHuazhong Tan int ret = 0; 2352862d969aSHuazhong Tan 2353862d969aSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2354862d969aSHuazhong Tan test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2355862d969aSHuazhong Tan hclgevf_misc_irq_uninit(hdev); 2356862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2357862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2358862d969aSHuazhong Tan } 2359862d969aSHuazhong Tan 2360862d969aSHuazhong Tan if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2361862d969aSHuazhong Tan pci_set_master(pdev); 2362862d969aSHuazhong Tan ret = hclgevf_init_msi(hdev); 2363862d969aSHuazhong Tan if (ret) { 2364862d969aSHuazhong Tan dev_err(&pdev->dev, 2365862d969aSHuazhong Tan "failed(%d) to init MSI/MSI-X\n", ret); 2366862d969aSHuazhong Tan return ret; 2367862d969aSHuazhong Tan } 2368862d969aSHuazhong Tan 2369862d969aSHuazhong Tan ret = hclgevf_misc_irq_init(hdev); 2370862d969aSHuazhong Tan if (ret) { 2371862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2372862d969aSHuazhong Tan dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2373862d969aSHuazhong Tan ret); 2374862d969aSHuazhong Tan return ret; 2375862d969aSHuazhong Tan } 2376862d969aSHuazhong Tan 2377862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2378862d969aSHuazhong Tan } 2379862d969aSHuazhong Tan 2380862d969aSHuazhong Tan return ret; 2381862d969aSHuazhong Tan } 2382862d969aSHuazhong Tan 23839c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2384e2cb1decSSalil Mehta { 23857a01c897SSalil Mehta struct pci_dev *pdev = hdev->pdev; 2386e2cb1decSSalil Mehta int ret; 2387e2cb1decSSalil Mehta 2388862d969aSHuazhong Tan ret = hclgevf_pci_reset(hdev); 2389862d969aSHuazhong Tan if (ret) { 2390862d969aSHuazhong Tan dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2391862d969aSHuazhong Tan return ret; 2392862d969aSHuazhong Tan } 2393862d969aSHuazhong Tan 23949c6f7085SHuazhong Tan ret = hclgevf_cmd_init(hdev); 23959c6f7085SHuazhong Tan if (ret) { 23969c6f7085SHuazhong Tan dev_err(&pdev->dev, "cmd failed %d\n", ret); 23979c6f7085SHuazhong Tan return ret; 23987a01c897SSalil Mehta } 2399e2cb1decSSalil Mehta 24009c6f7085SHuazhong Tan ret = hclgevf_rss_init_hw(hdev); 24019c6f7085SHuazhong Tan if (ret) { 24029c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 24039c6f7085SHuazhong Tan "failed(%d) to initialize RSS\n", ret); 24049c6f7085SHuazhong Tan return ret; 24059c6f7085SHuazhong Tan } 24069c6f7085SHuazhong Tan 2407b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2408b26a6feaSPeng Li if (ret) 2409b26a6feaSPeng Li return ret; 2410b26a6feaSPeng Li 24119c6f7085SHuazhong Tan ret = hclgevf_init_vlan_config(hdev); 24129c6f7085SHuazhong Tan if (ret) { 24139c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 24149c6f7085SHuazhong Tan "failed(%d) to initialize VLAN config\n", ret); 24159c6f7085SHuazhong Tan return ret; 24169c6f7085SHuazhong Tan } 24179c6f7085SHuazhong Tan 24189c6f7085SHuazhong Tan dev_info(&hdev->pdev->dev, "Reset done\n"); 24199c6f7085SHuazhong Tan 24209c6f7085SHuazhong Tan return 0; 24219c6f7085SHuazhong Tan } 24229c6f7085SHuazhong Tan 24239c6f7085SHuazhong Tan static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 24249c6f7085SHuazhong Tan { 24259c6f7085SHuazhong Tan struct pci_dev *pdev = hdev->pdev; 24269c6f7085SHuazhong Tan int ret; 24279c6f7085SHuazhong Tan 2428e2cb1decSSalil Mehta ret = hclgevf_pci_init(hdev); 2429e2cb1decSSalil Mehta if (ret) { 2430e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI initialization failed\n"); 2431e2cb1decSSalil Mehta return ret; 2432e2cb1decSSalil Mehta } 2433e2cb1decSSalil Mehta 24348b0195a3SHuazhong Tan ret = hclgevf_cmd_queue_init(hdev); 24358b0195a3SHuazhong Tan if (ret) { 24368b0195a3SHuazhong Tan dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret); 24378b0195a3SHuazhong Tan goto err_cmd_queue_init; 24388b0195a3SHuazhong Tan } 24398b0195a3SHuazhong Tan 2440eddf0462SYunsheng Lin ret = hclgevf_cmd_init(hdev); 2441eddf0462SYunsheng Lin if (ret) 2442eddf0462SYunsheng Lin goto err_cmd_init; 2443eddf0462SYunsheng Lin 244407acf909SJian Shen /* Get vf resource */ 244507acf909SJian Shen ret = hclgevf_query_vf_resource(hdev); 244607acf909SJian Shen if (ret) { 244707acf909SJian Shen dev_err(&hdev->pdev->dev, 244807acf909SJian Shen "Query vf status error, ret = %d.\n", ret); 24498b0195a3SHuazhong Tan goto err_cmd_init; 245007acf909SJian Shen } 245107acf909SJian Shen 245207acf909SJian Shen ret = hclgevf_init_msi(hdev); 245307acf909SJian Shen if (ret) { 245407acf909SJian Shen dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 24558b0195a3SHuazhong Tan goto err_cmd_init; 245607acf909SJian Shen } 245707acf909SJian Shen 245807acf909SJian Shen hclgevf_state_init(hdev); 2459dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 246007acf909SJian Shen 2461e2cb1decSSalil Mehta ret = hclgevf_misc_irq_init(hdev); 2462e2cb1decSSalil Mehta if (ret) { 2463e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2464e2cb1decSSalil Mehta ret); 2465e2cb1decSSalil Mehta goto err_misc_irq_init; 2466e2cb1decSSalil Mehta } 2467e2cb1decSSalil Mehta 2468862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2469862d969aSHuazhong Tan 2470e2cb1decSSalil Mehta ret = hclgevf_configure(hdev); 2471e2cb1decSSalil Mehta if (ret) { 2472e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2473e2cb1decSSalil Mehta goto err_config; 2474e2cb1decSSalil Mehta } 2475e2cb1decSSalil Mehta 2476e2cb1decSSalil Mehta ret = hclgevf_alloc_tqps(hdev); 2477e2cb1decSSalil Mehta if (ret) { 2478e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2479e2cb1decSSalil Mehta goto err_config; 2480e2cb1decSSalil Mehta } 2481e2cb1decSSalil Mehta 2482e2cb1decSSalil Mehta ret = hclgevf_set_handle_info(hdev); 2483e2cb1decSSalil Mehta if (ret) { 2484e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 2485e2cb1decSSalil Mehta goto err_config; 2486e2cb1decSSalil Mehta } 2487e2cb1decSSalil Mehta 2488b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2489b26a6feaSPeng Li if (ret) 2490b26a6feaSPeng Li goto err_config; 2491b26a6feaSPeng Li 2492f01f5559SJian Shen /* vf is not allowed to enable unicast/multicast promisc mode. 2493f01f5559SJian Shen * For revision 0x20, default to disable broadcast promisc mode, 2494f01f5559SJian Shen * firmware makes sure broadcast packets can be accepted. 2495f01f5559SJian Shen * For revision 0x21, default to enable broadcast promisc mode. 2496f01f5559SJian Shen */ 2497f01f5559SJian Shen ret = hclgevf_set_promisc_mode(hdev, true); 2498f01f5559SJian Shen if (ret) 2499f01f5559SJian Shen goto err_config; 2500f01f5559SJian Shen 2501e2cb1decSSalil Mehta /* Initialize RSS for this VF */ 2502e2cb1decSSalil Mehta ret = hclgevf_rss_init_hw(hdev); 2503e2cb1decSSalil Mehta if (ret) { 2504e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2505e2cb1decSSalil Mehta "failed(%d) to initialize RSS\n", ret); 2506e2cb1decSSalil Mehta goto err_config; 2507e2cb1decSSalil Mehta } 2508e2cb1decSSalil Mehta 2509e2cb1decSSalil Mehta ret = hclgevf_init_vlan_config(hdev); 2510e2cb1decSSalil Mehta if (ret) { 2511e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2512e2cb1decSSalil Mehta "failed(%d) to initialize VLAN config\n", ret); 2513e2cb1decSSalil Mehta goto err_config; 2514e2cb1decSSalil Mehta } 2515e2cb1decSSalil Mehta 25160742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 2517e2cb1decSSalil Mehta pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME); 2518e2cb1decSSalil Mehta 2519e2cb1decSSalil Mehta return 0; 2520e2cb1decSSalil Mehta 2521e2cb1decSSalil Mehta err_config: 2522e2cb1decSSalil Mehta hclgevf_misc_irq_uninit(hdev); 2523e2cb1decSSalil Mehta err_misc_irq_init: 2524e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2525e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 252607acf909SJian Shen err_cmd_init: 25278b0195a3SHuazhong Tan hclgevf_cmd_uninit(hdev); 25288b0195a3SHuazhong Tan err_cmd_queue_init: 2529e2cb1decSSalil Mehta hclgevf_pci_uninit(hdev); 2530862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2531e2cb1decSSalil Mehta return ret; 2532e2cb1decSSalil Mehta } 2533e2cb1decSSalil Mehta 25347a01c897SSalil Mehta static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2535e2cb1decSSalil Mehta { 2536e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2537862d969aSHuazhong Tan 2538862d969aSHuazhong Tan if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2539eddf0462SYunsheng Lin hclgevf_misc_irq_uninit(hdev); 2540e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 25417a01c897SSalil Mehta } 25427a01c897SSalil Mehta 2543e3338205SHuazhong Tan hclgevf_pci_uninit(hdev); 2544862d969aSHuazhong Tan hclgevf_cmd_uninit(hdev); 2545862d969aSHuazhong Tan } 2546862d969aSHuazhong Tan 25477a01c897SSalil Mehta static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 25487a01c897SSalil Mehta { 25497a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 2550a6d818e3SYunsheng Lin struct hclgevf_dev *hdev; 25517a01c897SSalil Mehta int ret; 25527a01c897SSalil Mehta 25537a01c897SSalil Mehta ret = hclgevf_alloc_hdev(ae_dev); 25547a01c897SSalil Mehta if (ret) { 25557a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device allocation failed\n"); 25567a01c897SSalil Mehta return ret; 25577a01c897SSalil Mehta } 25587a01c897SSalil Mehta 25597a01c897SSalil Mehta ret = hclgevf_init_hdev(ae_dev->priv); 2560a6d818e3SYunsheng Lin if (ret) { 25617a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device initialization failed\n"); 25627a01c897SSalil Mehta return ret; 25637a01c897SSalil Mehta } 25647a01c897SSalil Mehta 2565a6d818e3SYunsheng Lin hdev = ae_dev->priv; 2566a6d818e3SYunsheng Lin timer_setup(&hdev->keep_alive_timer, hclgevf_keep_alive_timer, 0); 2567a6d818e3SYunsheng Lin INIT_WORK(&hdev->keep_alive_task, hclgevf_keep_alive_task); 2568a6d818e3SYunsheng Lin 2569a6d818e3SYunsheng Lin return 0; 2570a6d818e3SYunsheng Lin } 2571a6d818e3SYunsheng Lin 25727a01c897SSalil Mehta static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 25737a01c897SSalil Mehta { 25747a01c897SSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 25757a01c897SSalil Mehta 25767a01c897SSalil Mehta hclgevf_uninit_hdev(hdev); 2577e2cb1decSSalil Mehta ae_dev->priv = NULL; 2578e2cb1decSSalil Mehta } 2579e2cb1decSSalil Mehta 2580849e4607SPeng Li static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2581849e4607SPeng Li { 2582849e4607SPeng Li struct hnae3_handle *nic = &hdev->nic; 2583849e4607SPeng Li struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2584849e4607SPeng Li 25858be73621SHuazhong Tan return min_t(u32, hdev->rss_size_max, 25868be73621SHuazhong Tan hdev->num_tqps / kinfo->num_tc); 2587849e4607SPeng Li } 2588849e4607SPeng Li 2589849e4607SPeng Li /** 2590849e4607SPeng Li * hclgevf_get_channels - Get the current channels enabled and max supported. 2591849e4607SPeng Li * @handle: hardware information for network interface 2592849e4607SPeng Li * @ch: ethtool channels structure 2593849e4607SPeng Li * 2594849e4607SPeng Li * We don't support separate tx and rx queues as channels. The other count 2595849e4607SPeng Li * represents how many queues are being used for control. max_combined counts 2596849e4607SPeng Li * how many queue pairs we can support. They may not be mapped 1 to 1 with 2597849e4607SPeng Li * q_vectors since we support a lot more queue pairs than q_vectors. 2598849e4607SPeng Li **/ 2599849e4607SPeng Li static void hclgevf_get_channels(struct hnae3_handle *handle, 2600849e4607SPeng Li struct ethtool_channels *ch) 2601849e4607SPeng Li { 2602849e4607SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2603849e4607SPeng Li 2604849e4607SPeng Li ch->max_combined = hclgevf_get_max_channels(hdev); 2605849e4607SPeng Li ch->other_count = 0; 2606849e4607SPeng Li ch->max_other = 0; 26078be73621SHuazhong Tan ch->combined_count = handle->kinfo.rss_size; 2608849e4607SPeng Li } 2609849e4607SPeng Li 2610cc719218SPeng Li static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 26110d43bf45SHuazhong Tan u16 *alloc_tqps, u16 *max_rss_size) 2612cc719218SPeng Li { 2613cc719218SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2614cc719218SPeng Li 26150d43bf45SHuazhong Tan *alloc_tqps = hdev->num_tqps; 2616cc719218SPeng Li *max_rss_size = hdev->rss_size_max; 2617cc719218SPeng Li } 2618cc719218SPeng Li 2619175ec96bSFuyun Liang static int hclgevf_get_status(struct hnae3_handle *handle) 2620175ec96bSFuyun Liang { 2621175ec96bSFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2622175ec96bSFuyun Liang 2623175ec96bSFuyun Liang return hdev->hw.mac.link; 2624175ec96bSFuyun Liang } 2625175ec96bSFuyun Liang 26264a152de9SFuyun Liang static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 26274a152de9SFuyun Liang u8 *auto_neg, u32 *speed, 26284a152de9SFuyun Liang u8 *duplex) 26294a152de9SFuyun Liang { 26304a152de9SFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 26314a152de9SFuyun Liang 26324a152de9SFuyun Liang if (speed) 26334a152de9SFuyun Liang *speed = hdev->hw.mac.speed; 26344a152de9SFuyun Liang if (duplex) 26354a152de9SFuyun Liang *duplex = hdev->hw.mac.duplex; 26364a152de9SFuyun Liang if (auto_neg) 26374a152de9SFuyun Liang *auto_neg = AUTONEG_DISABLE; 26384a152de9SFuyun Liang } 26394a152de9SFuyun Liang 26404a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 26414a152de9SFuyun Liang u8 duplex) 26424a152de9SFuyun Liang { 26434a152de9SFuyun Liang hdev->hw.mac.speed = speed; 26444a152de9SFuyun Liang hdev->hw.mac.duplex = duplex; 26454a152de9SFuyun Liang } 26464a152de9SFuyun Liang 26471731be4cSYonglong Liu static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 26485c9f6b39SPeng Li { 26495c9f6b39SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 26505c9f6b39SPeng Li 26515c9f6b39SPeng Li return hclgevf_config_gro(hdev, enable); 26525c9f6b39SPeng Li } 26535c9f6b39SPeng Li 2654c136b884SPeng Li static void hclgevf_get_media_type(struct hnae3_handle *handle, 2655c136b884SPeng Li u8 *media_type) 2656c136b884SPeng Li { 2657c136b884SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2658c136b884SPeng Li if (media_type) 2659c136b884SPeng Li *media_type = hdev->hw.mac.media_type; 2660c136b884SPeng Li } 2661c136b884SPeng Li 26624d60291bSHuazhong Tan static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 26634d60291bSHuazhong Tan { 26644d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 26654d60291bSHuazhong Tan 2666aa5c4f17SHuazhong Tan return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 26674d60291bSHuazhong Tan } 26684d60291bSHuazhong Tan 26694d60291bSHuazhong Tan static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 26704d60291bSHuazhong Tan { 26714d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 26724d60291bSHuazhong Tan 26734d60291bSHuazhong Tan return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 26744d60291bSHuazhong Tan } 26754d60291bSHuazhong Tan 26764d60291bSHuazhong Tan static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 26774d60291bSHuazhong Tan { 26784d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 26794d60291bSHuazhong Tan 26804d60291bSHuazhong Tan return hdev->reset_count; 26814d60291bSHuazhong Tan } 26824d60291bSHuazhong Tan 26839194d18bSliuzhongzhu static void hclgevf_get_link_mode(struct hnae3_handle *handle, 26849194d18bSliuzhongzhu unsigned long *supported, 26859194d18bSliuzhongzhu unsigned long *advertising) 26869194d18bSliuzhongzhu { 26879194d18bSliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 26889194d18bSliuzhongzhu 26899194d18bSliuzhongzhu *supported = hdev->hw.mac.supported; 26909194d18bSliuzhongzhu *advertising = hdev->hw.mac.advertising; 26919194d18bSliuzhongzhu } 26929194d18bSliuzhongzhu 26931600c3e5SJian Shen #define MAX_SEPARATE_NUM 4 26941600c3e5SJian Shen #define SEPARATOR_VALUE 0xFFFFFFFF 26951600c3e5SJian Shen #define REG_NUM_PER_LINE 4 26961600c3e5SJian Shen #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 26971600c3e5SJian Shen 26981600c3e5SJian Shen static int hclgevf_get_regs_len(struct hnae3_handle *handle) 26991600c3e5SJian Shen { 27001600c3e5SJian Shen int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 27011600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27021600c3e5SJian Shen 27031600c3e5SJian Shen cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 27041600c3e5SJian Shen common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 27051600c3e5SJian Shen ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 27061600c3e5SJian Shen tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 27071600c3e5SJian Shen 27081600c3e5SJian Shen return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 27091600c3e5SJian Shen tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 27101600c3e5SJian Shen } 27111600c3e5SJian Shen 27121600c3e5SJian Shen static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 27131600c3e5SJian Shen void *data) 27141600c3e5SJian Shen { 27151600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27161600c3e5SJian Shen int i, j, reg_um, separator_num; 27171600c3e5SJian Shen u32 *reg = data; 27181600c3e5SJian Shen 27191600c3e5SJian Shen *version = hdev->fw_version; 27201600c3e5SJian Shen 27211600c3e5SJian Shen /* fetching per-VF registers values from VF PCIe register space */ 27221600c3e5SJian Shen reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 27231600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 27241600c3e5SJian Shen for (i = 0; i < reg_um; i++) 27251600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 27261600c3e5SJian Shen for (i = 0; i < separator_num; i++) 27271600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 27281600c3e5SJian Shen 27291600c3e5SJian Shen reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 27301600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 27311600c3e5SJian Shen for (i = 0; i < reg_um; i++) 27321600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 27331600c3e5SJian Shen for (i = 0; i < separator_num; i++) 27341600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 27351600c3e5SJian Shen 27361600c3e5SJian Shen reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 27371600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 27381600c3e5SJian Shen for (j = 0; j < hdev->num_tqps; j++) { 27391600c3e5SJian Shen for (i = 0; i < reg_um; i++) 27401600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 27411600c3e5SJian Shen ring_reg_addr_list[i] + 27421600c3e5SJian Shen 0x200 * j); 27431600c3e5SJian Shen for (i = 0; i < separator_num; i++) 27441600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 27451600c3e5SJian Shen } 27461600c3e5SJian Shen 27471600c3e5SJian Shen reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 27481600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 27491600c3e5SJian Shen for (j = 0; j < hdev->num_msi_used - 1; j++) { 27501600c3e5SJian Shen for (i = 0; i < reg_um; i++) 27511600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 27521600c3e5SJian Shen tqp_intr_reg_addr_list[i] + 27531600c3e5SJian Shen 4 * j); 27541600c3e5SJian Shen for (i = 0; i < separator_num; i++) 27551600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 27561600c3e5SJian Shen } 27571600c3e5SJian Shen } 27581600c3e5SJian Shen 2759e2cb1decSSalil Mehta static const struct hnae3_ae_ops hclgevf_ops = { 2760e2cb1decSSalil Mehta .init_ae_dev = hclgevf_init_ae_dev, 2761e2cb1decSSalil Mehta .uninit_ae_dev = hclgevf_uninit_ae_dev, 27626ff3cf07SHuazhong Tan .flr_prepare = hclgevf_flr_prepare, 27636ff3cf07SHuazhong Tan .flr_done = hclgevf_flr_done, 2764e718a93fSPeng Li .init_client_instance = hclgevf_init_client_instance, 2765e718a93fSPeng Li .uninit_client_instance = hclgevf_uninit_client_instance, 2766e2cb1decSSalil Mehta .start = hclgevf_ae_start, 2767e2cb1decSSalil Mehta .stop = hclgevf_ae_stop, 2768a6d818e3SYunsheng Lin .client_start = hclgevf_client_start, 2769a6d818e3SYunsheng Lin .client_stop = hclgevf_client_stop, 2770e2cb1decSSalil Mehta .map_ring_to_vector = hclgevf_map_ring_to_vector, 2771e2cb1decSSalil Mehta .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 2772e2cb1decSSalil Mehta .get_vector = hclgevf_get_vector, 27730d3e6631SYunsheng Lin .put_vector = hclgevf_put_vector, 2774e2cb1decSSalil Mehta .reset_queue = hclgevf_reset_tqp, 2775e2cb1decSSalil Mehta .get_mac_addr = hclgevf_get_mac_addr, 2776e2cb1decSSalil Mehta .set_mac_addr = hclgevf_set_mac_addr, 2777e2cb1decSSalil Mehta .add_uc_addr = hclgevf_add_uc_addr, 2778e2cb1decSSalil Mehta .rm_uc_addr = hclgevf_rm_uc_addr, 2779e2cb1decSSalil Mehta .add_mc_addr = hclgevf_add_mc_addr, 2780e2cb1decSSalil Mehta .rm_mc_addr = hclgevf_rm_mc_addr, 2781e2cb1decSSalil Mehta .get_stats = hclgevf_get_stats, 2782e2cb1decSSalil Mehta .update_stats = hclgevf_update_stats, 2783e2cb1decSSalil Mehta .get_strings = hclgevf_get_strings, 2784e2cb1decSSalil Mehta .get_sset_count = hclgevf_get_sset_count, 2785e2cb1decSSalil Mehta .get_rss_key_size = hclgevf_get_rss_key_size, 2786e2cb1decSSalil Mehta .get_rss_indir_size = hclgevf_get_rss_indir_size, 2787e2cb1decSSalil Mehta .get_rss = hclgevf_get_rss, 2788e2cb1decSSalil Mehta .set_rss = hclgevf_set_rss, 2789d97b3072SJian Shen .get_rss_tuple = hclgevf_get_rss_tuple, 2790d97b3072SJian Shen .set_rss_tuple = hclgevf_set_rss_tuple, 2791e2cb1decSSalil Mehta .get_tc_size = hclgevf_get_tc_size, 2792e2cb1decSSalil Mehta .get_fw_version = hclgevf_get_fw_version, 2793e2cb1decSSalil Mehta .set_vlan_filter = hclgevf_set_vlan_filter, 2794b2641e2aSYunsheng Lin .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 27956d4c3981SSalil Mehta .reset_event = hclgevf_reset_event, 2796720bd583SHuazhong Tan .set_default_reset_request = hclgevf_set_def_reset_request, 2797849e4607SPeng Li .get_channels = hclgevf_get_channels, 2798cc719218SPeng Li .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 27991600c3e5SJian Shen .get_regs_len = hclgevf_get_regs_len, 28001600c3e5SJian Shen .get_regs = hclgevf_get_regs, 2801175ec96bSFuyun Liang .get_status = hclgevf_get_status, 28024a152de9SFuyun Liang .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 2803c136b884SPeng Li .get_media_type = hclgevf_get_media_type, 28044d60291bSHuazhong Tan .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 28054d60291bSHuazhong Tan .ae_dev_resetting = hclgevf_ae_dev_resetting, 28064d60291bSHuazhong Tan .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 28075c9f6b39SPeng Li .set_gro_en = hclgevf_gro_en, 2808818f1675SYunsheng Lin .set_mtu = hclgevf_set_mtu, 28090c29d191Sliuzhongzhu .get_global_queue_id = hclgevf_get_qid_global, 28108cdb992fSJian Shen .set_timer_task = hclgevf_set_timer_task, 28119194d18bSliuzhongzhu .get_link_mode = hclgevf_get_link_mode, 2812e2cb1decSSalil Mehta }; 2813e2cb1decSSalil Mehta 2814e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf = { 2815e2cb1decSSalil Mehta .ops = &hclgevf_ops, 2816e2cb1decSSalil Mehta .pdev_id_table = ae_algovf_pci_tbl, 2817e2cb1decSSalil Mehta }; 2818e2cb1decSSalil Mehta 2819e2cb1decSSalil Mehta static int hclgevf_init(void) 2820e2cb1decSSalil Mehta { 2821e2cb1decSSalil Mehta pr_info("%s is initializing\n", HCLGEVF_NAME); 2822e2cb1decSSalil Mehta 2823854cf33aSFuyun Liang hnae3_register_ae_algo(&ae_algovf); 2824854cf33aSFuyun Liang 2825854cf33aSFuyun Liang return 0; 2826e2cb1decSSalil Mehta } 2827e2cb1decSSalil Mehta 2828e2cb1decSSalil Mehta static void hclgevf_exit(void) 2829e2cb1decSSalil Mehta { 2830e2cb1decSSalil Mehta hnae3_unregister_ae_algo(&ae_algovf); 2831e2cb1decSSalil Mehta } 2832e2cb1decSSalil Mehta module_init(hclgevf_init); 2833e2cb1decSSalil Mehta module_exit(hclgevf_exit); 2834e2cb1decSSalil Mehta 2835e2cb1decSSalil Mehta MODULE_LICENSE("GPL"); 2836e2cb1decSSalil Mehta MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 2837e2cb1decSSalil Mehta MODULE_DESCRIPTION("HCLGEVF Driver"); 2838e2cb1decSSalil Mehta MODULE_VERSION(HCLGEVF_MOD_VERSION); 2839