1e2cb1decSSalil Mehta // SPDX-License-Identifier: GPL-2.0+ 2e2cb1decSSalil Mehta // Copyright (c) 2016-2017 Hisilicon Limited. 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #include <linux/etherdevice.h> 5aa5c4f17SHuazhong Tan #include <linux/iopoll.h> 66988eb2aSSalil Mehta #include <net/rtnetlink.h> 7e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 8e2cb1decSSalil Mehta #include "hclgevf_main.h" 9e2cb1decSSalil Mehta #include "hclge_mbx.h" 10e2cb1decSSalil Mehta #include "hnae3.h" 11e2cb1decSSalil Mehta 12e2cb1decSSalil Mehta #define HCLGEVF_NAME "hclgevf" 13e2cb1decSSalil Mehta 149c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 15e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf; 16e2cb1decSSalil Mehta 17e2cb1decSSalil Mehta static const struct pci_device_id ae_algovf_pci_tbl[] = { 18e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 19e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 20e2cb1decSSalil Mehta /* required last entry */ 21e2cb1decSSalil Mehta {0, } 22e2cb1decSSalil Mehta }; 23e2cb1decSSalil Mehta 24472d7eceSJian Shen static const u8 hclgevf_hash_key[] = { 25472d7eceSJian Shen 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 26472d7eceSJian Shen 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 27472d7eceSJian Shen 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 28472d7eceSJian Shen 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 29472d7eceSJian Shen 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 30472d7eceSJian Shen }; 31472d7eceSJian Shen 322f550a46SYunsheng Lin MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 332f550a46SYunsheng Lin 341600c3e5SJian Shen static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 351600c3e5SJian Shen HCLGEVF_CMDQ_TX_ADDR_H_REG, 361600c3e5SJian Shen HCLGEVF_CMDQ_TX_DEPTH_REG, 371600c3e5SJian Shen HCLGEVF_CMDQ_TX_TAIL_REG, 381600c3e5SJian Shen HCLGEVF_CMDQ_TX_HEAD_REG, 391600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_L_REG, 401600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_H_REG, 411600c3e5SJian Shen HCLGEVF_CMDQ_RX_DEPTH_REG, 421600c3e5SJian Shen HCLGEVF_CMDQ_RX_TAIL_REG, 431600c3e5SJian Shen HCLGEVF_CMDQ_RX_HEAD_REG, 441600c3e5SJian Shen HCLGEVF_VECTOR0_CMDQ_SRC_REG, 451600c3e5SJian Shen HCLGEVF_CMDQ_INTR_STS_REG, 461600c3e5SJian Shen HCLGEVF_CMDQ_INTR_EN_REG, 471600c3e5SJian Shen HCLGEVF_CMDQ_INTR_GEN_REG}; 481600c3e5SJian Shen 491600c3e5SJian Shen static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 501600c3e5SJian Shen HCLGEVF_RST_ING, 511600c3e5SJian Shen HCLGEVF_GRO_EN_REG}; 521600c3e5SJian Shen 531600c3e5SJian Shen static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 541600c3e5SJian Shen HCLGEVF_RING_RX_ADDR_H_REG, 551600c3e5SJian Shen HCLGEVF_RING_RX_BD_NUM_REG, 561600c3e5SJian Shen HCLGEVF_RING_RX_BD_LENGTH_REG, 571600c3e5SJian Shen HCLGEVF_RING_RX_MERGE_EN_REG, 581600c3e5SJian Shen HCLGEVF_RING_RX_TAIL_REG, 591600c3e5SJian Shen HCLGEVF_RING_RX_HEAD_REG, 601600c3e5SJian Shen HCLGEVF_RING_RX_FBD_NUM_REG, 611600c3e5SJian Shen HCLGEVF_RING_RX_OFFSET_REG, 621600c3e5SJian Shen HCLGEVF_RING_RX_FBD_OFFSET_REG, 631600c3e5SJian Shen HCLGEVF_RING_RX_STASH_REG, 641600c3e5SJian Shen HCLGEVF_RING_RX_BD_ERR_REG, 651600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_L_REG, 661600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_H_REG, 671600c3e5SJian Shen HCLGEVF_RING_TX_BD_NUM_REG, 681600c3e5SJian Shen HCLGEVF_RING_TX_PRIORITY_REG, 691600c3e5SJian Shen HCLGEVF_RING_TX_TC_REG, 701600c3e5SJian Shen HCLGEVF_RING_TX_MERGE_EN_REG, 711600c3e5SJian Shen HCLGEVF_RING_TX_TAIL_REG, 721600c3e5SJian Shen HCLGEVF_RING_TX_HEAD_REG, 731600c3e5SJian Shen HCLGEVF_RING_TX_FBD_NUM_REG, 741600c3e5SJian Shen HCLGEVF_RING_TX_OFFSET_REG, 751600c3e5SJian Shen HCLGEVF_RING_TX_EBD_NUM_REG, 761600c3e5SJian Shen HCLGEVF_RING_TX_EBD_OFFSET_REG, 771600c3e5SJian Shen HCLGEVF_RING_TX_BD_ERR_REG, 781600c3e5SJian Shen HCLGEVF_RING_EN_REG}; 791600c3e5SJian Shen 801600c3e5SJian Shen static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 811600c3e5SJian Shen HCLGEVF_TQP_INTR_GL0_REG, 821600c3e5SJian Shen HCLGEVF_TQP_INTR_GL1_REG, 831600c3e5SJian Shen HCLGEVF_TQP_INTR_GL2_REG, 841600c3e5SJian Shen HCLGEVF_TQP_INTR_RL_REG}; 851600c3e5SJian Shen 86e2cb1decSSalil Mehta static inline struct hclgevf_dev *hclgevf_ae_get_hdev( 87e2cb1decSSalil Mehta struct hnae3_handle *handle) 88e2cb1decSSalil Mehta { 89eed9535fSPeng Li if (!handle->client) 90eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, nic); 91eed9535fSPeng Li else if (handle->client->type == HNAE3_CLIENT_ROCE) 92eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, roce); 93eed9535fSPeng Li else 94e2cb1decSSalil Mehta return container_of(handle, struct hclgevf_dev, nic); 95e2cb1decSSalil Mehta } 96e2cb1decSSalil Mehta 97e2cb1decSSalil Mehta static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 98e2cb1decSSalil Mehta { 99b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 100e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 101e2cb1decSSalil Mehta struct hclgevf_desc desc; 102e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 103e2cb1decSSalil Mehta int status; 104e2cb1decSSalil Mehta int i; 105e2cb1decSSalil Mehta 106b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 107b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 108e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 109e2cb1decSSalil Mehta HCLGEVF_OPC_QUERY_RX_STATUS, 110e2cb1decSSalil Mehta true); 111e2cb1decSSalil Mehta 112e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 113e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 114e2cb1decSSalil Mehta if (status) { 115e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 116e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 117e2cb1decSSalil Mehta status, i); 118e2cb1decSSalil Mehta return status; 119e2cb1decSSalil Mehta } 120e2cb1decSSalil Mehta tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 121cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 122e2cb1decSSalil Mehta 123e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 124e2cb1decSSalil Mehta true); 125e2cb1decSSalil Mehta 126e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 127e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 128e2cb1decSSalil Mehta if (status) { 129e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 130e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 131e2cb1decSSalil Mehta status, i); 132e2cb1decSSalil Mehta return status; 133e2cb1decSSalil Mehta } 134e2cb1decSSalil Mehta tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 135cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 136e2cb1decSSalil Mehta } 137e2cb1decSSalil Mehta 138e2cb1decSSalil Mehta return 0; 139e2cb1decSSalil Mehta } 140e2cb1decSSalil Mehta 141e2cb1decSSalil Mehta static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 142e2cb1decSSalil Mehta { 143e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo = &handle->kinfo; 144e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 145e2cb1decSSalil Mehta u64 *buff = data; 146e2cb1decSSalil Mehta int i; 147e2cb1decSSalil Mehta 148b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 149b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 150e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 151e2cb1decSSalil Mehta } 152e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 153b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 154e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 155e2cb1decSSalil Mehta } 156e2cb1decSSalil Mehta 157e2cb1decSSalil Mehta return buff; 158e2cb1decSSalil Mehta } 159e2cb1decSSalil Mehta 160e2cb1decSSalil Mehta static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 161e2cb1decSSalil Mehta { 162b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 163e2cb1decSSalil Mehta 164b4f1d303SJian Shen return kinfo->num_tqps * 2; 165e2cb1decSSalil Mehta } 166e2cb1decSSalil Mehta 167e2cb1decSSalil Mehta static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 168e2cb1decSSalil Mehta { 169b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 170e2cb1decSSalil Mehta u8 *buff = data; 171e2cb1decSSalil Mehta int i = 0; 172e2cb1decSSalil Mehta 173b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 174b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 175e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1760c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 177e2cb1decSSalil Mehta tqp->index); 178e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 179e2cb1decSSalil Mehta } 180e2cb1decSSalil Mehta 181b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 182b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 183e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1840c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 185e2cb1decSSalil Mehta tqp->index); 186e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 187e2cb1decSSalil Mehta } 188e2cb1decSSalil Mehta 189e2cb1decSSalil Mehta return buff; 190e2cb1decSSalil Mehta } 191e2cb1decSSalil Mehta 192e2cb1decSSalil Mehta static void hclgevf_update_stats(struct hnae3_handle *handle, 193e2cb1decSSalil Mehta struct net_device_stats *net_stats) 194e2cb1decSSalil Mehta { 195e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 196e2cb1decSSalil Mehta int status; 197e2cb1decSSalil Mehta 198e2cb1decSSalil Mehta status = hclgevf_tqps_update_stats(handle); 199e2cb1decSSalil Mehta if (status) 200e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 201e2cb1decSSalil Mehta "VF update of TQPS stats fail, status = %d.\n", 202e2cb1decSSalil Mehta status); 203e2cb1decSSalil Mehta } 204e2cb1decSSalil Mehta 205e2cb1decSSalil Mehta static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 206e2cb1decSSalil Mehta { 207e2cb1decSSalil Mehta if (strset == ETH_SS_TEST) 208e2cb1decSSalil Mehta return -EOPNOTSUPP; 209e2cb1decSSalil Mehta else if (strset == ETH_SS_STATS) 210e2cb1decSSalil Mehta return hclgevf_tqps_get_sset_count(handle, strset); 211e2cb1decSSalil Mehta 212e2cb1decSSalil Mehta return 0; 213e2cb1decSSalil Mehta } 214e2cb1decSSalil Mehta 215e2cb1decSSalil Mehta static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 216e2cb1decSSalil Mehta u8 *data) 217e2cb1decSSalil Mehta { 218e2cb1decSSalil Mehta u8 *p = (char *)data; 219e2cb1decSSalil Mehta 220e2cb1decSSalil Mehta if (strset == ETH_SS_STATS) 221e2cb1decSSalil Mehta p = hclgevf_tqps_get_strings(handle, p); 222e2cb1decSSalil Mehta } 223e2cb1decSSalil Mehta 224e2cb1decSSalil Mehta static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 225e2cb1decSSalil Mehta { 226e2cb1decSSalil Mehta hclgevf_tqps_get_stats(handle, data); 227e2cb1decSSalil Mehta } 228e2cb1decSSalil Mehta 229e2cb1decSSalil Mehta static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 230e2cb1decSSalil Mehta { 231e2cb1decSSalil Mehta u8 resp_msg; 232e2cb1decSSalil Mehta int status; 233e2cb1decSSalil Mehta 234e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 235e2cb1decSSalil Mehta true, &resp_msg, sizeof(u8)); 236e2cb1decSSalil Mehta if (status) { 237e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 238e2cb1decSSalil Mehta "VF request to get TC info from PF failed %d", 239e2cb1decSSalil Mehta status); 240e2cb1decSSalil Mehta return status; 241e2cb1decSSalil Mehta } 242e2cb1decSSalil Mehta 243e2cb1decSSalil Mehta hdev->hw_tc_map = resp_msg; 244e2cb1decSSalil Mehta 245e2cb1decSSalil Mehta return 0; 246e2cb1decSSalil Mehta } 247e2cb1decSSalil Mehta 2486cee6fc3SJian Shen static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 249e2cb1decSSalil Mehta { 250c0425944SPeng Li #define HCLGEVF_TQPS_RSS_INFO_LEN 6 251e2cb1decSSalil Mehta u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 252e2cb1decSSalil Mehta int status; 253e2cb1decSSalil Mehta 254e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 255e2cb1decSSalil Mehta true, resp_msg, 256e2cb1decSSalil Mehta HCLGEVF_TQPS_RSS_INFO_LEN); 257e2cb1decSSalil Mehta if (status) { 258e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 259e2cb1decSSalil Mehta "VF request to get tqp info from PF failed %d", 260e2cb1decSSalil Mehta status); 261e2cb1decSSalil Mehta return status; 262e2cb1decSSalil Mehta } 263e2cb1decSSalil Mehta 264e2cb1decSSalil Mehta memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 265e2cb1decSSalil Mehta memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 266c0425944SPeng Li memcpy(&hdev->rx_buf_len, &resp_msg[4], sizeof(u16)); 267c0425944SPeng Li 268c0425944SPeng Li return 0; 269c0425944SPeng Li } 270c0425944SPeng Li 271c0425944SPeng Li static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 272c0425944SPeng Li { 273c0425944SPeng Li #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 274c0425944SPeng Li u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 275c0425944SPeng Li int ret; 276c0425944SPeng Li 277c0425944SPeng Li ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QDEPTH, 0, NULL, 0, 278c0425944SPeng Li true, resp_msg, 279c0425944SPeng Li HCLGEVF_TQPS_DEPTH_INFO_LEN); 280c0425944SPeng Li if (ret) { 281c0425944SPeng Li dev_err(&hdev->pdev->dev, 282c0425944SPeng Li "VF request to get tqp depth info from PF failed %d", 283c0425944SPeng Li ret); 284c0425944SPeng Li return ret; 285c0425944SPeng Li } 286c0425944SPeng Li 287c0425944SPeng Li memcpy(&hdev->num_tx_desc, &resp_msg[0], sizeof(u16)); 288c0425944SPeng Li memcpy(&hdev->num_rx_desc, &resp_msg[2], sizeof(u16)); 289e2cb1decSSalil Mehta 290e2cb1decSSalil Mehta return 0; 291e2cb1decSSalil Mehta } 292e2cb1decSSalil Mehta 2930c29d191Sliuzhongzhu static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 2940c29d191Sliuzhongzhu { 2950c29d191Sliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2960c29d191Sliuzhongzhu u8 msg_data[2], resp_data[2]; 2970c29d191Sliuzhongzhu u16 qid_in_pf = 0; 2980c29d191Sliuzhongzhu int ret; 2990c29d191Sliuzhongzhu 3000c29d191Sliuzhongzhu memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 3010c29d191Sliuzhongzhu 3020c29d191Sliuzhongzhu ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data, 3030c29d191Sliuzhongzhu 2, true, resp_data, 2); 3040c29d191Sliuzhongzhu if (!ret) 3050c29d191Sliuzhongzhu qid_in_pf = *(u16 *)resp_data; 3060c29d191Sliuzhongzhu 3070c29d191Sliuzhongzhu return qid_in_pf; 3080c29d191Sliuzhongzhu } 3090c29d191Sliuzhongzhu 3109c3e7130Sliuzhongzhu static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 3119c3e7130Sliuzhongzhu { 3129c3e7130Sliuzhongzhu u8 resp_msg; 3139c3e7130Sliuzhongzhu int ret; 3149c3e7130Sliuzhongzhu 3159c3e7130Sliuzhongzhu ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_MEDIA_TYPE, 0, NULL, 0, 3169c3e7130Sliuzhongzhu true, &resp_msg, sizeof(resp_msg)); 3179c3e7130Sliuzhongzhu if (ret) { 3189c3e7130Sliuzhongzhu dev_err(&hdev->pdev->dev, 3199c3e7130Sliuzhongzhu "VF request to get the pf port media type failed %d", 3209c3e7130Sliuzhongzhu ret); 3219c3e7130Sliuzhongzhu return ret; 3229c3e7130Sliuzhongzhu } 3239c3e7130Sliuzhongzhu 3249c3e7130Sliuzhongzhu hdev->hw.mac.media_type = resp_msg; 3259c3e7130Sliuzhongzhu 3269c3e7130Sliuzhongzhu return 0; 3279c3e7130Sliuzhongzhu } 3289c3e7130Sliuzhongzhu 329e2cb1decSSalil Mehta static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 330e2cb1decSSalil Mehta { 331e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 332e2cb1decSSalil Mehta int i; 333e2cb1decSSalil Mehta 334e2cb1decSSalil Mehta hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 335e2cb1decSSalil Mehta sizeof(struct hclgevf_tqp), GFP_KERNEL); 336e2cb1decSSalil Mehta if (!hdev->htqp) 337e2cb1decSSalil Mehta return -ENOMEM; 338e2cb1decSSalil Mehta 339e2cb1decSSalil Mehta tqp = hdev->htqp; 340e2cb1decSSalil Mehta 341e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 342e2cb1decSSalil Mehta tqp->dev = &hdev->pdev->dev; 343e2cb1decSSalil Mehta tqp->index = i; 344e2cb1decSSalil Mehta 345e2cb1decSSalil Mehta tqp->q.ae_algo = &ae_algovf; 346e2cb1decSSalil Mehta tqp->q.buf_size = hdev->rx_buf_len; 347c0425944SPeng Li tqp->q.tx_desc_num = hdev->num_tx_desc; 348c0425944SPeng Li tqp->q.rx_desc_num = hdev->num_rx_desc; 349e2cb1decSSalil Mehta tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 350e2cb1decSSalil Mehta i * HCLGEVF_TQP_REG_SIZE; 351e2cb1decSSalil Mehta 352e2cb1decSSalil Mehta tqp++; 353e2cb1decSSalil Mehta } 354e2cb1decSSalil Mehta 355e2cb1decSSalil Mehta return 0; 356e2cb1decSSalil Mehta } 357e2cb1decSSalil Mehta 358e2cb1decSSalil Mehta static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 359e2cb1decSSalil Mehta { 360e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 361e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo; 362e2cb1decSSalil Mehta u16 new_tqps = hdev->num_tqps; 363e2cb1decSSalil Mehta int i; 364e2cb1decSSalil Mehta 365e2cb1decSSalil Mehta kinfo = &nic->kinfo; 366e2cb1decSSalil Mehta kinfo->num_tc = 0; 367c0425944SPeng Li kinfo->num_tx_desc = hdev->num_tx_desc; 368c0425944SPeng Li kinfo->num_rx_desc = hdev->num_rx_desc; 369e2cb1decSSalil Mehta kinfo->rx_buf_len = hdev->rx_buf_len; 370e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 371e2cb1decSSalil Mehta if (hdev->hw_tc_map & BIT(i)) 372e2cb1decSSalil Mehta kinfo->num_tc++; 373e2cb1decSSalil Mehta 374e2cb1decSSalil Mehta kinfo->rss_size 375e2cb1decSSalil Mehta = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 376e2cb1decSSalil Mehta new_tqps = kinfo->rss_size * kinfo->num_tc; 377e2cb1decSSalil Mehta kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 378e2cb1decSSalil Mehta 379e2cb1decSSalil Mehta kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 380e2cb1decSSalil Mehta sizeof(struct hnae3_queue *), GFP_KERNEL); 381e2cb1decSSalil Mehta if (!kinfo->tqp) 382e2cb1decSSalil Mehta return -ENOMEM; 383e2cb1decSSalil Mehta 384e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 385e2cb1decSSalil Mehta hdev->htqp[i].q.handle = &hdev->nic; 386e2cb1decSSalil Mehta hdev->htqp[i].q.tqp_index = i; 387e2cb1decSSalil Mehta kinfo->tqp[i] = &hdev->htqp[i].q; 388e2cb1decSSalil Mehta } 389e2cb1decSSalil Mehta 390e2cb1decSSalil Mehta return 0; 391e2cb1decSSalil Mehta } 392e2cb1decSSalil Mehta 393e2cb1decSSalil Mehta static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 394e2cb1decSSalil Mehta { 395e2cb1decSSalil Mehta int status; 396e2cb1decSSalil Mehta u8 resp_msg; 397e2cb1decSSalil Mehta 398e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 399e2cb1decSSalil Mehta 0, false, &resp_msg, sizeof(u8)); 400e2cb1decSSalil Mehta if (status) 401e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 402e2cb1decSSalil Mehta "VF failed to fetch link status(%d) from PF", status); 403e2cb1decSSalil Mehta } 404e2cb1decSSalil Mehta 405e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 406e2cb1decSSalil Mehta { 40745e92b7eSPeng Li struct hnae3_handle *rhandle = &hdev->roce; 408e2cb1decSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 40945e92b7eSPeng Li struct hnae3_client *rclient; 410e2cb1decSSalil Mehta struct hnae3_client *client; 411e2cb1decSSalil Mehta 412e2cb1decSSalil Mehta client = handle->client; 41345e92b7eSPeng Li rclient = hdev->roce_client; 414e2cb1decSSalil Mehta 415582d37bbSPeng Li link_state = 416582d37bbSPeng Li test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 417582d37bbSPeng Li 418e2cb1decSSalil Mehta if (link_state != hdev->hw.mac.link) { 419e2cb1decSSalil Mehta client->ops->link_status_change(handle, !!link_state); 42045e92b7eSPeng Li if (rclient && rclient->ops->link_status_change) 42145e92b7eSPeng Li rclient->ops->link_status_change(rhandle, !!link_state); 422e2cb1decSSalil Mehta hdev->hw.mac.link = link_state; 423e2cb1decSSalil Mehta } 424e2cb1decSSalil Mehta } 425e2cb1decSSalil Mehta 426538abaf3SYueHaibing static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 4279194d18bSliuzhongzhu { 4289194d18bSliuzhongzhu #define HCLGEVF_ADVERTISING 0 4299194d18bSliuzhongzhu #define HCLGEVF_SUPPORTED 1 4309194d18bSliuzhongzhu u8 send_msg; 4319194d18bSliuzhongzhu u8 resp_msg; 4329194d18bSliuzhongzhu 4339194d18bSliuzhongzhu send_msg = HCLGEVF_ADVERTISING; 4349194d18bSliuzhongzhu hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, &send_msg, 4359194d18bSliuzhongzhu sizeof(u8), false, &resp_msg, sizeof(u8)); 4369194d18bSliuzhongzhu send_msg = HCLGEVF_SUPPORTED; 4379194d18bSliuzhongzhu hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, &send_msg, 4389194d18bSliuzhongzhu sizeof(u8), false, &resp_msg, sizeof(u8)); 4399194d18bSliuzhongzhu } 4409194d18bSliuzhongzhu 441e2cb1decSSalil Mehta static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 442e2cb1decSSalil Mehta { 443e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 444e2cb1decSSalil Mehta int ret; 445e2cb1decSSalil Mehta 446e2cb1decSSalil Mehta nic->ae_algo = &ae_algovf; 447e2cb1decSSalil Mehta nic->pdev = hdev->pdev; 448e2cb1decSSalil Mehta nic->numa_node_mask = hdev->numa_node_mask; 449424eb834SSalil Mehta nic->flags |= HNAE3_SUPPORT_VF; 450e2cb1decSSalil Mehta 451e2cb1decSSalil Mehta if (hdev->ae_dev->dev_type != HNAE3_DEV_KNIC) { 452e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "unsupported device type %d\n", 453e2cb1decSSalil Mehta hdev->ae_dev->dev_type); 454e2cb1decSSalil Mehta return -EINVAL; 455e2cb1decSSalil Mehta } 456e2cb1decSSalil Mehta 457e2cb1decSSalil Mehta ret = hclgevf_knic_setup(hdev); 458e2cb1decSSalil Mehta if (ret) 459e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 460e2cb1decSSalil Mehta ret); 461e2cb1decSSalil Mehta return ret; 462e2cb1decSSalil Mehta } 463e2cb1decSSalil Mehta 464e2cb1decSSalil Mehta static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 465e2cb1decSSalil Mehta { 46636cbbdf6SPeng Li if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 46736cbbdf6SPeng Li dev_warn(&hdev->pdev->dev, 46836cbbdf6SPeng Li "vector(vector_id %d) has been freed.\n", vector_id); 46936cbbdf6SPeng Li return; 47036cbbdf6SPeng Li } 47136cbbdf6SPeng Li 472e2cb1decSSalil Mehta hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 473e2cb1decSSalil Mehta hdev->num_msi_left += 1; 474e2cb1decSSalil Mehta hdev->num_msi_used -= 1; 475e2cb1decSSalil Mehta } 476e2cb1decSSalil Mehta 477e2cb1decSSalil Mehta static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 478e2cb1decSSalil Mehta struct hnae3_vector_info *vector_info) 479e2cb1decSSalil Mehta { 480e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 481e2cb1decSSalil Mehta struct hnae3_vector_info *vector = vector_info; 482e2cb1decSSalil Mehta int alloc = 0; 483e2cb1decSSalil Mehta int i, j; 484e2cb1decSSalil Mehta 485e2cb1decSSalil Mehta vector_num = min(hdev->num_msi_left, vector_num); 486e2cb1decSSalil Mehta 487e2cb1decSSalil Mehta for (j = 0; j < vector_num; j++) { 488e2cb1decSSalil Mehta for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 489e2cb1decSSalil Mehta if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 490e2cb1decSSalil Mehta vector->vector = pci_irq_vector(hdev->pdev, i); 491e2cb1decSSalil Mehta vector->io_addr = hdev->hw.io_base + 492e2cb1decSSalil Mehta HCLGEVF_VECTOR_REG_BASE + 493e2cb1decSSalil Mehta (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 494e2cb1decSSalil Mehta hdev->vector_status[i] = 0; 495e2cb1decSSalil Mehta hdev->vector_irq[i] = vector->vector; 496e2cb1decSSalil Mehta 497e2cb1decSSalil Mehta vector++; 498e2cb1decSSalil Mehta alloc++; 499e2cb1decSSalil Mehta 500e2cb1decSSalil Mehta break; 501e2cb1decSSalil Mehta } 502e2cb1decSSalil Mehta } 503e2cb1decSSalil Mehta } 504e2cb1decSSalil Mehta hdev->num_msi_left -= alloc; 505e2cb1decSSalil Mehta hdev->num_msi_used += alloc; 506e2cb1decSSalil Mehta 507e2cb1decSSalil Mehta return alloc; 508e2cb1decSSalil Mehta } 509e2cb1decSSalil Mehta 510e2cb1decSSalil Mehta static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 511e2cb1decSSalil Mehta { 512e2cb1decSSalil Mehta int i; 513e2cb1decSSalil Mehta 514e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 515e2cb1decSSalil Mehta if (vector == hdev->vector_irq[i]) 516e2cb1decSSalil Mehta return i; 517e2cb1decSSalil Mehta 518e2cb1decSSalil Mehta return -EINVAL; 519e2cb1decSSalil Mehta } 520e2cb1decSSalil Mehta 521374ad291SJian Shen static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 522374ad291SJian Shen const u8 hfunc, const u8 *key) 523374ad291SJian Shen { 524374ad291SJian Shen struct hclgevf_rss_config_cmd *req; 525374ad291SJian Shen struct hclgevf_desc desc; 526374ad291SJian Shen int key_offset; 527374ad291SJian Shen int key_size; 528374ad291SJian Shen int ret; 529374ad291SJian Shen 530374ad291SJian Shen req = (struct hclgevf_rss_config_cmd *)desc.data; 531374ad291SJian Shen 532374ad291SJian Shen for (key_offset = 0; key_offset < 3; key_offset++) { 533374ad291SJian Shen hclgevf_cmd_setup_basic_desc(&desc, 534374ad291SJian Shen HCLGEVF_OPC_RSS_GENERIC_CONFIG, 535374ad291SJian Shen false); 536374ad291SJian Shen 537374ad291SJian Shen req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 538374ad291SJian Shen req->hash_config |= 539374ad291SJian Shen (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 540374ad291SJian Shen 541374ad291SJian Shen if (key_offset == 2) 542374ad291SJian Shen key_size = 543374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE - HCLGEVF_RSS_HASH_KEY_NUM * 2; 544374ad291SJian Shen else 545374ad291SJian Shen key_size = HCLGEVF_RSS_HASH_KEY_NUM; 546374ad291SJian Shen 547374ad291SJian Shen memcpy(req->hash_key, 548374ad291SJian Shen key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 549374ad291SJian Shen 550374ad291SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 551374ad291SJian Shen if (ret) { 552374ad291SJian Shen dev_err(&hdev->pdev->dev, 553374ad291SJian Shen "Configure RSS config fail, status = %d\n", 554374ad291SJian Shen ret); 555374ad291SJian Shen return ret; 556374ad291SJian Shen } 557374ad291SJian Shen } 558374ad291SJian Shen 559374ad291SJian Shen return 0; 560374ad291SJian Shen } 561374ad291SJian Shen 562e2cb1decSSalil Mehta static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 563e2cb1decSSalil Mehta { 564e2cb1decSSalil Mehta return HCLGEVF_RSS_KEY_SIZE; 565e2cb1decSSalil Mehta } 566e2cb1decSSalil Mehta 567e2cb1decSSalil Mehta static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 568e2cb1decSSalil Mehta { 569e2cb1decSSalil Mehta return HCLGEVF_RSS_IND_TBL_SIZE; 570e2cb1decSSalil Mehta } 571e2cb1decSSalil Mehta 572e2cb1decSSalil Mehta static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 573e2cb1decSSalil Mehta { 574e2cb1decSSalil Mehta const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 575e2cb1decSSalil Mehta struct hclgevf_rss_indirection_table_cmd *req; 576e2cb1decSSalil Mehta struct hclgevf_desc desc; 577e2cb1decSSalil Mehta int status; 578e2cb1decSSalil Mehta int i, j; 579e2cb1decSSalil Mehta 580e2cb1decSSalil Mehta req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 581e2cb1decSSalil Mehta 582e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 583e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 584e2cb1decSSalil Mehta false); 585e2cb1decSSalil Mehta req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 586e2cb1decSSalil Mehta req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 587e2cb1decSSalil Mehta for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 588e2cb1decSSalil Mehta req->rss_result[j] = 589e2cb1decSSalil Mehta indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 590e2cb1decSSalil Mehta 591e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 592e2cb1decSSalil Mehta if (status) { 593e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 594e2cb1decSSalil Mehta "VF failed(=%d) to set RSS indirection table\n", 595e2cb1decSSalil Mehta status); 596e2cb1decSSalil Mehta return status; 597e2cb1decSSalil Mehta } 598e2cb1decSSalil Mehta } 599e2cb1decSSalil Mehta 600e2cb1decSSalil Mehta return 0; 601e2cb1decSSalil Mehta } 602e2cb1decSSalil Mehta 603e2cb1decSSalil Mehta static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 604e2cb1decSSalil Mehta { 605e2cb1decSSalil Mehta struct hclgevf_rss_tc_mode_cmd *req; 606e2cb1decSSalil Mehta u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 607e2cb1decSSalil Mehta u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 608e2cb1decSSalil Mehta u16 tc_size[HCLGEVF_MAX_TC_NUM]; 609e2cb1decSSalil Mehta struct hclgevf_desc desc; 610e2cb1decSSalil Mehta u16 roundup_size; 611e2cb1decSSalil Mehta int status; 612e2cb1decSSalil Mehta int i; 613e2cb1decSSalil Mehta 614e2cb1decSSalil Mehta req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 615e2cb1decSSalil Mehta 616e2cb1decSSalil Mehta roundup_size = roundup_pow_of_two(rss_size); 617e2cb1decSSalil Mehta roundup_size = ilog2(roundup_size); 618e2cb1decSSalil Mehta 619e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 620e2cb1decSSalil Mehta tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 621e2cb1decSSalil Mehta tc_size[i] = roundup_size; 622e2cb1decSSalil Mehta tc_offset[i] = rss_size * i; 623e2cb1decSSalil Mehta } 624e2cb1decSSalil Mehta 625e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 626e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 627e4e87715SPeng Li hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 628e2cb1decSSalil Mehta (tc_valid[i] & 0x1)); 629e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 630e2cb1decSSalil Mehta HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 631e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 632e2cb1decSSalil Mehta HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 633e2cb1decSSalil Mehta } 634e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 635e2cb1decSSalil Mehta if (status) 636e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 637e2cb1decSSalil Mehta "VF failed(=%d) to set rss tc mode\n", status); 638e2cb1decSSalil Mehta 639e2cb1decSSalil Mehta return status; 640e2cb1decSSalil Mehta } 641e2cb1decSSalil Mehta 642a638b1d8SJian Shen /* for revision 0x20, vf shared the same rss config with pf */ 643a638b1d8SJian Shen static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 644a638b1d8SJian Shen { 645a638b1d8SJian Shen #define HCLGEVF_RSS_MBX_RESP_LEN 8 646a638b1d8SJian Shen 647a638b1d8SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 648a638b1d8SJian Shen u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 649a638b1d8SJian Shen u16 msg_num, hash_key_index; 650a638b1d8SJian Shen u8 index; 651a638b1d8SJian Shen int ret; 652a638b1d8SJian Shen 653a638b1d8SJian Shen msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 654a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN; 655a638b1d8SJian Shen for (index = 0; index < msg_num; index++) { 656a638b1d8SJian Shen ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_RSS_KEY, 0, 657a638b1d8SJian Shen &index, sizeof(index), 658a638b1d8SJian Shen true, resp_msg, 659a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN); 660a638b1d8SJian Shen if (ret) { 661a638b1d8SJian Shen dev_err(&hdev->pdev->dev, 662a638b1d8SJian Shen "VF get rss hash key from PF failed, ret=%d", 663a638b1d8SJian Shen ret); 664a638b1d8SJian Shen return ret; 665a638b1d8SJian Shen } 666a638b1d8SJian Shen 667a638b1d8SJian Shen hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 668a638b1d8SJian Shen if (index == msg_num - 1) 669a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 670a638b1d8SJian Shen &resp_msg[0], 671a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE - hash_key_index); 672a638b1d8SJian Shen else 673a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 674a638b1d8SJian Shen &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 675a638b1d8SJian Shen } 676a638b1d8SJian Shen 677a638b1d8SJian Shen return 0; 678a638b1d8SJian Shen } 679a638b1d8SJian Shen 680e2cb1decSSalil Mehta static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 681e2cb1decSSalil Mehta u8 *hfunc) 682e2cb1decSSalil Mehta { 683e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 684e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 685a638b1d8SJian Shen int i, ret; 686e2cb1decSSalil Mehta 687374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 688374ad291SJian Shen /* Get hash algorithm */ 689374ad291SJian Shen if (hfunc) { 690374ad291SJian Shen switch (rss_cfg->hash_algo) { 691374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 692374ad291SJian Shen *hfunc = ETH_RSS_HASH_TOP; 693374ad291SJian Shen break; 694374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 695374ad291SJian Shen *hfunc = ETH_RSS_HASH_XOR; 696374ad291SJian Shen break; 697374ad291SJian Shen default: 698374ad291SJian Shen *hfunc = ETH_RSS_HASH_UNKNOWN; 699374ad291SJian Shen break; 700374ad291SJian Shen } 701374ad291SJian Shen } 702374ad291SJian Shen 703374ad291SJian Shen /* Get the RSS Key required by the user */ 704374ad291SJian Shen if (key) 705374ad291SJian Shen memcpy(key, rss_cfg->rss_hash_key, 706374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 707a638b1d8SJian Shen } else { 708a638b1d8SJian Shen if (hfunc) 709a638b1d8SJian Shen *hfunc = ETH_RSS_HASH_TOP; 710a638b1d8SJian Shen if (key) { 711a638b1d8SJian Shen ret = hclgevf_get_rss_hash_key(hdev); 712a638b1d8SJian Shen if (ret) 713a638b1d8SJian Shen return ret; 714a638b1d8SJian Shen memcpy(key, rss_cfg->rss_hash_key, 715a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE); 716a638b1d8SJian Shen } 717374ad291SJian Shen } 718374ad291SJian Shen 719e2cb1decSSalil Mehta if (indir) 720e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 721e2cb1decSSalil Mehta indir[i] = rss_cfg->rss_indirection_tbl[i]; 722e2cb1decSSalil Mehta 723374ad291SJian Shen return 0; 724e2cb1decSSalil Mehta } 725e2cb1decSSalil Mehta 726e2cb1decSSalil Mehta static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 727e2cb1decSSalil Mehta const u8 *key, const u8 hfunc) 728e2cb1decSSalil Mehta { 729e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 730e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 731374ad291SJian Shen int ret, i; 732374ad291SJian Shen 733374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 734374ad291SJian Shen /* Set the RSS Hash Key if specififed by the user */ 735374ad291SJian Shen if (key) { 736374ad291SJian Shen switch (hfunc) { 737374ad291SJian Shen case ETH_RSS_HASH_TOP: 738374ad291SJian Shen rss_cfg->hash_algo = 739374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 740374ad291SJian Shen break; 741374ad291SJian Shen case ETH_RSS_HASH_XOR: 742374ad291SJian Shen rss_cfg->hash_algo = 743374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_SIMPLE; 744374ad291SJian Shen break; 745374ad291SJian Shen case ETH_RSS_HASH_NO_CHANGE: 746374ad291SJian Shen break; 747374ad291SJian Shen default: 748374ad291SJian Shen return -EINVAL; 749374ad291SJian Shen } 750374ad291SJian Shen 751374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 752374ad291SJian Shen key); 753374ad291SJian Shen if (ret) 754374ad291SJian Shen return ret; 755374ad291SJian Shen 756374ad291SJian Shen /* Update the shadow RSS key with user specified qids */ 757374ad291SJian Shen memcpy(rss_cfg->rss_hash_key, key, 758374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 759374ad291SJian Shen } 760374ad291SJian Shen } 761e2cb1decSSalil Mehta 762e2cb1decSSalil Mehta /* update the shadow RSS table with user specified qids */ 763e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 764e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = indir[i]; 765e2cb1decSSalil Mehta 766e2cb1decSSalil Mehta /* update the hardware */ 767e2cb1decSSalil Mehta return hclgevf_set_rss_indir_table(hdev); 768e2cb1decSSalil Mehta } 769e2cb1decSSalil Mehta 770d97b3072SJian Shen static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 771d97b3072SJian Shen { 772d97b3072SJian Shen u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 773d97b3072SJian Shen 774d97b3072SJian Shen if (nfc->data & RXH_L4_B_2_3) 775d97b3072SJian Shen hash_sets |= HCLGEVF_D_PORT_BIT; 776d97b3072SJian Shen else 777d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_PORT_BIT; 778d97b3072SJian Shen 779d97b3072SJian Shen if (nfc->data & RXH_IP_SRC) 780d97b3072SJian Shen hash_sets |= HCLGEVF_S_IP_BIT; 781d97b3072SJian Shen else 782d97b3072SJian Shen hash_sets &= ~HCLGEVF_S_IP_BIT; 783d97b3072SJian Shen 784d97b3072SJian Shen if (nfc->data & RXH_IP_DST) 785d97b3072SJian Shen hash_sets |= HCLGEVF_D_IP_BIT; 786d97b3072SJian Shen else 787d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_IP_BIT; 788d97b3072SJian Shen 789d97b3072SJian Shen if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 790d97b3072SJian Shen hash_sets |= HCLGEVF_V_TAG_BIT; 791d97b3072SJian Shen 792d97b3072SJian Shen return hash_sets; 793d97b3072SJian Shen } 794d97b3072SJian Shen 795d97b3072SJian Shen static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 796d97b3072SJian Shen struct ethtool_rxnfc *nfc) 797d97b3072SJian Shen { 798d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 799d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 800d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 801d97b3072SJian Shen struct hclgevf_desc desc; 802d97b3072SJian Shen u8 tuple_sets; 803d97b3072SJian Shen int ret; 804d97b3072SJian Shen 805d97b3072SJian Shen if (handle->pdev->revision == 0x20) 806d97b3072SJian Shen return -EOPNOTSUPP; 807d97b3072SJian Shen 808d97b3072SJian Shen if (nfc->data & 809d97b3072SJian Shen ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 810d97b3072SJian Shen return -EINVAL; 811d97b3072SJian Shen 812d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 813d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 814d97b3072SJian Shen 815d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 816d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 817d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 818d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 819d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 820d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 821d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 822d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 823d97b3072SJian Shen 824d97b3072SJian Shen tuple_sets = hclgevf_get_rss_hash_bits(nfc); 825d97b3072SJian Shen switch (nfc->flow_type) { 826d97b3072SJian Shen case TCP_V4_FLOW: 827d97b3072SJian Shen req->ipv4_tcp_en = tuple_sets; 828d97b3072SJian Shen break; 829d97b3072SJian Shen case TCP_V6_FLOW: 830d97b3072SJian Shen req->ipv6_tcp_en = tuple_sets; 831d97b3072SJian Shen break; 832d97b3072SJian Shen case UDP_V4_FLOW: 833d97b3072SJian Shen req->ipv4_udp_en = tuple_sets; 834d97b3072SJian Shen break; 835d97b3072SJian Shen case UDP_V6_FLOW: 836d97b3072SJian Shen req->ipv6_udp_en = tuple_sets; 837d97b3072SJian Shen break; 838d97b3072SJian Shen case SCTP_V4_FLOW: 839d97b3072SJian Shen req->ipv4_sctp_en = tuple_sets; 840d97b3072SJian Shen break; 841d97b3072SJian Shen case SCTP_V6_FLOW: 842d97b3072SJian Shen if ((nfc->data & RXH_L4_B_0_1) || 843d97b3072SJian Shen (nfc->data & RXH_L4_B_2_3)) 844d97b3072SJian Shen return -EINVAL; 845d97b3072SJian Shen 846d97b3072SJian Shen req->ipv6_sctp_en = tuple_sets; 847d97b3072SJian Shen break; 848d97b3072SJian Shen case IPV4_FLOW: 849d97b3072SJian Shen req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 850d97b3072SJian Shen break; 851d97b3072SJian Shen case IPV6_FLOW: 852d97b3072SJian Shen req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 853d97b3072SJian Shen break; 854d97b3072SJian Shen default: 855d97b3072SJian Shen return -EINVAL; 856d97b3072SJian Shen } 857d97b3072SJian Shen 858d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 859d97b3072SJian Shen if (ret) { 860d97b3072SJian Shen dev_err(&hdev->pdev->dev, 861d97b3072SJian Shen "Set rss tuple fail, status = %d\n", ret); 862d97b3072SJian Shen return ret; 863d97b3072SJian Shen } 864d97b3072SJian Shen 865d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 866d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 867d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 868d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 869d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 870d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 871d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 872d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 873d97b3072SJian Shen return 0; 874d97b3072SJian Shen } 875d97b3072SJian Shen 876d97b3072SJian Shen static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 877d97b3072SJian Shen struct ethtool_rxnfc *nfc) 878d97b3072SJian Shen { 879d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 880d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 881d97b3072SJian Shen u8 tuple_sets; 882d97b3072SJian Shen 883d97b3072SJian Shen if (handle->pdev->revision == 0x20) 884d97b3072SJian Shen return -EOPNOTSUPP; 885d97b3072SJian Shen 886d97b3072SJian Shen nfc->data = 0; 887d97b3072SJian Shen 888d97b3072SJian Shen switch (nfc->flow_type) { 889d97b3072SJian Shen case TCP_V4_FLOW: 890d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 891d97b3072SJian Shen break; 892d97b3072SJian Shen case UDP_V4_FLOW: 893d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 894d97b3072SJian Shen break; 895d97b3072SJian Shen case TCP_V6_FLOW: 896d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 897d97b3072SJian Shen break; 898d97b3072SJian Shen case UDP_V6_FLOW: 899d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 900d97b3072SJian Shen break; 901d97b3072SJian Shen case SCTP_V4_FLOW: 902d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 903d97b3072SJian Shen break; 904d97b3072SJian Shen case SCTP_V6_FLOW: 905d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 906d97b3072SJian Shen break; 907d97b3072SJian Shen case IPV4_FLOW: 908d97b3072SJian Shen case IPV6_FLOW: 909d97b3072SJian Shen tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 910d97b3072SJian Shen break; 911d97b3072SJian Shen default: 912d97b3072SJian Shen return -EINVAL; 913d97b3072SJian Shen } 914d97b3072SJian Shen 915d97b3072SJian Shen if (!tuple_sets) 916d97b3072SJian Shen return 0; 917d97b3072SJian Shen 918d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_PORT_BIT) 919d97b3072SJian Shen nfc->data |= RXH_L4_B_2_3; 920d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_PORT_BIT) 921d97b3072SJian Shen nfc->data |= RXH_L4_B_0_1; 922d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_IP_BIT) 923d97b3072SJian Shen nfc->data |= RXH_IP_DST; 924d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_IP_BIT) 925d97b3072SJian Shen nfc->data |= RXH_IP_SRC; 926d97b3072SJian Shen 927d97b3072SJian Shen return 0; 928d97b3072SJian Shen } 929d97b3072SJian Shen 930d97b3072SJian Shen static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 931d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg) 932d97b3072SJian Shen { 933d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 934d97b3072SJian Shen struct hclgevf_desc desc; 935d97b3072SJian Shen int ret; 936d97b3072SJian Shen 937d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 938d97b3072SJian Shen 939d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 940d97b3072SJian Shen 941d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 942d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 943d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 944d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 945d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 946d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 947d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 948d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 949d97b3072SJian Shen 950d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 951d97b3072SJian Shen if (ret) 952d97b3072SJian Shen dev_err(&hdev->pdev->dev, 953d97b3072SJian Shen "Configure rss input fail, status = %d\n", ret); 954d97b3072SJian Shen return ret; 955d97b3072SJian Shen } 956d97b3072SJian Shen 957e2cb1decSSalil Mehta static int hclgevf_get_tc_size(struct hnae3_handle *handle) 958e2cb1decSSalil Mehta { 959e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 960e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 961e2cb1decSSalil Mehta 962e2cb1decSSalil Mehta return rss_cfg->rss_size; 963e2cb1decSSalil Mehta } 964e2cb1decSSalil Mehta 965e2cb1decSSalil Mehta static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 966b204bc74SPeng Li int vector_id, 967e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 968e2cb1decSSalil Mehta { 969e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 970e2cb1decSSalil Mehta struct hnae3_ring_chain_node *node; 971e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 972e2cb1decSSalil Mehta struct hclgevf_desc desc; 973b204bc74SPeng Li int i = 0; 974e2cb1decSSalil Mehta int status; 975e2cb1decSSalil Mehta u8 type; 976e2cb1decSSalil Mehta 977e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 978e2cb1decSSalil Mehta 979e2cb1decSSalil Mehta for (node = ring_chain; node; node = node->next) { 9805d02a58dSYunsheng Lin int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 9815d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 9825d02a58dSYunsheng Lin 9835d02a58dSYunsheng Lin if (i == 0) { 9845d02a58dSYunsheng Lin hclgevf_cmd_setup_basic_desc(&desc, 9855d02a58dSYunsheng Lin HCLGEVF_OPC_MBX_VF_TO_PF, 9865d02a58dSYunsheng Lin false); 9875d02a58dSYunsheng Lin type = en ? 9885d02a58dSYunsheng Lin HCLGE_MBX_MAP_RING_TO_VECTOR : 9895d02a58dSYunsheng Lin HCLGE_MBX_UNMAP_RING_TO_VECTOR; 9905d02a58dSYunsheng Lin req->msg[0] = type; 9915d02a58dSYunsheng Lin req->msg[1] = vector_id; 9925d02a58dSYunsheng Lin } 9935d02a58dSYunsheng Lin 9945d02a58dSYunsheng Lin req->msg[idx_offset] = 995e4e87715SPeng Li hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 9965d02a58dSYunsheng Lin req->msg[idx_offset + 1] = node->tqp_index; 997e4e87715SPeng Li req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 99879eee410SFuyun Liang HNAE3_RING_GL_IDX_M, 99979eee410SFuyun Liang HNAE3_RING_GL_IDX_S); 100079eee410SFuyun Liang 10015d02a58dSYunsheng Lin i++; 10025d02a58dSYunsheng Lin if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 10035d02a58dSYunsheng Lin HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 10045d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 10055d02a58dSYunsheng Lin !node->next) { 1006e2cb1decSSalil Mehta req->msg[2] = i; 1007e2cb1decSSalil Mehta 1008e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1009e2cb1decSSalil Mehta if (status) { 1010e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1011e2cb1decSSalil Mehta "Map TQP fail, status is %d.\n", 1012e2cb1decSSalil Mehta status); 1013e2cb1decSSalil Mehta return status; 1014e2cb1decSSalil Mehta } 1015e2cb1decSSalil Mehta i = 0; 1016e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 1017e2cb1decSSalil Mehta HCLGEVF_OPC_MBX_VF_TO_PF, 1018e2cb1decSSalil Mehta false); 1019e2cb1decSSalil Mehta req->msg[0] = type; 1020e2cb1decSSalil Mehta req->msg[1] = vector_id; 1021e2cb1decSSalil Mehta } 1022e2cb1decSSalil Mehta } 1023e2cb1decSSalil Mehta 1024e2cb1decSSalil Mehta return 0; 1025e2cb1decSSalil Mehta } 1026e2cb1decSSalil Mehta 1027e2cb1decSSalil Mehta static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1028e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1029e2cb1decSSalil Mehta { 1030b204bc74SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1031b204bc74SPeng Li int vector_id; 1032b204bc74SPeng Li 1033b204bc74SPeng Li vector_id = hclgevf_get_vector_index(hdev, vector); 1034b204bc74SPeng Li if (vector_id < 0) { 1035b204bc74SPeng Li dev_err(&handle->pdev->dev, 1036b204bc74SPeng Li "Get vector index fail. ret =%d\n", vector_id); 1037b204bc74SPeng Li return vector_id; 1038b204bc74SPeng Li } 1039b204bc74SPeng Li 1040b204bc74SPeng Li return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1041e2cb1decSSalil Mehta } 1042e2cb1decSSalil Mehta 1043e2cb1decSSalil Mehta static int hclgevf_unmap_ring_from_vector( 1044e2cb1decSSalil Mehta struct hnae3_handle *handle, 1045e2cb1decSSalil Mehta int vector, 1046e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1047e2cb1decSSalil Mehta { 1048e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1049e2cb1decSSalil Mehta int ret, vector_id; 1050e2cb1decSSalil Mehta 1051dea846e8SHuazhong Tan if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1052dea846e8SHuazhong Tan return 0; 1053dea846e8SHuazhong Tan 1054e2cb1decSSalil Mehta vector_id = hclgevf_get_vector_index(hdev, vector); 1055e2cb1decSSalil Mehta if (vector_id < 0) { 1056e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1057e2cb1decSSalil Mehta "Get vector index fail. ret =%d\n", vector_id); 1058e2cb1decSSalil Mehta return vector_id; 1059e2cb1decSSalil Mehta } 1060e2cb1decSSalil Mehta 1061b204bc74SPeng Li ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 10620d3e6631SYunsheng Lin if (ret) 1063e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1064e2cb1decSSalil Mehta "Unmap ring from vector fail. vector=%d, ret =%d\n", 1065e2cb1decSSalil Mehta vector_id, 1066e2cb1decSSalil Mehta ret); 10670d3e6631SYunsheng Lin 1068e2cb1decSSalil Mehta return ret; 1069e2cb1decSSalil Mehta } 1070e2cb1decSSalil Mehta 10710d3e6631SYunsheng Lin static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 10720d3e6631SYunsheng Lin { 10730d3e6631SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 107403718db9SYunsheng Lin int vector_id; 10750d3e6631SYunsheng Lin 107603718db9SYunsheng Lin vector_id = hclgevf_get_vector_index(hdev, vector); 107703718db9SYunsheng Lin if (vector_id < 0) { 107803718db9SYunsheng Lin dev_err(&handle->pdev->dev, 107903718db9SYunsheng Lin "hclgevf_put_vector get vector index fail. ret =%d\n", 108003718db9SYunsheng Lin vector_id); 108103718db9SYunsheng Lin return vector_id; 108203718db9SYunsheng Lin } 108303718db9SYunsheng Lin 108403718db9SYunsheng Lin hclgevf_free_vector(hdev, vector_id); 1085e2cb1decSSalil Mehta 1086e2cb1decSSalil Mehta return 0; 1087e2cb1decSSalil Mehta } 1088e2cb1decSSalil Mehta 10893b75c3dfSPeng Li static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1090f01f5559SJian Shen bool en_bc_pmc) 1091e2cb1decSSalil Mehta { 1092e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 1093e2cb1decSSalil Mehta struct hclgevf_desc desc; 1094f01f5559SJian Shen int ret; 1095e2cb1decSSalil Mehta 1096e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1097e2cb1decSSalil Mehta 1098e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 1099e2cb1decSSalil Mehta req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 1100f01f5559SJian Shen req->msg[1] = en_bc_pmc ? 1 : 0; 1101e2cb1decSSalil Mehta 1102f01f5559SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1103f01f5559SJian Shen if (ret) 1104e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1105f01f5559SJian Shen "Set promisc mode fail, status is %d.\n", ret); 1106e2cb1decSSalil Mehta 1107f01f5559SJian Shen return ret; 1108e2cb1decSSalil Mehta } 1109e2cb1decSSalil Mehta 1110f01f5559SJian Shen static int hclgevf_set_promisc_mode(struct hclgevf_dev *hdev, bool en_bc_pmc) 1111e2cb1decSSalil Mehta { 1112f01f5559SJian Shen return hclgevf_cmd_set_promisc_mode(hdev, en_bc_pmc); 1113e2cb1decSSalil Mehta } 1114e2cb1decSSalil Mehta 1115e2cb1decSSalil Mehta static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, int tqp_id, 1116e2cb1decSSalil Mehta int stream_id, bool enable) 1117e2cb1decSSalil Mehta { 1118e2cb1decSSalil Mehta struct hclgevf_cfg_com_tqp_queue_cmd *req; 1119e2cb1decSSalil Mehta struct hclgevf_desc desc; 1120e2cb1decSSalil Mehta int status; 1121e2cb1decSSalil Mehta 1122e2cb1decSSalil Mehta req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1123e2cb1decSSalil Mehta 1124e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1125e2cb1decSSalil Mehta false); 1126e2cb1decSSalil Mehta req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1127e2cb1decSSalil Mehta req->stream_id = cpu_to_le16(stream_id); 1128e2cb1decSSalil Mehta req->enable |= enable << HCLGEVF_TQP_ENABLE_B; 1129e2cb1decSSalil Mehta 1130e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1131e2cb1decSSalil Mehta if (status) 1132e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1133e2cb1decSSalil Mehta "TQP enable fail, status =%d.\n", status); 1134e2cb1decSSalil Mehta 1135e2cb1decSSalil Mehta return status; 1136e2cb1decSSalil Mehta } 1137e2cb1decSSalil Mehta 1138e2cb1decSSalil Mehta static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1139e2cb1decSSalil Mehta { 1140b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1141e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 1142e2cb1decSSalil Mehta int i; 1143e2cb1decSSalil Mehta 1144b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 1145b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1146e2cb1decSSalil Mehta memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1147e2cb1decSSalil Mehta } 1148e2cb1decSSalil Mehta } 1149e2cb1decSSalil Mehta 1150e2cb1decSSalil Mehta static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1151e2cb1decSSalil Mehta { 1152e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1153e2cb1decSSalil Mehta 1154e2cb1decSSalil Mehta ether_addr_copy(p, hdev->hw.mac.mac_addr); 1155e2cb1decSSalil Mehta } 1156e2cb1decSSalil Mehta 115759098055SFuyun Liang static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 115859098055SFuyun Liang bool is_first) 1159e2cb1decSSalil Mehta { 1160e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1161e2cb1decSSalil Mehta u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1162e2cb1decSSalil Mehta u8 *new_mac_addr = (u8 *)p; 1163e2cb1decSSalil Mehta u8 msg_data[ETH_ALEN * 2]; 116459098055SFuyun Liang u16 subcode; 1165e2cb1decSSalil Mehta int status; 1166e2cb1decSSalil Mehta 1167e2cb1decSSalil Mehta ether_addr_copy(msg_data, new_mac_addr); 1168e2cb1decSSalil Mehta ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 1169e2cb1decSSalil Mehta 117059098055SFuyun Liang subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 117159098055SFuyun Liang HCLGE_MBX_MAC_VLAN_UC_MODIFY; 117259098055SFuyun Liang 1173e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 117459098055SFuyun Liang subcode, msg_data, ETH_ALEN * 2, 11752097fdefSJian Shen true, NULL, 0); 1176e2cb1decSSalil Mehta if (!status) 1177e2cb1decSSalil Mehta ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1178e2cb1decSSalil Mehta 1179e2cb1decSSalil Mehta return status; 1180e2cb1decSSalil Mehta } 1181e2cb1decSSalil Mehta 1182e2cb1decSSalil Mehta static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1183e2cb1decSSalil Mehta const unsigned char *addr) 1184e2cb1decSSalil Mehta { 1185e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1186e2cb1decSSalil Mehta 1187e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1188e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_ADD, 1189e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1190e2cb1decSSalil Mehta } 1191e2cb1decSSalil Mehta 1192e2cb1decSSalil Mehta static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1193e2cb1decSSalil Mehta const unsigned char *addr) 1194e2cb1decSSalil Mehta { 1195e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1196e2cb1decSSalil Mehta 1197e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1198e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1199e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1200e2cb1decSSalil Mehta } 1201e2cb1decSSalil Mehta 1202e2cb1decSSalil Mehta static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1203e2cb1decSSalil Mehta const unsigned char *addr) 1204e2cb1decSSalil Mehta { 1205e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1206e2cb1decSSalil Mehta 1207e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1208e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_ADD, 1209e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1210e2cb1decSSalil Mehta } 1211e2cb1decSSalil Mehta 1212e2cb1decSSalil Mehta static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1213e2cb1decSSalil Mehta const unsigned char *addr) 1214e2cb1decSSalil Mehta { 1215e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1216e2cb1decSSalil Mehta 1217e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1218e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1219e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1220e2cb1decSSalil Mehta } 1221e2cb1decSSalil Mehta 1222e2cb1decSSalil Mehta static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1223e2cb1decSSalil Mehta __be16 proto, u16 vlan_id, 1224e2cb1decSSalil Mehta bool is_kill) 1225e2cb1decSSalil Mehta { 1226e2cb1decSSalil Mehta #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1227e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1228e2cb1decSSalil Mehta u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1229e2cb1decSSalil Mehta 1230e2cb1decSSalil Mehta if (vlan_id > 4095) 1231e2cb1decSSalil Mehta return -EINVAL; 1232e2cb1decSSalil Mehta 1233e2cb1decSSalil Mehta if (proto != htons(ETH_P_8021Q)) 1234e2cb1decSSalil Mehta return -EPROTONOSUPPORT; 1235e2cb1decSSalil Mehta 1236e2cb1decSSalil Mehta msg_data[0] = is_kill; 1237e2cb1decSSalil Mehta memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1238e2cb1decSSalil Mehta memcpy(&msg_data[3], &proto, sizeof(proto)); 1239e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1240e2cb1decSSalil Mehta HCLGE_MBX_VLAN_FILTER, msg_data, 1241e2cb1decSSalil Mehta HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 1242e2cb1decSSalil Mehta } 1243e2cb1decSSalil Mehta 1244b2641e2aSYunsheng Lin static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1245b2641e2aSYunsheng Lin { 1246b2641e2aSYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1247b2641e2aSYunsheng Lin u8 msg_data; 1248b2641e2aSYunsheng Lin 1249b2641e2aSYunsheng Lin msg_data = enable ? 1 : 0; 1250b2641e2aSYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1251b2641e2aSYunsheng Lin HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1252b2641e2aSYunsheng Lin 1, false, NULL, 0); 1253b2641e2aSYunsheng Lin } 1254b2641e2aSYunsheng Lin 12557fa6be4fSHuazhong Tan static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1256e2cb1decSSalil Mehta { 1257e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1258e2cb1decSSalil Mehta u8 msg_data[2]; 12591a426f8bSPeng Li int ret; 1260e2cb1decSSalil Mehta 1261e2cb1decSSalil Mehta memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 1262e2cb1decSSalil Mehta 12631a426f8bSPeng Li /* disable vf queue before send queue reset msg to PF */ 12641a426f8bSPeng Li ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 12651a426f8bSPeng Li if (ret) 12667fa6be4fSHuazhong Tan return ret; 12671a426f8bSPeng Li 12687fa6be4fSHuazhong Tan return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 12691a426f8bSPeng Li 2, true, NULL, 0); 1270e2cb1decSSalil Mehta } 1271e2cb1decSSalil Mehta 1272818f1675SYunsheng Lin static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1273818f1675SYunsheng Lin { 1274818f1675SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1275818f1675SYunsheng Lin 1276818f1675SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu, 1277818f1675SYunsheng Lin sizeof(new_mtu), true, NULL, 0); 1278818f1675SYunsheng Lin } 1279818f1675SYunsheng Lin 12806988eb2aSSalil Mehta static int hclgevf_notify_client(struct hclgevf_dev *hdev, 12816988eb2aSSalil Mehta enum hnae3_reset_notify_type type) 12826988eb2aSSalil Mehta { 12836988eb2aSSalil Mehta struct hnae3_client *client = hdev->nic_client; 12846988eb2aSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 12856a5f6fa3SHuazhong Tan int ret; 12866988eb2aSSalil Mehta 12876988eb2aSSalil Mehta if (!client->ops->reset_notify) 12886988eb2aSSalil Mehta return -EOPNOTSUPP; 12896988eb2aSSalil Mehta 12906a5f6fa3SHuazhong Tan ret = client->ops->reset_notify(handle, type); 12916a5f6fa3SHuazhong Tan if (ret) 12926a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 12936a5f6fa3SHuazhong Tan type, ret); 12946a5f6fa3SHuazhong Tan 12956a5f6fa3SHuazhong Tan return ret; 12966988eb2aSSalil Mehta } 12976988eb2aSSalil Mehta 12986ff3cf07SHuazhong Tan static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 12996ff3cf07SHuazhong Tan { 13006ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 13016ff3cf07SHuazhong Tan 13026ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DONE, &hdev->flr_state); 13036ff3cf07SHuazhong Tan } 13046ff3cf07SHuazhong Tan 13056ff3cf07SHuazhong Tan static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev, 13066ff3cf07SHuazhong Tan unsigned long delay_us, 13076ff3cf07SHuazhong Tan unsigned long wait_cnt) 13086ff3cf07SHuazhong Tan { 13096ff3cf07SHuazhong Tan unsigned long cnt = 0; 13106ff3cf07SHuazhong Tan 13116ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) && 13126ff3cf07SHuazhong Tan cnt++ < wait_cnt) 13136ff3cf07SHuazhong Tan usleep_range(delay_us, delay_us * 2); 13146ff3cf07SHuazhong Tan 13156ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) { 13166ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 13176ff3cf07SHuazhong Tan "flr wait timeout\n"); 13186ff3cf07SHuazhong Tan return -ETIMEDOUT; 13196ff3cf07SHuazhong Tan } 13206ff3cf07SHuazhong Tan 13216ff3cf07SHuazhong Tan return 0; 13226ff3cf07SHuazhong Tan } 13236ff3cf07SHuazhong Tan 13246988eb2aSSalil Mehta static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 13256988eb2aSSalil Mehta { 1326aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_US 20000 1327aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_CNT 2000 1328aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1329aa5c4f17SHuazhong Tan (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1330aa5c4f17SHuazhong Tan 1331aa5c4f17SHuazhong Tan u32 val; 1332aa5c4f17SHuazhong Tan int ret; 13336988eb2aSSalil Mehta 13346988eb2aSSalil Mehta /* wait to check the hardware reset completion status */ 1335aa5c4f17SHuazhong Tan val = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1336aa5c4f17SHuazhong Tan dev_info(&hdev->pdev->dev, "checking vf resetting status: %x\n", val); 1337aa5c4f17SHuazhong Tan 13386ff3cf07SHuazhong Tan if (hdev->reset_type == HNAE3_FLR_RESET) 13396ff3cf07SHuazhong Tan return hclgevf_flr_poll_timeout(hdev, 13406ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_US, 13416ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_CNT); 13426ff3cf07SHuazhong Tan 1343aa5c4f17SHuazhong Tan ret = readl_poll_timeout(hdev->hw.io_base + HCLGEVF_RST_ING, val, 1344aa5c4f17SHuazhong Tan !(val & HCLGEVF_RST_ING_BITS), 1345aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_US, 1346aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 13476988eb2aSSalil Mehta 13486988eb2aSSalil Mehta /* hardware completion status should be available by this time */ 1349aa5c4f17SHuazhong Tan if (ret) { 1350aa5c4f17SHuazhong Tan dev_err(&hdev->pdev->dev, 13516988eb2aSSalil Mehta "could'nt get reset done status from h/w, timeout!\n"); 1352aa5c4f17SHuazhong Tan return ret; 13536988eb2aSSalil Mehta } 13546988eb2aSSalil Mehta 13556988eb2aSSalil Mehta /* we will wait a bit more to let reset of the stack to complete. This 13566988eb2aSSalil Mehta * might happen in case reset assertion was made by PF. Yes, this also 13576988eb2aSSalil Mehta * means we might end up waiting bit more even for VF reset. 13586988eb2aSSalil Mehta */ 13596988eb2aSSalil Mehta msleep(5000); 13606988eb2aSSalil Mehta 13616988eb2aSSalil Mehta return 0; 13626988eb2aSSalil Mehta } 13636988eb2aSSalil Mehta 13646988eb2aSSalil Mehta static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 13656988eb2aSSalil Mehta { 13667a01c897SSalil Mehta int ret; 13677a01c897SSalil Mehta 13686988eb2aSSalil Mehta /* uninitialize the nic client */ 13696a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 13706a5f6fa3SHuazhong Tan if (ret) 13716a5f6fa3SHuazhong Tan return ret; 13726988eb2aSSalil Mehta 13737a01c897SSalil Mehta /* re-initialize the hclge device */ 13749c6f7085SHuazhong Tan ret = hclgevf_reset_hdev(hdev); 13757a01c897SSalil Mehta if (ret) { 13767a01c897SSalil Mehta dev_err(&hdev->pdev->dev, 13777a01c897SSalil Mehta "hclge device re-init failed, VF is disabled!\n"); 13787a01c897SSalil Mehta return ret; 13797a01c897SSalil Mehta } 13806988eb2aSSalil Mehta 13816988eb2aSSalil Mehta /* bring up the nic client again */ 13826a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 13836a5f6fa3SHuazhong Tan if (ret) 13846a5f6fa3SHuazhong Tan return ret; 13856988eb2aSSalil Mehta 13861f609492SYunsheng Lin return hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT); 13876988eb2aSSalil Mehta } 13886988eb2aSSalil Mehta 1389dea846e8SHuazhong Tan static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1390dea846e8SHuazhong Tan { 1391dea846e8SHuazhong Tan int ret = 0; 1392dea846e8SHuazhong Tan 1393dea846e8SHuazhong Tan switch (hdev->reset_type) { 1394dea846e8SHuazhong Tan case HNAE3_VF_FUNC_RESET: 1395dea846e8SHuazhong Tan ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1396dea846e8SHuazhong Tan 0, true, NULL, sizeof(u8)); 1397dea846e8SHuazhong Tan break; 13986ff3cf07SHuazhong Tan case HNAE3_FLR_RESET: 13996ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 14006ff3cf07SHuazhong Tan break; 1401dea846e8SHuazhong Tan default: 1402dea846e8SHuazhong Tan break; 1403dea846e8SHuazhong Tan } 1404dea846e8SHuazhong Tan 1405ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1406ef5f8e50SHuazhong Tan 1407dea846e8SHuazhong Tan dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1408dea846e8SHuazhong Tan hdev->reset_type, ret); 1409dea846e8SHuazhong Tan 1410dea846e8SHuazhong Tan return ret; 1411dea846e8SHuazhong Tan } 1412dea846e8SHuazhong Tan 14136988eb2aSSalil Mehta static int hclgevf_reset(struct hclgevf_dev *hdev) 14146988eb2aSSalil Mehta { 1415dea846e8SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 14166988eb2aSSalil Mehta int ret; 14176988eb2aSSalil Mehta 1418dea846e8SHuazhong Tan /* Initialize ae_dev reset status as well, in case enet layer wants to 1419dea846e8SHuazhong Tan * know if device is undergoing reset 1420dea846e8SHuazhong Tan */ 1421dea846e8SHuazhong Tan ae_dev->reset_type = hdev->reset_type; 14224d60291bSHuazhong Tan hdev->reset_count++; 14236988eb2aSSalil Mehta rtnl_lock(); 14246988eb2aSSalil Mehta 14256988eb2aSSalil Mehta /* bring down the nic to stop any ongoing TX/RX */ 14266a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 14276a5f6fa3SHuazhong Tan if (ret) 14286a5f6fa3SHuazhong Tan goto err_reset_lock; 14296988eb2aSSalil Mehta 143029118ab9SHuazhong Tan rtnl_unlock(); 143129118ab9SHuazhong Tan 14326a5f6fa3SHuazhong Tan ret = hclgevf_reset_prepare_wait(hdev); 14336a5f6fa3SHuazhong Tan if (ret) 14346a5f6fa3SHuazhong Tan goto err_reset; 1435dea846e8SHuazhong Tan 14366988eb2aSSalil Mehta /* check if VF could successfully fetch the hardware reset completion 14376988eb2aSSalil Mehta * status from the hardware 14386988eb2aSSalil Mehta */ 14396988eb2aSSalil Mehta ret = hclgevf_reset_wait(hdev); 14406988eb2aSSalil Mehta if (ret) { 14416988eb2aSSalil Mehta /* can't do much in this situation, will disable VF */ 14426988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, 14436988eb2aSSalil Mehta "VF failed(=%d) to fetch H/W reset completion status\n", 14446988eb2aSSalil Mehta ret); 14456a5f6fa3SHuazhong Tan goto err_reset; 14466988eb2aSSalil Mehta } 14476988eb2aSSalil Mehta 144829118ab9SHuazhong Tan rtnl_lock(); 144929118ab9SHuazhong Tan 14506988eb2aSSalil Mehta /* now, re-initialize the nic client and ae device*/ 14516988eb2aSSalil Mehta ret = hclgevf_reset_stack(hdev); 14526a5f6fa3SHuazhong Tan if (ret) { 14536988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 14546a5f6fa3SHuazhong Tan goto err_reset_lock; 14556a5f6fa3SHuazhong Tan } 14566988eb2aSSalil Mehta 14576988eb2aSSalil Mehta /* bring up the nic to enable TX/RX again */ 14586a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 14596a5f6fa3SHuazhong Tan if (ret) 14606a5f6fa3SHuazhong Tan goto err_reset_lock; 14616988eb2aSSalil Mehta 14626988eb2aSSalil Mehta rtnl_unlock(); 14636988eb2aSSalil Mehta 1464b644a8d4SHuazhong Tan hdev->last_reset_time = jiffies; 1465b644a8d4SHuazhong Tan ae_dev->reset_type = HNAE3_NONE_RESET; 1466b644a8d4SHuazhong Tan 14676988eb2aSSalil Mehta return ret; 14686a5f6fa3SHuazhong Tan err_reset_lock: 14696a5f6fa3SHuazhong Tan rtnl_unlock(); 14706a5f6fa3SHuazhong Tan err_reset: 14716a5f6fa3SHuazhong Tan /* When VF reset failed, only the higher level reset asserted by PF 14726a5f6fa3SHuazhong Tan * can restore it, so re-initialize the command queue to receive 14736a5f6fa3SHuazhong Tan * this higher reset event. 14746a5f6fa3SHuazhong Tan */ 14756a5f6fa3SHuazhong Tan hclgevf_cmd_init(hdev); 14766a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "failed to reset VF\n"); 14776a5f6fa3SHuazhong Tan 14786a5f6fa3SHuazhong Tan return ret; 14796988eb2aSSalil Mehta } 14806988eb2aSSalil Mehta 1481720bd583SHuazhong Tan static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1482720bd583SHuazhong Tan unsigned long *addr) 1483720bd583SHuazhong Tan { 1484720bd583SHuazhong Tan enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1485720bd583SHuazhong Tan 1486dea846e8SHuazhong Tan /* return the highest priority reset level amongst all */ 1487b90fcc5bSHuazhong Tan if (test_bit(HNAE3_VF_RESET, addr)) { 1488b90fcc5bSHuazhong Tan rst_level = HNAE3_VF_RESET; 1489b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_RESET, addr); 1490b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1491b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1492b90fcc5bSHuazhong Tan } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1493dea846e8SHuazhong Tan rst_level = HNAE3_VF_FULL_RESET; 1494dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FULL_RESET, addr); 1495dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1496aa5c4f17SHuazhong Tan } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1497aa5c4f17SHuazhong Tan rst_level = HNAE3_VF_PF_FUNC_RESET; 1498aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1499aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1500dea846e8SHuazhong Tan } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1501dea846e8SHuazhong Tan rst_level = HNAE3_VF_FUNC_RESET; 1502dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 15036ff3cf07SHuazhong Tan } else if (test_bit(HNAE3_FLR_RESET, addr)) { 15046ff3cf07SHuazhong Tan rst_level = HNAE3_FLR_RESET; 15056ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_RESET, addr); 1506720bd583SHuazhong Tan } 1507720bd583SHuazhong Tan 1508720bd583SHuazhong Tan return rst_level; 1509720bd583SHuazhong Tan } 1510720bd583SHuazhong Tan 15116ae4e733SShiju Jose static void hclgevf_reset_event(struct pci_dev *pdev, 15126ae4e733SShiju Jose struct hnae3_handle *handle) 15136d4c3981SSalil Mehta { 15146ff3cf07SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 15156ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 15166d4c3981SSalil Mehta 15176d4c3981SSalil Mehta dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 15186d4c3981SSalil Mehta 15196ff3cf07SHuazhong Tan if (hdev->default_reset_request) 15200742ed7cSHuazhong Tan hdev->reset_level = 1521720bd583SHuazhong Tan hclgevf_get_reset_level(hdev, 1522720bd583SHuazhong Tan &hdev->default_reset_request); 1523720bd583SHuazhong Tan else 1524dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 15256d4c3981SSalil Mehta 1526436667d2SSalil Mehta /* reset of this VF requested */ 1527436667d2SSalil Mehta set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1528436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 15296d4c3981SSalil Mehta 15300742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 15316d4c3981SSalil Mehta } 15326d4c3981SSalil Mehta 1533720bd583SHuazhong Tan static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1534720bd583SHuazhong Tan enum hnae3_reset_type rst_type) 1535720bd583SHuazhong Tan { 1536720bd583SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1537720bd583SHuazhong Tan 1538720bd583SHuazhong Tan set_bit(rst_type, &hdev->default_reset_request); 1539720bd583SHuazhong Tan } 1540720bd583SHuazhong Tan 15416ff3cf07SHuazhong Tan static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 15426ff3cf07SHuazhong Tan { 15436ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_MS 100 15446ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_CNT 50 15456ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 15466ff3cf07SHuazhong Tan int cnt = 0; 15476ff3cf07SHuazhong Tan 15486ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 15496ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DONE, &hdev->flr_state); 15506ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request); 15516ff3cf07SHuazhong Tan hclgevf_reset_event(hdev->pdev, NULL); 15526ff3cf07SHuazhong Tan 15536ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) && 15546ff3cf07SHuazhong Tan cnt++ < HCLGEVF_FLR_WAIT_CNT) 15556ff3cf07SHuazhong Tan msleep(HCLGEVF_FLR_WAIT_MS); 15566ff3cf07SHuazhong Tan 15576ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state)) 15586ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 15596ff3cf07SHuazhong Tan "flr wait down timeout: %d\n", cnt); 15606ff3cf07SHuazhong Tan } 15616ff3cf07SHuazhong Tan 1562e2cb1decSSalil Mehta static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1563e2cb1decSSalil Mehta { 1564e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1565e2cb1decSSalil Mehta 1566e2cb1decSSalil Mehta return hdev->fw_version; 1567e2cb1decSSalil Mehta } 1568e2cb1decSSalil Mehta 1569e2cb1decSSalil Mehta static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1570e2cb1decSSalil Mehta { 1571e2cb1decSSalil Mehta struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1572e2cb1decSSalil Mehta 1573e2cb1decSSalil Mehta vector->vector_irq = pci_irq_vector(hdev->pdev, 1574e2cb1decSSalil Mehta HCLGEVF_MISC_VECTOR_NUM); 1575e2cb1decSSalil Mehta vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1576e2cb1decSSalil Mehta /* vector status always valid for Vector 0 */ 1577e2cb1decSSalil Mehta hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1578e2cb1decSSalil Mehta hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1579e2cb1decSSalil Mehta 1580e2cb1decSSalil Mehta hdev->num_msi_left -= 1; 1581e2cb1decSSalil Mehta hdev->num_msi_used += 1; 1582e2cb1decSSalil Mehta } 1583e2cb1decSSalil Mehta 158435a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 158535a1e503SSalil Mehta { 158635a1e503SSalil Mehta if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) && 158735a1e503SSalil Mehta !test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) { 158835a1e503SSalil Mehta set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 158935a1e503SSalil Mehta schedule_work(&hdev->rst_service_task); 159035a1e503SSalil Mehta } 159135a1e503SSalil Mehta } 159235a1e503SSalil Mehta 159307a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1594e2cb1decSSalil Mehta { 159507a0556aSSalil Mehta if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) && 159607a0556aSSalil Mehta !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) { 159707a0556aSSalil Mehta set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1598e2cb1decSSalil Mehta schedule_work(&hdev->mbx_service_task); 1599e2cb1decSSalil Mehta } 160007a0556aSSalil Mehta } 1601e2cb1decSSalil Mehta 1602e2cb1decSSalil Mehta static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 1603e2cb1decSSalil Mehta { 1604e2cb1decSSalil Mehta if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 1605e2cb1decSSalil Mehta !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 1606e2cb1decSSalil Mehta schedule_work(&hdev->service_task); 1607e2cb1decSSalil Mehta } 1608e2cb1decSSalil Mehta 1609436667d2SSalil Mehta static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev) 1610436667d2SSalil Mehta { 161107a0556aSSalil Mehta /* if we have any pending mailbox event then schedule the mbx task */ 161207a0556aSSalil Mehta if (hdev->mbx_event_pending) 161307a0556aSSalil Mehta hclgevf_mbx_task_schedule(hdev); 161407a0556aSSalil Mehta 1615436667d2SSalil Mehta if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state)) 1616436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 1617436667d2SSalil Mehta } 1618436667d2SSalil Mehta 1619e2cb1decSSalil Mehta static void hclgevf_service_timer(struct timer_list *t) 1620e2cb1decSSalil Mehta { 1621e2cb1decSSalil Mehta struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 1622e2cb1decSSalil Mehta 1623e2cb1decSSalil Mehta mod_timer(&hdev->service_timer, jiffies + 5 * HZ); 1624e2cb1decSSalil Mehta 1625e2cb1decSSalil Mehta hclgevf_task_schedule(hdev); 1626e2cb1decSSalil Mehta } 1627e2cb1decSSalil Mehta 162835a1e503SSalil Mehta static void hclgevf_reset_service_task(struct work_struct *work) 162935a1e503SSalil Mehta { 163035a1e503SSalil Mehta struct hclgevf_dev *hdev = 163135a1e503SSalil Mehta container_of(work, struct hclgevf_dev, rst_service_task); 1632a8dedb65SSalil Mehta int ret; 163335a1e503SSalil Mehta 163435a1e503SSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 163535a1e503SSalil Mehta return; 163635a1e503SSalil Mehta 163735a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 163835a1e503SSalil Mehta 1639436667d2SSalil Mehta if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1640436667d2SSalil Mehta &hdev->reset_state)) { 1641436667d2SSalil Mehta /* PF has initmated that it is about to reset the hardware. 1642436667d2SSalil Mehta * We now have to poll & check if harware has actually completed 1643436667d2SSalil Mehta * the reset sequence. On hardware reset completion, VF needs to 1644436667d2SSalil Mehta * reset the client and ae device. 164535a1e503SSalil Mehta */ 1646436667d2SSalil Mehta hdev->reset_attempts = 0; 1647436667d2SSalil Mehta 1648dea846e8SHuazhong Tan hdev->last_reset_time = jiffies; 1649dea846e8SHuazhong Tan while ((hdev->reset_type = 1650dea846e8SHuazhong Tan hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 1651dea846e8SHuazhong Tan != HNAE3_NONE_RESET) { 16526988eb2aSSalil Mehta ret = hclgevf_reset(hdev); 16536988eb2aSSalil Mehta if (ret) 1654dea846e8SHuazhong Tan dev_err(&hdev->pdev->dev, 1655dea846e8SHuazhong Tan "VF stack reset failed %d.\n", ret); 1656dea846e8SHuazhong Tan } 1657436667d2SSalil Mehta } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1658436667d2SSalil Mehta &hdev->reset_state)) { 1659436667d2SSalil Mehta /* we could be here when either of below happens: 1660436667d2SSalil Mehta * 1. reset was initiated due to watchdog timeout due to 1661436667d2SSalil Mehta * a. IMP was earlier reset and our TX got choked down and 1662436667d2SSalil Mehta * which resulted in watchdog reacting and inducing VF 1663436667d2SSalil Mehta * reset. This also means our cmdq would be unreliable. 1664436667d2SSalil Mehta * b. problem in TX due to other lower layer(example link 1665436667d2SSalil Mehta * layer not functioning properly etc.) 1666436667d2SSalil Mehta * 2. VF reset might have been initiated due to some config 1667436667d2SSalil Mehta * change. 1668436667d2SSalil Mehta * 1669436667d2SSalil Mehta * NOTE: Theres no clear way to detect above cases than to react 1670436667d2SSalil Mehta * to the response of PF for this reset request. PF will ack the 1671436667d2SSalil Mehta * 1b and 2. cases but we will not get any intimation about 1a 1672436667d2SSalil Mehta * from PF as cmdq would be in unreliable state i.e. mailbox 1673436667d2SSalil Mehta * communication between PF and VF would be broken. 1674436667d2SSalil Mehta */ 1675436667d2SSalil Mehta 1676436667d2SSalil Mehta /* if we are never geting into pending state it means either: 1677436667d2SSalil Mehta * 1. PF is not receiving our request which could be due to IMP 1678436667d2SSalil Mehta * reset 1679436667d2SSalil Mehta * 2. PF is screwed 1680436667d2SSalil Mehta * We cannot do much for 2. but to check first we can try reset 1681436667d2SSalil Mehta * our PCIe + stack and see if it alleviates the problem. 1682436667d2SSalil Mehta */ 1683436667d2SSalil Mehta if (hdev->reset_attempts > 3) { 1684436667d2SSalil Mehta /* prepare for full reset of stack + pcie interface */ 1685dea846e8SHuazhong Tan set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1686436667d2SSalil Mehta 1687436667d2SSalil Mehta /* "defer" schedule the reset task again */ 1688436667d2SSalil Mehta set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1689436667d2SSalil Mehta } else { 1690436667d2SSalil Mehta hdev->reset_attempts++; 1691436667d2SSalil Mehta 1692dea846e8SHuazhong Tan set_bit(hdev->reset_level, &hdev->reset_pending); 1693dea846e8SHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1694436667d2SSalil Mehta } 1695dea846e8SHuazhong Tan hclgevf_reset_task_schedule(hdev); 1696436667d2SSalil Mehta } 169735a1e503SSalil Mehta 169835a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 169935a1e503SSalil Mehta } 170035a1e503SSalil Mehta 1701e2cb1decSSalil Mehta static void hclgevf_mailbox_service_task(struct work_struct *work) 1702e2cb1decSSalil Mehta { 1703e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1704e2cb1decSSalil Mehta 1705e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 1706e2cb1decSSalil Mehta 1707e2cb1decSSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1708e2cb1decSSalil Mehta return; 1709e2cb1decSSalil Mehta 1710e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1711e2cb1decSSalil Mehta 171207a0556aSSalil Mehta hclgevf_mbx_async_handler(hdev); 1713e2cb1decSSalil Mehta 1714e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1715e2cb1decSSalil Mehta } 1716e2cb1decSSalil Mehta 1717a6d818e3SYunsheng Lin static void hclgevf_keep_alive_timer(struct timer_list *t) 1718a6d818e3SYunsheng Lin { 1719a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = from_timer(hdev, t, keep_alive_timer); 1720a6d818e3SYunsheng Lin 1721a6d818e3SYunsheng Lin schedule_work(&hdev->keep_alive_task); 1722a6d818e3SYunsheng Lin mod_timer(&hdev->keep_alive_timer, jiffies + 2 * HZ); 1723a6d818e3SYunsheng Lin } 1724a6d818e3SYunsheng Lin 1725a6d818e3SYunsheng Lin static void hclgevf_keep_alive_task(struct work_struct *work) 1726a6d818e3SYunsheng Lin { 1727a6d818e3SYunsheng Lin struct hclgevf_dev *hdev; 1728a6d818e3SYunsheng Lin u8 respmsg; 1729a6d818e3SYunsheng Lin int ret; 1730a6d818e3SYunsheng Lin 1731a6d818e3SYunsheng Lin hdev = container_of(work, struct hclgevf_dev, keep_alive_task); 1732c59a85c0SJian Shen 1733c59a85c0SJian Shen if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1734c59a85c0SJian Shen return; 1735c59a85c0SJian Shen 1736a6d818e3SYunsheng Lin ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL, 1737a6d818e3SYunsheng Lin 0, false, &respmsg, sizeof(u8)); 1738a6d818e3SYunsheng Lin if (ret) 1739a6d818e3SYunsheng Lin dev_err(&hdev->pdev->dev, 1740a6d818e3SYunsheng Lin "VF sends keep alive cmd failed(=%d)\n", ret); 1741a6d818e3SYunsheng Lin } 1742a6d818e3SYunsheng Lin 1743e2cb1decSSalil Mehta static void hclgevf_service_task(struct work_struct *work) 1744e2cb1decSSalil Mehta { 1745e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1746e2cb1decSSalil Mehta 1747e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, service_task); 1748e2cb1decSSalil Mehta 1749e2cb1decSSalil Mehta /* request the link status from the PF. PF would be able to tell VF 1750e2cb1decSSalil Mehta * about such updates in future so we might remove this later 1751e2cb1decSSalil Mehta */ 1752e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1753e2cb1decSSalil Mehta 17549194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 17559194d18bSliuzhongzhu 1756436667d2SSalil Mehta hclgevf_deferred_task_schedule(hdev); 1757436667d2SSalil Mehta 1758e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1759e2cb1decSSalil Mehta } 1760e2cb1decSSalil Mehta 1761e2cb1decSSalil Mehta static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1762e2cb1decSSalil Mehta { 1763e2cb1decSSalil Mehta hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1764e2cb1decSSalil Mehta } 1765e2cb1decSSalil Mehta 1766b90fcc5bSHuazhong Tan static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1767b90fcc5bSHuazhong Tan u32 *clearval) 1768e2cb1decSSalil Mehta { 1769b90fcc5bSHuazhong Tan u32 cmdq_src_reg, rst_ing_reg; 1770e2cb1decSSalil Mehta 1771e2cb1decSSalil Mehta /* fetch the events from their corresponding regs */ 1772e2cb1decSSalil Mehta cmdq_src_reg = hclgevf_read_dev(&hdev->hw, 1773e2cb1decSSalil Mehta HCLGEVF_VECTOR0_CMDQ_SRC_REG); 1774e2cb1decSSalil Mehta 1775b90fcc5bSHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_src_reg) { 1776b90fcc5bSHuazhong Tan rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1777b90fcc5bSHuazhong Tan dev_info(&hdev->pdev->dev, 1778b90fcc5bSHuazhong Tan "receive reset interrupt 0x%x!\n", rst_ing_reg); 1779b90fcc5bSHuazhong Tan set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1780b90fcc5bSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1781ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1782b90fcc5bSHuazhong Tan cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RST_INT_B); 1783b90fcc5bSHuazhong Tan *clearval = cmdq_src_reg; 1784b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_RST; 1785b90fcc5bSHuazhong Tan } 1786b90fcc5bSHuazhong Tan 1787e2cb1decSSalil Mehta /* check for vector0 mailbox(=CMDQ RX) event source */ 1788e2cb1decSSalil Mehta if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 1789e2cb1decSSalil Mehta cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1790e2cb1decSSalil Mehta *clearval = cmdq_src_reg; 1791b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_MBX; 1792e2cb1decSSalil Mehta } 1793e2cb1decSSalil Mehta 1794e2cb1decSSalil Mehta dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 1795e2cb1decSSalil Mehta 1796b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_OTHER; 1797e2cb1decSSalil Mehta } 1798e2cb1decSSalil Mehta 1799e2cb1decSSalil Mehta static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1800e2cb1decSSalil Mehta { 1801e2cb1decSSalil Mehta writel(en ? 1 : 0, vector->addr); 1802e2cb1decSSalil Mehta } 1803e2cb1decSSalil Mehta 1804e2cb1decSSalil Mehta static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1805e2cb1decSSalil Mehta { 1806b90fcc5bSHuazhong Tan enum hclgevf_evt_cause event_cause; 1807e2cb1decSSalil Mehta struct hclgevf_dev *hdev = data; 1808e2cb1decSSalil Mehta u32 clearval; 1809e2cb1decSSalil Mehta 1810e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 1811b90fcc5bSHuazhong Tan event_cause = hclgevf_check_evt_cause(hdev, &clearval); 1812e2cb1decSSalil Mehta 1813b90fcc5bSHuazhong Tan switch (event_cause) { 1814b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_RST: 1815b90fcc5bSHuazhong Tan hclgevf_reset_task_schedule(hdev); 1816b90fcc5bSHuazhong Tan break; 1817b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_MBX: 181807a0556aSSalil Mehta hclgevf_mbx_handler(hdev); 1819b90fcc5bSHuazhong Tan break; 1820b90fcc5bSHuazhong Tan default: 1821b90fcc5bSHuazhong Tan break; 1822b90fcc5bSHuazhong Tan } 1823e2cb1decSSalil Mehta 1824b90fcc5bSHuazhong Tan if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 1825e2cb1decSSalil Mehta hclgevf_clear_event_cause(hdev, clearval); 1826e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 1827b90fcc5bSHuazhong Tan } 1828e2cb1decSSalil Mehta 1829e2cb1decSSalil Mehta return IRQ_HANDLED; 1830e2cb1decSSalil Mehta } 1831e2cb1decSSalil Mehta 1832e2cb1decSSalil Mehta static int hclgevf_configure(struct hclgevf_dev *hdev) 1833e2cb1decSSalil Mehta { 1834e2cb1decSSalil Mehta int ret; 1835e2cb1decSSalil Mehta 1836e2cb1decSSalil Mehta /* get queue configuration from PF */ 18376cee6fc3SJian Shen ret = hclgevf_get_queue_info(hdev); 1838e2cb1decSSalil Mehta if (ret) 1839e2cb1decSSalil Mehta return ret; 1840c0425944SPeng Li 1841c0425944SPeng Li /* get queue depth info from PF */ 1842c0425944SPeng Li ret = hclgevf_get_queue_depth(hdev); 1843c0425944SPeng Li if (ret) 1844c0425944SPeng Li return ret; 1845c0425944SPeng Li 18469c3e7130Sliuzhongzhu ret = hclgevf_get_pf_media_type(hdev); 18479c3e7130Sliuzhongzhu if (ret) 18489c3e7130Sliuzhongzhu return ret; 18499c3e7130Sliuzhongzhu 1850e2cb1decSSalil Mehta /* get tc configuration from PF */ 1851e2cb1decSSalil Mehta return hclgevf_get_tc_info(hdev); 1852e2cb1decSSalil Mehta } 1853e2cb1decSSalil Mehta 18547a01c897SSalil Mehta static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 18557a01c897SSalil Mehta { 18567a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 18571154bb26SPeng Li struct hclgevf_dev *hdev; 18587a01c897SSalil Mehta 18597a01c897SSalil Mehta hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 18607a01c897SSalil Mehta if (!hdev) 18617a01c897SSalil Mehta return -ENOMEM; 18627a01c897SSalil Mehta 18637a01c897SSalil Mehta hdev->pdev = pdev; 18647a01c897SSalil Mehta hdev->ae_dev = ae_dev; 18657a01c897SSalil Mehta ae_dev->priv = hdev; 18667a01c897SSalil Mehta 18677a01c897SSalil Mehta return 0; 18687a01c897SSalil Mehta } 18697a01c897SSalil Mehta 1870e2cb1decSSalil Mehta static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 1871e2cb1decSSalil Mehta { 1872e2cb1decSSalil Mehta struct hnae3_handle *roce = &hdev->roce; 1873e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 1874e2cb1decSSalil Mehta 187507acf909SJian Shen roce->rinfo.num_vectors = hdev->num_roce_msix; 1876e2cb1decSSalil Mehta 1877e2cb1decSSalil Mehta if (hdev->num_msi_left < roce->rinfo.num_vectors || 1878e2cb1decSSalil Mehta hdev->num_msi_left == 0) 1879e2cb1decSSalil Mehta return -EINVAL; 1880e2cb1decSSalil Mehta 188107acf909SJian Shen roce->rinfo.base_vector = hdev->roce_base_vector; 1882e2cb1decSSalil Mehta 1883e2cb1decSSalil Mehta roce->rinfo.netdev = nic->kinfo.netdev; 1884e2cb1decSSalil Mehta roce->rinfo.roce_io_base = hdev->hw.io_base; 1885e2cb1decSSalil Mehta 1886e2cb1decSSalil Mehta roce->pdev = nic->pdev; 1887e2cb1decSSalil Mehta roce->ae_algo = nic->ae_algo; 1888e2cb1decSSalil Mehta roce->numa_node_mask = nic->numa_node_mask; 1889e2cb1decSSalil Mehta 1890e2cb1decSSalil Mehta return 0; 1891e2cb1decSSalil Mehta } 1892e2cb1decSSalil Mehta 1893b26a6feaSPeng Li static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 1894b26a6feaSPeng Li { 1895b26a6feaSPeng Li struct hclgevf_cfg_gro_status_cmd *req; 1896b26a6feaSPeng Li struct hclgevf_desc desc; 1897b26a6feaSPeng Li int ret; 1898b26a6feaSPeng Li 1899b26a6feaSPeng Li if (!hnae3_dev_gro_supported(hdev)) 1900b26a6feaSPeng Li return 0; 1901b26a6feaSPeng Li 1902b26a6feaSPeng Li hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 1903b26a6feaSPeng Li false); 1904b26a6feaSPeng Li req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 1905b26a6feaSPeng Li 1906b26a6feaSPeng Li req->gro_en = cpu_to_le16(en ? 1 : 0); 1907b26a6feaSPeng Li 1908b26a6feaSPeng Li ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1909b26a6feaSPeng Li if (ret) 1910b26a6feaSPeng Li dev_err(&hdev->pdev->dev, 1911b26a6feaSPeng Li "VF GRO hardware config cmd failed, ret = %d.\n", ret); 1912b26a6feaSPeng Li 1913b26a6feaSPeng Li return ret; 1914b26a6feaSPeng Li } 1915b26a6feaSPeng Li 1916e2cb1decSSalil Mehta static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 1917e2cb1decSSalil Mehta { 1918e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1919e2cb1decSSalil Mehta int i, ret; 1920e2cb1decSSalil Mehta 1921e2cb1decSSalil Mehta rss_cfg->rss_size = hdev->rss_size_max; 1922e2cb1decSSalil Mehta 1923374ad291SJian Shen if (hdev->pdev->revision >= 0x21) { 1924472d7eceSJian Shen rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 1925472d7eceSJian Shen memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 1926374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 1927374ad291SJian Shen 1928374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 1929374ad291SJian Shen rss_cfg->rss_hash_key); 1930374ad291SJian Shen if (ret) 1931374ad291SJian Shen return ret; 1932d97b3072SJian Shen 1933d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = 1934d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1935d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = 1936d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1937d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = 1938d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1939d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = 1940d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1941d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = 1942d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1943d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = 1944d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1945d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = 1946d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1947d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = 1948d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1949d97b3072SJian Shen 1950d97b3072SJian Shen ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 1951d97b3072SJian Shen if (ret) 1952d97b3072SJian Shen return ret; 1953d97b3072SJian Shen 1954374ad291SJian Shen } 1955374ad291SJian Shen 1956e2cb1decSSalil Mehta /* Initialize RSS indirect table for each vport */ 1957e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 1958e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max; 1959e2cb1decSSalil Mehta 1960e2cb1decSSalil Mehta ret = hclgevf_set_rss_indir_table(hdev); 1961e2cb1decSSalil Mehta if (ret) 1962e2cb1decSSalil Mehta return ret; 1963e2cb1decSSalil Mehta 1964e2cb1decSSalil Mehta return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max); 1965e2cb1decSSalil Mehta } 1966e2cb1decSSalil Mehta 1967e2cb1decSSalil Mehta static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 1968e2cb1decSSalil Mehta { 1969e2cb1decSSalil Mehta /* other vlan config(like, VLAN TX/RX offload) would also be added 1970e2cb1decSSalil Mehta * here later 1971e2cb1decSSalil Mehta */ 1972e2cb1decSSalil Mehta return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 1973e2cb1decSSalil Mehta false); 1974e2cb1decSSalil Mehta } 1975e2cb1decSSalil Mehta 19768cdb992fSJian Shen static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 19778cdb992fSJian Shen { 19788cdb992fSJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 19798cdb992fSJian Shen 19808cdb992fSJian Shen if (enable) { 19818cdb992fSJian Shen mod_timer(&hdev->service_timer, jiffies + HZ); 19828cdb992fSJian Shen } else { 19838cdb992fSJian Shen del_timer_sync(&hdev->service_timer); 19848cdb992fSJian Shen cancel_work_sync(&hdev->service_task); 19858cdb992fSJian Shen clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 19868cdb992fSJian Shen } 19878cdb992fSJian Shen } 19888cdb992fSJian Shen 1989e2cb1decSSalil Mehta static int hclgevf_ae_start(struct hnae3_handle *handle) 1990e2cb1decSSalil Mehta { 1991e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1992e2cb1decSSalil Mehta 1993e2cb1decSSalil Mehta /* reset tqp stats */ 1994e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 1995e2cb1decSSalil Mehta 1996e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1997e2cb1decSSalil Mehta 19989194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 19999194d18bSliuzhongzhu 2000e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2001e2cb1decSSalil Mehta 2002e2cb1decSSalil Mehta return 0; 2003e2cb1decSSalil Mehta } 2004e2cb1decSSalil Mehta 2005e2cb1decSSalil Mehta static void hclgevf_ae_stop(struct hnae3_handle *handle) 2006e2cb1decSSalil Mehta { 2007e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 200839cfbc9cSHuazhong Tan int i; 2009e2cb1decSSalil Mehta 20102f7e4896SFuyun Liang set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 20112f7e4896SFuyun Liang 201239cfbc9cSHuazhong Tan for (i = 0; i < handle->kinfo.num_tqps; i++) 201339cfbc9cSHuazhong Tan hclgevf_reset_tqp(handle, i); 201439cfbc9cSHuazhong Tan 2015e2cb1decSSalil Mehta /* reset tqp stats */ 2016e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 20178cc6c1f7SFuyun Liang hclgevf_update_link_status(hdev, 0); 2018e2cb1decSSalil Mehta } 2019e2cb1decSSalil Mehta 2020a6d818e3SYunsheng Lin static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2021a6d818e3SYunsheng Lin { 2022a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2023a6d818e3SYunsheng Lin u8 msg_data; 2024a6d818e3SYunsheng Lin 2025a6d818e3SYunsheng Lin msg_data = alive ? 1 : 0; 2026a6d818e3SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE, 2027a6d818e3SYunsheng Lin 0, &msg_data, 1, false, NULL, 0); 2028a6d818e3SYunsheng Lin } 2029a6d818e3SYunsheng Lin 2030a6d818e3SYunsheng Lin static int hclgevf_client_start(struct hnae3_handle *handle) 2031a6d818e3SYunsheng Lin { 2032a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2033a6d818e3SYunsheng Lin 2034a6d818e3SYunsheng Lin mod_timer(&hdev->keep_alive_timer, jiffies + 2 * HZ); 2035a6d818e3SYunsheng Lin return hclgevf_set_alive(handle, true); 2036a6d818e3SYunsheng Lin } 2037a6d818e3SYunsheng Lin 2038a6d818e3SYunsheng Lin static void hclgevf_client_stop(struct hnae3_handle *handle) 2039a6d818e3SYunsheng Lin { 2040a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2041a6d818e3SYunsheng Lin int ret; 2042a6d818e3SYunsheng Lin 2043a6d818e3SYunsheng Lin ret = hclgevf_set_alive(handle, false); 2044a6d818e3SYunsheng Lin if (ret) 2045a6d818e3SYunsheng Lin dev_warn(&hdev->pdev->dev, 2046a6d818e3SYunsheng Lin "%s failed %d\n", __func__, ret); 2047a6d818e3SYunsheng Lin 2048a6d818e3SYunsheng Lin del_timer_sync(&hdev->keep_alive_timer); 2049a6d818e3SYunsheng Lin cancel_work_sync(&hdev->keep_alive_task); 2050a6d818e3SYunsheng Lin } 2051a6d818e3SYunsheng Lin 2052e2cb1decSSalil Mehta static void hclgevf_state_init(struct hclgevf_dev *hdev) 2053e2cb1decSSalil Mehta { 2054e2cb1decSSalil Mehta /* setup tasks for the MBX */ 2055e2cb1decSSalil Mehta INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 2056e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2057e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2058e2cb1decSSalil Mehta 2059e2cb1decSSalil Mehta /* setup tasks for service timer */ 2060e2cb1decSSalil Mehta timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 2061e2cb1decSSalil Mehta 2062e2cb1decSSalil Mehta INIT_WORK(&hdev->service_task, hclgevf_service_task); 2063e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2064e2cb1decSSalil Mehta 206535a1e503SSalil Mehta INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task); 206635a1e503SSalil Mehta 2067e2cb1decSSalil Mehta mutex_init(&hdev->mbx_resp.mbx_mutex); 2068e2cb1decSSalil Mehta 2069e2cb1decSSalil Mehta /* bring the device down */ 2070e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2071e2cb1decSSalil Mehta } 2072e2cb1decSSalil Mehta 2073e2cb1decSSalil Mehta static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2074e2cb1decSSalil Mehta { 2075e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2076e2cb1decSSalil Mehta 2077e2cb1decSSalil Mehta if (hdev->service_timer.function) 2078e2cb1decSSalil Mehta del_timer_sync(&hdev->service_timer); 2079e2cb1decSSalil Mehta if (hdev->service_task.func) 2080e2cb1decSSalil Mehta cancel_work_sync(&hdev->service_task); 2081e2cb1decSSalil Mehta if (hdev->mbx_service_task.func) 2082e2cb1decSSalil Mehta cancel_work_sync(&hdev->mbx_service_task); 208335a1e503SSalil Mehta if (hdev->rst_service_task.func) 208435a1e503SSalil Mehta cancel_work_sync(&hdev->rst_service_task); 2085e2cb1decSSalil Mehta 2086e2cb1decSSalil Mehta mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2087e2cb1decSSalil Mehta } 2088e2cb1decSSalil Mehta 2089e2cb1decSSalil Mehta static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2090e2cb1decSSalil Mehta { 2091e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2092e2cb1decSSalil Mehta int vectors; 2093e2cb1decSSalil Mehta int i; 2094e2cb1decSSalil Mehta 209507acf909SJian Shen if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) 209607acf909SJian Shen vectors = pci_alloc_irq_vectors(pdev, 209707acf909SJian Shen hdev->roce_base_msix_offset + 1, 209807acf909SJian Shen hdev->num_msi, 209907acf909SJian Shen PCI_IRQ_MSIX); 210007acf909SJian Shen else 2101e2cb1decSSalil Mehta vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 2102e2cb1decSSalil Mehta PCI_IRQ_MSI | PCI_IRQ_MSIX); 210307acf909SJian Shen 2104e2cb1decSSalil Mehta if (vectors < 0) { 2105e2cb1decSSalil Mehta dev_err(&pdev->dev, 2106e2cb1decSSalil Mehta "failed(%d) to allocate MSI/MSI-X vectors\n", 2107e2cb1decSSalil Mehta vectors); 2108e2cb1decSSalil Mehta return vectors; 2109e2cb1decSSalil Mehta } 2110e2cb1decSSalil Mehta if (vectors < hdev->num_msi) 2111e2cb1decSSalil Mehta dev_warn(&hdev->pdev->dev, 2112e2cb1decSSalil Mehta "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2113e2cb1decSSalil Mehta hdev->num_msi, vectors); 2114e2cb1decSSalil Mehta 2115e2cb1decSSalil Mehta hdev->num_msi = vectors; 2116e2cb1decSSalil Mehta hdev->num_msi_left = vectors; 2117e2cb1decSSalil Mehta hdev->base_msi_vector = pdev->irq; 211807acf909SJian Shen hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2119e2cb1decSSalil Mehta 2120e2cb1decSSalil Mehta hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2121e2cb1decSSalil Mehta sizeof(u16), GFP_KERNEL); 2122e2cb1decSSalil Mehta if (!hdev->vector_status) { 2123e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2124e2cb1decSSalil Mehta return -ENOMEM; 2125e2cb1decSSalil Mehta } 2126e2cb1decSSalil Mehta 2127e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 2128e2cb1decSSalil Mehta hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2129e2cb1decSSalil Mehta 2130e2cb1decSSalil Mehta hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2131e2cb1decSSalil Mehta sizeof(int), GFP_KERNEL); 2132e2cb1decSSalil Mehta if (!hdev->vector_irq) { 2133862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2134e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2135e2cb1decSSalil Mehta return -ENOMEM; 2136e2cb1decSSalil Mehta } 2137e2cb1decSSalil Mehta 2138e2cb1decSSalil Mehta return 0; 2139e2cb1decSSalil Mehta } 2140e2cb1decSSalil Mehta 2141e2cb1decSSalil Mehta static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2142e2cb1decSSalil Mehta { 2143e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2144e2cb1decSSalil Mehta 2145862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2146862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_irq); 2147e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2148e2cb1decSSalil Mehta } 2149e2cb1decSSalil Mehta 2150e2cb1decSSalil Mehta static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2151e2cb1decSSalil Mehta { 2152e2cb1decSSalil Mehta int ret = 0; 2153e2cb1decSSalil Mehta 2154e2cb1decSSalil Mehta hclgevf_get_misc_vector(hdev); 2155e2cb1decSSalil Mehta 2156e2cb1decSSalil Mehta ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2157e2cb1decSSalil Mehta 0, "hclgevf_cmd", hdev); 2158e2cb1decSSalil Mehta if (ret) { 2159e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2160e2cb1decSSalil Mehta hdev->misc_vector.vector_irq); 2161e2cb1decSSalil Mehta return ret; 2162e2cb1decSSalil Mehta } 2163e2cb1decSSalil Mehta 21641819e409SXi Wang hclgevf_clear_event_cause(hdev, 0); 21651819e409SXi Wang 2166e2cb1decSSalil Mehta /* enable misc. vector(vector 0) */ 2167e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2168e2cb1decSSalil Mehta 2169e2cb1decSSalil Mehta return ret; 2170e2cb1decSSalil Mehta } 2171e2cb1decSSalil Mehta 2172e2cb1decSSalil Mehta static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2173e2cb1decSSalil Mehta { 2174e2cb1decSSalil Mehta /* disable misc vector(vector 0) */ 2175e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 21761819e409SXi Wang synchronize_irq(hdev->misc_vector.vector_irq); 2177e2cb1decSSalil Mehta free_irq(hdev->misc_vector.vector_irq, hdev); 2178e2cb1decSSalil Mehta hclgevf_free_vector(hdev, 0); 2179e2cb1decSSalil Mehta } 2180e2cb1decSSalil Mehta 2181e718a93fSPeng Li static int hclgevf_init_client_instance(struct hnae3_client *client, 2182e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2183e2cb1decSSalil Mehta { 2184e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2185e2cb1decSSalil Mehta int ret; 2186e2cb1decSSalil Mehta 2187e2cb1decSSalil Mehta switch (client->type) { 2188e2cb1decSSalil Mehta case HNAE3_CLIENT_KNIC: 2189e2cb1decSSalil Mehta hdev->nic_client = client; 2190e2cb1decSSalil Mehta hdev->nic.client = client; 2191e2cb1decSSalil Mehta 2192e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->nic); 2193e2cb1decSSalil Mehta if (ret) 219449dd8054SJian Shen goto clear_nic; 2195e2cb1decSSalil Mehta 2196d9f28fc2SJian Shen hnae3_set_client_init_flag(client, ae_dev, 1); 2197d9f28fc2SJian Shen 2198e2cb1decSSalil Mehta if (hdev->roce_client && hnae3_dev_roce_supported(hdev)) { 2199e2cb1decSSalil Mehta struct hnae3_client *rc = hdev->roce_client; 2200e2cb1decSSalil Mehta 2201e2cb1decSSalil Mehta ret = hclgevf_init_roce_base_info(hdev); 2202e2cb1decSSalil Mehta if (ret) 220349dd8054SJian Shen goto clear_roce; 2204e2cb1decSSalil Mehta ret = rc->ops->init_instance(&hdev->roce); 2205e2cb1decSSalil Mehta if (ret) 220649dd8054SJian Shen goto clear_roce; 2207d9f28fc2SJian Shen 2208d9f28fc2SJian Shen hnae3_set_client_init_flag(hdev->roce_client, ae_dev, 2209d9f28fc2SJian Shen 1); 2210e2cb1decSSalil Mehta } 2211e2cb1decSSalil Mehta break; 2212e2cb1decSSalil Mehta case HNAE3_CLIENT_UNIC: 2213e2cb1decSSalil Mehta hdev->nic_client = client; 2214e2cb1decSSalil Mehta hdev->nic.client = client; 2215e2cb1decSSalil Mehta 2216e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->nic); 2217e2cb1decSSalil Mehta if (ret) 221849dd8054SJian Shen goto clear_nic; 2219d9f28fc2SJian Shen 2220d9f28fc2SJian Shen hnae3_set_client_init_flag(client, ae_dev, 1); 2221e2cb1decSSalil Mehta break; 2222e2cb1decSSalil Mehta case HNAE3_CLIENT_ROCE: 2223544a7bcdSLijun Ou if (hnae3_dev_roce_supported(hdev)) { 2224e2cb1decSSalil Mehta hdev->roce_client = client; 2225e2cb1decSSalil Mehta hdev->roce.client = client; 2226544a7bcdSLijun Ou } 2227e2cb1decSSalil Mehta 2228544a7bcdSLijun Ou if (hdev->roce_client && hdev->nic_client) { 2229e2cb1decSSalil Mehta ret = hclgevf_init_roce_base_info(hdev); 2230e2cb1decSSalil Mehta if (ret) 223149dd8054SJian Shen goto clear_roce; 2232e2cb1decSSalil Mehta 2233e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->roce); 2234e2cb1decSSalil Mehta if (ret) 223549dd8054SJian Shen goto clear_roce; 2236e2cb1decSSalil Mehta } 2237d9f28fc2SJian Shen 2238d9f28fc2SJian Shen hnae3_set_client_init_flag(client, ae_dev, 1); 2239fa7a4bd5SJian Shen break; 2240fa7a4bd5SJian Shen default: 2241fa7a4bd5SJian Shen return -EINVAL; 2242e2cb1decSSalil Mehta } 2243e2cb1decSSalil Mehta 2244e2cb1decSSalil Mehta return 0; 224549dd8054SJian Shen 224649dd8054SJian Shen clear_nic: 224749dd8054SJian Shen hdev->nic_client = NULL; 224849dd8054SJian Shen hdev->nic.client = NULL; 224949dd8054SJian Shen return ret; 225049dd8054SJian Shen clear_roce: 225149dd8054SJian Shen hdev->roce_client = NULL; 225249dd8054SJian Shen hdev->roce.client = NULL; 225349dd8054SJian Shen return ret; 2254e2cb1decSSalil Mehta } 2255e2cb1decSSalil Mehta 2256e718a93fSPeng Li static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2257e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2258e2cb1decSSalil Mehta { 2259e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2260e718a93fSPeng Li 2261e2cb1decSSalil Mehta /* un-init roce, if it exists */ 226249dd8054SJian Shen if (hdev->roce_client) { 2263e2cb1decSSalil Mehta hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 226449dd8054SJian Shen hdev->roce_client = NULL; 226549dd8054SJian Shen hdev->roce.client = NULL; 226649dd8054SJian Shen } 2267e2cb1decSSalil Mehta 2268e2cb1decSSalil Mehta /* un-init nic/unic, if this was not called by roce client */ 226949dd8054SJian Shen if (client->ops->uninit_instance && hdev->nic_client && 227049dd8054SJian Shen client->type != HNAE3_CLIENT_ROCE) { 2271e2cb1decSSalil Mehta client->ops->uninit_instance(&hdev->nic, 0); 227249dd8054SJian Shen hdev->nic_client = NULL; 227349dd8054SJian Shen hdev->nic.client = NULL; 227449dd8054SJian Shen } 2275e2cb1decSSalil Mehta } 2276e2cb1decSSalil Mehta 2277e2cb1decSSalil Mehta static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2278e2cb1decSSalil Mehta { 2279e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2280e2cb1decSSalil Mehta struct hclgevf_hw *hw; 2281e2cb1decSSalil Mehta int ret; 2282e2cb1decSSalil Mehta 2283e2cb1decSSalil Mehta ret = pci_enable_device(pdev); 2284e2cb1decSSalil Mehta if (ret) { 2285e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed to enable PCI device\n"); 22863e249d3bSFuyun Liang return ret; 2287e2cb1decSSalil Mehta } 2288e2cb1decSSalil Mehta 2289e2cb1decSSalil Mehta ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2290e2cb1decSSalil Mehta if (ret) { 2291e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2292e2cb1decSSalil Mehta goto err_disable_device; 2293e2cb1decSSalil Mehta } 2294e2cb1decSSalil Mehta 2295e2cb1decSSalil Mehta ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2296e2cb1decSSalil Mehta if (ret) { 2297e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2298e2cb1decSSalil Mehta goto err_disable_device; 2299e2cb1decSSalil Mehta } 2300e2cb1decSSalil Mehta 2301e2cb1decSSalil Mehta pci_set_master(pdev); 2302e2cb1decSSalil Mehta hw = &hdev->hw; 2303e2cb1decSSalil Mehta hw->hdev = hdev; 23042e1ea493SPeng Li hw->io_base = pci_iomap(pdev, 2, 0); 2305e2cb1decSSalil Mehta if (!hw->io_base) { 2306e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't map configuration register space\n"); 2307e2cb1decSSalil Mehta ret = -ENOMEM; 2308e2cb1decSSalil Mehta goto err_clr_master; 2309e2cb1decSSalil Mehta } 2310e2cb1decSSalil Mehta 2311e2cb1decSSalil Mehta return 0; 2312e2cb1decSSalil Mehta 2313e2cb1decSSalil Mehta err_clr_master: 2314e2cb1decSSalil Mehta pci_clear_master(pdev); 2315e2cb1decSSalil Mehta pci_release_regions(pdev); 2316e2cb1decSSalil Mehta err_disable_device: 2317e2cb1decSSalil Mehta pci_disable_device(pdev); 23183e249d3bSFuyun Liang 2319e2cb1decSSalil Mehta return ret; 2320e2cb1decSSalil Mehta } 2321e2cb1decSSalil Mehta 2322e2cb1decSSalil Mehta static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2323e2cb1decSSalil Mehta { 2324e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2325e2cb1decSSalil Mehta 2326e2cb1decSSalil Mehta pci_iounmap(pdev, hdev->hw.io_base); 2327e2cb1decSSalil Mehta pci_clear_master(pdev); 2328e2cb1decSSalil Mehta pci_release_regions(pdev); 2329e2cb1decSSalil Mehta pci_disable_device(pdev); 2330e2cb1decSSalil Mehta } 2331e2cb1decSSalil Mehta 233207acf909SJian Shen static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 233307acf909SJian Shen { 233407acf909SJian Shen struct hclgevf_query_res_cmd *req; 233507acf909SJian Shen struct hclgevf_desc desc; 233607acf909SJian Shen int ret; 233707acf909SJian Shen 233807acf909SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 233907acf909SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 234007acf909SJian Shen if (ret) { 234107acf909SJian Shen dev_err(&hdev->pdev->dev, 234207acf909SJian Shen "query vf resource failed, ret = %d.\n", ret); 234307acf909SJian Shen return ret; 234407acf909SJian Shen } 234507acf909SJian Shen 234607acf909SJian Shen req = (struct hclgevf_query_res_cmd *)desc.data; 234707acf909SJian Shen 234807acf909SJian Shen if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) { 234907acf909SJian Shen hdev->roce_base_msix_offset = 235007acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 235107acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_M, 235207acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_S); 235307acf909SJian Shen hdev->num_roce_msix = 235407acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 235507acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 235607acf909SJian Shen 235707acf909SJian Shen /* VF should have NIC vectors and Roce vectors, NIC vectors 235807acf909SJian Shen * are queued before Roce vectors. The offset is fixed to 64. 235907acf909SJian Shen */ 236007acf909SJian Shen hdev->num_msi = hdev->num_roce_msix + 236107acf909SJian Shen hdev->roce_base_msix_offset; 236207acf909SJian Shen } else { 236307acf909SJian Shen hdev->num_msi = 236407acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 236507acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 236607acf909SJian Shen } 236707acf909SJian Shen 236807acf909SJian Shen return 0; 236907acf909SJian Shen } 237007acf909SJian Shen 2371862d969aSHuazhong Tan static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2372862d969aSHuazhong Tan { 2373862d969aSHuazhong Tan struct pci_dev *pdev = hdev->pdev; 2374862d969aSHuazhong Tan int ret = 0; 2375862d969aSHuazhong Tan 2376862d969aSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2377862d969aSHuazhong Tan test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2378862d969aSHuazhong Tan hclgevf_misc_irq_uninit(hdev); 2379862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2380862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2381862d969aSHuazhong Tan } 2382862d969aSHuazhong Tan 2383862d969aSHuazhong Tan if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2384862d969aSHuazhong Tan pci_set_master(pdev); 2385862d969aSHuazhong Tan ret = hclgevf_init_msi(hdev); 2386862d969aSHuazhong Tan if (ret) { 2387862d969aSHuazhong Tan dev_err(&pdev->dev, 2388862d969aSHuazhong Tan "failed(%d) to init MSI/MSI-X\n", ret); 2389862d969aSHuazhong Tan return ret; 2390862d969aSHuazhong Tan } 2391862d969aSHuazhong Tan 2392862d969aSHuazhong Tan ret = hclgevf_misc_irq_init(hdev); 2393862d969aSHuazhong Tan if (ret) { 2394862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2395862d969aSHuazhong Tan dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2396862d969aSHuazhong Tan ret); 2397862d969aSHuazhong Tan return ret; 2398862d969aSHuazhong Tan } 2399862d969aSHuazhong Tan 2400862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2401862d969aSHuazhong Tan } 2402862d969aSHuazhong Tan 2403862d969aSHuazhong Tan return ret; 2404862d969aSHuazhong Tan } 2405862d969aSHuazhong Tan 24069c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2407e2cb1decSSalil Mehta { 24087a01c897SSalil Mehta struct pci_dev *pdev = hdev->pdev; 2409e2cb1decSSalil Mehta int ret; 2410e2cb1decSSalil Mehta 2411862d969aSHuazhong Tan ret = hclgevf_pci_reset(hdev); 2412862d969aSHuazhong Tan if (ret) { 2413862d969aSHuazhong Tan dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2414862d969aSHuazhong Tan return ret; 2415862d969aSHuazhong Tan } 2416862d969aSHuazhong Tan 24179c6f7085SHuazhong Tan ret = hclgevf_cmd_init(hdev); 24189c6f7085SHuazhong Tan if (ret) { 24199c6f7085SHuazhong Tan dev_err(&pdev->dev, "cmd failed %d\n", ret); 24209c6f7085SHuazhong Tan return ret; 24217a01c897SSalil Mehta } 2422e2cb1decSSalil Mehta 24239c6f7085SHuazhong Tan ret = hclgevf_rss_init_hw(hdev); 24249c6f7085SHuazhong Tan if (ret) { 24259c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 24269c6f7085SHuazhong Tan "failed(%d) to initialize RSS\n", ret); 24279c6f7085SHuazhong Tan return ret; 24289c6f7085SHuazhong Tan } 24299c6f7085SHuazhong Tan 2430b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2431b26a6feaSPeng Li if (ret) 2432b26a6feaSPeng Li return ret; 2433b26a6feaSPeng Li 24349c6f7085SHuazhong Tan ret = hclgevf_init_vlan_config(hdev); 24359c6f7085SHuazhong Tan if (ret) { 24369c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 24379c6f7085SHuazhong Tan "failed(%d) to initialize VLAN config\n", ret); 24389c6f7085SHuazhong Tan return ret; 24399c6f7085SHuazhong Tan } 24409c6f7085SHuazhong Tan 24419c6f7085SHuazhong Tan dev_info(&hdev->pdev->dev, "Reset done\n"); 24429c6f7085SHuazhong Tan 24439c6f7085SHuazhong Tan return 0; 24449c6f7085SHuazhong Tan } 24459c6f7085SHuazhong Tan 24469c6f7085SHuazhong Tan static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 24479c6f7085SHuazhong Tan { 24489c6f7085SHuazhong Tan struct pci_dev *pdev = hdev->pdev; 24499c6f7085SHuazhong Tan int ret; 24509c6f7085SHuazhong Tan 2451e2cb1decSSalil Mehta ret = hclgevf_pci_init(hdev); 2452e2cb1decSSalil Mehta if (ret) { 2453e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI initialization failed\n"); 2454e2cb1decSSalil Mehta return ret; 2455e2cb1decSSalil Mehta } 2456e2cb1decSSalil Mehta 24578b0195a3SHuazhong Tan ret = hclgevf_cmd_queue_init(hdev); 24588b0195a3SHuazhong Tan if (ret) { 24598b0195a3SHuazhong Tan dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret); 24608b0195a3SHuazhong Tan goto err_cmd_queue_init; 24618b0195a3SHuazhong Tan } 24628b0195a3SHuazhong Tan 2463eddf0462SYunsheng Lin ret = hclgevf_cmd_init(hdev); 2464eddf0462SYunsheng Lin if (ret) 2465eddf0462SYunsheng Lin goto err_cmd_init; 2466eddf0462SYunsheng Lin 246707acf909SJian Shen /* Get vf resource */ 246807acf909SJian Shen ret = hclgevf_query_vf_resource(hdev); 246907acf909SJian Shen if (ret) { 247007acf909SJian Shen dev_err(&hdev->pdev->dev, 247107acf909SJian Shen "Query vf status error, ret = %d.\n", ret); 24728b0195a3SHuazhong Tan goto err_cmd_init; 247307acf909SJian Shen } 247407acf909SJian Shen 247507acf909SJian Shen ret = hclgevf_init_msi(hdev); 247607acf909SJian Shen if (ret) { 247707acf909SJian Shen dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 24788b0195a3SHuazhong Tan goto err_cmd_init; 247907acf909SJian Shen } 248007acf909SJian Shen 248107acf909SJian Shen hclgevf_state_init(hdev); 2482dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 248307acf909SJian Shen 2484e2cb1decSSalil Mehta ret = hclgevf_misc_irq_init(hdev); 2485e2cb1decSSalil Mehta if (ret) { 2486e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2487e2cb1decSSalil Mehta ret); 2488e2cb1decSSalil Mehta goto err_misc_irq_init; 2489e2cb1decSSalil Mehta } 2490e2cb1decSSalil Mehta 2491862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2492862d969aSHuazhong Tan 2493e2cb1decSSalil Mehta ret = hclgevf_configure(hdev); 2494e2cb1decSSalil Mehta if (ret) { 2495e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2496e2cb1decSSalil Mehta goto err_config; 2497e2cb1decSSalil Mehta } 2498e2cb1decSSalil Mehta 2499e2cb1decSSalil Mehta ret = hclgevf_alloc_tqps(hdev); 2500e2cb1decSSalil Mehta if (ret) { 2501e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2502e2cb1decSSalil Mehta goto err_config; 2503e2cb1decSSalil Mehta } 2504e2cb1decSSalil Mehta 2505e2cb1decSSalil Mehta ret = hclgevf_set_handle_info(hdev); 2506e2cb1decSSalil Mehta if (ret) { 2507e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 2508e2cb1decSSalil Mehta goto err_config; 2509e2cb1decSSalil Mehta } 2510e2cb1decSSalil Mehta 2511b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2512b26a6feaSPeng Li if (ret) 2513b26a6feaSPeng Li goto err_config; 2514b26a6feaSPeng Li 2515f01f5559SJian Shen /* vf is not allowed to enable unicast/multicast promisc mode. 2516f01f5559SJian Shen * For revision 0x20, default to disable broadcast promisc mode, 2517f01f5559SJian Shen * firmware makes sure broadcast packets can be accepted. 2518f01f5559SJian Shen * For revision 0x21, default to enable broadcast promisc mode. 2519f01f5559SJian Shen */ 2520f01f5559SJian Shen ret = hclgevf_set_promisc_mode(hdev, true); 2521f01f5559SJian Shen if (ret) 2522f01f5559SJian Shen goto err_config; 2523f01f5559SJian Shen 2524e2cb1decSSalil Mehta /* Initialize RSS for this VF */ 2525e2cb1decSSalil Mehta ret = hclgevf_rss_init_hw(hdev); 2526e2cb1decSSalil Mehta if (ret) { 2527e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2528e2cb1decSSalil Mehta "failed(%d) to initialize RSS\n", ret); 2529e2cb1decSSalil Mehta goto err_config; 2530e2cb1decSSalil Mehta } 2531e2cb1decSSalil Mehta 2532e2cb1decSSalil Mehta ret = hclgevf_init_vlan_config(hdev); 2533e2cb1decSSalil Mehta if (ret) { 2534e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2535e2cb1decSSalil Mehta "failed(%d) to initialize VLAN config\n", ret); 2536e2cb1decSSalil Mehta goto err_config; 2537e2cb1decSSalil Mehta } 2538e2cb1decSSalil Mehta 25390742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 2540e2cb1decSSalil Mehta pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME); 2541e2cb1decSSalil Mehta 2542e2cb1decSSalil Mehta return 0; 2543e2cb1decSSalil Mehta 2544e2cb1decSSalil Mehta err_config: 2545e2cb1decSSalil Mehta hclgevf_misc_irq_uninit(hdev); 2546e2cb1decSSalil Mehta err_misc_irq_init: 2547e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2548e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 254907acf909SJian Shen err_cmd_init: 25508b0195a3SHuazhong Tan hclgevf_cmd_uninit(hdev); 25518b0195a3SHuazhong Tan err_cmd_queue_init: 2552e2cb1decSSalil Mehta hclgevf_pci_uninit(hdev); 2553862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2554e2cb1decSSalil Mehta return ret; 2555e2cb1decSSalil Mehta } 2556e2cb1decSSalil Mehta 25577a01c897SSalil Mehta static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2558e2cb1decSSalil Mehta { 2559e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2560862d969aSHuazhong Tan 2561862d969aSHuazhong Tan if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2562eddf0462SYunsheng Lin hclgevf_misc_irq_uninit(hdev); 2563e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 25647a01c897SSalil Mehta } 25657a01c897SSalil Mehta 2566e3338205SHuazhong Tan hclgevf_pci_uninit(hdev); 2567862d969aSHuazhong Tan hclgevf_cmd_uninit(hdev); 2568862d969aSHuazhong Tan } 2569862d969aSHuazhong Tan 25707a01c897SSalil Mehta static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 25717a01c897SSalil Mehta { 25727a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 2573a6d818e3SYunsheng Lin struct hclgevf_dev *hdev; 25747a01c897SSalil Mehta int ret; 25757a01c897SSalil Mehta 25767a01c897SSalil Mehta ret = hclgevf_alloc_hdev(ae_dev); 25777a01c897SSalil Mehta if (ret) { 25787a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device allocation failed\n"); 25797a01c897SSalil Mehta return ret; 25807a01c897SSalil Mehta } 25817a01c897SSalil Mehta 25827a01c897SSalil Mehta ret = hclgevf_init_hdev(ae_dev->priv); 2583a6d818e3SYunsheng Lin if (ret) { 25847a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device initialization failed\n"); 25857a01c897SSalil Mehta return ret; 25867a01c897SSalil Mehta } 25877a01c897SSalil Mehta 2588a6d818e3SYunsheng Lin hdev = ae_dev->priv; 2589a6d818e3SYunsheng Lin timer_setup(&hdev->keep_alive_timer, hclgevf_keep_alive_timer, 0); 2590a6d818e3SYunsheng Lin INIT_WORK(&hdev->keep_alive_task, hclgevf_keep_alive_task); 2591a6d818e3SYunsheng Lin 2592a6d818e3SYunsheng Lin return 0; 2593a6d818e3SYunsheng Lin } 2594a6d818e3SYunsheng Lin 25957a01c897SSalil Mehta static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 25967a01c897SSalil Mehta { 25977a01c897SSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 25987a01c897SSalil Mehta 25997a01c897SSalil Mehta hclgevf_uninit_hdev(hdev); 2600e2cb1decSSalil Mehta ae_dev->priv = NULL; 2601e2cb1decSSalil Mehta } 2602e2cb1decSSalil Mehta 2603849e4607SPeng Li static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2604849e4607SPeng Li { 2605849e4607SPeng Li struct hnae3_handle *nic = &hdev->nic; 2606849e4607SPeng Li struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2607849e4607SPeng Li 26088be73621SHuazhong Tan return min_t(u32, hdev->rss_size_max, 26098be73621SHuazhong Tan hdev->num_tqps / kinfo->num_tc); 2610849e4607SPeng Li } 2611849e4607SPeng Li 2612849e4607SPeng Li /** 2613849e4607SPeng Li * hclgevf_get_channels - Get the current channels enabled and max supported. 2614849e4607SPeng Li * @handle: hardware information for network interface 2615849e4607SPeng Li * @ch: ethtool channels structure 2616849e4607SPeng Li * 2617849e4607SPeng Li * We don't support separate tx and rx queues as channels. The other count 2618849e4607SPeng Li * represents how many queues are being used for control. max_combined counts 2619849e4607SPeng Li * how many queue pairs we can support. They may not be mapped 1 to 1 with 2620849e4607SPeng Li * q_vectors since we support a lot more queue pairs than q_vectors. 2621849e4607SPeng Li **/ 2622849e4607SPeng Li static void hclgevf_get_channels(struct hnae3_handle *handle, 2623849e4607SPeng Li struct ethtool_channels *ch) 2624849e4607SPeng Li { 2625849e4607SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2626849e4607SPeng Li 2627849e4607SPeng Li ch->max_combined = hclgevf_get_max_channels(hdev); 2628849e4607SPeng Li ch->other_count = 0; 2629849e4607SPeng Li ch->max_other = 0; 26308be73621SHuazhong Tan ch->combined_count = handle->kinfo.rss_size; 2631849e4607SPeng Li } 2632849e4607SPeng Li 2633cc719218SPeng Li static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 26340d43bf45SHuazhong Tan u16 *alloc_tqps, u16 *max_rss_size) 2635cc719218SPeng Li { 2636cc719218SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2637cc719218SPeng Li 26380d43bf45SHuazhong Tan *alloc_tqps = hdev->num_tqps; 2639cc719218SPeng Li *max_rss_size = hdev->rss_size_max; 2640cc719218SPeng Li } 2641cc719218SPeng Li 2642175ec96bSFuyun Liang static int hclgevf_get_status(struct hnae3_handle *handle) 2643175ec96bSFuyun Liang { 2644175ec96bSFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2645175ec96bSFuyun Liang 2646175ec96bSFuyun Liang return hdev->hw.mac.link; 2647175ec96bSFuyun Liang } 2648175ec96bSFuyun Liang 26494a152de9SFuyun Liang static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 26504a152de9SFuyun Liang u8 *auto_neg, u32 *speed, 26514a152de9SFuyun Liang u8 *duplex) 26524a152de9SFuyun Liang { 26534a152de9SFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 26544a152de9SFuyun Liang 26554a152de9SFuyun Liang if (speed) 26564a152de9SFuyun Liang *speed = hdev->hw.mac.speed; 26574a152de9SFuyun Liang if (duplex) 26584a152de9SFuyun Liang *duplex = hdev->hw.mac.duplex; 26594a152de9SFuyun Liang if (auto_neg) 26604a152de9SFuyun Liang *auto_neg = AUTONEG_DISABLE; 26614a152de9SFuyun Liang } 26624a152de9SFuyun Liang 26634a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 26644a152de9SFuyun Liang u8 duplex) 26654a152de9SFuyun Liang { 26664a152de9SFuyun Liang hdev->hw.mac.speed = speed; 26674a152de9SFuyun Liang hdev->hw.mac.duplex = duplex; 26684a152de9SFuyun Liang } 26694a152de9SFuyun Liang 26701731be4cSYonglong Liu static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 26715c9f6b39SPeng Li { 26725c9f6b39SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 26735c9f6b39SPeng Li 26745c9f6b39SPeng Li return hclgevf_config_gro(hdev, enable); 26755c9f6b39SPeng Li } 26765c9f6b39SPeng Li 2677c136b884SPeng Li static void hclgevf_get_media_type(struct hnae3_handle *handle, 2678c136b884SPeng Li u8 *media_type) 2679c136b884SPeng Li { 2680c136b884SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2681c136b884SPeng Li if (media_type) 2682c136b884SPeng Li *media_type = hdev->hw.mac.media_type; 2683c136b884SPeng Li } 2684c136b884SPeng Li 26854d60291bSHuazhong Tan static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 26864d60291bSHuazhong Tan { 26874d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 26884d60291bSHuazhong Tan 2689aa5c4f17SHuazhong Tan return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 26904d60291bSHuazhong Tan } 26914d60291bSHuazhong Tan 26924d60291bSHuazhong Tan static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 26934d60291bSHuazhong Tan { 26944d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 26954d60291bSHuazhong Tan 26964d60291bSHuazhong Tan return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 26974d60291bSHuazhong Tan } 26984d60291bSHuazhong Tan 26994d60291bSHuazhong Tan static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 27004d60291bSHuazhong Tan { 27014d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27024d60291bSHuazhong Tan 27034d60291bSHuazhong Tan return hdev->reset_count; 27044d60291bSHuazhong Tan } 27054d60291bSHuazhong Tan 27069194d18bSliuzhongzhu static void hclgevf_get_link_mode(struct hnae3_handle *handle, 27079194d18bSliuzhongzhu unsigned long *supported, 27089194d18bSliuzhongzhu unsigned long *advertising) 27099194d18bSliuzhongzhu { 27109194d18bSliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27119194d18bSliuzhongzhu 27129194d18bSliuzhongzhu *supported = hdev->hw.mac.supported; 27139194d18bSliuzhongzhu *advertising = hdev->hw.mac.advertising; 27149194d18bSliuzhongzhu } 27159194d18bSliuzhongzhu 27161600c3e5SJian Shen #define MAX_SEPARATE_NUM 4 27171600c3e5SJian Shen #define SEPARATOR_VALUE 0xFFFFFFFF 27181600c3e5SJian Shen #define REG_NUM_PER_LINE 4 27191600c3e5SJian Shen #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 27201600c3e5SJian Shen 27211600c3e5SJian Shen static int hclgevf_get_regs_len(struct hnae3_handle *handle) 27221600c3e5SJian Shen { 27231600c3e5SJian Shen int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 27241600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27251600c3e5SJian Shen 27261600c3e5SJian Shen cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 27271600c3e5SJian Shen common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 27281600c3e5SJian Shen ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 27291600c3e5SJian Shen tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 27301600c3e5SJian Shen 27311600c3e5SJian Shen return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 27321600c3e5SJian Shen tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 27331600c3e5SJian Shen } 27341600c3e5SJian Shen 27351600c3e5SJian Shen static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 27361600c3e5SJian Shen void *data) 27371600c3e5SJian Shen { 27381600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27391600c3e5SJian Shen int i, j, reg_um, separator_num; 27401600c3e5SJian Shen u32 *reg = data; 27411600c3e5SJian Shen 27421600c3e5SJian Shen *version = hdev->fw_version; 27431600c3e5SJian Shen 27441600c3e5SJian Shen /* fetching per-VF registers values from VF PCIe register space */ 27451600c3e5SJian Shen reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 27461600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 27471600c3e5SJian Shen for (i = 0; i < reg_um; i++) 27481600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 27491600c3e5SJian Shen for (i = 0; i < separator_num; i++) 27501600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 27511600c3e5SJian Shen 27521600c3e5SJian Shen reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 27531600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 27541600c3e5SJian Shen for (i = 0; i < reg_um; i++) 27551600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 27561600c3e5SJian Shen for (i = 0; i < separator_num; i++) 27571600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 27581600c3e5SJian Shen 27591600c3e5SJian Shen reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 27601600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 27611600c3e5SJian Shen for (j = 0; j < hdev->num_tqps; j++) { 27621600c3e5SJian Shen for (i = 0; i < reg_um; i++) 27631600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 27641600c3e5SJian Shen ring_reg_addr_list[i] + 27651600c3e5SJian Shen 0x200 * j); 27661600c3e5SJian Shen for (i = 0; i < separator_num; i++) 27671600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 27681600c3e5SJian Shen } 27691600c3e5SJian Shen 27701600c3e5SJian Shen reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 27711600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 27721600c3e5SJian Shen for (j = 0; j < hdev->num_msi_used - 1; j++) { 27731600c3e5SJian Shen for (i = 0; i < reg_um; i++) 27741600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 27751600c3e5SJian Shen tqp_intr_reg_addr_list[i] + 27761600c3e5SJian Shen 4 * j); 27771600c3e5SJian Shen for (i = 0; i < separator_num; i++) 27781600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 27791600c3e5SJian Shen } 27801600c3e5SJian Shen } 27811600c3e5SJian Shen 2782e2cb1decSSalil Mehta static const struct hnae3_ae_ops hclgevf_ops = { 2783e2cb1decSSalil Mehta .init_ae_dev = hclgevf_init_ae_dev, 2784e2cb1decSSalil Mehta .uninit_ae_dev = hclgevf_uninit_ae_dev, 27856ff3cf07SHuazhong Tan .flr_prepare = hclgevf_flr_prepare, 27866ff3cf07SHuazhong Tan .flr_done = hclgevf_flr_done, 2787e718a93fSPeng Li .init_client_instance = hclgevf_init_client_instance, 2788e718a93fSPeng Li .uninit_client_instance = hclgevf_uninit_client_instance, 2789e2cb1decSSalil Mehta .start = hclgevf_ae_start, 2790e2cb1decSSalil Mehta .stop = hclgevf_ae_stop, 2791a6d818e3SYunsheng Lin .client_start = hclgevf_client_start, 2792a6d818e3SYunsheng Lin .client_stop = hclgevf_client_stop, 2793e2cb1decSSalil Mehta .map_ring_to_vector = hclgevf_map_ring_to_vector, 2794e2cb1decSSalil Mehta .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 2795e2cb1decSSalil Mehta .get_vector = hclgevf_get_vector, 27960d3e6631SYunsheng Lin .put_vector = hclgevf_put_vector, 2797e2cb1decSSalil Mehta .reset_queue = hclgevf_reset_tqp, 2798e2cb1decSSalil Mehta .get_mac_addr = hclgevf_get_mac_addr, 2799e2cb1decSSalil Mehta .set_mac_addr = hclgevf_set_mac_addr, 2800e2cb1decSSalil Mehta .add_uc_addr = hclgevf_add_uc_addr, 2801e2cb1decSSalil Mehta .rm_uc_addr = hclgevf_rm_uc_addr, 2802e2cb1decSSalil Mehta .add_mc_addr = hclgevf_add_mc_addr, 2803e2cb1decSSalil Mehta .rm_mc_addr = hclgevf_rm_mc_addr, 2804e2cb1decSSalil Mehta .get_stats = hclgevf_get_stats, 2805e2cb1decSSalil Mehta .update_stats = hclgevf_update_stats, 2806e2cb1decSSalil Mehta .get_strings = hclgevf_get_strings, 2807e2cb1decSSalil Mehta .get_sset_count = hclgevf_get_sset_count, 2808e2cb1decSSalil Mehta .get_rss_key_size = hclgevf_get_rss_key_size, 2809e2cb1decSSalil Mehta .get_rss_indir_size = hclgevf_get_rss_indir_size, 2810e2cb1decSSalil Mehta .get_rss = hclgevf_get_rss, 2811e2cb1decSSalil Mehta .set_rss = hclgevf_set_rss, 2812d97b3072SJian Shen .get_rss_tuple = hclgevf_get_rss_tuple, 2813d97b3072SJian Shen .set_rss_tuple = hclgevf_set_rss_tuple, 2814e2cb1decSSalil Mehta .get_tc_size = hclgevf_get_tc_size, 2815e2cb1decSSalil Mehta .get_fw_version = hclgevf_get_fw_version, 2816e2cb1decSSalil Mehta .set_vlan_filter = hclgevf_set_vlan_filter, 2817b2641e2aSYunsheng Lin .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 28186d4c3981SSalil Mehta .reset_event = hclgevf_reset_event, 2819720bd583SHuazhong Tan .set_default_reset_request = hclgevf_set_def_reset_request, 2820849e4607SPeng Li .get_channels = hclgevf_get_channels, 2821cc719218SPeng Li .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 28221600c3e5SJian Shen .get_regs_len = hclgevf_get_regs_len, 28231600c3e5SJian Shen .get_regs = hclgevf_get_regs, 2824175ec96bSFuyun Liang .get_status = hclgevf_get_status, 28254a152de9SFuyun Liang .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 2826c136b884SPeng Li .get_media_type = hclgevf_get_media_type, 28274d60291bSHuazhong Tan .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 28284d60291bSHuazhong Tan .ae_dev_resetting = hclgevf_ae_dev_resetting, 28294d60291bSHuazhong Tan .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 28305c9f6b39SPeng Li .set_gro_en = hclgevf_gro_en, 2831818f1675SYunsheng Lin .set_mtu = hclgevf_set_mtu, 28320c29d191Sliuzhongzhu .get_global_queue_id = hclgevf_get_qid_global, 28338cdb992fSJian Shen .set_timer_task = hclgevf_set_timer_task, 28349194d18bSliuzhongzhu .get_link_mode = hclgevf_get_link_mode, 2835e2cb1decSSalil Mehta }; 2836e2cb1decSSalil Mehta 2837e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf = { 2838e2cb1decSSalil Mehta .ops = &hclgevf_ops, 2839e2cb1decSSalil Mehta .pdev_id_table = ae_algovf_pci_tbl, 2840e2cb1decSSalil Mehta }; 2841e2cb1decSSalil Mehta 2842e2cb1decSSalil Mehta static int hclgevf_init(void) 2843e2cb1decSSalil Mehta { 2844e2cb1decSSalil Mehta pr_info("%s is initializing\n", HCLGEVF_NAME); 2845e2cb1decSSalil Mehta 2846854cf33aSFuyun Liang hnae3_register_ae_algo(&ae_algovf); 2847854cf33aSFuyun Liang 2848854cf33aSFuyun Liang return 0; 2849e2cb1decSSalil Mehta } 2850e2cb1decSSalil Mehta 2851e2cb1decSSalil Mehta static void hclgevf_exit(void) 2852e2cb1decSSalil Mehta { 2853e2cb1decSSalil Mehta hnae3_unregister_ae_algo(&ae_algovf); 2854e2cb1decSSalil Mehta } 2855e2cb1decSSalil Mehta module_init(hclgevf_init); 2856e2cb1decSSalil Mehta module_exit(hclgevf_exit); 2857e2cb1decSSalil Mehta 2858e2cb1decSSalil Mehta MODULE_LICENSE("GPL"); 2859e2cb1decSSalil Mehta MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 2860e2cb1decSSalil Mehta MODULE_DESCRIPTION("HCLGEVF Driver"); 2861e2cb1decSSalil Mehta MODULE_VERSION(HCLGEVF_MOD_VERSION); 2862