1e2cb1decSSalil Mehta // SPDX-License-Identifier: GPL-2.0+ 2e2cb1decSSalil Mehta // Copyright (c) 2016-2017 Hisilicon Limited. 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #include <linux/etherdevice.h> 5aa5c4f17SHuazhong Tan #include <linux/iopoll.h> 66988eb2aSSalil Mehta #include <net/rtnetlink.h> 7e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 8e2cb1decSSalil Mehta #include "hclgevf_main.h" 9e2cb1decSSalil Mehta #include "hclge_mbx.h" 10e2cb1decSSalil Mehta #include "hnae3.h" 11cd624299SYufeng Mo #include "hclgevf_devlink.h" 12e2cb1decSSalil Mehta 13e2cb1decSSalil Mehta #define HCLGEVF_NAME "hclgevf" 14e2cb1decSSalil Mehta 15bbe6540eSHuazhong Tan #define HCLGEVF_RESET_MAX_FAIL_CNT 5 16bbe6540eSHuazhong Tan 179c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 185e7414cdSJian Shen static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 195e7414cdSJian Shen unsigned long delay); 205e7414cdSJian Shen 21e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf; 22e2cb1decSSalil Mehta 230ea68902SYunsheng Lin static struct workqueue_struct *hclgevf_wq; 240ea68902SYunsheng Lin 25e2cb1decSSalil Mehta static const struct pci_device_id ae_algovf_pci_tbl[] = { 26c155e22bSGuangbin Huang {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0}, 27c155e22bSGuangbin Huang {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 28c155e22bSGuangbin Huang HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 29e2cb1decSSalil Mehta /* required last entry */ 30e2cb1decSSalil Mehta {0, } 31e2cb1decSSalil Mehta }; 32e2cb1decSSalil Mehta 33472d7eceSJian Shen static const u8 hclgevf_hash_key[] = { 34472d7eceSJian Shen 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 35472d7eceSJian Shen 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 36472d7eceSJian Shen 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 37472d7eceSJian Shen 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 38472d7eceSJian Shen 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 39472d7eceSJian Shen }; 40472d7eceSJian Shen 412f550a46SYunsheng Lin MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 422f550a46SYunsheng Lin 43cb413bfaSJie Wang static const u32 cmdq_reg_addr_list[] = {HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG, 44cb413bfaSJie Wang HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG, 45cb413bfaSJie Wang HCLGE_COMM_NIC_CSQ_DEPTH_REG, 46cb413bfaSJie Wang HCLGE_COMM_NIC_CSQ_TAIL_REG, 47cb413bfaSJie Wang HCLGE_COMM_NIC_CSQ_HEAD_REG, 48cb413bfaSJie Wang HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG, 49cb413bfaSJie Wang HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG, 50cb413bfaSJie Wang HCLGE_COMM_NIC_CRQ_DEPTH_REG, 51cb413bfaSJie Wang HCLGE_COMM_NIC_CRQ_TAIL_REG, 52cb413bfaSJie Wang HCLGE_COMM_NIC_CRQ_HEAD_REG, 53cb413bfaSJie Wang HCLGE_COMM_VECTOR0_CMDQ_SRC_REG, 54cb413bfaSJie Wang HCLGE_COMM_VECTOR0_CMDQ_STATE_REG, 55cb413bfaSJie Wang HCLGE_COMM_CMDQ_INTR_EN_REG, 56cb413bfaSJie Wang HCLGE_COMM_CMDQ_INTR_GEN_REG}; 571600c3e5SJian Shen 581600c3e5SJian Shen static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 591600c3e5SJian Shen HCLGEVF_RST_ING, 601600c3e5SJian Shen HCLGEVF_GRO_EN_REG}; 611600c3e5SJian Shen 621600c3e5SJian Shen static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 631600c3e5SJian Shen HCLGEVF_RING_RX_ADDR_H_REG, 641600c3e5SJian Shen HCLGEVF_RING_RX_BD_NUM_REG, 651600c3e5SJian Shen HCLGEVF_RING_RX_BD_LENGTH_REG, 661600c3e5SJian Shen HCLGEVF_RING_RX_MERGE_EN_REG, 671600c3e5SJian Shen HCLGEVF_RING_RX_TAIL_REG, 681600c3e5SJian Shen HCLGEVF_RING_RX_HEAD_REG, 691600c3e5SJian Shen HCLGEVF_RING_RX_FBD_NUM_REG, 701600c3e5SJian Shen HCLGEVF_RING_RX_OFFSET_REG, 711600c3e5SJian Shen HCLGEVF_RING_RX_FBD_OFFSET_REG, 721600c3e5SJian Shen HCLGEVF_RING_RX_STASH_REG, 731600c3e5SJian Shen HCLGEVF_RING_RX_BD_ERR_REG, 741600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_L_REG, 751600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_H_REG, 761600c3e5SJian Shen HCLGEVF_RING_TX_BD_NUM_REG, 771600c3e5SJian Shen HCLGEVF_RING_TX_PRIORITY_REG, 781600c3e5SJian Shen HCLGEVF_RING_TX_TC_REG, 791600c3e5SJian Shen HCLGEVF_RING_TX_MERGE_EN_REG, 801600c3e5SJian Shen HCLGEVF_RING_TX_TAIL_REG, 811600c3e5SJian Shen HCLGEVF_RING_TX_HEAD_REG, 821600c3e5SJian Shen HCLGEVF_RING_TX_FBD_NUM_REG, 831600c3e5SJian Shen HCLGEVF_RING_TX_OFFSET_REG, 841600c3e5SJian Shen HCLGEVF_RING_TX_EBD_NUM_REG, 851600c3e5SJian Shen HCLGEVF_RING_TX_EBD_OFFSET_REG, 861600c3e5SJian Shen HCLGEVF_RING_TX_BD_ERR_REG, 871600c3e5SJian Shen HCLGEVF_RING_EN_REG}; 881600c3e5SJian Shen 891600c3e5SJian Shen static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 901600c3e5SJian Shen HCLGEVF_TQP_INTR_GL0_REG, 911600c3e5SJian Shen HCLGEVF_TQP_INTR_GL1_REG, 921600c3e5SJian Shen HCLGEVF_TQP_INTR_GL2_REG, 931600c3e5SJian Shen HCLGEVF_TQP_INTR_RL_REG}; 941600c3e5SJian Shen 95aab8d1c6SJie Wang /* hclgevf_cmd_send - send command to command queue 96aab8d1c6SJie Wang * @hw: pointer to the hw struct 97aab8d1c6SJie Wang * @desc: prefilled descriptor for describing the command 98aab8d1c6SJie Wang * @num : the number of descriptors to be sent 99aab8d1c6SJie Wang * 100aab8d1c6SJie Wang * This is the main send command for command queue, it 101aab8d1c6SJie Wang * sends the queue, cleans the queue, etc 102aab8d1c6SJie Wang */ 103aab8d1c6SJie Wang int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclge_desc *desc, int num) 104aab8d1c6SJie Wang { 105*9970308fSJie Wang return hclge_comm_cmd_send(&hw->hw, desc, num); 106aab8d1c6SJie Wang } 107aab8d1c6SJie Wang 108aab8d1c6SJie Wang void hclgevf_arq_init(struct hclgevf_dev *hdev) 109aab8d1c6SJie Wang { 110aab8d1c6SJie Wang struct hclge_comm_cmq *cmdq = &hdev->hw.hw.cmq; 111aab8d1c6SJie Wang 112aab8d1c6SJie Wang spin_lock(&cmdq->crq.lock); 113aab8d1c6SJie Wang /* initialize the pointers of async rx queue of mailbox */ 114aab8d1c6SJie Wang hdev->arq.hdev = hdev; 115aab8d1c6SJie Wang hdev->arq.head = 0; 116aab8d1c6SJie Wang hdev->arq.tail = 0; 117aab8d1c6SJie Wang atomic_set(&hdev->arq.count, 0); 118aab8d1c6SJie Wang spin_unlock(&cmdq->crq.lock); 119aab8d1c6SJie Wang } 120aab8d1c6SJie Wang 1219b2f3477SWeihang Li static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 122e2cb1decSSalil Mehta { 123eed9535fSPeng Li if (!handle->client) 124eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, nic); 125eed9535fSPeng Li else if (handle->client->type == HNAE3_CLIENT_ROCE) 126eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, roce); 127eed9535fSPeng Li else 128e2cb1decSSalil Mehta return container_of(handle, struct hclgevf_dev, nic); 129e2cb1decSSalil Mehta } 130e2cb1decSSalil Mehta 131e2cb1decSSalil Mehta static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 132e2cb1decSSalil Mehta { 133b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 134e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1356befad60SJie Wang struct hclge_desc desc; 136e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 137e2cb1decSSalil Mehta int status; 138e2cb1decSSalil Mehta int i; 139e2cb1decSSalil Mehta 140b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 141b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 142e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 143e2cb1decSSalil Mehta HCLGEVF_OPC_QUERY_RX_STATUS, 144e2cb1decSSalil Mehta true); 145e2cb1decSSalil Mehta 146e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 147e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 148e2cb1decSSalil Mehta if (status) { 149e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 150e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 151e2cb1decSSalil Mehta status, i); 152e2cb1decSSalil Mehta return status; 153e2cb1decSSalil Mehta } 154e2cb1decSSalil Mehta tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 155cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 156e2cb1decSSalil Mehta 157e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 158e2cb1decSSalil Mehta true); 159e2cb1decSSalil Mehta 160e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 161e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 162e2cb1decSSalil Mehta if (status) { 163e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 164e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 165e2cb1decSSalil Mehta status, i); 166e2cb1decSSalil Mehta return status; 167e2cb1decSSalil Mehta } 168e2cb1decSSalil Mehta tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 169cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 170e2cb1decSSalil Mehta } 171e2cb1decSSalil Mehta 172e2cb1decSSalil Mehta return 0; 173e2cb1decSSalil Mehta } 174e2cb1decSSalil Mehta 175e2cb1decSSalil Mehta static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 176e2cb1decSSalil Mehta { 177e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo = &handle->kinfo; 178e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 179e2cb1decSSalil Mehta u64 *buff = data; 180e2cb1decSSalil Mehta int i; 181e2cb1decSSalil Mehta 182b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 183b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 184e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 185e2cb1decSSalil Mehta } 186e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 187b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 188e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 189e2cb1decSSalil Mehta } 190e2cb1decSSalil Mehta 191e2cb1decSSalil Mehta return buff; 192e2cb1decSSalil Mehta } 193e2cb1decSSalil Mehta 194e2cb1decSSalil Mehta static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 195e2cb1decSSalil Mehta { 196b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 197e2cb1decSSalil Mehta 198b4f1d303SJian Shen return kinfo->num_tqps * 2; 199e2cb1decSSalil Mehta } 200e2cb1decSSalil Mehta 201e2cb1decSSalil Mehta static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 202e2cb1decSSalil Mehta { 203b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 204e2cb1decSSalil Mehta u8 *buff = data; 2059d8d5a36SYufeng Mo int i; 206e2cb1decSSalil Mehta 207b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 208b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 209e2cb1decSSalil Mehta struct hclgevf_tqp, q); 210c5aaf176SJiaran Zhang snprintf(buff, ETH_GSTRING_LEN, "txq%u_pktnum_rcd", 211e2cb1decSSalil Mehta tqp->index); 212e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 213e2cb1decSSalil Mehta } 214e2cb1decSSalil Mehta 215b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 216b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 217e2cb1decSSalil Mehta struct hclgevf_tqp, q); 218c5aaf176SJiaran Zhang snprintf(buff, ETH_GSTRING_LEN, "rxq%u_pktnum_rcd", 219e2cb1decSSalil Mehta tqp->index); 220e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 221e2cb1decSSalil Mehta } 222e2cb1decSSalil Mehta 223e2cb1decSSalil Mehta return buff; 224e2cb1decSSalil Mehta } 225e2cb1decSSalil Mehta 226e2cb1decSSalil Mehta static void hclgevf_update_stats(struct hnae3_handle *handle, 227e2cb1decSSalil Mehta struct net_device_stats *net_stats) 228e2cb1decSSalil Mehta { 229e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 230e2cb1decSSalil Mehta int status; 231e2cb1decSSalil Mehta 232e2cb1decSSalil Mehta status = hclgevf_tqps_update_stats(handle); 233e2cb1decSSalil Mehta if (status) 234e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 235e2cb1decSSalil Mehta "VF update of TQPS stats fail, status = %d.\n", 236e2cb1decSSalil Mehta status); 237e2cb1decSSalil Mehta } 238e2cb1decSSalil Mehta 239e2cb1decSSalil Mehta static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 240e2cb1decSSalil Mehta { 241e2cb1decSSalil Mehta if (strset == ETH_SS_TEST) 242e2cb1decSSalil Mehta return -EOPNOTSUPP; 243e2cb1decSSalil Mehta else if (strset == ETH_SS_STATS) 244e2cb1decSSalil Mehta return hclgevf_tqps_get_sset_count(handle, strset); 245e2cb1decSSalil Mehta 246e2cb1decSSalil Mehta return 0; 247e2cb1decSSalil Mehta } 248e2cb1decSSalil Mehta 249e2cb1decSSalil Mehta static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 250e2cb1decSSalil Mehta u8 *data) 251e2cb1decSSalil Mehta { 252e2cb1decSSalil Mehta u8 *p = (char *)data; 253e2cb1decSSalil Mehta 254e2cb1decSSalil Mehta if (strset == ETH_SS_STATS) 255e2cb1decSSalil Mehta p = hclgevf_tqps_get_strings(handle, p); 256e2cb1decSSalil Mehta } 257e2cb1decSSalil Mehta 258e2cb1decSSalil Mehta static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 259e2cb1decSSalil Mehta { 260e2cb1decSSalil Mehta hclgevf_tqps_get_stats(handle, data); 261e2cb1decSSalil Mehta } 262e2cb1decSSalil Mehta 263d3410018SYufeng Mo static void hclgevf_build_send_msg(struct hclge_vf_to_pf_msg *msg, u8 code, 264d3410018SYufeng Mo u8 subcode) 265d3410018SYufeng Mo { 266d3410018SYufeng Mo if (msg) { 267d3410018SYufeng Mo memset(msg, 0, sizeof(struct hclge_vf_to_pf_msg)); 268d3410018SYufeng Mo msg->code = code; 269d3410018SYufeng Mo msg->subcode = subcode; 270d3410018SYufeng Mo } 271d3410018SYufeng Mo } 272d3410018SYufeng Mo 27332e6d104SJian Shen static int hclgevf_get_basic_info(struct hclgevf_dev *hdev) 274e2cb1decSSalil Mehta { 27532e6d104SJian Shen struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 27632e6d104SJian Shen u8 resp_msg[HCLGE_MBX_MAX_RESP_DATA_SIZE]; 27732e6d104SJian Shen struct hclge_basic_info *basic_info; 278d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 27932e6d104SJian Shen unsigned long caps; 280e2cb1decSSalil Mehta int status; 281e2cb1decSSalil Mehta 28232e6d104SJian Shen hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_BASIC_INFO, 0); 28332e6d104SJian Shen status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 284d3410018SYufeng Mo sizeof(resp_msg)); 285e2cb1decSSalil Mehta if (status) { 286e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 28732e6d104SJian Shen "failed to get basic info from pf, ret = %d", status); 288e2cb1decSSalil Mehta return status; 289e2cb1decSSalil Mehta } 290e2cb1decSSalil Mehta 29132e6d104SJian Shen basic_info = (struct hclge_basic_info *)resp_msg; 29232e6d104SJian Shen 29332e6d104SJian Shen hdev->hw_tc_map = basic_info->hw_tc_map; 29432e6d104SJian Shen hdev->mbx_api_version = basic_info->mbx_api_version; 29532e6d104SJian Shen caps = basic_info->pf_caps; 29632e6d104SJian Shen if (test_bit(HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B, &caps)) 29732e6d104SJian Shen set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps); 298e2cb1decSSalil Mehta 299e2cb1decSSalil Mehta return 0; 300e2cb1decSSalil Mehta } 301e2cb1decSSalil Mehta 30292f11ea1SJian Shen static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 30392f11ea1SJian Shen { 30492f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 305d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 30692f11ea1SJian Shen u8 resp_msg; 30792f11ea1SJian Shen int ret; 30892f11ea1SJian Shen 309d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 310d3410018SYufeng Mo HCLGE_MBX_GET_PORT_BASE_VLAN_STATE); 311d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg, 312d3410018SYufeng Mo sizeof(u8)); 31392f11ea1SJian Shen if (ret) { 31492f11ea1SJian Shen dev_err(&hdev->pdev->dev, 31592f11ea1SJian Shen "VF request to get port based vlan state failed %d", 31692f11ea1SJian Shen ret); 31792f11ea1SJian Shen return ret; 31892f11ea1SJian Shen } 31992f11ea1SJian Shen 32092f11ea1SJian Shen nic->port_base_vlan_state = resp_msg; 32192f11ea1SJian Shen 32292f11ea1SJian Shen return 0; 32392f11ea1SJian Shen } 32492f11ea1SJian Shen 3256cee6fc3SJian Shen static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 326e2cb1decSSalil Mehta { 327c0425944SPeng Li #define HCLGEVF_TQPS_RSS_INFO_LEN 6 328d3410018SYufeng Mo #define HCLGEVF_TQPS_ALLOC_OFFSET 0 329d3410018SYufeng Mo #define HCLGEVF_TQPS_RSS_SIZE_OFFSET 2 330d3410018SYufeng Mo #define HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET 4 331d3410018SYufeng Mo 332e2cb1decSSalil Mehta u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 333d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 334e2cb1decSSalil Mehta int status; 335e2cb1decSSalil Mehta 336d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QINFO, 0); 337d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 338e2cb1decSSalil Mehta HCLGEVF_TQPS_RSS_INFO_LEN); 339e2cb1decSSalil Mehta if (status) { 340e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 341e2cb1decSSalil Mehta "VF request to get tqp info from PF failed %d", 342e2cb1decSSalil Mehta status); 343e2cb1decSSalil Mehta return status; 344e2cb1decSSalil Mehta } 345e2cb1decSSalil Mehta 346d3410018SYufeng Mo memcpy(&hdev->num_tqps, &resp_msg[HCLGEVF_TQPS_ALLOC_OFFSET], 347d3410018SYufeng Mo sizeof(u16)); 348d3410018SYufeng Mo memcpy(&hdev->rss_size_max, &resp_msg[HCLGEVF_TQPS_RSS_SIZE_OFFSET], 349d3410018SYufeng Mo sizeof(u16)); 350d3410018SYufeng Mo memcpy(&hdev->rx_buf_len, &resp_msg[HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET], 351d3410018SYufeng Mo sizeof(u16)); 352c0425944SPeng Li 353c0425944SPeng Li return 0; 354c0425944SPeng Li } 355c0425944SPeng Li 356c0425944SPeng Li static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 357c0425944SPeng Li { 358c0425944SPeng Li #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 359d3410018SYufeng Mo #define HCLGEVF_TQPS_NUM_TX_DESC_OFFSET 0 360d3410018SYufeng Mo #define HCLGEVF_TQPS_NUM_RX_DESC_OFFSET 2 361d3410018SYufeng Mo 362c0425944SPeng Li u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 363d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 364c0425944SPeng Li int ret; 365c0425944SPeng Li 366d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QDEPTH, 0); 367d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 368c0425944SPeng Li HCLGEVF_TQPS_DEPTH_INFO_LEN); 369c0425944SPeng Li if (ret) { 370c0425944SPeng Li dev_err(&hdev->pdev->dev, 371c0425944SPeng Li "VF request to get tqp depth info from PF failed %d", 372c0425944SPeng Li ret); 373c0425944SPeng Li return ret; 374c0425944SPeng Li } 375c0425944SPeng Li 376d3410018SYufeng Mo memcpy(&hdev->num_tx_desc, &resp_msg[HCLGEVF_TQPS_NUM_TX_DESC_OFFSET], 377d3410018SYufeng Mo sizeof(u16)); 378d3410018SYufeng Mo memcpy(&hdev->num_rx_desc, &resp_msg[HCLGEVF_TQPS_NUM_RX_DESC_OFFSET], 379d3410018SYufeng Mo sizeof(u16)); 380e2cb1decSSalil Mehta 381e2cb1decSSalil Mehta return 0; 382e2cb1decSSalil Mehta } 383e2cb1decSSalil Mehta 3840c29d191Sliuzhongzhu static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 3850c29d191Sliuzhongzhu { 3860c29d191Sliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 387d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 3880c29d191Sliuzhongzhu u16 qid_in_pf = 0; 389d3410018SYufeng Mo u8 resp_data[2]; 3900c29d191Sliuzhongzhu int ret; 3910c29d191Sliuzhongzhu 392d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QID_IN_PF, 0); 393d3410018SYufeng Mo memcpy(send_msg.data, &queue_id, sizeof(queue_id)); 394d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_data, 39563cbf7a9SYufeng Mo sizeof(resp_data)); 3960c29d191Sliuzhongzhu if (!ret) 3970c29d191Sliuzhongzhu qid_in_pf = *(u16 *)resp_data; 3980c29d191Sliuzhongzhu 3990c29d191Sliuzhongzhu return qid_in_pf; 4000c29d191Sliuzhongzhu } 4010c29d191Sliuzhongzhu 4029c3e7130Sliuzhongzhu static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 4039c3e7130Sliuzhongzhu { 404d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 40588d10bd6SJian Shen u8 resp_msg[2]; 4069c3e7130Sliuzhongzhu int ret; 4079c3e7130Sliuzhongzhu 408d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MEDIA_TYPE, 0); 409d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 410d3410018SYufeng Mo sizeof(resp_msg)); 4119c3e7130Sliuzhongzhu if (ret) { 4129c3e7130Sliuzhongzhu dev_err(&hdev->pdev->dev, 4139c3e7130Sliuzhongzhu "VF request to get the pf port media type failed %d", 4149c3e7130Sliuzhongzhu ret); 4159c3e7130Sliuzhongzhu return ret; 4169c3e7130Sliuzhongzhu } 4179c3e7130Sliuzhongzhu 41888d10bd6SJian Shen hdev->hw.mac.media_type = resp_msg[0]; 41988d10bd6SJian Shen hdev->hw.mac.module_type = resp_msg[1]; 4209c3e7130Sliuzhongzhu 4219c3e7130Sliuzhongzhu return 0; 4229c3e7130Sliuzhongzhu } 4239c3e7130Sliuzhongzhu 424e2cb1decSSalil Mehta static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 425e2cb1decSSalil Mehta { 426e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 427e2cb1decSSalil Mehta int i; 428e2cb1decSSalil Mehta 429e2cb1decSSalil Mehta hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 430e2cb1decSSalil Mehta sizeof(struct hclgevf_tqp), GFP_KERNEL); 431e2cb1decSSalil Mehta if (!hdev->htqp) 432e2cb1decSSalil Mehta return -ENOMEM; 433e2cb1decSSalil Mehta 434e2cb1decSSalil Mehta tqp = hdev->htqp; 435e2cb1decSSalil Mehta 436e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 437e2cb1decSSalil Mehta tqp->dev = &hdev->pdev->dev; 438e2cb1decSSalil Mehta tqp->index = i; 439e2cb1decSSalil Mehta 440e2cb1decSSalil Mehta tqp->q.ae_algo = &ae_algovf; 441e2cb1decSSalil Mehta tqp->q.buf_size = hdev->rx_buf_len; 442c0425944SPeng Li tqp->q.tx_desc_num = hdev->num_tx_desc; 443c0425944SPeng Li tqp->q.rx_desc_num = hdev->num_rx_desc; 4449a5ef4aaSYonglong Liu 4459a5ef4aaSYonglong Liu /* need an extended offset to configure queues >= 4469a5ef4aaSYonglong Liu * HCLGEVF_TQP_MAX_SIZE_DEV_V2. 4479a5ef4aaSYonglong Liu */ 4489a5ef4aaSYonglong Liu if (i < HCLGEVF_TQP_MAX_SIZE_DEV_V2) 449076bb537SJie Wang tqp->q.io_base = hdev->hw.hw.io_base + 4509a5ef4aaSYonglong Liu HCLGEVF_TQP_REG_OFFSET + 451e2cb1decSSalil Mehta i * HCLGEVF_TQP_REG_SIZE; 4529a5ef4aaSYonglong Liu else 453076bb537SJie Wang tqp->q.io_base = hdev->hw.hw.io_base + 4549a5ef4aaSYonglong Liu HCLGEVF_TQP_REG_OFFSET + 4559a5ef4aaSYonglong Liu HCLGEVF_TQP_EXT_REG_OFFSET + 4569a5ef4aaSYonglong Liu (i - HCLGEVF_TQP_MAX_SIZE_DEV_V2) * 4579a5ef4aaSYonglong Liu HCLGEVF_TQP_REG_SIZE; 458e2cb1decSSalil Mehta 459e2cb1decSSalil Mehta tqp++; 460e2cb1decSSalil Mehta } 461e2cb1decSSalil Mehta 462e2cb1decSSalil Mehta return 0; 463e2cb1decSSalil Mehta } 464e2cb1decSSalil Mehta 465e2cb1decSSalil Mehta static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 466e2cb1decSSalil Mehta { 467e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 468e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo; 469e2cb1decSSalil Mehta u16 new_tqps = hdev->num_tqps; 470ebaf1908SWeihang Li unsigned int i; 47135244430SJian Shen u8 num_tc = 0; 472e2cb1decSSalil Mehta 473e2cb1decSSalil Mehta kinfo = &nic->kinfo; 474c0425944SPeng Li kinfo->num_tx_desc = hdev->num_tx_desc; 475c0425944SPeng Li kinfo->num_rx_desc = hdev->num_rx_desc; 476e2cb1decSSalil Mehta kinfo->rx_buf_len = hdev->rx_buf_len; 477e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 478e2cb1decSSalil Mehta if (hdev->hw_tc_map & BIT(i)) 47935244430SJian Shen num_tc++; 480e2cb1decSSalil Mehta 48135244430SJian Shen num_tc = num_tc ? num_tc : 1; 48235244430SJian Shen kinfo->tc_info.num_tc = num_tc; 48335244430SJian Shen kinfo->rss_size = min_t(u16, hdev->rss_size_max, new_tqps / num_tc); 48435244430SJian Shen new_tqps = kinfo->rss_size * num_tc; 485e2cb1decSSalil Mehta kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 486e2cb1decSSalil Mehta 487e2cb1decSSalil Mehta kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 488e2cb1decSSalil Mehta sizeof(struct hnae3_queue *), GFP_KERNEL); 489e2cb1decSSalil Mehta if (!kinfo->tqp) 490e2cb1decSSalil Mehta return -ENOMEM; 491e2cb1decSSalil Mehta 492e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 493e2cb1decSSalil Mehta hdev->htqp[i].q.handle = &hdev->nic; 494e2cb1decSSalil Mehta hdev->htqp[i].q.tqp_index = i; 495e2cb1decSSalil Mehta kinfo->tqp[i] = &hdev->htqp[i].q; 496e2cb1decSSalil Mehta } 497e2cb1decSSalil Mehta 498580a05f9SYonglong Liu /* after init the max rss_size and tqps, adjust the default tqp numbers 499580a05f9SYonglong Liu * and rss size with the actual vector numbers 500580a05f9SYonglong Liu */ 501580a05f9SYonglong Liu kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps); 50235244430SJian Shen kinfo->rss_size = min_t(u16, kinfo->num_tqps / num_tc, 503580a05f9SYonglong Liu kinfo->rss_size); 504580a05f9SYonglong Liu 505e2cb1decSSalil Mehta return 0; 506e2cb1decSSalil Mehta } 507e2cb1decSSalil Mehta 508e2cb1decSSalil Mehta static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 509e2cb1decSSalil Mehta { 510d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 511e2cb1decSSalil Mehta int status; 512e2cb1decSSalil Mehta 513d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_STATUS, 0); 514d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 515e2cb1decSSalil Mehta if (status) 516e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 517e2cb1decSSalil Mehta "VF failed to fetch link status(%d) from PF", status); 518e2cb1decSSalil Mehta } 519e2cb1decSSalil Mehta 520e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 521e2cb1decSSalil Mehta { 52245e92b7eSPeng Li struct hnae3_handle *rhandle = &hdev->roce; 523e2cb1decSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 52445e92b7eSPeng Li struct hnae3_client *rclient; 525e2cb1decSSalil Mehta struct hnae3_client *client; 526e2cb1decSSalil Mehta 527ff200099SYunsheng Lin if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state)) 528ff200099SYunsheng Lin return; 529ff200099SYunsheng Lin 530e2cb1decSSalil Mehta client = handle->client; 53145e92b7eSPeng Li rclient = hdev->roce_client; 532e2cb1decSSalil Mehta 533582d37bbSPeng Li link_state = 534582d37bbSPeng Li test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 535e2cb1decSSalil Mehta if (link_state != hdev->hw.mac.link) { 536b15c072aSYonglong Liu hdev->hw.mac.link = link_state; 537e2cb1decSSalil Mehta client->ops->link_status_change(handle, !!link_state); 53845e92b7eSPeng Li if (rclient && rclient->ops->link_status_change) 53945e92b7eSPeng Li rclient->ops->link_status_change(rhandle, !!link_state); 540e2cb1decSSalil Mehta } 541ff200099SYunsheng Lin 542ff200099SYunsheng Lin clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state); 543e2cb1decSSalil Mehta } 544e2cb1decSSalil Mehta 545538abaf3SYueHaibing static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 5469194d18bSliuzhongzhu { 5479194d18bSliuzhongzhu #define HCLGEVF_ADVERTISING 0 5489194d18bSliuzhongzhu #define HCLGEVF_SUPPORTED 1 5499194d18bSliuzhongzhu 550d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 551d3410018SYufeng Mo 552d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_MODE, 0); 553d3410018SYufeng Mo send_msg.data[0] = HCLGEVF_ADVERTISING; 554d3410018SYufeng Mo hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 555d3410018SYufeng Mo send_msg.data[0] = HCLGEVF_SUPPORTED; 556d3410018SYufeng Mo hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 5579194d18bSliuzhongzhu } 5589194d18bSliuzhongzhu 559e2cb1decSSalil Mehta static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 560e2cb1decSSalil Mehta { 561e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 562e2cb1decSSalil Mehta int ret; 563e2cb1decSSalil Mehta 564e2cb1decSSalil Mehta nic->ae_algo = &ae_algovf; 565e2cb1decSSalil Mehta nic->pdev = hdev->pdev; 566e2cb1decSSalil Mehta nic->numa_node_mask = hdev->numa_node_mask; 567424eb834SSalil Mehta nic->flags |= HNAE3_SUPPORT_VF; 568076bb537SJie Wang nic->kinfo.io_base = hdev->hw.hw.io_base; 569e2cb1decSSalil Mehta 570e2cb1decSSalil Mehta ret = hclgevf_knic_setup(hdev); 571e2cb1decSSalil Mehta if (ret) 572e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 573e2cb1decSSalil Mehta ret); 574e2cb1decSSalil Mehta return ret; 575e2cb1decSSalil Mehta } 576e2cb1decSSalil Mehta 577e2cb1decSSalil Mehta static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 578e2cb1decSSalil Mehta { 57936cbbdf6SPeng Li if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 58036cbbdf6SPeng Li dev_warn(&hdev->pdev->dev, 58136cbbdf6SPeng Li "vector(vector_id %d) has been freed.\n", vector_id); 58236cbbdf6SPeng Li return; 58336cbbdf6SPeng Li } 58436cbbdf6SPeng Li 585e2cb1decSSalil Mehta hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 586e2cb1decSSalil Mehta hdev->num_msi_left += 1; 587e2cb1decSSalil Mehta hdev->num_msi_used -= 1; 588e2cb1decSSalil Mehta } 589e2cb1decSSalil Mehta 590e2cb1decSSalil Mehta static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 591e2cb1decSSalil Mehta struct hnae3_vector_info *vector_info) 592e2cb1decSSalil Mehta { 593e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 594e2cb1decSSalil Mehta struct hnae3_vector_info *vector = vector_info; 595e2cb1decSSalil Mehta int alloc = 0; 596e2cb1decSSalil Mehta int i, j; 597e2cb1decSSalil Mehta 598580a05f9SYonglong Liu vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num); 599e2cb1decSSalil Mehta vector_num = min(hdev->num_msi_left, vector_num); 600e2cb1decSSalil Mehta 601e2cb1decSSalil Mehta for (j = 0; j < vector_num; j++) { 602e2cb1decSSalil Mehta for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 603e2cb1decSSalil Mehta if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 604e2cb1decSSalil Mehta vector->vector = pci_irq_vector(hdev->pdev, i); 605076bb537SJie Wang vector->io_addr = hdev->hw.hw.io_base + 606e2cb1decSSalil Mehta HCLGEVF_VECTOR_REG_BASE + 607e2cb1decSSalil Mehta (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 608e2cb1decSSalil Mehta hdev->vector_status[i] = 0; 609e2cb1decSSalil Mehta hdev->vector_irq[i] = vector->vector; 610e2cb1decSSalil Mehta 611e2cb1decSSalil Mehta vector++; 612e2cb1decSSalil Mehta alloc++; 613e2cb1decSSalil Mehta 614e2cb1decSSalil Mehta break; 615e2cb1decSSalil Mehta } 616e2cb1decSSalil Mehta } 617e2cb1decSSalil Mehta } 618e2cb1decSSalil Mehta hdev->num_msi_left -= alloc; 619e2cb1decSSalil Mehta hdev->num_msi_used += alloc; 620e2cb1decSSalil Mehta 621e2cb1decSSalil Mehta return alloc; 622e2cb1decSSalil Mehta } 623e2cb1decSSalil Mehta 624e2cb1decSSalil Mehta static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 625e2cb1decSSalil Mehta { 626e2cb1decSSalil Mehta int i; 627e2cb1decSSalil Mehta 628e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 629e2cb1decSSalil Mehta if (vector == hdev->vector_irq[i]) 630e2cb1decSSalil Mehta return i; 631e2cb1decSSalil Mehta 632e2cb1decSSalil Mehta return -EINVAL; 633e2cb1decSSalil Mehta } 634e2cb1decSSalil Mehta 635374ad291SJian Shen static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 636374ad291SJian Shen const u8 hfunc, const u8 *key) 637374ad291SJian Shen { 638374ad291SJian Shen struct hclgevf_rss_config_cmd *req; 639ebaf1908SWeihang Li unsigned int key_offset = 0; 6406befad60SJie Wang struct hclge_desc desc; 6413caf772bSYufeng Mo int key_counts; 642374ad291SJian Shen int key_size; 643374ad291SJian Shen int ret; 644374ad291SJian Shen 6453caf772bSYufeng Mo key_counts = HCLGEVF_RSS_KEY_SIZE; 646374ad291SJian Shen req = (struct hclgevf_rss_config_cmd *)desc.data; 647374ad291SJian Shen 6483caf772bSYufeng Mo while (key_counts) { 649374ad291SJian Shen hclgevf_cmd_setup_basic_desc(&desc, 650374ad291SJian Shen HCLGEVF_OPC_RSS_GENERIC_CONFIG, 651374ad291SJian Shen false); 652374ad291SJian Shen 653374ad291SJian Shen req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 654374ad291SJian Shen req->hash_config |= 655374ad291SJian Shen (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 656374ad291SJian Shen 6573caf772bSYufeng Mo key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts); 658374ad291SJian Shen memcpy(req->hash_key, 659374ad291SJian Shen key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 660374ad291SJian Shen 6613caf772bSYufeng Mo key_counts -= key_size; 6623caf772bSYufeng Mo key_offset++; 663374ad291SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 664374ad291SJian Shen if (ret) { 665374ad291SJian Shen dev_err(&hdev->pdev->dev, 666374ad291SJian Shen "Configure RSS config fail, status = %d\n", 667374ad291SJian Shen ret); 668374ad291SJian Shen return ret; 669374ad291SJian Shen } 670374ad291SJian Shen } 671374ad291SJian Shen 672374ad291SJian Shen return 0; 673374ad291SJian Shen } 674374ad291SJian Shen 675e2cb1decSSalil Mehta static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 676e2cb1decSSalil Mehta { 677e2cb1decSSalil Mehta return HCLGEVF_RSS_KEY_SIZE; 678e2cb1decSSalil Mehta } 679e2cb1decSSalil Mehta 680e2cb1decSSalil Mehta static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 681e2cb1decSSalil Mehta { 682e2cb1decSSalil Mehta const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 683e2cb1decSSalil Mehta struct hclgevf_rss_indirection_table_cmd *req; 6846befad60SJie Wang struct hclge_desc desc; 68587ce161eSGuangbin Huang int rss_cfg_tbl_num; 686e2cb1decSSalil Mehta int status; 687e2cb1decSSalil Mehta int i, j; 688e2cb1decSSalil Mehta 689e2cb1decSSalil Mehta req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 69087ce161eSGuangbin Huang rss_cfg_tbl_num = hdev->ae_dev->dev_specs.rss_ind_tbl_size / 69187ce161eSGuangbin Huang HCLGEVF_RSS_CFG_TBL_SIZE; 692e2cb1decSSalil Mehta 69387ce161eSGuangbin Huang for (i = 0; i < rss_cfg_tbl_num; i++) { 694e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 695e2cb1decSSalil Mehta false); 69655ff3ed5SJian Shen req->start_table_index = 69755ff3ed5SJian Shen cpu_to_le16(i * HCLGEVF_RSS_CFG_TBL_SIZE); 69855ff3ed5SJian Shen req->rss_set_bitmap = cpu_to_le16(HCLGEVF_RSS_SET_BITMAP_MSK); 699e2cb1decSSalil Mehta for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 700e2cb1decSSalil Mehta req->rss_result[j] = 701e2cb1decSSalil Mehta indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 702e2cb1decSSalil Mehta 703e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 704e2cb1decSSalil Mehta if (status) { 705e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 706e2cb1decSSalil Mehta "VF failed(=%d) to set RSS indirection table\n", 707e2cb1decSSalil Mehta status); 708e2cb1decSSalil Mehta return status; 709e2cb1decSSalil Mehta } 710e2cb1decSSalil Mehta } 711e2cb1decSSalil Mehta 712e2cb1decSSalil Mehta return 0; 713e2cb1decSSalil Mehta } 714e2cb1decSSalil Mehta 715e2cb1decSSalil Mehta static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 716e2cb1decSSalil Mehta { 717e2cb1decSSalil Mehta struct hclgevf_rss_tc_mode_cmd *req; 718e2cb1decSSalil Mehta u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 719e2cb1decSSalil Mehta u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 720e2cb1decSSalil Mehta u16 tc_size[HCLGEVF_MAX_TC_NUM]; 7216befad60SJie Wang struct hclge_desc desc; 722e2cb1decSSalil Mehta u16 roundup_size; 723ebaf1908SWeihang Li unsigned int i; 7242adb8187SHuazhong Tan int status; 725e2cb1decSSalil Mehta 726e2cb1decSSalil Mehta req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 727e2cb1decSSalil Mehta 728e2cb1decSSalil Mehta roundup_size = roundup_pow_of_two(rss_size); 729e2cb1decSSalil Mehta roundup_size = ilog2(roundup_size); 730e2cb1decSSalil Mehta 731e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 7328d2ad993SGuangbin Huang tc_valid[i] = 1; 733e2cb1decSSalil Mehta tc_size[i] = roundup_size; 7348d2ad993SGuangbin Huang tc_offset[i] = (hdev->hw_tc_map & BIT(i)) ? rss_size * i : 0; 735e2cb1decSSalil Mehta } 736e2cb1decSSalil Mehta 737e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 738e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 73955ff3ed5SJian Shen u16 mode = 0; 74055ff3ed5SJian Shen 74155ff3ed5SJian Shen hnae3_set_bit(mode, HCLGEVF_RSS_TC_VALID_B, 742e2cb1decSSalil Mehta (tc_valid[i] & 0x1)); 74355ff3ed5SJian Shen hnae3_set_field(mode, HCLGEVF_RSS_TC_SIZE_M, 744e2cb1decSSalil Mehta HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 74533a8f764SGuojia Liao hnae3_set_bit(mode, HCLGEVF_RSS_TC_SIZE_MSB_B, 74633a8f764SGuojia Liao tc_size[i] >> HCLGEVF_RSS_TC_SIZE_MSB_OFFSET & 74733a8f764SGuojia Liao 0x1); 74855ff3ed5SJian Shen hnae3_set_field(mode, HCLGEVF_RSS_TC_OFFSET_M, 749e2cb1decSSalil Mehta HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 75055ff3ed5SJian Shen 75155ff3ed5SJian Shen req->rss_tc_mode[i] = cpu_to_le16(mode); 752e2cb1decSSalil Mehta } 753e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 754e2cb1decSSalil Mehta if (status) 755e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 756e2cb1decSSalil Mehta "VF failed(=%d) to set rss tc mode\n", status); 757e2cb1decSSalil Mehta 758e2cb1decSSalil Mehta return status; 759e2cb1decSSalil Mehta } 760e2cb1decSSalil Mehta 761a638b1d8SJian Shen /* for revision 0x20, vf shared the same rss config with pf */ 762a638b1d8SJian Shen static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 763a638b1d8SJian Shen { 764a638b1d8SJian Shen #define HCLGEVF_RSS_MBX_RESP_LEN 8 765a638b1d8SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 766a638b1d8SJian Shen u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 767d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 768a638b1d8SJian Shen u16 msg_num, hash_key_index; 769a638b1d8SJian Shen u8 index; 770a638b1d8SJian Shen int ret; 771a638b1d8SJian Shen 772d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_RSS_KEY, 0); 773a638b1d8SJian Shen msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 774a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN; 775a638b1d8SJian Shen for (index = 0; index < msg_num; index++) { 776d3410018SYufeng Mo send_msg.data[0] = index; 777d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 778a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN); 779a638b1d8SJian Shen if (ret) { 780a638b1d8SJian Shen dev_err(&hdev->pdev->dev, 781a638b1d8SJian Shen "VF get rss hash key from PF failed, ret=%d", 782a638b1d8SJian Shen ret); 783a638b1d8SJian Shen return ret; 784a638b1d8SJian Shen } 785a638b1d8SJian Shen 786a638b1d8SJian Shen hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 787a638b1d8SJian Shen if (index == msg_num - 1) 788a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 789a638b1d8SJian Shen &resp_msg[0], 790a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE - hash_key_index); 791a638b1d8SJian Shen else 792a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 793a638b1d8SJian Shen &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 794a638b1d8SJian Shen } 795a638b1d8SJian Shen 796a638b1d8SJian Shen return 0; 797a638b1d8SJian Shen } 798a638b1d8SJian Shen 799e2cb1decSSalil Mehta static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 800e2cb1decSSalil Mehta u8 *hfunc) 801e2cb1decSSalil Mehta { 802e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 803e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 804a638b1d8SJian Shen int i, ret; 805e2cb1decSSalil Mehta 806295ba232SGuangbin Huang if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 807374ad291SJian Shen /* Get hash algorithm */ 808374ad291SJian Shen if (hfunc) { 809374ad291SJian Shen switch (rss_cfg->hash_algo) { 810374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 811374ad291SJian Shen *hfunc = ETH_RSS_HASH_TOP; 812374ad291SJian Shen break; 813374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 814374ad291SJian Shen *hfunc = ETH_RSS_HASH_XOR; 815374ad291SJian Shen break; 816374ad291SJian Shen default: 817374ad291SJian Shen *hfunc = ETH_RSS_HASH_UNKNOWN; 818374ad291SJian Shen break; 819374ad291SJian Shen } 820374ad291SJian Shen } 821374ad291SJian Shen 822374ad291SJian Shen /* Get the RSS Key required by the user */ 823374ad291SJian Shen if (key) 824374ad291SJian Shen memcpy(key, rss_cfg->rss_hash_key, 825374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 826a638b1d8SJian Shen } else { 827a638b1d8SJian Shen if (hfunc) 828a638b1d8SJian Shen *hfunc = ETH_RSS_HASH_TOP; 829a638b1d8SJian Shen if (key) { 830a638b1d8SJian Shen ret = hclgevf_get_rss_hash_key(hdev); 831a638b1d8SJian Shen if (ret) 832a638b1d8SJian Shen return ret; 833a638b1d8SJian Shen memcpy(key, rss_cfg->rss_hash_key, 834a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE); 835a638b1d8SJian Shen } 836374ad291SJian Shen } 837374ad291SJian Shen 838e2cb1decSSalil Mehta if (indir) 83987ce161eSGuangbin Huang for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 840e2cb1decSSalil Mehta indir[i] = rss_cfg->rss_indirection_tbl[i]; 841e2cb1decSSalil Mehta 842374ad291SJian Shen return 0; 843e2cb1decSSalil Mehta } 844e2cb1decSSalil Mehta 845e184cec5SJian Shen static int hclgevf_parse_rss_hfunc(struct hclgevf_dev *hdev, const u8 hfunc, 846e184cec5SJian Shen u8 *hash_algo) 847e184cec5SJian Shen { 848e184cec5SJian Shen switch (hfunc) { 849e184cec5SJian Shen case ETH_RSS_HASH_TOP: 850e184cec5SJian Shen *hash_algo = HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 851e184cec5SJian Shen return 0; 852e184cec5SJian Shen case ETH_RSS_HASH_XOR: 853e184cec5SJian Shen *hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 854e184cec5SJian Shen return 0; 855e184cec5SJian Shen case ETH_RSS_HASH_NO_CHANGE: 856e184cec5SJian Shen *hash_algo = hdev->rss_cfg.hash_algo; 857e184cec5SJian Shen return 0; 858e184cec5SJian Shen default: 859e184cec5SJian Shen return -EINVAL; 860e184cec5SJian Shen } 861e184cec5SJian Shen } 862e184cec5SJian Shen 863e2cb1decSSalil Mehta static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 864e2cb1decSSalil Mehta const u8 *key, const u8 hfunc) 865e2cb1decSSalil Mehta { 866e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 867e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 868e184cec5SJian Shen u8 hash_algo; 869374ad291SJian Shen int ret, i; 870374ad291SJian Shen 871295ba232SGuangbin Huang if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 872e184cec5SJian Shen ret = hclgevf_parse_rss_hfunc(hdev, hfunc, &hash_algo); 873374ad291SJian Shen if (ret) 874374ad291SJian Shen return ret; 875374ad291SJian Shen 876e184cec5SJian Shen /* Set the RSS Hash Key if specififed by the user */ 877e184cec5SJian Shen if (key) { 878e184cec5SJian Shen ret = hclgevf_set_rss_algo_key(hdev, hash_algo, key); 879e184cec5SJian Shen if (ret) { 880e184cec5SJian Shen dev_err(&hdev->pdev->dev, 881e184cec5SJian Shen "invalid hfunc type %u\n", hfunc); 882e184cec5SJian Shen return ret; 883e184cec5SJian Shen } 884e184cec5SJian Shen 885374ad291SJian Shen /* Update the shadow RSS key with user specified qids */ 886374ad291SJian Shen memcpy(rss_cfg->rss_hash_key, key, 887374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 888e184cec5SJian Shen } else { 889e184cec5SJian Shen ret = hclgevf_set_rss_algo_key(hdev, hash_algo, 890e184cec5SJian Shen rss_cfg->rss_hash_key); 891e184cec5SJian Shen if (ret) 892e184cec5SJian Shen return ret; 893374ad291SJian Shen } 894e184cec5SJian Shen rss_cfg->hash_algo = hash_algo; 895374ad291SJian Shen } 896e2cb1decSSalil Mehta 897e2cb1decSSalil Mehta /* update the shadow RSS table with user specified qids */ 89887ce161eSGuangbin Huang for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 899e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = indir[i]; 900e2cb1decSSalil Mehta 901e2cb1decSSalil Mehta /* update the hardware */ 902e2cb1decSSalil Mehta return hclgevf_set_rss_indir_table(hdev); 903e2cb1decSSalil Mehta } 904e2cb1decSSalil Mehta 905d97b3072SJian Shen static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 906d97b3072SJian Shen { 907d97b3072SJian Shen u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 908d97b3072SJian Shen 909d97b3072SJian Shen if (nfc->data & RXH_L4_B_2_3) 910d97b3072SJian Shen hash_sets |= HCLGEVF_D_PORT_BIT; 911d97b3072SJian Shen else 912d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_PORT_BIT; 913d97b3072SJian Shen 914d97b3072SJian Shen if (nfc->data & RXH_IP_SRC) 915d97b3072SJian Shen hash_sets |= HCLGEVF_S_IP_BIT; 916d97b3072SJian Shen else 917d97b3072SJian Shen hash_sets &= ~HCLGEVF_S_IP_BIT; 918d97b3072SJian Shen 919d97b3072SJian Shen if (nfc->data & RXH_IP_DST) 920d97b3072SJian Shen hash_sets |= HCLGEVF_D_IP_BIT; 921d97b3072SJian Shen else 922d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_IP_BIT; 923d97b3072SJian Shen 924d97b3072SJian Shen if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 925d97b3072SJian Shen hash_sets |= HCLGEVF_V_TAG_BIT; 926d97b3072SJian Shen 927d97b3072SJian Shen return hash_sets; 928d97b3072SJian Shen } 929d97b3072SJian Shen 9305fd0e7b4SHuazhong Tan static int hclgevf_init_rss_tuple_cmd(struct hnae3_handle *handle, 9315fd0e7b4SHuazhong Tan struct ethtool_rxnfc *nfc, 9325fd0e7b4SHuazhong Tan struct hclgevf_rss_input_tuple_cmd *req) 933d97b3072SJian Shen { 934d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 935d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 936d97b3072SJian Shen u8 tuple_sets; 937d97b3072SJian Shen 938d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 939d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 940d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 941d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 942d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 943d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 944d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 945d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 946d97b3072SJian Shen 947d97b3072SJian Shen tuple_sets = hclgevf_get_rss_hash_bits(nfc); 948d97b3072SJian Shen switch (nfc->flow_type) { 949d97b3072SJian Shen case TCP_V4_FLOW: 950d97b3072SJian Shen req->ipv4_tcp_en = tuple_sets; 951d97b3072SJian Shen break; 952d97b3072SJian Shen case TCP_V6_FLOW: 953d97b3072SJian Shen req->ipv6_tcp_en = tuple_sets; 954d97b3072SJian Shen break; 955d97b3072SJian Shen case UDP_V4_FLOW: 956d97b3072SJian Shen req->ipv4_udp_en = tuple_sets; 957d97b3072SJian Shen break; 958d97b3072SJian Shen case UDP_V6_FLOW: 959d97b3072SJian Shen req->ipv6_udp_en = tuple_sets; 960d97b3072SJian Shen break; 961d97b3072SJian Shen case SCTP_V4_FLOW: 962d97b3072SJian Shen req->ipv4_sctp_en = tuple_sets; 963d97b3072SJian Shen break; 964d97b3072SJian Shen case SCTP_V6_FLOW: 965ab6e32d2SJian Shen if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 && 966ab6e32d2SJian Shen (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3))) 967d97b3072SJian Shen return -EINVAL; 968d97b3072SJian Shen 969d97b3072SJian Shen req->ipv6_sctp_en = tuple_sets; 970d97b3072SJian Shen break; 971d97b3072SJian Shen case IPV4_FLOW: 972d97b3072SJian Shen req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 973d97b3072SJian Shen break; 974d97b3072SJian Shen case IPV6_FLOW: 975d97b3072SJian Shen req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 976d97b3072SJian Shen break; 977d97b3072SJian Shen default: 978d97b3072SJian Shen return -EINVAL; 979d97b3072SJian Shen } 980d97b3072SJian Shen 9815fd0e7b4SHuazhong Tan return 0; 9825fd0e7b4SHuazhong Tan } 9835fd0e7b4SHuazhong Tan 9845fd0e7b4SHuazhong Tan static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 9855fd0e7b4SHuazhong Tan struct ethtool_rxnfc *nfc) 9865fd0e7b4SHuazhong Tan { 9875fd0e7b4SHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 9885fd0e7b4SHuazhong Tan struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 9895fd0e7b4SHuazhong Tan struct hclgevf_rss_input_tuple_cmd *req; 9906befad60SJie Wang struct hclge_desc desc; 9915fd0e7b4SHuazhong Tan int ret; 9925fd0e7b4SHuazhong Tan 9935fd0e7b4SHuazhong Tan if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9945fd0e7b4SHuazhong Tan return -EOPNOTSUPP; 9955fd0e7b4SHuazhong Tan 9965fd0e7b4SHuazhong Tan if (nfc->data & 9975fd0e7b4SHuazhong Tan ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 9985fd0e7b4SHuazhong Tan return -EINVAL; 9995fd0e7b4SHuazhong Tan 10005fd0e7b4SHuazhong Tan req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 10015fd0e7b4SHuazhong Tan hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 10025fd0e7b4SHuazhong Tan 10035fd0e7b4SHuazhong Tan ret = hclgevf_init_rss_tuple_cmd(handle, nfc, req); 10045fd0e7b4SHuazhong Tan if (ret) { 10055fd0e7b4SHuazhong Tan dev_err(&hdev->pdev->dev, 10065fd0e7b4SHuazhong Tan "failed to init rss tuple cmd, ret = %d\n", ret); 10075fd0e7b4SHuazhong Tan return ret; 10085fd0e7b4SHuazhong Tan } 10095fd0e7b4SHuazhong Tan 1010d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1011d97b3072SJian Shen if (ret) { 1012d97b3072SJian Shen dev_err(&hdev->pdev->dev, 1013d97b3072SJian Shen "Set rss tuple fail, status = %d\n", ret); 1014d97b3072SJian Shen return ret; 1015d97b3072SJian Shen } 1016d97b3072SJian Shen 1017d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 1018d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 1019d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 1020d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 1021d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 1022d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 1023d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 1024d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 1025d97b3072SJian Shen return 0; 1026d97b3072SJian Shen } 1027d97b3072SJian Shen 102873f7767eSJian Shen static int hclgevf_get_rss_tuple_by_flow_type(struct hclgevf_dev *hdev, 102973f7767eSJian Shen int flow_type, u8 *tuple_sets) 103073f7767eSJian Shen { 103173f7767eSJian Shen switch (flow_type) { 103273f7767eSJian Shen case TCP_V4_FLOW: 103373f7767eSJian Shen *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_tcp_en; 103473f7767eSJian Shen break; 103573f7767eSJian Shen case UDP_V4_FLOW: 103673f7767eSJian Shen *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_udp_en; 103773f7767eSJian Shen break; 103873f7767eSJian Shen case TCP_V6_FLOW: 103973f7767eSJian Shen *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_tcp_en; 104073f7767eSJian Shen break; 104173f7767eSJian Shen case UDP_V6_FLOW: 104273f7767eSJian Shen *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_udp_en; 104373f7767eSJian Shen break; 104473f7767eSJian Shen case SCTP_V4_FLOW: 104573f7767eSJian Shen *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_sctp_en; 104673f7767eSJian Shen break; 104773f7767eSJian Shen case SCTP_V6_FLOW: 104873f7767eSJian Shen *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_sctp_en; 104973f7767eSJian Shen break; 105073f7767eSJian Shen case IPV4_FLOW: 105173f7767eSJian Shen case IPV6_FLOW: 105273f7767eSJian Shen *tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 105373f7767eSJian Shen break; 105473f7767eSJian Shen default: 105573f7767eSJian Shen return -EINVAL; 105673f7767eSJian Shen } 105773f7767eSJian Shen 105873f7767eSJian Shen return 0; 105973f7767eSJian Shen } 106073f7767eSJian Shen 106173f7767eSJian Shen static u64 hclgevf_convert_rss_tuple(u8 tuple_sets) 106273f7767eSJian Shen { 106373f7767eSJian Shen u64 tuple_data = 0; 106473f7767eSJian Shen 106573f7767eSJian Shen if (tuple_sets & HCLGEVF_D_PORT_BIT) 106673f7767eSJian Shen tuple_data |= RXH_L4_B_2_3; 106773f7767eSJian Shen if (tuple_sets & HCLGEVF_S_PORT_BIT) 106873f7767eSJian Shen tuple_data |= RXH_L4_B_0_1; 106973f7767eSJian Shen if (tuple_sets & HCLGEVF_D_IP_BIT) 107073f7767eSJian Shen tuple_data |= RXH_IP_DST; 107173f7767eSJian Shen if (tuple_sets & HCLGEVF_S_IP_BIT) 107273f7767eSJian Shen tuple_data |= RXH_IP_SRC; 107373f7767eSJian Shen 107473f7767eSJian Shen return tuple_data; 107573f7767eSJian Shen } 107673f7767eSJian Shen 1077d97b3072SJian Shen static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 1078d97b3072SJian Shen struct ethtool_rxnfc *nfc) 1079d97b3072SJian Shen { 1080d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1081d97b3072SJian Shen u8 tuple_sets; 108273f7767eSJian Shen int ret; 1083d97b3072SJian Shen 1084295ba232SGuangbin Huang if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 1085d97b3072SJian Shen return -EOPNOTSUPP; 1086d97b3072SJian Shen 1087d97b3072SJian Shen nfc->data = 0; 1088d97b3072SJian Shen 108973f7767eSJian Shen ret = hclgevf_get_rss_tuple_by_flow_type(hdev, nfc->flow_type, 109073f7767eSJian Shen &tuple_sets); 109173f7767eSJian Shen if (ret || !tuple_sets) 109273f7767eSJian Shen return ret; 1093d97b3072SJian Shen 109473f7767eSJian Shen nfc->data = hclgevf_convert_rss_tuple(tuple_sets); 1095d97b3072SJian Shen 1096d97b3072SJian Shen return 0; 1097d97b3072SJian Shen } 1098d97b3072SJian Shen 1099d97b3072SJian Shen static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 1100d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg) 1101d97b3072SJian Shen { 1102d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 11036befad60SJie Wang struct hclge_desc desc; 1104d97b3072SJian Shen int ret; 1105d97b3072SJian Shen 1106d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 1107d97b3072SJian Shen 1108d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 1109d97b3072SJian Shen 1110d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 1111d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 1112d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 1113d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 1114d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 1115d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 1116d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 1117d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 1118d97b3072SJian Shen 1119d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1120d97b3072SJian Shen if (ret) 1121d97b3072SJian Shen dev_err(&hdev->pdev->dev, 1122d97b3072SJian Shen "Configure rss input fail, status = %d\n", ret); 1123d97b3072SJian Shen return ret; 1124d97b3072SJian Shen } 1125d97b3072SJian Shen 1126e2cb1decSSalil Mehta static int hclgevf_get_tc_size(struct hnae3_handle *handle) 1127e2cb1decSSalil Mehta { 1128e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1129e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1130e2cb1decSSalil Mehta 1131e2cb1decSSalil Mehta return rss_cfg->rss_size; 1132e2cb1decSSalil Mehta } 1133e2cb1decSSalil Mehta 1134e2cb1decSSalil Mehta static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 1135b204bc74SPeng Li int vector_id, 1136e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1137e2cb1decSSalil Mehta { 1138e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1139d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1140e2cb1decSSalil Mehta struct hnae3_ring_chain_node *node; 1141e2cb1decSSalil Mehta int status; 1142d3410018SYufeng Mo int i = 0; 1143e2cb1decSSalil Mehta 1144d3410018SYufeng Mo memset(&send_msg, 0, sizeof(send_msg)); 1145d3410018SYufeng Mo send_msg.code = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 1146c09ba484SPeng Li HCLGE_MBX_UNMAP_RING_TO_VECTOR; 1147d3410018SYufeng Mo send_msg.vector_id = vector_id; 1148e2cb1decSSalil Mehta 1149e2cb1decSSalil Mehta for (node = ring_chain; node; node = node->next) { 1150d3410018SYufeng Mo send_msg.param[i].ring_type = 1151e4e87715SPeng Li hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 1152d3410018SYufeng Mo 1153d3410018SYufeng Mo send_msg.param[i].tqp_index = node->tqp_index; 1154d3410018SYufeng Mo send_msg.param[i].int_gl_index = 1155d3410018SYufeng Mo hnae3_get_field(node->int_gl_idx, 115679eee410SFuyun Liang HNAE3_RING_GL_IDX_M, 115779eee410SFuyun Liang HNAE3_RING_GL_IDX_S); 115879eee410SFuyun Liang 11595d02a58dSYunsheng Lin i++; 1160d3410018SYufeng Mo if (i == HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM || !node->next) { 1161d3410018SYufeng Mo send_msg.ring_num = i; 1162e2cb1decSSalil Mehta 1163d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, false, 1164d3410018SYufeng Mo NULL, 0); 1165e2cb1decSSalil Mehta if (status) { 1166e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1167e2cb1decSSalil Mehta "Map TQP fail, status is %d.\n", 1168e2cb1decSSalil Mehta status); 1169e2cb1decSSalil Mehta return status; 1170e2cb1decSSalil Mehta } 1171e2cb1decSSalil Mehta i = 0; 1172e2cb1decSSalil Mehta } 1173e2cb1decSSalil Mehta } 1174e2cb1decSSalil Mehta 1175e2cb1decSSalil Mehta return 0; 1176e2cb1decSSalil Mehta } 1177e2cb1decSSalil Mehta 1178e2cb1decSSalil Mehta static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1179e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1180e2cb1decSSalil Mehta { 1181b204bc74SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1182b204bc74SPeng Li int vector_id; 1183b204bc74SPeng Li 1184b204bc74SPeng Li vector_id = hclgevf_get_vector_index(hdev, vector); 1185b204bc74SPeng Li if (vector_id < 0) { 1186b204bc74SPeng Li dev_err(&handle->pdev->dev, 1187b204bc74SPeng Li "Get vector index fail. ret =%d\n", vector_id); 1188b204bc74SPeng Li return vector_id; 1189b204bc74SPeng Li } 1190b204bc74SPeng Li 1191b204bc74SPeng Li return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1192e2cb1decSSalil Mehta } 1193e2cb1decSSalil Mehta 1194e2cb1decSSalil Mehta static int hclgevf_unmap_ring_from_vector( 1195e2cb1decSSalil Mehta struct hnae3_handle *handle, 1196e2cb1decSSalil Mehta int vector, 1197e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1198e2cb1decSSalil Mehta { 1199e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1200e2cb1decSSalil Mehta int ret, vector_id; 1201e2cb1decSSalil Mehta 1202dea846e8SHuazhong Tan if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1203dea846e8SHuazhong Tan return 0; 1204dea846e8SHuazhong Tan 1205e2cb1decSSalil Mehta vector_id = hclgevf_get_vector_index(hdev, vector); 1206e2cb1decSSalil Mehta if (vector_id < 0) { 1207e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1208e2cb1decSSalil Mehta "Get vector index fail. ret =%d\n", vector_id); 1209e2cb1decSSalil Mehta return vector_id; 1210e2cb1decSSalil Mehta } 1211e2cb1decSSalil Mehta 1212b204bc74SPeng Li ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 12130d3e6631SYunsheng Lin if (ret) 1214e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1215e2cb1decSSalil Mehta "Unmap ring from vector fail. vector=%d, ret =%d\n", 1216e2cb1decSSalil Mehta vector_id, 1217e2cb1decSSalil Mehta ret); 12180d3e6631SYunsheng Lin 1219e2cb1decSSalil Mehta return ret; 1220e2cb1decSSalil Mehta } 1221e2cb1decSSalil Mehta 12220d3e6631SYunsheng Lin static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 12230d3e6631SYunsheng Lin { 12240d3e6631SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 122503718db9SYunsheng Lin int vector_id; 12260d3e6631SYunsheng Lin 122703718db9SYunsheng Lin vector_id = hclgevf_get_vector_index(hdev, vector); 122803718db9SYunsheng Lin if (vector_id < 0) { 122903718db9SYunsheng Lin dev_err(&handle->pdev->dev, 123003718db9SYunsheng Lin "hclgevf_put_vector get vector index fail. ret =%d\n", 123103718db9SYunsheng Lin vector_id); 123203718db9SYunsheng Lin return vector_id; 123303718db9SYunsheng Lin } 123403718db9SYunsheng Lin 123503718db9SYunsheng Lin hclgevf_free_vector(hdev, vector_id); 1236e2cb1decSSalil Mehta 1237e2cb1decSSalil Mehta return 0; 1238e2cb1decSSalil Mehta } 1239e2cb1decSSalil Mehta 12403b75c3dfSPeng Li static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1241e196ec75SJian Shen bool en_uc_pmc, bool en_mc_pmc, 1242f01f5559SJian Shen bool en_bc_pmc) 1243e2cb1decSSalil Mehta { 12445e7414cdSJian Shen struct hnae3_handle *handle = &hdev->nic; 1245d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1246f01f5559SJian Shen int ret; 1247e2cb1decSSalil Mehta 1248d3410018SYufeng Mo memset(&send_msg, 0, sizeof(send_msg)); 1249d3410018SYufeng Mo send_msg.code = HCLGE_MBX_SET_PROMISC_MODE; 1250d3410018SYufeng Mo send_msg.en_bc = en_bc_pmc ? 1 : 0; 1251d3410018SYufeng Mo send_msg.en_uc = en_uc_pmc ? 1 : 0; 1252d3410018SYufeng Mo send_msg.en_mc = en_mc_pmc ? 1 : 0; 12535e7414cdSJian Shen send_msg.en_limit_promisc = test_bit(HNAE3_PFLAG_LIMIT_PROMISC, 12545e7414cdSJian Shen &handle->priv_flags) ? 1 : 0; 1255e2cb1decSSalil Mehta 1256d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1257f01f5559SJian Shen if (ret) 1258e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1259f01f5559SJian Shen "Set promisc mode fail, status is %d.\n", ret); 1260e2cb1decSSalil Mehta 1261f01f5559SJian Shen return ret; 1262e2cb1decSSalil Mehta } 1263e2cb1decSSalil Mehta 1264e196ec75SJian Shen static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 1265e196ec75SJian Shen bool en_mc_pmc) 1266e2cb1decSSalil Mehta { 1267e196ec75SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1268e196ec75SJian Shen bool en_bc_pmc; 1269e196ec75SJian Shen 1270295ba232SGuangbin Huang en_bc_pmc = hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2; 1271e196ec75SJian Shen 1272e196ec75SJian Shen return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc, 1273e196ec75SJian Shen en_bc_pmc); 1274e2cb1decSSalil Mehta } 1275e2cb1decSSalil Mehta 1276c631c696SJian Shen static void hclgevf_request_update_promisc_mode(struct hnae3_handle *handle) 1277c631c696SJian Shen { 1278c631c696SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1279c631c696SJian Shen 1280c631c696SJian Shen set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 12815e7414cdSJian Shen hclgevf_task_schedule(hdev, 0); 1282c631c696SJian Shen } 1283c631c696SJian Shen 1284c631c696SJian Shen static void hclgevf_sync_promisc_mode(struct hclgevf_dev *hdev) 1285c631c696SJian Shen { 1286c631c696SJian Shen struct hnae3_handle *handle = &hdev->nic; 1287c631c696SJian Shen bool en_uc_pmc = handle->netdev_flags & HNAE3_UPE; 1288c631c696SJian Shen bool en_mc_pmc = handle->netdev_flags & HNAE3_MPE; 1289c631c696SJian Shen int ret; 1290c631c696SJian Shen 1291c631c696SJian Shen if (test_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state)) { 1292c631c696SJian Shen ret = hclgevf_set_promisc_mode(handle, en_uc_pmc, en_mc_pmc); 1293c631c696SJian Shen if (!ret) 1294c631c696SJian Shen clear_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 1295c631c696SJian Shen } 1296c631c696SJian Shen } 1297c631c696SJian Shen 12988fa86551SYufeng Mo static int hclgevf_tqp_enable_cmd_send(struct hclgevf_dev *hdev, u16 tqp_id, 12998fa86551SYufeng Mo u16 stream_id, bool enable) 1300e2cb1decSSalil Mehta { 1301e2cb1decSSalil Mehta struct hclgevf_cfg_com_tqp_queue_cmd *req; 13026befad60SJie Wang struct hclge_desc desc; 1303e2cb1decSSalil Mehta 1304e2cb1decSSalil Mehta req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1305e2cb1decSSalil Mehta 1306e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1307e2cb1decSSalil Mehta false); 1308e2cb1decSSalil Mehta req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1309e2cb1decSSalil Mehta req->stream_id = cpu_to_le16(stream_id); 1310ebaf1908SWeihang Li if (enable) 1311ebaf1908SWeihang Li req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 1312e2cb1decSSalil Mehta 13138fa86551SYufeng Mo return hclgevf_cmd_send(&hdev->hw, &desc, 1); 13148fa86551SYufeng Mo } 1315e2cb1decSSalil Mehta 13168fa86551SYufeng Mo static int hclgevf_tqp_enable(struct hnae3_handle *handle, bool enable) 13178fa86551SYufeng Mo { 13188fa86551SYufeng Mo struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 13198fa86551SYufeng Mo int ret; 13208fa86551SYufeng Mo u16 i; 13218fa86551SYufeng Mo 13228fa86551SYufeng Mo for (i = 0; i < handle->kinfo.num_tqps; i++) { 13238fa86551SYufeng Mo ret = hclgevf_tqp_enable_cmd_send(hdev, i, 0, enable); 13248fa86551SYufeng Mo if (ret) 13258fa86551SYufeng Mo return ret; 13268fa86551SYufeng Mo } 13278fa86551SYufeng Mo 13288fa86551SYufeng Mo return 0; 1329e2cb1decSSalil Mehta } 1330e2cb1decSSalil Mehta 1331e2cb1decSSalil Mehta static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1332e2cb1decSSalil Mehta { 1333b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1334e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 1335e2cb1decSSalil Mehta int i; 1336e2cb1decSSalil Mehta 1337b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 1338b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1339e2cb1decSSalil Mehta memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1340e2cb1decSSalil Mehta } 1341e2cb1decSSalil Mehta } 1342e2cb1decSSalil Mehta 13438e6de441SHuazhong Tan static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p) 13448e6de441SHuazhong Tan { 1345d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 13468e6de441SHuazhong Tan u8 host_mac[ETH_ALEN]; 13478e6de441SHuazhong Tan int status; 13488e6de441SHuazhong Tan 1349d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MAC_ADDR, 0); 1350d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, true, host_mac, 1351d3410018SYufeng Mo ETH_ALEN); 13528e6de441SHuazhong Tan if (status) { 13538e6de441SHuazhong Tan dev_err(&hdev->pdev->dev, 13548e6de441SHuazhong Tan "fail to get VF MAC from host %d", status); 13558e6de441SHuazhong Tan return status; 13568e6de441SHuazhong Tan } 13578e6de441SHuazhong Tan 13588e6de441SHuazhong Tan ether_addr_copy(p, host_mac); 13598e6de441SHuazhong Tan 13608e6de441SHuazhong Tan return 0; 13618e6de441SHuazhong Tan } 13628e6de441SHuazhong Tan 1363e2cb1decSSalil Mehta static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1364e2cb1decSSalil Mehta { 1365e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 13668e6de441SHuazhong Tan u8 host_mac_addr[ETH_ALEN]; 1367e2cb1decSSalil Mehta 13688e6de441SHuazhong Tan if (hclgevf_get_host_mac_addr(hdev, host_mac_addr)) 13698e6de441SHuazhong Tan return; 13708e6de441SHuazhong Tan 13718e6de441SHuazhong Tan hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr); 13728e6de441SHuazhong Tan if (hdev->has_pf_mac) 13738e6de441SHuazhong Tan ether_addr_copy(p, host_mac_addr); 13748e6de441SHuazhong Tan else 1375e2cb1decSSalil Mehta ether_addr_copy(p, hdev->hw.mac.mac_addr); 1376e2cb1decSSalil Mehta } 1377e2cb1decSSalil Mehta 137876660757SJakub Kicinski static int hclgevf_set_mac_addr(struct hnae3_handle *handle, const void *p, 137959098055SFuyun Liang bool is_first) 1380e2cb1decSSalil Mehta { 1381e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1382e2cb1decSSalil Mehta u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1383d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1384e2cb1decSSalil Mehta u8 *new_mac_addr = (u8 *)p; 1385e2cb1decSSalil Mehta int status; 1386e2cb1decSSalil Mehta 1387d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 0); 1388ee4bcd3bSJian Shen send_msg.subcode = HCLGE_MBX_MAC_VLAN_UC_MODIFY; 1389d3410018SYufeng Mo ether_addr_copy(send_msg.data, new_mac_addr); 1390ee4bcd3bSJian Shen if (is_first && !hdev->has_pf_mac) 1391ee4bcd3bSJian Shen eth_zero_addr(&send_msg.data[ETH_ALEN]); 1392ee4bcd3bSJian Shen else 1393d3410018SYufeng Mo ether_addr_copy(&send_msg.data[ETH_ALEN], old_mac_addr); 1394d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1395e2cb1decSSalil Mehta if (!status) 1396e2cb1decSSalil Mehta ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1397e2cb1decSSalil Mehta 1398e2cb1decSSalil Mehta return status; 1399e2cb1decSSalil Mehta } 1400e2cb1decSSalil Mehta 1401ee4bcd3bSJian Shen static struct hclgevf_mac_addr_node * 1402ee4bcd3bSJian Shen hclgevf_find_mac_node(struct list_head *list, const u8 *mac_addr) 1403ee4bcd3bSJian Shen { 1404ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp; 1405ee4bcd3bSJian Shen 1406ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, list, node) 1407ee4bcd3bSJian Shen if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 1408ee4bcd3bSJian Shen return mac_node; 1409ee4bcd3bSJian Shen 1410ee4bcd3bSJian Shen return NULL; 1411ee4bcd3bSJian Shen } 1412ee4bcd3bSJian Shen 1413ee4bcd3bSJian Shen static void hclgevf_update_mac_node(struct hclgevf_mac_addr_node *mac_node, 1414ee4bcd3bSJian Shen enum HCLGEVF_MAC_NODE_STATE state) 1415ee4bcd3bSJian Shen { 1416ee4bcd3bSJian Shen switch (state) { 1417ee4bcd3bSJian Shen /* from set_rx_mode or tmp_add_list */ 1418ee4bcd3bSJian Shen case HCLGEVF_MAC_TO_ADD: 1419ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_DEL) 1420ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_ACTIVE; 1421ee4bcd3bSJian Shen break; 1422ee4bcd3bSJian Shen /* only from set_rx_mode */ 1423ee4bcd3bSJian Shen case HCLGEVF_MAC_TO_DEL: 1424ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1425ee4bcd3bSJian Shen list_del(&mac_node->node); 1426ee4bcd3bSJian Shen kfree(mac_node); 1427ee4bcd3bSJian Shen } else { 1428ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_TO_DEL; 1429ee4bcd3bSJian Shen } 1430ee4bcd3bSJian Shen break; 1431ee4bcd3bSJian Shen /* only from tmp_add_list, the mac_node->state won't be 1432ee4bcd3bSJian Shen * HCLGEVF_MAC_ACTIVE 1433ee4bcd3bSJian Shen */ 1434ee4bcd3bSJian Shen case HCLGEVF_MAC_ACTIVE: 1435ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1436ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_ACTIVE; 1437ee4bcd3bSJian Shen break; 1438ee4bcd3bSJian Shen } 1439ee4bcd3bSJian Shen } 1440ee4bcd3bSJian Shen 1441ee4bcd3bSJian Shen static int hclgevf_update_mac_list(struct hnae3_handle *handle, 1442ee4bcd3bSJian Shen enum HCLGEVF_MAC_NODE_STATE state, 1443ee4bcd3bSJian Shen enum HCLGEVF_MAC_ADDR_TYPE mac_type, 1444e2cb1decSSalil Mehta const unsigned char *addr) 1445e2cb1decSSalil Mehta { 1446e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1447ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node; 1448ee4bcd3bSJian Shen struct list_head *list; 1449e2cb1decSSalil Mehta 1450ee4bcd3bSJian Shen list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1451ee4bcd3bSJian Shen &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1452ee4bcd3bSJian Shen 1453ee4bcd3bSJian Shen spin_lock_bh(&hdev->mac_table.mac_list_lock); 1454ee4bcd3bSJian Shen 1455ee4bcd3bSJian Shen /* if the mac addr is already in the mac list, no need to add a new 1456ee4bcd3bSJian Shen * one into it, just check the mac addr state, convert it to a new 1457ee4bcd3bSJian Shen * new state, or just remove it, or do nothing. 1458ee4bcd3bSJian Shen */ 1459ee4bcd3bSJian Shen mac_node = hclgevf_find_mac_node(list, addr); 1460ee4bcd3bSJian Shen if (mac_node) { 1461ee4bcd3bSJian Shen hclgevf_update_mac_node(mac_node, state); 1462ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1463ee4bcd3bSJian Shen return 0; 1464ee4bcd3bSJian Shen } 1465ee4bcd3bSJian Shen /* if this address is never added, unnecessary to delete */ 1466ee4bcd3bSJian Shen if (state == HCLGEVF_MAC_TO_DEL) { 1467ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1468ee4bcd3bSJian Shen return -ENOENT; 1469ee4bcd3bSJian Shen } 1470ee4bcd3bSJian Shen 1471ee4bcd3bSJian Shen mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 1472ee4bcd3bSJian Shen if (!mac_node) { 1473ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1474ee4bcd3bSJian Shen return -ENOMEM; 1475ee4bcd3bSJian Shen } 1476ee4bcd3bSJian Shen 1477ee4bcd3bSJian Shen mac_node->state = state; 1478ee4bcd3bSJian Shen ether_addr_copy(mac_node->mac_addr, addr); 1479ee4bcd3bSJian Shen list_add_tail(&mac_node->node, list); 1480ee4bcd3bSJian Shen 1481ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1482ee4bcd3bSJian Shen return 0; 1483ee4bcd3bSJian Shen } 1484ee4bcd3bSJian Shen 1485ee4bcd3bSJian Shen static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1486ee4bcd3bSJian Shen const unsigned char *addr) 1487ee4bcd3bSJian Shen { 1488ee4bcd3bSJian Shen return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1489ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_UC, addr); 1490e2cb1decSSalil Mehta } 1491e2cb1decSSalil Mehta 1492e2cb1decSSalil Mehta static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1493e2cb1decSSalil Mehta const unsigned char *addr) 1494e2cb1decSSalil Mehta { 1495ee4bcd3bSJian Shen return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1496ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_UC, addr); 1497e2cb1decSSalil Mehta } 1498e2cb1decSSalil Mehta 1499e2cb1decSSalil Mehta static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1500e2cb1decSSalil Mehta const unsigned char *addr) 1501e2cb1decSSalil Mehta { 1502ee4bcd3bSJian Shen return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1503ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_MC, addr); 1504e2cb1decSSalil Mehta } 1505e2cb1decSSalil Mehta 1506e2cb1decSSalil Mehta static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1507e2cb1decSSalil Mehta const unsigned char *addr) 1508e2cb1decSSalil Mehta { 1509ee4bcd3bSJian Shen return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1510ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_MC, addr); 1511ee4bcd3bSJian Shen } 1512e2cb1decSSalil Mehta 1513ee4bcd3bSJian Shen static int hclgevf_add_del_mac_addr(struct hclgevf_dev *hdev, 1514ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, 1515ee4bcd3bSJian Shen enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1516ee4bcd3bSJian Shen { 1517ee4bcd3bSJian Shen struct hclge_vf_to_pf_msg send_msg; 1518ee4bcd3bSJian Shen u8 code, subcode; 1519ee4bcd3bSJian Shen 1520ee4bcd3bSJian Shen if (mac_type == HCLGEVF_MAC_ADDR_UC) { 1521ee4bcd3bSJian Shen code = HCLGE_MBX_SET_UNICAST; 1522ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1523ee4bcd3bSJian Shen subcode = HCLGE_MBX_MAC_VLAN_UC_ADD; 1524ee4bcd3bSJian Shen else 1525ee4bcd3bSJian Shen subcode = HCLGE_MBX_MAC_VLAN_UC_REMOVE; 1526ee4bcd3bSJian Shen } else { 1527ee4bcd3bSJian Shen code = HCLGE_MBX_SET_MULTICAST; 1528ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1529ee4bcd3bSJian Shen subcode = HCLGE_MBX_MAC_VLAN_MC_ADD; 1530ee4bcd3bSJian Shen else 1531ee4bcd3bSJian Shen subcode = HCLGE_MBX_MAC_VLAN_MC_REMOVE; 1532ee4bcd3bSJian Shen } 1533ee4bcd3bSJian Shen 1534ee4bcd3bSJian Shen hclgevf_build_send_msg(&send_msg, code, subcode); 1535ee4bcd3bSJian Shen ether_addr_copy(send_msg.data, mac_node->mac_addr); 1536d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1537e2cb1decSSalil Mehta } 1538e2cb1decSSalil Mehta 1539ee4bcd3bSJian Shen static void hclgevf_config_mac_list(struct hclgevf_dev *hdev, 1540ee4bcd3bSJian Shen struct list_head *list, 1541ee4bcd3bSJian Shen enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1542ee4bcd3bSJian Shen { 15434f331fdaSYufeng Mo char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 1544ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp; 1545ee4bcd3bSJian Shen int ret; 1546ee4bcd3bSJian Shen 1547ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, list, node) { 1548ee4bcd3bSJian Shen ret = hclgevf_add_del_mac_addr(hdev, mac_node, mac_type); 1549ee4bcd3bSJian Shen if (ret) { 15504f331fdaSYufeng Mo hnae3_format_mac_addr(format_mac_addr, 15514f331fdaSYufeng Mo mac_node->mac_addr); 1552ee4bcd3bSJian Shen dev_err(&hdev->pdev->dev, 15534f331fdaSYufeng Mo "failed to configure mac %s, state = %d, ret = %d\n", 15544f331fdaSYufeng Mo format_mac_addr, mac_node->state, ret); 1555ee4bcd3bSJian Shen return; 1556ee4bcd3bSJian Shen } 1557ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1558ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_ACTIVE; 1559ee4bcd3bSJian Shen } else { 1560ee4bcd3bSJian Shen list_del(&mac_node->node); 1561ee4bcd3bSJian Shen kfree(mac_node); 1562ee4bcd3bSJian Shen } 1563ee4bcd3bSJian Shen } 1564ee4bcd3bSJian Shen } 1565ee4bcd3bSJian Shen 1566ee4bcd3bSJian Shen static void hclgevf_sync_from_add_list(struct list_head *add_list, 1567ee4bcd3bSJian Shen struct list_head *mac_list) 1568ee4bcd3bSJian Shen { 1569ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1570ee4bcd3bSJian Shen 1571ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, add_list, node) { 1572ee4bcd3bSJian Shen /* if the mac address from tmp_add_list is not in the 1573ee4bcd3bSJian Shen * uc/mc_mac_list, it means have received a TO_DEL request 1574ee4bcd3bSJian Shen * during the time window of sending mac config request to PF 1575ee4bcd3bSJian Shen * If mac_node state is ACTIVE, then change its state to TO_DEL, 1576ee4bcd3bSJian Shen * then it will be removed at next time. If is TO_ADD, it means 1577ee4bcd3bSJian Shen * send TO_ADD request failed, so just remove the mac node. 1578ee4bcd3bSJian Shen */ 1579ee4bcd3bSJian Shen new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1580ee4bcd3bSJian Shen if (new_node) { 1581ee4bcd3bSJian Shen hclgevf_update_mac_node(new_node, mac_node->state); 1582ee4bcd3bSJian Shen list_del(&mac_node->node); 1583ee4bcd3bSJian Shen kfree(mac_node); 1584ee4bcd3bSJian Shen } else if (mac_node->state == HCLGEVF_MAC_ACTIVE) { 1585ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_TO_DEL; 158649768ce9SBaokun Li list_move_tail(&mac_node->node, mac_list); 1587ee4bcd3bSJian Shen } else { 1588ee4bcd3bSJian Shen list_del(&mac_node->node); 1589ee4bcd3bSJian Shen kfree(mac_node); 1590ee4bcd3bSJian Shen } 1591ee4bcd3bSJian Shen } 1592ee4bcd3bSJian Shen } 1593ee4bcd3bSJian Shen 1594ee4bcd3bSJian Shen static void hclgevf_sync_from_del_list(struct list_head *del_list, 1595ee4bcd3bSJian Shen struct list_head *mac_list) 1596ee4bcd3bSJian Shen { 1597ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1598ee4bcd3bSJian Shen 1599ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, del_list, node) { 1600ee4bcd3bSJian Shen new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1601ee4bcd3bSJian Shen if (new_node) { 1602ee4bcd3bSJian Shen /* If the mac addr is exist in the mac list, it means 1603ee4bcd3bSJian Shen * received a new request TO_ADD during the time window 1604ee4bcd3bSJian Shen * of sending mac addr configurrequest to PF, so just 1605ee4bcd3bSJian Shen * change the mac state to ACTIVE. 1606ee4bcd3bSJian Shen */ 1607ee4bcd3bSJian Shen new_node->state = HCLGEVF_MAC_ACTIVE; 1608ee4bcd3bSJian Shen list_del(&mac_node->node); 1609ee4bcd3bSJian Shen kfree(mac_node); 1610ee4bcd3bSJian Shen } else { 161149768ce9SBaokun Li list_move_tail(&mac_node->node, mac_list); 1612ee4bcd3bSJian Shen } 1613ee4bcd3bSJian Shen } 1614ee4bcd3bSJian Shen } 1615ee4bcd3bSJian Shen 1616ee4bcd3bSJian Shen static void hclgevf_clear_list(struct list_head *list) 1617ee4bcd3bSJian Shen { 1618ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp; 1619ee4bcd3bSJian Shen 1620ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, list, node) { 1621ee4bcd3bSJian Shen list_del(&mac_node->node); 1622ee4bcd3bSJian Shen kfree(mac_node); 1623ee4bcd3bSJian Shen } 1624ee4bcd3bSJian Shen } 1625ee4bcd3bSJian Shen 1626ee4bcd3bSJian Shen static void hclgevf_sync_mac_list(struct hclgevf_dev *hdev, 1627ee4bcd3bSJian Shen enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1628ee4bcd3bSJian Shen { 1629ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1630ee4bcd3bSJian Shen struct list_head tmp_add_list, tmp_del_list; 1631ee4bcd3bSJian Shen struct list_head *list; 1632ee4bcd3bSJian Shen 1633ee4bcd3bSJian Shen INIT_LIST_HEAD(&tmp_add_list); 1634ee4bcd3bSJian Shen INIT_LIST_HEAD(&tmp_del_list); 1635ee4bcd3bSJian Shen 1636ee4bcd3bSJian Shen /* move the mac addr to the tmp_add_list and tmp_del_list, then 1637ee4bcd3bSJian Shen * we can add/delete these mac addr outside the spin lock 1638ee4bcd3bSJian Shen */ 1639ee4bcd3bSJian Shen list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1640ee4bcd3bSJian Shen &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1641ee4bcd3bSJian Shen 1642ee4bcd3bSJian Shen spin_lock_bh(&hdev->mac_table.mac_list_lock); 1643ee4bcd3bSJian Shen 1644ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, list, node) { 1645ee4bcd3bSJian Shen switch (mac_node->state) { 1646ee4bcd3bSJian Shen case HCLGEVF_MAC_TO_DEL: 164749768ce9SBaokun Li list_move_tail(&mac_node->node, &tmp_del_list); 1648ee4bcd3bSJian Shen break; 1649ee4bcd3bSJian Shen case HCLGEVF_MAC_TO_ADD: 1650ee4bcd3bSJian Shen new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 1651ee4bcd3bSJian Shen if (!new_node) 1652ee4bcd3bSJian Shen goto stop_traverse; 1653ee4bcd3bSJian Shen 1654ee4bcd3bSJian Shen ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 1655ee4bcd3bSJian Shen new_node->state = mac_node->state; 1656ee4bcd3bSJian Shen list_add_tail(&new_node->node, &tmp_add_list); 1657ee4bcd3bSJian Shen break; 1658ee4bcd3bSJian Shen default: 1659ee4bcd3bSJian Shen break; 1660ee4bcd3bSJian Shen } 1661ee4bcd3bSJian Shen } 1662ee4bcd3bSJian Shen 1663ee4bcd3bSJian Shen stop_traverse: 1664ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1665ee4bcd3bSJian Shen 1666ee4bcd3bSJian Shen /* delete first, in order to get max mac table space for adding */ 1667ee4bcd3bSJian Shen hclgevf_config_mac_list(hdev, &tmp_del_list, mac_type); 1668ee4bcd3bSJian Shen hclgevf_config_mac_list(hdev, &tmp_add_list, mac_type); 1669ee4bcd3bSJian Shen 1670ee4bcd3bSJian Shen /* if some mac addresses were added/deleted fail, move back to the 1671ee4bcd3bSJian Shen * mac_list, and retry at next time. 1672ee4bcd3bSJian Shen */ 1673ee4bcd3bSJian Shen spin_lock_bh(&hdev->mac_table.mac_list_lock); 1674ee4bcd3bSJian Shen 1675ee4bcd3bSJian Shen hclgevf_sync_from_del_list(&tmp_del_list, list); 1676ee4bcd3bSJian Shen hclgevf_sync_from_add_list(&tmp_add_list, list); 1677ee4bcd3bSJian Shen 1678ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1679ee4bcd3bSJian Shen } 1680ee4bcd3bSJian Shen 1681ee4bcd3bSJian Shen static void hclgevf_sync_mac_table(struct hclgevf_dev *hdev) 1682ee4bcd3bSJian Shen { 1683ee4bcd3bSJian Shen hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_UC); 1684ee4bcd3bSJian Shen hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_MC); 1685ee4bcd3bSJian Shen } 1686ee4bcd3bSJian Shen 1687ee4bcd3bSJian Shen static void hclgevf_uninit_mac_list(struct hclgevf_dev *hdev) 1688ee4bcd3bSJian Shen { 1689ee4bcd3bSJian Shen spin_lock_bh(&hdev->mac_table.mac_list_lock); 1690ee4bcd3bSJian Shen 1691ee4bcd3bSJian Shen hclgevf_clear_list(&hdev->mac_table.uc_mac_list); 1692ee4bcd3bSJian Shen hclgevf_clear_list(&hdev->mac_table.mc_mac_list); 1693ee4bcd3bSJian Shen 1694ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1695ee4bcd3bSJian Shen } 1696ee4bcd3bSJian Shen 1697fa6a262aSJian Shen static int hclgevf_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 1698fa6a262aSJian Shen { 1699fa6a262aSJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1700fa6a262aSJian Shen struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 1701fa6a262aSJian Shen struct hclge_vf_to_pf_msg send_msg; 1702fa6a262aSJian Shen 1703fa6a262aSJian Shen if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 1704fa6a262aSJian Shen return -EOPNOTSUPP; 1705fa6a262aSJian Shen 1706fa6a262aSJian Shen hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1707fa6a262aSJian Shen HCLGE_MBX_ENABLE_VLAN_FILTER); 1708fa6a262aSJian Shen send_msg.data[0] = enable ? 1 : 0; 1709fa6a262aSJian Shen 1710fa6a262aSJian Shen return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1711fa6a262aSJian Shen } 1712fa6a262aSJian Shen 1713e2cb1decSSalil Mehta static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1714e2cb1decSSalil Mehta __be16 proto, u16 vlan_id, 1715e2cb1decSSalil Mehta bool is_kill) 1716e2cb1decSSalil Mehta { 1717d3410018SYufeng Mo #define HCLGEVF_VLAN_MBX_IS_KILL_OFFSET 0 1718d3410018SYufeng Mo #define HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET 1 1719d3410018SYufeng Mo #define HCLGEVF_VLAN_MBX_PROTO_OFFSET 3 1720d3410018SYufeng Mo 1721e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1722d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1723fe4144d4SJian Shen int ret; 1724e2cb1decSSalil Mehta 1725b37ce587SYufeng Mo if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1726e2cb1decSSalil Mehta return -EINVAL; 1727e2cb1decSSalil Mehta 1728e2cb1decSSalil Mehta if (proto != htons(ETH_P_8021Q)) 1729e2cb1decSSalil Mehta return -EPROTONOSUPPORT; 1730e2cb1decSSalil Mehta 1731b7b5d25bSGuojia Liao /* When device is resetting or reset failed, firmware is unable to 1732b7b5d25bSGuojia Liao * handle mailbox. Just record the vlan id, and remove it after 1733fe4144d4SJian Shen * reset finished. 1734fe4144d4SJian Shen */ 1735b7b5d25bSGuojia Liao if ((test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 1736b7b5d25bSGuojia Liao test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) && is_kill) { 1737fe4144d4SJian Shen set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1738fe4144d4SJian Shen return -EBUSY; 1739fe4144d4SJian Shen } 1740fe4144d4SJian Shen 1741d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1742d3410018SYufeng Mo HCLGE_MBX_VLAN_FILTER); 1743d3410018SYufeng Mo send_msg.data[HCLGEVF_VLAN_MBX_IS_KILL_OFFSET] = is_kill; 1744d3410018SYufeng Mo memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET], &vlan_id, 1745d3410018SYufeng Mo sizeof(vlan_id)); 1746d3410018SYufeng Mo memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_PROTO_OFFSET], &proto, 1747d3410018SYufeng Mo sizeof(proto)); 174846ee7350SGuojia Liao /* when remove hw vlan filter failed, record the vlan id, 1749fe4144d4SJian Shen * and try to remove it from hw later, to be consistence 1750fe4144d4SJian Shen * with stack. 1751fe4144d4SJian Shen */ 1752d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1753fe4144d4SJian Shen if (is_kill && ret) 1754fe4144d4SJian Shen set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1755fe4144d4SJian Shen 1756fe4144d4SJian Shen return ret; 1757fe4144d4SJian Shen } 1758fe4144d4SJian Shen 1759fe4144d4SJian Shen static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1760fe4144d4SJian Shen { 1761fe4144d4SJian Shen #define HCLGEVF_MAX_SYNC_COUNT 60 1762fe4144d4SJian Shen struct hnae3_handle *handle = &hdev->nic; 1763fe4144d4SJian Shen int ret, sync_cnt = 0; 1764fe4144d4SJian Shen u16 vlan_id; 1765fe4144d4SJian Shen 1766fe4144d4SJian Shen vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1767fe4144d4SJian Shen while (vlan_id != VLAN_N_VID) { 1768fe4144d4SJian Shen ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1769fe4144d4SJian Shen vlan_id, true); 1770fe4144d4SJian Shen if (ret) 1771fe4144d4SJian Shen return; 1772fe4144d4SJian Shen 1773fe4144d4SJian Shen clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1774fe4144d4SJian Shen sync_cnt++; 1775fe4144d4SJian Shen if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1776fe4144d4SJian Shen return; 1777fe4144d4SJian Shen 1778fe4144d4SJian Shen vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1779fe4144d4SJian Shen } 1780e2cb1decSSalil Mehta } 1781e2cb1decSSalil Mehta 1782b2641e2aSYunsheng Lin static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1783b2641e2aSYunsheng Lin { 1784b2641e2aSYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1785d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1786b2641e2aSYunsheng Lin 1787d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1788d3410018SYufeng Mo HCLGE_MBX_VLAN_RX_OFF_CFG); 1789d3410018SYufeng Mo send_msg.data[0] = enable ? 1 : 0; 1790d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1791b2641e2aSYunsheng Lin } 1792b2641e2aSYunsheng Lin 17938fa86551SYufeng Mo static int hclgevf_reset_tqp(struct hnae3_handle *handle) 1794e2cb1decSSalil Mehta { 17958fa86551SYufeng Mo #define HCLGEVF_RESET_ALL_QUEUE_DONE 1U 1796e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1797d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 17988fa86551SYufeng Mo u8 return_status = 0; 17991a426f8bSPeng Li int ret; 18008fa86551SYufeng Mo u16 i; 1801e2cb1decSSalil Mehta 18021a426f8bSPeng Li /* disable vf queue before send queue reset msg to PF */ 18038fa86551SYufeng Mo ret = hclgevf_tqp_enable(handle, false); 18048fa86551SYufeng Mo if (ret) { 18058fa86551SYufeng Mo dev_err(&hdev->pdev->dev, "failed to disable tqp, ret = %d\n", 18068fa86551SYufeng Mo ret); 18077fa6be4fSHuazhong Tan return ret; 18088fa86551SYufeng Mo } 18091a426f8bSPeng Li 1810d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 18118fa86551SYufeng Mo 18128fa86551SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &return_status, 18138fa86551SYufeng Mo sizeof(return_status)); 18148fa86551SYufeng Mo if (ret || return_status == HCLGEVF_RESET_ALL_QUEUE_DONE) 18158fa86551SYufeng Mo return ret; 18168fa86551SYufeng Mo 18178fa86551SYufeng Mo for (i = 1; i < handle->kinfo.num_tqps; i++) { 18188fa86551SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 18198fa86551SYufeng Mo memcpy(send_msg.data, &i, sizeof(i)); 18208fa86551SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 18218fa86551SYufeng Mo if (ret) 18228fa86551SYufeng Mo return ret; 18238fa86551SYufeng Mo } 18248fa86551SYufeng Mo 18258fa86551SYufeng Mo return 0; 1826e2cb1decSSalil Mehta } 1827e2cb1decSSalil Mehta 1828818f1675SYunsheng Lin static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1829818f1675SYunsheng Lin { 1830818f1675SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1831d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1832818f1675SYunsheng Lin 1833d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MTU, 0); 1834d3410018SYufeng Mo memcpy(send_msg.data, &new_mtu, sizeof(new_mtu)); 1835d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1836818f1675SYunsheng Lin } 1837818f1675SYunsheng Lin 18386988eb2aSSalil Mehta static int hclgevf_notify_client(struct hclgevf_dev *hdev, 18396988eb2aSSalil Mehta enum hnae3_reset_notify_type type) 18406988eb2aSSalil Mehta { 18416988eb2aSSalil Mehta struct hnae3_client *client = hdev->nic_client; 18426988eb2aSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 18436a5f6fa3SHuazhong Tan int ret; 18446988eb2aSSalil Mehta 184525d1817cSHuazhong Tan if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 184625d1817cSHuazhong Tan !client) 184725d1817cSHuazhong Tan return 0; 184825d1817cSHuazhong Tan 18496988eb2aSSalil Mehta if (!client->ops->reset_notify) 18506988eb2aSSalil Mehta return -EOPNOTSUPP; 18516988eb2aSSalil Mehta 18526a5f6fa3SHuazhong Tan ret = client->ops->reset_notify(handle, type); 18536a5f6fa3SHuazhong Tan if (ret) 18546a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 18556a5f6fa3SHuazhong Tan type, ret); 18566a5f6fa3SHuazhong Tan 18576a5f6fa3SHuazhong Tan return ret; 18586988eb2aSSalil Mehta } 18596988eb2aSSalil Mehta 1860fe735c84SHuazhong Tan static int hclgevf_notify_roce_client(struct hclgevf_dev *hdev, 1861fe735c84SHuazhong Tan enum hnae3_reset_notify_type type) 1862fe735c84SHuazhong Tan { 1863fe735c84SHuazhong Tan struct hnae3_client *client = hdev->roce_client; 1864fe735c84SHuazhong Tan struct hnae3_handle *handle = &hdev->roce; 1865fe735c84SHuazhong Tan int ret; 1866fe735c84SHuazhong Tan 1867fe735c84SHuazhong Tan if (!test_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state) || !client) 1868fe735c84SHuazhong Tan return 0; 1869fe735c84SHuazhong Tan 1870fe735c84SHuazhong Tan if (!client->ops->reset_notify) 1871fe735c84SHuazhong Tan return -EOPNOTSUPP; 1872fe735c84SHuazhong Tan 1873fe735c84SHuazhong Tan ret = client->ops->reset_notify(handle, type); 1874fe735c84SHuazhong Tan if (ret) 1875fe735c84SHuazhong Tan dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 1876fe735c84SHuazhong Tan type, ret); 1877fe735c84SHuazhong Tan return ret; 1878fe735c84SHuazhong Tan } 1879fe735c84SHuazhong Tan 18806988eb2aSSalil Mehta static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 18816988eb2aSSalil Mehta { 1882aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_US 20000 1883aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_CNT 2000 1884aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1885aa5c4f17SHuazhong Tan (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1886aa5c4f17SHuazhong Tan 1887aa5c4f17SHuazhong Tan u32 val; 1888aa5c4f17SHuazhong Tan int ret; 18896988eb2aSSalil Mehta 1890f28368bbSHuazhong Tan if (hdev->reset_type == HNAE3_VF_RESET) 1891076bb537SJie Wang ret = readl_poll_timeout(hdev->hw.hw.io_base + 189272e2fb07SHuazhong Tan HCLGEVF_VF_RST_ING, val, 189372e2fb07SHuazhong Tan !(val & HCLGEVF_VF_RST_ING_BIT), 189472e2fb07SHuazhong Tan HCLGEVF_RESET_WAIT_US, 189572e2fb07SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 189672e2fb07SHuazhong Tan else 1897076bb537SJie Wang ret = readl_poll_timeout(hdev->hw.hw.io_base + 189872e2fb07SHuazhong Tan HCLGEVF_RST_ING, val, 1899aa5c4f17SHuazhong Tan !(val & HCLGEVF_RST_ING_BITS), 1900aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_US, 1901aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 19026988eb2aSSalil Mehta 19036988eb2aSSalil Mehta /* hardware completion status should be available by this time */ 1904aa5c4f17SHuazhong Tan if (ret) { 1905aa5c4f17SHuazhong Tan dev_err(&hdev->pdev->dev, 19068912fd6aSColin Ian King "couldn't get reset done status from h/w, timeout!\n"); 1907aa5c4f17SHuazhong Tan return ret; 19086988eb2aSSalil Mehta } 19096988eb2aSSalil Mehta 19106988eb2aSSalil Mehta /* we will wait a bit more to let reset of the stack to complete. This 19116988eb2aSSalil Mehta * might happen in case reset assertion was made by PF. Yes, this also 19126988eb2aSSalil Mehta * means we might end up waiting bit more even for VF reset. 19136988eb2aSSalil Mehta */ 19146988eb2aSSalil Mehta msleep(5000); 19156988eb2aSSalil Mehta 19166988eb2aSSalil Mehta return 0; 19176988eb2aSSalil Mehta } 19186988eb2aSSalil Mehta 19196b428b4fSHuazhong Tan static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable) 19206b428b4fSHuazhong Tan { 19216b428b4fSHuazhong Tan u32 reg_val; 19226b428b4fSHuazhong Tan 1923cb413bfaSJie Wang reg_val = hclgevf_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG); 19246b428b4fSHuazhong Tan if (enable) 19256b428b4fSHuazhong Tan reg_val |= HCLGEVF_NIC_SW_RST_RDY; 19266b428b4fSHuazhong Tan else 19276b428b4fSHuazhong Tan reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; 19286b428b4fSHuazhong Tan 1929cb413bfaSJie Wang hclgevf_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, 19306b428b4fSHuazhong Tan reg_val); 19316b428b4fSHuazhong Tan } 19326b428b4fSHuazhong Tan 19336988eb2aSSalil Mehta static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 19346988eb2aSSalil Mehta { 19357a01c897SSalil Mehta int ret; 19367a01c897SSalil Mehta 19376988eb2aSSalil Mehta /* uninitialize the nic client */ 19386a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 19396a5f6fa3SHuazhong Tan if (ret) 19406a5f6fa3SHuazhong Tan return ret; 19416988eb2aSSalil Mehta 19427a01c897SSalil Mehta /* re-initialize the hclge device */ 19439c6f7085SHuazhong Tan ret = hclgevf_reset_hdev(hdev); 19447a01c897SSalil Mehta if (ret) { 19457a01c897SSalil Mehta dev_err(&hdev->pdev->dev, 19467a01c897SSalil Mehta "hclge device re-init failed, VF is disabled!\n"); 19477a01c897SSalil Mehta return ret; 19487a01c897SSalil Mehta } 19496988eb2aSSalil Mehta 19506988eb2aSSalil Mehta /* bring up the nic client again */ 19516a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 19526a5f6fa3SHuazhong Tan if (ret) 19536a5f6fa3SHuazhong Tan return ret; 19546988eb2aSSalil Mehta 19556b428b4fSHuazhong Tan /* clear handshake status with IMP */ 19566b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, false); 19576b428b4fSHuazhong Tan 19581cc9bc6eSHuazhong Tan /* bring up the nic to enable TX/RX again */ 19591cc9bc6eSHuazhong Tan return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 19606988eb2aSSalil Mehta } 19616988eb2aSSalil Mehta 1962dea846e8SHuazhong Tan static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1963dea846e8SHuazhong Tan { 1964ada13ee3SHuazhong Tan #define HCLGEVF_RESET_SYNC_TIME 100 1965ada13ee3SHuazhong Tan 1966f28368bbSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FUNC_RESET) { 1967d41884eeSHuazhong Tan struct hclge_vf_to_pf_msg send_msg; 1968d41884eeSHuazhong Tan int ret; 1969d41884eeSHuazhong Tan 1970d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_RESET, 0); 1971d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1972cddd5648SHuazhong Tan if (ret) { 1973cddd5648SHuazhong Tan dev_err(&hdev->pdev->dev, 1974cddd5648SHuazhong Tan "failed to assert VF reset, ret = %d\n", ret); 1975cddd5648SHuazhong Tan return ret; 1976cddd5648SHuazhong Tan } 1977c88a6e7dSHuazhong Tan hdev->rst_stats.vf_func_rst_cnt++; 1978dea846e8SHuazhong Tan } 1979dea846e8SHuazhong Tan 1980076bb537SJie Wang set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 1981ada13ee3SHuazhong Tan /* inform hardware that preparatory work is done */ 1982ada13ee3SHuazhong Tan msleep(HCLGEVF_RESET_SYNC_TIME); 19836b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, true); 1984d41884eeSHuazhong Tan dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done\n", 1985d41884eeSHuazhong Tan hdev->reset_type); 1986dea846e8SHuazhong Tan 1987d41884eeSHuazhong Tan return 0; 1988dea846e8SHuazhong Tan } 1989dea846e8SHuazhong Tan 19903d77d0cbSHuazhong Tan static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev) 19913d77d0cbSHuazhong Tan { 19923d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "VF function reset count: %u\n", 19933d77d0cbSHuazhong Tan hdev->rst_stats.vf_func_rst_cnt); 19943d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "FLR reset count: %u\n", 19953d77d0cbSHuazhong Tan hdev->rst_stats.flr_rst_cnt); 19963d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "VF reset count: %u\n", 19973d77d0cbSHuazhong Tan hdev->rst_stats.vf_rst_cnt); 19983d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "reset done count: %u\n", 19993d77d0cbSHuazhong Tan hdev->rst_stats.rst_done_cnt); 20003d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "HW reset done count: %u\n", 20013d77d0cbSHuazhong Tan hdev->rst_stats.hw_rst_done_cnt); 20023d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "reset count: %u\n", 20033d77d0cbSHuazhong Tan hdev->rst_stats.rst_cnt); 20043d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "reset fail count: %u\n", 20053d77d0cbSHuazhong Tan hdev->rst_stats.rst_fail_cnt); 20063d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n", 20073d77d0cbSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE)); 20083d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n", 2009cb413bfaSJie Wang hclgevf_read_dev(&hdev->hw, HCLGE_COMM_VECTOR0_CMDQ_STATE_REG)); 20103d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n", 2011cb413bfaSJie Wang hclgevf_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG)); 20123d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n", 20133d77d0cbSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING)); 20143d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state); 20153d77d0cbSHuazhong Tan } 20163d77d0cbSHuazhong Tan 2017bbe6540eSHuazhong Tan static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 2018bbe6540eSHuazhong Tan { 20196b428b4fSHuazhong Tan /* recover handshake status with IMP when reset fail */ 20206b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, true); 2021bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt++; 2022adcf738bSGuojia Liao dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n", 2023bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt); 2024bbe6540eSHuazhong Tan 2025bbe6540eSHuazhong Tan if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 2026bbe6540eSHuazhong Tan set_bit(hdev->reset_type, &hdev->reset_pending); 2027bbe6540eSHuazhong Tan 2028bbe6540eSHuazhong Tan if (hclgevf_is_reset_pending(hdev)) { 2029bbe6540eSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2030bbe6540eSHuazhong Tan hclgevf_reset_task_schedule(hdev); 20313d77d0cbSHuazhong Tan } else { 2032d5432455SGuojia Liao set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 20333d77d0cbSHuazhong Tan hclgevf_dump_rst_info(hdev); 2034bbe6540eSHuazhong Tan } 2035bbe6540eSHuazhong Tan } 2036bbe6540eSHuazhong Tan 20371cc9bc6eSHuazhong Tan static int hclgevf_reset_prepare(struct hclgevf_dev *hdev) 20386988eb2aSSalil Mehta { 20396988eb2aSSalil Mehta int ret; 20406988eb2aSSalil Mehta 2041c88a6e7dSHuazhong Tan hdev->rst_stats.rst_cnt++; 20426988eb2aSSalil Mehta 2043fe735c84SHuazhong Tan /* perform reset of the stack & ae device for a client */ 2044fe735c84SHuazhong Tan ret = hclgevf_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 2045fe735c84SHuazhong Tan if (ret) 2046fe735c84SHuazhong Tan return ret; 2047fe735c84SHuazhong Tan 20481cc9bc6eSHuazhong Tan rtnl_lock(); 20496988eb2aSSalil Mehta /* bring down the nic to stop any ongoing TX/RX */ 20506a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 205129118ab9SHuazhong Tan rtnl_unlock(); 20526a5f6fa3SHuazhong Tan if (ret) 20531cc9bc6eSHuazhong Tan return ret; 2054dea846e8SHuazhong Tan 20551cc9bc6eSHuazhong Tan return hclgevf_reset_prepare_wait(hdev); 20566988eb2aSSalil Mehta } 20576988eb2aSSalil Mehta 20581cc9bc6eSHuazhong Tan static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev) 20591cc9bc6eSHuazhong Tan { 20601cc9bc6eSHuazhong Tan int ret; 20611cc9bc6eSHuazhong Tan 2062c88a6e7dSHuazhong Tan hdev->rst_stats.hw_rst_done_cnt++; 2063fe735c84SHuazhong Tan ret = hclgevf_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 2064fe735c84SHuazhong Tan if (ret) 2065fe735c84SHuazhong Tan return ret; 2066c88a6e7dSHuazhong Tan 206729118ab9SHuazhong Tan rtnl_lock(); 20686988eb2aSSalil Mehta /* now, re-initialize the nic client and ae device */ 20696988eb2aSSalil Mehta ret = hclgevf_reset_stack(hdev); 20701cc9bc6eSHuazhong Tan rtnl_unlock(); 20716a5f6fa3SHuazhong Tan if (ret) { 20726988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 20731cc9bc6eSHuazhong Tan return ret; 20746a5f6fa3SHuazhong Tan } 20756988eb2aSSalil Mehta 2076fe735c84SHuazhong Tan ret = hclgevf_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 2077fe735c84SHuazhong Tan /* ignore RoCE notify error if it fails HCLGEVF_RESET_MAX_FAIL_CNT - 1 2078fe735c84SHuazhong Tan * times 2079fe735c84SHuazhong Tan */ 2080fe735c84SHuazhong Tan if (ret && 2081fe735c84SHuazhong Tan hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT - 1) 2082fe735c84SHuazhong Tan return ret; 2083fe735c84SHuazhong Tan 2084fe735c84SHuazhong Tan ret = hclgevf_notify_roce_client(hdev, HNAE3_UP_CLIENT); 2085fe735c84SHuazhong Tan if (ret) 2086fe735c84SHuazhong Tan return ret; 2087fe735c84SHuazhong Tan 2088b644a8d4SHuazhong Tan hdev->last_reset_time = jiffies; 2089c88a6e7dSHuazhong Tan hdev->rst_stats.rst_done_cnt++; 2090bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt = 0; 2091d5432455SGuojia Liao clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 2092b644a8d4SHuazhong Tan 20931cc9bc6eSHuazhong Tan return 0; 20941cc9bc6eSHuazhong Tan } 20951cc9bc6eSHuazhong Tan 20961cc9bc6eSHuazhong Tan static void hclgevf_reset(struct hclgevf_dev *hdev) 20971cc9bc6eSHuazhong Tan { 20981cc9bc6eSHuazhong Tan if (hclgevf_reset_prepare(hdev)) 20991cc9bc6eSHuazhong Tan goto err_reset; 21001cc9bc6eSHuazhong Tan 21011cc9bc6eSHuazhong Tan /* check if VF could successfully fetch the hardware reset completion 21021cc9bc6eSHuazhong Tan * status from the hardware 21031cc9bc6eSHuazhong Tan */ 21041cc9bc6eSHuazhong Tan if (hclgevf_reset_wait(hdev)) { 21051cc9bc6eSHuazhong Tan /* can't do much in this situation, will disable VF */ 21061cc9bc6eSHuazhong Tan dev_err(&hdev->pdev->dev, 21071cc9bc6eSHuazhong Tan "failed to fetch H/W reset completion status\n"); 21081cc9bc6eSHuazhong Tan goto err_reset; 21091cc9bc6eSHuazhong Tan } 21101cc9bc6eSHuazhong Tan 21111cc9bc6eSHuazhong Tan if (hclgevf_reset_rebuild(hdev)) 21121cc9bc6eSHuazhong Tan goto err_reset; 21131cc9bc6eSHuazhong Tan 21141cc9bc6eSHuazhong Tan return; 21151cc9bc6eSHuazhong Tan 21166a5f6fa3SHuazhong Tan err_reset: 2117bbe6540eSHuazhong Tan hclgevf_reset_err_handle(hdev); 21186988eb2aSSalil Mehta } 21196988eb2aSSalil Mehta 2120720bd583SHuazhong Tan static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 2121720bd583SHuazhong Tan unsigned long *addr) 2122720bd583SHuazhong Tan { 2123720bd583SHuazhong Tan enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 2124720bd583SHuazhong Tan 2125dea846e8SHuazhong Tan /* return the highest priority reset level amongst all */ 2126b90fcc5bSHuazhong Tan if (test_bit(HNAE3_VF_RESET, addr)) { 2127b90fcc5bSHuazhong Tan rst_level = HNAE3_VF_RESET; 2128b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_RESET, addr); 2129b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 2130b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 2131b90fcc5bSHuazhong Tan } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 2132dea846e8SHuazhong Tan rst_level = HNAE3_VF_FULL_RESET; 2133dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FULL_RESET, addr); 2134dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 2135aa5c4f17SHuazhong Tan } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 2136aa5c4f17SHuazhong Tan rst_level = HNAE3_VF_PF_FUNC_RESET; 2137aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 2138aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 2139dea846e8SHuazhong Tan } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 2140dea846e8SHuazhong Tan rst_level = HNAE3_VF_FUNC_RESET; 2141dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 21426ff3cf07SHuazhong Tan } else if (test_bit(HNAE3_FLR_RESET, addr)) { 21436ff3cf07SHuazhong Tan rst_level = HNAE3_FLR_RESET; 21446ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_RESET, addr); 2145720bd583SHuazhong Tan } 2146720bd583SHuazhong Tan 2147720bd583SHuazhong Tan return rst_level; 2148720bd583SHuazhong Tan } 2149720bd583SHuazhong Tan 21506ae4e733SShiju Jose static void hclgevf_reset_event(struct pci_dev *pdev, 21516ae4e733SShiju Jose struct hnae3_handle *handle) 21526d4c3981SSalil Mehta { 21536ff3cf07SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 21546ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 21556d4c3981SSalil Mehta 21566d4c3981SSalil Mehta dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 21576d4c3981SSalil Mehta 21586ff3cf07SHuazhong Tan if (hdev->default_reset_request) 21590742ed7cSHuazhong Tan hdev->reset_level = 2160720bd583SHuazhong Tan hclgevf_get_reset_level(hdev, 2161720bd583SHuazhong Tan &hdev->default_reset_request); 2162720bd583SHuazhong Tan else 2163dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 21646d4c3981SSalil Mehta 2165436667d2SSalil Mehta /* reset of this VF requested */ 2166436667d2SSalil Mehta set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 2167436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 21686d4c3981SSalil Mehta 21690742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 21706d4c3981SSalil Mehta } 21716d4c3981SSalil Mehta 2172720bd583SHuazhong Tan static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 2173720bd583SHuazhong Tan enum hnae3_reset_type rst_type) 2174720bd583SHuazhong Tan { 2175720bd583SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 2176720bd583SHuazhong Tan 2177720bd583SHuazhong Tan set_bit(rst_type, &hdev->default_reset_request); 2178720bd583SHuazhong Tan } 2179720bd583SHuazhong Tan 2180f28368bbSHuazhong Tan static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 2181f28368bbSHuazhong Tan { 2182f28368bbSHuazhong Tan writel(en ? 1 : 0, vector->addr); 2183f28368bbSHuazhong Tan } 2184f28368bbSHuazhong Tan 2185bb1890d5SJiaran Zhang static void hclgevf_reset_prepare_general(struct hnae3_ae_dev *ae_dev, 2186bb1890d5SJiaran Zhang enum hnae3_reset_type rst_type) 21876ff3cf07SHuazhong Tan { 2188bb1890d5SJiaran Zhang #define HCLGEVF_RESET_RETRY_WAIT_MS 500 2189bb1890d5SJiaran Zhang #define HCLGEVF_RESET_RETRY_CNT 5 2190f28368bbSHuazhong Tan 21916ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 2192f28368bbSHuazhong Tan int retry_cnt = 0; 2193f28368bbSHuazhong Tan int ret; 21946ff3cf07SHuazhong Tan 2195ed0e658cSJiaran Zhang while (retry_cnt++ < HCLGEVF_RESET_RETRY_CNT) { 2196f28368bbSHuazhong Tan down(&hdev->reset_sem); 2197f28368bbSHuazhong Tan set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2198bb1890d5SJiaran Zhang hdev->reset_type = rst_type; 2199f28368bbSHuazhong Tan ret = hclgevf_reset_prepare(hdev); 2200ed0e658cSJiaran Zhang if (!ret && !hdev->reset_pending) 2201ed0e658cSJiaran Zhang break; 2202ed0e658cSJiaran Zhang 22036ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 2204ed0e658cSJiaran Zhang "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n", 2205ed0e658cSJiaran Zhang ret, hdev->reset_pending, retry_cnt); 2206f28368bbSHuazhong Tan clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2207f28368bbSHuazhong Tan up(&hdev->reset_sem); 2208bb1890d5SJiaran Zhang msleep(HCLGEVF_RESET_RETRY_WAIT_MS); 2209f28368bbSHuazhong Tan } 2210f28368bbSHuazhong Tan 2211bb1890d5SJiaran Zhang /* disable misc vector before reset done */ 2212f28368bbSHuazhong Tan hclgevf_enable_vector(&hdev->misc_vector, false); 2213bb1890d5SJiaran Zhang 2214bb1890d5SJiaran Zhang if (hdev->reset_type == HNAE3_FLR_RESET) 2215f28368bbSHuazhong Tan hdev->rst_stats.flr_rst_cnt++; 2216f28368bbSHuazhong Tan } 2217f28368bbSHuazhong Tan 2218bb1890d5SJiaran Zhang static void hclgevf_reset_done(struct hnae3_ae_dev *ae_dev) 2219f28368bbSHuazhong Tan { 2220f28368bbSHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 2221f28368bbSHuazhong Tan int ret; 2222f28368bbSHuazhong Tan 2223f28368bbSHuazhong Tan hclgevf_enable_vector(&hdev->misc_vector, true); 2224f28368bbSHuazhong Tan 2225f28368bbSHuazhong Tan ret = hclgevf_reset_rebuild(hdev); 2226f28368bbSHuazhong Tan if (ret) 2227f28368bbSHuazhong Tan dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", 2228f28368bbSHuazhong Tan ret); 2229f28368bbSHuazhong Tan 2230f28368bbSHuazhong Tan hdev->reset_type = HNAE3_NONE_RESET; 2231f28368bbSHuazhong Tan clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2232f28368bbSHuazhong Tan up(&hdev->reset_sem); 22336ff3cf07SHuazhong Tan } 22346ff3cf07SHuazhong Tan 2235e2cb1decSSalil Mehta static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 2236e2cb1decSSalil Mehta { 2237e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2238e2cb1decSSalil Mehta 2239e2cb1decSSalil Mehta return hdev->fw_version; 2240e2cb1decSSalil Mehta } 2241e2cb1decSSalil Mehta 2242e2cb1decSSalil Mehta static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 2243e2cb1decSSalil Mehta { 2244e2cb1decSSalil Mehta struct hclgevf_misc_vector *vector = &hdev->misc_vector; 2245e2cb1decSSalil Mehta 2246e2cb1decSSalil Mehta vector->vector_irq = pci_irq_vector(hdev->pdev, 2247e2cb1decSSalil Mehta HCLGEVF_MISC_VECTOR_NUM); 2248076bb537SJie Wang vector->addr = hdev->hw.hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 2249e2cb1decSSalil Mehta /* vector status always valid for Vector 0 */ 2250e2cb1decSSalil Mehta hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 2251e2cb1decSSalil Mehta hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 2252e2cb1decSSalil Mehta 2253e2cb1decSSalil Mehta hdev->num_msi_left -= 1; 2254e2cb1decSSalil Mehta hdev->num_msi_used += 1; 2255e2cb1decSSalil Mehta } 2256e2cb1decSSalil Mehta 225735a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 225835a1e503SSalil Mehta { 2259ff200099SYunsheng Lin if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 22600251d196SGuangbin Huang test_bit(HCLGEVF_STATE_SERVICE_INITED, &hdev->state) && 2261ff200099SYunsheng Lin !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, 2262ff200099SYunsheng Lin &hdev->state)) 22630ea68902SYunsheng Lin mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 226435a1e503SSalil Mehta } 226535a1e503SSalil Mehta 226607a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 2267e2cb1decSSalil Mehta { 2268ff200099SYunsheng Lin if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2269ff200099SYunsheng Lin !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, 2270ff200099SYunsheng Lin &hdev->state)) 22710ea68902SYunsheng Lin mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 227207a0556aSSalil Mehta } 2273e2cb1decSSalil Mehta 2274ff200099SYunsheng Lin static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 2275ff200099SYunsheng Lin unsigned long delay) 2276e2cb1decSSalil Mehta { 2277d5432455SGuojia Liao if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2278d5432455SGuojia Liao !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 22790ea68902SYunsheng Lin mod_delayed_work(hclgevf_wq, &hdev->service_task, delay); 2280e2cb1decSSalil Mehta } 2281e2cb1decSSalil Mehta 2282ff200099SYunsheng Lin static void hclgevf_reset_service_task(struct hclgevf_dev *hdev) 228335a1e503SSalil Mehta { 2284d6ad7c53SGuojia Liao #define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3 2285d6ad7c53SGuojia Liao 2286ff200099SYunsheng Lin if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state)) 2287ff200099SYunsheng Lin return; 2288ff200099SYunsheng Lin 2289f28368bbSHuazhong Tan down(&hdev->reset_sem); 2290f28368bbSHuazhong Tan set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 229135a1e503SSalil Mehta 2292436667d2SSalil Mehta if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 2293436667d2SSalil Mehta &hdev->reset_state)) { 2294cd7e963dSSalil Mehta /* PF has intimated that it is about to reset the hardware. 22959b2f3477SWeihang Li * We now have to poll & check if hardware has actually 22969b2f3477SWeihang Li * completed the reset sequence. On hardware reset completion, 22979b2f3477SWeihang Li * VF needs to reset the client and ae device. 229835a1e503SSalil Mehta */ 2299436667d2SSalil Mehta hdev->reset_attempts = 0; 2300436667d2SSalil Mehta 2301dea846e8SHuazhong Tan hdev->last_reset_time = jiffies; 23021385cc81SYufeng Mo hdev->reset_type = 23031385cc81SYufeng Mo hclgevf_get_reset_level(hdev, &hdev->reset_pending); 23041385cc81SYufeng Mo if (hdev->reset_type != HNAE3_NONE_RESET) 23051cc9bc6eSHuazhong Tan hclgevf_reset(hdev); 2306436667d2SSalil Mehta } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 2307436667d2SSalil Mehta &hdev->reset_state)) { 2308436667d2SSalil Mehta /* we could be here when either of below happens: 23099b2f3477SWeihang Li * 1. reset was initiated due to watchdog timeout caused by 2310436667d2SSalil Mehta * a. IMP was earlier reset and our TX got choked down and 2311436667d2SSalil Mehta * which resulted in watchdog reacting and inducing VF 2312436667d2SSalil Mehta * reset. This also means our cmdq would be unreliable. 2313436667d2SSalil Mehta * b. problem in TX due to other lower layer(example link 2314436667d2SSalil Mehta * layer not functioning properly etc.) 2315436667d2SSalil Mehta * 2. VF reset might have been initiated due to some config 2316436667d2SSalil Mehta * change. 2317436667d2SSalil Mehta * 2318436667d2SSalil Mehta * NOTE: Theres no clear way to detect above cases than to react 2319436667d2SSalil Mehta * to the response of PF for this reset request. PF will ack the 2320436667d2SSalil Mehta * 1b and 2. cases but we will not get any intimation about 1a 2321436667d2SSalil Mehta * from PF as cmdq would be in unreliable state i.e. mailbox 2322436667d2SSalil Mehta * communication between PF and VF would be broken. 232346ee7350SGuojia Liao * 232446ee7350SGuojia Liao * if we are never geting into pending state it means either: 2325436667d2SSalil Mehta * 1. PF is not receiving our request which could be due to IMP 2326436667d2SSalil Mehta * reset 2327436667d2SSalil Mehta * 2. PF is screwed 2328436667d2SSalil Mehta * We cannot do much for 2. but to check first we can try reset 2329436667d2SSalil Mehta * our PCIe + stack and see if it alleviates the problem. 2330436667d2SSalil Mehta */ 2331d6ad7c53SGuojia Liao if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) { 2332436667d2SSalil Mehta /* prepare for full reset of stack + pcie interface */ 2333dea846e8SHuazhong Tan set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 2334436667d2SSalil Mehta 2335436667d2SSalil Mehta /* "defer" schedule the reset task again */ 2336436667d2SSalil Mehta set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2337436667d2SSalil Mehta } else { 2338436667d2SSalil Mehta hdev->reset_attempts++; 2339436667d2SSalil Mehta 2340dea846e8SHuazhong Tan set_bit(hdev->reset_level, &hdev->reset_pending); 2341dea846e8SHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2342436667d2SSalil Mehta } 2343dea846e8SHuazhong Tan hclgevf_reset_task_schedule(hdev); 2344436667d2SSalil Mehta } 234535a1e503SSalil Mehta 2346afb6afdbSHuazhong Tan hdev->reset_type = HNAE3_NONE_RESET; 234735a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2348f28368bbSHuazhong Tan up(&hdev->reset_sem); 234935a1e503SSalil Mehta } 235035a1e503SSalil Mehta 2351ff200099SYunsheng Lin static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev) 2352e2cb1decSSalil Mehta { 2353ff200099SYunsheng Lin if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state)) 2354ff200099SYunsheng Lin return; 2355e2cb1decSSalil Mehta 2356e2cb1decSSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 2357e2cb1decSSalil Mehta return; 2358e2cb1decSSalil Mehta 235907a0556aSSalil Mehta hclgevf_mbx_async_handler(hdev); 2360e2cb1decSSalil Mehta 2361e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2362e2cb1decSSalil Mehta } 2363e2cb1decSSalil Mehta 2364ff200099SYunsheng Lin static void hclgevf_keep_alive(struct hclgevf_dev *hdev) 2365a6d818e3SYunsheng Lin { 2366d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 2367a6d818e3SYunsheng Lin int ret; 2368a6d818e3SYunsheng Lin 2369076bb537SJie Wang if (test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state)) 2370c59a85c0SJian Shen return; 2371c59a85c0SJian Shen 2372d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_KEEP_ALIVE, 0); 2373d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2374a6d818e3SYunsheng Lin if (ret) 2375a6d818e3SYunsheng Lin dev_err(&hdev->pdev->dev, 2376a6d818e3SYunsheng Lin "VF sends keep alive cmd failed(=%d)\n", ret); 2377a6d818e3SYunsheng Lin } 2378a6d818e3SYunsheng Lin 2379ff200099SYunsheng Lin static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev) 2380e2cb1decSSalil Mehta { 2381ff200099SYunsheng Lin unsigned long delta = round_jiffies_relative(HZ); 2382ff200099SYunsheng Lin struct hnae3_handle *handle = &hdev->nic; 2383e2cb1decSSalil Mehta 2384e6394363SGuangbin Huang if (test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 2385e6394363SGuangbin Huang return; 2386e6394363SGuangbin Huang 2387ff200099SYunsheng Lin if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 2388ff200099SYunsheng Lin delta = jiffies - hdev->last_serv_processed; 2389db01afebSliuzhongzhu 2390ff200099SYunsheng Lin if (delta < round_jiffies_relative(HZ)) { 2391ff200099SYunsheng Lin delta = round_jiffies_relative(HZ) - delta; 2392ff200099SYunsheng Lin goto out; 2393db01afebSliuzhongzhu } 2394ff200099SYunsheng Lin } 2395ff200099SYunsheng Lin 2396ff200099SYunsheng Lin hdev->serv_processed_cnt++; 2397ff200099SYunsheng Lin if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL)) 2398ff200099SYunsheng Lin hclgevf_keep_alive(hdev); 2399ff200099SYunsheng Lin 2400ff200099SYunsheng Lin if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) { 2401ff200099SYunsheng Lin hdev->last_serv_processed = jiffies; 2402ff200099SYunsheng Lin goto out; 2403ff200099SYunsheng Lin } 2404ff200099SYunsheng Lin 2405ff200099SYunsheng Lin if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL)) 2406ff200099SYunsheng Lin hclgevf_tqps_update_stats(handle); 2407e2cb1decSSalil Mehta 240801305e16SGuangbin Huang /* VF does not need to request link status when this bit is set, because 240901305e16SGuangbin Huang * PF will push its link status to VFs when link status changed. 2410e2cb1decSSalil Mehta */ 241101305e16SGuangbin Huang if (!test_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state)) 2412e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 2413e2cb1decSSalil Mehta 24149194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 24159194d18bSliuzhongzhu 2416fe4144d4SJian Shen hclgevf_sync_vlan_filter(hdev); 2417fe4144d4SJian Shen 2418ee4bcd3bSJian Shen hclgevf_sync_mac_table(hdev); 2419ee4bcd3bSJian Shen 2420c631c696SJian Shen hclgevf_sync_promisc_mode(hdev); 2421c631c696SJian Shen 2422ff200099SYunsheng Lin hdev->last_serv_processed = jiffies; 2423436667d2SSalil Mehta 2424ff200099SYunsheng Lin out: 2425ff200099SYunsheng Lin hclgevf_task_schedule(hdev, delta); 2426ff200099SYunsheng Lin } 2427b3c3fe8eSYunsheng Lin 2428ff200099SYunsheng Lin static void hclgevf_service_task(struct work_struct *work) 2429ff200099SYunsheng Lin { 2430ff200099SYunsheng Lin struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev, 2431ff200099SYunsheng Lin service_task.work); 2432ff200099SYunsheng Lin 2433ff200099SYunsheng Lin hclgevf_reset_service_task(hdev); 2434ff200099SYunsheng Lin hclgevf_mailbox_service_task(hdev); 2435ff200099SYunsheng Lin hclgevf_periodic_service_task(hdev); 2436ff200099SYunsheng Lin 2437ff200099SYunsheng Lin /* Handle reset and mbx again in case periodical task delays the 2438ff200099SYunsheng Lin * handling by calling hclgevf_task_schedule() in 2439ff200099SYunsheng Lin * hclgevf_periodic_service_task() 2440ff200099SYunsheng Lin */ 2441ff200099SYunsheng Lin hclgevf_reset_service_task(hdev); 2442ff200099SYunsheng Lin hclgevf_mailbox_service_task(hdev); 2443e2cb1decSSalil Mehta } 2444e2cb1decSSalil Mehta 2445e2cb1decSSalil Mehta static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 2446e2cb1decSSalil Mehta { 2447cb413bfaSJie Wang hclgevf_write_dev(&hdev->hw, HCLGE_COMM_VECTOR0_CMDQ_SRC_REG, regclr); 2448e2cb1decSSalil Mehta } 2449e2cb1decSSalil Mehta 2450b90fcc5bSHuazhong Tan static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 2451b90fcc5bSHuazhong Tan u32 *clearval) 2452e2cb1decSSalil Mehta { 245313050921SHuazhong Tan u32 val, cmdq_stat_reg, rst_ing_reg; 2454e2cb1decSSalil Mehta 2455e2cb1decSSalil Mehta /* fetch the events from their corresponding regs */ 245613050921SHuazhong Tan cmdq_stat_reg = hclgevf_read_dev(&hdev->hw, 2457cb413bfaSJie Wang HCLGE_COMM_VECTOR0_CMDQ_STATE_REG); 245813050921SHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 2459b90fcc5bSHuazhong Tan rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 2460b90fcc5bSHuazhong Tan dev_info(&hdev->pdev->dev, 2461b90fcc5bSHuazhong Tan "receive reset interrupt 0x%x!\n", rst_ing_reg); 2462b90fcc5bSHuazhong Tan set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 2463b90fcc5bSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2464076bb537SJie Wang set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 246513050921SHuazhong Tan *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B); 2466c88a6e7dSHuazhong Tan hdev->rst_stats.vf_rst_cnt++; 246772e2fb07SHuazhong Tan /* set up VF hardware reset status, its PF will clear 246872e2fb07SHuazhong Tan * this status when PF has initialized done. 246972e2fb07SHuazhong Tan */ 247072e2fb07SHuazhong Tan val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING); 247172e2fb07SHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING, 247272e2fb07SHuazhong Tan val | HCLGEVF_VF_RST_ING_BIT); 2473b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_RST; 2474b90fcc5bSHuazhong Tan } 2475b90fcc5bSHuazhong Tan 2476e2cb1decSSalil Mehta /* check for vector0 mailbox(=CMDQ RX) event source */ 247713050921SHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 247813050921SHuazhong Tan /* for revision 0x21, clearing interrupt is writing bit 0 247913050921SHuazhong Tan * to the clear register, writing bit 1 means to keep the 248013050921SHuazhong Tan * old value. 248113050921SHuazhong Tan * for revision 0x20, the clear register is a read & write 248213050921SHuazhong Tan * register, so we should just write 0 to the bit we are 248313050921SHuazhong Tan * handling, and keep other bits as cmdq_stat_reg. 248413050921SHuazhong Tan */ 2485295ba232SGuangbin Huang if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) 248613050921SHuazhong Tan *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 248713050921SHuazhong Tan else 248813050921SHuazhong Tan *clearval = cmdq_stat_reg & 248913050921SHuazhong Tan ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 249013050921SHuazhong Tan 2491b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_MBX; 2492e2cb1decSSalil Mehta } 2493e2cb1decSSalil Mehta 2494e45afb39SHuazhong Tan /* print other vector0 event source */ 2495e45afb39SHuazhong Tan dev_info(&hdev->pdev->dev, 2496e45afb39SHuazhong Tan "vector 0 interrupt from unknown source, cmdq_src = %#x\n", 2497e45afb39SHuazhong Tan cmdq_stat_reg); 2498e2cb1decSSalil Mehta 2499b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_OTHER; 2500e2cb1decSSalil Mehta } 2501e2cb1decSSalil Mehta 2502e2cb1decSSalil Mehta static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 2503e2cb1decSSalil Mehta { 2504b90fcc5bSHuazhong Tan enum hclgevf_evt_cause event_cause; 2505e2cb1decSSalil Mehta struct hclgevf_dev *hdev = data; 2506e2cb1decSSalil Mehta u32 clearval; 2507e2cb1decSSalil Mehta 2508e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 2509b90fcc5bSHuazhong Tan event_cause = hclgevf_check_evt_cause(hdev, &clearval); 2510427900d2SJiaran Zhang if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) 2511427900d2SJiaran Zhang hclgevf_clear_event_cause(hdev, clearval); 2512e2cb1decSSalil Mehta 2513b90fcc5bSHuazhong Tan switch (event_cause) { 2514b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_RST: 2515b90fcc5bSHuazhong Tan hclgevf_reset_task_schedule(hdev); 2516b90fcc5bSHuazhong Tan break; 2517b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_MBX: 251807a0556aSSalil Mehta hclgevf_mbx_handler(hdev); 2519b90fcc5bSHuazhong Tan break; 2520b90fcc5bSHuazhong Tan default: 2521b90fcc5bSHuazhong Tan break; 2522b90fcc5bSHuazhong Tan } 2523e2cb1decSSalil Mehta 2524427900d2SJiaran Zhang if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) 2525e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2526e2cb1decSSalil Mehta 2527e2cb1decSSalil Mehta return IRQ_HANDLED; 2528e2cb1decSSalil Mehta } 2529e2cb1decSSalil Mehta 2530e2cb1decSSalil Mehta static int hclgevf_configure(struct hclgevf_dev *hdev) 2531e2cb1decSSalil Mehta { 2532e2cb1decSSalil Mehta int ret; 2533e2cb1decSSalil Mehta 25343462207dSYufeng Mo hdev->gro_en = true; 25353462207dSYufeng Mo 253632e6d104SJian Shen ret = hclgevf_get_basic_info(hdev); 253732e6d104SJian Shen if (ret) 253832e6d104SJian Shen return ret; 253932e6d104SJian Shen 254092f11ea1SJian Shen /* get current port based vlan state from PF */ 254192f11ea1SJian Shen ret = hclgevf_get_port_base_vlan_filter_state(hdev); 254292f11ea1SJian Shen if (ret) 254392f11ea1SJian Shen return ret; 254492f11ea1SJian Shen 2545e2cb1decSSalil Mehta /* get queue configuration from PF */ 25466cee6fc3SJian Shen ret = hclgevf_get_queue_info(hdev); 2547e2cb1decSSalil Mehta if (ret) 2548e2cb1decSSalil Mehta return ret; 2549c0425944SPeng Li 2550c0425944SPeng Li /* get queue depth info from PF */ 2551c0425944SPeng Li ret = hclgevf_get_queue_depth(hdev); 2552c0425944SPeng Li if (ret) 2553c0425944SPeng Li return ret; 2554c0425944SPeng Li 255532e6d104SJian Shen return hclgevf_get_pf_media_type(hdev); 2556e2cb1decSSalil Mehta } 2557e2cb1decSSalil Mehta 25587a01c897SSalil Mehta static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 25597a01c897SSalil Mehta { 25607a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 25611154bb26SPeng Li struct hclgevf_dev *hdev; 25627a01c897SSalil Mehta 25637a01c897SSalil Mehta hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 25647a01c897SSalil Mehta if (!hdev) 25657a01c897SSalil Mehta return -ENOMEM; 25667a01c897SSalil Mehta 25677a01c897SSalil Mehta hdev->pdev = pdev; 25687a01c897SSalil Mehta hdev->ae_dev = ae_dev; 25697a01c897SSalil Mehta ae_dev->priv = hdev; 25707a01c897SSalil Mehta 25717a01c897SSalil Mehta return 0; 25727a01c897SSalil Mehta } 25737a01c897SSalil Mehta 2574e2cb1decSSalil Mehta static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 2575e2cb1decSSalil Mehta { 2576e2cb1decSSalil Mehta struct hnae3_handle *roce = &hdev->roce; 2577e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 2578e2cb1decSSalil Mehta 257907acf909SJian Shen roce->rinfo.num_vectors = hdev->num_roce_msix; 2580e2cb1decSSalil Mehta 2581e2cb1decSSalil Mehta if (hdev->num_msi_left < roce->rinfo.num_vectors || 2582e2cb1decSSalil Mehta hdev->num_msi_left == 0) 2583e2cb1decSSalil Mehta return -EINVAL; 2584e2cb1decSSalil Mehta 2585beb27ca4SJie Wang roce->rinfo.base_vector = hdev->roce_base_msix_offset; 2586e2cb1decSSalil Mehta 2587e2cb1decSSalil Mehta roce->rinfo.netdev = nic->kinfo.netdev; 2588076bb537SJie Wang roce->rinfo.roce_io_base = hdev->hw.hw.io_base; 2589076bb537SJie Wang roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base; 2590e2cb1decSSalil Mehta 2591e2cb1decSSalil Mehta roce->pdev = nic->pdev; 2592e2cb1decSSalil Mehta roce->ae_algo = nic->ae_algo; 2593e2cb1decSSalil Mehta roce->numa_node_mask = nic->numa_node_mask; 2594e2cb1decSSalil Mehta 2595e2cb1decSSalil Mehta return 0; 2596e2cb1decSSalil Mehta } 2597e2cb1decSSalil Mehta 25983462207dSYufeng Mo static int hclgevf_config_gro(struct hclgevf_dev *hdev) 2599b26a6feaSPeng Li { 2600b26a6feaSPeng Li struct hclgevf_cfg_gro_status_cmd *req; 26016befad60SJie Wang struct hclge_desc desc; 2602b26a6feaSPeng Li int ret; 2603b26a6feaSPeng Li 2604b26a6feaSPeng Li if (!hnae3_dev_gro_supported(hdev)) 2605b26a6feaSPeng Li return 0; 2606b26a6feaSPeng Li 2607b26a6feaSPeng Li hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 2608b26a6feaSPeng Li false); 2609b26a6feaSPeng Li req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2610b26a6feaSPeng Li 26113462207dSYufeng Mo req->gro_en = hdev->gro_en ? 1 : 0; 2612b26a6feaSPeng Li 2613b26a6feaSPeng Li ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2614b26a6feaSPeng Li if (ret) 2615b26a6feaSPeng Li dev_err(&hdev->pdev->dev, 2616b26a6feaSPeng Li "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2617b26a6feaSPeng Li 2618b26a6feaSPeng Li return ret; 2619b26a6feaSPeng Li } 2620b26a6feaSPeng Li 262187ce161eSGuangbin Huang static int hclgevf_rss_init_cfg(struct hclgevf_dev *hdev) 2622e2cb1decSSalil Mehta { 262387ce161eSGuangbin Huang u16 rss_ind_tbl_size = hdev->ae_dev->dev_specs.rss_ind_tbl_size; 2624e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2625944de484SGuojia Liao struct hclgevf_rss_tuple_cfg *tuple_sets; 26264093d1a2SGuangbin Huang u32 i; 2627e2cb1decSSalil Mehta 2628944de484SGuojia Liao rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 26294093d1a2SGuangbin Huang rss_cfg->rss_size = hdev->nic.kinfo.rss_size; 2630944de484SGuojia Liao tuple_sets = &rss_cfg->rss_tuple_sets; 2631295ba232SGuangbin Huang if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 263287ce161eSGuangbin Huang u8 *rss_ind_tbl; 263387ce161eSGuangbin Huang 2634472d7eceSJian Shen rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 263587ce161eSGuangbin Huang 263687ce161eSGuangbin Huang rss_ind_tbl = devm_kcalloc(&hdev->pdev->dev, rss_ind_tbl_size, 263787ce161eSGuangbin Huang sizeof(*rss_ind_tbl), GFP_KERNEL); 263887ce161eSGuangbin Huang if (!rss_ind_tbl) 263987ce161eSGuangbin Huang return -ENOMEM; 264087ce161eSGuangbin Huang 264187ce161eSGuangbin Huang rss_cfg->rss_indirection_tbl = rss_ind_tbl; 2642472d7eceSJian Shen memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 2643374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 2644374ad291SJian Shen 2645944de484SGuojia Liao tuple_sets->ipv4_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2646944de484SGuojia Liao tuple_sets->ipv4_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2647944de484SGuojia Liao tuple_sets->ipv4_sctp_en = HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2648944de484SGuojia Liao tuple_sets->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2649944de484SGuojia Liao tuple_sets->ipv6_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2650944de484SGuojia Liao tuple_sets->ipv6_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2651ab6e32d2SJian Shen tuple_sets->ipv6_sctp_en = 2652ab6e32d2SJian Shen hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 ? 2653ab6e32d2SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP_NO_PORT : 2654ab6e32d2SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2655944de484SGuojia Liao tuple_sets->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2656374ad291SJian Shen } 2657374ad291SJian Shen 26589b2f3477SWeihang Li /* Initialize RSS indirect table */ 265987ce161eSGuangbin Huang for (i = 0; i < rss_ind_tbl_size; i++) 26604093d1a2SGuangbin Huang rss_cfg->rss_indirection_tbl[i] = i % rss_cfg->rss_size; 266187ce161eSGuangbin Huang 266287ce161eSGuangbin Huang return 0; 2663944de484SGuojia Liao } 2664944de484SGuojia Liao 2665944de484SGuojia Liao static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2666944de484SGuojia Liao { 2667944de484SGuojia Liao struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2668944de484SGuojia Liao int ret; 2669944de484SGuojia Liao 2670295ba232SGuangbin Huang if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 2671944de484SGuojia Liao ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 2672944de484SGuojia Liao rss_cfg->rss_hash_key); 2673944de484SGuojia Liao if (ret) 2674944de484SGuojia Liao return ret; 2675944de484SGuojia Liao 2676944de484SGuojia Liao ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 2677944de484SGuojia Liao if (ret) 2678944de484SGuojia Liao return ret; 2679944de484SGuojia Liao } 2680e2cb1decSSalil Mehta 2681e2cb1decSSalil Mehta ret = hclgevf_set_rss_indir_table(hdev); 2682e2cb1decSSalil Mehta if (ret) 2683e2cb1decSSalil Mehta return ret; 2684e2cb1decSSalil Mehta 26854093d1a2SGuangbin Huang return hclgevf_set_rss_tc_mode(hdev, rss_cfg->rss_size); 2686e2cb1decSSalil Mehta } 2687e2cb1decSSalil Mehta 2688e2cb1decSSalil Mehta static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2689e2cb1decSSalil Mehta { 2690bbfd4506SJian Shen struct hnae3_handle *nic = &hdev->nic; 2691bbfd4506SJian Shen int ret; 2692bbfd4506SJian Shen 2693bbfd4506SJian Shen ret = hclgevf_en_hw_strip_rxvtag(nic, true); 2694bbfd4506SJian Shen if (ret) { 2695bbfd4506SJian Shen dev_err(&hdev->pdev->dev, 2696bbfd4506SJian Shen "failed to enable rx vlan offload, ret = %d\n", ret); 2697bbfd4506SJian Shen return ret; 2698bbfd4506SJian Shen } 2699bbfd4506SJian Shen 2700e2cb1decSSalil Mehta return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2701e2cb1decSSalil Mehta false); 2702e2cb1decSSalil Mehta } 2703e2cb1decSSalil Mehta 2704ff200099SYunsheng Lin static void hclgevf_flush_link_update(struct hclgevf_dev *hdev) 2705ff200099SYunsheng Lin { 2706ff200099SYunsheng Lin #define HCLGEVF_FLUSH_LINK_TIMEOUT 100000 2707ff200099SYunsheng Lin 2708ff200099SYunsheng Lin unsigned long last = hdev->serv_processed_cnt; 2709ff200099SYunsheng Lin int i = 0; 2710ff200099SYunsheng Lin 2711ff200099SYunsheng Lin while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) && 2712ff200099SYunsheng Lin i++ < HCLGEVF_FLUSH_LINK_TIMEOUT && 2713ff200099SYunsheng Lin last == hdev->serv_processed_cnt) 2714ff200099SYunsheng Lin usleep_range(1, 1); 2715ff200099SYunsheng Lin } 2716ff200099SYunsheng Lin 27178cdb992fSJian Shen static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 27188cdb992fSJian Shen { 27198cdb992fSJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27208cdb992fSJian Shen 27218cdb992fSJian Shen if (enable) { 2722ff200099SYunsheng Lin hclgevf_task_schedule(hdev, 0); 27238cdb992fSJian Shen } else { 2724b3c3fe8eSYunsheng Lin set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2725ff200099SYunsheng Lin 2726ff200099SYunsheng Lin /* flush memory to make sure DOWN is seen by service task */ 2727ff200099SYunsheng Lin smp_mb__before_atomic(); 2728ff200099SYunsheng Lin hclgevf_flush_link_update(hdev); 27298cdb992fSJian Shen } 27308cdb992fSJian Shen } 27318cdb992fSJian Shen 2732e2cb1decSSalil Mehta static int hclgevf_ae_start(struct hnae3_handle *handle) 2733e2cb1decSSalil Mehta { 2734e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2735e2cb1decSSalil Mehta 2736ed7bedd2SGuangbin Huang clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 273701305e16SGuangbin Huang clear_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state); 2738ed7bedd2SGuangbin Huang 2739e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 2740e2cb1decSSalil Mehta 2741e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 2742e2cb1decSSalil Mehta 27439194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 27449194d18bSliuzhongzhu 2745e2cb1decSSalil Mehta return 0; 2746e2cb1decSSalil Mehta } 2747e2cb1decSSalil Mehta 2748e2cb1decSSalil Mehta static void hclgevf_ae_stop(struct hnae3_handle *handle) 2749e2cb1decSSalil Mehta { 2750e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2751e2cb1decSSalil Mehta 27522f7e4896SFuyun Liang set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 27532f7e4896SFuyun Liang 2754146e92c1SHuazhong Tan if (hdev->reset_type != HNAE3_VF_RESET) 27558fa86551SYufeng Mo hclgevf_reset_tqp(handle); 275639cfbc9cSHuazhong Tan 2757e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 27588cc6c1f7SFuyun Liang hclgevf_update_link_status(hdev, 0); 2759e2cb1decSSalil Mehta } 2760e2cb1decSSalil Mehta 2761a6d818e3SYunsheng Lin static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2762a6d818e3SYunsheng Lin { 2763d3410018SYufeng Mo #define HCLGEVF_STATE_ALIVE 1 2764d3410018SYufeng Mo #define HCLGEVF_STATE_NOT_ALIVE 0 2765a6d818e3SYunsheng Lin 2766d3410018SYufeng Mo struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2767d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 2768d3410018SYufeng Mo 2769d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_ALIVE, 0); 2770d3410018SYufeng Mo send_msg.data[0] = alive ? HCLGEVF_STATE_ALIVE : 2771d3410018SYufeng Mo HCLGEVF_STATE_NOT_ALIVE; 2772d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2773a6d818e3SYunsheng Lin } 2774a6d818e3SYunsheng Lin 2775a6d818e3SYunsheng Lin static int hclgevf_client_start(struct hnae3_handle *handle) 2776a6d818e3SYunsheng Lin { 2777f621df96SQinglang Miao return hclgevf_set_alive(handle, true); 2778a6d818e3SYunsheng Lin } 2779a6d818e3SYunsheng Lin 2780a6d818e3SYunsheng Lin static void hclgevf_client_stop(struct hnae3_handle *handle) 2781a6d818e3SYunsheng Lin { 2782a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2783a6d818e3SYunsheng Lin int ret; 2784a6d818e3SYunsheng Lin 2785a6d818e3SYunsheng Lin ret = hclgevf_set_alive(handle, false); 2786a6d818e3SYunsheng Lin if (ret) 2787a6d818e3SYunsheng Lin dev_warn(&hdev->pdev->dev, 2788a6d818e3SYunsheng Lin "%s failed %d\n", __func__, ret); 2789a6d818e3SYunsheng Lin } 2790a6d818e3SYunsheng Lin 2791e2cb1decSSalil Mehta static void hclgevf_state_init(struct hclgevf_dev *hdev) 2792e2cb1decSSalil Mehta { 2793e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2794e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2795d5432455SGuojia Liao clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 2796e2cb1decSSalil Mehta 2797b3c3fe8eSYunsheng Lin INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task); 279835a1e503SSalil Mehta 2799e2cb1decSSalil Mehta mutex_init(&hdev->mbx_resp.mbx_mutex); 2800f28368bbSHuazhong Tan sema_init(&hdev->reset_sem, 1); 2801e2cb1decSSalil Mehta 2802ee4bcd3bSJian Shen spin_lock_init(&hdev->mac_table.mac_list_lock); 2803ee4bcd3bSJian Shen INIT_LIST_HEAD(&hdev->mac_table.uc_mac_list); 2804ee4bcd3bSJian Shen INIT_LIST_HEAD(&hdev->mac_table.mc_mac_list); 2805ee4bcd3bSJian Shen 2806e2cb1decSSalil Mehta /* bring the device down */ 2807e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2808e2cb1decSSalil Mehta } 2809e2cb1decSSalil Mehta 2810e2cb1decSSalil Mehta static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2811e2cb1decSSalil Mehta { 2812e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2813acfc3d55SHuazhong Tan set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2814e2cb1decSSalil Mehta 2815b3c3fe8eSYunsheng Lin if (hdev->service_task.work.func) 2816b3c3fe8eSYunsheng Lin cancel_delayed_work_sync(&hdev->service_task); 2817e2cb1decSSalil Mehta 2818e2cb1decSSalil Mehta mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2819e2cb1decSSalil Mehta } 2820e2cb1decSSalil Mehta 2821e2cb1decSSalil Mehta static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2822e2cb1decSSalil Mehta { 2823e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2824e2cb1decSSalil Mehta int vectors; 2825e2cb1decSSalil Mehta int i; 2826e2cb1decSSalil Mehta 2827580a05f9SYonglong Liu if (hnae3_dev_roce_supported(hdev)) 282807acf909SJian Shen vectors = pci_alloc_irq_vectors(pdev, 282907acf909SJian Shen hdev->roce_base_msix_offset + 1, 283007acf909SJian Shen hdev->num_msi, 283107acf909SJian Shen PCI_IRQ_MSIX); 283207acf909SJian Shen else 2833580a05f9SYonglong Liu vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2834580a05f9SYonglong Liu hdev->num_msi, 2835e2cb1decSSalil Mehta PCI_IRQ_MSI | PCI_IRQ_MSIX); 283607acf909SJian Shen 2837e2cb1decSSalil Mehta if (vectors < 0) { 2838e2cb1decSSalil Mehta dev_err(&pdev->dev, 2839e2cb1decSSalil Mehta "failed(%d) to allocate MSI/MSI-X vectors\n", 2840e2cb1decSSalil Mehta vectors); 2841e2cb1decSSalil Mehta return vectors; 2842e2cb1decSSalil Mehta } 2843e2cb1decSSalil Mehta if (vectors < hdev->num_msi) 2844e2cb1decSSalil Mehta dev_warn(&hdev->pdev->dev, 2845adcf738bSGuojia Liao "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2846e2cb1decSSalil Mehta hdev->num_msi, vectors); 2847e2cb1decSSalil Mehta 2848e2cb1decSSalil Mehta hdev->num_msi = vectors; 2849e2cb1decSSalil Mehta hdev->num_msi_left = vectors; 2850580a05f9SYonglong Liu 2851e2cb1decSSalil Mehta hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2852e2cb1decSSalil Mehta sizeof(u16), GFP_KERNEL); 2853e2cb1decSSalil Mehta if (!hdev->vector_status) { 2854e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2855e2cb1decSSalil Mehta return -ENOMEM; 2856e2cb1decSSalil Mehta } 2857e2cb1decSSalil Mehta 2858e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 2859e2cb1decSSalil Mehta hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2860e2cb1decSSalil Mehta 2861e2cb1decSSalil Mehta hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2862e2cb1decSSalil Mehta sizeof(int), GFP_KERNEL); 2863e2cb1decSSalil Mehta if (!hdev->vector_irq) { 2864862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2865e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2866e2cb1decSSalil Mehta return -ENOMEM; 2867e2cb1decSSalil Mehta } 2868e2cb1decSSalil Mehta 2869e2cb1decSSalil Mehta return 0; 2870e2cb1decSSalil Mehta } 2871e2cb1decSSalil Mehta 2872e2cb1decSSalil Mehta static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2873e2cb1decSSalil Mehta { 2874e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2875e2cb1decSSalil Mehta 2876862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2877862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_irq); 2878e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2879e2cb1decSSalil Mehta } 2880e2cb1decSSalil Mehta 2881e2cb1decSSalil Mehta static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2882e2cb1decSSalil Mehta { 2883cdd332acSGuojia Liao int ret; 2884e2cb1decSSalil Mehta 2885e2cb1decSSalil Mehta hclgevf_get_misc_vector(hdev); 2886e2cb1decSSalil Mehta 2887f97c4d82SYonglong Liu snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 2888f97c4d82SYonglong Liu HCLGEVF_NAME, pci_name(hdev->pdev)); 2889e2cb1decSSalil Mehta ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2890f97c4d82SYonglong Liu 0, hdev->misc_vector.name, hdev); 2891e2cb1decSSalil Mehta if (ret) { 2892e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2893e2cb1decSSalil Mehta hdev->misc_vector.vector_irq); 2894e2cb1decSSalil Mehta return ret; 2895e2cb1decSSalil Mehta } 2896e2cb1decSSalil Mehta 28971819e409SXi Wang hclgevf_clear_event_cause(hdev, 0); 28981819e409SXi Wang 2899e2cb1decSSalil Mehta /* enable misc. vector(vector 0) */ 2900e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2901e2cb1decSSalil Mehta 2902e2cb1decSSalil Mehta return ret; 2903e2cb1decSSalil Mehta } 2904e2cb1decSSalil Mehta 2905e2cb1decSSalil Mehta static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2906e2cb1decSSalil Mehta { 2907e2cb1decSSalil Mehta /* disable misc vector(vector 0) */ 2908e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 29091819e409SXi Wang synchronize_irq(hdev->misc_vector.vector_irq); 2910e2cb1decSSalil Mehta free_irq(hdev->misc_vector.vector_irq, hdev); 2911e2cb1decSSalil Mehta hclgevf_free_vector(hdev, 0); 2912e2cb1decSSalil Mehta } 2913e2cb1decSSalil Mehta 2914bb87be87SYonglong Liu static void hclgevf_info_show(struct hclgevf_dev *hdev) 2915bb87be87SYonglong Liu { 2916bb87be87SYonglong Liu struct device *dev = &hdev->pdev->dev; 2917bb87be87SYonglong Liu 2918bb87be87SYonglong Liu dev_info(dev, "VF info begin:\n"); 2919bb87be87SYonglong Liu 2920adcf738bSGuojia Liao dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 2921adcf738bSGuojia Liao dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 2922adcf738bSGuojia Liao dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 2923adcf738bSGuojia Liao dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 2924adcf738bSGuojia Liao dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 2925adcf738bSGuojia Liao dev_info(dev, "PF media type of this VF: %u\n", 2926bb87be87SYonglong Liu hdev->hw.mac.media_type); 2927bb87be87SYonglong Liu 2928bb87be87SYonglong Liu dev_info(dev, "VF info end.\n"); 2929bb87be87SYonglong Liu } 2930bb87be87SYonglong Liu 29311db58f86SHuazhong Tan static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 29321db58f86SHuazhong Tan struct hnae3_client *client) 29331db58f86SHuazhong Tan { 29341db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 29354cd5beaaSGuangbin Huang int rst_cnt = hdev->rst_stats.rst_cnt; 29361db58f86SHuazhong Tan int ret; 29371db58f86SHuazhong Tan 29381db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->nic); 29391db58f86SHuazhong Tan if (ret) 29401db58f86SHuazhong Tan return ret; 29411db58f86SHuazhong Tan 29421db58f86SHuazhong Tan set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 29434cd5beaaSGuangbin Huang if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 29444cd5beaaSGuangbin Huang rst_cnt != hdev->rst_stats.rst_cnt) { 29454cd5beaaSGuangbin Huang clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 29464cd5beaaSGuangbin Huang 29474cd5beaaSGuangbin Huang client->ops->uninit_instance(&hdev->nic, 0); 29484cd5beaaSGuangbin Huang return -EBUSY; 29494cd5beaaSGuangbin Huang } 29504cd5beaaSGuangbin Huang 29511db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 29521db58f86SHuazhong Tan 29531db58f86SHuazhong Tan if (netif_msg_drv(&hdev->nic)) 29541db58f86SHuazhong Tan hclgevf_info_show(hdev); 29551db58f86SHuazhong Tan 29561db58f86SHuazhong Tan return 0; 29571db58f86SHuazhong Tan } 29581db58f86SHuazhong Tan 29591db58f86SHuazhong Tan static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 29601db58f86SHuazhong Tan struct hnae3_client *client) 29611db58f86SHuazhong Tan { 29621db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 29631db58f86SHuazhong Tan int ret; 29641db58f86SHuazhong Tan 29651db58f86SHuazhong Tan if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 29661db58f86SHuazhong Tan !hdev->nic_client) 29671db58f86SHuazhong Tan return 0; 29681db58f86SHuazhong Tan 29691db58f86SHuazhong Tan ret = hclgevf_init_roce_base_info(hdev); 29701db58f86SHuazhong Tan if (ret) 29711db58f86SHuazhong Tan return ret; 29721db58f86SHuazhong Tan 29731db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->roce); 29741db58f86SHuazhong Tan if (ret) 29751db58f86SHuazhong Tan return ret; 29761db58f86SHuazhong Tan 2977fe735c84SHuazhong Tan set_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 29781db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 29791db58f86SHuazhong Tan 29801db58f86SHuazhong Tan return 0; 29811db58f86SHuazhong Tan } 29821db58f86SHuazhong Tan 2983e718a93fSPeng Li static int hclgevf_init_client_instance(struct hnae3_client *client, 2984e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2985e2cb1decSSalil Mehta { 2986e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2987e2cb1decSSalil Mehta int ret; 2988e2cb1decSSalil Mehta 2989e2cb1decSSalil Mehta switch (client->type) { 2990e2cb1decSSalil Mehta case HNAE3_CLIENT_KNIC: 2991e2cb1decSSalil Mehta hdev->nic_client = client; 2992e2cb1decSSalil Mehta hdev->nic.client = client; 2993e2cb1decSSalil Mehta 29941db58f86SHuazhong Tan ret = hclgevf_init_nic_client_instance(ae_dev, client); 2995e2cb1decSSalil Mehta if (ret) 299649dd8054SJian Shen goto clear_nic; 2997e2cb1decSSalil Mehta 29981db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, 29991db58f86SHuazhong Tan hdev->roce_client); 3000e2cb1decSSalil Mehta if (ret) 300149dd8054SJian Shen goto clear_roce; 3002d9f28fc2SJian Shen 3003e2cb1decSSalil Mehta break; 3004e2cb1decSSalil Mehta case HNAE3_CLIENT_ROCE: 3005544a7bcdSLijun Ou if (hnae3_dev_roce_supported(hdev)) { 3006e2cb1decSSalil Mehta hdev->roce_client = client; 3007e2cb1decSSalil Mehta hdev->roce.client = client; 3008544a7bcdSLijun Ou } 3009e2cb1decSSalil Mehta 30101db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, client); 3011e2cb1decSSalil Mehta if (ret) 301249dd8054SJian Shen goto clear_roce; 3013e2cb1decSSalil Mehta 3014fa7a4bd5SJian Shen break; 3015fa7a4bd5SJian Shen default: 3016fa7a4bd5SJian Shen return -EINVAL; 3017e2cb1decSSalil Mehta } 3018e2cb1decSSalil Mehta 3019e2cb1decSSalil Mehta return 0; 302049dd8054SJian Shen 302149dd8054SJian Shen clear_nic: 302249dd8054SJian Shen hdev->nic_client = NULL; 302349dd8054SJian Shen hdev->nic.client = NULL; 302449dd8054SJian Shen return ret; 302549dd8054SJian Shen clear_roce: 302649dd8054SJian Shen hdev->roce_client = NULL; 302749dd8054SJian Shen hdev->roce.client = NULL; 302849dd8054SJian Shen return ret; 3029e2cb1decSSalil Mehta } 3030e2cb1decSSalil Mehta 3031e718a93fSPeng Li static void hclgevf_uninit_client_instance(struct hnae3_client *client, 3032e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 3033e2cb1decSSalil Mehta { 3034e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 3035e718a93fSPeng Li 3036e2cb1decSSalil Mehta /* un-init roce, if it exists */ 303749dd8054SJian Shen if (hdev->roce_client) { 3038e140c798SYufeng Mo while (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 3039e140c798SYufeng Mo msleep(HCLGEVF_WAIT_RESET_DONE); 3040fe735c84SHuazhong Tan clear_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 3041e140c798SYufeng Mo 3042e2cb1decSSalil Mehta hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 304349dd8054SJian Shen hdev->roce_client = NULL; 304449dd8054SJian Shen hdev->roce.client = NULL; 304549dd8054SJian Shen } 3046e2cb1decSSalil Mehta 3047e2cb1decSSalil Mehta /* un-init nic/unic, if this was not called by roce client */ 304849dd8054SJian Shen if (client->ops->uninit_instance && hdev->nic_client && 304949dd8054SJian Shen client->type != HNAE3_CLIENT_ROCE) { 3050e140c798SYufeng Mo while (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 3051e140c798SYufeng Mo msleep(HCLGEVF_WAIT_RESET_DONE); 305225d1817cSHuazhong Tan clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 305325d1817cSHuazhong Tan 3054e2cb1decSSalil Mehta client->ops->uninit_instance(&hdev->nic, 0); 305549dd8054SJian Shen hdev->nic_client = NULL; 305649dd8054SJian Shen hdev->nic.client = NULL; 305749dd8054SJian Shen } 3058e2cb1decSSalil Mehta } 3059e2cb1decSSalil Mehta 306030ae7f8aSHuazhong Tan static int hclgevf_dev_mem_map(struct hclgevf_dev *hdev) 306130ae7f8aSHuazhong Tan { 306230ae7f8aSHuazhong Tan #define HCLGEVF_MEM_BAR 4 306330ae7f8aSHuazhong Tan 306430ae7f8aSHuazhong Tan struct pci_dev *pdev = hdev->pdev; 306530ae7f8aSHuazhong Tan struct hclgevf_hw *hw = &hdev->hw; 306630ae7f8aSHuazhong Tan 306730ae7f8aSHuazhong Tan /* for device does not have device memory, return directly */ 306830ae7f8aSHuazhong Tan if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGEVF_MEM_BAR))) 306930ae7f8aSHuazhong Tan return 0; 307030ae7f8aSHuazhong Tan 3071076bb537SJie Wang hw->hw.mem_base = 3072076bb537SJie Wang devm_ioremap_wc(&pdev->dev, 3073076bb537SJie Wang pci_resource_start(pdev, HCLGEVF_MEM_BAR), 307430ae7f8aSHuazhong Tan pci_resource_len(pdev, HCLGEVF_MEM_BAR)); 3075076bb537SJie Wang if (!hw->hw.mem_base) { 3076be419fcaSColin Ian King dev_err(&pdev->dev, "failed to map device memory\n"); 307730ae7f8aSHuazhong Tan return -EFAULT; 307830ae7f8aSHuazhong Tan } 307930ae7f8aSHuazhong Tan 308030ae7f8aSHuazhong Tan return 0; 308130ae7f8aSHuazhong Tan } 308230ae7f8aSHuazhong Tan 3083e2cb1decSSalil Mehta static int hclgevf_pci_init(struct hclgevf_dev *hdev) 3084e2cb1decSSalil Mehta { 3085e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 3086e2cb1decSSalil Mehta struct hclgevf_hw *hw; 3087e2cb1decSSalil Mehta int ret; 3088e2cb1decSSalil Mehta 3089e2cb1decSSalil Mehta ret = pci_enable_device(pdev); 3090e2cb1decSSalil Mehta if (ret) { 3091e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed to enable PCI device\n"); 30923e249d3bSFuyun Liang return ret; 3093e2cb1decSSalil Mehta } 3094e2cb1decSSalil Mehta 3095e2cb1decSSalil Mehta ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3096e2cb1decSSalil Mehta if (ret) { 3097e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 3098e2cb1decSSalil Mehta goto err_disable_device; 3099e2cb1decSSalil Mehta } 3100e2cb1decSSalil Mehta 3101e2cb1decSSalil Mehta ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 3102e2cb1decSSalil Mehta if (ret) { 3103e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 3104e2cb1decSSalil Mehta goto err_disable_device; 3105e2cb1decSSalil Mehta } 3106e2cb1decSSalil Mehta 3107e2cb1decSSalil Mehta pci_set_master(pdev); 3108e2cb1decSSalil Mehta hw = &hdev->hw; 3109076bb537SJie Wang hw->hw.io_base = pci_iomap(pdev, 2, 0); 3110076bb537SJie Wang if (!hw->hw.io_base) { 3111e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't map configuration register space\n"); 3112e2cb1decSSalil Mehta ret = -ENOMEM; 3113e2cb1decSSalil Mehta goto err_clr_master; 3114e2cb1decSSalil Mehta } 3115e2cb1decSSalil Mehta 311630ae7f8aSHuazhong Tan ret = hclgevf_dev_mem_map(hdev); 311730ae7f8aSHuazhong Tan if (ret) 311830ae7f8aSHuazhong Tan goto err_unmap_io_base; 311930ae7f8aSHuazhong Tan 3120e2cb1decSSalil Mehta return 0; 3121e2cb1decSSalil Mehta 312230ae7f8aSHuazhong Tan err_unmap_io_base: 3123076bb537SJie Wang pci_iounmap(pdev, hdev->hw.hw.io_base); 3124e2cb1decSSalil Mehta err_clr_master: 3125e2cb1decSSalil Mehta pci_clear_master(pdev); 3126e2cb1decSSalil Mehta pci_release_regions(pdev); 3127e2cb1decSSalil Mehta err_disable_device: 3128e2cb1decSSalil Mehta pci_disable_device(pdev); 31293e249d3bSFuyun Liang 3130e2cb1decSSalil Mehta return ret; 3131e2cb1decSSalil Mehta } 3132e2cb1decSSalil Mehta 3133e2cb1decSSalil Mehta static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 3134e2cb1decSSalil Mehta { 3135e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 3136e2cb1decSSalil Mehta 3137076bb537SJie Wang if (hdev->hw.hw.mem_base) 3138076bb537SJie Wang devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base); 313930ae7f8aSHuazhong Tan 3140076bb537SJie Wang pci_iounmap(pdev, hdev->hw.hw.io_base); 3141e2cb1decSSalil Mehta pci_clear_master(pdev); 3142e2cb1decSSalil Mehta pci_release_regions(pdev); 3143e2cb1decSSalil Mehta pci_disable_device(pdev); 3144e2cb1decSSalil Mehta } 3145e2cb1decSSalil Mehta 314607acf909SJian Shen static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 314707acf909SJian Shen { 314807acf909SJian Shen struct hclgevf_query_res_cmd *req; 31496befad60SJie Wang struct hclge_desc desc; 315007acf909SJian Shen int ret; 315107acf909SJian Shen 315207acf909SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 315307acf909SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 315407acf909SJian Shen if (ret) { 315507acf909SJian Shen dev_err(&hdev->pdev->dev, 315607acf909SJian Shen "query vf resource failed, ret = %d.\n", ret); 315707acf909SJian Shen return ret; 315807acf909SJian Shen } 315907acf909SJian Shen 316007acf909SJian Shen req = (struct hclgevf_query_res_cmd *)desc.data; 316107acf909SJian Shen 3162580a05f9SYonglong Liu if (hnae3_dev_roce_supported(hdev)) { 316307acf909SJian Shen hdev->roce_base_msix_offset = 316460df7e91SHuazhong Tan hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee), 316507acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_M, 316607acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_S); 316707acf909SJian Shen hdev->num_roce_msix = 316860df7e91SHuazhong Tan hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 316907acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 317007acf909SJian Shen 3171580a05f9SYonglong Liu /* nic's msix numbers is always equals to the roce's. */ 3172580a05f9SYonglong Liu hdev->num_nic_msix = hdev->num_roce_msix; 3173580a05f9SYonglong Liu 317407acf909SJian Shen /* VF should have NIC vectors and Roce vectors, NIC vectors 317507acf909SJian Shen * are queued before Roce vectors. The offset is fixed to 64. 317607acf909SJian Shen */ 317707acf909SJian Shen hdev->num_msi = hdev->num_roce_msix + 317807acf909SJian Shen hdev->roce_base_msix_offset; 317907acf909SJian Shen } else { 318007acf909SJian Shen hdev->num_msi = 318160df7e91SHuazhong Tan hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 318207acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 3183580a05f9SYonglong Liu 3184580a05f9SYonglong Liu hdev->num_nic_msix = hdev->num_msi; 3185580a05f9SYonglong Liu } 3186580a05f9SYonglong Liu 3187580a05f9SYonglong Liu if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) { 3188580a05f9SYonglong Liu dev_err(&hdev->pdev->dev, 3189580a05f9SYonglong Liu "Just %u msi resources, not enough for vf(min:2).\n", 3190580a05f9SYonglong Liu hdev->num_nic_msix); 3191580a05f9SYonglong Liu return -EINVAL; 319207acf909SJian Shen } 319307acf909SJian Shen 319407acf909SJian Shen return 0; 319507acf909SJian Shen } 319607acf909SJian Shen 3197af2aedc5SGuangbin Huang static void hclgevf_set_default_dev_specs(struct hclgevf_dev *hdev) 3198af2aedc5SGuangbin Huang { 3199af2aedc5SGuangbin Huang #define HCLGEVF_MAX_NON_TSO_BD_NUM 8U 3200af2aedc5SGuangbin Huang 3201af2aedc5SGuangbin Huang struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 3202af2aedc5SGuangbin Huang 3203af2aedc5SGuangbin Huang ae_dev->dev_specs.max_non_tso_bd_num = 3204af2aedc5SGuangbin Huang HCLGEVF_MAX_NON_TSO_BD_NUM; 3205af2aedc5SGuangbin Huang ae_dev->dev_specs.rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 3206af2aedc5SGuangbin Huang ae_dev->dev_specs.rss_key_size = HCLGEVF_RSS_KEY_SIZE; 3207ab16b49cSHuazhong Tan ae_dev->dev_specs.max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 3208e070c8b9SYufeng Mo ae_dev->dev_specs.max_frm_size = HCLGEVF_MAC_MAX_FRAME; 3209af2aedc5SGuangbin Huang } 3210af2aedc5SGuangbin Huang 3211af2aedc5SGuangbin Huang static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev, 32126befad60SJie Wang struct hclge_desc *desc) 3213af2aedc5SGuangbin Huang { 3214af2aedc5SGuangbin Huang struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 3215af2aedc5SGuangbin Huang struct hclgevf_dev_specs_0_cmd *req0; 3216ab16b49cSHuazhong Tan struct hclgevf_dev_specs_1_cmd *req1; 3217af2aedc5SGuangbin Huang 3218af2aedc5SGuangbin Huang req0 = (struct hclgevf_dev_specs_0_cmd *)desc[0].data; 3219ab16b49cSHuazhong Tan req1 = (struct hclgevf_dev_specs_1_cmd *)desc[1].data; 3220af2aedc5SGuangbin Huang 3221af2aedc5SGuangbin Huang ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 3222af2aedc5SGuangbin Huang ae_dev->dev_specs.rss_ind_tbl_size = 3223af2aedc5SGuangbin Huang le16_to_cpu(req0->rss_ind_tbl_size); 322491bfae25SHuazhong Tan ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 3225af2aedc5SGuangbin Huang ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 3226ab16b49cSHuazhong Tan ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 3227e070c8b9SYufeng Mo ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 3228af2aedc5SGuangbin Huang } 3229af2aedc5SGuangbin Huang 323013297028SGuangbin Huang static void hclgevf_check_dev_specs(struct hclgevf_dev *hdev) 323113297028SGuangbin Huang { 323213297028SGuangbin Huang struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 323313297028SGuangbin Huang 323413297028SGuangbin Huang if (!dev_specs->max_non_tso_bd_num) 323513297028SGuangbin Huang dev_specs->max_non_tso_bd_num = HCLGEVF_MAX_NON_TSO_BD_NUM; 323613297028SGuangbin Huang if (!dev_specs->rss_ind_tbl_size) 323713297028SGuangbin Huang dev_specs->rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 323813297028SGuangbin Huang if (!dev_specs->rss_key_size) 323913297028SGuangbin Huang dev_specs->rss_key_size = HCLGEVF_RSS_KEY_SIZE; 3240ab16b49cSHuazhong Tan if (!dev_specs->max_int_gl) 3241ab16b49cSHuazhong Tan dev_specs->max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 3242e070c8b9SYufeng Mo if (!dev_specs->max_frm_size) 3243e070c8b9SYufeng Mo dev_specs->max_frm_size = HCLGEVF_MAC_MAX_FRAME; 324413297028SGuangbin Huang } 324513297028SGuangbin Huang 3246af2aedc5SGuangbin Huang static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev) 3247af2aedc5SGuangbin Huang { 32486befad60SJie Wang struct hclge_desc desc[HCLGEVF_QUERY_DEV_SPECS_BD_NUM]; 3249af2aedc5SGuangbin Huang int ret; 3250af2aedc5SGuangbin Huang int i; 3251af2aedc5SGuangbin Huang 3252af2aedc5SGuangbin Huang /* set default specifications as devices lower than version V3 do not 3253af2aedc5SGuangbin Huang * support querying specifications from firmware. 3254af2aedc5SGuangbin Huang */ 3255af2aedc5SGuangbin Huang if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 3256af2aedc5SGuangbin Huang hclgevf_set_default_dev_specs(hdev); 3257af2aedc5SGuangbin Huang return 0; 3258af2aedc5SGuangbin Huang } 3259af2aedc5SGuangbin Huang 3260af2aedc5SGuangbin Huang for (i = 0; i < HCLGEVF_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 3261af2aedc5SGuangbin Huang hclgevf_cmd_setup_basic_desc(&desc[i], 3262af2aedc5SGuangbin Huang HCLGEVF_OPC_QUERY_DEV_SPECS, true); 3263cb413bfaSJie Wang desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3264af2aedc5SGuangbin Huang } 3265af2aedc5SGuangbin Huang hclgevf_cmd_setup_basic_desc(&desc[i], HCLGEVF_OPC_QUERY_DEV_SPECS, 3266af2aedc5SGuangbin Huang true); 3267af2aedc5SGuangbin Huang 3268af2aedc5SGuangbin Huang ret = hclgevf_cmd_send(&hdev->hw, desc, HCLGEVF_QUERY_DEV_SPECS_BD_NUM); 3269af2aedc5SGuangbin Huang if (ret) 3270af2aedc5SGuangbin Huang return ret; 3271af2aedc5SGuangbin Huang 3272af2aedc5SGuangbin Huang hclgevf_parse_dev_specs(hdev, desc); 327313297028SGuangbin Huang hclgevf_check_dev_specs(hdev); 3274af2aedc5SGuangbin Huang 3275af2aedc5SGuangbin Huang return 0; 3276af2aedc5SGuangbin Huang } 3277af2aedc5SGuangbin Huang 3278862d969aSHuazhong Tan static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 3279862d969aSHuazhong Tan { 3280862d969aSHuazhong Tan struct pci_dev *pdev = hdev->pdev; 3281862d969aSHuazhong Tan int ret = 0; 3282862d969aSHuazhong Tan 3283862d969aSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FULL_RESET && 3284862d969aSHuazhong Tan test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3285862d969aSHuazhong Tan hclgevf_misc_irq_uninit(hdev); 3286862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 3287862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3288862d969aSHuazhong Tan } 3289862d969aSHuazhong Tan 3290862d969aSHuazhong Tan if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3291862d969aSHuazhong Tan pci_set_master(pdev); 3292862d969aSHuazhong Tan ret = hclgevf_init_msi(hdev); 3293862d969aSHuazhong Tan if (ret) { 3294862d969aSHuazhong Tan dev_err(&pdev->dev, 3295862d969aSHuazhong Tan "failed(%d) to init MSI/MSI-X\n", ret); 3296862d969aSHuazhong Tan return ret; 3297862d969aSHuazhong Tan } 3298862d969aSHuazhong Tan 3299862d969aSHuazhong Tan ret = hclgevf_misc_irq_init(hdev); 3300862d969aSHuazhong Tan if (ret) { 3301862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 3302862d969aSHuazhong Tan dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 3303862d969aSHuazhong Tan ret); 3304862d969aSHuazhong Tan return ret; 3305862d969aSHuazhong Tan } 3306862d969aSHuazhong Tan 3307862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3308862d969aSHuazhong Tan } 3309862d969aSHuazhong Tan 3310862d969aSHuazhong Tan return ret; 3311862d969aSHuazhong Tan } 3312862d969aSHuazhong Tan 3313039ba863SJian Shen static int hclgevf_clear_vport_list(struct hclgevf_dev *hdev) 3314039ba863SJian Shen { 3315039ba863SJian Shen struct hclge_vf_to_pf_msg send_msg; 3316039ba863SJian Shen 3317039ba863SJian Shen hclgevf_build_send_msg(&send_msg, HCLGE_MBX_HANDLE_VF_TBL, 3318039ba863SJian Shen HCLGE_MBX_VPORT_LIST_CLEAR); 3319039ba863SJian Shen return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3320039ba863SJian Shen } 3321039ba863SJian Shen 332279664077SHuazhong Tan static void hclgevf_init_rxd_adv_layout(struct hclgevf_dev *hdev) 332379664077SHuazhong Tan { 332479664077SHuazhong Tan if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 332579664077SHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 1); 332679664077SHuazhong Tan } 332779664077SHuazhong Tan 332879664077SHuazhong Tan static void hclgevf_uninit_rxd_adv_layout(struct hclgevf_dev *hdev) 332979664077SHuazhong Tan { 333079664077SHuazhong Tan if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 333179664077SHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 0); 333279664077SHuazhong Tan } 333379664077SHuazhong Tan 33349c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 3335e2cb1decSSalil Mehta { 33367a01c897SSalil Mehta struct pci_dev *pdev = hdev->pdev; 3337e2cb1decSSalil Mehta int ret; 3338e2cb1decSSalil Mehta 3339862d969aSHuazhong Tan ret = hclgevf_pci_reset(hdev); 3340862d969aSHuazhong Tan if (ret) { 3341862d969aSHuazhong Tan dev_err(&pdev->dev, "pci reset failed %d\n", ret); 3342862d969aSHuazhong Tan return ret; 3343862d969aSHuazhong Tan } 3344862d969aSHuazhong Tan 3345cb413bfaSJie Wang hclgevf_arq_init(hdev); 3346cb413bfaSJie Wang ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, 3347cb413bfaSJie Wang &hdev->fw_version, false, 3348cb413bfaSJie Wang hdev->reset_pending); 33499c6f7085SHuazhong Tan if (ret) { 33509c6f7085SHuazhong Tan dev_err(&pdev->dev, "cmd failed %d\n", ret); 33519c6f7085SHuazhong Tan return ret; 33527a01c897SSalil Mehta } 3353e2cb1decSSalil Mehta 33549c6f7085SHuazhong Tan ret = hclgevf_rss_init_hw(hdev); 33559c6f7085SHuazhong Tan if (ret) { 33569c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 33579c6f7085SHuazhong Tan "failed(%d) to initialize RSS\n", ret); 33589c6f7085SHuazhong Tan return ret; 33599c6f7085SHuazhong Tan } 33609c6f7085SHuazhong Tan 33613462207dSYufeng Mo ret = hclgevf_config_gro(hdev); 3362b26a6feaSPeng Li if (ret) 3363b26a6feaSPeng Li return ret; 3364b26a6feaSPeng Li 33659c6f7085SHuazhong Tan ret = hclgevf_init_vlan_config(hdev); 33669c6f7085SHuazhong Tan if (ret) { 33679c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 33689c6f7085SHuazhong Tan "failed(%d) to initialize VLAN config\n", ret); 33699c6f7085SHuazhong Tan return ret; 33709c6f7085SHuazhong Tan } 33719c6f7085SHuazhong Tan 3372c631c696SJian Shen set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 3373c631c696SJian Shen 337479664077SHuazhong Tan hclgevf_init_rxd_adv_layout(hdev); 337579664077SHuazhong Tan 33769c6f7085SHuazhong Tan dev_info(&hdev->pdev->dev, "Reset done\n"); 33779c6f7085SHuazhong Tan 33789c6f7085SHuazhong Tan return 0; 33799c6f7085SHuazhong Tan } 33809c6f7085SHuazhong Tan 33819c6f7085SHuazhong Tan static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 33829c6f7085SHuazhong Tan { 33839c6f7085SHuazhong Tan struct pci_dev *pdev = hdev->pdev; 33849c6f7085SHuazhong Tan int ret; 33859c6f7085SHuazhong Tan 3386e2cb1decSSalil Mehta ret = hclgevf_pci_init(hdev); 338760df7e91SHuazhong Tan if (ret) 3388e2cb1decSSalil Mehta return ret; 3389e2cb1decSSalil Mehta 3390cd624299SYufeng Mo ret = hclgevf_devlink_init(hdev); 3391cd624299SYufeng Mo if (ret) 3392cd624299SYufeng Mo goto err_devlink_init; 3393cd624299SYufeng Mo 3394cb413bfaSJie Wang ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw); 339560df7e91SHuazhong Tan if (ret) 33968b0195a3SHuazhong Tan goto err_cmd_queue_init; 33978b0195a3SHuazhong Tan 3398cb413bfaSJie Wang hclgevf_arq_init(hdev); 3399cb413bfaSJie Wang ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, 3400cb413bfaSJie Wang &hdev->fw_version, false, 3401cb413bfaSJie Wang hdev->reset_pending); 3402eddf0462SYunsheng Lin if (ret) 3403eddf0462SYunsheng Lin goto err_cmd_init; 3404eddf0462SYunsheng Lin 340507acf909SJian Shen /* Get vf resource */ 340607acf909SJian Shen ret = hclgevf_query_vf_resource(hdev); 340760df7e91SHuazhong Tan if (ret) 34088b0195a3SHuazhong Tan goto err_cmd_init; 340907acf909SJian Shen 3410af2aedc5SGuangbin Huang ret = hclgevf_query_dev_specs(hdev); 3411af2aedc5SGuangbin Huang if (ret) { 3412af2aedc5SGuangbin Huang dev_err(&pdev->dev, 3413af2aedc5SGuangbin Huang "failed to query dev specifications, ret = %d\n", ret); 3414af2aedc5SGuangbin Huang goto err_cmd_init; 3415af2aedc5SGuangbin Huang } 3416af2aedc5SGuangbin Huang 341707acf909SJian Shen ret = hclgevf_init_msi(hdev); 341807acf909SJian Shen if (ret) { 341907acf909SJian Shen dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 34208b0195a3SHuazhong Tan goto err_cmd_init; 342107acf909SJian Shen } 342207acf909SJian Shen 342307acf909SJian Shen hclgevf_state_init(hdev); 3424dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 3425afb6afdbSHuazhong Tan hdev->reset_type = HNAE3_NONE_RESET; 342607acf909SJian Shen 3427e2cb1decSSalil Mehta ret = hclgevf_misc_irq_init(hdev); 342860df7e91SHuazhong Tan if (ret) 3429e2cb1decSSalil Mehta goto err_misc_irq_init; 3430e2cb1decSSalil Mehta 3431862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3432862d969aSHuazhong Tan 3433e2cb1decSSalil Mehta ret = hclgevf_configure(hdev); 3434e2cb1decSSalil Mehta if (ret) { 3435e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 3436e2cb1decSSalil Mehta goto err_config; 3437e2cb1decSSalil Mehta } 3438e2cb1decSSalil Mehta 3439e2cb1decSSalil Mehta ret = hclgevf_alloc_tqps(hdev); 3440e2cb1decSSalil Mehta if (ret) { 3441e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 3442e2cb1decSSalil Mehta goto err_config; 3443e2cb1decSSalil Mehta } 3444e2cb1decSSalil Mehta 3445e2cb1decSSalil Mehta ret = hclgevf_set_handle_info(hdev); 344660df7e91SHuazhong Tan if (ret) 3447e2cb1decSSalil Mehta goto err_config; 3448e2cb1decSSalil Mehta 34493462207dSYufeng Mo ret = hclgevf_config_gro(hdev); 3450b26a6feaSPeng Li if (ret) 3451b26a6feaSPeng Li goto err_config; 3452b26a6feaSPeng Li 3453e2cb1decSSalil Mehta /* Initialize RSS for this VF */ 345487ce161eSGuangbin Huang ret = hclgevf_rss_init_cfg(hdev); 345587ce161eSGuangbin Huang if (ret) { 345687ce161eSGuangbin Huang dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 345787ce161eSGuangbin Huang goto err_config; 345887ce161eSGuangbin Huang } 345987ce161eSGuangbin Huang 3460e2cb1decSSalil Mehta ret = hclgevf_rss_init_hw(hdev); 3461e2cb1decSSalil Mehta if (ret) { 3462e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 3463e2cb1decSSalil Mehta "failed(%d) to initialize RSS\n", ret); 3464e2cb1decSSalil Mehta goto err_config; 3465e2cb1decSSalil Mehta } 3466e2cb1decSSalil Mehta 3467039ba863SJian Shen /* ensure vf tbl list as empty before init*/ 3468039ba863SJian Shen ret = hclgevf_clear_vport_list(hdev); 3469039ba863SJian Shen if (ret) { 3470039ba863SJian Shen dev_err(&pdev->dev, 3471039ba863SJian Shen "failed to clear tbl list configuration, ret = %d.\n", 3472039ba863SJian Shen ret); 3473039ba863SJian Shen goto err_config; 3474039ba863SJian Shen } 3475039ba863SJian Shen 3476e2cb1decSSalil Mehta ret = hclgevf_init_vlan_config(hdev); 3477e2cb1decSSalil Mehta if (ret) { 3478e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 3479e2cb1decSSalil Mehta "failed(%d) to initialize VLAN config\n", ret); 3480e2cb1decSSalil Mehta goto err_config; 3481e2cb1decSSalil Mehta } 3482e2cb1decSSalil Mehta 348379664077SHuazhong Tan hclgevf_init_rxd_adv_layout(hdev); 348479664077SHuazhong Tan 34850251d196SGuangbin Huang set_bit(HCLGEVF_STATE_SERVICE_INITED, &hdev->state); 34860251d196SGuangbin Huang 34870742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 348808d80a4cSHuazhong Tan dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 348908d80a4cSHuazhong Tan HCLGEVF_DRIVER_NAME); 3490e2cb1decSSalil Mehta 3491ff200099SYunsheng Lin hclgevf_task_schedule(hdev, round_jiffies_relative(HZ)); 3492ff200099SYunsheng Lin 3493e2cb1decSSalil Mehta return 0; 3494e2cb1decSSalil Mehta 3495e2cb1decSSalil Mehta err_config: 3496e2cb1decSSalil Mehta hclgevf_misc_irq_uninit(hdev); 3497e2cb1decSSalil Mehta err_misc_irq_init: 3498e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 3499e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 350007acf909SJian Shen err_cmd_init: 3501*9970308fSJie Wang hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 35028b0195a3SHuazhong Tan err_cmd_queue_init: 3503cd624299SYufeng Mo hclgevf_devlink_uninit(hdev); 3504cd624299SYufeng Mo err_devlink_init: 3505e2cb1decSSalil Mehta hclgevf_pci_uninit(hdev); 3506862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3507e2cb1decSSalil Mehta return ret; 3508e2cb1decSSalil Mehta } 3509e2cb1decSSalil Mehta 35107a01c897SSalil Mehta static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 3511e2cb1decSSalil Mehta { 3512d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 3513d3410018SYufeng Mo 3514e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 351579664077SHuazhong Tan hclgevf_uninit_rxd_adv_layout(hdev); 3516862d969aSHuazhong Tan 3517d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_VF_UNINIT, 0); 3518d3410018SYufeng Mo hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 351923b4201dSJian Shen 3520862d969aSHuazhong Tan if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3521eddf0462SYunsheng Lin hclgevf_misc_irq_uninit(hdev); 3522e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 35237a01c897SSalil Mehta } 35247a01c897SSalil Mehta 3525*9970308fSJie Wang hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 3526cd624299SYufeng Mo hclgevf_devlink_uninit(hdev); 3527e3364c5fSZenghui Yu hclgevf_pci_uninit(hdev); 3528ee4bcd3bSJian Shen hclgevf_uninit_mac_list(hdev); 3529862d969aSHuazhong Tan } 3530862d969aSHuazhong Tan 35317a01c897SSalil Mehta static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 35327a01c897SSalil Mehta { 35337a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 35347a01c897SSalil Mehta int ret; 35357a01c897SSalil Mehta 35367a01c897SSalil Mehta ret = hclgevf_alloc_hdev(ae_dev); 35377a01c897SSalil Mehta if (ret) { 35387a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device allocation failed\n"); 35397a01c897SSalil Mehta return ret; 35407a01c897SSalil Mehta } 35417a01c897SSalil Mehta 35427a01c897SSalil Mehta ret = hclgevf_init_hdev(ae_dev->priv); 3543a6d818e3SYunsheng Lin if (ret) { 35447a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device initialization failed\n"); 35457a01c897SSalil Mehta return ret; 35467a01c897SSalil Mehta } 35477a01c897SSalil Mehta 3548a6d818e3SYunsheng Lin return 0; 3549a6d818e3SYunsheng Lin } 3550a6d818e3SYunsheng Lin 35517a01c897SSalil Mehta static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 35527a01c897SSalil Mehta { 35537a01c897SSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 35547a01c897SSalil Mehta 35557a01c897SSalil Mehta hclgevf_uninit_hdev(hdev); 3556e2cb1decSSalil Mehta ae_dev->priv = NULL; 3557e2cb1decSSalil Mehta } 3558e2cb1decSSalil Mehta 3559849e4607SPeng Li static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 3560849e4607SPeng Li { 3561849e4607SPeng Li struct hnae3_handle *nic = &hdev->nic; 3562849e4607SPeng Li struct hnae3_knic_private_info *kinfo = &nic->kinfo; 3563849e4607SPeng Li 35648be73621SHuazhong Tan return min_t(u32, hdev->rss_size_max, 356535244430SJian Shen hdev->num_tqps / kinfo->tc_info.num_tc); 3566849e4607SPeng Li } 3567849e4607SPeng Li 3568849e4607SPeng Li /** 3569849e4607SPeng Li * hclgevf_get_channels - Get the current channels enabled and max supported. 3570849e4607SPeng Li * @handle: hardware information for network interface 3571849e4607SPeng Li * @ch: ethtool channels structure 3572849e4607SPeng Li * 3573849e4607SPeng Li * We don't support separate tx and rx queues as channels. The other count 3574849e4607SPeng Li * represents how many queues are being used for control. max_combined counts 3575849e4607SPeng Li * how many queue pairs we can support. They may not be mapped 1 to 1 with 3576849e4607SPeng Li * q_vectors since we support a lot more queue pairs than q_vectors. 3577849e4607SPeng Li **/ 3578849e4607SPeng Li static void hclgevf_get_channels(struct hnae3_handle *handle, 3579849e4607SPeng Li struct ethtool_channels *ch) 3580849e4607SPeng Li { 3581849e4607SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3582849e4607SPeng Li 3583849e4607SPeng Li ch->max_combined = hclgevf_get_max_channels(hdev); 3584849e4607SPeng Li ch->other_count = 0; 3585849e4607SPeng Li ch->max_other = 0; 35868be73621SHuazhong Tan ch->combined_count = handle->kinfo.rss_size; 3587849e4607SPeng Li } 3588849e4607SPeng Li 3589cc719218SPeng Li static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 35900d43bf45SHuazhong Tan u16 *alloc_tqps, u16 *max_rss_size) 3591cc719218SPeng Li { 3592cc719218SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3593cc719218SPeng Li 35940d43bf45SHuazhong Tan *alloc_tqps = hdev->num_tqps; 3595cc719218SPeng Li *max_rss_size = hdev->rss_size_max; 3596cc719218SPeng Li } 3597cc719218SPeng Li 35984093d1a2SGuangbin Huang static void hclgevf_update_rss_size(struct hnae3_handle *handle, 35994093d1a2SGuangbin Huang u32 new_tqps_num) 36004093d1a2SGuangbin Huang { 36014093d1a2SGuangbin Huang struct hnae3_knic_private_info *kinfo = &handle->kinfo; 36024093d1a2SGuangbin Huang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 36034093d1a2SGuangbin Huang u16 max_rss_size; 36044093d1a2SGuangbin Huang 36054093d1a2SGuangbin Huang kinfo->req_rss_size = new_tqps_num; 36064093d1a2SGuangbin Huang 36074093d1a2SGuangbin Huang max_rss_size = min_t(u16, hdev->rss_size_max, 360835244430SJian Shen hdev->num_tqps / kinfo->tc_info.num_tc); 36094093d1a2SGuangbin Huang 36104093d1a2SGuangbin Huang /* Use the user's configuration when it is not larger than 36114093d1a2SGuangbin Huang * max_rss_size, otherwise, use the maximum specification value. 36124093d1a2SGuangbin Huang */ 36134093d1a2SGuangbin Huang if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 36144093d1a2SGuangbin Huang kinfo->req_rss_size <= max_rss_size) 36154093d1a2SGuangbin Huang kinfo->rss_size = kinfo->req_rss_size; 36164093d1a2SGuangbin Huang else if (kinfo->rss_size > max_rss_size || 36174093d1a2SGuangbin Huang (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) 36184093d1a2SGuangbin Huang kinfo->rss_size = max_rss_size; 36194093d1a2SGuangbin Huang 362035244430SJian Shen kinfo->num_tqps = kinfo->tc_info.num_tc * kinfo->rss_size; 36214093d1a2SGuangbin Huang } 36224093d1a2SGuangbin Huang 36234093d1a2SGuangbin Huang static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 36244093d1a2SGuangbin Huang bool rxfh_configured) 36254093d1a2SGuangbin Huang { 36264093d1a2SGuangbin Huang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 36274093d1a2SGuangbin Huang struct hnae3_knic_private_info *kinfo = &handle->kinfo; 36284093d1a2SGuangbin Huang u16 cur_rss_size = kinfo->rss_size; 36294093d1a2SGuangbin Huang u16 cur_tqps = kinfo->num_tqps; 36304093d1a2SGuangbin Huang u32 *rss_indir; 36314093d1a2SGuangbin Huang unsigned int i; 36324093d1a2SGuangbin Huang int ret; 36334093d1a2SGuangbin Huang 36344093d1a2SGuangbin Huang hclgevf_update_rss_size(handle, new_tqps_num); 36354093d1a2SGuangbin Huang 36364093d1a2SGuangbin Huang ret = hclgevf_set_rss_tc_mode(hdev, kinfo->rss_size); 36374093d1a2SGuangbin Huang if (ret) 36384093d1a2SGuangbin Huang return ret; 36394093d1a2SGuangbin Huang 3640cd7e963dSSalil Mehta /* RSS indirection table has been configured by user */ 36414093d1a2SGuangbin Huang if (rxfh_configured) 36424093d1a2SGuangbin Huang goto out; 36434093d1a2SGuangbin Huang 36444093d1a2SGuangbin Huang /* Reinitializes the rss indirect table according to the new RSS size */ 364587ce161eSGuangbin Huang rss_indir = kcalloc(hdev->ae_dev->dev_specs.rss_ind_tbl_size, 364687ce161eSGuangbin Huang sizeof(u32), GFP_KERNEL); 36474093d1a2SGuangbin Huang if (!rss_indir) 36484093d1a2SGuangbin Huang return -ENOMEM; 36494093d1a2SGuangbin Huang 365087ce161eSGuangbin Huang for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 36514093d1a2SGuangbin Huang rss_indir[i] = i % kinfo->rss_size; 36524093d1a2SGuangbin Huang 3653944de484SGuojia Liao hdev->rss_cfg.rss_size = kinfo->rss_size; 3654944de484SGuojia Liao 36554093d1a2SGuangbin Huang ret = hclgevf_set_rss(handle, rss_indir, NULL, 0); 36564093d1a2SGuangbin Huang if (ret) 36574093d1a2SGuangbin Huang dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 36584093d1a2SGuangbin Huang ret); 36594093d1a2SGuangbin Huang 36604093d1a2SGuangbin Huang kfree(rss_indir); 36614093d1a2SGuangbin Huang 36624093d1a2SGuangbin Huang out: 36634093d1a2SGuangbin Huang if (!ret) 36644093d1a2SGuangbin Huang dev_info(&hdev->pdev->dev, 36654093d1a2SGuangbin Huang "Channels changed, rss_size from %u to %u, tqps from %u to %u", 36664093d1a2SGuangbin Huang cur_rss_size, kinfo->rss_size, 366735244430SJian Shen cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 36684093d1a2SGuangbin Huang 36694093d1a2SGuangbin Huang return ret; 36704093d1a2SGuangbin Huang } 36714093d1a2SGuangbin Huang 3672175ec96bSFuyun Liang static int hclgevf_get_status(struct hnae3_handle *handle) 3673175ec96bSFuyun Liang { 3674175ec96bSFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3675175ec96bSFuyun Liang 3676175ec96bSFuyun Liang return hdev->hw.mac.link; 3677175ec96bSFuyun Liang } 3678175ec96bSFuyun Liang 36794a152de9SFuyun Liang static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 36804a152de9SFuyun Liang u8 *auto_neg, u32 *speed, 36814a152de9SFuyun Liang u8 *duplex) 36824a152de9SFuyun Liang { 36834a152de9SFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 36844a152de9SFuyun Liang 36854a152de9SFuyun Liang if (speed) 36864a152de9SFuyun Liang *speed = hdev->hw.mac.speed; 36874a152de9SFuyun Liang if (duplex) 36884a152de9SFuyun Liang *duplex = hdev->hw.mac.duplex; 36894a152de9SFuyun Liang if (auto_neg) 36904a152de9SFuyun Liang *auto_neg = AUTONEG_DISABLE; 36914a152de9SFuyun Liang } 36924a152de9SFuyun Liang 36934a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 36944a152de9SFuyun Liang u8 duplex) 36954a152de9SFuyun Liang { 36964a152de9SFuyun Liang hdev->hw.mac.speed = speed; 36974a152de9SFuyun Liang hdev->hw.mac.duplex = duplex; 36984a152de9SFuyun Liang } 36994a152de9SFuyun Liang 37001731be4cSYonglong Liu static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 37015c9f6b39SPeng Li { 37025c9f6b39SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 37033462207dSYufeng Mo bool gro_en_old = hdev->gro_en; 37043462207dSYufeng Mo int ret; 37055c9f6b39SPeng Li 37063462207dSYufeng Mo hdev->gro_en = enable; 37073462207dSYufeng Mo ret = hclgevf_config_gro(hdev); 37083462207dSYufeng Mo if (ret) 37093462207dSYufeng Mo hdev->gro_en = gro_en_old; 37103462207dSYufeng Mo 37113462207dSYufeng Mo return ret; 37125c9f6b39SPeng Li } 37135c9f6b39SPeng Li 371488d10bd6SJian Shen static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 371588d10bd6SJian Shen u8 *module_type) 3716c136b884SPeng Li { 3717c136b884SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 371888d10bd6SJian Shen 3719c136b884SPeng Li if (media_type) 3720c136b884SPeng Li *media_type = hdev->hw.mac.media_type; 372188d10bd6SJian Shen 372288d10bd6SJian Shen if (module_type) 372388d10bd6SJian Shen *module_type = hdev->hw.mac.module_type; 3724c136b884SPeng Li } 3725c136b884SPeng Li 37264d60291bSHuazhong Tan static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 37274d60291bSHuazhong Tan { 37284d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 37294d60291bSHuazhong Tan 3730aa5c4f17SHuazhong Tan return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 37314d60291bSHuazhong Tan } 37324d60291bSHuazhong Tan 3733fe735c84SHuazhong Tan static bool hclgevf_get_cmdq_stat(struct hnae3_handle *handle) 3734fe735c84SHuazhong Tan { 3735fe735c84SHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3736fe735c84SHuazhong Tan 3737076bb537SJie Wang return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3738fe735c84SHuazhong Tan } 3739fe735c84SHuazhong Tan 37404d60291bSHuazhong Tan static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 37414d60291bSHuazhong Tan { 37424d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 37434d60291bSHuazhong Tan 37444d60291bSHuazhong Tan return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 37454d60291bSHuazhong Tan } 37464d60291bSHuazhong Tan 37474d60291bSHuazhong Tan static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 37484d60291bSHuazhong Tan { 37494d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 37504d60291bSHuazhong Tan 3751c88a6e7dSHuazhong Tan return hdev->rst_stats.hw_rst_done_cnt; 37524d60291bSHuazhong Tan } 37534d60291bSHuazhong Tan 37549194d18bSliuzhongzhu static void hclgevf_get_link_mode(struct hnae3_handle *handle, 37559194d18bSliuzhongzhu unsigned long *supported, 37569194d18bSliuzhongzhu unsigned long *advertising) 37579194d18bSliuzhongzhu { 37589194d18bSliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 37599194d18bSliuzhongzhu 37609194d18bSliuzhongzhu *supported = hdev->hw.mac.supported; 37619194d18bSliuzhongzhu *advertising = hdev->hw.mac.advertising; 37629194d18bSliuzhongzhu } 37639194d18bSliuzhongzhu 37641600c3e5SJian Shen #define MAX_SEPARATE_NUM 4 3765e407efddSHuazhong Tan #define SEPARATOR_VALUE 0xFDFCFBFA 37661600c3e5SJian Shen #define REG_NUM_PER_LINE 4 37671600c3e5SJian Shen #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 37681600c3e5SJian Shen 37691600c3e5SJian Shen static int hclgevf_get_regs_len(struct hnae3_handle *handle) 37701600c3e5SJian Shen { 37711600c3e5SJian Shen int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 37721600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 37731600c3e5SJian Shen 37741600c3e5SJian Shen cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 37751600c3e5SJian Shen common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 37761600c3e5SJian Shen ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 37771600c3e5SJian Shen tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 37781600c3e5SJian Shen 37791600c3e5SJian Shen return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 37801600c3e5SJian Shen tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 37811600c3e5SJian Shen } 37821600c3e5SJian Shen 37831600c3e5SJian Shen static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 37841600c3e5SJian Shen void *data) 37851600c3e5SJian Shen { 37861600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 37871600c3e5SJian Shen int i, j, reg_um, separator_num; 37881600c3e5SJian Shen u32 *reg = data; 37891600c3e5SJian Shen 37901600c3e5SJian Shen *version = hdev->fw_version; 37911600c3e5SJian Shen 37921600c3e5SJian Shen /* fetching per-VF registers values from VF PCIe register space */ 37931600c3e5SJian Shen reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 37941600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 37951600c3e5SJian Shen for (i = 0; i < reg_um; i++) 37961600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 37971600c3e5SJian Shen for (i = 0; i < separator_num; i++) 37981600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 37991600c3e5SJian Shen 38001600c3e5SJian Shen reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 38011600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 38021600c3e5SJian Shen for (i = 0; i < reg_um; i++) 38031600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 38041600c3e5SJian Shen for (i = 0; i < separator_num; i++) 38051600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 38061600c3e5SJian Shen 38071600c3e5SJian Shen reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 38081600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 38091600c3e5SJian Shen for (j = 0; j < hdev->num_tqps; j++) { 38101600c3e5SJian Shen for (i = 0; i < reg_um; i++) 38111600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 38121600c3e5SJian Shen ring_reg_addr_list[i] + 38131600c3e5SJian Shen 0x200 * j); 38141600c3e5SJian Shen for (i = 0; i < separator_num; i++) 38151600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 38161600c3e5SJian Shen } 38171600c3e5SJian Shen 38181600c3e5SJian Shen reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 38191600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 38201600c3e5SJian Shen for (j = 0; j < hdev->num_msi_used - 1; j++) { 38211600c3e5SJian Shen for (i = 0; i < reg_um; i++) 38221600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 38231600c3e5SJian Shen tqp_intr_reg_addr_list[i] + 38241600c3e5SJian Shen 4 * j); 38251600c3e5SJian Shen for (i = 0; i < separator_num; i++) 38261600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 38271600c3e5SJian Shen } 38281600c3e5SJian Shen } 38291600c3e5SJian Shen 383092f11ea1SJian Shen void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 383192f11ea1SJian Shen u8 *port_base_vlan_info, u8 data_size) 383292f11ea1SJian Shen { 383392f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 3834d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 3835a6f7bfdcSJian Shen int ret; 383692f11ea1SJian Shen 383792f11ea1SJian Shen rtnl_lock(); 3838a6f7bfdcSJian Shen 3839b7b5d25bSGuojia Liao if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 3840b7b5d25bSGuojia Liao test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) { 3841a6f7bfdcSJian Shen dev_warn(&hdev->pdev->dev, 3842a6f7bfdcSJian Shen "is resetting when updating port based vlan info\n"); 384392f11ea1SJian Shen rtnl_unlock(); 3844a6f7bfdcSJian Shen return; 3845a6f7bfdcSJian Shen } 3846a6f7bfdcSJian Shen 3847a6f7bfdcSJian Shen ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 3848a6f7bfdcSJian Shen if (ret) { 3849a6f7bfdcSJian Shen rtnl_unlock(); 3850a6f7bfdcSJian Shen return; 3851a6f7bfdcSJian Shen } 385292f11ea1SJian Shen 385392f11ea1SJian Shen /* send msg to PF and wait update port based vlan info */ 3854d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 3855d3410018SYufeng Mo HCLGE_MBX_PORT_BASE_VLAN_CFG); 3856d3410018SYufeng Mo memcpy(send_msg.data, port_base_vlan_info, data_size); 3857a6f7bfdcSJian Shen ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3858a6f7bfdcSJian Shen if (!ret) { 385992f11ea1SJian Shen if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 3860a6f7bfdcSJian Shen nic->port_base_vlan_state = state; 386192f11ea1SJian Shen else 386292f11ea1SJian Shen nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 3863a6f7bfdcSJian Shen } 386492f11ea1SJian Shen 386592f11ea1SJian Shen hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 386692f11ea1SJian Shen rtnl_unlock(); 386792f11ea1SJian Shen } 386892f11ea1SJian Shen 3869e2cb1decSSalil Mehta static const struct hnae3_ae_ops hclgevf_ops = { 3870e2cb1decSSalil Mehta .init_ae_dev = hclgevf_init_ae_dev, 3871e2cb1decSSalil Mehta .uninit_ae_dev = hclgevf_uninit_ae_dev, 3872bb1890d5SJiaran Zhang .reset_prepare = hclgevf_reset_prepare_general, 3873bb1890d5SJiaran Zhang .reset_done = hclgevf_reset_done, 3874e718a93fSPeng Li .init_client_instance = hclgevf_init_client_instance, 3875e718a93fSPeng Li .uninit_client_instance = hclgevf_uninit_client_instance, 3876e2cb1decSSalil Mehta .start = hclgevf_ae_start, 3877e2cb1decSSalil Mehta .stop = hclgevf_ae_stop, 3878a6d818e3SYunsheng Lin .client_start = hclgevf_client_start, 3879a6d818e3SYunsheng Lin .client_stop = hclgevf_client_stop, 3880e2cb1decSSalil Mehta .map_ring_to_vector = hclgevf_map_ring_to_vector, 3881e2cb1decSSalil Mehta .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 3882e2cb1decSSalil Mehta .get_vector = hclgevf_get_vector, 38830d3e6631SYunsheng Lin .put_vector = hclgevf_put_vector, 3884e2cb1decSSalil Mehta .reset_queue = hclgevf_reset_tqp, 3885e2cb1decSSalil Mehta .get_mac_addr = hclgevf_get_mac_addr, 3886e2cb1decSSalil Mehta .set_mac_addr = hclgevf_set_mac_addr, 3887e2cb1decSSalil Mehta .add_uc_addr = hclgevf_add_uc_addr, 3888e2cb1decSSalil Mehta .rm_uc_addr = hclgevf_rm_uc_addr, 3889e2cb1decSSalil Mehta .add_mc_addr = hclgevf_add_mc_addr, 3890e2cb1decSSalil Mehta .rm_mc_addr = hclgevf_rm_mc_addr, 3891e2cb1decSSalil Mehta .get_stats = hclgevf_get_stats, 3892e2cb1decSSalil Mehta .update_stats = hclgevf_update_stats, 3893e2cb1decSSalil Mehta .get_strings = hclgevf_get_strings, 3894e2cb1decSSalil Mehta .get_sset_count = hclgevf_get_sset_count, 3895e2cb1decSSalil Mehta .get_rss_key_size = hclgevf_get_rss_key_size, 3896e2cb1decSSalil Mehta .get_rss = hclgevf_get_rss, 3897e2cb1decSSalil Mehta .set_rss = hclgevf_set_rss, 3898d97b3072SJian Shen .get_rss_tuple = hclgevf_get_rss_tuple, 3899d97b3072SJian Shen .set_rss_tuple = hclgevf_set_rss_tuple, 3900e2cb1decSSalil Mehta .get_tc_size = hclgevf_get_tc_size, 3901e2cb1decSSalil Mehta .get_fw_version = hclgevf_get_fw_version, 3902e2cb1decSSalil Mehta .set_vlan_filter = hclgevf_set_vlan_filter, 3903fa6a262aSJian Shen .enable_vlan_filter = hclgevf_enable_vlan_filter, 3904b2641e2aSYunsheng Lin .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 39056d4c3981SSalil Mehta .reset_event = hclgevf_reset_event, 3906720bd583SHuazhong Tan .set_default_reset_request = hclgevf_set_def_reset_request, 39074093d1a2SGuangbin Huang .set_channels = hclgevf_set_channels, 3908849e4607SPeng Li .get_channels = hclgevf_get_channels, 3909cc719218SPeng Li .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 39101600c3e5SJian Shen .get_regs_len = hclgevf_get_regs_len, 39111600c3e5SJian Shen .get_regs = hclgevf_get_regs, 3912175ec96bSFuyun Liang .get_status = hclgevf_get_status, 39134a152de9SFuyun Liang .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3914c136b884SPeng Li .get_media_type = hclgevf_get_media_type, 39154d60291bSHuazhong Tan .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 39164d60291bSHuazhong Tan .ae_dev_resetting = hclgevf_ae_dev_resetting, 39174d60291bSHuazhong Tan .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 39185c9f6b39SPeng Li .set_gro_en = hclgevf_gro_en, 3919818f1675SYunsheng Lin .set_mtu = hclgevf_set_mtu, 39200c29d191Sliuzhongzhu .get_global_queue_id = hclgevf_get_qid_global, 39218cdb992fSJian Shen .set_timer_task = hclgevf_set_timer_task, 39229194d18bSliuzhongzhu .get_link_mode = hclgevf_get_link_mode, 3923e196ec75SJian Shen .set_promisc_mode = hclgevf_set_promisc_mode, 3924c631c696SJian Shen .request_update_promisc_mode = hclgevf_request_update_promisc_mode, 3925fe735c84SHuazhong Tan .get_cmdq_stat = hclgevf_get_cmdq_stat, 3926e2cb1decSSalil Mehta }; 3927e2cb1decSSalil Mehta 3928e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf = { 3929e2cb1decSSalil Mehta .ops = &hclgevf_ops, 3930e2cb1decSSalil Mehta .pdev_id_table = ae_algovf_pci_tbl, 3931e2cb1decSSalil Mehta }; 3932e2cb1decSSalil Mehta 3933e2cb1decSSalil Mehta static int hclgevf_init(void) 3934e2cb1decSSalil Mehta { 3935e2cb1decSSalil Mehta pr_info("%s is initializing\n", HCLGEVF_NAME); 3936e2cb1decSSalil Mehta 3937f29da408SYufeng Mo hclgevf_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGEVF_NAME); 39380ea68902SYunsheng Lin if (!hclgevf_wq) { 39390ea68902SYunsheng Lin pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME); 39400ea68902SYunsheng Lin return -ENOMEM; 39410ea68902SYunsheng Lin } 39420ea68902SYunsheng Lin 3943854cf33aSFuyun Liang hnae3_register_ae_algo(&ae_algovf); 3944854cf33aSFuyun Liang 3945854cf33aSFuyun Liang return 0; 3946e2cb1decSSalil Mehta } 3947e2cb1decSSalil Mehta 3948e2cb1decSSalil Mehta static void hclgevf_exit(void) 3949e2cb1decSSalil Mehta { 3950e2cb1decSSalil Mehta hnae3_unregister_ae_algo(&ae_algovf); 39510ea68902SYunsheng Lin destroy_workqueue(hclgevf_wq); 3952e2cb1decSSalil Mehta } 3953e2cb1decSSalil Mehta module_init(hclgevf_init); 3954e2cb1decSSalil Mehta module_exit(hclgevf_exit); 3955e2cb1decSSalil Mehta 3956e2cb1decSSalil Mehta MODULE_LICENSE("GPL"); 3957e2cb1decSSalil Mehta MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3958e2cb1decSSalil Mehta MODULE_DESCRIPTION("HCLGEVF Driver"); 3959e2cb1decSSalil Mehta MODULE_VERSION(HCLGEVF_MOD_VERSION); 3960