1e2cb1decSSalil Mehta // SPDX-License-Identifier: GPL-2.0+ 2e2cb1decSSalil Mehta // Copyright (c) 2016-2017 Hisilicon Limited. 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #include <linux/etherdevice.h> 5aa5c4f17SHuazhong Tan #include <linux/iopoll.h> 66988eb2aSSalil Mehta #include <net/rtnetlink.h> 7e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 8e2cb1decSSalil Mehta #include "hclgevf_main.h" 9e2cb1decSSalil Mehta #include "hclge_mbx.h" 10e2cb1decSSalil Mehta #include "hnae3.h" 11e2cb1decSSalil Mehta 12e2cb1decSSalil Mehta #define HCLGEVF_NAME "hclgevf" 13e2cb1decSSalil Mehta 149c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 15e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf; 16e2cb1decSSalil Mehta 17e2cb1decSSalil Mehta static const struct pci_device_id ae_algovf_pci_tbl[] = { 18e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 19e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 20e2cb1decSSalil Mehta /* required last entry */ 21e2cb1decSSalil Mehta {0, } 22e2cb1decSSalil Mehta }; 23e2cb1decSSalil Mehta 24472d7eceSJian Shen static const u8 hclgevf_hash_key[] = { 25472d7eceSJian Shen 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 26472d7eceSJian Shen 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 27472d7eceSJian Shen 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 28472d7eceSJian Shen 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 29472d7eceSJian Shen 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 30472d7eceSJian Shen }; 31472d7eceSJian Shen 322f550a46SYunsheng Lin MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 332f550a46SYunsheng Lin 341600c3e5SJian Shen static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 351600c3e5SJian Shen HCLGEVF_CMDQ_TX_ADDR_H_REG, 361600c3e5SJian Shen HCLGEVF_CMDQ_TX_DEPTH_REG, 371600c3e5SJian Shen HCLGEVF_CMDQ_TX_TAIL_REG, 381600c3e5SJian Shen HCLGEVF_CMDQ_TX_HEAD_REG, 391600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_L_REG, 401600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_H_REG, 411600c3e5SJian Shen HCLGEVF_CMDQ_RX_DEPTH_REG, 421600c3e5SJian Shen HCLGEVF_CMDQ_RX_TAIL_REG, 431600c3e5SJian Shen HCLGEVF_CMDQ_RX_HEAD_REG, 441600c3e5SJian Shen HCLGEVF_VECTOR0_CMDQ_SRC_REG, 451600c3e5SJian Shen HCLGEVF_CMDQ_INTR_STS_REG, 461600c3e5SJian Shen HCLGEVF_CMDQ_INTR_EN_REG, 471600c3e5SJian Shen HCLGEVF_CMDQ_INTR_GEN_REG}; 481600c3e5SJian Shen 491600c3e5SJian Shen static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 501600c3e5SJian Shen HCLGEVF_RST_ING, 511600c3e5SJian Shen HCLGEVF_GRO_EN_REG}; 521600c3e5SJian Shen 531600c3e5SJian Shen static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 541600c3e5SJian Shen HCLGEVF_RING_RX_ADDR_H_REG, 551600c3e5SJian Shen HCLGEVF_RING_RX_BD_NUM_REG, 561600c3e5SJian Shen HCLGEVF_RING_RX_BD_LENGTH_REG, 571600c3e5SJian Shen HCLGEVF_RING_RX_MERGE_EN_REG, 581600c3e5SJian Shen HCLGEVF_RING_RX_TAIL_REG, 591600c3e5SJian Shen HCLGEVF_RING_RX_HEAD_REG, 601600c3e5SJian Shen HCLGEVF_RING_RX_FBD_NUM_REG, 611600c3e5SJian Shen HCLGEVF_RING_RX_OFFSET_REG, 621600c3e5SJian Shen HCLGEVF_RING_RX_FBD_OFFSET_REG, 631600c3e5SJian Shen HCLGEVF_RING_RX_STASH_REG, 641600c3e5SJian Shen HCLGEVF_RING_RX_BD_ERR_REG, 651600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_L_REG, 661600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_H_REG, 671600c3e5SJian Shen HCLGEVF_RING_TX_BD_NUM_REG, 681600c3e5SJian Shen HCLGEVF_RING_TX_PRIORITY_REG, 691600c3e5SJian Shen HCLGEVF_RING_TX_TC_REG, 701600c3e5SJian Shen HCLGEVF_RING_TX_MERGE_EN_REG, 711600c3e5SJian Shen HCLGEVF_RING_TX_TAIL_REG, 721600c3e5SJian Shen HCLGEVF_RING_TX_HEAD_REG, 731600c3e5SJian Shen HCLGEVF_RING_TX_FBD_NUM_REG, 741600c3e5SJian Shen HCLGEVF_RING_TX_OFFSET_REG, 751600c3e5SJian Shen HCLGEVF_RING_TX_EBD_NUM_REG, 761600c3e5SJian Shen HCLGEVF_RING_TX_EBD_OFFSET_REG, 771600c3e5SJian Shen HCLGEVF_RING_TX_BD_ERR_REG, 781600c3e5SJian Shen HCLGEVF_RING_EN_REG}; 791600c3e5SJian Shen 801600c3e5SJian Shen static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 811600c3e5SJian Shen HCLGEVF_TQP_INTR_GL0_REG, 821600c3e5SJian Shen HCLGEVF_TQP_INTR_GL1_REG, 831600c3e5SJian Shen HCLGEVF_TQP_INTR_GL2_REG, 841600c3e5SJian Shen HCLGEVF_TQP_INTR_RL_REG}; 851600c3e5SJian Shen 86e2cb1decSSalil Mehta static inline struct hclgevf_dev *hclgevf_ae_get_hdev( 87e2cb1decSSalil Mehta struct hnae3_handle *handle) 88e2cb1decSSalil Mehta { 89eed9535fSPeng Li if (!handle->client) 90eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, nic); 91eed9535fSPeng Li else if (handle->client->type == HNAE3_CLIENT_ROCE) 92eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, roce); 93eed9535fSPeng Li else 94e2cb1decSSalil Mehta return container_of(handle, struct hclgevf_dev, nic); 95e2cb1decSSalil Mehta } 96e2cb1decSSalil Mehta 97e2cb1decSSalil Mehta static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 98e2cb1decSSalil Mehta { 99b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 100e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 101e2cb1decSSalil Mehta struct hclgevf_desc desc; 102e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 103e2cb1decSSalil Mehta int status; 104e2cb1decSSalil Mehta int i; 105e2cb1decSSalil Mehta 106b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 107b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 108e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 109e2cb1decSSalil Mehta HCLGEVF_OPC_QUERY_RX_STATUS, 110e2cb1decSSalil Mehta true); 111e2cb1decSSalil Mehta 112e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 113e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 114e2cb1decSSalil Mehta if (status) { 115e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 116e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 117e2cb1decSSalil Mehta status, i); 118e2cb1decSSalil Mehta return status; 119e2cb1decSSalil Mehta } 120e2cb1decSSalil Mehta tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 121cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 122e2cb1decSSalil Mehta 123e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 124e2cb1decSSalil Mehta true); 125e2cb1decSSalil Mehta 126e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 127e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 128e2cb1decSSalil Mehta if (status) { 129e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 130e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 131e2cb1decSSalil Mehta status, i); 132e2cb1decSSalil Mehta return status; 133e2cb1decSSalil Mehta } 134e2cb1decSSalil Mehta tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 135cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 136e2cb1decSSalil Mehta } 137e2cb1decSSalil Mehta 138e2cb1decSSalil Mehta return 0; 139e2cb1decSSalil Mehta } 140e2cb1decSSalil Mehta 141e2cb1decSSalil Mehta static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 142e2cb1decSSalil Mehta { 143e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo = &handle->kinfo; 144e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 145e2cb1decSSalil Mehta u64 *buff = data; 146e2cb1decSSalil Mehta int i; 147e2cb1decSSalil Mehta 148b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 149b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 150e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 151e2cb1decSSalil Mehta } 152e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 153b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 154e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 155e2cb1decSSalil Mehta } 156e2cb1decSSalil Mehta 157e2cb1decSSalil Mehta return buff; 158e2cb1decSSalil Mehta } 159e2cb1decSSalil Mehta 160e2cb1decSSalil Mehta static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 161e2cb1decSSalil Mehta { 162b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 163e2cb1decSSalil Mehta 164b4f1d303SJian Shen return kinfo->num_tqps * 2; 165e2cb1decSSalil Mehta } 166e2cb1decSSalil Mehta 167e2cb1decSSalil Mehta static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 168e2cb1decSSalil Mehta { 169b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 170e2cb1decSSalil Mehta u8 *buff = data; 171e2cb1decSSalil Mehta int i = 0; 172e2cb1decSSalil Mehta 173b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 174b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 175e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1760c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 177e2cb1decSSalil Mehta tqp->index); 178e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 179e2cb1decSSalil Mehta } 180e2cb1decSSalil Mehta 181b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 182b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 183e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1840c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 185e2cb1decSSalil Mehta tqp->index); 186e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 187e2cb1decSSalil Mehta } 188e2cb1decSSalil Mehta 189e2cb1decSSalil Mehta return buff; 190e2cb1decSSalil Mehta } 191e2cb1decSSalil Mehta 192e2cb1decSSalil Mehta static void hclgevf_update_stats(struct hnae3_handle *handle, 193e2cb1decSSalil Mehta struct net_device_stats *net_stats) 194e2cb1decSSalil Mehta { 195e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 196e2cb1decSSalil Mehta int status; 197e2cb1decSSalil Mehta 198e2cb1decSSalil Mehta status = hclgevf_tqps_update_stats(handle); 199e2cb1decSSalil Mehta if (status) 200e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 201e2cb1decSSalil Mehta "VF update of TQPS stats fail, status = %d.\n", 202e2cb1decSSalil Mehta status); 203e2cb1decSSalil Mehta } 204e2cb1decSSalil Mehta 205e2cb1decSSalil Mehta static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 206e2cb1decSSalil Mehta { 207e2cb1decSSalil Mehta if (strset == ETH_SS_TEST) 208e2cb1decSSalil Mehta return -EOPNOTSUPP; 209e2cb1decSSalil Mehta else if (strset == ETH_SS_STATS) 210e2cb1decSSalil Mehta return hclgevf_tqps_get_sset_count(handle, strset); 211e2cb1decSSalil Mehta 212e2cb1decSSalil Mehta return 0; 213e2cb1decSSalil Mehta } 214e2cb1decSSalil Mehta 215e2cb1decSSalil Mehta static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 216e2cb1decSSalil Mehta u8 *data) 217e2cb1decSSalil Mehta { 218e2cb1decSSalil Mehta u8 *p = (char *)data; 219e2cb1decSSalil Mehta 220e2cb1decSSalil Mehta if (strset == ETH_SS_STATS) 221e2cb1decSSalil Mehta p = hclgevf_tqps_get_strings(handle, p); 222e2cb1decSSalil Mehta } 223e2cb1decSSalil Mehta 224e2cb1decSSalil Mehta static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 225e2cb1decSSalil Mehta { 226e2cb1decSSalil Mehta hclgevf_tqps_get_stats(handle, data); 227e2cb1decSSalil Mehta } 228e2cb1decSSalil Mehta 229e2cb1decSSalil Mehta static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 230e2cb1decSSalil Mehta { 231e2cb1decSSalil Mehta u8 resp_msg; 232e2cb1decSSalil Mehta int status; 233e2cb1decSSalil Mehta 234e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 235e2cb1decSSalil Mehta true, &resp_msg, sizeof(u8)); 236e2cb1decSSalil Mehta if (status) { 237e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 238e2cb1decSSalil Mehta "VF request to get TC info from PF failed %d", 239e2cb1decSSalil Mehta status); 240e2cb1decSSalil Mehta return status; 241e2cb1decSSalil Mehta } 242e2cb1decSSalil Mehta 243e2cb1decSSalil Mehta hdev->hw_tc_map = resp_msg; 244e2cb1decSSalil Mehta 245e2cb1decSSalil Mehta return 0; 246e2cb1decSSalil Mehta } 247e2cb1decSSalil Mehta 24892f11ea1SJian Shen static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 24992f11ea1SJian Shen { 25092f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 25192f11ea1SJian Shen u8 resp_msg; 25292f11ea1SJian Shen int ret; 25392f11ea1SJian Shen 25492f11ea1SJian Shen ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 25592f11ea1SJian Shen HCLGE_MBX_GET_PORT_BASE_VLAN_STATE, 25692f11ea1SJian Shen NULL, 0, true, &resp_msg, sizeof(u8)); 25792f11ea1SJian Shen if (ret) { 25892f11ea1SJian Shen dev_err(&hdev->pdev->dev, 25992f11ea1SJian Shen "VF request to get port based vlan state failed %d", 26092f11ea1SJian Shen ret); 26192f11ea1SJian Shen return ret; 26292f11ea1SJian Shen } 26392f11ea1SJian Shen 26492f11ea1SJian Shen nic->port_base_vlan_state = resp_msg; 26592f11ea1SJian Shen 26692f11ea1SJian Shen return 0; 26792f11ea1SJian Shen } 26892f11ea1SJian Shen 2696cee6fc3SJian Shen static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 270e2cb1decSSalil Mehta { 271c0425944SPeng Li #define HCLGEVF_TQPS_RSS_INFO_LEN 6 272e2cb1decSSalil Mehta u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 273e2cb1decSSalil Mehta int status; 274e2cb1decSSalil Mehta 275e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 276e2cb1decSSalil Mehta true, resp_msg, 277e2cb1decSSalil Mehta HCLGEVF_TQPS_RSS_INFO_LEN); 278e2cb1decSSalil Mehta if (status) { 279e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 280e2cb1decSSalil Mehta "VF request to get tqp info from PF failed %d", 281e2cb1decSSalil Mehta status); 282e2cb1decSSalil Mehta return status; 283e2cb1decSSalil Mehta } 284e2cb1decSSalil Mehta 285e2cb1decSSalil Mehta memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 286e2cb1decSSalil Mehta memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 287c0425944SPeng Li memcpy(&hdev->rx_buf_len, &resp_msg[4], sizeof(u16)); 288c0425944SPeng Li 289c0425944SPeng Li return 0; 290c0425944SPeng Li } 291c0425944SPeng Li 292c0425944SPeng Li static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 293c0425944SPeng Li { 294c0425944SPeng Li #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 295c0425944SPeng Li u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 296c0425944SPeng Li int ret; 297c0425944SPeng Li 298c0425944SPeng Li ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QDEPTH, 0, NULL, 0, 299c0425944SPeng Li true, resp_msg, 300c0425944SPeng Li HCLGEVF_TQPS_DEPTH_INFO_LEN); 301c0425944SPeng Li if (ret) { 302c0425944SPeng Li dev_err(&hdev->pdev->dev, 303c0425944SPeng Li "VF request to get tqp depth info from PF failed %d", 304c0425944SPeng Li ret); 305c0425944SPeng Li return ret; 306c0425944SPeng Li } 307c0425944SPeng Li 308c0425944SPeng Li memcpy(&hdev->num_tx_desc, &resp_msg[0], sizeof(u16)); 309c0425944SPeng Li memcpy(&hdev->num_rx_desc, &resp_msg[2], sizeof(u16)); 310e2cb1decSSalil Mehta 311e2cb1decSSalil Mehta return 0; 312e2cb1decSSalil Mehta } 313e2cb1decSSalil Mehta 3140c29d191Sliuzhongzhu static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 3150c29d191Sliuzhongzhu { 3160c29d191Sliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3170c29d191Sliuzhongzhu u8 msg_data[2], resp_data[2]; 3180c29d191Sliuzhongzhu u16 qid_in_pf = 0; 3190c29d191Sliuzhongzhu int ret; 3200c29d191Sliuzhongzhu 3210c29d191Sliuzhongzhu memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 3220c29d191Sliuzhongzhu 3230c29d191Sliuzhongzhu ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data, 3240c29d191Sliuzhongzhu 2, true, resp_data, 2); 3250c29d191Sliuzhongzhu if (!ret) 3260c29d191Sliuzhongzhu qid_in_pf = *(u16 *)resp_data; 3270c29d191Sliuzhongzhu 3280c29d191Sliuzhongzhu return qid_in_pf; 3290c29d191Sliuzhongzhu } 3300c29d191Sliuzhongzhu 3319c3e7130Sliuzhongzhu static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 3329c3e7130Sliuzhongzhu { 3339c3e7130Sliuzhongzhu u8 resp_msg; 3349c3e7130Sliuzhongzhu int ret; 3359c3e7130Sliuzhongzhu 3369c3e7130Sliuzhongzhu ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_MEDIA_TYPE, 0, NULL, 0, 3379c3e7130Sliuzhongzhu true, &resp_msg, sizeof(resp_msg)); 3389c3e7130Sliuzhongzhu if (ret) { 3399c3e7130Sliuzhongzhu dev_err(&hdev->pdev->dev, 3409c3e7130Sliuzhongzhu "VF request to get the pf port media type failed %d", 3419c3e7130Sliuzhongzhu ret); 3429c3e7130Sliuzhongzhu return ret; 3439c3e7130Sliuzhongzhu } 3449c3e7130Sliuzhongzhu 3459c3e7130Sliuzhongzhu hdev->hw.mac.media_type = resp_msg; 3469c3e7130Sliuzhongzhu 3479c3e7130Sliuzhongzhu return 0; 3489c3e7130Sliuzhongzhu } 3499c3e7130Sliuzhongzhu 350e2cb1decSSalil Mehta static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 351e2cb1decSSalil Mehta { 352e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 353e2cb1decSSalil Mehta int i; 354e2cb1decSSalil Mehta 355e2cb1decSSalil Mehta hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 356e2cb1decSSalil Mehta sizeof(struct hclgevf_tqp), GFP_KERNEL); 357e2cb1decSSalil Mehta if (!hdev->htqp) 358e2cb1decSSalil Mehta return -ENOMEM; 359e2cb1decSSalil Mehta 360e2cb1decSSalil Mehta tqp = hdev->htqp; 361e2cb1decSSalil Mehta 362e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 363e2cb1decSSalil Mehta tqp->dev = &hdev->pdev->dev; 364e2cb1decSSalil Mehta tqp->index = i; 365e2cb1decSSalil Mehta 366e2cb1decSSalil Mehta tqp->q.ae_algo = &ae_algovf; 367e2cb1decSSalil Mehta tqp->q.buf_size = hdev->rx_buf_len; 368c0425944SPeng Li tqp->q.tx_desc_num = hdev->num_tx_desc; 369c0425944SPeng Li tqp->q.rx_desc_num = hdev->num_rx_desc; 370e2cb1decSSalil Mehta tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 371e2cb1decSSalil Mehta i * HCLGEVF_TQP_REG_SIZE; 372e2cb1decSSalil Mehta 373e2cb1decSSalil Mehta tqp++; 374e2cb1decSSalil Mehta } 375e2cb1decSSalil Mehta 376e2cb1decSSalil Mehta return 0; 377e2cb1decSSalil Mehta } 378e2cb1decSSalil Mehta 379e2cb1decSSalil Mehta static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 380e2cb1decSSalil Mehta { 381e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 382e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo; 383e2cb1decSSalil Mehta u16 new_tqps = hdev->num_tqps; 384e2cb1decSSalil Mehta int i; 385e2cb1decSSalil Mehta 386e2cb1decSSalil Mehta kinfo = &nic->kinfo; 387e2cb1decSSalil Mehta kinfo->num_tc = 0; 388c0425944SPeng Li kinfo->num_tx_desc = hdev->num_tx_desc; 389c0425944SPeng Li kinfo->num_rx_desc = hdev->num_rx_desc; 390e2cb1decSSalil Mehta kinfo->rx_buf_len = hdev->rx_buf_len; 391e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 392e2cb1decSSalil Mehta if (hdev->hw_tc_map & BIT(i)) 393e2cb1decSSalil Mehta kinfo->num_tc++; 394e2cb1decSSalil Mehta 395e2cb1decSSalil Mehta kinfo->rss_size 396e2cb1decSSalil Mehta = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 397e2cb1decSSalil Mehta new_tqps = kinfo->rss_size * kinfo->num_tc; 398e2cb1decSSalil Mehta kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 399e2cb1decSSalil Mehta 400e2cb1decSSalil Mehta kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 401e2cb1decSSalil Mehta sizeof(struct hnae3_queue *), GFP_KERNEL); 402e2cb1decSSalil Mehta if (!kinfo->tqp) 403e2cb1decSSalil Mehta return -ENOMEM; 404e2cb1decSSalil Mehta 405e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 406e2cb1decSSalil Mehta hdev->htqp[i].q.handle = &hdev->nic; 407e2cb1decSSalil Mehta hdev->htqp[i].q.tqp_index = i; 408e2cb1decSSalil Mehta kinfo->tqp[i] = &hdev->htqp[i].q; 409e2cb1decSSalil Mehta } 410e2cb1decSSalil Mehta 411e2cb1decSSalil Mehta return 0; 412e2cb1decSSalil Mehta } 413e2cb1decSSalil Mehta 414e2cb1decSSalil Mehta static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 415e2cb1decSSalil Mehta { 416e2cb1decSSalil Mehta int status; 417e2cb1decSSalil Mehta u8 resp_msg; 418e2cb1decSSalil Mehta 419e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 420e2cb1decSSalil Mehta 0, false, &resp_msg, sizeof(u8)); 421e2cb1decSSalil Mehta if (status) 422e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 423e2cb1decSSalil Mehta "VF failed to fetch link status(%d) from PF", status); 424e2cb1decSSalil Mehta } 425e2cb1decSSalil Mehta 426e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 427e2cb1decSSalil Mehta { 42845e92b7eSPeng Li struct hnae3_handle *rhandle = &hdev->roce; 429e2cb1decSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 43045e92b7eSPeng Li struct hnae3_client *rclient; 431e2cb1decSSalil Mehta struct hnae3_client *client; 432e2cb1decSSalil Mehta 433e2cb1decSSalil Mehta client = handle->client; 43445e92b7eSPeng Li rclient = hdev->roce_client; 435e2cb1decSSalil Mehta 436582d37bbSPeng Li link_state = 437582d37bbSPeng Li test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 438582d37bbSPeng Li 439e2cb1decSSalil Mehta if (link_state != hdev->hw.mac.link) { 440e2cb1decSSalil Mehta client->ops->link_status_change(handle, !!link_state); 44145e92b7eSPeng Li if (rclient && rclient->ops->link_status_change) 44245e92b7eSPeng Li rclient->ops->link_status_change(rhandle, !!link_state); 443e2cb1decSSalil Mehta hdev->hw.mac.link = link_state; 444e2cb1decSSalil Mehta } 445e2cb1decSSalil Mehta } 446e2cb1decSSalil Mehta 447538abaf3SYueHaibing static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 4489194d18bSliuzhongzhu { 4499194d18bSliuzhongzhu #define HCLGEVF_ADVERTISING 0 4509194d18bSliuzhongzhu #define HCLGEVF_SUPPORTED 1 4519194d18bSliuzhongzhu u8 send_msg; 4529194d18bSliuzhongzhu u8 resp_msg; 4539194d18bSliuzhongzhu 4549194d18bSliuzhongzhu send_msg = HCLGEVF_ADVERTISING; 4559194d18bSliuzhongzhu hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, &send_msg, 4569194d18bSliuzhongzhu sizeof(u8), false, &resp_msg, sizeof(u8)); 4579194d18bSliuzhongzhu send_msg = HCLGEVF_SUPPORTED; 4589194d18bSliuzhongzhu hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, &send_msg, 4599194d18bSliuzhongzhu sizeof(u8), false, &resp_msg, sizeof(u8)); 4609194d18bSliuzhongzhu } 4619194d18bSliuzhongzhu 462e2cb1decSSalil Mehta static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 463e2cb1decSSalil Mehta { 464e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 465e2cb1decSSalil Mehta int ret; 466e2cb1decSSalil Mehta 467e2cb1decSSalil Mehta nic->ae_algo = &ae_algovf; 468e2cb1decSSalil Mehta nic->pdev = hdev->pdev; 469e2cb1decSSalil Mehta nic->numa_node_mask = hdev->numa_node_mask; 470424eb834SSalil Mehta nic->flags |= HNAE3_SUPPORT_VF; 471e2cb1decSSalil Mehta 472e2cb1decSSalil Mehta if (hdev->ae_dev->dev_type != HNAE3_DEV_KNIC) { 473e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "unsupported device type %d\n", 474e2cb1decSSalil Mehta hdev->ae_dev->dev_type); 475e2cb1decSSalil Mehta return -EINVAL; 476e2cb1decSSalil Mehta } 477e2cb1decSSalil Mehta 478e2cb1decSSalil Mehta ret = hclgevf_knic_setup(hdev); 479e2cb1decSSalil Mehta if (ret) 480e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 481e2cb1decSSalil Mehta ret); 482e2cb1decSSalil Mehta return ret; 483e2cb1decSSalil Mehta } 484e2cb1decSSalil Mehta 485e2cb1decSSalil Mehta static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 486e2cb1decSSalil Mehta { 48736cbbdf6SPeng Li if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 48836cbbdf6SPeng Li dev_warn(&hdev->pdev->dev, 48936cbbdf6SPeng Li "vector(vector_id %d) has been freed.\n", vector_id); 49036cbbdf6SPeng Li return; 49136cbbdf6SPeng Li } 49236cbbdf6SPeng Li 493e2cb1decSSalil Mehta hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 494e2cb1decSSalil Mehta hdev->num_msi_left += 1; 495e2cb1decSSalil Mehta hdev->num_msi_used -= 1; 496e2cb1decSSalil Mehta } 497e2cb1decSSalil Mehta 498e2cb1decSSalil Mehta static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 499e2cb1decSSalil Mehta struct hnae3_vector_info *vector_info) 500e2cb1decSSalil Mehta { 501e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 502e2cb1decSSalil Mehta struct hnae3_vector_info *vector = vector_info; 503e2cb1decSSalil Mehta int alloc = 0; 504e2cb1decSSalil Mehta int i, j; 505e2cb1decSSalil Mehta 506e2cb1decSSalil Mehta vector_num = min(hdev->num_msi_left, vector_num); 507e2cb1decSSalil Mehta 508e2cb1decSSalil Mehta for (j = 0; j < vector_num; j++) { 509e2cb1decSSalil Mehta for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 510e2cb1decSSalil Mehta if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 511e2cb1decSSalil Mehta vector->vector = pci_irq_vector(hdev->pdev, i); 512e2cb1decSSalil Mehta vector->io_addr = hdev->hw.io_base + 513e2cb1decSSalil Mehta HCLGEVF_VECTOR_REG_BASE + 514e2cb1decSSalil Mehta (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 515e2cb1decSSalil Mehta hdev->vector_status[i] = 0; 516e2cb1decSSalil Mehta hdev->vector_irq[i] = vector->vector; 517e2cb1decSSalil Mehta 518e2cb1decSSalil Mehta vector++; 519e2cb1decSSalil Mehta alloc++; 520e2cb1decSSalil Mehta 521e2cb1decSSalil Mehta break; 522e2cb1decSSalil Mehta } 523e2cb1decSSalil Mehta } 524e2cb1decSSalil Mehta } 525e2cb1decSSalil Mehta hdev->num_msi_left -= alloc; 526e2cb1decSSalil Mehta hdev->num_msi_used += alloc; 527e2cb1decSSalil Mehta 528e2cb1decSSalil Mehta return alloc; 529e2cb1decSSalil Mehta } 530e2cb1decSSalil Mehta 531e2cb1decSSalil Mehta static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 532e2cb1decSSalil Mehta { 533e2cb1decSSalil Mehta int i; 534e2cb1decSSalil Mehta 535e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 536e2cb1decSSalil Mehta if (vector == hdev->vector_irq[i]) 537e2cb1decSSalil Mehta return i; 538e2cb1decSSalil Mehta 539e2cb1decSSalil Mehta return -EINVAL; 540e2cb1decSSalil Mehta } 541e2cb1decSSalil Mehta 542374ad291SJian Shen static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 543374ad291SJian Shen const u8 hfunc, const u8 *key) 544374ad291SJian Shen { 545374ad291SJian Shen struct hclgevf_rss_config_cmd *req; 546374ad291SJian Shen struct hclgevf_desc desc; 547374ad291SJian Shen int key_offset; 548374ad291SJian Shen int key_size; 549374ad291SJian Shen int ret; 550374ad291SJian Shen 551374ad291SJian Shen req = (struct hclgevf_rss_config_cmd *)desc.data; 552374ad291SJian Shen 553374ad291SJian Shen for (key_offset = 0; key_offset < 3; key_offset++) { 554374ad291SJian Shen hclgevf_cmd_setup_basic_desc(&desc, 555374ad291SJian Shen HCLGEVF_OPC_RSS_GENERIC_CONFIG, 556374ad291SJian Shen false); 557374ad291SJian Shen 558374ad291SJian Shen req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 559374ad291SJian Shen req->hash_config |= 560374ad291SJian Shen (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 561374ad291SJian Shen 562374ad291SJian Shen if (key_offset == 2) 563374ad291SJian Shen key_size = 564374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE - HCLGEVF_RSS_HASH_KEY_NUM * 2; 565374ad291SJian Shen else 566374ad291SJian Shen key_size = HCLGEVF_RSS_HASH_KEY_NUM; 567374ad291SJian Shen 568374ad291SJian Shen memcpy(req->hash_key, 569374ad291SJian Shen key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 570374ad291SJian Shen 571374ad291SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 572374ad291SJian Shen if (ret) { 573374ad291SJian Shen dev_err(&hdev->pdev->dev, 574374ad291SJian Shen "Configure RSS config fail, status = %d\n", 575374ad291SJian Shen ret); 576374ad291SJian Shen return ret; 577374ad291SJian Shen } 578374ad291SJian Shen } 579374ad291SJian Shen 580374ad291SJian Shen return 0; 581374ad291SJian Shen } 582374ad291SJian Shen 583e2cb1decSSalil Mehta static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 584e2cb1decSSalil Mehta { 585e2cb1decSSalil Mehta return HCLGEVF_RSS_KEY_SIZE; 586e2cb1decSSalil Mehta } 587e2cb1decSSalil Mehta 588e2cb1decSSalil Mehta static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 589e2cb1decSSalil Mehta { 590e2cb1decSSalil Mehta return HCLGEVF_RSS_IND_TBL_SIZE; 591e2cb1decSSalil Mehta } 592e2cb1decSSalil Mehta 593e2cb1decSSalil Mehta static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 594e2cb1decSSalil Mehta { 595e2cb1decSSalil Mehta const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 596e2cb1decSSalil Mehta struct hclgevf_rss_indirection_table_cmd *req; 597e2cb1decSSalil Mehta struct hclgevf_desc desc; 598e2cb1decSSalil Mehta int status; 599e2cb1decSSalil Mehta int i, j; 600e2cb1decSSalil Mehta 601e2cb1decSSalil Mehta req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 602e2cb1decSSalil Mehta 603e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 604e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 605e2cb1decSSalil Mehta false); 606e2cb1decSSalil Mehta req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 607e2cb1decSSalil Mehta req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 608e2cb1decSSalil Mehta for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 609e2cb1decSSalil Mehta req->rss_result[j] = 610e2cb1decSSalil Mehta indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 611e2cb1decSSalil Mehta 612e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 613e2cb1decSSalil Mehta if (status) { 614e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 615e2cb1decSSalil Mehta "VF failed(=%d) to set RSS indirection table\n", 616e2cb1decSSalil Mehta status); 617e2cb1decSSalil Mehta return status; 618e2cb1decSSalil Mehta } 619e2cb1decSSalil Mehta } 620e2cb1decSSalil Mehta 621e2cb1decSSalil Mehta return 0; 622e2cb1decSSalil Mehta } 623e2cb1decSSalil Mehta 624e2cb1decSSalil Mehta static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 625e2cb1decSSalil Mehta { 626e2cb1decSSalil Mehta struct hclgevf_rss_tc_mode_cmd *req; 627e2cb1decSSalil Mehta u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 628e2cb1decSSalil Mehta u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 629e2cb1decSSalil Mehta u16 tc_size[HCLGEVF_MAX_TC_NUM]; 630e2cb1decSSalil Mehta struct hclgevf_desc desc; 631e2cb1decSSalil Mehta u16 roundup_size; 632e2cb1decSSalil Mehta int status; 633e2cb1decSSalil Mehta int i; 634e2cb1decSSalil Mehta 635e2cb1decSSalil Mehta req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 636e2cb1decSSalil Mehta 637e2cb1decSSalil Mehta roundup_size = roundup_pow_of_two(rss_size); 638e2cb1decSSalil Mehta roundup_size = ilog2(roundup_size); 639e2cb1decSSalil Mehta 640e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 641e2cb1decSSalil Mehta tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 642e2cb1decSSalil Mehta tc_size[i] = roundup_size; 643e2cb1decSSalil Mehta tc_offset[i] = rss_size * i; 644e2cb1decSSalil Mehta } 645e2cb1decSSalil Mehta 646e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 647e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 648e4e87715SPeng Li hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 649e2cb1decSSalil Mehta (tc_valid[i] & 0x1)); 650e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 651e2cb1decSSalil Mehta HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 652e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 653e2cb1decSSalil Mehta HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 654e2cb1decSSalil Mehta } 655e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 656e2cb1decSSalil Mehta if (status) 657e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 658e2cb1decSSalil Mehta "VF failed(=%d) to set rss tc mode\n", status); 659e2cb1decSSalil Mehta 660e2cb1decSSalil Mehta return status; 661e2cb1decSSalil Mehta } 662e2cb1decSSalil Mehta 663a638b1d8SJian Shen /* for revision 0x20, vf shared the same rss config with pf */ 664a638b1d8SJian Shen static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 665a638b1d8SJian Shen { 666a638b1d8SJian Shen #define HCLGEVF_RSS_MBX_RESP_LEN 8 667a638b1d8SJian Shen 668a638b1d8SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 669a638b1d8SJian Shen u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 670a638b1d8SJian Shen u16 msg_num, hash_key_index; 671a638b1d8SJian Shen u8 index; 672a638b1d8SJian Shen int ret; 673a638b1d8SJian Shen 674a638b1d8SJian Shen msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 675a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN; 676a638b1d8SJian Shen for (index = 0; index < msg_num; index++) { 677a638b1d8SJian Shen ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_RSS_KEY, 0, 678a638b1d8SJian Shen &index, sizeof(index), 679a638b1d8SJian Shen true, resp_msg, 680a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN); 681a638b1d8SJian Shen if (ret) { 682a638b1d8SJian Shen dev_err(&hdev->pdev->dev, 683a638b1d8SJian Shen "VF get rss hash key from PF failed, ret=%d", 684a638b1d8SJian Shen ret); 685a638b1d8SJian Shen return ret; 686a638b1d8SJian Shen } 687a638b1d8SJian Shen 688a638b1d8SJian Shen hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 689a638b1d8SJian Shen if (index == msg_num - 1) 690a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 691a638b1d8SJian Shen &resp_msg[0], 692a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE - hash_key_index); 693a638b1d8SJian Shen else 694a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 695a638b1d8SJian Shen &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 696a638b1d8SJian Shen } 697a638b1d8SJian Shen 698a638b1d8SJian Shen return 0; 699a638b1d8SJian Shen } 700a638b1d8SJian Shen 701e2cb1decSSalil Mehta static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 702e2cb1decSSalil Mehta u8 *hfunc) 703e2cb1decSSalil Mehta { 704e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 705e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 706a638b1d8SJian Shen int i, ret; 707e2cb1decSSalil Mehta 708374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 709374ad291SJian Shen /* Get hash algorithm */ 710374ad291SJian Shen if (hfunc) { 711374ad291SJian Shen switch (rss_cfg->hash_algo) { 712374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 713374ad291SJian Shen *hfunc = ETH_RSS_HASH_TOP; 714374ad291SJian Shen break; 715374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 716374ad291SJian Shen *hfunc = ETH_RSS_HASH_XOR; 717374ad291SJian Shen break; 718374ad291SJian Shen default: 719374ad291SJian Shen *hfunc = ETH_RSS_HASH_UNKNOWN; 720374ad291SJian Shen break; 721374ad291SJian Shen } 722374ad291SJian Shen } 723374ad291SJian Shen 724374ad291SJian Shen /* Get the RSS Key required by the user */ 725374ad291SJian Shen if (key) 726374ad291SJian Shen memcpy(key, rss_cfg->rss_hash_key, 727374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 728a638b1d8SJian Shen } else { 729a638b1d8SJian Shen if (hfunc) 730a638b1d8SJian Shen *hfunc = ETH_RSS_HASH_TOP; 731a638b1d8SJian Shen if (key) { 732a638b1d8SJian Shen ret = hclgevf_get_rss_hash_key(hdev); 733a638b1d8SJian Shen if (ret) 734a638b1d8SJian Shen return ret; 735a638b1d8SJian Shen memcpy(key, rss_cfg->rss_hash_key, 736a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE); 737a638b1d8SJian Shen } 738374ad291SJian Shen } 739374ad291SJian Shen 740e2cb1decSSalil Mehta if (indir) 741e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 742e2cb1decSSalil Mehta indir[i] = rss_cfg->rss_indirection_tbl[i]; 743e2cb1decSSalil Mehta 744374ad291SJian Shen return 0; 745e2cb1decSSalil Mehta } 746e2cb1decSSalil Mehta 747e2cb1decSSalil Mehta static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 748e2cb1decSSalil Mehta const u8 *key, const u8 hfunc) 749e2cb1decSSalil Mehta { 750e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 751e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 752374ad291SJian Shen int ret, i; 753374ad291SJian Shen 754374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 755374ad291SJian Shen /* Set the RSS Hash Key if specififed by the user */ 756374ad291SJian Shen if (key) { 757374ad291SJian Shen switch (hfunc) { 758374ad291SJian Shen case ETH_RSS_HASH_TOP: 759374ad291SJian Shen rss_cfg->hash_algo = 760374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 761374ad291SJian Shen break; 762374ad291SJian Shen case ETH_RSS_HASH_XOR: 763374ad291SJian Shen rss_cfg->hash_algo = 764374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_SIMPLE; 765374ad291SJian Shen break; 766374ad291SJian Shen case ETH_RSS_HASH_NO_CHANGE: 767374ad291SJian Shen break; 768374ad291SJian Shen default: 769374ad291SJian Shen return -EINVAL; 770374ad291SJian Shen } 771374ad291SJian Shen 772374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 773374ad291SJian Shen key); 774374ad291SJian Shen if (ret) 775374ad291SJian Shen return ret; 776374ad291SJian Shen 777374ad291SJian Shen /* Update the shadow RSS key with user specified qids */ 778374ad291SJian Shen memcpy(rss_cfg->rss_hash_key, key, 779374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 780374ad291SJian Shen } 781374ad291SJian Shen } 782e2cb1decSSalil Mehta 783e2cb1decSSalil Mehta /* update the shadow RSS table with user specified qids */ 784e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 785e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = indir[i]; 786e2cb1decSSalil Mehta 787e2cb1decSSalil Mehta /* update the hardware */ 788e2cb1decSSalil Mehta return hclgevf_set_rss_indir_table(hdev); 789e2cb1decSSalil Mehta } 790e2cb1decSSalil Mehta 791d97b3072SJian Shen static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 792d97b3072SJian Shen { 793d97b3072SJian Shen u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 794d97b3072SJian Shen 795d97b3072SJian Shen if (nfc->data & RXH_L4_B_2_3) 796d97b3072SJian Shen hash_sets |= HCLGEVF_D_PORT_BIT; 797d97b3072SJian Shen else 798d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_PORT_BIT; 799d97b3072SJian Shen 800d97b3072SJian Shen if (nfc->data & RXH_IP_SRC) 801d97b3072SJian Shen hash_sets |= HCLGEVF_S_IP_BIT; 802d97b3072SJian Shen else 803d97b3072SJian Shen hash_sets &= ~HCLGEVF_S_IP_BIT; 804d97b3072SJian Shen 805d97b3072SJian Shen if (nfc->data & RXH_IP_DST) 806d97b3072SJian Shen hash_sets |= HCLGEVF_D_IP_BIT; 807d97b3072SJian Shen else 808d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_IP_BIT; 809d97b3072SJian Shen 810d97b3072SJian Shen if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 811d97b3072SJian Shen hash_sets |= HCLGEVF_V_TAG_BIT; 812d97b3072SJian Shen 813d97b3072SJian Shen return hash_sets; 814d97b3072SJian Shen } 815d97b3072SJian Shen 816d97b3072SJian Shen static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 817d97b3072SJian Shen struct ethtool_rxnfc *nfc) 818d97b3072SJian Shen { 819d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 820d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 821d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 822d97b3072SJian Shen struct hclgevf_desc desc; 823d97b3072SJian Shen u8 tuple_sets; 824d97b3072SJian Shen int ret; 825d97b3072SJian Shen 826d97b3072SJian Shen if (handle->pdev->revision == 0x20) 827d97b3072SJian Shen return -EOPNOTSUPP; 828d97b3072SJian Shen 829d97b3072SJian Shen if (nfc->data & 830d97b3072SJian Shen ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 831d97b3072SJian Shen return -EINVAL; 832d97b3072SJian Shen 833d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 834d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 835d97b3072SJian Shen 836d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 837d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 838d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 839d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 840d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 841d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 842d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 843d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 844d97b3072SJian Shen 845d97b3072SJian Shen tuple_sets = hclgevf_get_rss_hash_bits(nfc); 846d97b3072SJian Shen switch (nfc->flow_type) { 847d97b3072SJian Shen case TCP_V4_FLOW: 848d97b3072SJian Shen req->ipv4_tcp_en = tuple_sets; 849d97b3072SJian Shen break; 850d97b3072SJian Shen case TCP_V6_FLOW: 851d97b3072SJian Shen req->ipv6_tcp_en = tuple_sets; 852d97b3072SJian Shen break; 853d97b3072SJian Shen case UDP_V4_FLOW: 854d97b3072SJian Shen req->ipv4_udp_en = tuple_sets; 855d97b3072SJian Shen break; 856d97b3072SJian Shen case UDP_V6_FLOW: 857d97b3072SJian Shen req->ipv6_udp_en = tuple_sets; 858d97b3072SJian Shen break; 859d97b3072SJian Shen case SCTP_V4_FLOW: 860d97b3072SJian Shen req->ipv4_sctp_en = tuple_sets; 861d97b3072SJian Shen break; 862d97b3072SJian Shen case SCTP_V6_FLOW: 863d97b3072SJian Shen if ((nfc->data & RXH_L4_B_0_1) || 864d97b3072SJian Shen (nfc->data & RXH_L4_B_2_3)) 865d97b3072SJian Shen return -EINVAL; 866d97b3072SJian Shen 867d97b3072SJian Shen req->ipv6_sctp_en = tuple_sets; 868d97b3072SJian Shen break; 869d97b3072SJian Shen case IPV4_FLOW: 870d97b3072SJian Shen req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 871d97b3072SJian Shen break; 872d97b3072SJian Shen case IPV6_FLOW: 873d97b3072SJian Shen req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 874d97b3072SJian Shen break; 875d97b3072SJian Shen default: 876d97b3072SJian Shen return -EINVAL; 877d97b3072SJian Shen } 878d97b3072SJian Shen 879d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 880d97b3072SJian Shen if (ret) { 881d97b3072SJian Shen dev_err(&hdev->pdev->dev, 882d97b3072SJian Shen "Set rss tuple fail, status = %d\n", ret); 883d97b3072SJian Shen return ret; 884d97b3072SJian Shen } 885d97b3072SJian Shen 886d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 887d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 888d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 889d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 890d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 891d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 892d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 893d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 894d97b3072SJian Shen return 0; 895d97b3072SJian Shen } 896d97b3072SJian Shen 897d97b3072SJian Shen static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 898d97b3072SJian Shen struct ethtool_rxnfc *nfc) 899d97b3072SJian Shen { 900d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 901d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 902d97b3072SJian Shen u8 tuple_sets; 903d97b3072SJian Shen 904d97b3072SJian Shen if (handle->pdev->revision == 0x20) 905d97b3072SJian Shen return -EOPNOTSUPP; 906d97b3072SJian Shen 907d97b3072SJian Shen nfc->data = 0; 908d97b3072SJian Shen 909d97b3072SJian Shen switch (nfc->flow_type) { 910d97b3072SJian Shen case TCP_V4_FLOW: 911d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 912d97b3072SJian Shen break; 913d97b3072SJian Shen case UDP_V4_FLOW: 914d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 915d97b3072SJian Shen break; 916d97b3072SJian Shen case TCP_V6_FLOW: 917d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 918d97b3072SJian Shen break; 919d97b3072SJian Shen case UDP_V6_FLOW: 920d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 921d97b3072SJian Shen break; 922d97b3072SJian Shen case SCTP_V4_FLOW: 923d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 924d97b3072SJian Shen break; 925d97b3072SJian Shen case SCTP_V6_FLOW: 926d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 927d97b3072SJian Shen break; 928d97b3072SJian Shen case IPV4_FLOW: 929d97b3072SJian Shen case IPV6_FLOW: 930d97b3072SJian Shen tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 931d97b3072SJian Shen break; 932d97b3072SJian Shen default: 933d97b3072SJian Shen return -EINVAL; 934d97b3072SJian Shen } 935d97b3072SJian Shen 936d97b3072SJian Shen if (!tuple_sets) 937d97b3072SJian Shen return 0; 938d97b3072SJian Shen 939d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_PORT_BIT) 940d97b3072SJian Shen nfc->data |= RXH_L4_B_2_3; 941d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_PORT_BIT) 942d97b3072SJian Shen nfc->data |= RXH_L4_B_0_1; 943d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_IP_BIT) 944d97b3072SJian Shen nfc->data |= RXH_IP_DST; 945d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_IP_BIT) 946d97b3072SJian Shen nfc->data |= RXH_IP_SRC; 947d97b3072SJian Shen 948d97b3072SJian Shen return 0; 949d97b3072SJian Shen } 950d97b3072SJian Shen 951d97b3072SJian Shen static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 952d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg) 953d97b3072SJian Shen { 954d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 955d97b3072SJian Shen struct hclgevf_desc desc; 956d97b3072SJian Shen int ret; 957d97b3072SJian Shen 958d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 959d97b3072SJian Shen 960d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 961d97b3072SJian Shen 962d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 963d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 964d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 965d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 966d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 967d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 968d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 969d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 970d97b3072SJian Shen 971d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 972d97b3072SJian Shen if (ret) 973d97b3072SJian Shen dev_err(&hdev->pdev->dev, 974d97b3072SJian Shen "Configure rss input fail, status = %d\n", ret); 975d97b3072SJian Shen return ret; 976d97b3072SJian Shen } 977d97b3072SJian Shen 978e2cb1decSSalil Mehta static int hclgevf_get_tc_size(struct hnae3_handle *handle) 979e2cb1decSSalil Mehta { 980e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 981e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 982e2cb1decSSalil Mehta 983e2cb1decSSalil Mehta return rss_cfg->rss_size; 984e2cb1decSSalil Mehta } 985e2cb1decSSalil Mehta 986e2cb1decSSalil Mehta static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 987b204bc74SPeng Li int vector_id, 988e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 989e2cb1decSSalil Mehta { 990e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 991e2cb1decSSalil Mehta struct hnae3_ring_chain_node *node; 992e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 993e2cb1decSSalil Mehta struct hclgevf_desc desc; 994b204bc74SPeng Li int i = 0; 995e2cb1decSSalil Mehta int status; 996e2cb1decSSalil Mehta u8 type; 997e2cb1decSSalil Mehta 998e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 999e2cb1decSSalil Mehta 1000e2cb1decSSalil Mehta for (node = ring_chain; node; node = node->next) { 10015d02a58dSYunsheng Lin int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 10025d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 10035d02a58dSYunsheng Lin 10045d02a58dSYunsheng Lin if (i == 0) { 10055d02a58dSYunsheng Lin hclgevf_cmd_setup_basic_desc(&desc, 10065d02a58dSYunsheng Lin HCLGEVF_OPC_MBX_VF_TO_PF, 10075d02a58dSYunsheng Lin false); 10085d02a58dSYunsheng Lin type = en ? 10095d02a58dSYunsheng Lin HCLGE_MBX_MAP_RING_TO_VECTOR : 10105d02a58dSYunsheng Lin HCLGE_MBX_UNMAP_RING_TO_VECTOR; 10115d02a58dSYunsheng Lin req->msg[0] = type; 10125d02a58dSYunsheng Lin req->msg[1] = vector_id; 10135d02a58dSYunsheng Lin } 10145d02a58dSYunsheng Lin 10155d02a58dSYunsheng Lin req->msg[idx_offset] = 1016e4e87715SPeng Li hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 10175d02a58dSYunsheng Lin req->msg[idx_offset + 1] = node->tqp_index; 1018e4e87715SPeng Li req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 101979eee410SFuyun Liang HNAE3_RING_GL_IDX_M, 102079eee410SFuyun Liang HNAE3_RING_GL_IDX_S); 102179eee410SFuyun Liang 10225d02a58dSYunsheng Lin i++; 10235d02a58dSYunsheng Lin if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 10245d02a58dSYunsheng Lin HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 10255d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 10265d02a58dSYunsheng Lin !node->next) { 1027e2cb1decSSalil Mehta req->msg[2] = i; 1028e2cb1decSSalil Mehta 1029e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1030e2cb1decSSalil Mehta if (status) { 1031e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1032e2cb1decSSalil Mehta "Map TQP fail, status is %d.\n", 1033e2cb1decSSalil Mehta status); 1034e2cb1decSSalil Mehta return status; 1035e2cb1decSSalil Mehta } 1036e2cb1decSSalil Mehta i = 0; 1037e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 1038e2cb1decSSalil Mehta HCLGEVF_OPC_MBX_VF_TO_PF, 1039e2cb1decSSalil Mehta false); 1040e2cb1decSSalil Mehta req->msg[0] = type; 1041e2cb1decSSalil Mehta req->msg[1] = vector_id; 1042e2cb1decSSalil Mehta } 1043e2cb1decSSalil Mehta } 1044e2cb1decSSalil Mehta 1045e2cb1decSSalil Mehta return 0; 1046e2cb1decSSalil Mehta } 1047e2cb1decSSalil Mehta 1048e2cb1decSSalil Mehta static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1049e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1050e2cb1decSSalil Mehta { 1051b204bc74SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1052b204bc74SPeng Li int vector_id; 1053b204bc74SPeng Li 1054b204bc74SPeng Li vector_id = hclgevf_get_vector_index(hdev, vector); 1055b204bc74SPeng Li if (vector_id < 0) { 1056b204bc74SPeng Li dev_err(&handle->pdev->dev, 1057b204bc74SPeng Li "Get vector index fail. ret =%d\n", vector_id); 1058b204bc74SPeng Li return vector_id; 1059b204bc74SPeng Li } 1060b204bc74SPeng Li 1061b204bc74SPeng Li return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1062e2cb1decSSalil Mehta } 1063e2cb1decSSalil Mehta 1064e2cb1decSSalil Mehta static int hclgevf_unmap_ring_from_vector( 1065e2cb1decSSalil Mehta struct hnae3_handle *handle, 1066e2cb1decSSalil Mehta int vector, 1067e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1068e2cb1decSSalil Mehta { 1069e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1070e2cb1decSSalil Mehta int ret, vector_id; 1071e2cb1decSSalil Mehta 1072dea846e8SHuazhong Tan if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1073dea846e8SHuazhong Tan return 0; 1074dea846e8SHuazhong Tan 1075e2cb1decSSalil Mehta vector_id = hclgevf_get_vector_index(hdev, vector); 1076e2cb1decSSalil Mehta if (vector_id < 0) { 1077e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1078e2cb1decSSalil Mehta "Get vector index fail. ret =%d\n", vector_id); 1079e2cb1decSSalil Mehta return vector_id; 1080e2cb1decSSalil Mehta } 1081e2cb1decSSalil Mehta 1082b204bc74SPeng Li ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 10830d3e6631SYunsheng Lin if (ret) 1084e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1085e2cb1decSSalil Mehta "Unmap ring from vector fail. vector=%d, ret =%d\n", 1086e2cb1decSSalil Mehta vector_id, 1087e2cb1decSSalil Mehta ret); 10880d3e6631SYunsheng Lin 1089e2cb1decSSalil Mehta return ret; 1090e2cb1decSSalil Mehta } 1091e2cb1decSSalil Mehta 10920d3e6631SYunsheng Lin static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 10930d3e6631SYunsheng Lin { 10940d3e6631SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 109503718db9SYunsheng Lin int vector_id; 10960d3e6631SYunsheng Lin 109703718db9SYunsheng Lin vector_id = hclgevf_get_vector_index(hdev, vector); 109803718db9SYunsheng Lin if (vector_id < 0) { 109903718db9SYunsheng Lin dev_err(&handle->pdev->dev, 110003718db9SYunsheng Lin "hclgevf_put_vector get vector index fail. ret =%d\n", 110103718db9SYunsheng Lin vector_id); 110203718db9SYunsheng Lin return vector_id; 110303718db9SYunsheng Lin } 110403718db9SYunsheng Lin 110503718db9SYunsheng Lin hclgevf_free_vector(hdev, vector_id); 1106e2cb1decSSalil Mehta 1107e2cb1decSSalil Mehta return 0; 1108e2cb1decSSalil Mehta } 1109e2cb1decSSalil Mehta 11103b75c3dfSPeng Li static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1111f01f5559SJian Shen bool en_bc_pmc) 1112e2cb1decSSalil Mehta { 1113e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 1114e2cb1decSSalil Mehta struct hclgevf_desc desc; 1115f01f5559SJian Shen int ret; 1116e2cb1decSSalil Mehta 1117e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1118e2cb1decSSalil Mehta 1119e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 1120e2cb1decSSalil Mehta req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 1121f01f5559SJian Shen req->msg[1] = en_bc_pmc ? 1 : 0; 1122e2cb1decSSalil Mehta 1123f01f5559SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1124f01f5559SJian Shen if (ret) 1125e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1126f01f5559SJian Shen "Set promisc mode fail, status is %d.\n", ret); 1127e2cb1decSSalil Mehta 1128f01f5559SJian Shen return ret; 1129e2cb1decSSalil Mehta } 1130e2cb1decSSalil Mehta 1131f01f5559SJian Shen static int hclgevf_set_promisc_mode(struct hclgevf_dev *hdev, bool en_bc_pmc) 1132e2cb1decSSalil Mehta { 1133f01f5559SJian Shen return hclgevf_cmd_set_promisc_mode(hdev, en_bc_pmc); 1134e2cb1decSSalil Mehta } 1135e2cb1decSSalil Mehta 1136e2cb1decSSalil Mehta static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, int tqp_id, 1137e2cb1decSSalil Mehta int stream_id, bool enable) 1138e2cb1decSSalil Mehta { 1139e2cb1decSSalil Mehta struct hclgevf_cfg_com_tqp_queue_cmd *req; 1140e2cb1decSSalil Mehta struct hclgevf_desc desc; 1141e2cb1decSSalil Mehta int status; 1142e2cb1decSSalil Mehta 1143e2cb1decSSalil Mehta req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1144e2cb1decSSalil Mehta 1145e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1146e2cb1decSSalil Mehta false); 1147e2cb1decSSalil Mehta req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1148e2cb1decSSalil Mehta req->stream_id = cpu_to_le16(stream_id); 1149e2cb1decSSalil Mehta req->enable |= enable << HCLGEVF_TQP_ENABLE_B; 1150e2cb1decSSalil Mehta 1151e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1152e2cb1decSSalil Mehta if (status) 1153e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1154e2cb1decSSalil Mehta "TQP enable fail, status =%d.\n", status); 1155e2cb1decSSalil Mehta 1156e2cb1decSSalil Mehta return status; 1157e2cb1decSSalil Mehta } 1158e2cb1decSSalil Mehta 1159e2cb1decSSalil Mehta static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1160e2cb1decSSalil Mehta { 1161b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1162e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 1163e2cb1decSSalil Mehta int i; 1164e2cb1decSSalil Mehta 1165b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 1166b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1167e2cb1decSSalil Mehta memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1168e2cb1decSSalil Mehta } 1169e2cb1decSSalil Mehta } 1170e2cb1decSSalil Mehta 1171e2cb1decSSalil Mehta static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1172e2cb1decSSalil Mehta { 1173e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1174e2cb1decSSalil Mehta 1175e2cb1decSSalil Mehta ether_addr_copy(p, hdev->hw.mac.mac_addr); 1176e2cb1decSSalil Mehta } 1177e2cb1decSSalil Mehta 117859098055SFuyun Liang static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 117959098055SFuyun Liang bool is_first) 1180e2cb1decSSalil Mehta { 1181e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1182e2cb1decSSalil Mehta u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1183e2cb1decSSalil Mehta u8 *new_mac_addr = (u8 *)p; 1184e2cb1decSSalil Mehta u8 msg_data[ETH_ALEN * 2]; 118559098055SFuyun Liang u16 subcode; 1186e2cb1decSSalil Mehta int status; 1187e2cb1decSSalil Mehta 1188e2cb1decSSalil Mehta ether_addr_copy(msg_data, new_mac_addr); 1189e2cb1decSSalil Mehta ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 1190e2cb1decSSalil Mehta 119159098055SFuyun Liang subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 119259098055SFuyun Liang HCLGE_MBX_MAC_VLAN_UC_MODIFY; 119359098055SFuyun Liang 1194e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 119559098055SFuyun Liang subcode, msg_data, ETH_ALEN * 2, 11962097fdefSJian Shen true, NULL, 0); 1197e2cb1decSSalil Mehta if (!status) 1198e2cb1decSSalil Mehta ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1199e2cb1decSSalil Mehta 1200e2cb1decSSalil Mehta return status; 1201e2cb1decSSalil Mehta } 1202e2cb1decSSalil Mehta 1203e2cb1decSSalil Mehta static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1204e2cb1decSSalil Mehta const unsigned char *addr) 1205e2cb1decSSalil Mehta { 1206e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1207e2cb1decSSalil Mehta 1208e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1209e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_ADD, 1210e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1211e2cb1decSSalil Mehta } 1212e2cb1decSSalil Mehta 1213e2cb1decSSalil Mehta static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1214e2cb1decSSalil Mehta const unsigned char *addr) 1215e2cb1decSSalil Mehta { 1216e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1217e2cb1decSSalil Mehta 1218e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1219e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1220e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1221e2cb1decSSalil Mehta } 1222e2cb1decSSalil Mehta 1223e2cb1decSSalil Mehta static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1224e2cb1decSSalil Mehta const unsigned char *addr) 1225e2cb1decSSalil Mehta { 1226e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1227e2cb1decSSalil Mehta 1228e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1229e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_ADD, 1230e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1231e2cb1decSSalil Mehta } 1232e2cb1decSSalil Mehta 1233e2cb1decSSalil Mehta static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1234e2cb1decSSalil Mehta const unsigned char *addr) 1235e2cb1decSSalil Mehta { 1236e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1237e2cb1decSSalil Mehta 1238e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1239e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1240e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1241e2cb1decSSalil Mehta } 1242e2cb1decSSalil Mehta 1243e2cb1decSSalil Mehta static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1244e2cb1decSSalil Mehta __be16 proto, u16 vlan_id, 1245e2cb1decSSalil Mehta bool is_kill) 1246e2cb1decSSalil Mehta { 1247e2cb1decSSalil Mehta #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1248e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1249e2cb1decSSalil Mehta u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1250e2cb1decSSalil Mehta 1251e2cb1decSSalil Mehta if (vlan_id > 4095) 1252e2cb1decSSalil Mehta return -EINVAL; 1253e2cb1decSSalil Mehta 1254e2cb1decSSalil Mehta if (proto != htons(ETH_P_8021Q)) 1255e2cb1decSSalil Mehta return -EPROTONOSUPPORT; 1256e2cb1decSSalil Mehta 1257e2cb1decSSalil Mehta msg_data[0] = is_kill; 1258e2cb1decSSalil Mehta memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1259e2cb1decSSalil Mehta memcpy(&msg_data[3], &proto, sizeof(proto)); 1260e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1261e2cb1decSSalil Mehta HCLGE_MBX_VLAN_FILTER, msg_data, 1262e2cb1decSSalil Mehta HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 1263e2cb1decSSalil Mehta } 1264e2cb1decSSalil Mehta 1265b2641e2aSYunsheng Lin static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1266b2641e2aSYunsheng Lin { 1267b2641e2aSYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1268b2641e2aSYunsheng Lin u8 msg_data; 1269b2641e2aSYunsheng Lin 1270b2641e2aSYunsheng Lin msg_data = enable ? 1 : 0; 1271b2641e2aSYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1272b2641e2aSYunsheng Lin HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1273b2641e2aSYunsheng Lin 1, false, NULL, 0); 1274b2641e2aSYunsheng Lin } 1275b2641e2aSYunsheng Lin 12767fa6be4fSHuazhong Tan static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1277e2cb1decSSalil Mehta { 1278e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1279e2cb1decSSalil Mehta u8 msg_data[2]; 12801a426f8bSPeng Li int ret; 1281e2cb1decSSalil Mehta 1282e2cb1decSSalil Mehta memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 1283e2cb1decSSalil Mehta 12841a426f8bSPeng Li /* disable vf queue before send queue reset msg to PF */ 12851a426f8bSPeng Li ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 12861a426f8bSPeng Li if (ret) 12877fa6be4fSHuazhong Tan return ret; 12881a426f8bSPeng Li 12897fa6be4fSHuazhong Tan return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 12901a426f8bSPeng Li 2, true, NULL, 0); 1291e2cb1decSSalil Mehta } 1292e2cb1decSSalil Mehta 1293818f1675SYunsheng Lin static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1294818f1675SYunsheng Lin { 1295818f1675SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1296818f1675SYunsheng Lin 1297818f1675SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu, 1298818f1675SYunsheng Lin sizeof(new_mtu), true, NULL, 0); 1299818f1675SYunsheng Lin } 1300818f1675SYunsheng Lin 13016988eb2aSSalil Mehta static int hclgevf_notify_client(struct hclgevf_dev *hdev, 13026988eb2aSSalil Mehta enum hnae3_reset_notify_type type) 13036988eb2aSSalil Mehta { 13046988eb2aSSalil Mehta struct hnae3_client *client = hdev->nic_client; 13056988eb2aSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 13066a5f6fa3SHuazhong Tan int ret; 13076988eb2aSSalil Mehta 13086988eb2aSSalil Mehta if (!client->ops->reset_notify) 13096988eb2aSSalil Mehta return -EOPNOTSUPP; 13106988eb2aSSalil Mehta 13116a5f6fa3SHuazhong Tan ret = client->ops->reset_notify(handle, type); 13126a5f6fa3SHuazhong Tan if (ret) 13136a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 13146a5f6fa3SHuazhong Tan type, ret); 13156a5f6fa3SHuazhong Tan 13166a5f6fa3SHuazhong Tan return ret; 13176988eb2aSSalil Mehta } 13186988eb2aSSalil Mehta 13196ff3cf07SHuazhong Tan static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 13206ff3cf07SHuazhong Tan { 13216ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 13226ff3cf07SHuazhong Tan 13236ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DONE, &hdev->flr_state); 13246ff3cf07SHuazhong Tan } 13256ff3cf07SHuazhong Tan 13266ff3cf07SHuazhong Tan static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev, 13276ff3cf07SHuazhong Tan unsigned long delay_us, 13286ff3cf07SHuazhong Tan unsigned long wait_cnt) 13296ff3cf07SHuazhong Tan { 13306ff3cf07SHuazhong Tan unsigned long cnt = 0; 13316ff3cf07SHuazhong Tan 13326ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) && 13336ff3cf07SHuazhong Tan cnt++ < wait_cnt) 13346ff3cf07SHuazhong Tan usleep_range(delay_us, delay_us * 2); 13356ff3cf07SHuazhong Tan 13366ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) { 13376ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 13386ff3cf07SHuazhong Tan "flr wait timeout\n"); 13396ff3cf07SHuazhong Tan return -ETIMEDOUT; 13406ff3cf07SHuazhong Tan } 13416ff3cf07SHuazhong Tan 13426ff3cf07SHuazhong Tan return 0; 13436ff3cf07SHuazhong Tan } 13446ff3cf07SHuazhong Tan 13456988eb2aSSalil Mehta static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 13466988eb2aSSalil Mehta { 1347aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_US 20000 1348aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_CNT 2000 1349aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1350aa5c4f17SHuazhong Tan (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1351aa5c4f17SHuazhong Tan 1352aa5c4f17SHuazhong Tan u32 val; 1353aa5c4f17SHuazhong Tan int ret; 13546988eb2aSSalil Mehta 13556988eb2aSSalil Mehta /* wait to check the hardware reset completion status */ 1356aa5c4f17SHuazhong Tan val = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1357aa5c4f17SHuazhong Tan dev_info(&hdev->pdev->dev, "checking vf resetting status: %x\n", val); 1358aa5c4f17SHuazhong Tan 13596ff3cf07SHuazhong Tan if (hdev->reset_type == HNAE3_FLR_RESET) 13606ff3cf07SHuazhong Tan return hclgevf_flr_poll_timeout(hdev, 13616ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_US, 13626ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_CNT); 13636ff3cf07SHuazhong Tan 1364aa5c4f17SHuazhong Tan ret = readl_poll_timeout(hdev->hw.io_base + HCLGEVF_RST_ING, val, 1365aa5c4f17SHuazhong Tan !(val & HCLGEVF_RST_ING_BITS), 1366aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_US, 1367aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 13686988eb2aSSalil Mehta 13696988eb2aSSalil Mehta /* hardware completion status should be available by this time */ 1370aa5c4f17SHuazhong Tan if (ret) { 1371aa5c4f17SHuazhong Tan dev_err(&hdev->pdev->dev, 13726988eb2aSSalil Mehta "could'nt get reset done status from h/w, timeout!\n"); 1373aa5c4f17SHuazhong Tan return ret; 13746988eb2aSSalil Mehta } 13756988eb2aSSalil Mehta 13766988eb2aSSalil Mehta /* we will wait a bit more to let reset of the stack to complete. This 13776988eb2aSSalil Mehta * might happen in case reset assertion was made by PF. Yes, this also 13786988eb2aSSalil Mehta * means we might end up waiting bit more even for VF reset. 13796988eb2aSSalil Mehta */ 13806988eb2aSSalil Mehta msleep(5000); 13816988eb2aSSalil Mehta 13826988eb2aSSalil Mehta return 0; 13836988eb2aSSalil Mehta } 13846988eb2aSSalil Mehta 13856988eb2aSSalil Mehta static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 13866988eb2aSSalil Mehta { 13877a01c897SSalil Mehta int ret; 13887a01c897SSalil Mehta 13896988eb2aSSalil Mehta /* uninitialize the nic client */ 13906a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 13916a5f6fa3SHuazhong Tan if (ret) 13926a5f6fa3SHuazhong Tan return ret; 13936988eb2aSSalil Mehta 13947a01c897SSalil Mehta /* re-initialize the hclge device */ 13959c6f7085SHuazhong Tan ret = hclgevf_reset_hdev(hdev); 13967a01c897SSalil Mehta if (ret) { 13977a01c897SSalil Mehta dev_err(&hdev->pdev->dev, 13987a01c897SSalil Mehta "hclge device re-init failed, VF is disabled!\n"); 13997a01c897SSalil Mehta return ret; 14007a01c897SSalil Mehta } 14016988eb2aSSalil Mehta 14026988eb2aSSalil Mehta /* bring up the nic client again */ 14036a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 14046a5f6fa3SHuazhong Tan if (ret) 14056a5f6fa3SHuazhong Tan return ret; 14066988eb2aSSalil Mehta 14071f609492SYunsheng Lin return hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT); 14086988eb2aSSalil Mehta } 14096988eb2aSSalil Mehta 1410dea846e8SHuazhong Tan static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1411dea846e8SHuazhong Tan { 1412dea846e8SHuazhong Tan int ret = 0; 1413dea846e8SHuazhong Tan 1414dea846e8SHuazhong Tan switch (hdev->reset_type) { 1415dea846e8SHuazhong Tan case HNAE3_VF_FUNC_RESET: 1416dea846e8SHuazhong Tan ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1417dea846e8SHuazhong Tan 0, true, NULL, sizeof(u8)); 1418dea846e8SHuazhong Tan break; 14196ff3cf07SHuazhong Tan case HNAE3_FLR_RESET: 14206ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 14216ff3cf07SHuazhong Tan break; 1422dea846e8SHuazhong Tan default: 1423dea846e8SHuazhong Tan break; 1424dea846e8SHuazhong Tan } 1425dea846e8SHuazhong Tan 1426ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1427ef5f8e50SHuazhong Tan 1428dea846e8SHuazhong Tan dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1429dea846e8SHuazhong Tan hdev->reset_type, ret); 1430dea846e8SHuazhong Tan 1431dea846e8SHuazhong Tan return ret; 1432dea846e8SHuazhong Tan } 1433dea846e8SHuazhong Tan 14346988eb2aSSalil Mehta static int hclgevf_reset(struct hclgevf_dev *hdev) 14356988eb2aSSalil Mehta { 1436dea846e8SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 14376988eb2aSSalil Mehta int ret; 14386988eb2aSSalil Mehta 1439dea846e8SHuazhong Tan /* Initialize ae_dev reset status as well, in case enet layer wants to 1440dea846e8SHuazhong Tan * know if device is undergoing reset 1441dea846e8SHuazhong Tan */ 1442dea846e8SHuazhong Tan ae_dev->reset_type = hdev->reset_type; 14434d60291bSHuazhong Tan hdev->reset_count++; 14446988eb2aSSalil Mehta rtnl_lock(); 14456988eb2aSSalil Mehta 14466988eb2aSSalil Mehta /* bring down the nic to stop any ongoing TX/RX */ 14476a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 14486a5f6fa3SHuazhong Tan if (ret) 14496a5f6fa3SHuazhong Tan goto err_reset_lock; 14506988eb2aSSalil Mehta 145129118ab9SHuazhong Tan rtnl_unlock(); 145229118ab9SHuazhong Tan 14536a5f6fa3SHuazhong Tan ret = hclgevf_reset_prepare_wait(hdev); 14546a5f6fa3SHuazhong Tan if (ret) 14556a5f6fa3SHuazhong Tan goto err_reset; 1456dea846e8SHuazhong Tan 14576988eb2aSSalil Mehta /* check if VF could successfully fetch the hardware reset completion 14586988eb2aSSalil Mehta * status from the hardware 14596988eb2aSSalil Mehta */ 14606988eb2aSSalil Mehta ret = hclgevf_reset_wait(hdev); 14616988eb2aSSalil Mehta if (ret) { 14626988eb2aSSalil Mehta /* can't do much in this situation, will disable VF */ 14636988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, 14646988eb2aSSalil Mehta "VF failed(=%d) to fetch H/W reset completion status\n", 14656988eb2aSSalil Mehta ret); 14666a5f6fa3SHuazhong Tan goto err_reset; 14676988eb2aSSalil Mehta } 14686988eb2aSSalil Mehta 146929118ab9SHuazhong Tan rtnl_lock(); 147029118ab9SHuazhong Tan 14716988eb2aSSalil Mehta /* now, re-initialize the nic client and ae device*/ 14726988eb2aSSalil Mehta ret = hclgevf_reset_stack(hdev); 14736a5f6fa3SHuazhong Tan if (ret) { 14746988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 14756a5f6fa3SHuazhong Tan goto err_reset_lock; 14766a5f6fa3SHuazhong Tan } 14776988eb2aSSalil Mehta 14786988eb2aSSalil Mehta /* bring up the nic to enable TX/RX again */ 14796a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 14806a5f6fa3SHuazhong Tan if (ret) 14816a5f6fa3SHuazhong Tan goto err_reset_lock; 14826988eb2aSSalil Mehta 14836988eb2aSSalil Mehta rtnl_unlock(); 14846988eb2aSSalil Mehta 1485b644a8d4SHuazhong Tan hdev->last_reset_time = jiffies; 1486b644a8d4SHuazhong Tan ae_dev->reset_type = HNAE3_NONE_RESET; 1487b644a8d4SHuazhong Tan 14886988eb2aSSalil Mehta return ret; 14896a5f6fa3SHuazhong Tan err_reset_lock: 14906a5f6fa3SHuazhong Tan rtnl_unlock(); 14916a5f6fa3SHuazhong Tan err_reset: 14926a5f6fa3SHuazhong Tan /* When VF reset failed, only the higher level reset asserted by PF 14936a5f6fa3SHuazhong Tan * can restore it, so re-initialize the command queue to receive 14946a5f6fa3SHuazhong Tan * this higher reset event. 14956a5f6fa3SHuazhong Tan */ 14966a5f6fa3SHuazhong Tan hclgevf_cmd_init(hdev); 14976a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "failed to reset VF\n"); 1498cf1f2129SHuazhong Tan if (hclgevf_is_reset_pending(hdev)) 1499cf1f2129SHuazhong Tan hclgevf_reset_task_schedule(hdev); 15006a5f6fa3SHuazhong Tan 15016a5f6fa3SHuazhong Tan return ret; 15026988eb2aSSalil Mehta } 15036988eb2aSSalil Mehta 1504720bd583SHuazhong Tan static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1505720bd583SHuazhong Tan unsigned long *addr) 1506720bd583SHuazhong Tan { 1507720bd583SHuazhong Tan enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1508720bd583SHuazhong Tan 1509dea846e8SHuazhong Tan /* return the highest priority reset level amongst all */ 1510b90fcc5bSHuazhong Tan if (test_bit(HNAE3_VF_RESET, addr)) { 1511b90fcc5bSHuazhong Tan rst_level = HNAE3_VF_RESET; 1512b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_RESET, addr); 1513b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1514b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1515b90fcc5bSHuazhong Tan } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1516dea846e8SHuazhong Tan rst_level = HNAE3_VF_FULL_RESET; 1517dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FULL_RESET, addr); 1518dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1519aa5c4f17SHuazhong Tan } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1520aa5c4f17SHuazhong Tan rst_level = HNAE3_VF_PF_FUNC_RESET; 1521aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1522aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1523dea846e8SHuazhong Tan } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1524dea846e8SHuazhong Tan rst_level = HNAE3_VF_FUNC_RESET; 1525dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 15266ff3cf07SHuazhong Tan } else if (test_bit(HNAE3_FLR_RESET, addr)) { 15276ff3cf07SHuazhong Tan rst_level = HNAE3_FLR_RESET; 15286ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_RESET, addr); 1529720bd583SHuazhong Tan } 1530720bd583SHuazhong Tan 1531720bd583SHuazhong Tan return rst_level; 1532720bd583SHuazhong Tan } 1533720bd583SHuazhong Tan 15346ae4e733SShiju Jose static void hclgevf_reset_event(struct pci_dev *pdev, 15356ae4e733SShiju Jose struct hnae3_handle *handle) 15366d4c3981SSalil Mehta { 15376ff3cf07SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 15386ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 15396d4c3981SSalil Mehta 15406d4c3981SSalil Mehta dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 15416d4c3981SSalil Mehta 15426ff3cf07SHuazhong Tan if (hdev->default_reset_request) 15430742ed7cSHuazhong Tan hdev->reset_level = 1544720bd583SHuazhong Tan hclgevf_get_reset_level(hdev, 1545720bd583SHuazhong Tan &hdev->default_reset_request); 1546720bd583SHuazhong Tan else 1547dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 15486d4c3981SSalil Mehta 1549436667d2SSalil Mehta /* reset of this VF requested */ 1550436667d2SSalil Mehta set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1551436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 15526d4c3981SSalil Mehta 15530742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 15546d4c3981SSalil Mehta } 15556d4c3981SSalil Mehta 1556720bd583SHuazhong Tan static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1557720bd583SHuazhong Tan enum hnae3_reset_type rst_type) 1558720bd583SHuazhong Tan { 1559720bd583SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1560720bd583SHuazhong Tan 1561720bd583SHuazhong Tan set_bit(rst_type, &hdev->default_reset_request); 1562720bd583SHuazhong Tan } 1563720bd583SHuazhong Tan 15646ff3cf07SHuazhong Tan static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 15656ff3cf07SHuazhong Tan { 15666ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_MS 100 15676ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_CNT 50 15686ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 15696ff3cf07SHuazhong Tan int cnt = 0; 15706ff3cf07SHuazhong Tan 15716ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 15726ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DONE, &hdev->flr_state); 15736ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request); 15746ff3cf07SHuazhong Tan hclgevf_reset_event(hdev->pdev, NULL); 15756ff3cf07SHuazhong Tan 15766ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) && 15776ff3cf07SHuazhong Tan cnt++ < HCLGEVF_FLR_WAIT_CNT) 15786ff3cf07SHuazhong Tan msleep(HCLGEVF_FLR_WAIT_MS); 15796ff3cf07SHuazhong Tan 15806ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state)) 15816ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 15826ff3cf07SHuazhong Tan "flr wait down timeout: %d\n", cnt); 15836ff3cf07SHuazhong Tan } 15846ff3cf07SHuazhong Tan 1585e2cb1decSSalil Mehta static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1586e2cb1decSSalil Mehta { 1587e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1588e2cb1decSSalil Mehta 1589e2cb1decSSalil Mehta return hdev->fw_version; 1590e2cb1decSSalil Mehta } 1591e2cb1decSSalil Mehta 1592e2cb1decSSalil Mehta static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1593e2cb1decSSalil Mehta { 1594e2cb1decSSalil Mehta struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1595e2cb1decSSalil Mehta 1596e2cb1decSSalil Mehta vector->vector_irq = pci_irq_vector(hdev->pdev, 1597e2cb1decSSalil Mehta HCLGEVF_MISC_VECTOR_NUM); 1598e2cb1decSSalil Mehta vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1599e2cb1decSSalil Mehta /* vector status always valid for Vector 0 */ 1600e2cb1decSSalil Mehta hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1601e2cb1decSSalil Mehta hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1602e2cb1decSSalil Mehta 1603e2cb1decSSalil Mehta hdev->num_msi_left -= 1; 1604e2cb1decSSalil Mehta hdev->num_msi_used += 1; 1605e2cb1decSSalil Mehta } 1606e2cb1decSSalil Mehta 160735a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 160835a1e503SSalil Mehta { 16097d600706SHuazhong Tan if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state)) { 161035a1e503SSalil Mehta set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 161135a1e503SSalil Mehta schedule_work(&hdev->rst_service_task); 161235a1e503SSalil Mehta } 161335a1e503SSalil Mehta } 161435a1e503SSalil Mehta 161507a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1616e2cb1decSSalil Mehta { 161707a0556aSSalil Mehta if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) && 161807a0556aSSalil Mehta !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) { 161907a0556aSSalil Mehta set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1620e2cb1decSSalil Mehta schedule_work(&hdev->mbx_service_task); 1621e2cb1decSSalil Mehta } 162207a0556aSSalil Mehta } 1623e2cb1decSSalil Mehta 1624e2cb1decSSalil Mehta static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 1625e2cb1decSSalil Mehta { 1626e2cb1decSSalil Mehta if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 1627e2cb1decSSalil Mehta !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 1628e2cb1decSSalil Mehta schedule_work(&hdev->service_task); 1629e2cb1decSSalil Mehta } 1630e2cb1decSSalil Mehta 1631436667d2SSalil Mehta static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev) 1632436667d2SSalil Mehta { 163307a0556aSSalil Mehta /* if we have any pending mailbox event then schedule the mbx task */ 163407a0556aSSalil Mehta if (hdev->mbx_event_pending) 163507a0556aSSalil Mehta hclgevf_mbx_task_schedule(hdev); 163607a0556aSSalil Mehta 1637436667d2SSalil Mehta if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state)) 1638436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 1639436667d2SSalil Mehta } 1640436667d2SSalil Mehta 1641e2cb1decSSalil Mehta static void hclgevf_service_timer(struct timer_list *t) 1642e2cb1decSSalil Mehta { 1643e2cb1decSSalil Mehta struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 1644e2cb1decSSalil Mehta 1645e2cb1decSSalil Mehta mod_timer(&hdev->service_timer, jiffies + 5 * HZ); 1646e2cb1decSSalil Mehta 1647e2cb1decSSalil Mehta hclgevf_task_schedule(hdev); 1648e2cb1decSSalil Mehta } 1649e2cb1decSSalil Mehta 165035a1e503SSalil Mehta static void hclgevf_reset_service_task(struct work_struct *work) 165135a1e503SSalil Mehta { 165235a1e503SSalil Mehta struct hclgevf_dev *hdev = 165335a1e503SSalil Mehta container_of(work, struct hclgevf_dev, rst_service_task); 1654a8dedb65SSalil Mehta int ret; 165535a1e503SSalil Mehta 165635a1e503SSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 165735a1e503SSalil Mehta return; 165835a1e503SSalil Mehta 165935a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 166035a1e503SSalil Mehta 1661436667d2SSalil Mehta if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1662436667d2SSalil Mehta &hdev->reset_state)) { 1663436667d2SSalil Mehta /* PF has initmated that it is about to reset the hardware. 1664436667d2SSalil Mehta * We now have to poll & check if harware has actually completed 1665436667d2SSalil Mehta * the reset sequence. On hardware reset completion, VF needs to 1666436667d2SSalil Mehta * reset the client and ae device. 166735a1e503SSalil Mehta */ 1668436667d2SSalil Mehta hdev->reset_attempts = 0; 1669436667d2SSalil Mehta 1670dea846e8SHuazhong Tan hdev->last_reset_time = jiffies; 1671dea846e8SHuazhong Tan while ((hdev->reset_type = 1672dea846e8SHuazhong Tan hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 1673dea846e8SHuazhong Tan != HNAE3_NONE_RESET) { 16746988eb2aSSalil Mehta ret = hclgevf_reset(hdev); 16756988eb2aSSalil Mehta if (ret) 1676dea846e8SHuazhong Tan dev_err(&hdev->pdev->dev, 1677dea846e8SHuazhong Tan "VF stack reset failed %d.\n", ret); 1678dea846e8SHuazhong Tan } 1679436667d2SSalil Mehta } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1680436667d2SSalil Mehta &hdev->reset_state)) { 1681436667d2SSalil Mehta /* we could be here when either of below happens: 1682436667d2SSalil Mehta * 1. reset was initiated due to watchdog timeout due to 1683436667d2SSalil Mehta * a. IMP was earlier reset and our TX got choked down and 1684436667d2SSalil Mehta * which resulted in watchdog reacting and inducing VF 1685436667d2SSalil Mehta * reset. This also means our cmdq would be unreliable. 1686436667d2SSalil Mehta * b. problem in TX due to other lower layer(example link 1687436667d2SSalil Mehta * layer not functioning properly etc.) 1688436667d2SSalil Mehta * 2. VF reset might have been initiated due to some config 1689436667d2SSalil Mehta * change. 1690436667d2SSalil Mehta * 1691436667d2SSalil Mehta * NOTE: Theres no clear way to detect above cases than to react 1692436667d2SSalil Mehta * to the response of PF for this reset request. PF will ack the 1693436667d2SSalil Mehta * 1b and 2. cases but we will not get any intimation about 1a 1694436667d2SSalil Mehta * from PF as cmdq would be in unreliable state i.e. mailbox 1695436667d2SSalil Mehta * communication between PF and VF would be broken. 1696436667d2SSalil Mehta */ 1697436667d2SSalil Mehta 1698436667d2SSalil Mehta /* if we are never geting into pending state it means either: 1699436667d2SSalil Mehta * 1. PF is not receiving our request which could be due to IMP 1700436667d2SSalil Mehta * reset 1701436667d2SSalil Mehta * 2. PF is screwed 1702436667d2SSalil Mehta * We cannot do much for 2. but to check first we can try reset 1703436667d2SSalil Mehta * our PCIe + stack and see if it alleviates the problem. 1704436667d2SSalil Mehta */ 1705436667d2SSalil Mehta if (hdev->reset_attempts > 3) { 1706436667d2SSalil Mehta /* prepare for full reset of stack + pcie interface */ 1707dea846e8SHuazhong Tan set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1708436667d2SSalil Mehta 1709436667d2SSalil Mehta /* "defer" schedule the reset task again */ 1710436667d2SSalil Mehta set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1711436667d2SSalil Mehta } else { 1712436667d2SSalil Mehta hdev->reset_attempts++; 1713436667d2SSalil Mehta 1714dea846e8SHuazhong Tan set_bit(hdev->reset_level, &hdev->reset_pending); 1715dea846e8SHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1716436667d2SSalil Mehta } 1717dea846e8SHuazhong Tan hclgevf_reset_task_schedule(hdev); 1718436667d2SSalil Mehta } 171935a1e503SSalil Mehta 172035a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 172135a1e503SSalil Mehta } 172235a1e503SSalil Mehta 1723e2cb1decSSalil Mehta static void hclgevf_mailbox_service_task(struct work_struct *work) 1724e2cb1decSSalil Mehta { 1725e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1726e2cb1decSSalil Mehta 1727e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 1728e2cb1decSSalil Mehta 1729e2cb1decSSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1730e2cb1decSSalil Mehta return; 1731e2cb1decSSalil Mehta 1732e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1733e2cb1decSSalil Mehta 173407a0556aSSalil Mehta hclgevf_mbx_async_handler(hdev); 1735e2cb1decSSalil Mehta 1736e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1737e2cb1decSSalil Mehta } 1738e2cb1decSSalil Mehta 1739a6d818e3SYunsheng Lin static void hclgevf_keep_alive_timer(struct timer_list *t) 1740a6d818e3SYunsheng Lin { 1741a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = from_timer(hdev, t, keep_alive_timer); 1742a6d818e3SYunsheng Lin 1743a6d818e3SYunsheng Lin schedule_work(&hdev->keep_alive_task); 1744a6d818e3SYunsheng Lin mod_timer(&hdev->keep_alive_timer, jiffies + 2 * HZ); 1745a6d818e3SYunsheng Lin } 1746a6d818e3SYunsheng Lin 1747a6d818e3SYunsheng Lin static void hclgevf_keep_alive_task(struct work_struct *work) 1748a6d818e3SYunsheng Lin { 1749a6d818e3SYunsheng Lin struct hclgevf_dev *hdev; 1750a6d818e3SYunsheng Lin u8 respmsg; 1751a6d818e3SYunsheng Lin int ret; 1752a6d818e3SYunsheng Lin 1753a6d818e3SYunsheng Lin hdev = container_of(work, struct hclgevf_dev, keep_alive_task); 1754c59a85c0SJian Shen 1755c59a85c0SJian Shen if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1756c59a85c0SJian Shen return; 1757c59a85c0SJian Shen 1758a6d818e3SYunsheng Lin ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL, 1759a6d818e3SYunsheng Lin 0, false, &respmsg, sizeof(u8)); 1760a6d818e3SYunsheng Lin if (ret) 1761a6d818e3SYunsheng Lin dev_err(&hdev->pdev->dev, 1762a6d818e3SYunsheng Lin "VF sends keep alive cmd failed(=%d)\n", ret); 1763a6d818e3SYunsheng Lin } 1764a6d818e3SYunsheng Lin 1765e2cb1decSSalil Mehta static void hclgevf_service_task(struct work_struct *work) 1766e2cb1decSSalil Mehta { 1767e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1768e2cb1decSSalil Mehta 1769e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, service_task); 1770e2cb1decSSalil Mehta 1771e2cb1decSSalil Mehta /* request the link status from the PF. PF would be able to tell VF 1772e2cb1decSSalil Mehta * about such updates in future so we might remove this later 1773e2cb1decSSalil Mehta */ 1774e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1775e2cb1decSSalil Mehta 17769194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 17779194d18bSliuzhongzhu 1778436667d2SSalil Mehta hclgevf_deferred_task_schedule(hdev); 1779436667d2SSalil Mehta 1780e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1781e2cb1decSSalil Mehta } 1782e2cb1decSSalil Mehta 1783e2cb1decSSalil Mehta static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1784e2cb1decSSalil Mehta { 1785e2cb1decSSalil Mehta hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1786e2cb1decSSalil Mehta } 1787e2cb1decSSalil Mehta 1788b90fcc5bSHuazhong Tan static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1789b90fcc5bSHuazhong Tan u32 *clearval) 1790e2cb1decSSalil Mehta { 1791b90fcc5bSHuazhong Tan u32 cmdq_src_reg, rst_ing_reg; 1792e2cb1decSSalil Mehta 1793e2cb1decSSalil Mehta /* fetch the events from their corresponding regs */ 1794e2cb1decSSalil Mehta cmdq_src_reg = hclgevf_read_dev(&hdev->hw, 1795e2cb1decSSalil Mehta HCLGEVF_VECTOR0_CMDQ_SRC_REG); 1796e2cb1decSSalil Mehta 1797b90fcc5bSHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_src_reg) { 1798b90fcc5bSHuazhong Tan rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1799b90fcc5bSHuazhong Tan dev_info(&hdev->pdev->dev, 1800b90fcc5bSHuazhong Tan "receive reset interrupt 0x%x!\n", rst_ing_reg); 1801b90fcc5bSHuazhong Tan set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1802b90fcc5bSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1803ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1804b90fcc5bSHuazhong Tan cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RST_INT_B); 1805b90fcc5bSHuazhong Tan *clearval = cmdq_src_reg; 1806b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_RST; 1807b90fcc5bSHuazhong Tan } 1808b90fcc5bSHuazhong Tan 1809e2cb1decSSalil Mehta /* check for vector0 mailbox(=CMDQ RX) event source */ 1810e2cb1decSSalil Mehta if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 1811e2cb1decSSalil Mehta cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1812e2cb1decSSalil Mehta *clearval = cmdq_src_reg; 1813b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_MBX; 1814e2cb1decSSalil Mehta } 1815e2cb1decSSalil Mehta 1816e2cb1decSSalil Mehta dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 1817e2cb1decSSalil Mehta 1818b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_OTHER; 1819e2cb1decSSalil Mehta } 1820e2cb1decSSalil Mehta 1821e2cb1decSSalil Mehta static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1822e2cb1decSSalil Mehta { 1823e2cb1decSSalil Mehta writel(en ? 1 : 0, vector->addr); 1824e2cb1decSSalil Mehta } 1825e2cb1decSSalil Mehta 1826e2cb1decSSalil Mehta static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1827e2cb1decSSalil Mehta { 1828b90fcc5bSHuazhong Tan enum hclgevf_evt_cause event_cause; 1829e2cb1decSSalil Mehta struct hclgevf_dev *hdev = data; 1830e2cb1decSSalil Mehta u32 clearval; 1831e2cb1decSSalil Mehta 1832e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 1833b90fcc5bSHuazhong Tan event_cause = hclgevf_check_evt_cause(hdev, &clearval); 1834e2cb1decSSalil Mehta 1835b90fcc5bSHuazhong Tan switch (event_cause) { 1836b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_RST: 1837b90fcc5bSHuazhong Tan hclgevf_reset_task_schedule(hdev); 1838b90fcc5bSHuazhong Tan break; 1839b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_MBX: 184007a0556aSSalil Mehta hclgevf_mbx_handler(hdev); 1841b90fcc5bSHuazhong Tan break; 1842b90fcc5bSHuazhong Tan default: 1843b90fcc5bSHuazhong Tan break; 1844b90fcc5bSHuazhong Tan } 1845e2cb1decSSalil Mehta 1846b90fcc5bSHuazhong Tan if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 1847e2cb1decSSalil Mehta hclgevf_clear_event_cause(hdev, clearval); 1848e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 1849b90fcc5bSHuazhong Tan } 1850e2cb1decSSalil Mehta 1851e2cb1decSSalil Mehta return IRQ_HANDLED; 1852e2cb1decSSalil Mehta } 1853e2cb1decSSalil Mehta 1854e2cb1decSSalil Mehta static int hclgevf_configure(struct hclgevf_dev *hdev) 1855e2cb1decSSalil Mehta { 1856e2cb1decSSalil Mehta int ret; 1857e2cb1decSSalil Mehta 185892f11ea1SJian Shen /* get current port based vlan state from PF */ 185992f11ea1SJian Shen ret = hclgevf_get_port_base_vlan_filter_state(hdev); 186092f11ea1SJian Shen if (ret) 186192f11ea1SJian Shen return ret; 186292f11ea1SJian Shen 1863e2cb1decSSalil Mehta /* get queue configuration from PF */ 18646cee6fc3SJian Shen ret = hclgevf_get_queue_info(hdev); 1865e2cb1decSSalil Mehta if (ret) 1866e2cb1decSSalil Mehta return ret; 1867c0425944SPeng Li 1868c0425944SPeng Li /* get queue depth info from PF */ 1869c0425944SPeng Li ret = hclgevf_get_queue_depth(hdev); 1870c0425944SPeng Li if (ret) 1871c0425944SPeng Li return ret; 1872c0425944SPeng Li 18739c3e7130Sliuzhongzhu ret = hclgevf_get_pf_media_type(hdev); 18749c3e7130Sliuzhongzhu if (ret) 18759c3e7130Sliuzhongzhu return ret; 18769c3e7130Sliuzhongzhu 1877e2cb1decSSalil Mehta /* get tc configuration from PF */ 1878e2cb1decSSalil Mehta return hclgevf_get_tc_info(hdev); 1879e2cb1decSSalil Mehta } 1880e2cb1decSSalil Mehta 18817a01c897SSalil Mehta static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 18827a01c897SSalil Mehta { 18837a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 18841154bb26SPeng Li struct hclgevf_dev *hdev; 18857a01c897SSalil Mehta 18867a01c897SSalil Mehta hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 18877a01c897SSalil Mehta if (!hdev) 18887a01c897SSalil Mehta return -ENOMEM; 18897a01c897SSalil Mehta 18907a01c897SSalil Mehta hdev->pdev = pdev; 18917a01c897SSalil Mehta hdev->ae_dev = ae_dev; 18927a01c897SSalil Mehta ae_dev->priv = hdev; 18937a01c897SSalil Mehta 18947a01c897SSalil Mehta return 0; 18957a01c897SSalil Mehta } 18967a01c897SSalil Mehta 1897e2cb1decSSalil Mehta static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 1898e2cb1decSSalil Mehta { 1899e2cb1decSSalil Mehta struct hnae3_handle *roce = &hdev->roce; 1900e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 1901e2cb1decSSalil Mehta 190207acf909SJian Shen roce->rinfo.num_vectors = hdev->num_roce_msix; 1903e2cb1decSSalil Mehta 1904e2cb1decSSalil Mehta if (hdev->num_msi_left < roce->rinfo.num_vectors || 1905e2cb1decSSalil Mehta hdev->num_msi_left == 0) 1906e2cb1decSSalil Mehta return -EINVAL; 1907e2cb1decSSalil Mehta 190807acf909SJian Shen roce->rinfo.base_vector = hdev->roce_base_vector; 1909e2cb1decSSalil Mehta 1910e2cb1decSSalil Mehta roce->rinfo.netdev = nic->kinfo.netdev; 1911e2cb1decSSalil Mehta roce->rinfo.roce_io_base = hdev->hw.io_base; 1912e2cb1decSSalil Mehta 1913e2cb1decSSalil Mehta roce->pdev = nic->pdev; 1914e2cb1decSSalil Mehta roce->ae_algo = nic->ae_algo; 1915e2cb1decSSalil Mehta roce->numa_node_mask = nic->numa_node_mask; 1916e2cb1decSSalil Mehta 1917e2cb1decSSalil Mehta return 0; 1918e2cb1decSSalil Mehta } 1919e2cb1decSSalil Mehta 1920b26a6feaSPeng Li static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 1921b26a6feaSPeng Li { 1922b26a6feaSPeng Li struct hclgevf_cfg_gro_status_cmd *req; 1923b26a6feaSPeng Li struct hclgevf_desc desc; 1924b26a6feaSPeng Li int ret; 1925b26a6feaSPeng Li 1926b26a6feaSPeng Li if (!hnae3_dev_gro_supported(hdev)) 1927b26a6feaSPeng Li return 0; 1928b26a6feaSPeng Li 1929b26a6feaSPeng Li hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 1930b26a6feaSPeng Li false); 1931b26a6feaSPeng Li req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 1932b26a6feaSPeng Li 1933b26a6feaSPeng Li req->gro_en = cpu_to_le16(en ? 1 : 0); 1934b26a6feaSPeng Li 1935b26a6feaSPeng Li ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1936b26a6feaSPeng Li if (ret) 1937b26a6feaSPeng Li dev_err(&hdev->pdev->dev, 1938b26a6feaSPeng Li "VF GRO hardware config cmd failed, ret = %d.\n", ret); 1939b26a6feaSPeng Li 1940b26a6feaSPeng Li return ret; 1941b26a6feaSPeng Li } 1942b26a6feaSPeng Li 1943e2cb1decSSalil Mehta static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 1944e2cb1decSSalil Mehta { 1945e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1946e2cb1decSSalil Mehta int i, ret; 1947e2cb1decSSalil Mehta 1948e2cb1decSSalil Mehta rss_cfg->rss_size = hdev->rss_size_max; 1949e2cb1decSSalil Mehta 1950374ad291SJian Shen if (hdev->pdev->revision >= 0x21) { 1951472d7eceSJian Shen rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 1952472d7eceSJian Shen memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 1953374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 1954374ad291SJian Shen 1955374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 1956374ad291SJian Shen rss_cfg->rss_hash_key); 1957374ad291SJian Shen if (ret) 1958374ad291SJian Shen return ret; 1959d97b3072SJian Shen 1960d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = 1961d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1962d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = 1963d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1964d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = 1965d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1966d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = 1967d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1968d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = 1969d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1970d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = 1971d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1972d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = 1973d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1974d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = 1975d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1976d97b3072SJian Shen 1977d97b3072SJian Shen ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 1978d97b3072SJian Shen if (ret) 1979d97b3072SJian Shen return ret; 1980d97b3072SJian Shen 1981374ad291SJian Shen } 1982374ad291SJian Shen 1983e2cb1decSSalil Mehta /* Initialize RSS indirect table for each vport */ 1984e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 1985e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max; 1986e2cb1decSSalil Mehta 1987e2cb1decSSalil Mehta ret = hclgevf_set_rss_indir_table(hdev); 1988e2cb1decSSalil Mehta if (ret) 1989e2cb1decSSalil Mehta return ret; 1990e2cb1decSSalil Mehta 1991e2cb1decSSalil Mehta return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max); 1992e2cb1decSSalil Mehta } 1993e2cb1decSSalil Mehta 1994e2cb1decSSalil Mehta static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 1995e2cb1decSSalil Mehta { 1996e2cb1decSSalil Mehta /* other vlan config(like, VLAN TX/RX offload) would also be added 1997e2cb1decSSalil Mehta * here later 1998e2cb1decSSalil Mehta */ 1999e2cb1decSSalil Mehta return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2000e2cb1decSSalil Mehta false); 2001e2cb1decSSalil Mehta } 2002e2cb1decSSalil Mehta 20038cdb992fSJian Shen static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 20048cdb992fSJian Shen { 20058cdb992fSJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 20068cdb992fSJian Shen 20078cdb992fSJian Shen if (enable) { 20088cdb992fSJian Shen mod_timer(&hdev->service_timer, jiffies + HZ); 20098cdb992fSJian Shen } else { 20108cdb992fSJian Shen del_timer_sync(&hdev->service_timer); 20118cdb992fSJian Shen cancel_work_sync(&hdev->service_task); 20128cdb992fSJian Shen clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 20138cdb992fSJian Shen } 20148cdb992fSJian Shen } 20158cdb992fSJian Shen 2016e2cb1decSSalil Mehta static int hclgevf_ae_start(struct hnae3_handle *handle) 2017e2cb1decSSalil Mehta { 2018e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2019e2cb1decSSalil Mehta 2020e2cb1decSSalil Mehta /* reset tqp stats */ 2021e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 2022e2cb1decSSalil Mehta 2023e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 2024e2cb1decSSalil Mehta 20259194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 20269194d18bSliuzhongzhu 2027e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2028e2cb1decSSalil Mehta 2029e2cb1decSSalil Mehta return 0; 2030e2cb1decSSalil Mehta } 2031e2cb1decSSalil Mehta 2032e2cb1decSSalil Mehta static void hclgevf_ae_stop(struct hnae3_handle *handle) 2033e2cb1decSSalil Mehta { 2034e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 203539cfbc9cSHuazhong Tan int i; 2036e2cb1decSSalil Mehta 20372f7e4896SFuyun Liang set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 20382f7e4896SFuyun Liang 203939cfbc9cSHuazhong Tan for (i = 0; i < handle->kinfo.num_tqps; i++) 204039cfbc9cSHuazhong Tan hclgevf_reset_tqp(handle, i); 204139cfbc9cSHuazhong Tan 2042e2cb1decSSalil Mehta /* reset tqp stats */ 2043e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 20448cc6c1f7SFuyun Liang hclgevf_update_link_status(hdev, 0); 2045e2cb1decSSalil Mehta } 2046e2cb1decSSalil Mehta 2047a6d818e3SYunsheng Lin static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2048a6d818e3SYunsheng Lin { 2049a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2050a6d818e3SYunsheng Lin u8 msg_data; 2051a6d818e3SYunsheng Lin 2052a6d818e3SYunsheng Lin msg_data = alive ? 1 : 0; 2053a6d818e3SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE, 2054a6d818e3SYunsheng Lin 0, &msg_data, 1, false, NULL, 0); 2055a6d818e3SYunsheng Lin } 2056a6d818e3SYunsheng Lin 2057a6d818e3SYunsheng Lin static int hclgevf_client_start(struct hnae3_handle *handle) 2058a6d818e3SYunsheng Lin { 2059a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2060e233516eSHuazhong Tan int ret; 2061e233516eSHuazhong Tan 2062e233516eSHuazhong Tan ret = hclgevf_set_alive(handle, true); 2063e233516eSHuazhong Tan if (ret) 2064e233516eSHuazhong Tan return ret; 2065a6d818e3SYunsheng Lin 2066a6d818e3SYunsheng Lin mod_timer(&hdev->keep_alive_timer, jiffies + 2 * HZ); 2067e233516eSHuazhong Tan 2068e233516eSHuazhong Tan return 0; 2069a6d818e3SYunsheng Lin } 2070a6d818e3SYunsheng Lin 2071a6d818e3SYunsheng Lin static void hclgevf_client_stop(struct hnae3_handle *handle) 2072a6d818e3SYunsheng Lin { 2073a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2074a6d818e3SYunsheng Lin int ret; 2075a6d818e3SYunsheng Lin 2076a6d818e3SYunsheng Lin ret = hclgevf_set_alive(handle, false); 2077a6d818e3SYunsheng Lin if (ret) 2078a6d818e3SYunsheng Lin dev_warn(&hdev->pdev->dev, 2079a6d818e3SYunsheng Lin "%s failed %d\n", __func__, ret); 2080a6d818e3SYunsheng Lin 2081a6d818e3SYunsheng Lin del_timer_sync(&hdev->keep_alive_timer); 2082a6d818e3SYunsheng Lin cancel_work_sync(&hdev->keep_alive_task); 2083a6d818e3SYunsheng Lin } 2084a6d818e3SYunsheng Lin 2085e2cb1decSSalil Mehta static void hclgevf_state_init(struct hclgevf_dev *hdev) 2086e2cb1decSSalil Mehta { 2087e2cb1decSSalil Mehta /* setup tasks for the MBX */ 2088e2cb1decSSalil Mehta INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 2089e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2090e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2091e2cb1decSSalil Mehta 2092e2cb1decSSalil Mehta /* setup tasks for service timer */ 2093e2cb1decSSalil Mehta timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 2094e2cb1decSSalil Mehta 2095e2cb1decSSalil Mehta INIT_WORK(&hdev->service_task, hclgevf_service_task); 2096e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2097e2cb1decSSalil Mehta 209835a1e503SSalil Mehta INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task); 209935a1e503SSalil Mehta 2100e2cb1decSSalil Mehta mutex_init(&hdev->mbx_resp.mbx_mutex); 2101e2cb1decSSalil Mehta 2102e2cb1decSSalil Mehta /* bring the device down */ 2103e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2104e2cb1decSSalil Mehta } 2105e2cb1decSSalil Mehta 2106e2cb1decSSalil Mehta static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2107e2cb1decSSalil Mehta { 2108e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2109e2cb1decSSalil Mehta 2110e233516eSHuazhong Tan if (hdev->keep_alive_timer.function) 2111e233516eSHuazhong Tan del_timer_sync(&hdev->keep_alive_timer); 2112e233516eSHuazhong Tan if (hdev->keep_alive_task.func) 2113e233516eSHuazhong Tan cancel_work_sync(&hdev->keep_alive_task); 2114e2cb1decSSalil Mehta if (hdev->service_timer.function) 2115e2cb1decSSalil Mehta del_timer_sync(&hdev->service_timer); 2116e2cb1decSSalil Mehta if (hdev->service_task.func) 2117e2cb1decSSalil Mehta cancel_work_sync(&hdev->service_task); 2118e2cb1decSSalil Mehta if (hdev->mbx_service_task.func) 2119e2cb1decSSalil Mehta cancel_work_sync(&hdev->mbx_service_task); 212035a1e503SSalil Mehta if (hdev->rst_service_task.func) 212135a1e503SSalil Mehta cancel_work_sync(&hdev->rst_service_task); 2122e2cb1decSSalil Mehta 2123e2cb1decSSalil Mehta mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2124e2cb1decSSalil Mehta } 2125e2cb1decSSalil Mehta 2126e2cb1decSSalil Mehta static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2127e2cb1decSSalil Mehta { 2128e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2129e2cb1decSSalil Mehta int vectors; 2130e2cb1decSSalil Mehta int i; 2131e2cb1decSSalil Mehta 213207acf909SJian Shen if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) 213307acf909SJian Shen vectors = pci_alloc_irq_vectors(pdev, 213407acf909SJian Shen hdev->roce_base_msix_offset + 1, 213507acf909SJian Shen hdev->num_msi, 213607acf909SJian Shen PCI_IRQ_MSIX); 213707acf909SJian Shen else 2138e2cb1decSSalil Mehta vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 2139e2cb1decSSalil Mehta PCI_IRQ_MSI | PCI_IRQ_MSIX); 214007acf909SJian Shen 2141e2cb1decSSalil Mehta if (vectors < 0) { 2142e2cb1decSSalil Mehta dev_err(&pdev->dev, 2143e2cb1decSSalil Mehta "failed(%d) to allocate MSI/MSI-X vectors\n", 2144e2cb1decSSalil Mehta vectors); 2145e2cb1decSSalil Mehta return vectors; 2146e2cb1decSSalil Mehta } 2147e2cb1decSSalil Mehta if (vectors < hdev->num_msi) 2148e2cb1decSSalil Mehta dev_warn(&hdev->pdev->dev, 2149e2cb1decSSalil Mehta "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2150e2cb1decSSalil Mehta hdev->num_msi, vectors); 2151e2cb1decSSalil Mehta 2152e2cb1decSSalil Mehta hdev->num_msi = vectors; 2153e2cb1decSSalil Mehta hdev->num_msi_left = vectors; 2154e2cb1decSSalil Mehta hdev->base_msi_vector = pdev->irq; 215507acf909SJian Shen hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2156e2cb1decSSalil Mehta 2157e2cb1decSSalil Mehta hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2158e2cb1decSSalil Mehta sizeof(u16), GFP_KERNEL); 2159e2cb1decSSalil Mehta if (!hdev->vector_status) { 2160e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2161e2cb1decSSalil Mehta return -ENOMEM; 2162e2cb1decSSalil Mehta } 2163e2cb1decSSalil Mehta 2164e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 2165e2cb1decSSalil Mehta hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2166e2cb1decSSalil Mehta 2167e2cb1decSSalil Mehta hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2168e2cb1decSSalil Mehta sizeof(int), GFP_KERNEL); 2169e2cb1decSSalil Mehta if (!hdev->vector_irq) { 2170862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2171e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2172e2cb1decSSalil Mehta return -ENOMEM; 2173e2cb1decSSalil Mehta } 2174e2cb1decSSalil Mehta 2175e2cb1decSSalil Mehta return 0; 2176e2cb1decSSalil Mehta } 2177e2cb1decSSalil Mehta 2178e2cb1decSSalil Mehta static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2179e2cb1decSSalil Mehta { 2180e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2181e2cb1decSSalil Mehta 2182862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2183862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_irq); 2184e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2185e2cb1decSSalil Mehta } 2186e2cb1decSSalil Mehta 2187e2cb1decSSalil Mehta static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2188e2cb1decSSalil Mehta { 2189e2cb1decSSalil Mehta int ret = 0; 2190e2cb1decSSalil Mehta 2191e2cb1decSSalil Mehta hclgevf_get_misc_vector(hdev); 2192e2cb1decSSalil Mehta 2193e2cb1decSSalil Mehta ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2194e2cb1decSSalil Mehta 0, "hclgevf_cmd", hdev); 2195e2cb1decSSalil Mehta if (ret) { 2196e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2197e2cb1decSSalil Mehta hdev->misc_vector.vector_irq); 2198e2cb1decSSalil Mehta return ret; 2199e2cb1decSSalil Mehta } 2200e2cb1decSSalil Mehta 22011819e409SXi Wang hclgevf_clear_event_cause(hdev, 0); 22021819e409SXi Wang 2203e2cb1decSSalil Mehta /* enable misc. vector(vector 0) */ 2204e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2205e2cb1decSSalil Mehta 2206e2cb1decSSalil Mehta return ret; 2207e2cb1decSSalil Mehta } 2208e2cb1decSSalil Mehta 2209e2cb1decSSalil Mehta static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2210e2cb1decSSalil Mehta { 2211e2cb1decSSalil Mehta /* disable misc vector(vector 0) */ 2212e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 22131819e409SXi Wang synchronize_irq(hdev->misc_vector.vector_irq); 2214e2cb1decSSalil Mehta free_irq(hdev->misc_vector.vector_irq, hdev); 2215e2cb1decSSalil Mehta hclgevf_free_vector(hdev, 0); 2216e2cb1decSSalil Mehta } 2217e2cb1decSSalil Mehta 2218e718a93fSPeng Li static int hclgevf_init_client_instance(struct hnae3_client *client, 2219e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2220e2cb1decSSalil Mehta { 2221e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2222e2cb1decSSalil Mehta int ret; 2223e2cb1decSSalil Mehta 2224e2cb1decSSalil Mehta switch (client->type) { 2225e2cb1decSSalil Mehta case HNAE3_CLIENT_KNIC: 2226e2cb1decSSalil Mehta hdev->nic_client = client; 2227e2cb1decSSalil Mehta hdev->nic.client = client; 2228e2cb1decSSalil Mehta 2229e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->nic); 2230e2cb1decSSalil Mehta if (ret) 223149dd8054SJian Shen goto clear_nic; 2232e2cb1decSSalil Mehta 2233d9f28fc2SJian Shen hnae3_set_client_init_flag(client, ae_dev, 1); 2234d9f28fc2SJian Shen 2235e2cb1decSSalil Mehta if (hdev->roce_client && hnae3_dev_roce_supported(hdev)) { 2236e2cb1decSSalil Mehta struct hnae3_client *rc = hdev->roce_client; 2237e2cb1decSSalil Mehta 2238e2cb1decSSalil Mehta ret = hclgevf_init_roce_base_info(hdev); 2239e2cb1decSSalil Mehta if (ret) 224049dd8054SJian Shen goto clear_roce; 2241e2cb1decSSalil Mehta ret = rc->ops->init_instance(&hdev->roce); 2242e2cb1decSSalil Mehta if (ret) 224349dd8054SJian Shen goto clear_roce; 2244d9f28fc2SJian Shen 2245d9f28fc2SJian Shen hnae3_set_client_init_flag(hdev->roce_client, ae_dev, 2246d9f28fc2SJian Shen 1); 2247e2cb1decSSalil Mehta } 2248e2cb1decSSalil Mehta break; 2249e2cb1decSSalil Mehta case HNAE3_CLIENT_UNIC: 2250e2cb1decSSalil Mehta hdev->nic_client = client; 2251e2cb1decSSalil Mehta hdev->nic.client = client; 2252e2cb1decSSalil Mehta 2253e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->nic); 2254e2cb1decSSalil Mehta if (ret) 225549dd8054SJian Shen goto clear_nic; 2256d9f28fc2SJian Shen 2257d9f28fc2SJian Shen hnae3_set_client_init_flag(client, ae_dev, 1); 2258e2cb1decSSalil Mehta break; 2259e2cb1decSSalil Mehta case HNAE3_CLIENT_ROCE: 2260544a7bcdSLijun Ou if (hnae3_dev_roce_supported(hdev)) { 2261e2cb1decSSalil Mehta hdev->roce_client = client; 2262e2cb1decSSalil Mehta hdev->roce.client = client; 2263544a7bcdSLijun Ou } 2264e2cb1decSSalil Mehta 2265544a7bcdSLijun Ou if (hdev->roce_client && hdev->nic_client) { 2266e2cb1decSSalil Mehta ret = hclgevf_init_roce_base_info(hdev); 2267e2cb1decSSalil Mehta if (ret) 226849dd8054SJian Shen goto clear_roce; 2269e2cb1decSSalil Mehta 2270e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->roce); 2271e2cb1decSSalil Mehta if (ret) 227249dd8054SJian Shen goto clear_roce; 2273e2cb1decSSalil Mehta } 2274d9f28fc2SJian Shen 2275d9f28fc2SJian Shen hnae3_set_client_init_flag(client, ae_dev, 1); 2276fa7a4bd5SJian Shen break; 2277fa7a4bd5SJian Shen default: 2278fa7a4bd5SJian Shen return -EINVAL; 2279e2cb1decSSalil Mehta } 2280e2cb1decSSalil Mehta 2281e2cb1decSSalil Mehta return 0; 228249dd8054SJian Shen 228349dd8054SJian Shen clear_nic: 228449dd8054SJian Shen hdev->nic_client = NULL; 228549dd8054SJian Shen hdev->nic.client = NULL; 228649dd8054SJian Shen return ret; 228749dd8054SJian Shen clear_roce: 228849dd8054SJian Shen hdev->roce_client = NULL; 228949dd8054SJian Shen hdev->roce.client = NULL; 229049dd8054SJian Shen return ret; 2291e2cb1decSSalil Mehta } 2292e2cb1decSSalil Mehta 2293e718a93fSPeng Li static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2294e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2295e2cb1decSSalil Mehta { 2296e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2297e718a93fSPeng Li 2298e2cb1decSSalil Mehta /* un-init roce, if it exists */ 229949dd8054SJian Shen if (hdev->roce_client) { 2300e2cb1decSSalil Mehta hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 230149dd8054SJian Shen hdev->roce_client = NULL; 230249dd8054SJian Shen hdev->roce.client = NULL; 230349dd8054SJian Shen } 2304e2cb1decSSalil Mehta 2305e2cb1decSSalil Mehta /* un-init nic/unic, if this was not called by roce client */ 230649dd8054SJian Shen if (client->ops->uninit_instance && hdev->nic_client && 230749dd8054SJian Shen client->type != HNAE3_CLIENT_ROCE) { 2308e2cb1decSSalil Mehta client->ops->uninit_instance(&hdev->nic, 0); 230949dd8054SJian Shen hdev->nic_client = NULL; 231049dd8054SJian Shen hdev->nic.client = NULL; 231149dd8054SJian Shen } 2312e2cb1decSSalil Mehta } 2313e2cb1decSSalil Mehta 2314e2cb1decSSalil Mehta static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2315e2cb1decSSalil Mehta { 2316e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2317e2cb1decSSalil Mehta struct hclgevf_hw *hw; 2318e2cb1decSSalil Mehta int ret; 2319e2cb1decSSalil Mehta 2320e2cb1decSSalil Mehta ret = pci_enable_device(pdev); 2321e2cb1decSSalil Mehta if (ret) { 2322e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed to enable PCI device\n"); 23233e249d3bSFuyun Liang return ret; 2324e2cb1decSSalil Mehta } 2325e2cb1decSSalil Mehta 2326e2cb1decSSalil Mehta ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2327e2cb1decSSalil Mehta if (ret) { 2328e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2329e2cb1decSSalil Mehta goto err_disable_device; 2330e2cb1decSSalil Mehta } 2331e2cb1decSSalil Mehta 2332e2cb1decSSalil Mehta ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2333e2cb1decSSalil Mehta if (ret) { 2334e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2335e2cb1decSSalil Mehta goto err_disable_device; 2336e2cb1decSSalil Mehta } 2337e2cb1decSSalil Mehta 2338e2cb1decSSalil Mehta pci_set_master(pdev); 2339e2cb1decSSalil Mehta hw = &hdev->hw; 2340e2cb1decSSalil Mehta hw->hdev = hdev; 23412e1ea493SPeng Li hw->io_base = pci_iomap(pdev, 2, 0); 2342e2cb1decSSalil Mehta if (!hw->io_base) { 2343e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't map configuration register space\n"); 2344e2cb1decSSalil Mehta ret = -ENOMEM; 2345e2cb1decSSalil Mehta goto err_clr_master; 2346e2cb1decSSalil Mehta } 2347e2cb1decSSalil Mehta 2348e2cb1decSSalil Mehta return 0; 2349e2cb1decSSalil Mehta 2350e2cb1decSSalil Mehta err_clr_master: 2351e2cb1decSSalil Mehta pci_clear_master(pdev); 2352e2cb1decSSalil Mehta pci_release_regions(pdev); 2353e2cb1decSSalil Mehta err_disable_device: 2354e2cb1decSSalil Mehta pci_disable_device(pdev); 23553e249d3bSFuyun Liang 2356e2cb1decSSalil Mehta return ret; 2357e2cb1decSSalil Mehta } 2358e2cb1decSSalil Mehta 2359e2cb1decSSalil Mehta static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2360e2cb1decSSalil Mehta { 2361e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2362e2cb1decSSalil Mehta 2363e2cb1decSSalil Mehta pci_iounmap(pdev, hdev->hw.io_base); 2364e2cb1decSSalil Mehta pci_clear_master(pdev); 2365e2cb1decSSalil Mehta pci_release_regions(pdev); 2366e2cb1decSSalil Mehta pci_disable_device(pdev); 2367e2cb1decSSalil Mehta } 2368e2cb1decSSalil Mehta 236907acf909SJian Shen static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 237007acf909SJian Shen { 237107acf909SJian Shen struct hclgevf_query_res_cmd *req; 237207acf909SJian Shen struct hclgevf_desc desc; 237307acf909SJian Shen int ret; 237407acf909SJian Shen 237507acf909SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 237607acf909SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 237707acf909SJian Shen if (ret) { 237807acf909SJian Shen dev_err(&hdev->pdev->dev, 237907acf909SJian Shen "query vf resource failed, ret = %d.\n", ret); 238007acf909SJian Shen return ret; 238107acf909SJian Shen } 238207acf909SJian Shen 238307acf909SJian Shen req = (struct hclgevf_query_res_cmd *)desc.data; 238407acf909SJian Shen 238507acf909SJian Shen if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) { 238607acf909SJian Shen hdev->roce_base_msix_offset = 238707acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 238807acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_M, 238907acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_S); 239007acf909SJian Shen hdev->num_roce_msix = 239107acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 239207acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 239307acf909SJian Shen 239407acf909SJian Shen /* VF should have NIC vectors and Roce vectors, NIC vectors 239507acf909SJian Shen * are queued before Roce vectors. The offset is fixed to 64. 239607acf909SJian Shen */ 239707acf909SJian Shen hdev->num_msi = hdev->num_roce_msix + 239807acf909SJian Shen hdev->roce_base_msix_offset; 239907acf909SJian Shen } else { 240007acf909SJian Shen hdev->num_msi = 240107acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 240207acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 240307acf909SJian Shen } 240407acf909SJian Shen 240507acf909SJian Shen return 0; 240607acf909SJian Shen } 240707acf909SJian Shen 2408862d969aSHuazhong Tan static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2409862d969aSHuazhong Tan { 2410862d969aSHuazhong Tan struct pci_dev *pdev = hdev->pdev; 2411862d969aSHuazhong Tan int ret = 0; 2412862d969aSHuazhong Tan 2413862d969aSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2414862d969aSHuazhong Tan test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2415862d969aSHuazhong Tan hclgevf_misc_irq_uninit(hdev); 2416862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2417862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2418862d969aSHuazhong Tan } 2419862d969aSHuazhong Tan 2420862d969aSHuazhong Tan if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2421862d969aSHuazhong Tan pci_set_master(pdev); 2422862d969aSHuazhong Tan ret = hclgevf_init_msi(hdev); 2423862d969aSHuazhong Tan if (ret) { 2424862d969aSHuazhong Tan dev_err(&pdev->dev, 2425862d969aSHuazhong Tan "failed(%d) to init MSI/MSI-X\n", ret); 2426862d969aSHuazhong Tan return ret; 2427862d969aSHuazhong Tan } 2428862d969aSHuazhong Tan 2429862d969aSHuazhong Tan ret = hclgevf_misc_irq_init(hdev); 2430862d969aSHuazhong Tan if (ret) { 2431862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2432862d969aSHuazhong Tan dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2433862d969aSHuazhong Tan ret); 2434862d969aSHuazhong Tan return ret; 2435862d969aSHuazhong Tan } 2436862d969aSHuazhong Tan 2437862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2438862d969aSHuazhong Tan } 2439862d969aSHuazhong Tan 2440862d969aSHuazhong Tan return ret; 2441862d969aSHuazhong Tan } 2442862d969aSHuazhong Tan 24439c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2444e2cb1decSSalil Mehta { 24457a01c897SSalil Mehta struct pci_dev *pdev = hdev->pdev; 2446e2cb1decSSalil Mehta int ret; 2447e2cb1decSSalil Mehta 2448862d969aSHuazhong Tan ret = hclgevf_pci_reset(hdev); 2449862d969aSHuazhong Tan if (ret) { 2450862d969aSHuazhong Tan dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2451862d969aSHuazhong Tan return ret; 2452862d969aSHuazhong Tan } 2453862d969aSHuazhong Tan 24549c6f7085SHuazhong Tan ret = hclgevf_cmd_init(hdev); 24559c6f7085SHuazhong Tan if (ret) { 24569c6f7085SHuazhong Tan dev_err(&pdev->dev, "cmd failed %d\n", ret); 24579c6f7085SHuazhong Tan return ret; 24587a01c897SSalil Mehta } 2459e2cb1decSSalil Mehta 24609c6f7085SHuazhong Tan ret = hclgevf_rss_init_hw(hdev); 24619c6f7085SHuazhong Tan if (ret) { 24629c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 24639c6f7085SHuazhong Tan "failed(%d) to initialize RSS\n", ret); 24649c6f7085SHuazhong Tan return ret; 24659c6f7085SHuazhong Tan } 24669c6f7085SHuazhong Tan 2467b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2468b26a6feaSPeng Li if (ret) 2469b26a6feaSPeng Li return ret; 2470b26a6feaSPeng Li 24719c6f7085SHuazhong Tan ret = hclgevf_init_vlan_config(hdev); 24729c6f7085SHuazhong Tan if (ret) { 24739c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 24749c6f7085SHuazhong Tan "failed(%d) to initialize VLAN config\n", ret); 24759c6f7085SHuazhong Tan return ret; 24769c6f7085SHuazhong Tan } 24779c6f7085SHuazhong Tan 24789c6f7085SHuazhong Tan dev_info(&hdev->pdev->dev, "Reset done\n"); 24799c6f7085SHuazhong Tan 24809c6f7085SHuazhong Tan return 0; 24819c6f7085SHuazhong Tan } 24829c6f7085SHuazhong Tan 24839c6f7085SHuazhong Tan static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 24849c6f7085SHuazhong Tan { 24859c6f7085SHuazhong Tan struct pci_dev *pdev = hdev->pdev; 24869c6f7085SHuazhong Tan int ret; 24879c6f7085SHuazhong Tan 2488e2cb1decSSalil Mehta ret = hclgevf_pci_init(hdev); 2489e2cb1decSSalil Mehta if (ret) { 2490e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI initialization failed\n"); 2491e2cb1decSSalil Mehta return ret; 2492e2cb1decSSalil Mehta } 2493e2cb1decSSalil Mehta 24948b0195a3SHuazhong Tan ret = hclgevf_cmd_queue_init(hdev); 24958b0195a3SHuazhong Tan if (ret) { 24968b0195a3SHuazhong Tan dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret); 24978b0195a3SHuazhong Tan goto err_cmd_queue_init; 24988b0195a3SHuazhong Tan } 24998b0195a3SHuazhong Tan 2500eddf0462SYunsheng Lin ret = hclgevf_cmd_init(hdev); 2501eddf0462SYunsheng Lin if (ret) 2502eddf0462SYunsheng Lin goto err_cmd_init; 2503eddf0462SYunsheng Lin 250407acf909SJian Shen /* Get vf resource */ 250507acf909SJian Shen ret = hclgevf_query_vf_resource(hdev); 250607acf909SJian Shen if (ret) { 250707acf909SJian Shen dev_err(&hdev->pdev->dev, 250807acf909SJian Shen "Query vf status error, ret = %d.\n", ret); 25098b0195a3SHuazhong Tan goto err_cmd_init; 251007acf909SJian Shen } 251107acf909SJian Shen 251207acf909SJian Shen ret = hclgevf_init_msi(hdev); 251307acf909SJian Shen if (ret) { 251407acf909SJian Shen dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 25158b0195a3SHuazhong Tan goto err_cmd_init; 251607acf909SJian Shen } 251707acf909SJian Shen 251807acf909SJian Shen hclgevf_state_init(hdev); 2519dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 252007acf909SJian Shen 2521e2cb1decSSalil Mehta ret = hclgevf_misc_irq_init(hdev); 2522e2cb1decSSalil Mehta if (ret) { 2523e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2524e2cb1decSSalil Mehta ret); 2525e2cb1decSSalil Mehta goto err_misc_irq_init; 2526e2cb1decSSalil Mehta } 2527e2cb1decSSalil Mehta 2528862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2529862d969aSHuazhong Tan 2530e2cb1decSSalil Mehta ret = hclgevf_configure(hdev); 2531e2cb1decSSalil Mehta if (ret) { 2532e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2533e2cb1decSSalil Mehta goto err_config; 2534e2cb1decSSalil Mehta } 2535e2cb1decSSalil Mehta 2536e2cb1decSSalil Mehta ret = hclgevf_alloc_tqps(hdev); 2537e2cb1decSSalil Mehta if (ret) { 2538e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2539e2cb1decSSalil Mehta goto err_config; 2540e2cb1decSSalil Mehta } 2541e2cb1decSSalil Mehta 2542e2cb1decSSalil Mehta ret = hclgevf_set_handle_info(hdev); 2543e2cb1decSSalil Mehta if (ret) { 2544e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 2545e2cb1decSSalil Mehta goto err_config; 2546e2cb1decSSalil Mehta } 2547e2cb1decSSalil Mehta 2548b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2549b26a6feaSPeng Li if (ret) 2550b26a6feaSPeng Li goto err_config; 2551b26a6feaSPeng Li 2552f01f5559SJian Shen /* vf is not allowed to enable unicast/multicast promisc mode. 2553f01f5559SJian Shen * For revision 0x20, default to disable broadcast promisc mode, 2554f01f5559SJian Shen * firmware makes sure broadcast packets can be accepted. 2555f01f5559SJian Shen * For revision 0x21, default to enable broadcast promisc mode. 2556f01f5559SJian Shen */ 2557f01f5559SJian Shen ret = hclgevf_set_promisc_mode(hdev, true); 2558f01f5559SJian Shen if (ret) 2559f01f5559SJian Shen goto err_config; 2560f01f5559SJian Shen 2561e2cb1decSSalil Mehta /* Initialize RSS for this VF */ 2562e2cb1decSSalil Mehta ret = hclgevf_rss_init_hw(hdev); 2563e2cb1decSSalil Mehta if (ret) { 2564e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2565e2cb1decSSalil Mehta "failed(%d) to initialize RSS\n", ret); 2566e2cb1decSSalil Mehta goto err_config; 2567e2cb1decSSalil Mehta } 2568e2cb1decSSalil Mehta 2569e2cb1decSSalil Mehta ret = hclgevf_init_vlan_config(hdev); 2570e2cb1decSSalil Mehta if (ret) { 2571e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2572e2cb1decSSalil Mehta "failed(%d) to initialize VLAN config\n", ret); 2573e2cb1decSSalil Mehta goto err_config; 2574e2cb1decSSalil Mehta } 2575e2cb1decSSalil Mehta 25760742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 2577e2cb1decSSalil Mehta pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME); 2578e2cb1decSSalil Mehta 2579e2cb1decSSalil Mehta return 0; 2580e2cb1decSSalil Mehta 2581e2cb1decSSalil Mehta err_config: 2582e2cb1decSSalil Mehta hclgevf_misc_irq_uninit(hdev); 2583e2cb1decSSalil Mehta err_misc_irq_init: 2584e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2585e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 258607acf909SJian Shen err_cmd_init: 25878b0195a3SHuazhong Tan hclgevf_cmd_uninit(hdev); 25888b0195a3SHuazhong Tan err_cmd_queue_init: 2589e2cb1decSSalil Mehta hclgevf_pci_uninit(hdev); 2590862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2591e2cb1decSSalil Mehta return ret; 2592e2cb1decSSalil Mehta } 2593e2cb1decSSalil Mehta 25947a01c897SSalil Mehta static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2595e2cb1decSSalil Mehta { 2596e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2597862d969aSHuazhong Tan 2598862d969aSHuazhong Tan if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2599eddf0462SYunsheng Lin hclgevf_misc_irq_uninit(hdev); 2600e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 26017a01c897SSalil Mehta } 26027a01c897SSalil Mehta 2603e3338205SHuazhong Tan hclgevf_pci_uninit(hdev); 2604862d969aSHuazhong Tan hclgevf_cmd_uninit(hdev); 2605862d969aSHuazhong Tan } 2606862d969aSHuazhong Tan 26077a01c897SSalil Mehta static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 26087a01c897SSalil Mehta { 26097a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 2610a6d818e3SYunsheng Lin struct hclgevf_dev *hdev; 26117a01c897SSalil Mehta int ret; 26127a01c897SSalil Mehta 26137a01c897SSalil Mehta ret = hclgevf_alloc_hdev(ae_dev); 26147a01c897SSalil Mehta if (ret) { 26157a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device allocation failed\n"); 26167a01c897SSalil Mehta return ret; 26177a01c897SSalil Mehta } 26187a01c897SSalil Mehta 26197a01c897SSalil Mehta ret = hclgevf_init_hdev(ae_dev->priv); 2620a6d818e3SYunsheng Lin if (ret) { 26217a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device initialization failed\n"); 26227a01c897SSalil Mehta return ret; 26237a01c897SSalil Mehta } 26247a01c897SSalil Mehta 2625a6d818e3SYunsheng Lin hdev = ae_dev->priv; 2626a6d818e3SYunsheng Lin timer_setup(&hdev->keep_alive_timer, hclgevf_keep_alive_timer, 0); 2627a6d818e3SYunsheng Lin INIT_WORK(&hdev->keep_alive_task, hclgevf_keep_alive_task); 2628a6d818e3SYunsheng Lin 2629a6d818e3SYunsheng Lin return 0; 2630a6d818e3SYunsheng Lin } 2631a6d818e3SYunsheng Lin 26327a01c897SSalil Mehta static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 26337a01c897SSalil Mehta { 26347a01c897SSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 26357a01c897SSalil Mehta 26367a01c897SSalil Mehta hclgevf_uninit_hdev(hdev); 2637e2cb1decSSalil Mehta ae_dev->priv = NULL; 2638e2cb1decSSalil Mehta } 2639e2cb1decSSalil Mehta 2640849e4607SPeng Li static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2641849e4607SPeng Li { 2642849e4607SPeng Li struct hnae3_handle *nic = &hdev->nic; 2643849e4607SPeng Li struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2644849e4607SPeng Li 26458be73621SHuazhong Tan return min_t(u32, hdev->rss_size_max, 26468be73621SHuazhong Tan hdev->num_tqps / kinfo->num_tc); 2647849e4607SPeng Li } 2648849e4607SPeng Li 2649849e4607SPeng Li /** 2650849e4607SPeng Li * hclgevf_get_channels - Get the current channels enabled and max supported. 2651849e4607SPeng Li * @handle: hardware information for network interface 2652849e4607SPeng Li * @ch: ethtool channels structure 2653849e4607SPeng Li * 2654849e4607SPeng Li * We don't support separate tx and rx queues as channels. The other count 2655849e4607SPeng Li * represents how many queues are being used for control. max_combined counts 2656849e4607SPeng Li * how many queue pairs we can support. They may not be mapped 1 to 1 with 2657849e4607SPeng Li * q_vectors since we support a lot more queue pairs than q_vectors. 2658849e4607SPeng Li **/ 2659849e4607SPeng Li static void hclgevf_get_channels(struct hnae3_handle *handle, 2660849e4607SPeng Li struct ethtool_channels *ch) 2661849e4607SPeng Li { 2662849e4607SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2663849e4607SPeng Li 2664849e4607SPeng Li ch->max_combined = hclgevf_get_max_channels(hdev); 2665849e4607SPeng Li ch->other_count = 0; 2666849e4607SPeng Li ch->max_other = 0; 26678be73621SHuazhong Tan ch->combined_count = handle->kinfo.rss_size; 2668849e4607SPeng Li } 2669849e4607SPeng Li 2670cc719218SPeng Li static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 26710d43bf45SHuazhong Tan u16 *alloc_tqps, u16 *max_rss_size) 2672cc719218SPeng Li { 2673cc719218SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2674cc719218SPeng Li 26750d43bf45SHuazhong Tan *alloc_tqps = hdev->num_tqps; 2676cc719218SPeng Li *max_rss_size = hdev->rss_size_max; 2677cc719218SPeng Li } 2678cc719218SPeng Li 2679175ec96bSFuyun Liang static int hclgevf_get_status(struct hnae3_handle *handle) 2680175ec96bSFuyun Liang { 2681175ec96bSFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2682175ec96bSFuyun Liang 2683175ec96bSFuyun Liang return hdev->hw.mac.link; 2684175ec96bSFuyun Liang } 2685175ec96bSFuyun Liang 26864a152de9SFuyun Liang static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 26874a152de9SFuyun Liang u8 *auto_neg, u32 *speed, 26884a152de9SFuyun Liang u8 *duplex) 26894a152de9SFuyun Liang { 26904a152de9SFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 26914a152de9SFuyun Liang 26924a152de9SFuyun Liang if (speed) 26934a152de9SFuyun Liang *speed = hdev->hw.mac.speed; 26944a152de9SFuyun Liang if (duplex) 26954a152de9SFuyun Liang *duplex = hdev->hw.mac.duplex; 26964a152de9SFuyun Liang if (auto_neg) 26974a152de9SFuyun Liang *auto_neg = AUTONEG_DISABLE; 26984a152de9SFuyun Liang } 26994a152de9SFuyun Liang 27004a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 27014a152de9SFuyun Liang u8 duplex) 27024a152de9SFuyun Liang { 27034a152de9SFuyun Liang hdev->hw.mac.speed = speed; 27044a152de9SFuyun Liang hdev->hw.mac.duplex = duplex; 27054a152de9SFuyun Liang } 27064a152de9SFuyun Liang 27071731be4cSYonglong Liu static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 27085c9f6b39SPeng Li { 27095c9f6b39SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27105c9f6b39SPeng Li 27115c9f6b39SPeng Li return hclgevf_config_gro(hdev, enable); 27125c9f6b39SPeng Li } 27135c9f6b39SPeng Li 2714c136b884SPeng Li static void hclgevf_get_media_type(struct hnae3_handle *handle, 2715c136b884SPeng Li u8 *media_type) 2716c136b884SPeng Li { 2717c136b884SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2718c136b884SPeng Li if (media_type) 2719c136b884SPeng Li *media_type = hdev->hw.mac.media_type; 2720c136b884SPeng Li } 2721c136b884SPeng Li 27224d60291bSHuazhong Tan static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 27234d60291bSHuazhong Tan { 27244d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27254d60291bSHuazhong Tan 2726aa5c4f17SHuazhong Tan return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 27274d60291bSHuazhong Tan } 27284d60291bSHuazhong Tan 27294d60291bSHuazhong Tan static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 27304d60291bSHuazhong Tan { 27314d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27324d60291bSHuazhong Tan 27334d60291bSHuazhong Tan return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 27344d60291bSHuazhong Tan } 27354d60291bSHuazhong Tan 27364d60291bSHuazhong Tan static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 27374d60291bSHuazhong Tan { 27384d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27394d60291bSHuazhong Tan 27404d60291bSHuazhong Tan return hdev->reset_count; 27414d60291bSHuazhong Tan } 27424d60291bSHuazhong Tan 27439194d18bSliuzhongzhu static void hclgevf_get_link_mode(struct hnae3_handle *handle, 27449194d18bSliuzhongzhu unsigned long *supported, 27459194d18bSliuzhongzhu unsigned long *advertising) 27469194d18bSliuzhongzhu { 27479194d18bSliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27489194d18bSliuzhongzhu 27499194d18bSliuzhongzhu *supported = hdev->hw.mac.supported; 27509194d18bSliuzhongzhu *advertising = hdev->hw.mac.advertising; 27519194d18bSliuzhongzhu } 27529194d18bSliuzhongzhu 27531600c3e5SJian Shen #define MAX_SEPARATE_NUM 4 27541600c3e5SJian Shen #define SEPARATOR_VALUE 0xFFFFFFFF 27551600c3e5SJian Shen #define REG_NUM_PER_LINE 4 27561600c3e5SJian Shen #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 27571600c3e5SJian Shen 27581600c3e5SJian Shen static int hclgevf_get_regs_len(struct hnae3_handle *handle) 27591600c3e5SJian Shen { 27601600c3e5SJian Shen int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 27611600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27621600c3e5SJian Shen 27631600c3e5SJian Shen cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 27641600c3e5SJian Shen common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 27651600c3e5SJian Shen ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 27661600c3e5SJian Shen tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 27671600c3e5SJian Shen 27681600c3e5SJian Shen return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 27691600c3e5SJian Shen tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 27701600c3e5SJian Shen } 27711600c3e5SJian Shen 27721600c3e5SJian Shen static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 27731600c3e5SJian Shen void *data) 27741600c3e5SJian Shen { 27751600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27761600c3e5SJian Shen int i, j, reg_um, separator_num; 27771600c3e5SJian Shen u32 *reg = data; 27781600c3e5SJian Shen 27791600c3e5SJian Shen *version = hdev->fw_version; 27801600c3e5SJian Shen 27811600c3e5SJian Shen /* fetching per-VF registers values from VF PCIe register space */ 27821600c3e5SJian Shen reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 27831600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 27841600c3e5SJian Shen for (i = 0; i < reg_um; i++) 27851600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 27861600c3e5SJian Shen for (i = 0; i < separator_num; i++) 27871600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 27881600c3e5SJian Shen 27891600c3e5SJian Shen reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 27901600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 27911600c3e5SJian Shen for (i = 0; i < reg_um; i++) 27921600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 27931600c3e5SJian Shen for (i = 0; i < separator_num; i++) 27941600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 27951600c3e5SJian Shen 27961600c3e5SJian Shen reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 27971600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 27981600c3e5SJian Shen for (j = 0; j < hdev->num_tqps; j++) { 27991600c3e5SJian Shen for (i = 0; i < reg_um; i++) 28001600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 28011600c3e5SJian Shen ring_reg_addr_list[i] + 28021600c3e5SJian Shen 0x200 * j); 28031600c3e5SJian Shen for (i = 0; i < separator_num; i++) 28041600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 28051600c3e5SJian Shen } 28061600c3e5SJian Shen 28071600c3e5SJian Shen reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 28081600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 28091600c3e5SJian Shen for (j = 0; j < hdev->num_msi_used - 1; j++) { 28101600c3e5SJian Shen for (i = 0; i < reg_um; i++) 28111600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 28121600c3e5SJian Shen tqp_intr_reg_addr_list[i] + 28131600c3e5SJian Shen 4 * j); 28141600c3e5SJian Shen for (i = 0; i < separator_num; i++) 28151600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 28161600c3e5SJian Shen } 28171600c3e5SJian Shen } 28181600c3e5SJian Shen 281992f11ea1SJian Shen void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 282092f11ea1SJian Shen u8 *port_base_vlan_info, u8 data_size) 282192f11ea1SJian Shen { 282292f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 282392f11ea1SJian Shen 282492f11ea1SJian Shen rtnl_lock(); 282592f11ea1SJian Shen hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 282692f11ea1SJian Shen rtnl_unlock(); 282792f11ea1SJian Shen 282892f11ea1SJian Shen /* send msg to PF and wait update port based vlan info */ 282992f11ea1SJian Shen hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 283092f11ea1SJian Shen HCLGE_MBX_PORT_BASE_VLAN_CFG, 283192f11ea1SJian Shen port_base_vlan_info, data_size, 283292f11ea1SJian Shen false, NULL, 0); 283392f11ea1SJian Shen 283492f11ea1SJian Shen if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 283592f11ea1SJian Shen nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 283692f11ea1SJian Shen else 283792f11ea1SJian Shen nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 283892f11ea1SJian Shen 283992f11ea1SJian Shen rtnl_lock(); 284092f11ea1SJian Shen hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 284192f11ea1SJian Shen rtnl_unlock(); 284292f11ea1SJian Shen } 284392f11ea1SJian Shen 2844e2cb1decSSalil Mehta static const struct hnae3_ae_ops hclgevf_ops = { 2845e2cb1decSSalil Mehta .init_ae_dev = hclgevf_init_ae_dev, 2846e2cb1decSSalil Mehta .uninit_ae_dev = hclgevf_uninit_ae_dev, 28476ff3cf07SHuazhong Tan .flr_prepare = hclgevf_flr_prepare, 28486ff3cf07SHuazhong Tan .flr_done = hclgevf_flr_done, 2849e718a93fSPeng Li .init_client_instance = hclgevf_init_client_instance, 2850e718a93fSPeng Li .uninit_client_instance = hclgevf_uninit_client_instance, 2851e2cb1decSSalil Mehta .start = hclgevf_ae_start, 2852e2cb1decSSalil Mehta .stop = hclgevf_ae_stop, 2853a6d818e3SYunsheng Lin .client_start = hclgevf_client_start, 2854a6d818e3SYunsheng Lin .client_stop = hclgevf_client_stop, 2855e2cb1decSSalil Mehta .map_ring_to_vector = hclgevf_map_ring_to_vector, 2856e2cb1decSSalil Mehta .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 2857e2cb1decSSalil Mehta .get_vector = hclgevf_get_vector, 28580d3e6631SYunsheng Lin .put_vector = hclgevf_put_vector, 2859e2cb1decSSalil Mehta .reset_queue = hclgevf_reset_tqp, 2860e2cb1decSSalil Mehta .get_mac_addr = hclgevf_get_mac_addr, 2861e2cb1decSSalil Mehta .set_mac_addr = hclgevf_set_mac_addr, 2862e2cb1decSSalil Mehta .add_uc_addr = hclgevf_add_uc_addr, 2863e2cb1decSSalil Mehta .rm_uc_addr = hclgevf_rm_uc_addr, 2864e2cb1decSSalil Mehta .add_mc_addr = hclgevf_add_mc_addr, 2865e2cb1decSSalil Mehta .rm_mc_addr = hclgevf_rm_mc_addr, 2866e2cb1decSSalil Mehta .get_stats = hclgevf_get_stats, 2867e2cb1decSSalil Mehta .update_stats = hclgevf_update_stats, 2868e2cb1decSSalil Mehta .get_strings = hclgevf_get_strings, 2869e2cb1decSSalil Mehta .get_sset_count = hclgevf_get_sset_count, 2870e2cb1decSSalil Mehta .get_rss_key_size = hclgevf_get_rss_key_size, 2871e2cb1decSSalil Mehta .get_rss_indir_size = hclgevf_get_rss_indir_size, 2872e2cb1decSSalil Mehta .get_rss = hclgevf_get_rss, 2873e2cb1decSSalil Mehta .set_rss = hclgevf_set_rss, 2874d97b3072SJian Shen .get_rss_tuple = hclgevf_get_rss_tuple, 2875d97b3072SJian Shen .set_rss_tuple = hclgevf_set_rss_tuple, 2876e2cb1decSSalil Mehta .get_tc_size = hclgevf_get_tc_size, 2877e2cb1decSSalil Mehta .get_fw_version = hclgevf_get_fw_version, 2878e2cb1decSSalil Mehta .set_vlan_filter = hclgevf_set_vlan_filter, 2879b2641e2aSYunsheng Lin .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 28806d4c3981SSalil Mehta .reset_event = hclgevf_reset_event, 2881720bd583SHuazhong Tan .set_default_reset_request = hclgevf_set_def_reset_request, 2882849e4607SPeng Li .get_channels = hclgevf_get_channels, 2883cc719218SPeng Li .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 28841600c3e5SJian Shen .get_regs_len = hclgevf_get_regs_len, 28851600c3e5SJian Shen .get_regs = hclgevf_get_regs, 2886175ec96bSFuyun Liang .get_status = hclgevf_get_status, 28874a152de9SFuyun Liang .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 2888c136b884SPeng Li .get_media_type = hclgevf_get_media_type, 28894d60291bSHuazhong Tan .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 28904d60291bSHuazhong Tan .ae_dev_resetting = hclgevf_ae_dev_resetting, 28914d60291bSHuazhong Tan .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 28925c9f6b39SPeng Li .set_gro_en = hclgevf_gro_en, 2893818f1675SYunsheng Lin .set_mtu = hclgevf_set_mtu, 28940c29d191Sliuzhongzhu .get_global_queue_id = hclgevf_get_qid_global, 28958cdb992fSJian Shen .set_timer_task = hclgevf_set_timer_task, 28969194d18bSliuzhongzhu .get_link_mode = hclgevf_get_link_mode, 2897e2cb1decSSalil Mehta }; 2898e2cb1decSSalil Mehta 2899e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf = { 2900e2cb1decSSalil Mehta .ops = &hclgevf_ops, 2901e2cb1decSSalil Mehta .pdev_id_table = ae_algovf_pci_tbl, 2902e2cb1decSSalil Mehta }; 2903e2cb1decSSalil Mehta 2904e2cb1decSSalil Mehta static int hclgevf_init(void) 2905e2cb1decSSalil Mehta { 2906e2cb1decSSalil Mehta pr_info("%s is initializing\n", HCLGEVF_NAME); 2907e2cb1decSSalil Mehta 2908854cf33aSFuyun Liang hnae3_register_ae_algo(&ae_algovf); 2909854cf33aSFuyun Liang 2910854cf33aSFuyun Liang return 0; 2911e2cb1decSSalil Mehta } 2912e2cb1decSSalil Mehta 2913e2cb1decSSalil Mehta static void hclgevf_exit(void) 2914e2cb1decSSalil Mehta { 2915e2cb1decSSalil Mehta hnae3_unregister_ae_algo(&ae_algovf); 2916e2cb1decSSalil Mehta } 2917e2cb1decSSalil Mehta module_init(hclgevf_init); 2918e2cb1decSSalil Mehta module_exit(hclgevf_exit); 2919e2cb1decSSalil Mehta 2920e2cb1decSSalil Mehta MODULE_LICENSE("GPL"); 2921e2cb1decSSalil Mehta MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 2922e2cb1decSSalil Mehta MODULE_DESCRIPTION("HCLGEVF Driver"); 2923e2cb1decSSalil Mehta MODULE_VERSION(HCLGEVF_MOD_VERSION); 2924