1e2cb1decSSalil Mehta // SPDX-License-Identifier: GPL-2.0+ 2e2cb1decSSalil Mehta // Copyright (c) 2016-2017 Hisilicon Limited. 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #include <linux/etherdevice.h> 5aa5c4f17SHuazhong Tan #include <linux/iopoll.h> 66988eb2aSSalil Mehta #include <net/rtnetlink.h> 7e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 8e2cb1decSSalil Mehta #include "hclgevf_main.h" 9e2cb1decSSalil Mehta #include "hclge_mbx.h" 10e2cb1decSSalil Mehta #include "hnae3.h" 11e2cb1decSSalil Mehta 12e2cb1decSSalil Mehta #define HCLGEVF_NAME "hclgevf" 13e2cb1decSSalil Mehta 149c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 15e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf; 16e2cb1decSSalil Mehta 17e2cb1decSSalil Mehta static const struct pci_device_id ae_algovf_pci_tbl[] = { 18e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 19e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 20e2cb1decSSalil Mehta /* required last entry */ 21e2cb1decSSalil Mehta {0, } 22e2cb1decSSalil Mehta }; 23e2cb1decSSalil Mehta 24472d7eceSJian Shen static const u8 hclgevf_hash_key[] = { 25472d7eceSJian Shen 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 26472d7eceSJian Shen 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 27472d7eceSJian Shen 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 28472d7eceSJian Shen 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 29472d7eceSJian Shen 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 30472d7eceSJian Shen }; 31472d7eceSJian Shen 322f550a46SYunsheng Lin MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 332f550a46SYunsheng Lin 341600c3e5SJian Shen static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 351600c3e5SJian Shen HCLGEVF_CMDQ_TX_ADDR_H_REG, 361600c3e5SJian Shen HCLGEVF_CMDQ_TX_DEPTH_REG, 371600c3e5SJian Shen HCLGEVF_CMDQ_TX_TAIL_REG, 381600c3e5SJian Shen HCLGEVF_CMDQ_TX_HEAD_REG, 391600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_L_REG, 401600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_H_REG, 411600c3e5SJian Shen HCLGEVF_CMDQ_RX_DEPTH_REG, 421600c3e5SJian Shen HCLGEVF_CMDQ_RX_TAIL_REG, 431600c3e5SJian Shen HCLGEVF_CMDQ_RX_HEAD_REG, 441600c3e5SJian Shen HCLGEVF_VECTOR0_CMDQ_SRC_REG, 451600c3e5SJian Shen HCLGEVF_CMDQ_INTR_STS_REG, 461600c3e5SJian Shen HCLGEVF_CMDQ_INTR_EN_REG, 471600c3e5SJian Shen HCLGEVF_CMDQ_INTR_GEN_REG}; 481600c3e5SJian Shen 491600c3e5SJian Shen static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 501600c3e5SJian Shen HCLGEVF_RST_ING, 511600c3e5SJian Shen HCLGEVF_GRO_EN_REG}; 521600c3e5SJian Shen 531600c3e5SJian Shen static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 541600c3e5SJian Shen HCLGEVF_RING_RX_ADDR_H_REG, 551600c3e5SJian Shen HCLGEVF_RING_RX_BD_NUM_REG, 561600c3e5SJian Shen HCLGEVF_RING_RX_BD_LENGTH_REG, 571600c3e5SJian Shen HCLGEVF_RING_RX_MERGE_EN_REG, 581600c3e5SJian Shen HCLGEVF_RING_RX_TAIL_REG, 591600c3e5SJian Shen HCLGEVF_RING_RX_HEAD_REG, 601600c3e5SJian Shen HCLGEVF_RING_RX_FBD_NUM_REG, 611600c3e5SJian Shen HCLGEVF_RING_RX_OFFSET_REG, 621600c3e5SJian Shen HCLGEVF_RING_RX_FBD_OFFSET_REG, 631600c3e5SJian Shen HCLGEVF_RING_RX_STASH_REG, 641600c3e5SJian Shen HCLGEVF_RING_RX_BD_ERR_REG, 651600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_L_REG, 661600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_H_REG, 671600c3e5SJian Shen HCLGEVF_RING_TX_BD_NUM_REG, 681600c3e5SJian Shen HCLGEVF_RING_TX_PRIORITY_REG, 691600c3e5SJian Shen HCLGEVF_RING_TX_TC_REG, 701600c3e5SJian Shen HCLGEVF_RING_TX_MERGE_EN_REG, 711600c3e5SJian Shen HCLGEVF_RING_TX_TAIL_REG, 721600c3e5SJian Shen HCLGEVF_RING_TX_HEAD_REG, 731600c3e5SJian Shen HCLGEVF_RING_TX_FBD_NUM_REG, 741600c3e5SJian Shen HCLGEVF_RING_TX_OFFSET_REG, 751600c3e5SJian Shen HCLGEVF_RING_TX_EBD_NUM_REG, 761600c3e5SJian Shen HCLGEVF_RING_TX_EBD_OFFSET_REG, 771600c3e5SJian Shen HCLGEVF_RING_TX_BD_ERR_REG, 781600c3e5SJian Shen HCLGEVF_RING_EN_REG}; 791600c3e5SJian Shen 801600c3e5SJian Shen static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 811600c3e5SJian Shen HCLGEVF_TQP_INTR_GL0_REG, 821600c3e5SJian Shen HCLGEVF_TQP_INTR_GL1_REG, 831600c3e5SJian Shen HCLGEVF_TQP_INTR_GL2_REG, 841600c3e5SJian Shen HCLGEVF_TQP_INTR_RL_REG}; 851600c3e5SJian Shen 86e2cb1decSSalil Mehta static inline struct hclgevf_dev *hclgevf_ae_get_hdev( 87e2cb1decSSalil Mehta struct hnae3_handle *handle) 88e2cb1decSSalil Mehta { 89eed9535fSPeng Li if (!handle->client) 90eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, nic); 91eed9535fSPeng Li else if (handle->client->type == HNAE3_CLIENT_ROCE) 92eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, roce); 93eed9535fSPeng Li else 94e2cb1decSSalil Mehta return container_of(handle, struct hclgevf_dev, nic); 95e2cb1decSSalil Mehta } 96e2cb1decSSalil Mehta 97e2cb1decSSalil Mehta static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 98e2cb1decSSalil Mehta { 99b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 100e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 101e2cb1decSSalil Mehta struct hclgevf_desc desc; 102e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 103e2cb1decSSalil Mehta int status; 104e2cb1decSSalil Mehta int i; 105e2cb1decSSalil Mehta 106b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 107b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 108e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 109e2cb1decSSalil Mehta HCLGEVF_OPC_QUERY_RX_STATUS, 110e2cb1decSSalil Mehta true); 111e2cb1decSSalil Mehta 112e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 113e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 114e2cb1decSSalil Mehta if (status) { 115e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 116e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 117e2cb1decSSalil Mehta status, i); 118e2cb1decSSalil Mehta return status; 119e2cb1decSSalil Mehta } 120e2cb1decSSalil Mehta tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 121cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 122e2cb1decSSalil Mehta 123e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 124e2cb1decSSalil Mehta true); 125e2cb1decSSalil Mehta 126e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 127e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 128e2cb1decSSalil Mehta if (status) { 129e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 130e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 131e2cb1decSSalil Mehta status, i); 132e2cb1decSSalil Mehta return status; 133e2cb1decSSalil Mehta } 134e2cb1decSSalil Mehta tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 135cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 136e2cb1decSSalil Mehta } 137e2cb1decSSalil Mehta 138e2cb1decSSalil Mehta return 0; 139e2cb1decSSalil Mehta } 140e2cb1decSSalil Mehta 141e2cb1decSSalil Mehta static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 142e2cb1decSSalil Mehta { 143e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo = &handle->kinfo; 144e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 145e2cb1decSSalil Mehta u64 *buff = data; 146e2cb1decSSalil Mehta int i; 147e2cb1decSSalil Mehta 148b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 149b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 150e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 151e2cb1decSSalil Mehta } 152e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 153b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 154e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 155e2cb1decSSalil Mehta } 156e2cb1decSSalil Mehta 157e2cb1decSSalil Mehta return buff; 158e2cb1decSSalil Mehta } 159e2cb1decSSalil Mehta 160e2cb1decSSalil Mehta static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 161e2cb1decSSalil Mehta { 162b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 163e2cb1decSSalil Mehta 164b4f1d303SJian Shen return kinfo->num_tqps * 2; 165e2cb1decSSalil Mehta } 166e2cb1decSSalil Mehta 167e2cb1decSSalil Mehta static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 168e2cb1decSSalil Mehta { 169b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 170e2cb1decSSalil Mehta u8 *buff = data; 171e2cb1decSSalil Mehta int i = 0; 172e2cb1decSSalil Mehta 173b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 174b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 175e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1760c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 177e2cb1decSSalil Mehta tqp->index); 178e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 179e2cb1decSSalil Mehta } 180e2cb1decSSalil Mehta 181b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 182b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 183e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1840c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 185e2cb1decSSalil Mehta tqp->index); 186e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 187e2cb1decSSalil Mehta } 188e2cb1decSSalil Mehta 189e2cb1decSSalil Mehta return buff; 190e2cb1decSSalil Mehta } 191e2cb1decSSalil Mehta 192e2cb1decSSalil Mehta static void hclgevf_update_stats(struct hnae3_handle *handle, 193e2cb1decSSalil Mehta struct net_device_stats *net_stats) 194e2cb1decSSalil Mehta { 195e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 196e2cb1decSSalil Mehta int status; 197e2cb1decSSalil Mehta 198e2cb1decSSalil Mehta status = hclgevf_tqps_update_stats(handle); 199e2cb1decSSalil Mehta if (status) 200e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 201e2cb1decSSalil Mehta "VF update of TQPS stats fail, status = %d.\n", 202e2cb1decSSalil Mehta status); 203e2cb1decSSalil Mehta } 204e2cb1decSSalil Mehta 205e2cb1decSSalil Mehta static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 206e2cb1decSSalil Mehta { 207e2cb1decSSalil Mehta if (strset == ETH_SS_TEST) 208e2cb1decSSalil Mehta return -EOPNOTSUPP; 209e2cb1decSSalil Mehta else if (strset == ETH_SS_STATS) 210e2cb1decSSalil Mehta return hclgevf_tqps_get_sset_count(handle, strset); 211e2cb1decSSalil Mehta 212e2cb1decSSalil Mehta return 0; 213e2cb1decSSalil Mehta } 214e2cb1decSSalil Mehta 215e2cb1decSSalil Mehta static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 216e2cb1decSSalil Mehta u8 *data) 217e2cb1decSSalil Mehta { 218e2cb1decSSalil Mehta u8 *p = (char *)data; 219e2cb1decSSalil Mehta 220e2cb1decSSalil Mehta if (strset == ETH_SS_STATS) 221e2cb1decSSalil Mehta p = hclgevf_tqps_get_strings(handle, p); 222e2cb1decSSalil Mehta } 223e2cb1decSSalil Mehta 224e2cb1decSSalil Mehta static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 225e2cb1decSSalil Mehta { 226e2cb1decSSalil Mehta hclgevf_tqps_get_stats(handle, data); 227e2cb1decSSalil Mehta } 228e2cb1decSSalil Mehta 229e2cb1decSSalil Mehta static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 230e2cb1decSSalil Mehta { 231e2cb1decSSalil Mehta u8 resp_msg; 232e2cb1decSSalil Mehta int status; 233e2cb1decSSalil Mehta 234e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 235e2cb1decSSalil Mehta true, &resp_msg, sizeof(u8)); 236e2cb1decSSalil Mehta if (status) { 237e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 238e2cb1decSSalil Mehta "VF request to get TC info from PF failed %d", 239e2cb1decSSalil Mehta status); 240e2cb1decSSalil Mehta return status; 241e2cb1decSSalil Mehta } 242e2cb1decSSalil Mehta 243e2cb1decSSalil Mehta hdev->hw_tc_map = resp_msg; 244e2cb1decSSalil Mehta 245e2cb1decSSalil Mehta return 0; 246e2cb1decSSalil Mehta } 247e2cb1decSSalil Mehta 2486cee6fc3SJian Shen static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 249e2cb1decSSalil Mehta { 250e2cb1decSSalil Mehta #define HCLGEVF_TQPS_RSS_INFO_LEN 8 251e2cb1decSSalil Mehta u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 252e2cb1decSSalil Mehta int status; 253e2cb1decSSalil Mehta 254e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 255e2cb1decSSalil Mehta true, resp_msg, 256e2cb1decSSalil Mehta HCLGEVF_TQPS_RSS_INFO_LEN); 257e2cb1decSSalil Mehta if (status) { 258e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 259e2cb1decSSalil Mehta "VF request to get tqp info from PF failed %d", 260e2cb1decSSalil Mehta status); 261e2cb1decSSalil Mehta return status; 262e2cb1decSSalil Mehta } 263e2cb1decSSalil Mehta 264e2cb1decSSalil Mehta memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 265e2cb1decSSalil Mehta memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 266e2cb1decSSalil Mehta memcpy(&hdev->num_desc, &resp_msg[4], sizeof(u16)); 267e2cb1decSSalil Mehta memcpy(&hdev->rx_buf_len, &resp_msg[6], sizeof(u16)); 268e2cb1decSSalil Mehta 269e2cb1decSSalil Mehta return 0; 270e2cb1decSSalil Mehta } 271e2cb1decSSalil Mehta 2720c29d191Sliuzhongzhu static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 2730c29d191Sliuzhongzhu { 2740c29d191Sliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2750c29d191Sliuzhongzhu u8 msg_data[2], resp_data[2]; 2760c29d191Sliuzhongzhu u16 qid_in_pf = 0; 2770c29d191Sliuzhongzhu int ret; 2780c29d191Sliuzhongzhu 2790c29d191Sliuzhongzhu memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 2800c29d191Sliuzhongzhu 2810c29d191Sliuzhongzhu ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data, 2820c29d191Sliuzhongzhu 2, true, resp_data, 2); 2830c29d191Sliuzhongzhu if (!ret) 2840c29d191Sliuzhongzhu qid_in_pf = *(u16 *)resp_data; 2850c29d191Sliuzhongzhu 2860c29d191Sliuzhongzhu return qid_in_pf; 2870c29d191Sliuzhongzhu } 2880c29d191Sliuzhongzhu 289e2cb1decSSalil Mehta static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 290e2cb1decSSalil Mehta { 291e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 292e2cb1decSSalil Mehta int i; 293e2cb1decSSalil Mehta 294e2cb1decSSalil Mehta hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 295e2cb1decSSalil Mehta sizeof(struct hclgevf_tqp), GFP_KERNEL); 296e2cb1decSSalil Mehta if (!hdev->htqp) 297e2cb1decSSalil Mehta return -ENOMEM; 298e2cb1decSSalil Mehta 299e2cb1decSSalil Mehta tqp = hdev->htqp; 300e2cb1decSSalil Mehta 301e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 302e2cb1decSSalil Mehta tqp->dev = &hdev->pdev->dev; 303e2cb1decSSalil Mehta tqp->index = i; 304e2cb1decSSalil Mehta 305e2cb1decSSalil Mehta tqp->q.ae_algo = &ae_algovf; 306e2cb1decSSalil Mehta tqp->q.buf_size = hdev->rx_buf_len; 307e2cb1decSSalil Mehta tqp->q.desc_num = hdev->num_desc; 308e2cb1decSSalil Mehta tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 309e2cb1decSSalil Mehta i * HCLGEVF_TQP_REG_SIZE; 310e2cb1decSSalil Mehta 311e2cb1decSSalil Mehta tqp++; 312e2cb1decSSalil Mehta } 313e2cb1decSSalil Mehta 314e2cb1decSSalil Mehta return 0; 315e2cb1decSSalil Mehta } 316e2cb1decSSalil Mehta 317e2cb1decSSalil Mehta static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 318e2cb1decSSalil Mehta { 319e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 320e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo; 321e2cb1decSSalil Mehta u16 new_tqps = hdev->num_tqps; 322e2cb1decSSalil Mehta int i; 323e2cb1decSSalil Mehta 324e2cb1decSSalil Mehta kinfo = &nic->kinfo; 325e2cb1decSSalil Mehta kinfo->num_tc = 0; 326e2cb1decSSalil Mehta kinfo->num_desc = hdev->num_desc; 327e2cb1decSSalil Mehta kinfo->rx_buf_len = hdev->rx_buf_len; 328e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 329e2cb1decSSalil Mehta if (hdev->hw_tc_map & BIT(i)) 330e2cb1decSSalil Mehta kinfo->num_tc++; 331e2cb1decSSalil Mehta 332e2cb1decSSalil Mehta kinfo->rss_size 333e2cb1decSSalil Mehta = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 334e2cb1decSSalil Mehta new_tqps = kinfo->rss_size * kinfo->num_tc; 335e2cb1decSSalil Mehta kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 336e2cb1decSSalil Mehta 337e2cb1decSSalil Mehta kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 338e2cb1decSSalil Mehta sizeof(struct hnae3_queue *), GFP_KERNEL); 339e2cb1decSSalil Mehta if (!kinfo->tqp) 340e2cb1decSSalil Mehta return -ENOMEM; 341e2cb1decSSalil Mehta 342e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 343e2cb1decSSalil Mehta hdev->htqp[i].q.handle = &hdev->nic; 344e2cb1decSSalil Mehta hdev->htqp[i].q.tqp_index = i; 345e2cb1decSSalil Mehta kinfo->tqp[i] = &hdev->htqp[i].q; 346e2cb1decSSalil Mehta } 347e2cb1decSSalil Mehta 348e2cb1decSSalil Mehta return 0; 349e2cb1decSSalil Mehta } 350e2cb1decSSalil Mehta 351e2cb1decSSalil Mehta static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 352e2cb1decSSalil Mehta { 353e2cb1decSSalil Mehta int status; 354e2cb1decSSalil Mehta u8 resp_msg; 355e2cb1decSSalil Mehta 356e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 357e2cb1decSSalil Mehta 0, false, &resp_msg, sizeof(u8)); 358e2cb1decSSalil Mehta if (status) 359e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 360e2cb1decSSalil Mehta "VF failed to fetch link status(%d) from PF", status); 361e2cb1decSSalil Mehta } 362e2cb1decSSalil Mehta 363e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 364e2cb1decSSalil Mehta { 36545e92b7eSPeng Li struct hnae3_handle *rhandle = &hdev->roce; 366e2cb1decSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 36745e92b7eSPeng Li struct hnae3_client *rclient; 368e2cb1decSSalil Mehta struct hnae3_client *client; 369e2cb1decSSalil Mehta 370e2cb1decSSalil Mehta client = handle->client; 37145e92b7eSPeng Li rclient = hdev->roce_client; 372e2cb1decSSalil Mehta 373582d37bbSPeng Li link_state = 374582d37bbSPeng Li test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 375582d37bbSPeng Li 376e2cb1decSSalil Mehta if (link_state != hdev->hw.mac.link) { 377e2cb1decSSalil Mehta client->ops->link_status_change(handle, !!link_state); 37845e92b7eSPeng Li if (rclient && rclient->ops->link_status_change) 37945e92b7eSPeng Li rclient->ops->link_status_change(rhandle, !!link_state); 380e2cb1decSSalil Mehta hdev->hw.mac.link = link_state; 381e2cb1decSSalil Mehta } 382e2cb1decSSalil Mehta } 383e2cb1decSSalil Mehta 3849194d18bSliuzhongzhu void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 3859194d18bSliuzhongzhu { 3869194d18bSliuzhongzhu #define HCLGEVF_ADVERTISING 0 3879194d18bSliuzhongzhu #define HCLGEVF_SUPPORTED 1 3889194d18bSliuzhongzhu u8 send_msg; 3899194d18bSliuzhongzhu u8 resp_msg; 3909194d18bSliuzhongzhu 3919194d18bSliuzhongzhu send_msg = HCLGEVF_ADVERTISING; 3929194d18bSliuzhongzhu hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, &send_msg, 3939194d18bSliuzhongzhu sizeof(u8), false, &resp_msg, sizeof(u8)); 3949194d18bSliuzhongzhu send_msg = HCLGEVF_SUPPORTED; 3959194d18bSliuzhongzhu hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, &send_msg, 3969194d18bSliuzhongzhu sizeof(u8), false, &resp_msg, sizeof(u8)); 3979194d18bSliuzhongzhu } 3989194d18bSliuzhongzhu 399e2cb1decSSalil Mehta static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 400e2cb1decSSalil Mehta { 401e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 402e2cb1decSSalil Mehta int ret; 403e2cb1decSSalil Mehta 404e2cb1decSSalil Mehta nic->ae_algo = &ae_algovf; 405e2cb1decSSalil Mehta nic->pdev = hdev->pdev; 406e2cb1decSSalil Mehta nic->numa_node_mask = hdev->numa_node_mask; 407424eb834SSalil Mehta nic->flags |= HNAE3_SUPPORT_VF; 408e2cb1decSSalil Mehta 409e2cb1decSSalil Mehta if (hdev->ae_dev->dev_type != HNAE3_DEV_KNIC) { 410e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "unsupported device type %d\n", 411e2cb1decSSalil Mehta hdev->ae_dev->dev_type); 412e2cb1decSSalil Mehta return -EINVAL; 413e2cb1decSSalil Mehta } 414e2cb1decSSalil Mehta 415e2cb1decSSalil Mehta ret = hclgevf_knic_setup(hdev); 416e2cb1decSSalil Mehta if (ret) 417e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 418e2cb1decSSalil Mehta ret); 419e2cb1decSSalil Mehta return ret; 420e2cb1decSSalil Mehta } 421e2cb1decSSalil Mehta 422e2cb1decSSalil Mehta static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 423e2cb1decSSalil Mehta { 42436cbbdf6SPeng Li if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 42536cbbdf6SPeng Li dev_warn(&hdev->pdev->dev, 42636cbbdf6SPeng Li "vector(vector_id %d) has been freed.\n", vector_id); 42736cbbdf6SPeng Li return; 42836cbbdf6SPeng Li } 42936cbbdf6SPeng Li 430e2cb1decSSalil Mehta hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 431e2cb1decSSalil Mehta hdev->num_msi_left += 1; 432e2cb1decSSalil Mehta hdev->num_msi_used -= 1; 433e2cb1decSSalil Mehta } 434e2cb1decSSalil Mehta 435e2cb1decSSalil Mehta static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 436e2cb1decSSalil Mehta struct hnae3_vector_info *vector_info) 437e2cb1decSSalil Mehta { 438e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 439e2cb1decSSalil Mehta struct hnae3_vector_info *vector = vector_info; 440e2cb1decSSalil Mehta int alloc = 0; 441e2cb1decSSalil Mehta int i, j; 442e2cb1decSSalil Mehta 443e2cb1decSSalil Mehta vector_num = min(hdev->num_msi_left, vector_num); 444e2cb1decSSalil Mehta 445e2cb1decSSalil Mehta for (j = 0; j < vector_num; j++) { 446e2cb1decSSalil Mehta for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 447e2cb1decSSalil Mehta if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 448e2cb1decSSalil Mehta vector->vector = pci_irq_vector(hdev->pdev, i); 449e2cb1decSSalil Mehta vector->io_addr = hdev->hw.io_base + 450e2cb1decSSalil Mehta HCLGEVF_VECTOR_REG_BASE + 451e2cb1decSSalil Mehta (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 452e2cb1decSSalil Mehta hdev->vector_status[i] = 0; 453e2cb1decSSalil Mehta hdev->vector_irq[i] = vector->vector; 454e2cb1decSSalil Mehta 455e2cb1decSSalil Mehta vector++; 456e2cb1decSSalil Mehta alloc++; 457e2cb1decSSalil Mehta 458e2cb1decSSalil Mehta break; 459e2cb1decSSalil Mehta } 460e2cb1decSSalil Mehta } 461e2cb1decSSalil Mehta } 462e2cb1decSSalil Mehta hdev->num_msi_left -= alloc; 463e2cb1decSSalil Mehta hdev->num_msi_used += alloc; 464e2cb1decSSalil Mehta 465e2cb1decSSalil Mehta return alloc; 466e2cb1decSSalil Mehta } 467e2cb1decSSalil Mehta 468e2cb1decSSalil Mehta static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 469e2cb1decSSalil Mehta { 470e2cb1decSSalil Mehta int i; 471e2cb1decSSalil Mehta 472e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 473e2cb1decSSalil Mehta if (vector == hdev->vector_irq[i]) 474e2cb1decSSalil Mehta return i; 475e2cb1decSSalil Mehta 476e2cb1decSSalil Mehta return -EINVAL; 477e2cb1decSSalil Mehta } 478e2cb1decSSalil Mehta 479374ad291SJian Shen static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 480374ad291SJian Shen const u8 hfunc, const u8 *key) 481374ad291SJian Shen { 482374ad291SJian Shen struct hclgevf_rss_config_cmd *req; 483374ad291SJian Shen struct hclgevf_desc desc; 484374ad291SJian Shen int key_offset; 485374ad291SJian Shen int key_size; 486374ad291SJian Shen int ret; 487374ad291SJian Shen 488374ad291SJian Shen req = (struct hclgevf_rss_config_cmd *)desc.data; 489374ad291SJian Shen 490374ad291SJian Shen for (key_offset = 0; key_offset < 3; key_offset++) { 491374ad291SJian Shen hclgevf_cmd_setup_basic_desc(&desc, 492374ad291SJian Shen HCLGEVF_OPC_RSS_GENERIC_CONFIG, 493374ad291SJian Shen false); 494374ad291SJian Shen 495374ad291SJian Shen req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 496374ad291SJian Shen req->hash_config |= 497374ad291SJian Shen (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 498374ad291SJian Shen 499374ad291SJian Shen if (key_offset == 2) 500374ad291SJian Shen key_size = 501374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE - HCLGEVF_RSS_HASH_KEY_NUM * 2; 502374ad291SJian Shen else 503374ad291SJian Shen key_size = HCLGEVF_RSS_HASH_KEY_NUM; 504374ad291SJian Shen 505374ad291SJian Shen memcpy(req->hash_key, 506374ad291SJian Shen key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 507374ad291SJian Shen 508374ad291SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 509374ad291SJian Shen if (ret) { 510374ad291SJian Shen dev_err(&hdev->pdev->dev, 511374ad291SJian Shen "Configure RSS config fail, status = %d\n", 512374ad291SJian Shen ret); 513374ad291SJian Shen return ret; 514374ad291SJian Shen } 515374ad291SJian Shen } 516374ad291SJian Shen 517374ad291SJian Shen return 0; 518374ad291SJian Shen } 519374ad291SJian Shen 520e2cb1decSSalil Mehta static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 521e2cb1decSSalil Mehta { 522e2cb1decSSalil Mehta return HCLGEVF_RSS_KEY_SIZE; 523e2cb1decSSalil Mehta } 524e2cb1decSSalil Mehta 525e2cb1decSSalil Mehta static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 526e2cb1decSSalil Mehta { 527e2cb1decSSalil Mehta return HCLGEVF_RSS_IND_TBL_SIZE; 528e2cb1decSSalil Mehta } 529e2cb1decSSalil Mehta 530e2cb1decSSalil Mehta static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 531e2cb1decSSalil Mehta { 532e2cb1decSSalil Mehta const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 533e2cb1decSSalil Mehta struct hclgevf_rss_indirection_table_cmd *req; 534e2cb1decSSalil Mehta struct hclgevf_desc desc; 535e2cb1decSSalil Mehta int status; 536e2cb1decSSalil Mehta int i, j; 537e2cb1decSSalil Mehta 538e2cb1decSSalil Mehta req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 539e2cb1decSSalil Mehta 540e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 541e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 542e2cb1decSSalil Mehta false); 543e2cb1decSSalil Mehta req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 544e2cb1decSSalil Mehta req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 545e2cb1decSSalil Mehta for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 546e2cb1decSSalil Mehta req->rss_result[j] = 547e2cb1decSSalil Mehta indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 548e2cb1decSSalil Mehta 549e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 550e2cb1decSSalil Mehta if (status) { 551e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 552e2cb1decSSalil Mehta "VF failed(=%d) to set RSS indirection table\n", 553e2cb1decSSalil Mehta status); 554e2cb1decSSalil Mehta return status; 555e2cb1decSSalil Mehta } 556e2cb1decSSalil Mehta } 557e2cb1decSSalil Mehta 558e2cb1decSSalil Mehta return 0; 559e2cb1decSSalil Mehta } 560e2cb1decSSalil Mehta 561e2cb1decSSalil Mehta static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 562e2cb1decSSalil Mehta { 563e2cb1decSSalil Mehta struct hclgevf_rss_tc_mode_cmd *req; 564e2cb1decSSalil Mehta u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 565e2cb1decSSalil Mehta u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 566e2cb1decSSalil Mehta u16 tc_size[HCLGEVF_MAX_TC_NUM]; 567e2cb1decSSalil Mehta struct hclgevf_desc desc; 568e2cb1decSSalil Mehta u16 roundup_size; 569e2cb1decSSalil Mehta int status; 570e2cb1decSSalil Mehta int i; 571e2cb1decSSalil Mehta 572e2cb1decSSalil Mehta req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 573e2cb1decSSalil Mehta 574e2cb1decSSalil Mehta roundup_size = roundup_pow_of_two(rss_size); 575e2cb1decSSalil Mehta roundup_size = ilog2(roundup_size); 576e2cb1decSSalil Mehta 577e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 578e2cb1decSSalil Mehta tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 579e2cb1decSSalil Mehta tc_size[i] = roundup_size; 580e2cb1decSSalil Mehta tc_offset[i] = rss_size * i; 581e2cb1decSSalil Mehta } 582e2cb1decSSalil Mehta 583e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 584e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 585e4e87715SPeng Li hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 586e2cb1decSSalil Mehta (tc_valid[i] & 0x1)); 587e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 588e2cb1decSSalil Mehta HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 589e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 590e2cb1decSSalil Mehta HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 591e2cb1decSSalil Mehta } 592e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 593e2cb1decSSalil Mehta if (status) 594e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 595e2cb1decSSalil Mehta "VF failed(=%d) to set rss tc mode\n", status); 596e2cb1decSSalil Mehta 597e2cb1decSSalil Mehta return status; 598e2cb1decSSalil Mehta } 599e2cb1decSSalil Mehta 600e2cb1decSSalil Mehta static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 601e2cb1decSSalil Mehta u8 *hfunc) 602e2cb1decSSalil Mehta { 603e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 604e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 605e2cb1decSSalil Mehta int i; 606e2cb1decSSalil Mehta 607374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 608374ad291SJian Shen /* Get hash algorithm */ 609374ad291SJian Shen if (hfunc) { 610374ad291SJian Shen switch (rss_cfg->hash_algo) { 611374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 612374ad291SJian Shen *hfunc = ETH_RSS_HASH_TOP; 613374ad291SJian Shen break; 614374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 615374ad291SJian Shen *hfunc = ETH_RSS_HASH_XOR; 616374ad291SJian Shen break; 617374ad291SJian Shen default: 618374ad291SJian Shen *hfunc = ETH_RSS_HASH_UNKNOWN; 619374ad291SJian Shen break; 620374ad291SJian Shen } 621374ad291SJian Shen } 622374ad291SJian Shen 623374ad291SJian Shen /* Get the RSS Key required by the user */ 624374ad291SJian Shen if (key) 625374ad291SJian Shen memcpy(key, rss_cfg->rss_hash_key, 626374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 627374ad291SJian Shen } 628374ad291SJian Shen 629e2cb1decSSalil Mehta if (indir) 630e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 631e2cb1decSSalil Mehta indir[i] = rss_cfg->rss_indirection_tbl[i]; 632e2cb1decSSalil Mehta 633374ad291SJian Shen return 0; 634e2cb1decSSalil Mehta } 635e2cb1decSSalil Mehta 636e2cb1decSSalil Mehta static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 637e2cb1decSSalil Mehta const u8 *key, const u8 hfunc) 638e2cb1decSSalil Mehta { 639e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 640e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 641374ad291SJian Shen int ret, i; 642374ad291SJian Shen 643374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 644374ad291SJian Shen /* Set the RSS Hash Key if specififed by the user */ 645374ad291SJian Shen if (key) { 646374ad291SJian Shen switch (hfunc) { 647374ad291SJian Shen case ETH_RSS_HASH_TOP: 648374ad291SJian Shen rss_cfg->hash_algo = 649374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 650374ad291SJian Shen break; 651374ad291SJian Shen case ETH_RSS_HASH_XOR: 652374ad291SJian Shen rss_cfg->hash_algo = 653374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_SIMPLE; 654374ad291SJian Shen break; 655374ad291SJian Shen case ETH_RSS_HASH_NO_CHANGE: 656374ad291SJian Shen break; 657374ad291SJian Shen default: 658374ad291SJian Shen return -EINVAL; 659374ad291SJian Shen } 660374ad291SJian Shen 661374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 662374ad291SJian Shen key); 663374ad291SJian Shen if (ret) 664374ad291SJian Shen return ret; 665374ad291SJian Shen 666374ad291SJian Shen /* Update the shadow RSS key with user specified qids */ 667374ad291SJian Shen memcpy(rss_cfg->rss_hash_key, key, 668374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 669374ad291SJian Shen } 670374ad291SJian Shen } 671e2cb1decSSalil Mehta 672e2cb1decSSalil Mehta /* update the shadow RSS table with user specified qids */ 673e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 674e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = indir[i]; 675e2cb1decSSalil Mehta 676e2cb1decSSalil Mehta /* update the hardware */ 677e2cb1decSSalil Mehta return hclgevf_set_rss_indir_table(hdev); 678e2cb1decSSalil Mehta } 679e2cb1decSSalil Mehta 680d97b3072SJian Shen static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 681d97b3072SJian Shen { 682d97b3072SJian Shen u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 683d97b3072SJian Shen 684d97b3072SJian Shen if (nfc->data & RXH_L4_B_2_3) 685d97b3072SJian Shen hash_sets |= HCLGEVF_D_PORT_BIT; 686d97b3072SJian Shen else 687d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_PORT_BIT; 688d97b3072SJian Shen 689d97b3072SJian Shen if (nfc->data & RXH_IP_SRC) 690d97b3072SJian Shen hash_sets |= HCLGEVF_S_IP_BIT; 691d97b3072SJian Shen else 692d97b3072SJian Shen hash_sets &= ~HCLGEVF_S_IP_BIT; 693d97b3072SJian Shen 694d97b3072SJian Shen if (nfc->data & RXH_IP_DST) 695d97b3072SJian Shen hash_sets |= HCLGEVF_D_IP_BIT; 696d97b3072SJian Shen else 697d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_IP_BIT; 698d97b3072SJian Shen 699d97b3072SJian Shen if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 700d97b3072SJian Shen hash_sets |= HCLGEVF_V_TAG_BIT; 701d97b3072SJian Shen 702d97b3072SJian Shen return hash_sets; 703d97b3072SJian Shen } 704d97b3072SJian Shen 705d97b3072SJian Shen static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 706d97b3072SJian Shen struct ethtool_rxnfc *nfc) 707d97b3072SJian Shen { 708d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 709d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 710d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 711d97b3072SJian Shen struct hclgevf_desc desc; 712d97b3072SJian Shen u8 tuple_sets; 713d97b3072SJian Shen int ret; 714d97b3072SJian Shen 715d97b3072SJian Shen if (handle->pdev->revision == 0x20) 716d97b3072SJian Shen return -EOPNOTSUPP; 717d97b3072SJian Shen 718d97b3072SJian Shen if (nfc->data & 719d97b3072SJian Shen ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 720d97b3072SJian Shen return -EINVAL; 721d97b3072SJian Shen 722d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 723d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 724d97b3072SJian Shen 725d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 726d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 727d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 728d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 729d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 730d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 731d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 732d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 733d97b3072SJian Shen 734d97b3072SJian Shen tuple_sets = hclgevf_get_rss_hash_bits(nfc); 735d97b3072SJian Shen switch (nfc->flow_type) { 736d97b3072SJian Shen case TCP_V4_FLOW: 737d97b3072SJian Shen req->ipv4_tcp_en = tuple_sets; 738d97b3072SJian Shen break; 739d97b3072SJian Shen case TCP_V6_FLOW: 740d97b3072SJian Shen req->ipv6_tcp_en = tuple_sets; 741d97b3072SJian Shen break; 742d97b3072SJian Shen case UDP_V4_FLOW: 743d97b3072SJian Shen req->ipv4_udp_en = tuple_sets; 744d97b3072SJian Shen break; 745d97b3072SJian Shen case UDP_V6_FLOW: 746d97b3072SJian Shen req->ipv6_udp_en = tuple_sets; 747d97b3072SJian Shen break; 748d97b3072SJian Shen case SCTP_V4_FLOW: 749d97b3072SJian Shen req->ipv4_sctp_en = tuple_sets; 750d97b3072SJian Shen break; 751d97b3072SJian Shen case SCTP_V6_FLOW: 752d97b3072SJian Shen if ((nfc->data & RXH_L4_B_0_1) || 753d97b3072SJian Shen (nfc->data & RXH_L4_B_2_3)) 754d97b3072SJian Shen return -EINVAL; 755d97b3072SJian Shen 756d97b3072SJian Shen req->ipv6_sctp_en = tuple_sets; 757d97b3072SJian Shen break; 758d97b3072SJian Shen case IPV4_FLOW: 759d97b3072SJian Shen req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 760d97b3072SJian Shen break; 761d97b3072SJian Shen case IPV6_FLOW: 762d97b3072SJian Shen req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 763d97b3072SJian Shen break; 764d97b3072SJian Shen default: 765d97b3072SJian Shen return -EINVAL; 766d97b3072SJian Shen } 767d97b3072SJian Shen 768d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 769d97b3072SJian Shen if (ret) { 770d97b3072SJian Shen dev_err(&hdev->pdev->dev, 771d97b3072SJian Shen "Set rss tuple fail, status = %d\n", ret); 772d97b3072SJian Shen return ret; 773d97b3072SJian Shen } 774d97b3072SJian Shen 775d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 776d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 777d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 778d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 779d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 780d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 781d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 782d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 783d97b3072SJian Shen return 0; 784d97b3072SJian Shen } 785d97b3072SJian Shen 786d97b3072SJian Shen static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 787d97b3072SJian Shen struct ethtool_rxnfc *nfc) 788d97b3072SJian Shen { 789d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 790d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 791d97b3072SJian Shen u8 tuple_sets; 792d97b3072SJian Shen 793d97b3072SJian Shen if (handle->pdev->revision == 0x20) 794d97b3072SJian Shen return -EOPNOTSUPP; 795d97b3072SJian Shen 796d97b3072SJian Shen nfc->data = 0; 797d97b3072SJian Shen 798d97b3072SJian Shen switch (nfc->flow_type) { 799d97b3072SJian Shen case TCP_V4_FLOW: 800d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 801d97b3072SJian Shen break; 802d97b3072SJian Shen case UDP_V4_FLOW: 803d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 804d97b3072SJian Shen break; 805d97b3072SJian Shen case TCP_V6_FLOW: 806d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 807d97b3072SJian Shen break; 808d97b3072SJian Shen case UDP_V6_FLOW: 809d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 810d97b3072SJian Shen break; 811d97b3072SJian Shen case SCTP_V4_FLOW: 812d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 813d97b3072SJian Shen break; 814d97b3072SJian Shen case SCTP_V6_FLOW: 815d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 816d97b3072SJian Shen break; 817d97b3072SJian Shen case IPV4_FLOW: 818d97b3072SJian Shen case IPV6_FLOW: 819d97b3072SJian Shen tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 820d97b3072SJian Shen break; 821d97b3072SJian Shen default: 822d97b3072SJian Shen return -EINVAL; 823d97b3072SJian Shen } 824d97b3072SJian Shen 825d97b3072SJian Shen if (!tuple_sets) 826d97b3072SJian Shen return 0; 827d97b3072SJian Shen 828d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_PORT_BIT) 829d97b3072SJian Shen nfc->data |= RXH_L4_B_2_3; 830d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_PORT_BIT) 831d97b3072SJian Shen nfc->data |= RXH_L4_B_0_1; 832d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_IP_BIT) 833d97b3072SJian Shen nfc->data |= RXH_IP_DST; 834d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_IP_BIT) 835d97b3072SJian Shen nfc->data |= RXH_IP_SRC; 836d97b3072SJian Shen 837d97b3072SJian Shen return 0; 838d97b3072SJian Shen } 839d97b3072SJian Shen 840d97b3072SJian Shen static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 841d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg) 842d97b3072SJian Shen { 843d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 844d97b3072SJian Shen struct hclgevf_desc desc; 845d97b3072SJian Shen int ret; 846d97b3072SJian Shen 847d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 848d97b3072SJian Shen 849d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 850d97b3072SJian Shen 851d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 852d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 853d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 854d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 855d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 856d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 857d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 858d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 859d97b3072SJian Shen 860d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 861d97b3072SJian Shen if (ret) 862d97b3072SJian Shen dev_err(&hdev->pdev->dev, 863d97b3072SJian Shen "Configure rss input fail, status = %d\n", ret); 864d97b3072SJian Shen return ret; 865d97b3072SJian Shen } 866d97b3072SJian Shen 867e2cb1decSSalil Mehta static int hclgevf_get_tc_size(struct hnae3_handle *handle) 868e2cb1decSSalil Mehta { 869e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 870e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 871e2cb1decSSalil Mehta 872e2cb1decSSalil Mehta return rss_cfg->rss_size; 873e2cb1decSSalil Mehta } 874e2cb1decSSalil Mehta 875e2cb1decSSalil Mehta static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 876b204bc74SPeng Li int vector_id, 877e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 878e2cb1decSSalil Mehta { 879e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 880e2cb1decSSalil Mehta struct hnae3_ring_chain_node *node; 881e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 882e2cb1decSSalil Mehta struct hclgevf_desc desc; 883b204bc74SPeng Li int i = 0; 884e2cb1decSSalil Mehta int status; 885e2cb1decSSalil Mehta u8 type; 886e2cb1decSSalil Mehta 887e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 888e2cb1decSSalil Mehta 889e2cb1decSSalil Mehta for (node = ring_chain; node; node = node->next) { 8905d02a58dSYunsheng Lin int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 8915d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 8925d02a58dSYunsheng Lin 8935d02a58dSYunsheng Lin if (i == 0) { 8945d02a58dSYunsheng Lin hclgevf_cmd_setup_basic_desc(&desc, 8955d02a58dSYunsheng Lin HCLGEVF_OPC_MBX_VF_TO_PF, 8965d02a58dSYunsheng Lin false); 8975d02a58dSYunsheng Lin type = en ? 8985d02a58dSYunsheng Lin HCLGE_MBX_MAP_RING_TO_VECTOR : 8995d02a58dSYunsheng Lin HCLGE_MBX_UNMAP_RING_TO_VECTOR; 9005d02a58dSYunsheng Lin req->msg[0] = type; 9015d02a58dSYunsheng Lin req->msg[1] = vector_id; 9025d02a58dSYunsheng Lin } 9035d02a58dSYunsheng Lin 9045d02a58dSYunsheng Lin req->msg[idx_offset] = 905e4e87715SPeng Li hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 9065d02a58dSYunsheng Lin req->msg[idx_offset + 1] = node->tqp_index; 907e4e87715SPeng Li req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 90879eee410SFuyun Liang HNAE3_RING_GL_IDX_M, 90979eee410SFuyun Liang HNAE3_RING_GL_IDX_S); 91079eee410SFuyun Liang 9115d02a58dSYunsheng Lin i++; 9125d02a58dSYunsheng Lin if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 9135d02a58dSYunsheng Lin HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 9145d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 9155d02a58dSYunsheng Lin !node->next) { 916e2cb1decSSalil Mehta req->msg[2] = i; 917e2cb1decSSalil Mehta 918e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 919e2cb1decSSalil Mehta if (status) { 920e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 921e2cb1decSSalil Mehta "Map TQP fail, status is %d.\n", 922e2cb1decSSalil Mehta status); 923e2cb1decSSalil Mehta return status; 924e2cb1decSSalil Mehta } 925e2cb1decSSalil Mehta i = 0; 926e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 927e2cb1decSSalil Mehta HCLGEVF_OPC_MBX_VF_TO_PF, 928e2cb1decSSalil Mehta false); 929e2cb1decSSalil Mehta req->msg[0] = type; 930e2cb1decSSalil Mehta req->msg[1] = vector_id; 931e2cb1decSSalil Mehta } 932e2cb1decSSalil Mehta } 933e2cb1decSSalil Mehta 934e2cb1decSSalil Mehta return 0; 935e2cb1decSSalil Mehta } 936e2cb1decSSalil Mehta 937e2cb1decSSalil Mehta static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 938e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 939e2cb1decSSalil Mehta { 940b204bc74SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 941b204bc74SPeng Li int vector_id; 942b204bc74SPeng Li 943b204bc74SPeng Li vector_id = hclgevf_get_vector_index(hdev, vector); 944b204bc74SPeng Li if (vector_id < 0) { 945b204bc74SPeng Li dev_err(&handle->pdev->dev, 946b204bc74SPeng Li "Get vector index fail. ret =%d\n", vector_id); 947b204bc74SPeng Li return vector_id; 948b204bc74SPeng Li } 949b204bc74SPeng Li 950b204bc74SPeng Li return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 951e2cb1decSSalil Mehta } 952e2cb1decSSalil Mehta 953e2cb1decSSalil Mehta static int hclgevf_unmap_ring_from_vector( 954e2cb1decSSalil Mehta struct hnae3_handle *handle, 955e2cb1decSSalil Mehta int vector, 956e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 957e2cb1decSSalil Mehta { 958e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 959e2cb1decSSalil Mehta int ret, vector_id; 960e2cb1decSSalil Mehta 961dea846e8SHuazhong Tan if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 962dea846e8SHuazhong Tan return 0; 963dea846e8SHuazhong Tan 964e2cb1decSSalil Mehta vector_id = hclgevf_get_vector_index(hdev, vector); 965e2cb1decSSalil Mehta if (vector_id < 0) { 966e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 967e2cb1decSSalil Mehta "Get vector index fail. ret =%d\n", vector_id); 968e2cb1decSSalil Mehta return vector_id; 969e2cb1decSSalil Mehta } 970e2cb1decSSalil Mehta 971b204bc74SPeng Li ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 9720d3e6631SYunsheng Lin if (ret) 973e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 974e2cb1decSSalil Mehta "Unmap ring from vector fail. vector=%d, ret =%d\n", 975e2cb1decSSalil Mehta vector_id, 976e2cb1decSSalil Mehta ret); 9770d3e6631SYunsheng Lin 978e2cb1decSSalil Mehta return ret; 979e2cb1decSSalil Mehta } 980e2cb1decSSalil Mehta 9810d3e6631SYunsheng Lin static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 9820d3e6631SYunsheng Lin { 9830d3e6631SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 98403718db9SYunsheng Lin int vector_id; 9850d3e6631SYunsheng Lin 98603718db9SYunsheng Lin vector_id = hclgevf_get_vector_index(hdev, vector); 98703718db9SYunsheng Lin if (vector_id < 0) { 98803718db9SYunsheng Lin dev_err(&handle->pdev->dev, 98903718db9SYunsheng Lin "hclgevf_put_vector get vector index fail. ret =%d\n", 99003718db9SYunsheng Lin vector_id); 99103718db9SYunsheng Lin return vector_id; 99203718db9SYunsheng Lin } 99303718db9SYunsheng Lin 99403718db9SYunsheng Lin hclgevf_free_vector(hdev, vector_id); 995e2cb1decSSalil Mehta 996e2cb1decSSalil Mehta return 0; 997e2cb1decSSalil Mehta } 998e2cb1decSSalil Mehta 9993b75c3dfSPeng Li static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1000f01f5559SJian Shen bool en_bc_pmc) 1001e2cb1decSSalil Mehta { 1002e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 1003e2cb1decSSalil Mehta struct hclgevf_desc desc; 1004f01f5559SJian Shen int ret; 1005e2cb1decSSalil Mehta 1006e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1007e2cb1decSSalil Mehta 1008e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 1009e2cb1decSSalil Mehta req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 1010f01f5559SJian Shen req->msg[1] = en_bc_pmc ? 1 : 0; 1011e2cb1decSSalil Mehta 1012f01f5559SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1013f01f5559SJian Shen if (ret) 1014e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1015f01f5559SJian Shen "Set promisc mode fail, status is %d.\n", ret); 1016e2cb1decSSalil Mehta 1017f01f5559SJian Shen return ret; 1018e2cb1decSSalil Mehta } 1019e2cb1decSSalil Mehta 1020f01f5559SJian Shen static int hclgevf_set_promisc_mode(struct hclgevf_dev *hdev, bool en_bc_pmc) 1021e2cb1decSSalil Mehta { 1022f01f5559SJian Shen return hclgevf_cmd_set_promisc_mode(hdev, en_bc_pmc); 1023e2cb1decSSalil Mehta } 1024e2cb1decSSalil Mehta 1025e2cb1decSSalil Mehta static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, int tqp_id, 1026e2cb1decSSalil Mehta int stream_id, bool enable) 1027e2cb1decSSalil Mehta { 1028e2cb1decSSalil Mehta struct hclgevf_cfg_com_tqp_queue_cmd *req; 1029e2cb1decSSalil Mehta struct hclgevf_desc desc; 1030e2cb1decSSalil Mehta int status; 1031e2cb1decSSalil Mehta 1032e2cb1decSSalil Mehta req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1033e2cb1decSSalil Mehta 1034e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1035e2cb1decSSalil Mehta false); 1036e2cb1decSSalil Mehta req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1037e2cb1decSSalil Mehta req->stream_id = cpu_to_le16(stream_id); 1038e2cb1decSSalil Mehta req->enable |= enable << HCLGEVF_TQP_ENABLE_B; 1039e2cb1decSSalil Mehta 1040e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1041e2cb1decSSalil Mehta if (status) 1042e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1043e2cb1decSSalil Mehta "TQP enable fail, status =%d.\n", status); 1044e2cb1decSSalil Mehta 1045e2cb1decSSalil Mehta return status; 1046e2cb1decSSalil Mehta } 1047e2cb1decSSalil Mehta 1048e2cb1decSSalil Mehta static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1049e2cb1decSSalil Mehta { 1050b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1051e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 1052e2cb1decSSalil Mehta int i; 1053e2cb1decSSalil Mehta 1054b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 1055b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1056e2cb1decSSalil Mehta memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1057e2cb1decSSalil Mehta } 1058e2cb1decSSalil Mehta } 1059e2cb1decSSalil Mehta 1060e2cb1decSSalil Mehta static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1061e2cb1decSSalil Mehta { 1062e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1063e2cb1decSSalil Mehta 1064e2cb1decSSalil Mehta ether_addr_copy(p, hdev->hw.mac.mac_addr); 1065e2cb1decSSalil Mehta } 1066e2cb1decSSalil Mehta 106759098055SFuyun Liang static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 106859098055SFuyun Liang bool is_first) 1069e2cb1decSSalil Mehta { 1070e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1071e2cb1decSSalil Mehta u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1072e2cb1decSSalil Mehta u8 *new_mac_addr = (u8 *)p; 1073e2cb1decSSalil Mehta u8 msg_data[ETH_ALEN * 2]; 107459098055SFuyun Liang u16 subcode; 1075e2cb1decSSalil Mehta int status; 1076e2cb1decSSalil Mehta 1077e2cb1decSSalil Mehta ether_addr_copy(msg_data, new_mac_addr); 1078e2cb1decSSalil Mehta ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 1079e2cb1decSSalil Mehta 108059098055SFuyun Liang subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 108159098055SFuyun Liang HCLGE_MBX_MAC_VLAN_UC_MODIFY; 108259098055SFuyun Liang 1083e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 108459098055SFuyun Liang subcode, msg_data, ETH_ALEN * 2, 10852097fdefSJian Shen true, NULL, 0); 1086e2cb1decSSalil Mehta if (!status) 1087e2cb1decSSalil Mehta ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1088e2cb1decSSalil Mehta 1089e2cb1decSSalil Mehta return status; 1090e2cb1decSSalil Mehta } 1091e2cb1decSSalil Mehta 1092e2cb1decSSalil Mehta static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1093e2cb1decSSalil Mehta const unsigned char *addr) 1094e2cb1decSSalil Mehta { 1095e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1096e2cb1decSSalil Mehta 1097e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1098e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_ADD, 1099e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1100e2cb1decSSalil Mehta } 1101e2cb1decSSalil Mehta 1102e2cb1decSSalil Mehta static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1103e2cb1decSSalil Mehta const unsigned char *addr) 1104e2cb1decSSalil Mehta { 1105e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1106e2cb1decSSalil Mehta 1107e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1108e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1109e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1110e2cb1decSSalil Mehta } 1111e2cb1decSSalil Mehta 1112e2cb1decSSalil Mehta static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1113e2cb1decSSalil Mehta const unsigned char *addr) 1114e2cb1decSSalil Mehta { 1115e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1116e2cb1decSSalil Mehta 1117e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1118e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_ADD, 1119e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1120e2cb1decSSalil Mehta } 1121e2cb1decSSalil Mehta 1122e2cb1decSSalil Mehta static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1123e2cb1decSSalil Mehta const unsigned char *addr) 1124e2cb1decSSalil Mehta { 1125e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1126e2cb1decSSalil Mehta 1127e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1128e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1129e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1130e2cb1decSSalil Mehta } 1131e2cb1decSSalil Mehta 1132e2cb1decSSalil Mehta static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1133e2cb1decSSalil Mehta __be16 proto, u16 vlan_id, 1134e2cb1decSSalil Mehta bool is_kill) 1135e2cb1decSSalil Mehta { 1136e2cb1decSSalil Mehta #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1137e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1138e2cb1decSSalil Mehta u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1139e2cb1decSSalil Mehta 1140e2cb1decSSalil Mehta if (vlan_id > 4095) 1141e2cb1decSSalil Mehta return -EINVAL; 1142e2cb1decSSalil Mehta 1143e2cb1decSSalil Mehta if (proto != htons(ETH_P_8021Q)) 1144e2cb1decSSalil Mehta return -EPROTONOSUPPORT; 1145e2cb1decSSalil Mehta 1146e2cb1decSSalil Mehta msg_data[0] = is_kill; 1147e2cb1decSSalil Mehta memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1148e2cb1decSSalil Mehta memcpy(&msg_data[3], &proto, sizeof(proto)); 1149e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1150e2cb1decSSalil Mehta HCLGE_MBX_VLAN_FILTER, msg_data, 1151e2cb1decSSalil Mehta HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 1152e2cb1decSSalil Mehta } 1153e2cb1decSSalil Mehta 1154b2641e2aSYunsheng Lin static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1155b2641e2aSYunsheng Lin { 1156b2641e2aSYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1157b2641e2aSYunsheng Lin u8 msg_data; 1158b2641e2aSYunsheng Lin 1159b2641e2aSYunsheng Lin msg_data = enable ? 1 : 0; 1160b2641e2aSYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1161b2641e2aSYunsheng Lin HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1162b2641e2aSYunsheng Lin 1, false, NULL, 0); 1163b2641e2aSYunsheng Lin } 1164b2641e2aSYunsheng Lin 11657fa6be4fSHuazhong Tan static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1166e2cb1decSSalil Mehta { 1167e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1168e2cb1decSSalil Mehta u8 msg_data[2]; 11691a426f8bSPeng Li int ret; 1170e2cb1decSSalil Mehta 1171e2cb1decSSalil Mehta memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 1172e2cb1decSSalil Mehta 11731a426f8bSPeng Li /* disable vf queue before send queue reset msg to PF */ 11741a426f8bSPeng Li ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 11751a426f8bSPeng Li if (ret) 11767fa6be4fSHuazhong Tan return ret; 11771a426f8bSPeng Li 11787fa6be4fSHuazhong Tan return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 11791a426f8bSPeng Li 2, true, NULL, 0); 1180e2cb1decSSalil Mehta } 1181e2cb1decSSalil Mehta 1182818f1675SYunsheng Lin static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1183818f1675SYunsheng Lin { 1184818f1675SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1185818f1675SYunsheng Lin 1186818f1675SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu, 1187818f1675SYunsheng Lin sizeof(new_mtu), true, NULL, 0); 1188818f1675SYunsheng Lin } 1189818f1675SYunsheng Lin 11906988eb2aSSalil Mehta static int hclgevf_notify_client(struct hclgevf_dev *hdev, 11916988eb2aSSalil Mehta enum hnae3_reset_notify_type type) 11926988eb2aSSalil Mehta { 11936988eb2aSSalil Mehta struct hnae3_client *client = hdev->nic_client; 11946988eb2aSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 11956a5f6fa3SHuazhong Tan int ret; 11966988eb2aSSalil Mehta 11976988eb2aSSalil Mehta if (!client->ops->reset_notify) 11986988eb2aSSalil Mehta return -EOPNOTSUPP; 11996988eb2aSSalil Mehta 12006a5f6fa3SHuazhong Tan ret = client->ops->reset_notify(handle, type); 12016a5f6fa3SHuazhong Tan if (ret) 12026a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 12036a5f6fa3SHuazhong Tan type, ret); 12046a5f6fa3SHuazhong Tan 12056a5f6fa3SHuazhong Tan return ret; 12066988eb2aSSalil Mehta } 12076988eb2aSSalil Mehta 12086ff3cf07SHuazhong Tan static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 12096ff3cf07SHuazhong Tan { 12106ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 12116ff3cf07SHuazhong Tan 12126ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DONE, &hdev->flr_state); 12136ff3cf07SHuazhong Tan } 12146ff3cf07SHuazhong Tan 12156ff3cf07SHuazhong Tan static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev, 12166ff3cf07SHuazhong Tan unsigned long delay_us, 12176ff3cf07SHuazhong Tan unsigned long wait_cnt) 12186ff3cf07SHuazhong Tan { 12196ff3cf07SHuazhong Tan unsigned long cnt = 0; 12206ff3cf07SHuazhong Tan 12216ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) && 12226ff3cf07SHuazhong Tan cnt++ < wait_cnt) 12236ff3cf07SHuazhong Tan usleep_range(delay_us, delay_us * 2); 12246ff3cf07SHuazhong Tan 12256ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) { 12266ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 12276ff3cf07SHuazhong Tan "flr wait timeout\n"); 12286ff3cf07SHuazhong Tan return -ETIMEDOUT; 12296ff3cf07SHuazhong Tan } 12306ff3cf07SHuazhong Tan 12316ff3cf07SHuazhong Tan return 0; 12326ff3cf07SHuazhong Tan } 12336ff3cf07SHuazhong Tan 12346988eb2aSSalil Mehta static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 12356988eb2aSSalil Mehta { 1236aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_US 20000 1237aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_CNT 2000 1238aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1239aa5c4f17SHuazhong Tan (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1240aa5c4f17SHuazhong Tan 1241aa5c4f17SHuazhong Tan u32 val; 1242aa5c4f17SHuazhong Tan int ret; 12436988eb2aSSalil Mehta 12446988eb2aSSalil Mehta /* wait to check the hardware reset completion status */ 1245aa5c4f17SHuazhong Tan val = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1246aa5c4f17SHuazhong Tan dev_info(&hdev->pdev->dev, "checking vf resetting status: %x\n", val); 1247aa5c4f17SHuazhong Tan 12486ff3cf07SHuazhong Tan if (hdev->reset_type == HNAE3_FLR_RESET) 12496ff3cf07SHuazhong Tan return hclgevf_flr_poll_timeout(hdev, 12506ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_US, 12516ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_CNT); 12526ff3cf07SHuazhong Tan 1253aa5c4f17SHuazhong Tan ret = readl_poll_timeout(hdev->hw.io_base + HCLGEVF_RST_ING, val, 1254aa5c4f17SHuazhong Tan !(val & HCLGEVF_RST_ING_BITS), 1255aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_US, 1256aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 12576988eb2aSSalil Mehta 12586988eb2aSSalil Mehta /* hardware completion status should be available by this time */ 1259aa5c4f17SHuazhong Tan if (ret) { 1260aa5c4f17SHuazhong Tan dev_err(&hdev->pdev->dev, 12616988eb2aSSalil Mehta "could'nt get reset done status from h/w, timeout!\n"); 1262aa5c4f17SHuazhong Tan return ret; 12636988eb2aSSalil Mehta } 12646988eb2aSSalil Mehta 12656988eb2aSSalil Mehta /* we will wait a bit more to let reset of the stack to complete. This 12666988eb2aSSalil Mehta * might happen in case reset assertion was made by PF. Yes, this also 12676988eb2aSSalil Mehta * means we might end up waiting bit more even for VF reset. 12686988eb2aSSalil Mehta */ 12696988eb2aSSalil Mehta msleep(5000); 12706988eb2aSSalil Mehta 12716988eb2aSSalil Mehta return 0; 12726988eb2aSSalil Mehta } 12736988eb2aSSalil Mehta 12746988eb2aSSalil Mehta static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 12756988eb2aSSalil Mehta { 12767a01c897SSalil Mehta int ret; 12777a01c897SSalil Mehta 12786988eb2aSSalil Mehta /* uninitialize the nic client */ 12796a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 12806a5f6fa3SHuazhong Tan if (ret) 12816a5f6fa3SHuazhong Tan return ret; 12826988eb2aSSalil Mehta 12837a01c897SSalil Mehta /* re-initialize the hclge device */ 12849c6f7085SHuazhong Tan ret = hclgevf_reset_hdev(hdev); 12857a01c897SSalil Mehta if (ret) { 12867a01c897SSalil Mehta dev_err(&hdev->pdev->dev, 12877a01c897SSalil Mehta "hclge device re-init failed, VF is disabled!\n"); 12887a01c897SSalil Mehta return ret; 12897a01c897SSalil Mehta } 12906988eb2aSSalil Mehta 12916988eb2aSSalil Mehta /* bring up the nic client again */ 12926a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 12936a5f6fa3SHuazhong Tan if (ret) 12946a5f6fa3SHuazhong Tan return ret; 12956988eb2aSSalil Mehta 12961f609492SYunsheng Lin return hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT); 12976988eb2aSSalil Mehta } 12986988eb2aSSalil Mehta 1299dea846e8SHuazhong Tan static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1300dea846e8SHuazhong Tan { 1301dea846e8SHuazhong Tan int ret = 0; 1302dea846e8SHuazhong Tan 1303dea846e8SHuazhong Tan switch (hdev->reset_type) { 1304dea846e8SHuazhong Tan case HNAE3_VF_FUNC_RESET: 1305dea846e8SHuazhong Tan ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1306dea846e8SHuazhong Tan 0, true, NULL, sizeof(u8)); 1307dea846e8SHuazhong Tan break; 13086ff3cf07SHuazhong Tan case HNAE3_FLR_RESET: 13096ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 13106ff3cf07SHuazhong Tan break; 1311dea846e8SHuazhong Tan default: 1312dea846e8SHuazhong Tan break; 1313dea846e8SHuazhong Tan } 1314dea846e8SHuazhong Tan 1315ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1316ef5f8e50SHuazhong Tan 1317dea846e8SHuazhong Tan dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1318dea846e8SHuazhong Tan hdev->reset_type, ret); 1319dea846e8SHuazhong Tan 1320dea846e8SHuazhong Tan return ret; 1321dea846e8SHuazhong Tan } 1322dea846e8SHuazhong Tan 13236988eb2aSSalil Mehta static int hclgevf_reset(struct hclgevf_dev *hdev) 13246988eb2aSSalil Mehta { 1325dea846e8SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 13266988eb2aSSalil Mehta int ret; 13276988eb2aSSalil Mehta 1328dea846e8SHuazhong Tan /* Initialize ae_dev reset status as well, in case enet layer wants to 1329dea846e8SHuazhong Tan * know if device is undergoing reset 1330dea846e8SHuazhong Tan */ 1331dea846e8SHuazhong Tan ae_dev->reset_type = hdev->reset_type; 13324d60291bSHuazhong Tan hdev->reset_count++; 13336988eb2aSSalil Mehta rtnl_lock(); 13346988eb2aSSalil Mehta 13356988eb2aSSalil Mehta /* bring down the nic to stop any ongoing TX/RX */ 13366a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 13376a5f6fa3SHuazhong Tan if (ret) 13386a5f6fa3SHuazhong Tan goto err_reset_lock; 13396988eb2aSSalil Mehta 134029118ab9SHuazhong Tan rtnl_unlock(); 134129118ab9SHuazhong Tan 13426a5f6fa3SHuazhong Tan ret = hclgevf_reset_prepare_wait(hdev); 13436a5f6fa3SHuazhong Tan if (ret) 13446a5f6fa3SHuazhong Tan goto err_reset; 1345dea846e8SHuazhong Tan 13466988eb2aSSalil Mehta /* check if VF could successfully fetch the hardware reset completion 13476988eb2aSSalil Mehta * status from the hardware 13486988eb2aSSalil Mehta */ 13496988eb2aSSalil Mehta ret = hclgevf_reset_wait(hdev); 13506988eb2aSSalil Mehta if (ret) { 13516988eb2aSSalil Mehta /* can't do much in this situation, will disable VF */ 13526988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, 13536988eb2aSSalil Mehta "VF failed(=%d) to fetch H/W reset completion status\n", 13546988eb2aSSalil Mehta ret); 13556a5f6fa3SHuazhong Tan goto err_reset; 13566988eb2aSSalil Mehta } 13576988eb2aSSalil Mehta 135829118ab9SHuazhong Tan rtnl_lock(); 135929118ab9SHuazhong Tan 13606988eb2aSSalil Mehta /* now, re-initialize the nic client and ae device*/ 13616988eb2aSSalil Mehta ret = hclgevf_reset_stack(hdev); 13626a5f6fa3SHuazhong Tan if (ret) { 13636988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 13646a5f6fa3SHuazhong Tan goto err_reset_lock; 13656a5f6fa3SHuazhong Tan } 13666988eb2aSSalil Mehta 13676988eb2aSSalil Mehta /* bring up the nic to enable TX/RX again */ 13686a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 13696a5f6fa3SHuazhong Tan if (ret) 13706a5f6fa3SHuazhong Tan goto err_reset_lock; 13716988eb2aSSalil Mehta 13726988eb2aSSalil Mehta rtnl_unlock(); 13736988eb2aSSalil Mehta 1374b644a8d4SHuazhong Tan hdev->last_reset_time = jiffies; 1375b644a8d4SHuazhong Tan ae_dev->reset_type = HNAE3_NONE_RESET; 1376b644a8d4SHuazhong Tan 13776988eb2aSSalil Mehta return ret; 13786a5f6fa3SHuazhong Tan err_reset_lock: 13796a5f6fa3SHuazhong Tan rtnl_unlock(); 13806a5f6fa3SHuazhong Tan err_reset: 13816a5f6fa3SHuazhong Tan /* When VF reset failed, only the higher level reset asserted by PF 13826a5f6fa3SHuazhong Tan * can restore it, so re-initialize the command queue to receive 13836a5f6fa3SHuazhong Tan * this higher reset event. 13846a5f6fa3SHuazhong Tan */ 13856a5f6fa3SHuazhong Tan hclgevf_cmd_init(hdev); 13866a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "failed to reset VF\n"); 13876a5f6fa3SHuazhong Tan 13886a5f6fa3SHuazhong Tan return ret; 13896988eb2aSSalil Mehta } 13906988eb2aSSalil Mehta 1391720bd583SHuazhong Tan static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1392720bd583SHuazhong Tan unsigned long *addr) 1393720bd583SHuazhong Tan { 1394720bd583SHuazhong Tan enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1395720bd583SHuazhong Tan 1396dea846e8SHuazhong Tan /* return the highest priority reset level amongst all */ 1397b90fcc5bSHuazhong Tan if (test_bit(HNAE3_VF_RESET, addr)) { 1398b90fcc5bSHuazhong Tan rst_level = HNAE3_VF_RESET; 1399b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_RESET, addr); 1400b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1401b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1402b90fcc5bSHuazhong Tan } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1403dea846e8SHuazhong Tan rst_level = HNAE3_VF_FULL_RESET; 1404dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FULL_RESET, addr); 1405dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1406aa5c4f17SHuazhong Tan } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1407aa5c4f17SHuazhong Tan rst_level = HNAE3_VF_PF_FUNC_RESET; 1408aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1409aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1410dea846e8SHuazhong Tan } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1411dea846e8SHuazhong Tan rst_level = HNAE3_VF_FUNC_RESET; 1412dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 14136ff3cf07SHuazhong Tan } else if (test_bit(HNAE3_FLR_RESET, addr)) { 14146ff3cf07SHuazhong Tan rst_level = HNAE3_FLR_RESET; 14156ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_RESET, addr); 1416720bd583SHuazhong Tan } 1417720bd583SHuazhong Tan 1418720bd583SHuazhong Tan return rst_level; 1419720bd583SHuazhong Tan } 1420720bd583SHuazhong Tan 14216ae4e733SShiju Jose static void hclgevf_reset_event(struct pci_dev *pdev, 14226ae4e733SShiju Jose struct hnae3_handle *handle) 14236d4c3981SSalil Mehta { 14246ff3cf07SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 14256ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 14266d4c3981SSalil Mehta 14276d4c3981SSalil Mehta dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 14286d4c3981SSalil Mehta 14296ff3cf07SHuazhong Tan if (hdev->default_reset_request) 14300742ed7cSHuazhong Tan hdev->reset_level = 1431720bd583SHuazhong Tan hclgevf_get_reset_level(hdev, 1432720bd583SHuazhong Tan &hdev->default_reset_request); 1433720bd583SHuazhong Tan else 1434dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 14356d4c3981SSalil Mehta 1436436667d2SSalil Mehta /* reset of this VF requested */ 1437436667d2SSalil Mehta set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1438436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 14396d4c3981SSalil Mehta 14400742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 14416d4c3981SSalil Mehta } 14426d4c3981SSalil Mehta 1443720bd583SHuazhong Tan static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1444720bd583SHuazhong Tan enum hnae3_reset_type rst_type) 1445720bd583SHuazhong Tan { 1446720bd583SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1447720bd583SHuazhong Tan 1448720bd583SHuazhong Tan set_bit(rst_type, &hdev->default_reset_request); 1449720bd583SHuazhong Tan } 1450720bd583SHuazhong Tan 14516ff3cf07SHuazhong Tan static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 14526ff3cf07SHuazhong Tan { 14536ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_MS 100 14546ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_CNT 50 14556ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 14566ff3cf07SHuazhong Tan int cnt = 0; 14576ff3cf07SHuazhong Tan 14586ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 14596ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DONE, &hdev->flr_state); 14606ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request); 14616ff3cf07SHuazhong Tan hclgevf_reset_event(hdev->pdev, NULL); 14626ff3cf07SHuazhong Tan 14636ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) && 14646ff3cf07SHuazhong Tan cnt++ < HCLGEVF_FLR_WAIT_CNT) 14656ff3cf07SHuazhong Tan msleep(HCLGEVF_FLR_WAIT_MS); 14666ff3cf07SHuazhong Tan 14676ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state)) 14686ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 14696ff3cf07SHuazhong Tan "flr wait down timeout: %d\n", cnt); 14706ff3cf07SHuazhong Tan } 14716ff3cf07SHuazhong Tan 1472e2cb1decSSalil Mehta static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1473e2cb1decSSalil Mehta { 1474e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1475e2cb1decSSalil Mehta 1476e2cb1decSSalil Mehta return hdev->fw_version; 1477e2cb1decSSalil Mehta } 1478e2cb1decSSalil Mehta 1479e2cb1decSSalil Mehta static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1480e2cb1decSSalil Mehta { 1481e2cb1decSSalil Mehta struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1482e2cb1decSSalil Mehta 1483e2cb1decSSalil Mehta vector->vector_irq = pci_irq_vector(hdev->pdev, 1484e2cb1decSSalil Mehta HCLGEVF_MISC_VECTOR_NUM); 1485e2cb1decSSalil Mehta vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1486e2cb1decSSalil Mehta /* vector status always valid for Vector 0 */ 1487e2cb1decSSalil Mehta hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1488e2cb1decSSalil Mehta hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1489e2cb1decSSalil Mehta 1490e2cb1decSSalil Mehta hdev->num_msi_left -= 1; 1491e2cb1decSSalil Mehta hdev->num_msi_used += 1; 1492e2cb1decSSalil Mehta } 1493e2cb1decSSalil Mehta 149435a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 149535a1e503SSalil Mehta { 149635a1e503SSalil Mehta if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) && 149735a1e503SSalil Mehta !test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) { 149835a1e503SSalil Mehta set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 149935a1e503SSalil Mehta schedule_work(&hdev->rst_service_task); 150035a1e503SSalil Mehta } 150135a1e503SSalil Mehta } 150235a1e503SSalil Mehta 150307a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1504e2cb1decSSalil Mehta { 150507a0556aSSalil Mehta if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) && 150607a0556aSSalil Mehta !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) { 150707a0556aSSalil Mehta set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1508e2cb1decSSalil Mehta schedule_work(&hdev->mbx_service_task); 1509e2cb1decSSalil Mehta } 151007a0556aSSalil Mehta } 1511e2cb1decSSalil Mehta 1512e2cb1decSSalil Mehta static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 1513e2cb1decSSalil Mehta { 1514e2cb1decSSalil Mehta if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 1515e2cb1decSSalil Mehta !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 1516e2cb1decSSalil Mehta schedule_work(&hdev->service_task); 1517e2cb1decSSalil Mehta } 1518e2cb1decSSalil Mehta 1519436667d2SSalil Mehta static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev) 1520436667d2SSalil Mehta { 152107a0556aSSalil Mehta /* if we have any pending mailbox event then schedule the mbx task */ 152207a0556aSSalil Mehta if (hdev->mbx_event_pending) 152307a0556aSSalil Mehta hclgevf_mbx_task_schedule(hdev); 152407a0556aSSalil Mehta 1525436667d2SSalil Mehta if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state)) 1526436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 1527436667d2SSalil Mehta } 1528436667d2SSalil Mehta 1529e2cb1decSSalil Mehta static void hclgevf_service_timer(struct timer_list *t) 1530e2cb1decSSalil Mehta { 1531e2cb1decSSalil Mehta struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 1532e2cb1decSSalil Mehta 1533e2cb1decSSalil Mehta mod_timer(&hdev->service_timer, jiffies + 5 * HZ); 1534e2cb1decSSalil Mehta 1535e2cb1decSSalil Mehta hclgevf_task_schedule(hdev); 1536e2cb1decSSalil Mehta } 1537e2cb1decSSalil Mehta 153835a1e503SSalil Mehta static void hclgevf_reset_service_task(struct work_struct *work) 153935a1e503SSalil Mehta { 154035a1e503SSalil Mehta struct hclgevf_dev *hdev = 154135a1e503SSalil Mehta container_of(work, struct hclgevf_dev, rst_service_task); 1542a8dedb65SSalil Mehta int ret; 154335a1e503SSalil Mehta 154435a1e503SSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 154535a1e503SSalil Mehta return; 154635a1e503SSalil Mehta 154735a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 154835a1e503SSalil Mehta 1549436667d2SSalil Mehta if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1550436667d2SSalil Mehta &hdev->reset_state)) { 1551436667d2SSalil Mehta /* PF has initmated that it is about to reset the hardware. 1552436667d2SSalil Mehta * We now have to poll & check if harware has actually completed 1553436667d2SSalil Mehta * the reset sequence. On hardware reset completion, VF needs to 1554436667d2SSalil Mehta * reset the client and ae device. 155535a1e503SSalil Mehta */ 1556436667d2SSalil Mehta hdev->reset_attempts = 0; 1557436667d2SSalil Mehta 1558dea846e8SHuazhong Tan hdev->last_reset_time = jiffies; 1559dea846e8SHuazhong Tan while ((hdev->reset_type = 1560dea846e8SHuazhong Tan hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 1561dea846e8SHuazhong Tan != HNAE3_NONE_RESET) { 15626988eb2aSSalil Mehta ret = hclgevf_reset(hdev); 15636988eb2aSSalil Mehta if (ret) 1564dea846e8SHuazhong Tan dev_err(&hdev->pdev->dev, 1565dea846e8SHuazhong Tan "VF stack reset failed %d.\n", ret); 1566dea846e8SHuazhong Tan } 1567436667d2SSalil Mehta } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1568436667d2SSalil Mehta &hdev->reset_state)) { 1569436667d2SSalil Mehta /* we could be here when either of below happens: 1570436667d2SSalil Mehta * 1. reset was initiated due to watchdog timeout due to 1571436667d2SSalil Mehta * a. IMP was earlier reset and our TX got choked down and 1572436667d2SSalil Mehta * which resulted in watchdog reacting and inducing VF 1573436667d2SSalil Mehta * reset. This also means our cmdq would be unreliable. 1574436667d2SSalil Mehta * b. problem in TX due to other lower layer(example link 1575436667d2SSalil Mehta * layer not functioning properly etc.) 1576436667d2SSalil Mehta * 2. VF reset might have been initiated due to some config 1577436667d2SSalil Mehta * change. 1578436667d2SSalil Mehta * 1579436667d2SSalil Mehta * NOTE: Theres no clear way to detect above cases than to react 1580436667d2SSalil Mehta * to the response of PF for this reset request. PF will ack the 1581436667d2SSalil Mehta * 1b and 2. cases but we will not get any intimation about 1a 1582436667d2SSalil Mehta * from PF as cmdq would be in unreliable state i.e. mailbox 1583436667d2SSalil Mehta * communication between PF and VF would be broken. 1584436667d2SSalil Mehta */ 1585436667d2SSalil Mehta 1586436667d2SSalil Mehta /* if we are never geting into pending state it means either: 1587436667d2SSalil Mehta * 1. PF is not receiving our request which could be due to IMP 1588436667d2SSalil Mehta * reset 1589436667d2SSalil Mehta * 2. PF is screwed 1590436667d2SSalil Mehta * We cannot do much for 2. but to check first we can try reset 1591436667d2SSalil Mehta * our PCIe + stack and see if it alleviates the problem. 1592436667d2SSalil Mehta */ 1593436667d2SSalil Mehta if (hdev->reset_attempts > 3) { 1594436667d2SSalil Mehta /* prepare for full reset of stack + pcie interface */ 1595dea846e8SHuazhong Tan set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1596436667d2SSalil Mehta 1597436667d2SSalil Mehta /* "defer" schedule the reset task again */ 1598436667d2SSalil Mehta set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1599436667d2SSalil Mehta } else { 1600436667d2SSalil Mehta hdev->reset_attempts++; 1601436667d2SSalil Mehta 1602dea846e8SHuazhong Tan set_bit(hdev->reset_level, &hdev->reset_pending); 1603dea846e8SHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1604436667d2SSalil Mehta } 1605dea846e8SHuazhong Tan hclgevf_reset_task_schedule(hdev); 1606436667d2SSalil Mehta } 160735a1e503SSalil Mehta 160835a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 160935a1e503SSalil Mehta } 161035a1e503SSalil Mehta 1611e2cb1decSSalil Mehta static void hclgevf_mailbox_service_task(struct work_struct *work) 1612e2cb1decSSalil Mehta { 1613e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1614e2cb1decSSalil Mehta 1615e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 1616e2cb1decSSalil Mehta 1617e2cb1decSSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1618e2cb1decSSalil Mehta return; 1619e2cb1decSSalil Mehta 1620e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1621e2cb1decSSalil Mehta 162207a0556aSSalil Mehta hclgevf_mbx_async_handler(hdev); 1623e2cb1decSSalil Mehta 1624e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1625e2cb1decSSalil Mehta } 1626e2cb1decSSalil Mehta 1627a6d818e3SYunsheng Lin static void hclgevf_keep_alive_timer(struct timer_list *t) 1628a6d818e3SYunsheng Lin { 1629a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = from_timer(hdev, t, keep_alive_timer); 1630a6d818e3SYunsheng Lin 1631a6d818e3SYunsheng Lin schedule_work(&hdev->keep_alive_task); 1632a6d818e3SYunsheng Lin mod_timer(&hdev->keep_alive_timer, jiffies + 2 * HZ); 1633a6d818e3SYunsheng Lin } 1634a6d818e3SYunsheng Lin 1635a6d818e3SYunsheng Lin static void hclgevf_keep_alive_task(struct work_struct *work) 1636a6d818e3SYunsheng Lin { 1637a6d818e3SYunsheng Lin struct hclgevf_dev *hdev; 1638a6d818e3SYunsheng Lin u8 respmsg; 1639a6d818e3SYunsheng Lin int ret; 1640a6d818e3SYunsheng Lin 1641a6d818e3SYunsheng Lin hdev = container_of(work, struct hclgevf_dev, keep_alive_task); 1642c59a85c0SJian Shen 1643c59a85c0SJian Shen if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1644c59a85c0SJian Shen return; 1645c59a85c0SJian Shen 1646a6d818e3SYunsheng Lin ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL, 1647a6d818e3SYunsheng Lin 0, false, &respmsg, sizeof(u8)); 1648a6d818e3SYunsheng Lin if (ret) 1649a6d818e3SYunsheng Lin dev_err(&hdev->pdev->dev, 1650a6d818e3SYunsheng Lin "VF sends keep alive cmd failed(=%d)\n", ret); 1651a6d818e3SYunsheng Lin } 1652a6d818e3SYunsheng Lin 1653e2cb1decSSalil Mehta static void hclgevf_service_task(struct work_struct *work) 1654e2cb1decSSalil Mehta { 1655e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1656e2cb1decSSalil Mehta 1657e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, service_task); 1658e2cb1decSSalil Mehta 1659e2cb1decSSalil Mehta /* request the link status from the PF. PF would be able to tell VF 1660e2cb1decSSalil Mehta * about such updates in future so we might remove this later 1661e2cb1decSSalil Mehta */ 1662e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1663e2cb1decSSalil Mehta 16649194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 16659194d18bSliuzhongzhu 1666436667d2SSalil Mehta hclgevf_deferred_task_schedule(hdev); 1667436667d2SSalil Mehta 1668e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1669e2cb1decSSalil Mehta } 1670e2cb1decSSalil Mehta 1671e2cb1decSSalil Mehta static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1672e2cb1decSSalil Mehta { 1673e2cb1decSSalil Mehta hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1674e2cb1decSSalil Mehta } 1675e2cb1decSSalil Mehta 1676b90fcc5bSHuazhong Tan static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1677b90fcc5bSHuazhong Tan u32 *clearval) 1678e2cb1decSSalil Mehta { 1679b90fcc5bSHuazhong Tan u32 cmdq_src_reg, rst_ing_reg; 1680e2cb1decSSalil Mehta 1681e2cb1decSSalil Mehta /* fetch the events from their corresponding regs */ 1682e2cb1decSSalil Mehta cmdq_src_reg = hclgevf_read_dev(&hdev->hw, 1683e2cb1decSSalil Mehta HCLGEVF_VECTOR0_CMDQ_SRC_REG); 1684e2cb1decSSalil Mehta 1685b90fcc5bSHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_src_reg) { 1686b90fcc5bSHuazhong Tan rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1687b90fcc5bSHuazhong Tan dev_info(&hdev->pdev->dev, 1688b90fcc5bSHuazhong Tan "receive reset interrupt 0x%x!\n", rst_ing_reg); 1689b90fcc5bSHuazhong Tan set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1690b90fcc5bSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1691ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1692b90fcc5bSHuazhong Tan cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RST_INT_B); 1693b90fcc5bSHuazhong Tan *clearval = cmdq_src_reg; 1694b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_RST; 1695b90fcc5bSHuazhong Tan } 1696b90fcc5bSHuazhong Tan 1697e2cb1decSSalil Mehta /* check for vector0 mailbox(=CMDQ RX) event source */ 1698e2cb1decSSalil Mehta if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 1699e2cb1decSSalil Mehta cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1700e2cb1decSSalil Mehta *clearval = cmdq_src_reg; 1701b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_MBX; 1702e2cb1decSSalil Mehta } 1703e2cb1decSSalil Mehta 1704e2cb1decSSalil Mehta dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 1705e2cb1decSSalil Mehta 1706b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_OTHER; 1707e2cb1decSSalil Mehta } 1708e2cb1decSSalil Mehta 1709e2cb1decSSalil Mehta static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1710e2cb1decSSalil Mehta { 1711e2cb1decSSalil Mehta writel(en ? 1 : 0, vector->addr); 1712e2cb1decSSalil Mehta } 1713e2cb1decSSalil Mehta 1714e2cb1decSSalil Mehta static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1715e2cb1decSSalil Mehta { 1716b90fcc5bSHuazhong Tan enum hclgevf_evt_cause event_cause; 1717e2cb1decSSalil Mehta struct hclgevf_dev *hdev = data; 1718e2cb1decSSalil Mehta u32 clearval; 1719e2cb1decSSalil Mehta 1720e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 1721b90fcc5bSHuazhong Tan event_cause = hclgevf_check_evt_cause(hdev, &clearval); 1722e2cb1decSSalil Mehta 1723b90fcc5bSHuazhong Tan switch (event_cause) { 1724b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_RST: 1725b90fcc5bSHuazhong Tan hclgevf_reset_task_schedule(hdev); 1726b90fcc5bSHuazhong Tan break; 1727b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_MBX: 172807a0556aSSalil Mehta hclgevf_mbx_handler(hdev); 1729b90fcc5bSHuazhong Tan break; 1730b90fcc5bSHuazhong Tan default: 1731b90fcc5bSHuazhong Tan break; 1732b90fcc5bSHuazhong Tan } 1733e2cb1decSSalil Mehta 1734b90fcc5bSHuazhong Tan if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 1735e2cb1decSSalil Mehta hclgevf_clear_event_cause(hdev, clearval); 1736e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 1737b90fcc5bSHuazhong Tan } 1738e2cb1decSSalil Mehta 1739e2cb1decSSalil Mehta return IRQ_HANDLED; 1740e2cb1decSSalil Mehta } 1741e2cb1decSSalil Mehta 1742e2cb1decSSalil Mehta static int hclgevf_configure(struct hclgevf_dev *hdev) 1743e2cb1decSSalil Mehta { 1744e2cb1decSSalil Mehta int ret; 1745e2cb1decSSalil Mehta 1746e2cb1decSSalil Mehta /* get queue configuration from PF */ 17476cee6fc3SJian Shen ret = hclgevf_get_queue_info(hdev); 1748e2cb1decSSalil Mehta if (ret) 1749e2cb1decSSalil Mehta return ret; 1750e2cb1decSSalil Mehta /* get tc configuration from PF */ 1751e2cb1decSSalil Mehta return hclgevf_get_tc_info(hdev); 1752e2cb1decSSalil Mehta } 1753e2cb1decSSalil Mehta 17547a01c897SSalil Mehta static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 17557a01c897SSalil Mehta { 17567a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 17571154bb26SPeng Li struct hclgevf_dev *hdev; 17587a01c897SSalil Mehta 17597a01c897SSalil Mehta hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 17607a01c897SSalil Mehta if (!hdev) 17617a01c897SSalil Mehta return -ENOMEM; 17627a01c897SSalil Mehta 17637a01c897SSalil Mehta hdev->pdev = pdev; 17647a01c897SSalil Mehta hdev->ae_dev = ae_dev; 17657a01c897SSalil Mehta ae_dev->priv = hdev; 17667a01c897SSalil Mehta 17677a01c897SSalil Mehta return 0; 17687a01c897SSalil Mehta } 17697a01c897SSalil Mehta 1770e2cb1decSSalil Mehta static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 1771e2cb1decSSalil Mehta { 1772e2cb1decSSalil Mehta struct hnae3_handle *roce = &hdev->roce; 1773e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 1774e2cb1decSSalil Mehta 177507acf909SJian Shen roce->rinfo.num_vectors = hdev->num_roce_msix; 1776e2cb1decSSalil Mehta 1777e2cb1decSSalil Mehta if (hdev->num_msi_left < roce->rinfo.num_vectors || 1778e2cb1decSSalil Mehta hdev->num_msi_left == 0) 1779e2cb1decSSalil Mehta return -EINVAL; 1780e2cb1decSSalil Mehta 178107acf909SJian Shen roce->rinfo.base_vector = hdev->roce_base_vector; 1782e2cb1decSSalil Mehta 1783e2cb1decSSalil Mehta roce->rinfo.netdev = nic->kinfo.netdev; 1784e2cb1decSSalil Mehta roce->rinfo.roce_io_base = hdev->hw.io_base; 1785e2cb1decSSalil Mehta 1786e2cb1decSSalil Mehta roce->pdev = nic->pdev; 1787e2cb1decSSalil Mehta roce->ae_algo = nic->ae_algo; 1788e2cb1decSSalil Mehta roce->numa_node_mask = nic->numa_node_mask; 1789e2cb1decSSalil Mehta 1790e2cb1decSSalil Mehta return 0; 1791e2cb1decSSalil Mehta } 1792e2cb1decSSalil Mehta 1793b26a6feaSPeng Li static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 1794b26a6feaSPeng Li { 1795b26a6feaSPeng Li struct hclgevf_cfg_gro_status_cmd *req; 1796b26a6feaSPeng Li struct hclgevf_desc desc; 1797b26a6feaSPeng Li int ret; 1798b26a6feaSPeng Li 1799b26a6feaSPeng Li if (!hnae3_dev_gro_supported(hdev)) 1800b26a6feaSPeng Li return 0; 1801b26a6feaSPeng Li 1802b26a6feaSPeng Li hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 1803b26a6feaSPeng Li false); 1804b26a6feaSPeng Li req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 1805b26a6feaSPeng Li 1806b26a6feaSPeng Li req->gro_en = cpu_to_le16(en ? 1 : 0); 1807b26a6feaSPeng Li 1808b26a6feaSPeng Li ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1809b26a6feaSPeng Li if (ret) 1810b26a6feaSPeng Li dev_err(&hdev->pdev->dev, 1811b26a6feaSPeng Li "VF GRO hardware config cmd failed, ret = %d.\n", ret); 1812b26a6feaSPeng Li 1813b26a6feaSPeng Li return ret; 1814b26a6feaSPeng Li } 1815b26a6feaSPeng Li 1816e2cb1decSSalil Mehta static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 1817e2cb1decSSalil Mehta { 1818e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1819e2cb1decSSalil Mehta int i, ret; 1820e2cb1decSSalil Mehta 1821e2cb1decSSalil Mehta rss_cfg->rss_size = hdev->rss_size_max; 1822e2cb1decSSalil Mehta 1823374ad291SJian Shen if (hdev->pdev->revision >= 0x21) { 1824472d7eceSJian Shen rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 1825472d7eceSJian Shen memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 1826374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 1827374ad291SJian Shen 1828374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 1829374ad291SJian Shen rss_cfg->rss_hash_key); 1830374ad291SJian Shen if (ret) 1831374ad291SJian Shen return ret; 1832d97b3072SJian Shen 1833d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = 1834d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1835d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = 1836d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1837d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = 1838d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1839d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = 1840d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1841d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = 1842d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1843d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = 1844d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1845d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = 1846d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1847d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = 1848d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1849d97b3072SJian Shen 1850d97b3072SJian Shen ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 1851d97b3072SJian Shen if (ret) 1852d97b3072SJian Shen return ret; 1853d97b3072SJian Shen 1854374ad291SJian Shen } 1855374ad291SJian Shen 1856e2cb1decSSalil Mehta /* Initialize RSS indirect table for each vport */ 1857e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 1858e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max; 1859e2cb1decSSalil Mehta 1860e2cb1decSSalil Mehta ret = hclgevf_set_rss_indir_table(hdev); 1861e2cb1decSSalil Mehta if (ret) 1862e2cb1decSSalil Mehta return ret; 1863e2cb1decSSalil Mehta 1864e2cb1decSSalil Mehta return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max); 1865e2cb1decSSalil Mehta } 1866e2cb1decSSalil Mehta 1867e2cb1decSSalil Mehta static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 1868e2cb1decSSalil Mehta { 1869e2cb1decSSalil Mehta /* other vlan config(like, VLAN TX/RX offload) would also be added 1870e2cb1decSSalil Mehta * here later 1871e2cb1decSSalil Mehta */ 1872e2cb1decSSalil Mehta return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 1873e2cb1decSSalil Mehta false); 1874e2cb1decSSalil Mehta } 1875e2cb1decSSalil Mehta 18768cdb992fSJian Shen static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 18778cdb992fSJian Shen { 18788cdb992fSJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 18798cdb992fSJian Shen 18808cdb992fSJian Shen if (enable) { 18818cdb992fSJian Shen mod_timer(&hdev->service_timer, jiffies + HZ); 18828cdb992fSJian Shen } else { 18838cdb992fSJian Shen del_timer_sync(&hdev->service_timer); 18848cdb992fSJian Shen cancel_work_sync(&hdev->service_task); 18858cdb992fSJian Shen clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 18868cdb992fSJian Shen } 18878cdb992fSJian Shen } 18888cdb992fSJian Shen 1889e2cb1decSSalil Mehta static int hclgevf_ae_start(struct hnae3_handle *handle) 1890e2cb1decSSalil Mehta { 1891e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1892e2cb1decSSalil Mehta 1893e2cb1decSSalil Mehta /* reset tqp stats */ 1894e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 1895e2cb1decSSalil Mehta 1896e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1897e2cb1decSSalil Mehta 18989194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 18999194d18bSliuzhongzhu 1900e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1901e2cb1decSSalil Mehta 1902e2cb1decSSalil Mehta return 0; 1903e2cb1decSSalil Mehta } 1904e2cb1decSSalil Mehta 1905e2cb1decSSalil Mehta static void hclgevf_ae_stop(struct hnae3_handle *handle) 1906e2cb1decSSalil Mehta { 1907e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 190839cfbc9cSHuazhong Tan int i; 1909e2cb1decSSalil Mehta 19102f7e4896SFuyun Liang set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 19112f7e4896SFuyun Liang 191239cfbc9cSHuazhong Tan for (i = 0; i < handle->kinfo.num_tqps; i++) 191339cfbc9cSHuazhong Tan hclgevf_reset_tqp(handle, i); 191439cfbc9cSHuazhong Tan 1915e2cb1decSSalil Mehta /* reset tqp stats */ 1916e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 19178cc6c1f7SFuyun Liang hclgevf_update_link_status(hdev, 0); 1918e2cb1decSSalil Mehta } 1919e2cb1decSSalil Mehta 1920a6d818e3SYunsheng Lin static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 1921a6d818e3SYunsheng Lin { 1922a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1923a6d818e3SYunsheng Lin u8 msg_data; 1924a6d818e3SYunsheng Lin 1925a6d818e3SYunsheng Lin msg_data = alive ? 1 : 0; 1926a6d818e3SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE, 1927a6d818e3SYunsheng Lin 0, &msg_data, 1, false, NULL, 0); 1928a6d818e3SYunsheng Lin } 1929a6d818e3SYunsheng Lin 1930a6d818e3SYunsheng Lin static int hclgevf_client_start(struct hnae3_handle *handle) 1931a6d818e3SYunsheng Lin { 1932a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1933a6d818e3SYunsheng Lin 1934a6d818e3SYunsheng Lin mod_timer(&hdev->keep_alive_timer, jiffies + 2 * HZ); 1935a6d818e3SYunsheng Lin return hclgevf_set_alive(handle, true); 1936a6d818e3SYunsheng Lin } 1937a6d818e3SYunsheng Lin 1938a6d818e3SYunsheng Lin static void hclgevf_client_stop(struct hnae3_handle *handle) 1939a6d818e3SYunsheng Lin { 1940a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1941a6d818e3SYunsheng Lin int ret; 1942a6d818e3SYunsheng Lin 1943a6d818e3SYunsheng Lin ret = hclgevf_set_alive(handle, false); 1944a6d818e3SYunsheng Lin if (ret) 1945a6d818e3SYunsheng Lin dev_warn(&hdev->pdev->dev, 1946a6d818e3SYunsheng Lin "%s failed %d\n", __func__, ret); 1947a6d818e3SYunsheng Lin 1948a6d818e3SYunsheng Lin del_timer_sync(&hdev->keep_alive_timer); 1949a6d818e3SYunsheng Lin cancel_work_sync(&hdev->keep_alive_task); 1950a6d818e3SYunsheng Lin } 1951a6d818e3SYunsheng Lin 1952e2cb1decSSalil Mehta static void hclgevf_state_init(struct hclgevf_dev *hdev) 1953e2cb1decSSalil Mehta { 1954e2cb1decSSalil Mehta /* setup tasks for the MBX */ 1955e2cb1decSSalil Mehta INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 1956e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1957e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1958e2cb1decSSalil Mehta 1959e2cb1decSSalil Mehta /* setup tasks for service timer */ 1960e2cb1decSSalil Mehta timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 1961e2cb1decSSalil Mehta 1962e2cb1decSSalil Mehta INIT_WORK(&hdev->service_task, hclgevf_service_task); 1963e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1964e2cb1decSSalil Mehta 196535a1e503SSalil Mehta INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task); 196635a1e503SSalil Mehta 1967e2cb1decSSalil Mehta mutex_init(&hdev->mbx_resp.mbx_mutex); 1968e2cb1decSSalil Mehta 1969e2cb1decSSalil Mehta /* bring the device down */ 1970e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1971e2cb1decSSalil Mehta } 1972e2cb1decSSalil Mehta 1973e2cb1decSSalil Mehta static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 1974e2cb1decSSalil Mehta { 1975e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1976e2cb1decSSalil Mehta 1977e2cb1decSSalil Mehta if (hdev->service_timer.function) 1978e2cb1decSSalil Mehta del_timer_sync(&hdev->service_timer); 1979e2cb1decSSalil Mehta if (hdev->service_task.func) 1980e2cb1decSSalil Mehta cancel_work_sync(&hdev->service_task); 1981e2cb1decSSalil Mehta if (hdev->mbx_service_task.func) 1982e2cb1decSSalil Mehta cancel_work_sync(&hdev->mbx_service_task); 198335a1e503SSalil Mehta if (hdev->rst_service_task.func) 198435a1e503SSalil Mehta cancel_work_sync(&hdev->rst_service_task); 1985e2cb1decSSalil Mehta 1986e2cb1decSSalil Mehta mutex_destroy(&hdev->mbx_resp.mbx_mutex); 1987e2cb1decSSalil Mehta } 1988e2cb1decSSalil Mehta 1989e2cb1decSSalil Mehta static int hclgevf_init_msi(struct hclgevf_dev *hdev) 1990e2cb1decSSalil Mehta { 1991e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 1992e2cb1decSSalil Mehta int vectors; 1993e2cb1decSSalil Mehta int i; 1994e2cb1decSSalil Mehta 199507acf909SJian Shen if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) 199607acf909SJian Shen vectors = pci_alloc_irq_vectors(pdev, 199707acf909SJian Shen hdev->roce_base_msix_offset + 1, 199807acf909SJian Shen hdev->num_msi, 199907acf909SJian Shen PCI_IRQ_MSIX); 200007acf909SJian Shen else 2001e2cb1decSSalil Mehta vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 2002e2cb1decSSalil Mehta PCI_IRQ_MSI | PCI_IRQ_MSIX); 200307acf909SJian Shen 2004e2cb1decSSalil Mehta if (vectors < 0) { 2005e2cb1decSSalil Mehta dev_err(&pdev->dev, 2006e2cb1decSSalil Mehta "failed(%d) to allocate MSI/MSI-X vectors\n", 2007e2cb1decSSalil Mehta vectors); 2008e2cb1decSSalil Mehta return vectors; 2009e2cb1decSSalil Mehta } 2010e2cb1decSSalil Mehta if (vectors < hdev->num_msi) 2011e2cb1decSSalil Mehta dev_warn(&hdev->pdev->dev, 2012e2cb1decSSalil Mehta "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2013e2cb1decSSalil Mehta hdev->num_msi, vectors); 2014e2cb1decSSalil Mehta 2015e2cb1decSSalil Mehta hdev->num_msi = vectors; 2016e2cb1decSSalil Mehta hdev->num_msi_left = vectors; 2017e2cb1decSSalil Mehta hdev->base_msi_vector = pdev->irq; 201807acf909SJian Shen hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2019e2cb1decSSalil Mehta 2020e2cb1decSSalil Mehta hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2021e2cb1decSSalil Mehta sizeof(u16), GFP_KERNEL); 2022e2cb1decSSalil Mehta if (!hdev->vector_status) { 2023e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2024e2cb1decSSalil Mehta return -ENOMEM; 2025e2cb1decSSalil Mehta } 2026e2cb1decSSalil Mehta 2027e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 2028e2cb1decSSalil Mehta hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2029e2cb1decSSalil Mehta 2030e2cb1decSSalil Mehta hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2031e2cb1decSSalil Mehta sizeof(int), GFP_KERNEL); 2032e2cb1decSSalil Mehta if (!hdev->vector_irq) { 2033862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2034e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2035e2cb1decSSalil Mehta return -ENOMEM; 2036e2cb1decSSalil Mehta } 2037e2cb1decSSalil Mehta 2038e2cb1decSSalil Mehta return 0; 2039e2cb1decSSalil Mehta } 2040e2cb1decSSalil Mehta 2041e2cb1decSSalil Mehta static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2042e2cb1decSSalil Mehta { 2043e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2044e2cb1decSSalil Mehta 2045862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2046862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_irq); 2047e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2048e2cb1decSSalil Mehta } 2049e2cb1decSSalil Mehta 2050e2cb1decSSalil Mehta static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2051e2cb1decSSalil Mehta { 2052e2cb1decSSalil Mehta int ret = 0; 2053e2cb1decSSalil Mehta 2054e2cb1decSSalil Mehta hclgevf_get_misc_vector(hdev); 2055e2cb1decSSalil Mehta 2056e2cb1decSSalil Mehta ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2057e2cb1decSSalil Mehta 0, "hclgevf_cmd", hdev); 2058e2cb1decSSalil Mehta if (ret) { 2059e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2060e2cb1decSSalil Mehta hdev->misc_vector.vector_irq); 2061e2cb1decSSalil Mehta return ret; 2062e2cb1decSSalil Mehta } 2063e2cb1decSSalil Mehta 20641819e409SXi Wang hclgevf_clear_event_cause(hdev, 0); 20651819e409SXi Wang 2066e2cb1decSSalil Mehta /* enable misc. vector(vector 0) */ 2067e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2068e2cb1decSSalil Mehta 2069e2cb1decSSalil Mehta return ret; 2070e2cb1decSSalil Mehta } 2071e2cb1decSSalil Mehta 2072e2cb1decSSalil Mehta static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2073e2cb1decSSalil Mehta { 2074e2cb1decSSalil Mehta /* disable misc vector(vector 0) */ 2075e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 20761819e409SXi Wang synchronize_irq(hdev->misc_vector.vector_irq); 2077e2cb1decSSalil Mehta free_irq(hdev->misc_vector.vector_irq, hdev); 2078e2cb1decSSalil Mehta hclgevf_free_vector(hdev, 0); 2079e2cb1decSSalil Mehta } 2080e2cb1decSSalil Mehta 2081e718a93fSPeng Li static int hclgevf_init_client_instance(struct hnae3_client *client, 2082e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2083e2cb1decSSalil Mehta { 2084e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2085e2cb1decSSalil Mehta int ret; 2086e2cb1decSSalil Mehta 2087e2cb1decSSalil Mehta switch (client->type) { 2088e2cb1decSSalil Mehta case HNAE3_CLIENT_KNIC: 2089e2cb1decSSalil Mehta hdev->nic_client = client; 2090e2cb1decSSalil Mehta hdev->nic.client = client; 2091e2cb1decSSalil Mehta 2092e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->nic); 2093e2cb1decSSalil Mehta if (ret) 209449dd8054SJian Shen goto clear_nic; 2095e2cb1decSSalil Mehta 2096d9f28fc2SJian Shen hnae3_set_client_init_flag(client, ae_dev, 1); 2097d9f28fc2SJian Shen 2098e2cb1decSSalil Mehta if (hdev->roce_client && hnae3_dev_roce_supported(hdev)) { 2099e2cb1decSSalil Mehta struct hnae3_client *rc = hdev->roce_client; 2100e2cb1decSSalil Mehta 2101e2cb1decSSalil Mehta ret = hclgevf_init_roce_base_info(hdev); 2102e2cb1decSSalil Mehta if (ret) 210349dd8054SJian Shen goto clear_roce; 2104e2cb1decSSalil Mehta ret = rc->ops->init_instance(&hdev->roce); 2105e2cb1decSSalil Mehta if (ret) 210649dd8054SJian Shen goto clear_roce; 2107d9f28fc2SJian Shen 2108d9f28fc2SJian Shen hnae3_set_client_init_flag(hdev->roce_client, ae_dev, 2109d9f28fc2SJian Shen 1); 2110e2cb1decSSalil Mehta } 2111e2cb1decSSalil Mehta break; 2112e2cb1decSSalil Mehta case HNAE3_CLIENT_UNIC: 2113e2cb1decSSalil Mehta hdev->nic_client = client; 2114e2cb1decSSalil Mehta hdev->nic.client = client; 2115e2cb1decSSalil Mehta 2116e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->nic); 2117e2cb1decSSalil Mehta if (ret) 211849dd8054SJian Shen goto clear_nic; 2119d9f28fc2SJian Shen 2120d9f28fc2SJian Shen hnae3_set_client_init_flag(client, ae_dev, 1); 2121e2cb1decSSalil Mehta break; 2122e2cb1decSSalil Mehta case HNAE3_CLIENT_ROCE: 2123544a7bcdSLijun Ou if (hnae3_dev_roce_supported(hdev)) { 2124e2cb1decSSalil Mehta hdev->roce_client = client; 2125e2cb1decSSalil Mehta hdev->roce.client = client; 2126544a7bcdSLijun Ou } 2127e2cb1decSSalil Mehta 2128544a7bcdSLijun Ou if (hdev->roce_client && hdev->nic_client) { 2129e2cb1decSSalil Mehta ret = hclgevf_init_roce_base_info(hdev); 2130e2cb1decSSalil Mehta if (ret) 213149dd8054SJian Shen goto clear_roce; 2132e2cb1decSSalil Mehta 2133e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->roce); 2134e2cb1decSSalil Mehta if (ret) 213549dd8054SJian Shen goto clear_roce; 2136e2cb1decSSalil Mehta } 2137d9f28fc2SJian Shen 2138d9f28fc2SJian Shen hnae3_set_client_init_flag(client, ae_dev, 1); 2139fa7a4bd5SJian Shen break; 2140fa7a4bd5SJian Shen default: 2141fa7a4bd5SJian Shen return -EINVAL; 2142e2cb1decSSalil Mehta } 2143e2cb1decSSalil Mehta 2144e2cb1decSSalil Mehta return 0; 214549dd8054SJian Shen 214649dd8054SJian Shen clear_nic: 214749dd8054SJian Shen hdev->nic_client = NULL; 214849dd8054SJian Shen hdev->nic.client = NULL; 214949dd8054SJian Shen return ret; 215049dd8054SJian Shen clear_roce: 215149dd8054SJian Shen hdev->roce_client = NULL; 215249dd8054SJian Shen hdev->roce.client = NULL; 215349dd8054SJian Shen return ret; 2154e2cb1decSSalil Mehta } 2155e2cb1decSSalil Mehta 2156e718a93fSPeng Li static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2157e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2158e2cb1decSSalil Mehta { 2159e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2160e718a93fSPeng Li 2161e2cb1decSSalil Mehta /* un-init roce, if it exists */ 216249dd8054SJian Shen if (hdev->roce_client) { 2163e2cb1decSSalil Mehta hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 216449dd8054SJian Shen hdev->roce_client = NULL; 216549dd8054SJian Shen hdev->roce.client = NULL; 216649dd8054SJian Shen } 2167e2cb1decSSalil Mehta 2168e2cb1decSSalil Mehta /* un-init nic/unic, if this was not called by roce client */ 216949dd8054SJian Shen if (client->ops->uninit_instance && hdev->nic_client && 217049dd8054SJian Shen client->type != HNAE3_CLIENT_ROCE) { 2171e2cb1decSSalil Mehta client->ops->uninit_instance(&hdev->nic, 0); 217249dd8054SJian Shen hdev->nic_client = NULL; 217349dd8054SJian Shen hdev->nic.client = NULL; 217449dd8054SJian Shen } 2175e2cb1decSSalil Mehta } 2176e2cb1decSSalil Mehta 2177e2cb1decSSalil Mehta static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2178e2cb1decSSalil Mehta { 2179e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2180e2cb1decSSalil Mehta struct hclgevf_hw *hw; 2181e2cb1decSSalil Mehta int ret; 2182e2cb1decSSalil Mehta 2183e2cb1decSSalil Mehta ret = pci_enable_device(pdev); 2184e2cb1decSSalil Mehta if (ret) { 2185e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed to enable PCI device\n"); 21863e249d3bSFuyun Liang return ret; 2187e2cb1decSSalil Mehta } 2188e2cb1decSSalil Mehta 2189e2cb1decSSalil Mehta ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2190e2cb1decSSalil Mehta if (ret) { 2191e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2192e2cb1decSSalil Mehta goto err_disable_device; 2193e2cb1decSSalil Mehta } 2194e2cb1decSSalil Mehta 2195e2cb1decSSalil Mehta ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2196e2cb1decSSalil Mehta if (ret) { 2197e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2198e2cb1decSSalil Mehta goto err_disable_device; 2199e2cb1decSSalil Mehta } 2200e2cb1decSSalil Mehta 2201e2cb1decSSalil Mehta pci_set_master(pdev); 2202e2cb1decSSalil Mehta hw = &hdev->hw; 2203e2cb1decSSalil Mehta hw->hdev = hdev; 22042e1ea493SPeng Li hw->io_base = pci_iomap(pdev, 2, 0); 2205e2cb1decSSalil Mehta if (!hw->io_base) { 2206e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't map configuration register space\n"); 2207e2cb1decSSalil Mehta ret = -ENOMEM; 2208e2cb1decSSalil Mehta goto err_clr_master; 2209e2cb1decSSalil Mehta } 2210e2cb1decSSalil Mehta 2211e2cb1decSSalil Mehta return 0; 2212e2cb1decSSalil Mehta 2213e2cb1decSSalil Mehta err_clr_master: 2214e2cb1decSSalil Mehta pci_clear_master(pdev); 2215e2cb1decSSalil Mehta pci_release_regions(pdev); 2216e2cb1decSSalil Mehta err_disable_device: 2217e2cb1decSSalil Mehta pci_disable_device(pdev); 22183e249d3bSFuyun Liang 2219e2cb1decSSalil Mehta return ret; 2220e2cb1decSSalil Mehta } 2221e2cb1decSSalil Mehta 2222e2cb1decSSalil Mehta static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2223e2cb1decSSalil Mehta { 2224e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2225e2cb1decSSalil Mehta 2226e2cb1decSSalil Mehta pci_iounmap(pdev, hdev->hw.io_base); 2227e2cb1decSSalil Mehta pci_clear_master(pdev); 2228e2cb1decSSalil Mehta pci_release_regions(pdev); 2229e2cb1decSSalil Mehta pci_disable_device(pdev); 2230e2cb1decSSalil Mehta } 2231e2cb1decSSalil Mehta 223207acf909SJian Shen static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 223307acf909SJian Shen { 223407acf909SJian Shen struct hclgevf_query_res_cmd *req; 223507acf909SJian Shen struct hclgevf_desc desc; 223607acf909SJian Shen int ret; 223707acf909SJian Shen 223807acf909SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 223907acf909SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 224007acf909SJian Shen if (ret) { 224107acf909SJian Shen dev_err(&hdev->pdev->dev, 224207acf909SJian Shen "query vf resource failed, ret = %d.\n", ret); 224307acf909SJian Shen return ret; 224407acf909SJian Shen } 224507acf909SJian Shen 224607acf909SJian Shen req = (struct hclgevf_query_res_cmd *)desc.data; 224707acf909SJian Shen 224807acf909SJian Shen if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) { 224907acf909SJian Shen hdev->roce_base_msix_offset = 225007acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 225107acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_M, 225207acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_S); 225307acf909SJian Shen hdev->num_roce_msix = 225407acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 225507acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 225607acf909SJian Shen 225707acf909SJian Shen /* VF should have NIC vectors and Roce vectors, NIC vectors 225807acf909SJian Shen * are queued before Roce vectors. The offset is fixed to 64. 225907acf909SJian Shen */ 226007acf909SJian Shen hdev->num_msi = hdev->num_roce_msix + 226107acf909SJian Shen hdev->roce_base_msix_offset; 226207acf909SJian Shen } else { 226307acf909SJian Shen hdev->num_msi = 226407acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 226507acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 226607acf909SJian Shen } 226707acf909SJian Shen 226807acf909SJian Shen return 0; 226907acf909SJian Shen } 227007acf909SJian Shen 2271862d969aSHuazhong Tan static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2272862d969aSHuazhong Tan { 2273862d969aSHuazhong Tan struct pci_dev *pdev = hdev->pdev; 2274862d969aSHuazhong Tan int ret = 0; 2275862d969aSHuazhong Tan 2276862d969aSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2277862d969aSHuazhong Tan test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2278862d969aSHuazhong Tan hclgevf_misc_irq_uninit(hdev); 2279862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2280862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2281862d969aSHuazhong Tan } 2282862d969aSHuazhong Tan 2283862d969aSHuazhong Tan if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2284862d969aSHuazhong Tan pci_set_master(pdev); 2285862d969aSHuazhong Tan ret = hclgevf_init_msi(hdev); 2286862d969aSHuazhong Tan if (ret) { 2287862d969aSHuazhong Tan dev_err(&pdev->dev, 2288862d969aSHuazhong Tan "failed(%d) to init MSI/MSI-X\n", ret); 2289862d969aSHuazhong Tan return ret; 2290862d969aSHuazhong Tan } 2291862d969aSHuazhong Tan 2292862d969aSHuazhong Tan ret = hclgevf_misc_irq_init(hdev); 2293862d969aSHuazhong Tan if (ret) { 2294862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2295862d969aSHuazhong Tan dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2296862d969aSHuazhong Tan ret); 2297862d969aSHuazhong Tan return ret; 2298862d969aSHuazhong Tan } 2299862d969aSHuazhong Tan 2300862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2301862d969aSHuazhong Tan } 2302862d969aSHuazhong Tan 2303862d969aSHuazhong Tan return ret; 2304862d969aSHuazhong Tan } 2305862d969aSHuazhong Tan 23069c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2307e2cb1decSSalil Mehta { 23087a01c897SSalil Mehta struct pci_dev *pdev = hdev->pdev; 2309e2cb1decSSalil Mehta int ret; 2310e2cb1decSSalil Mehta 2311862d969aSHuazhong Tan ret = hclgevf_pci_reset(hdev); 2312862d969aSHuazhong Tan if (ret) { 2313862d969aSHuazhong Tan dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2314862d969aSHuazhong Tan return ret; 2315862d969aSHuazhong Tan } 2316862d969aSHuazhong Tan 23179c6f7085SHuazhong Tan ret = hclgevf_cmd_init(hdev); 23189c6f7085SHuazhong Tan if (ret) { 23199c6f7085SHuazhong Tan dev_err(&pdev->dev, "cmd failed %d\n", ret); 23209c6f7085SHuazhong Tan return ret; 23217a01c897SSalil Mehta } 2322e2cb1decSSalil Mehta 23239c6f7085SHuazhong Tan ret = hclgevf_rss_init_hw(hdev); 23249c6f7085SHuazhong Tan if (ret) { 23259c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 23269c6f7085SHuazhong Tan "failed(%d) to initialize RSS\n", ret); 23279c6f7085SHuazhong Tan return ret; 23289c6f7085SHuazhong Tan } 23299c6f7085SHuazhong Tan 2330b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2331b26a6feaSPeng Li if (ret) 2332b26a6feaSPeng Li return ret; 2333b26a6feaSPeng Li 23349c6f7085SHuazhong Tan ret = hclgevf_init_vlan_config(hdev); 23359c6f7085SHuazhong Tan if (ret) { 23369c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 23379c6f7085SHuazhong Tan "failed(%d) to initialize VLAN config\n", ret); 23389c6f7085SHuazhong Tan return ret; 23399c6f7085SHuazhong Tan } 23409c6f7085SHuazhong Tan 23419c6f7085SHuazhong Tan dev_info(&hdev->pdev->dev, "Reset done\n"); 23429c6f7085SHuazhong Tan 23439c6f7085SHuazhong Tan return 0; 23449c6f7085SHuazhong Tan } 23459c6f7085SHuazhong Tan 23469c6f7085SHuazhong Tan static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 23479c6f7085SHuazhong Tan { 23489c6f7085SHuazhong Tan struct pci_dev *pdev = hdev->pdev; 23499c6f7085SHuazhong Tan int ret; 23509c6f7085SHuazhong Tan 2351e2cb1decSSalil Mehta ret = hclgevf_pci_init(hdev); 2352e2cb1decSSalil Mehta if (ret) { 2353e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI initialization failed\n"); 2354e2cb1decSSalil Mehta return ret; 2355e2cb1decSSalil Mehta } 2356e2cb1decSSalil Mehta 23578b0195a3SHuazhong Tan ret = hclgevf_cmd_queue_init(hdev); 23588b0195a3SHuazhong Tan if (ret) { 23598b0195a3SHuazhong Tan dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret); 23608b0195a3SHuazhong Tan goto err_cmd_queue_init; 23618b0195a3SHuazhong Tan } 23628b0195a3SHuazhong Tan 2363eddf0462SYunsheng Lin ret = hclgevf_cmd_init(hdev); 2364eddf0462SYunsheng Lin if (ret) 2365eddf0462SYunsheng Lin goto err_cmd_init; 2366eddf0462SYunsheng Lin 236707acf909SJian Shen /* Get vf resource */ 236807acf909SJian Shen ret = hclgevf_query_vf_resource(hdev); 236907acf909SJian Shen if (ret) { 237007acf909SJian Shen dev_err(&hdev->pdev->dev, 237107acf909SJian Shen "Query vf status error, ret = %d.\n", ret); 23728b0195a3SHuazhong Tan goto err_cmd_init; 237307acf909SJian Shen } 237407acf909SJian Shen 237507acf909SJian Shen ret = hclgevf_init_msi(hdev); 237607acf909SJian Shen if (ret) { 237707acf909SJian Shen dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 23788b0195a3SHuazhong Tan goto err_cmd_init; 237907acf909SJian Shen } 238007acf909SJian Shen 238107acf909SJian Shen hclgevf_state_init(hdev); 2382dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 238307acf909SJian Shen 2384e2cb1decSSalil Mehta ret = hclgevf_misc_irq_init(hdev); 2385e2cb1decSSalil Mehta if (ret) { 2386e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2387e2cb1decSSalil Mehta ret); 2388e2cb1decSSalil Mehta goto err_misc_irq_init; 2389e2cb1decSSalil Mehta } 2390e2cb1decSSalil Mehta 2391862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2392862d969aSHuazhong Tan 2393e2cb1decSSalil Mehta ret = hclgevf_configure(hdev); 2394e2cb1decSSalil Mehta if (ret) { 2395e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2396e2cb1decSSalil Mehta goto err_config; 2397e2cb1decSSalil Mehta } 2398e2cb1decSSalil Mehta 2399e2cb1decSSalil Mehta ret = hclgevf_alloc_tqps(hdev); 2400e2cb1decSSalil Mehta if (ret) { 2401e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2402e2cb1decSSalil Mehta goto err_config; 2403e2cb1decSSalil Mehta } 2404e2cb1decSSalil Mehta 2405e2cb1decSSalil Mehta ret = hclgevf_set_handle_info(hdev); 2406e2cb1decSSalil Mehta if (ret) { 2407e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 2408e2cb1decSSalil Mehta goto err_config; 2409e2cb1decSSalil Mehta } 2410e2cb1decSSalil Mehta 2411b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2412b26a6feaSPeng Li if (ret) 2413b26a6feaSPeng Li goto err_config; 2414b26a6feaSPeng Li 2415f01f5559SJian Shen /* vf is not allowed to enable unicast/multicast promisc mode. 2416f01f5559SJian Shen * For revision 0x20, default to disable broadcast promisc mode, 2417f01f5559SJian Shen * firmware makes sure broadcast packets can be accepted. 2418f01f5559SJian Shen * For revision 0x21, default to enable broadcast promisc mode. 2419f01f5559SJian Shen */ 2420f01f5559SJian Shen ret = hclgevf_set_promisc_mode(hdev, true); 2421f01f5559SJian Shen if (ret) 2422f01f5559SJian Shen goto err_config; 2423f01f5559SJian Shen 2424e2cb1decSSalil Mehta /* Initialize RSS for this VF */ 2425e2cb1decSSalil Mehta ret = hclgevf_rss_init_hw(hdev); 2426e2cb1decSSalil Mehta if (ret) { 2427e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2428e2cb1decSSalil Mehta "failed(%d) to initialize RSS\n", ret); 2429e2cb1decSSalil Mehta goto err_config; 2430e2cb1decSSalil Mehta } 2431e2cb1decSSalil Mehta 2432e2cb1decSSalil Mehta ret = hclgevf_init_vlan_config(hdev); 2433e2cb1decSSalil Mehta if (ret) { 2434e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2435e2cb1decSSalil Mehta "failed(%d) to initialize VLAN config\n", ret); 2436e2cb1decSSalil Mehta goto err_config; 2437e2cb1decSSalil Mehta } 2438e2cb1decSSalil Mehta 24390742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 2440e2cb1decSSalil Mehta pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME); 2441e2cb1decSSalil Mehta 2442e2cb1decSSalil Mehta return 0; 2443e2cb1decSSalil Mehta 2444e2cb1decSSalil Mehta err_config: 2445e2cb1decSSalil Mehta hclgevf_misc_irq_uninit(hdev); 2446e2cb1decSSalil Mehta err_misc_irq_init: 2447e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2448e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 244907acf909SJian Shen err_cmd_init: 24508b0195a3SHuazhong Tan hclgevf_cmd_uninit(hdev); 24518b0195a3SHuazhong Tan err_cmd_queue_init: 2452e2cb1decSSalil Mehta hclgevf_pci_uninit(hdev); 2453862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2454e2cb1decSSalil Mehta return ret; 2455e2cb1decSSalil Mehta } 2456e2cb1decSSalil Mehta 24577a01c897SSalil Mehta static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2458e2cb1decSSalil Mehta { 2459e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2460862d969aSHuazhong Tan 2461862d969aSHuazhong Tan if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2462eddf0462SYunsheng Lin hclgevf_misc_irq_uninit(hdev); 2463e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 24647a01c897SSalil Mehta } 24657a01c897SSalil Mehta 2466e3338205SHuazhong Tan hclgevf_pci_uninit(hdev); 2467862d969aSHuazhong Tan hclgevf_cmd_uninit(hdev); 2468862d969aSHuazhong Tan } 2469862d969aSHuazhong Tan 24707a01c897SSalil Mehta static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 24717a01c897SSalil Mehta { 24727a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 2473a6d818e3SYunsheng Lin struct hclgevf_dev *hdev; 24747a01c897SSalil Mehta int ret; 24757a01c897SSalil Mehta 24767a01c897SSalil Mehta ret = hclgevf_alloc_hdev(ae_dev); 24777a01c897SSalil Mehta if (ret) { 24787a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device allocation failed\n"); 24797a01c897SSalil Mehta return ret; 24807a01c897SSalil Mehta } 24817a01c897SSalil Mehta 24827a01c897SSalil Mehta ret = hclgevf_init_hdev(ae_dev->priv); 2483a6d818e3SYunsheng Lin if (ret) { 24847a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device initialization failed\n"); 24857a01c897SSalil Mehta return ret; 24867a01c897SSalil Mehta } 24877a01c897SSalil Mehta 2488a6d818e3SYunsheng Lin hdev = ae_dev->priv; 2489a6d818e3SYunsheng Lin timer_setup(&hdev->keep_alive_timer, hclgevf_keep_alive_timer, 0); 2490a6d818e3SYunsheng Lin INIT_WORK(&hdev->keep_alive_task, hclgevf_keep_alive_task); 2491a6d818e3SYunsheng Lin 2492a6d818e3SYunsheng Lin return 0; 2493a6d818e3SYunsheng Lin } 2494a6d818e3SYunsheng Lin 24957a01c897SSalil Mehta static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 24967a01c897SSalil Mehta { 24977a01c897SSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 24987a01c897SSalil Mehta 24997a01c897SSalil Mehta hclgevf_uninit_hdev(hdev); 2500e2cb1decSSalil Mehta ae_dev->priv = NULL; 2501e2cb1decSSalil Mehta } 2502e2cb1decSSalil Mehta 2503849e4607SPeng Li static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2504849e4607SPeng Li { 2505849e4607SPeng Li struct hnae3_handle *nic = &hdev->nic; 2506849e4607SPeng Li struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2507849e4607SPeng Li 25088be73621SHuazhong Tan return min_t(u32, hdev->rss_size_max, 25098be73621SHuazhong Tan hdev->num_tqps / kinfo->num_tc); 2510849e4607SPeng Li } 2511849e4607SPeng Li 2512849e4607SPeng Li /** 2513849e4607SPeng Li * hclgevf_get_channels - Get the current channels enabled and max supported. 2514849e4607SPeng Li * @handle: hardware information for network interface 2515849e4607SPeng Li * @ch: ethtool channels structure 2516849e4607SPeng Li * 2517849e4607SPeng Li * We don't support separate tx and rx queues as channels. The other count 2518849e4607SPeng Li * represents how many queues are being used for control. max_combined counts 2519849e4607SPeng Li * how many queue pairs we can support. They may not be mapped 1 to 1 with 2520849e4607SPeng Li * q_vectors since we support a lot more queue pairs than q_vectors. 2521849e4607SPeng Li **/ 2522849e4607SPeng Li static void hclgevf_get_channels(struct hnae3_handle *handle, 2523849e4607SPeng Li struct ethtool_channels *ch) 2524849e4607SPeng Li { 2525849e4607SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2526849e4607SPeng Li 2527849e4607SPeng Li ch->max_combined = hclgevf_get_max_channels(hdev); 2528849e4607SPeng Li ch->other_count = 0; 2529849e4607SPeng Li ch->max_other = 0; 25308be73621SHuazhong Tan ch->combined_count = handle->kinfo.rss_size; 2531849e4607SPeng Li } 2532849e4607SPeng Li 2533cc719218SPeng Li static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 25340d43bf45SHuazhong Tan u16 *alloc_tqps, u16 *max_rss_size) 2535cc719218SPeng Li { 2536cc719218SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2537cc719218SPeng Li 25380d43bf45SHuazhong Tan *alloc_tqps = hdev->num_tqps; 2539cc719218SPeng Li *max_rss_size = hdev->rss_size_max; 2540cc719218SPeng Li } 2541cc719218SPeng Li 2542175ec96bSFuyun Liang static int hclgevf_get_status(struct hnae3_handle *handle) 2543175ec96bSFuyun Liang { 2544175ec96bSFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2545175ec96bSFuyun Liang 2546175ec96bSFuyun Liang return hdev->hw.mac.link; 2547175ec96bSFuyun Liang } 2548175ec96bSFuyun Liang 25494a152de9SFuyun Liang static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 25504a152de9SFuyun Liang u8 *auto_neg, u32 *speed, 25514a152de9SFuyun Liang u8 *duplex) 25524a152de9SFuyun Liang { 25534a152de9SFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 25544a152de9SFuyun Liang 25554a152de9SFuyun Liang if (speed) 25564a152de9SFuyun Liang *speed = hdev->hw.mac.speed; 25574a152de9SFuyun Liang if (duplex) 25584a152de9SFuyun Liang *duplex = hdev->hw.mac.duplex; 25594a152de9SFuyun Liang if (auto_neg) 25604a152de9SFuyun Liang *auto_neg = AUTONEG_DISABLE; 25614a152de9SFuyun Liang } 25624a152de9SFuyun Liang 25634a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 25644a152de9SFuyun Liang u8 duplex) 25654a152de9SFuyun Liang { 25664a152de9SFuyun Liang hdev->hw.mac.speed = speed; 25674a152de9SFuyun Liang hdev->hw.mac.duplex = duplex; 25684a152de9SFuyun Liang } 25694a152de9SFuyun Liang 25701731be4cSYonglong Liu static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 25715c9f6b39SPeng Li { 25725c9f6b39SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 25735c9f6b39SPeng Li 25745c9f6b39SPeng Li return hclgevf_config_gro(hdev, enable); 25755c9f6b39SPeng Li } 25765c9f6b39SPeng Li 2577c136b884SPeng Li static void hclgevf_get_media_type(struct hnae3_handle *handle, 2578c136b884SPeng Li u8 *media_type) 2579c136b884SPeng Li { 2580c136b884SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2581c136b884SPeng Li if (media_type) 2582c136b884SPeng Li *media_type = hdev->hw.mac.media_type; 2583c136b884SPeng Li } 2584c136b884SPeng Li 25854d60291bSHuazhong Tan static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 25864d60291bSHuazhong Tan { 25874d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 25884d60291bSHuazhong Tan 2589aa5c4f17SHuazhong Tan return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 25904d60291bSHuazhong Tan } 25914d60291bSHuazhong Tan 25924d60291bSHuazhong Tan static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 25934d60291bSHuazhong Tan { 25944d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 25954d60291bSHuazhong Tan 25964d60291bSHuazhong Tan return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 25974d60291bSHuazhong Tan } 25984d60291bSHuazhong Tan 25994d60291bSHuazhong Tan static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 26004d60291bSHuazhong Tan { 26014d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 26024d60291bSHuazhong Tan 26034d60291bSHuazhong Tan return hdev->reset_count; 26044d60291bSHuazhong Tan } 26054d60291bSHuazhong Tan 26069194d18bSliuzhongzhu static void hclgevf_get_link_mode(struct hnae3_handle *handle, 26079194d18bSliuzhongzhu unsigned long *supported, 26089194d18bSliuzhongzhu unsigned long *advertising) 26099194d18bSliuzhongzhu { 26109194d18bSliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 26119194d18bSliuzhongzhu 26129194d18bSliuzhongzhu *supported = hdev->hw.mac.supported; 26139194d18bSliuzhongzhu *advertising = hdev->hw.mac.advertising; 26149194d18bSliuzhongzhu } 26159194d18bSliuzhongzhu 26161600c3e5SJian Shen #define MAX_SEPARATE_NUM 4 26171600c3e5SJian Shen #define SEPARATOR_VALUE 0xFFFFFFFF 26181600c3e5SJian Shen #define REG_NUM_PER_LINE 4 26191600c3e5SJian Shen #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 26201600c3e5SJian Shen 26211600c3e5SJian Shen static int hclgevf_get_regs_len(struct hnae3_handle *handle) 26221600c3e5SJian Shen { 26231600c3e5SJian Shen int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 26241600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 26251600c3e5SJian Shen 26261600c3e5SJian Shen cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 26271600c3e5SJian Shen common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 26281600c3e5SJian Shen ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 26291600c3e5SJian Shen tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 26301600c3e5SJian Shen 26311600c3e5SJian Shen return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 26321600c3e5SJian Shen tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 26331600c3e5SJian Shen } 26341600c3e5SJian Shen 26351600c3e5SJian Shen static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 26361600c3e5SJian Shen void *data) 26371600c3e5SJian Shen { 26381600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 26391600c3e5SJian Shen int i, j, reg_um, separator_num; 26401600c3e5SJian Shen u32 *reg = data; 26411600c3e5SJian Shen 26421600c3e5SJian Shen *version = hdev->fw_version; 26431600c3e5SJian Shen 26441600c3e5SJian Shen /* fetching per-VF registers values from VF PCIe register space */ 26451600c3e5SJian Shen reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 26461600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 26471600c3e5SJian Shen for (i = 0; i < reg_um; i++) 26481600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 26491600c3e5SJian Shen for (i = 0; i < separator_num; i++) 26501600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 26511600c3e5SJian Shen 26521600c3e5SJian Shen reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 26531600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 26541600c3e5SJian Shen for (i = 0; i < reg_um; i++) 26551600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 26561600c3e5SJian Shen for (i = 0; i < separator_num; i++) 26571600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 26581600c3e5SJian Shen 26591600c3e5SJian Shen reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 26601600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 26611600c3e5SJian Shen for (j = 0; j < hdev->num_tqps; j++) { 26621600c3e5SJian Shen for (i = 0; i < reg_um; i++) 26631600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 26641600c3e5SJian Shen ring_reg_addr_list[i] + 26651600c3e5SJian Shen 0x200 * j); 26661600c3e5SJian Shen for (i = 0; i < separator_num; i++) 26671600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 26681600c3e5SJian Shen } 26691600c3e5SJian Shen 26701600c3e5SJian Shen reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 26711600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 26721600c3e5SJian Shen for (j = 0; j < hdev->num_msi_used - 1; j++) { 26731600c3e5SJian Shen for (i = 0; i < reg_um; i++) 26741600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 26751600c3e5SJian Shen tqp_intr_reg_addr_list[i] + 26761600c3e5SJian Shen 4 * j); 26771600c3e5SJian Shen for (i = 0; i < separator_num; i++) 26781600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 26791600c3e5SJian Shen } 26801600c3e5SJian Shen } 26811600c3e5SJian Shen 2682e2cb1decSSalil Mehta static const struct hnae3_ae_ops hclgevf_ops = { 2683e2cb1decSSalil Mehta .init_ae_dev = hclgevf_init_ae_dev, 2684e2cb1decSSalil Mehta .uninit_ae_dev = hclgevf_uninit_ae_dev, 26856ff3cf07SHuazhong Tan .flr_prepare = hclgevf_flr_prepare, 26866ff3cf07SHuazhong Tan .flr_done = hclgevf_flr_done, 2687e718a93fSPeng Li .init_client_instance = hclgevf_init_client_instance, 2688e718a93fSPeng Li .uninit_client_instance = hclgevf_uninit_client_instance, 2689e2cb1decSSalil Mehta .start = hclgevf_ae_start, 2690e2cb1decSSalil Mehta .stop = hclgevf_ae_stop, 2691a6d818e3SYunsheng Lin .client_start = hclgevf_client_start, 2692a6d818e3SYunsheng Lin .client_stop = hclgevf_client_stop, 2693e2cb1decSSalil Mehta .map_ring_to_vector = hclgevf_map_ring_to_vector, 2694e2cb1decSSalil Mehta .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 2695e2cb1decSSalil Mehta .get_vector = hclgevf_get_vector, 26960d3e6631SYunsheng Lin .put_vector = hclgevf_put_vector, 2697e2cb1decSSalil Mehta .reset_queue = hclgevf_reset_tqp, 2698e2cb1decSSalil Mehta .get_mac_addr = hclgevf_get_mac_addr, 2699e2cb1decSSalil Mehta .set_mac_addr = hclgevf_set_mac_addr, 2700e2cb1decSSalil Mehta .add_uc_addr = hclgevf_add_uc_addr, 2701e2cb1decSSalil Mehta .rm_uc_addr = hclgevf_rm_uc_addr, 2702e2cb1decSSalil Mehta .add_mc_addr = hclgevf_add_mc_addr, 2703e2cb1decSSalil Mehta .rm_mc_addr = hclgevf_rm_mc_addr, 2704e2cb1decSSalil Mehta .get_stats = hclgevf_get_stats, 2705e2cb1decSSalil Mehta .update_stats = hclgevf_update_stats, 2706e2cb1decSSalil Mehta .get_strings = hclgevf_get_strings, 2707e2cb1decSSalil Mehta .get_sset_count = hclgevf_get_sset_count, 2708e2cb1decSSalil Mehta .get_rss_key_size = hclgevf_get_rss_key_size, 2709e2cb1decSSalil Mehta .get_rss_indir_size = hclgevf_get_rss_indir_size, 2710e2cb1decSSalil Mehta .get_rss = hclgevf_get_rss, 2711e2cb1decSSalil Mehta .set_rss = hclgevf_set_rss, 2712d97b3072SJian Shen .get_rss_tuple = hclgevf_get_rss_tuple, 2713d97b3072SJian Shen .set_rss_tuple = hclgevf_set_rss_tuple, 2714e2cb1decSSalil Mehta .get_tc_size = hclgevf_get_tc_size, 2715e2cb1decSSalil Mehta .get_fw_version = hclgevf_get_fw_version, 2716e2cb1decSSalil Mehta .set_vlan_filter = hclgevf_set_vlan_filter, 2717b2641e2aSYunsheng Lin .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 27186d4c3981SSalil Mehta .reset_event = hclgevf_reset_event, 2719720bd583SHuazhong Tan .set_default_reset_request = hclgevf_set_def_reset_request, 2720849e4607SPeng Li .get_channels = hclgevf_get_channels, 2721cc719218SPeng Li .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 27221600c3e5SJian Shen .get_regs_len = hclgevf_get_regs_len, 27231600c3e5SJian Shen .get_regs = hclgevf_get_regs, 2724175ec96bSFuyun Liang .get_status = hclgevf_get_status, 27254a152de9SFuyun Liang .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 2726c136b884SPeng Li .get_media_type = hclgevf_get_media_type, 27274d60291bSHuazhong Tan .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 27284d60291bSHuazhong Tan .ae_dev_resetting = hclgevf_ae_dev_resetting, 27294d60291bSHuazhong Tan .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 27305c9f6b39SPeng Li .set_gro_en = hclgevf_gro_en, 2731818f1675SYunsheng Lin .set_mtu = hclgevf_set_mtu, 27320c29d191Sliuzhongzhu .get_global_queue_id = hclgevf_get_qid_global, 27338cdb992fSJian Shen .set_timer_task = hclgevf_set_timer_task, 27349194d18bSliuzhongzhu .get_link_mode = hclgevf_get_link_mode, 2735e2cb1decSSalil Mehta }; 2736e2cb1decSSalil Mehta 2737e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf = { 2738e2cb1decSSalil Mehta .ops = &hclgevf_ops, 2739e2cb1decSSalil Mehta .pdev_id_table = ae_algovf_pci_tbl, 2740e2cb1decSSalil Mehta }; 2741e2cb1decSSalil Mehta 2742e2cb1decSSalil Mehta static int hclgevf_init(void) 2743e2cb1decSSalil Mehta { 2744e2cb1decSSalil Mehta pr_info("%s is initializing\n", HCLGEVF_NAME); 2745e2cb1decSSalil Mehta 2746854cf33aSFuyun Liang hnae3_register_ae_algo(&ae_algovf); 2747854cf33aSFuyun Liang 2748854cf33aSFuyun Liang return 0; 2749e2cb1decSSalil Mehta } 2750e2cb1decSSalil Mehta 2751e2cb1decSSalil Mehta static void hclgevf_exit(void) 2752e2cb1decSSalil Mehta { 2753e2cb1decSSalil Mehta hnae3_unregister_ae_algo(&ae_algovf); 2754e2cb1decSSalil Mehta } 2755e2cb1decSSalil Mehta module_init(hclgevf_init); 2756e2cb1decSSalil Mehta module_exit(hclgevf_exit); 2757e2cb1decSSalil Mehta 2758e2cb1decSSalil Mehta MODULE_LICENSE("GPL"); 2759e2cb1decSSalil Mehta MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 2760e2cb1decSSalil Mehta MODULE_DESCRIPTION("HCLGEVF Driver"); 2761e2cb1decSSalil Mehta MODULE_VERSION(HCLGEVF_MOD_VERSION); 2762