1e2cb1decSSalil Mehta // SPDX-License-Identifier: GPL-2.0+ 2e2cb1decSSalil Mehta // Copyright (c) 2016-2017 Hisilicon Limited. 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #include <linux/etherdevice.h> 5aa5c4f17SHuazhong Tan #include <linux/iopoll.h> 66988eb2aSSalil Mehta #include <net/rtnetlink.h> 7e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 8e2cb1decSSalil Mehta #include "hclgevf_main.h" 9e2cb1decSSalil Mehta #include "hclge_mbx.h" 10e2cb1decSSalil Mehta #include "hnae3.h" 11e2cb1decSSalil Mehta 12e2cb1decSSalil Mehta #define HCLGEVF_NAME "hclgevf" 13e2cb1decSSalil Mehta 149c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 15e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf; 16e2cb1decSSalil Mehta 17e2cb1decSSalil Mehta static const struct pci_device_id ae_algovf_pci_tbl[] = { 18e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 19e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 20e2cb1decSSalil Mehta /* required last entry */ 21e2cb1decSSalil Mehta {0, } 22e2cb1decSSalil Mehta }; 23e2cb1decSSalil Mehta 24472d7eceSJian Shen static const u8 hclgevf_hash_key[] = { 25472d7eceSJian Shen 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 26472d7eceSJian Shen 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 27472d7eceSJian Shen 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 28472d7eceSJian Shen 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 29472d7eceSJian Shen 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 30472d7eceSJian Shen }; 31472d7eceSJian Shen 322f550a46SYunsheng Lin MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 332f550a46SYunsheng Lin 341600c3e5SJian Shen static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 351600c3e5SJian Shen HCLGEVF_CMDQ_TX_ADDR_H_REG, 361600c3e5SJian Shen HCLGEVF_CMDQ_TX_DEPTH_REG, 371600c3e5SJian Shen HCLGEVF_CMDQ_TX_TAIL_REG, 381600c3e5SJian Shen HCLGEVF_CMDQ_TX_HEAD_REG, 391600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_L_REG, 401600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_H_REG, 411600c3e5SJian Shen HCLGEVF_CMDQ_RX_DEPTH_REG, 421600c3e5SJian Shen HCLGEVF_CMDQ_RX_TAIL_REG, 431600c3e5SJian Shen HCLGEVF_CMDQ_RX_HEAD_REG, 441600c3e5SJian Shen HCLGEVF_VECTOR0_CMDQ_SRC_REG, 451600c3e5SJian Shen HCLGEVF_CMDQ_INTR_STS_REG, 461600c3e5SJian Shen HCLGEVF_CMDQ_INTR_EN_REG, 471600c3e5SJian Shen HCLGEVF_CMDQ_INTR_GEN_REG}; 481600c3e5SJian Shen 491600c3e5SJian Shen static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 501600c3e5SJian Shen HCLGEVF_RST_ING, 511600c3e5SJian Shen HCLGEVF_GRO_EN_REG}; 521600c3e5SJian Shen 531600c3e5SJian Shen static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 541600c3e5SJian Shen HCLGEVF_RING_RX_ADDR_H_REG, 551600c3e5SJian Shen HCLGEVF_RING_RX_BD_NUM_REG, 561600c3e5SJian Shen HCLGEVF_RING_RX_BD_LENGTH_REG, 571600c3e5SJian Shen HCLGEVF_RING_RX_MERGE_EN_REG, 581600c3e5SJian Shen HCLGEVF_RING_RX_TAIL_REG, 591600c3e5SJian Shen HCLGEVF_RING_RX_HEAD_REG, 601600c3e5SJian Shen HCLGEVF_RING_RX_FBD_NUM_REG, 611600c3e5SJian Shen HCLGEVF_RING_RX_OFFSET_REG, 621600c3e5SJian Shen HCLGEVF_RING_RX_FBD_OFFSET_REG, 631600c3e5SJian Shen HCLGEVF_RING_RX_STASH_REG, 641600c3e5SJian Shen HCLGEVF_RING_RX_BD_ERR_REG, 651600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_L_REG, 661600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_H_REG, 671600c3e5SJian Shen HCLGEVF_RING_TX_BD_NUM_REG, 681600c3e5SJian Shen HCLGEVF_RING_TX_PRIORITY_REG, 691600c3e5SJian Shen HCLGEVF_RING_TX_TC_REG, 701600c3e5SJian Shen HCLGEVF_RING_TX_MERGE_EN_REG, 711600c3e5SJian Shen HCLGEVF_RING_TX_TAIL_REG, 721600c3e5SJian Shen HCLGEVF_RING_TX_HEAD_REG, 731600c3e5SJian Shen HCLGEVF_RING_TX_FBD_NUM_REG, 741600c3e5SJian Shen HCLGEVF_RING_TX_OFFSET_REG, 751600c3e5SJian Shen HCLGEVF_RING_TX_EBD_NUM_REG, 761600c3e5SJian Shen HCLGEVF_RING_TX_EBD_OFFSET_REG, 771600c3e5SJian Shen HCLGEVF_RING_TX_BD_ERR_REG, 781600c3e5SJian Shen HCLGEVF_RING_EN_REG}; 791600c3e5SJian Shen 801600c3e5SJian Shen static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 811600c3e5SJian Shen HCLGEVF_TQP_INTR_GL0_REG, 821600c3e5SJian Shen HCLGEVF_TQP_INTR_GL1_REG, 831600c3e5SJian Shen HCLGEVF_TQP_INTR_GL2_REG, 841600c3e5SJian Shen HCLGEVF_TQP_INTR_RL_REG}; 851600c3e5SJian Shen 86e2cb1decSSalil Mehta static inline struct hclgevf_dev *hclgevf_ae_get_hdev( 87e2cb1decSSalil Mehta struct hnae3_handle *handle) 88e2cb1decSSalil Mehta { 89eed9535fSPeng Li if (!handle->client) 90eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, nic); 91eed9535fSPeng Li else if (handle->client->type == HNAE3_CLIENT_ROCE) 92eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, roce); 93eed9535fSPeng Li else 94e2cb1decSSalil Mehta return container_of(handle, struct hclgevf_dev, nic); 95e2cb1decSSalil Mehta } 96e2cb1decSSalil Mehta 97e2cb1decSSalil Mehta static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 98e2cb1decSSalil Mehta { 99b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 100e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 101e2cb1decSSalil Mehta struct hclgevf_desc desc; 102e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 103e2cb1decSSalil Mehta int status; 104e2cb1decSSalil Mehta int i; 105e2cb1decSSalil Mehta 106b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 107b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 108e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 109e2cb1decSSalil Mehta HCLGEVF_OPC_QUERY_RX_STATUS, 110e2cb1decSSalil Mehta true); 111e2cb1decSSalil Mehta 112e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 113e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 114e2cb1decSSalil Mehta if (status) { 115e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 116e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 117e2cb1decSSalil Mehta status, i); 118e2cb1decSSalil Mehta return status; 119e2cb1decSSalil Mehta } 120e2cb1decSSalil Mehta tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 121cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 122e2cb1decSSalil Mehta 123e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 124e2cb1decSSalil Mehta true); 125e2cb1decSSalil Mehta 126e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 127e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 128e2cb1decSSalil Mehta if (status) { 129e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 130e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 131e2cb1decSSalil Mehta status, i); 132e2cb1decSSalil Mehta return status; 133e2cb1decSSalil Mehta } 134e2cb1decSSalil Mehta tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 135cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 136e2cb1decSSalil Mehta } 137e2cb1decSSalil Mehta 138e2cb1decSSalil Mehta return 0; 139e2cb1decSSalil Mehta } 140e2cb1decSSalil Mehta 141e2cb1decSSalil Mehta static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 142e2cb1decSSalil Mehta { 143e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo = &handle->kinfo; 144e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 145e2cb1decSSalil Mehta u64 *buff = data; 146e2cb1decSSalil Mehta int i; 147e2cb1decSSalil Mehta 148b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 149b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 150e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 151e2cb1decSSalil Mehta } 152e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 153b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 154e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 155e2cb1decSSalil Mehta } 156e2cb1decSSalil Mehta 157e2cb1decSSalil Mehta return buff; 158e2cb1decSSalil Mehta } 159e2cb1decSSalil Mehta 160e2cb1decSSalil Mehta static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 161e2cb1decSSalil Mehta { 162b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 163e2cb1decSSalil Mehta 164b4f1d303SJian Shen return kinfo->num_tqps * 2; 165e2cb1decSSalil Mehta } 166e2cb1decSSalil Mehta 167e2cb1decSSalil Mehta static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 168e2cb1decSSalil Mehta { 169b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 170e2cb1decSSalil Mehta u8 *buff = data; 171e2cb1decSSalil Mehta int i = 0; 172e2cb1decSSalil Mehta 173b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 174b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 175e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1760c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 177e2cb1decSSalil Mehta tqp->index); 178e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 179e2cb1decSSalil Mehta } 180e2cb1decSSalil Mehta 181b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 182b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 183e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1840c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 185e2cb1decSSalil Mehta tqp->index); 186e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 187e2cb1decSSalil Mehta } 188e2cb1decSSalil Mehta 189e2cb1decSSalil Mehta return buff; 190e2cb1decSSalil Mehta } 191e2cb1decSSalil Mehta 192e2cb1decSSalil Mehta static void hclgevf_update_stats(struct hnae3_handle *handle, 193e2cb1decSSalil Mehta struct net_device_stats *net_stats) 194e2cb1decSSalil Mehta { 195e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 196e2cb1decSSalil Mehta int status; 197e2cb1decSSalil Mehta 198e2cb1decSSalil Mehta status = hclgevf_tqps_update_stats(handle); 199e2cb1decSSalil Mehta if (status) 200e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 201e2cb1decSSalil Mehta "VF update of TQPS stats fail, status = %d.\n", 202e2cb1decSSalil Mehta status); 203e2cb1decSSalil Mehta } 204e2cb1decSSalil Mehta 205e2cb1decSSalil Mehta static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 206e2cb1decSSalil Mehta { 207e2cb1decSSalil Mehta if (strset == ETH_SS_TEST) 208e2cb1decSSalil Mehta return -EOPNOTSUPP; 209e2cb1decSSalil Mehta else if (strset == ETH_SS_STATS) 210e2cb1decSSalil Mehta return hclgevf_tqps_get_sset_count(handle, strset); 211e2cb1decSSalil Mehta 212e2cb1decSSalil Mehta return 0; 213e2cb1decSSalil Mehta } 214e2cb1decSSalil Mehta 215e2cb1decSSalil Mehta static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 216e2cb1decSSalil Mehta u8 *data) 217e2cb1decSSalil Mehta { 218e2cb1decSSalil Mehta u8 *p = (char *)data; 219e2cb1decSSalil Mehta 220e2cb1decSSalil Mehta if (strset == ETH_SS_STATS) 221e2cb1decSSalil Mehta p = hclgevf_tqps_get_strings(handle, p); 222e2cb1decSSalil Mehta } 223e2cb1decSSalil Mehta 224e2cb1decSSalil Mehta static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 225e2cb1decSSalil Mehta { 226e2cb1decSSalil Mehta hclgevf_tqps_get_stats(handle, data); 227e2cb1decSSalil Mehta } 228e2cb1decSSalil Mehta 229e2cb1decSSalil Mehta static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 230e2cb1decSSalil Mehta { 231e2cb1decSSalil Mehta u8 resp_msg; 232e2cb1decSSalil Mehta int status; 233e2cb1decSSalil Mehta 234e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 235e2cb1decSSalil Mehta true, &resp_msg, sizeof(u8)); 236e2cb1decSSalil Mehta if (status) { 237e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 238e2cb1decSSalil Mehta "VF request to get TC info from PF failed %d", 239e2cb1decSSalil Mehta status); 240e2cb1decSSalil Mehta return status; 241e2cb1decSSalil Mehta } 242e2cb1decSSalil Mehta 243e2cb1decSSalil Mehta hdev->hw_tc_map = resp_msg; 244e2cb1decSSalil Mehta 245e2cb1decSSalil Mehta return 0; 246e2cb1decSSalil Mehta } 247e2cb1decSSalil Mehta 24892f11ea1SJian Shen static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 24992f11ea1SJian Shen { 25092f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 25192f11ea1SJian Shen u8 resp_msg; 25292f11ea1SJian Shen int ret; 25392f11ea1SJian Shen 25492f11ea1SJian Shen ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 25592f11ea1SJian Shen HCLGE_MBX_GET_PORT_BASE_VLAN_STATE, 25692f11ea1SJian Shen NULL, 0, true, &resp_msg, sizeof(u8)); 25792f11ea1SJian Shen if (ret) { 25892f11ea1SJian Shen dev_err(&hdev->pdev->dev, 25992f11ea1SJian Shen "VF request to get port based vlan state failed %d", 26092f11ea1SJian Shen ret); 26192f11ea1SJian Shen return ret; 26292f11ea1SJian Shen } 26392f11ea1SJian Shen 26492f11ea1SJian Shen nic->port_base_vlan_state = resp_msg; 26592f11ea1SJian Shen 26692f11ea1SJian Shen return 0; 26792f11ea1SJian Shen } 26892f11ea1SJian Shen 2696cee6fc3SJian Shen static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 270e2cb1decSSalil Mehta { 271c0425944SPeng Li #define HCLGEVF_TQPS_RSS_INFO_LEN 6 272e2cb1decSSalil Mehta u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 273e2cb1decSSalil Mehta int status; 274e2cb1decSSalil Mehta 275e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 276e2cb1decSSalil Mehta true, resp_msg, 277e2cb1decSSalil Mehta HCLGEVF_TQPS_RSS_INFO_LEN); 278e2cb1decSSalil Mehta if (status) { 279e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 280e2cb1decSSalil Mehta "VF request to get tqp info from PF failed %d", 281e2cb1decSSalil Mehta status); 282e2cb1decSSalil Mehta return status; 283e2cb1decSSalil Mehta } 284e2cb1decSSalil Mehta 285e2cb1decSSalil Mehta memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 286e2cb1decSSalil Mehta memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 287c0425944SPeng Li memcpy(&hdev->rx_buf_len, &resp_msg[4], sizeof(u16)); 288c0425944SPeng Li 289c0425944SPeng Li return 0; 290c0425944SPeng Li } 291c0425944SPeng Li 292c0425944SPeng Li static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 293c0425944SPeng Li { 294c0425944SPeng Li #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 295c0425944SPeng Li u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 296c0425944SPeng Li int ret; 297c0425944SPeng Li 298c0425944SPeng Li ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QDEPTH, 0, NULL, 0, 299c0425944SPeng Li true, resp_msg, 300c0425944SPeng Li HCLGEVF_TQPS_DEPTH_INFO_LEN); 301c0425944SPeng Li if (ret) { 302c0425944SPeng Li dev_err(&hdev->pdev->dev, 303c0425944SPeng Li "VF request to get tqp depth info from PF failed %d", 304c0425944SPeng Li ret); 305c0425944SPeng Li return ret; 306c0425944SPeng Li } 307c0425944SPeng Li 308c0425944SPeng Li memcpy(&hdev->num_tx_desc, &resp_msg[0], sizeof(u16)); 309c0425944SPeng Li memcpy(&hdev->num_rx_desc, &resp_msg[2], sizeof(u16)); 310e2cb1decSSalil Mehta 311e2cb1decSSalil Mehta return 0; 312e2cb1decSSalil Mehta } 313e2cb1decSSalil Mehta 3140c29d191Sliuzhongzhu static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 3150c29d191Sliuzhongzhu { 3160c29d191Sliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3170c29d191Sliuzhongzhu u8 msg_data[2], resp_data[2]; 3180c29d191Sliuzhongzhu u16 qid_in_pf = 0; 3190c29d191Sliuzhongzhu int ret; 3200c29d191Sliuzhongzhu 3210c29d191Sliuzhongzhu memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 3220c29d191Sliuzhongzhu 3230c29d191Sliuzhongzhu ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data, 3240c29d191Sliuzhongzhu 2, true, resp_data, 2); 3250c29d191Sliuzhongzhu if (!ret) 3260c29d191Sliuzhongzhu qid_in_pf = *(u16 *)resp_data; 3270c29d191Sliuzhongzhu 3280c29d191Sliuzhongzhu return qid_in_pf; 3290c29d191Sliuzhongzhu } 3300c29d191Sliuzhongzhu 3319c3e7130Sliuzhongzhu static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 3329c3e7130Sliuzhongzhu { 33388d10bd6SJian Shen u8 resp_msg[2]; 3349c3e7130Sliuzhongzhu int ret; 3359c3e7130Sliuzhongzhu 3369c3e7130Sliuzhongzhu ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_MEDIA_TYPE, 0, NULL, 0, 33788d10bd6SJian Shen true, resp_msg, sizeof(resp_msg)); 3389c3e7130Sliuzhongzhu if (ret) { 3399c3e7130Sliuzhongzhu dev_err(&hdev->pdev->dev, 3409c3e7130Sliuzhongzhu "VF request to get the pf port media type failed %d", 3419c3e7130Sliuzhongzhu ret); 3429c3e7130Sliuzhongzhu return ret; 3439c3e7130Sliuzhongzhu } 3449c3e7130Sliuzhongzhu 34588d10bd6SJian Shen hdev->hw.mac.media_type = resp_msg[0]; 34688d10bd6SJian Shen hdev->hw.mac.module_type = resp_msg[1]; 3479c3e7130Sliuzhongzhu 3489c3e7130Sliuzhongzhu return 0; 3499c3e7130Sliuzhongzhu } 3509c3e7130Sliuzhongzhu 351e2cb1decSSalil Mehta static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 352e2cb1decSSalil Mehta { 353e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 354e2cb1decSSalil Mehta int i; 355e2cb1decSSalil Mehta 356e2cb1decSSalil Mehta hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 357e2cb1decSSalil Mehta sizeof(struct hclgevf_tqp), GFP_KERNEL); 358e2cb1decSSalil Mehta if (!hdev->htqp) 359e2cb1decSSalil Mehta return -ENOMEM; 360e2cb1decSSalil Mehta 361e2cb1decSSalil Mehta tqp = hdev->htqp; 362e2cb1decSSalil Mehta 363e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 364e2cb1decSSalil Mehta tqp->dev = &hdev->pdev->dev; 365e2cb1decSSalil Mehta tqp->index = i; 366e2cb1decSSalil Mehta 367e2cb1decSSalil Mehta tqp->q.ae_algo = &ae_algovf; 368e2cb1decSSalil Mehta tqp->q.buf_size = hdev->rx_buf_len; 369c0425944SPeng Li tqp->q.tx_desc_num = hdev->num_tx_desc; 370c0425944SPeng Li tqp->q.rx_desc_num = hdev->num_rx_desc; 371e2cb1decSSalil Mehta tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 372e2cb1decSSalil Mehta i * HCLGEVF_TQP_REG_SIZE; 373e2cb1decSSalil Mehta 374e2cb1decSSalil Mehta tqp++; 375e2cb1decSSalil Mehta } 376e2cb1decSSalil Mehta 377e2cb1decSSalil Mehta return 0; 378e2cb1decSSalil Mehta } 379e2cb1decSSalil Mehta 380e2cb1decSSalil Mehta static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 381e2cb1decSSalil Mehta { 382e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 383e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo; 384e2cb1decSSalil Mehta u16 new_tqps = hdev->num_tqps; 385e2cb1decSSalil Mehta int i; 386e2cb1decSSalil Mehta 387e2cb1decSSalil Mehta kinfo = &nic->kinfo; 388e2cb1decSSalil Mehta kinfo->num_tc = 0; 389c0425944SPeng Li kinfo->num_tx_desc = hdev->num_tx_desc; 390c0425944SPeng Li kinfo->num_rx_desc = hdev->num_rx_desc; 391e2cb1decSSalil Mehta kinfo->rx_buf_len = hdev->rx_buf_len; 392e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 393e2cb1decSSalil Mehta if (hdev->hw_tc_map & BIT(i)) 394e2cb1decSSalil Mehta kinfo->num_tc++; 395e2cb1decSSalil Mehta 396e2cb1decSSalil Mehta kinfo->rss_size 397e2cb1decSSalil Mehta = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 398e2cb1decSSalil Mehta new_tqps = kinfo->rss_size * kinfo->num_tc; 399e2cb1decSSalil Mehta kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 400e2cb1decSSalil Mehta 401e2cb1decSSalil Mehta kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 402e2cb1decSSalil Mehta sizeof(struct hnae3_queue *), GFP_KERNEL); 403e2cb1decSSalil Mehta if (!kinfo->tqp) 404e2cb1decSSalil Mehta return -ENOMEM; 405e2cb1decSSalil Mehta 406e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 407e2cb1decSSalil Mehta hdev->htqp[i].q.handle = &hdev->nic; 408e2cb1decSSalil Mehta hdev->htqp[i].q.tqp_index = i; 409e2cb1decSSalil Mehta kinfo->tqp[i] = &hdev->htqp[i].q; 410e2cb1decSSalil Mehta } 411e2cb1decSSalil Mehta 412e2cb1decSSalil Mehta return 0; 413e2cb1decSSalil Mehta } 414e2cb1decSSalil Mehta 415e2cb1decSSalil Mehta static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 416e2cb1decSSalil Mehta { 417e2cb1decSSalil Mehta int status; 418e2cb1decSSalil Mehta u8 resp_msg; 419e2cb1decSSalil Mehta 420e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 421e2cb1decSSalil Mehta 0, false, &resp_msg, sizeof(u8)); 422e2cb1decSSalil Mehta if (status) 423e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 424e2cb1decSSalil Mehta "VF failed to fetch link status(%d) from PF", status); 425e2cb1decSSalil Mehta } 426e2cb1decSSalil Mehta 427e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 428e2cb1decSSalil Mehta { 42945e92b7eSPeng Li struct hnae3_handle *rhandle = &hdev->roce; 430e2cb1decSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 43145e92b7eSPeng Li struct hnae3_client *rclient; 432e2cb1decSSalil Mehta struct hnae3_client *client; 433e2cb1decSSalil Mehta 434e2cb1decSSalil Mehta client = handle->client; 43545e92b7eSPeng Li rclient = hdev->roce_client; 436e2cb1decSSalil Mehta 437582d37bbSPeng Li link_state = 438582d37bbSPeng Li test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 439582d37bbSPeng Li 440e2cb1decSSalil Mehta if (link_state != hdev->hw.mac.link) { 441e2cb1decSSalil Mehta client->ops->link_status_change(handle, !!link_state); 44245e92b7eSPeng Li if (rclient && rclient->ops->link_status_change) 44345e92b7eSPeng Li rclient->ops->link_status_change(rhandle, !!link_state); 444e2cb1decSSalil Mehta hdev->hw.mac.link = link_state; 445e2cb1decSSalil Mehta } 446e2cb1decSSalil Mehta } 447e2cb1decSSalil Mehta 448538abaf3SYueHaibing static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 4499194d18bSliuzhongzhu { 4509194d18bSliuzhongzhu #define HCLGEVF_ADVERTISING 0 4519194d18bSliuzhongzhu #define HCLGEVF_SUPPORTED 1 4529194d18bSliuzhongzhu u8 send_msg; 4539194d18bSliuzhongzhu u8 resp_msg; 4549194d18bSliuzhongzhu 4559194d18bSliuzhongzhu send_msg = HCLGEVF_ADVERTISING; 4569194d18bSliuzhongzhu hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, &send_msg, 4579194d18bSliuzhongzhu sizeof(u8), false, &resp_msg, sizeof(u8)); 4589194d18bSliuzhongzhu send_msg = HCLGEVF_SUPPORTED; 4599194d18bSliuzhongzhu hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, &send_msg, 4609194d18bSliuzhongzhu sizeof(u8), false, &resp_msg, sizeof(u8)); 4619194d18bSliuzhongzhu } 4629194d18bSliuzhongzhu 463e2cb1decSSalil Mehta static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 464e2cb1decSSalil Mehta { 465e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 466e2cb1decSSalil Mehta int ret; 467e2cb1decSSalil Mehta 468e2cb1decSSalil Mehta nic->ae_algo = &ae_algovf; 469e2cb1decSSalil Mehta nic->pdev = hdev->pdev; 470e2cb1decSSalil Mehta nic->numa_node_mask = hdev->numa_node_mask; 471424eb834SSalil Mehta nic->flags |= HNAE3_SUPPORT_VF; 472e2cb1decSSalil Mehta 473e2cb1decSSalil Mehta if (hdev->ae_dev->dev_type != HNAE3_DEV_KNIC) { 474e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "unsupported device type %d\n", 475e2cb1decSSalil Mehta hdev->ae_dev->dev_type); 476e2cb1decSSalil Mehta return -EINVAL; 477e2cb1decSSalil Mehta } 478e2cb1decSSalil Mehta 479e2cb1decSSalil Mehta ret = hclgevf_knic_setup(hdev); 480e2cb1decSSalil Mehta if (ret) 481e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 482e2cb1decSSalil Mehta ret); 483e2cb1decSSalil Mehta return ret; 484e2cb1decSSalil Mehta } 485e2cb1decSSalil Mehta 486e2cb1decSSalil Mehta static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 487e2cb1decSSalil Mehta { 48836cbbdf6SPeng Li if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 48936cbbdf6SPeng Li dev_warn(&hdev->pdev->dev, 49036cbbdf6SPeng Li "vector(vector_id %d) has been freed.\n", vector_id); 49136cbbdf6SPeng Li return; 49236cbbdf6SPeng Li } 49336cbbdf6SPeng Li 494e2cb1decSSalil Mehta hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 495e2cb1decSSalil Mehta hdev->num_msi_left += 1; 496e2cb1decSSalil Mehta hdev->num_msi_used -= 1; 497e2cb1decSSalil Mehta } 498e2cb1decSSalil Mehta 499e2cb1decSSalil Mehta static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 500e2cb1decSSalil Mehta struct hnae3_vector_info *vector_info) 501e2cb1decSSalil Mehta { 502e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 503e2cb1decSSalil Mehta struct hnae3_vector_info *vector = vector_info; 504e2cb1decSSalil Mehta int alloc = 0; 505e2cb1decSSalil Mehta int i, j; 506e2cb1decSSalil Mehta 507e2cb1decSSalil Mehta vector_num = min(hdev->num_msi_left, vector_num); 508e2cb1decSSalil Mehta 509e2cb1decSSalil Mehta for (j = 0; j < vector_num; j++) { 510e2cb1decSSalil Mehta for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 511e2cb1decSSalil Mehta if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 512e2cb1decSSalil Mehta vector->vector = pci_irq_vector(hdev->pdev, i); 513e2cb1decSSalil Mehta vector->io_addr = hdev->hw.io_base + 514e2cb1decSSalil Mehta HCLGEVF_VECTOR_REG_BASE + 515e2cb1decSSalil Mehta (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 516e2cb1decSSalil Mehta hdev->vector_status[i] = 0; 517e2cb1decSSalil Mehta hdev->vector_irq[i] = vector->vector; 518e2cb1decSSalil Mehta 519e2cb1decSSalil Mehta vector++; 520e2cb1decSSalil Mehta alloc++; 521e2cb1decSSalil Mehta 522e2cb1decSSalil Mehta break; 523e2cb1decSSalil Mehta } 524e2cb1decSSalil Mehta } 525e2cb1decSSalil Mehta } 526e2cb1decSSalil Mehta hdev->num_msi_left -= alloc; 527e2cb1decSSalil Mehta hdev->num_msi_used += alloc; 528e2cb1decSSalil Mehta 529e2cb1decSSalil Mehta return alloc; 530e2cb1decSSalil Mehta } 531e2cb1decSSalil Mehta 532e2cb1decSSalil Mehta static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 533e2cb1decSSalil Mehta { 534e2cb1decSSalil Mehta int i; 535e2cb1decSSalil Mehta 536e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 537e2cb1decSSalil Mehta if (vector == hdev->vector_irq[i]) 538e2cb1decSSalil Mehta return i; 539e2cb1decSSalil Mehta 540e2cb1decSSalil Mehta return -EINVAL; 541e2cb1decSSalil Mehta } 542e2cb1decSSalil Mehta 543374ad291SJian Shen static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 544374ad291SJian Shen const u8 hfunc, const u8 *key) 545374ad291SJian Shen { 546374ad291SJian Shen struct hclgevf_rss_config_cmd *req; 547374ad291SJian Shen struct hclgevf_desc desc; 548374ad291SJian Shen int key_offset; 549374ad291SJian Shen int key_size; 550374ad291SJian Shen int ret; 551374ad291SJian Shen 552374ad291SJian Shen req = (struct hclgevf_rss_config_cmd *)desc.data; 553374ad291SJian Shen 554374ad291SJian Shen for (key_offset = 0; key_offset < 3; key_offset++) { 555374ad291SJian Shen hclgevf_cmd_setup_basic_desc(&desc, 556374ad291SJian Shen HCLGEVF_OPC_RSS_GENERIC_CONFIG, 557374ad291SJian Shen false); 558374ad291SJian Shen 559374ad291SJian Shen req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 560374ad291SJian Shen req->hash_config |= 561374ad291SJian Shen (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 562374ad291SJian Shen 563374ad291SJian Shen if (key_offset == 2) 564374ad291SJian Shen key_size = 565374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE - HCLGEVF_RSS_HASH_KEY_NUM * 2; 566374ad291SJian Shen else 567374ad291SJian Shen key_size = HCLGEVF_RSS_HASH_KEY_NUM; 568374ad291SJian Shen 569374ad291SJian Shen memcpy(req->hash_key, 570374ad291SJian Shen key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 571374ad291SJian Shen 572374ad291SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 573374ad291SJian Shen if (ret) { 574374ad291SJian Shen dev_err(&hdev->pdev->dev, 575374ad291SJian Shen "Configure RSS config fail, status = %d\n", 576374ad291SJian Shen ret); 577374ad291SJian Shen return ret; 578374ad291SJian Shen } 579374ad291SJian Shen } 580374ad291SJian Shen 581374ad291SJian Shen return 0; 582374ad291SJian Shen } 583374ad291SJian Shen 584e2cb1decSSalil Mehta static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 585e2cb1decSSalil Mehta { 586e2cb1decSSalil Mehta return HCLGEVF_RSS_KEY_SIZE; 587e2cb1decSSalil Mehta } 588e2cb1decSSalil Mehta 589e2cb1decSSalil Mehta static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 590e2cb1decSSalil Mehta { 591e2cb1decSSalil Mehta return HCLGEVF_RSS_IND_TBL_SIZE; 592e2cb1decSSalil Mehta } 593e2cb1decSSalil Mehta 594e2cb1decSSalil Mehta static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 595e2cb1decSSalil Mehta { 596e2cb1decSSalil Mehta const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 597e2cb1decSSalil Mehta struct hclgevf_rss_indirection_table_cmd *req; 598e2cb1decSSalil Mehta struct hclgevf_desc desc; 599e2cb1decSSalil Mehta int status; 600e2cb1decSSalil Mehta int i, j; 601e2cb1decSSalil Mehta 602e2cb1decSSalil Mehta req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 603e2cb1decSSalil Mehta 604e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 605e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 606e2cb1decSSalil Mehta false); 607e2cb1decSSalil Mehta req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 608e2cb1decSSalil Mehta req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 609e2cb1decSSalil Mehta for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 610e2cb1decSSalil Mehta req->rss_result[j] = 611e2cb1decSSalil Mehta indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 612e2cb1decSSalil Mehta 613e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 614e2cb1decSSalil Mehta if (status) { 615e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 616e2cb1decSSalil Mehta "VF failed(=%d) to set RSS indirection table\n", 617e2cb1decSSalil Mehta status); 618e2cb1decSSalil Mehta return status; 619e2cb1decSSalil Mehta } 620e2cb1decSSalil Mehta } 621e2cb1decSSalil Mehta 622e2cb1decSSalil Mehta return 0; 623e2cb1decSSalil Mehta } 624e2cb1decSSalil Mehta 625e2cb1decSSalil Mehta static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 626e2cb1decSSalil Mehta { 627e2cb1decSSalil Mehta struct hclgevf_rss_tc_mode_cmd *req; 628e2cb1decSSalil Mehta u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 629e2cb1decSSalil Mehta u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 630e2cb1decSSalil Mehta u16 tc_size[HCLGEVF_MAX_TC_NUM]; 631e2cb1decSSalil Mehta struct hclgevf_desc desc; 632e2cb1decSSalil Mehta u16 roundup_size; 633e2cb1decSSalil Mehta int status; 634e2cb1decSSalil Mehta int i; 635e2cb1decSSalil Mehta 636e2cb1decSSalil Mehta req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 637e2cb1decSSalil Mehta 638e2cb1decSSalil Mehta roundup_size = roundup_pow_of_two(rss_size); 639e2cb1decSSalil Mehta roundup_size = ilog2(roundup_size); 640e2cb1decSSalil Mehta 641e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 642e2cb1decSSalil Mehta tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 643e2cb1decSSalil Mehta tc_size[i] = roundup_size; 644e2cb1decSSalil Mehta tc_offset[i] = rss_size * i; 645e2cb1decSSalil Mehta } 646e2cb1decSSalil Mehta 647e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 648e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 649e4e87715SPeng Li hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 650e2cb1decSSalil Mehta (tc_valid[i] & 0x1)); 651e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 652e2cb1decSSalil Mehta HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 653e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 654e2cb1decSSalil Mehta HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 655e2cb1decSSalil Mehta } 656e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 657e2cb1decSSalil Mehta if (status) 658e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 659e2cb1decSSalil Mehta "VF failed(=%d) to set rss tc mode\n", status); 660e2cb1decSSalil Mehta 661e2cb1decSSalil Mehta return status; 662e2cb1decSSalil Mehta } 663e2cb1decSSalil Mehta 664a638b1d8SJian Shen /* for revision 0x20, vf shared the same rss config with pf */ 665a638b1d8SJian Shen static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 666a638b1d8SJian Shen { 667a638b1d8SJian Shen #define HCLGEVF_RSS_MBX_RESP_LEN 8 668a638b1d8SJian Shen 669a638b1d8SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 670a638b1d8SJian Shen u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 671a638b1d8SJian Shen u16 msg_num, hash_key_index; 672a638b1d8SJian Shen u8 index; 673a638b1d8SJian Shen int ret; 674a638b1d8SJian Shen 675a638b1d8SJian Shen msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 676a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN; 677a638b1d8SJian Shen for (index = 0; index < msg_num; index++) { 678a638b1d8SJian Shen ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_RSS_KEY, 0, 679a638b1d8SJian Shen &index, sizeof(index), 680a638b1d8SJian Shen true, resp_msg, 681a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN); 682a638b1d8SJian Shen if (ret) { 683a638b1d8SJian Shen dev_err(&hdev->pdev->dev, 684a638b1d8SJian Shen "VF get rss hash key from PF failed, ret=%d", 685a638b1d8SJian Shen ret); 686a638b1d8SJian Shen return ret; 687a638b1d8SJian Shen } 688a638b1d8SJian Shen 689a638b1d8SJian Shen hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 690a638b1d8SJian Shen if (index == msg_num - 1) 691a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 692a638b1d8SJian Shen &resp_msg[0], 693a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE - hash_key_index); 694a638b1d8SJian Shen else 695a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 696a638b1d8SJian Shen &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 697a638b1d8SJian Shen } 698a638b1d8SJian Shen 699a638b1d8SJian Shen return 0; 700a638b1d8SJian Shen } 701a638b1d8SJian Shen 702e2cb1decSSalil Mehta static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 703e2cb1decSSalil Mehta u8 *hfunc) 704e2cb1decSSalil Mehta { 705e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 706e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 707a638b1d8SJian Shen int i, ret; 708e2cb1decSSalil Mehta 709374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 710374ad291SJian Shen /* Get hash algorithm */ 711374ad291SJian Shen if (hfunc) { 712374ad291SJian Shen switch (rss_cfg->hash_algo) { 713374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 714374ad291SJian Shen *hfunc = ETH_RSS_HASH_TOP; 715374ad291SJian Shen break; 716374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 717374ad291SJian Shen *hfunc = ETH_RSS_HASH_XOR; 718374ad291SJian Shen break; 719374ad291SJian Shen default: 720374ad291SJian Shen *hfunc = ETH_RSS_HASH_UNKNOWN; 721374ad291SJian Shen break; 722374ad291SJian Shen } 723374ad291SJian Shen } 724374ad291SJian Shen 725374ad291SJian Shen /* Get the RSS Key required by the user */ 726374ad291SJian Shen if (key) 727374ad291SJian Shen memcpy(key, rss_cfg->rss_hash_key, 728374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 729a638b1d8SJian Shen } else { 730a638b1d8SJian Shen if (hfunc) 731a638b1d8SJian Shen *hfunc = ETH_RSS_HASH_TOP; 732a638b1d8SJian Shen if (key) { 733a638b1d8SJian Shen ret = hclgevf_get_rss_hash_key(hdev); 734a638b1d8SJian Shen if (ret) 735a638b1d8SJian Shen return ret; 736a638b1d8SJian Shen memcpy(key, rss_cfg->rss_hash_key, 737a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE); 738a638b1d8SJian Shen } 739374ad291SJian Shen } 740374ad291SJian Shen 741e2cb1decSSalil Mehta if (indir) 742e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 743e2cb1decSSalil Mehta indir[i] = rss_cfg->rss_indirection_tbl[i]; 744e2cb1decSSalil Mehta 745374ad291SJian Shen return 0; 746e2cb1decSSalil Mehta } 747e2cb1decSSalil Mehta 748e2cb1decSSalil Mehta static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 749e2cb1decSSalil Mehta const u8 *key, const u8 hfunc) 750e2cb1decSSalil Mehta { 751e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 752e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 753374ad291SJian Shen int ret, i; 754374ad291SJian Shen 755374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 756374ad291SJian Shen /* Set the RSS Hash Key if specififed by the user */ 757374ad291SJian Shen if (key) { 758374ad291SJian Shen switch (hfunc) { 759374ad291SJian Shen case ETH_RSS_HASH_TOP: 760374ad291SJian Shen rss_cfg->hash_algo = 761374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 762374ad291SJian Shen break; 763374ad291SJian Shen case ETH_RSS_HASH_XOR: 764374ad291SJian Shen rss_cfg->hash_algo = 765374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_SIMPLE; 766374ad291SJian Shen break; 767374ad291SJian Shen case ETH_RSS_HASH_NO_CHANGE: 768374ad291SJian Shen break; 769374ad291SJian Shen default: 770374ad291SJian Shen return -EINVAL; 771374ad291SJian Shen } 772374ad291SJian Shen 773374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 774374ad291SJian Shen key); 775374ad291SJian Shen if (ret) 776374ad291SJian Shen return ret; 777374ad291SJian Shen 778374ad291SJian Shen /* Update the shadow RSS key with user specified qids */ 779374ad291SJian Shen memcpy(rss_cfg->rss_hash_key, key, 780374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 781374ad291SJian Shen } 782374ad291SJian Shen } 783e2cb1decSSalil Mehta 784e2cb1decSSalil Mehta /* update the shadow RSS table with user specified qids */ 785e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 786e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = indir[i]; 787e2cb1decSSalil Mehta 788e2cb1decSSalil Mehta /* update the hardware */ 789e2cb1decSSalil Mehta return hclgevf_set_rss_indir_table(hdev); 790e2cb1decSSalil Mehta } 791e2cb1decSSalil Mehta 792d97b3072SJian Shen static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 793d97b3072SJian Shen { 794d97b3072SJian Shen u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 795d97b3072SJian Shen 796d97b3072SJian Shen if (nfc->data & RXH_L4_B_2_3) 797d97b3072SJian Shen hash_sets |= HCLGEVF_D_PORT_BIT; 798d97b3072SJian Shen else 799d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_PORT_BIT; 800d97b3072SJian Shen 801d97b3072SJian Shen if (nfc->data & RXH_IP_SRC) 802d97b3072SJian Shen hash_sets |= HCLGEVF_S_IP_BIT; 803d97b3072SJian Shen else 804d97b3072SJian Shen hash_sets &= ~HCLGEVF_S_IP_BIT; 805d97b3072SJian Shen 806d97b3072SJian Shen if (nfc->data & RXH_IP_DST) 807d97b3072SJian Shen hash_sets |= HCLGEVF_D_IP_BIT; 808d97b3072SJian Shen else 809d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_IP_BIT; 810d97b3072SJian Shen 811d97b3072SJian Shen if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 812d97b3072SJian Shen hash_sets |= HCLGEVF_V_TAG_BIT; 813d97b3072SJian Shen 814d97b3072SJian Shen return hash_sets; 815d97b3072SJian Shen } 816d97b3072SJian Shen 817d97b3072SJian Shen static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 818d97b3072SJian Shen struct ethtool_rxnfc *nfc) 819d97b3072SJian Shen { 820d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 821d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 822d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 823d97b3072SJian Shen struct hclgevf_desc desc; 824d97b3072SJian Shen u8 tuple_sets; 825d97b3072SJian Shen int ret; 826d97b3072SJian Shen 827d97b3072SJian Shen if (handle->pdev->revision == 0x20) 828d97b3072SJian Shen return -EOPNOTSUPP; 829d97b3072SJian Shen 830d97b3072SJian Shen if (nfc->data & 831d97b3072SJian Shen ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 832d97b3072SJian Shen return -EINVAL; 833d97b3072SJian Shen 834d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 835d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 836d97b3072SJian Shen 837d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 838d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 839d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 840d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 841d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 842d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 843d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 844d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 845d97b3072SJian Shen 846d97b3072SJian Shen tuple_sets = hclgevf_get_rss_hash_bits(nfc); 847d97b3072SJian Shen switch (nfc->flow_type) { 848d97b3072SJian Shen case TCP_V4_FLOW: 849d97b3072SJian Shen req->ipv4_tcp_en = tuple_sets; 850d97b3072SJian Shen break; 851d97b3072SJian Shen case TCP_V6_FLOW: 852d97b3072SJian Shen req->ipv6_tcp_en = tuple_sets; 853d97b3072SJian Shen break; 854d97b3072SJian Shen case UDP_V4_FLOW: 855d97b3072SJian Shen req->ipv4_udp_en = tuple_sets; 856d97b3072SJian Shen break; 857d97b3072SJian Shen case UDP_V6_FLOW: 858d97b3072SJian Shen req->ipv6_udp_en = tuple_sets; 859d97b3072SJian Shen break; 860d97b3072SJian Shen case SCTP_V4_FLOW: 861d97b3072SJian Shen req->ipv4_sctp_en = tuple_sets; 862d97b3072SJian Shen break; 863d97b3072SJian Shen case SCTP_V6_FLOW: 864d97b3072SJian Shen if ((nfc->data & RXH_L4_B_0_1) || 865d97b3072SJian Shen (nfc->data & RXH_L4_B_2_3)) 866d97b3072SJian Shen return -EINVAL; 867d97b3072SJian Shen 868d97b3072SJian Shen req->ipv6_sctp_en = tuple_sets; 869d97b3072SJian Shen break; 870d97b3072SJian Shen case IPV4_FLOW: 871d97b3072SJian Shen req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 872d97b3072SJian Shen break; 873d97b3072SJian Shen case IPV6_FLOW: 874d97b3072SJian Shen req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 875d97b3072SJian Shen break; 876d97b3072SJian Shen default: 877d97b3072SJian Shen return -EINVAL; 878d97b3072SJian Shen } 879d97b3072SJian Shen 880d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 881d97b3072SJian Shen if (ret) { 882d97b3072SJian Shen dev_err(&hdev->pdev->dev, 883d97b3072SJian Shen "Set rss tuple fail, status = %d\n", ret); 884d97b3072SJian Shen return ret; 885d97b3072SJian Shen } 886d97b3072SJian Shen 887d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 888d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 889d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 890d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 891d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 892d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 893d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 894d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 895d97b3072SJian Shen return 0; 896d97b3072SJian Shen } 897d97b3072SJian Shen 898d97b3072SJian Shen static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 899d97b3072SJian Shen struct ethtool_rxnfc *nfc) 900d97b3072SJian Shen { 901d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 902d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 903d97b3072SJian Shen u8 tuple_sets; 904d97b3072SJian Shen 905d97b3072SJian Shen if (handle->pdev->revision == 0x20) 906d97b3072SJian Shen return -EOPNOTSUPP; 907d97b3072SJian Shen 908d97b3072SJian Shen nfc->data = 0; 909d97b3072SJian Shen 910d97b3072SJian Shen switch (nfc->flow_type) { 911d97b3072SJian Shen case TCP_V4_FLOW: 912d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 913d97b3072SJian Shen break; 914d97b3072SJian Shen case UDP_V4_FLOW: 915d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 916d97b3072SJian Shen break; 917d97b3072SJian Shen case TCP_V6_FLOW: 918d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 919d97b3072SJian Shen break; 920d97b3072SJian Shen case UDP_V6_FLOW: 921d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 922d97b3072SJian Shen break; 923d97b3072SJian Shen case SCTP_V4_FLOW: 924d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 925d97b3072SJian Shen break; 926d97b3072SJian Shen case SCTP_V6_FLOW: 927d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 928d97b3072SJian Shen break; 929d97b3072SJian Shen case IPV4_FLOW: 930d97b3072SJian Shen case IPV6_FLOW: 931d97b3072SJian Shen tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 932d97b3072SJian Shen break; 933d97b3072SJian Shen default: 934d97b3072SJian Shen return -EINVAL; 935d97b3072SJian Shen } 936d97b3072SJian Shen 937d97b3072SJian Shen if (!tuple_sets) 938d97b3072SJian Shen return 0; 939d97b3072SJian Shen 940d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_PORT_BIT) 941d97b3072SJian Shen nfc->data |= RXH_L4_B_2_3; 942d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_PORT_BIT) 943d97b3072SJian Shen nfc->data |= RXH_L4_B_0_1; 944d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_IP_BIT) 945d97b3072SJian Shen nfc->data |= RXH_IP_DST; 946d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_IP_BIT) 947d97b3072SJian Shen nfc->data |= RXH_IP_SRC; 948d97b3072SJian Shen 949d97b3072SJian Shen return 0; 950d97b3072SJian Shen } 951d97b3072SJian Shen 952d97b3072SJian Shen static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 953d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg) 954d97b3072SJian Shen { 955d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 956d97b3072SJian Shen struct hclgevf_desc desc; 957d97b3072SJian Shen int ret; 958d97b3072SJian Shen 959d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 960d97b3072SJian Shen 961d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 962d97b3072SJian Shen 963d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 964d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 965d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 966d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 967d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 968d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 969d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 970d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 971d97b3072SJian Shen 972d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 973d97b3072SJian Shen if (ret) 974d97b3072SJian Shen dev_err(&hdev->pdev->dev, 975d97b3072SJian Shen "Configure rss input fail, status = %d\n", ret); 976d97b3072SJian Shen return ret; 977d97b3072SJian Shen } 978d97b3072SJian Shen 979e2cb1decSSalil Mehta static int hclgevf_get_tc_size(struct hnae3_handle *handle) 980e2cb1decSSalil Mehta { 981e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 982e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 983e2cb1decSSalil Mehta 984e2cb1decSSalil Mehta return rss_cfg->rss_size; 985e2cb1decSSalil Mehta } 986e2cb1decSSalil Mehta 987e2cb1decSSalil Mehta static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 988b204bc74SPeng Li int vector_id, 989e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 990e2cb1decSSalil Mehta { 991e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 992e2cb1decSSalil Mehta struct hnae3_ring_chain_node *node; 993e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 994e2cb1decSSalil Mehta struct hclgevf_desc desc; 995b204bc74SPeng Li int i = 0; 996e2cb1decSSalil Mehta int status; 997e2cb1decSSalil Mehta u8 type; 998e2cb1decSSalil Mehta 999e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1000e2cb1decSSalil Mehta 1001e2cb1decSSalil Mehta for (node = ring_chain; node; node = node->next) { 10025d02a58dSYunsheng Lin int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 10035d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 10045d02a58dSYunsheng Lin 10055d02a58dSYunsheng Lin if (i == 0) { 10065d02a58dSYunsheng Lin hclgevf_cmd_setup_basic_desc(&desc, 10075d02a58dSYunsheng Lin HCLGEVF_OPC_MBX_VF_TO_PF, 10085d02a58dSYunsheng Lin false); 10095d02a58dSYunsheng Lin type = en ? 10105d02a58dSYunsheng Lin HCLGE_MBX_MAP_RING_TO_VECTOR : 10115d02a58dSYunsheng Lin HCLGE_MBX_UNMAP_RING_TO_VECTOR; 10125d02a58dSYunsheng Lin req->msg[0] = type; 10135d02a58dSYunsheng Lin req->msg[1] = vector_id; 10145d02a58dSYunsheng Lin } 10155d02a58dSYunsheng Lin 10165d02a58dSYunsheng Lin req->msg[idx_offset] = 1017e4e87715SPeng Li hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 10185d02a58dSYunsheng Lin req->msg[idx_offset + 1] = node->tqp_index; 1019e4e87715SPeng Li req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 102079eee410SFuyun Liang HNAE3_RING_GL_IDX_M, 102179eee410SFuyun Liang HNAE3_RING_GL_IDX_S); 102279eee410SFuyun Liang 10235d02a58dSYunsheng Lin i++; 10245d02a58dSYunsheng Lin if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 10255d02a58dSYunsheng Lin HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 10265d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 10275d02a58dSYunsheng Lin !node->next) { 1028e2cb1decSSalil Mehta req->msg[2] = i; 1029e2cb1decSSalil Mehta 1030e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1031e2cb1decSSalil Mehta if (status) { 1032e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1033e2cb1decSSalil Mehta "Map TQP fail, status is %d.\n", 1034e2cb1decSSalil Mehta status); 1035e2cb1decSSalil Mehta return status; 1036e2cb1decSSalil Mehta } 1037e2cb1decSSalil Mehta i = 0; 1038e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 1039e2cb1decSSalil Mehta HCLGEVF_OPC_MBX_VF_TO_PF, 1040e2cb1decSSalil Mehta false); 1041e2cb1decSSalil Mehta req->msg[0] = type; 1042e2cb1decSSalil Mehta req->msg[1] = vector_id; 1043e2cb1decSSalil Mehta } 1044e2cb1decSSalil Mehta } 1045e2cb1decSSalil Mehta 1046e2cb1decSSalil Mehta return 0; 1047e2cb1decSSalil Mehta } 1048e2cb1decSSalil Mehta 1049e2cb1decSSalil Mehta static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1050e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1051e2cb1decSSalil Mehta { 1052b204bc74SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1053b204bc74SPeng Li int vector_id; 1054b204bc74SPeng Li 1055b204bc74SPeng Li vector_id = hclgevf_get_vector_index(hdev, vector); 1056b204bc74SPeng Li if (vector_id < 0) { 1057b204bc74SPeng Li dev_err(&handle->pdev->dev, 1058b204bc74SPeng Li "Get vector index fail. ret =%d\n", vector_id); 1059b204bc74SPeng Li return vector_id; 1060b204bc74SPeng Li } 1061b204bc74SPeng Li 1062b204bc74SPeng Li return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1063e2cb1decSSalil Mehta } 1064e2cb1decSSalil Mehta 1065e2cb1decSSalil Mehta static int hclgevf_unmap_ring_from_vector( 1066e2cb1decSSalil Mehta struct hnae3_handle *handle, 1067e2cb1decSSalil Mehta int vector, 1068e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1069e2cb1decSSalil Mehta { 1070e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1071e2cb1decSSalil Mehta int ret, vector_id; 1072e2cb1decSSalil Mehta 1073dea846e8SHuazhong Tan if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1074dea846e8SHuazhong Tan return 0; 1075dea846e8SHuazhong Tan 1076e2cb1decSSalil Mehta vector_id = hclgevf_get_vector_index(hdev, vector); 1077e2cb1decSSalil Mehta if (vector_id < 0) { 1078e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1079e2cb1decSSalil Mehta "Get vector index fail. ret =%d\n", vector_id); 1080e2cb1decSSalil Mehta return vector_id; 1081e2cb1decSSalil Mehta } 1082e2cb1decSSalil Mehta 1083b204bc74SPeng Li ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 10840d3e6631SYunsheng Lin if (ret) 1085e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1086e2cb1decSSalil Mehta "Unmap ring from vector fail. vector=%d, ret =%d\n", 1087e2cb1decSSalil Mehta vector_id, 1088e2cb1decSSalil Mehta ret); 10890d3e6631SYunsheng Lin 1090e2cb1decSSalil Mehta return ret; 1091e2cb1decSSalil Mehta } 1092e2cb1decSSalil Mehta 10930d3e6631SYunsheng Lin static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 10940d3e6631SYunsheng Lin { 10950d3e6631SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 109603718db9SYunsheng Lin int vector_id; 10970d3e6631SYunsheng Lin 109803718db9SYunsheng Lin vector_id = hclgevf_get_vector_index(hdev, vector); 109903718db9SYunsheng Lin if (vector_id < 0) { 110003718db9SYunsheng Lin dev_err(&handle->pdev->dev, 110103718db9SYunsheng Lin "hclgevf_put_vector get vector index fail. ret =%d\n", 110203718db9SYunsheng Lin vector_id); 110303718db9SYunsheng Lin return vector_id; 110403718db9SYunsheng Lin } 110503718db9SYunsheng Lin 110603718db9SYunsheng Lin hclgevf_free_vector(hdev, vector_id); 1107e2cb1decSSalil Mehta 1108e2cb1decSSalil Mehta return 0; 1109e2cb1decSSalil Mehta } 1110e2cb1decSSalil Mehta 11113b75c3dfSPeng Li static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1112f01f5559SJian Shen bool en_bc_pmc) 1113e2cb1decSSalil Mehta { 1114e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 1115e2cb1decSSalil Mehta struct hclgevf_desc desc; 1116f01f5559SJian Shen int ret; 1117e2cb1decSSalil Mehta 1118e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1119e2cb1decSSalil Mehta 1120e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 1121e2cb1decSSalil Mehta req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 1122f01f5559SJian Shen req->msg[1] = en_bc_pmc ? 1 : 0; 1123e2cb1decSSalil Mehta 1124f01f5559SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1125f01f5559SJian Shen if (ret) 1126e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1127f01f5559SJian Shen "Set promisc mode fail, status is %d.\n", ret); 1128e2cb1decSSalil Mehta 1129f01f5559SJian Shen return ret; 1130e2cb1decSSalil Mehta } 1131e2cb1decSSalil Mehta 1132f01f5559SJian Shen static int hclgevf_set_promisc_mode(struct hclgevf_dev *hdev, bool en_bc_pmc) 1133e2cb1decSSalil Mehta { 1134f01f5559SJian Shen return hclgevf_cmd_set_promisc_mode(hdev, en_bc_pmc); 1135e2cb1decSSalil Mehta } 1136e2cb1decSSalil Mehta 1137e2cb1decSSalil Mehta static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, int tqp_id, 1138e2cb1decSSalil Mehta int stream_id, bool enable) 1139e2cb1decSSalil Mehta { 1140e2cb1decSSalil Mehta struct hclgevf_cfg_com_tqp_queue_cmd *req; 1141e2cb1decSSalil Mehta struct hclgevf_desc desc; 1142e2cb1decSSalil Mehta int status; 1143e2cb1decSSalil Mehta 1144e2cb1decSSalil Mehta req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1145e2cb1decSSalil Mehta 1146e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1147e2cb1decSSalil Mehta false); 1148e2cb1decSSalil Mehta req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1149e2cb1decSSalil Mehta req->stream_id = cpu_to_le16(stream_id); 1150e2cb1decSSalil Mehta req->enable |= enable << HCLGEVF_TQP_ENABLE_B; 1151e2cb1decSSalil Mehta 1152e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1153e2cb1decSSalil Mehta if (status) 1154e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1155e2cb1decSSalil Mehta "TQP enable fail, status =%d.\n", status); 1156e2cb1decSSalil Mehta 1157e2cb1decSSalil Mehta return status; 1158e2cb1decSSalil Mehta } 1159e2cb1decSSalil Mehta 1160e2cb1decSSalil Mehta static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1161e2cb1decSSalil Mehta { 1162b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1163e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 1164e2cb1decSSalil Mehta int i; 1165e2cb1decSSalil Mehta 1166b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 1167b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1168e2cb1decSSalil Mehta memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1169e2cb1decSSalil Mehta } 1170e2cb1decSSalil Mehta } 1171e2cb1decSSalil Mehta 1172e2cb1decSSalil Mehta static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1173e2cb1decSSalil Mehta { 1174e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1175e2cb1decSSalil Mehta 1176e2cb1decSSalil Mehta ether_addr_copy(p, hdev->hw.mac.mac_addr); 1177e2cb1decSSalil Mehta } 1178e2cb1decSSalil Mehta 117959098055SFuyun Liang static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 118059098055SFuyun Liang bool is_first) 1181e2cb1decSSalil Mehta { 1182e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1183e2cb1decSSalil Mehta u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1184e2cb1decSSalil Mehta u8 *new_mac_addr = (u8 *)p; 1185e2cb1decSSalil Mehta u8 msg_data[ETH_ALEN * 2]; 118659098055SFuyun Liang u16 subcode; 1187e2cb1decSSalil Mehta int status; 1188e2cb1decSSalil Mehta 1189e2cb1decSSalil Mehta ether_addr_copy(msg_data, new_mac_addr); 1190e2cb1decSSalil Mehta ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 1191e2cb1decSSalil Mehta 119259098055SFuyun Liang subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 119359098055SFuyun Liang HCLGE_MBX_MAC_VLAN_UC_MODIFY; 119459098055SFuyun Liang 1195e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 119659098055SFuyun Liang subcode, msg_data, ETH_ALEN * 2, 11972097fdefSJian Shen true, NULL, 0); 1198e2cb1decSSalil Mehta if (!status) 1199e2cb1decSSalil Mehta ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1200e2cb1decSSalil Mehta 1201e2cb1decSSalil Mehta return status; 1202e2cb1decSSalil Mehta } 1203e2cb1decSSalil Mehta 1204e2cb1decSSalil Mehta static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1205e2cb1decSSalil Mehta const unsigned char *addr) 1206e2cb1decSSalil Mehta { 1207e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1208e2cb1decSSalil Mehta 1209e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1210e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_ADD, 1211e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1212e2cb1decSSalil Mehta } 1213e2cb1decSSalil Mehta 1214e2cb1decSSalil Mehta static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1215e2cb1decSSalil Mehta const unsigned char *addr) 1216e2cb1decSSalil Mehta { 1217e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1218e2cb1decSSalil Mehta 1219e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1220e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1221e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1222e2cb1decSSalil Mehta } 1223e2cb1decSSalil Mehta 1224e2cb1decSSalil Mehta static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1225e2cb1decSSalil Mehta const unsigned char *addr) 1226e2cb1decSSalil Mehta { 1227e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1228e2cb1decSSalil Mehta 1229e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1230e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_ADD, 1231e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1232e2cb1decSSalil Mehta } 1233e2cb1decSSalil Mehta 1234e2cb1decSSalil Mehta static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1235e2cb1decSSalil Mehta const unsigned char *addr) 1236e2cb1decSSalil Mehta { 1237e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1238e2cb1decSSalil Mehta 1239e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1240e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1241e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1242e2cb1decSSalil Mehta } 1243e2cb1decSSalil Mehta 1244e2cb1decSSalil Mehta static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1245e2cb1decSSalil Mehta __be16 proto, u16 vlan_id, 1246e2cb1decSSalil Mehta bool is_kill) 1247e2cb1decSSalil Mehta { 1248e2cb1decSSalil Mehta #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1249e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1250e2cb1decSSalil Mehta u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1251e2cb1decSSalil Mehta 1252e2cb1decSSalil Mehta if (vlan_id > 4095) 1253e2cb1decSSalil Mehta return -EINVAL; 1254e2cb1decSSalil Mehta 1255e2cb1decSSalil Mehta if (proto != htons(ETH_P_8021Q)) 1256e2cb1decSSalil Mehta return -EPROTONOSUPPORT; 1257e2cb1decSSalil Mehta 1258e2cb1decSSalil Mehta msg_data[0] = is_kill; 1259e2cb1decSSalil Mehta memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1260e2cb1decSSalil Mehta memcpy(&msg_data[3], &proto, sizeof(proto)); 1261e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1262e2cb1decSSalil Mehta HCLGE_MBX_VLAN_FILTER, msg_data, 1263e2cb1decSSalil Mehta HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 1264e2cb1decSSalil Mehta } 1265e2cb1decSSalil Mehta 1266b2641e2aSYunsheng Lin static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1267b2641e2aSYunsheng Lin { 1268b2641e2aSYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1269b2641e2aSYunsheng Lin u8 msg_data; 1270b2641e2aSYunsheng Lin 1271b2641e2aSYunsheng Lin msg_data = enable ? 1 : 0; 1272b2641e2aSYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1273b2641e2aSYunsheng Lin HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1274b2641e2aSYunsheng Lin 1, false, NULL, 0); 1275b2641e2aSYunsheng Lin } 1276b2641e2aSYunsheng Lin 12777fa6be4fSHuazhong Tan static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1278e2cb1decSSalil Mehta { 1279e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1280e2cb1decSSalil Mehta u8 msg_data[2]; 12811a426f8bSPeng Li int ret; 1282e2cb1decSSalil Mehta 1283e2cb1decSSalil Mehta memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 1284e2cb1decSSalil Mehta 12851a426f8bSPeng Li /* disable vf queue before send queue reset msg to PF */ 12861a426f8bSPeng Li ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 12871a426f8bSPeng Li if (ret) 12887fa6be4fSHuazhong Tan return ret; 12891a426f8bSPeng Li 12907fa6be4fSHuazhong Tan return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 12911a426f8bSPeng Li 2, true, NULL, 0); 1292e2cb1decSSalil Mehta } 1293e2cb1decSSalil Mehta 1294818f1675SYunsheng Lin static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1295818f1675SYunsheng Lin { 1296818f1675SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1297818f1675SYunsheng Lin 1298818f1675SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu, 1299818f1675SYunsheng Lin sizeof(new_mtu), true, NULL, 0); 1300818f1675SYunsheng Lin } 1301818f1675SYunsheng Lin 13026988eb2aSSalil Mehta static int hclgevf_notify_client(struct hclgevf_dev *hdev, 13036988eb2aSSalil Mehta enum hnae3_reset_notify_type type) 13046988eb2aSSalil Mehta { 13056988eb2aSSalil Mehta struct hnae3_client *client = hdev->nic_client; 13066988eb2aSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 13076a5f6fa3SHuazhong Tan int ret; 13086988eb2aSSalil Mehta 13096988eb2aSSalil Mehta if (!client->ops->reset_notify) 13106988eb2aSSalil Mehta return -EOPNOTSUPP; 13116988eb2aSSalil Mehta 13126a5f6fa3SHuazhong Tan ret = client->ops->reset_notify(handle, type); 13136a5f6fa3SHuazhong Tan if (ret) 13146a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 13156a5f6fa3SHuazhong Tan type, ret); 13166a5f6fa3SHuazhong Tan 13176a5f6fa3SHuazhong Tan return ret; 13186988eb2aSSalil Mehta } 13196988eb2aSSalil Mehta 13206ff3cf07SHuazhong Tan static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 13216ff3cf07SHuazhong Tan { 13226ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 13236ff3cf07SHuazhong Tan 13246ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DONE, &hdev->flr_state); 13256ff3cf07SHuazhong Tan } 13266ff3cf07SHuazhong Tan 13276ff3cf07SHuazhong Tan static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev, 13286ff3cf07SHuazhong Tan unsigned long delay_us, 13296ff3cf07SHuazhong Tan unsigned long wait_cnt) 13306ff3cf07SHuazhong Tan { 13316ff3cf07SHuazhong Tan unsigned long cnt = 0; 13326ff3cf07SHuazhong Tan 13336ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) && 13346ff3cf07SHuazhong Tan cnt++ < wait_cnt) 13356ff3cf07SHuazhong Tan usleep_range(delay_us, delay_us * 2); 13366ff3cf07SHuazhong Tan 13376ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) { 13386ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 13396ff3cf07SHuazhong Tan "flr wait timeout\n"); 13406ff3cf07SHuazhong Tan return -ETIMEDOUT; 13416ff3cf07SHuazhong Tan } 13426ff3cf07SHuazhong Tan 13436ff3cf07SHuazhong Tan return 0; 13446ff3cf07SHuazhong Tan } 13456ff3cf07SHuazhong Tan 13466988eb2aSSalil Mehta static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 13476988eb2aSSalil Mehta { 1348aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_US 20000 1349aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_CNT 2000 1350aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1351aa5c4f17SHuazhong Tan (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1352aa5c4f17SHuazhong Tan 1353aa5c4f17SHuazhong Tan u32 val; 1354aa5c4f17SHuazhong Tan int ret; 13556988eb2aSSalil Mehta 13566988eb2aSSalil Mehta /* wait to check the hardware reset completion status */ 1357aa5c4f17SHuazhong Tan val = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1358aa5c4f17SHuazhong Tan dev_info(&hdev->pdev->dev, "checking vf resetting status: %x\n", val); 1359aa5c4f17SHuazhong Tan 13606ff3cf07SHuazhong Tan if (hdev->reset_type == HNAE3_FLR_RESET) 13616ff3cf07SHuazhong Tan return hclgevf_flr_poll_timeout(hdev, 13626ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_US, 13636ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_CNT); 13646ff3cf07SHuazhong Tan 1365aa5c4f17SHuazhong Tan ret = readl_poll_timeout(hdev->hw.io_base + HCLGEVF_RST_ING, val, 1366aa5c4f17SHuazhong Tan !(val & HCLGEVF_RST_ING_BITS), 1367aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_US, 1368aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 13696988eb2aSSalil Mehta 13706988eb2aSSalil Mehta /* hardware completion status should be available by this time */ 1371aa5c4f17SHuazhong Tan if (ret) { 1372aa5c4f17SHuazhong Tan dev_err(&hdev->pdev->dev, 13736988eb2aSSalil Mehta "could'nt get reset done status from h/w, timeout!\n"); 1374aa5c4f17SHuazhong Tan return ret; 13756988eb2aSSalil Mehta } 13766988eb2aSSalil Mehta 13776988eb2aSSalil Mehta /* we will wait a bit more to let reset of the stack to complete. This 13786988eb2aSSalil Mehta * might happen in case reset assertion was made by PF. Yes, this also 13796988eb2aSSalil Mehta * means we might end up waiting bit more even for VF reset. 13806988eb2aSSalil Mehta */ 13816988eb2aSSalil Mehta msleep(5000); 13826988eb2aSSalil Mehta 13836988eb2aSSalil Mehta return 0; 13846988eb2aSSalil Mehta } 13856988eb2aSSalil Mehta 13866988eb2aSSalil Mehta static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 13876988eb2aSSalil Mehta { 13887a01c897SSalil Mehta int ret; 13897a01c897SSalil Mehta 13906988eb2aSSalil Mehta /* uninitialize the nic client */ 13916a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 13926a5f6fa3SHuazhong Tan if (ret) 13936a5f6fa3SHuazhong Tan return ret; 13946988eb2aSSalil Mehta 13957a01c897SSalil Mehta /* re-initialize the hclge device */ 13969c6f7085SHuazhong Tan ret = hclgevf_reset_hdev(hdev); 13977a01c897SSalil Mehta if (ret) { 13987a01c897SSalil Mehta dev_err(&hdev->pdev->dev, 13997a01c897SSalil Mehta "hclge device re-init failed, VF is disabled!\n"); 14007a01c897SSalil Mehta return ret; 14017a01c897SSalil Mehta } 14026988eb2aSSalil Mehta 14036988eb2aSSalil Mehta /* bring up the nic client again */ 14046a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 14056a5f6fa3SHuazhong Tan if (ret) 14066a5f6fa3SHuazhong Tan return ret; 14076988eb2aSSalil Mehta 14081f609492SYunsheng Lin return hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT); 14096988eb2aSSalil Mehta } 14106988eb2aSSalil Mehta 1411dea846e8SHuazhong Tan static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1412dea846e8SHuazhong Tan { 1413dea846e8SHuazhong Tan int ret = 0; 1414dea846e8SHuazhong Tan 1415dea846e8SHuazhong Tan switch (hdev->reset_type) { 1416dea846e8SHuazhong Tan case HNAE3_VF_FUNC_RESET: 1417dea846e8SHuazhong Tan ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1418dea846e8SHuazhong Tan 0, true, NULL, sizeof(u8)); 1419c88a6e7dSHuazhong Tan hdev->rst_stats.vf_func_rst_cnt++; 1420dea846e8SHuazhong Tan break; 14216ff3cf07SHuazhong Tan case HNAE3_FLR_RESET: 14226ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1423c88a6e7dSHuazhong Tan hdev->rst_stats.flr_rst_cnt++; 14246ff3cf07SHuazhong Tan break; 1425dea846e8SHuazhong Tan default: 1426dea846e8SHuazhong Tan break; 1427dea846e8SHuazhong Tan } 1428dea846e8SHuazhong Tan 1429ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1430ef5f8e50SHuazhong Tan 1431dea846e8SHuazhong Tan dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1432dea846e8SHuazhong Tan hdev->reset_type, ret); 1433dea846e8SHuazhong Tan 1434dea846e8SHuazhong Tan return ret; 1435dea846e8SHuazhong Tan } 1436dea846e8SHuazhong Tan 14376988eb2aSSalil Mehta static int hclgevf_reset(struct hclgevf_dev *hdev) 14386988eb2aSSalil Mehta { 1439dea846e8SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 14406988eb2aSSalil Mehta int ret; 14416988eb2aSSalil Mehta 1442dea846e8SHuazhong Tan /* Initialize ae_dev reset status as well, in case enet layer wants to 1443dea846e8SHuazhong Tan * know if device is undergoing reset 1444dea846e8SHuazhong Tan */ 1445dea846e8SHuazhong Tan ae_dev->reset_type = hdev->reset_type; 1446c88a6e7dSHuazhong Tan hdev->rst_stats.rst_cnt++; 14476988eb2aSSalil Mehta rtnl_lock(); 14486988eb2aSSalil Mehta 14496988eb2aSSalil Mehta /* bring down the nic to stop any ongoing TX/RX */ 14506a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 14516a5f6fa3SHuazhong Tan if (ret) 14526a5f6fa3SHuazhong Tan goto err_reset_lock; 14536988eb2aSSalil Mehta 145429118ab9SHuazhong Tan rtnl_unlock(); 145529118ab9SHuazhong Tan 14566a5f6fa3SHuazhong Tan ret = hclgevf_reset_prepare_wait(hdev); 14576a5f6fa3SHuazhong Tan if (ret) 14586a5f6fa3SHuazhong Tan goto err_reset; 1459dea846e8SHuazhong Tan 14606988eb2aSSalil Mehta /* check if VF could successfully fetch the hardware reset completion 14616988eb2aSSalil Mehta * status from the hardware 14626988eb2aSSalil Mehta */ 14636988eb2aSSalil Mehta ret = hclgevf_reset_wait(hdev); 14646988eb2aSSalil Mehta if (ret) { 14656988eb2aSSalil Mehta /* can't do much in this situation, will disable VF */ 14666988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, 14676988eb2aSSalil Mehta "VF failed(=%d) to fetch H/W reset completion status\n", 14686988eb2aSSalil Mehta ret); 14696a5f6fa3SHuazhong Tan goto err_reset; 14706988eb2aSSalil Mehta } 14716988eb2aSSalil Mehta 1472c88a6e7dSHuazhong Tan hdev->rst_stats.hw_rst_done_cnt++; 1473c88a6e7dSHuazhong Tan 147429118ab9SHuazhong Tan rtnl_lock(); 147529118ab9SHuazhong Tan 14766988eb2aSSalil Mehta /* now, re-initialize the nic client and ae device*/ 14776988eb2aSSalil Mehta ret = hclgevf_reset_stack(hdev); 14786a5f6fa3SHuazhong Tan if (ret) { 14796988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 14806a5f6fa3SHuazhong Tan goto err_reset_lock; 14816a5f6fa3SHuazhong Tan } 14826988eb2aSSalil Mehta 14836988eb2aSSalil Mehta /* bring up the nic to enable TX/RX again */ 14846a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 14856a5f6fa3SHuazhong Tan if (ret) 14866a5f6fa3SHuazhong Tan goto err_reset_lock; 14876988eb2aSSalil Mehta 14886988eb2aSSalil Mehta rtnl_unlock(); 14896988eb2aSSalil Mehta 1490b644a8d4SHuazhong Tan hdev->last_reset_time = jiffies; 1491b644a8d4SHuazhong Tan ae_dev->reset_type = HNAE3_NONE_RESET; 1492c88a6e7dSHuazhong Tan hdev->rst_stats.rst_done_cnt++; 1493b644a8d4SHuazhong Tan 14946988eb2aSSalil Mehta return ret; 14956a5f6fa3SHuazhong Tan err_reset_lock: 14966a5f6fa3SHuazhong Tan rtnl_unlock(); 14976a5f6fa3SHuazhong Tan err_reset: 14986a5f6fa3SHuazhong Tan /* When VF reset failed, only the higher level reset asserted by PF 14996a5f6fa3SHuazhong Tan * can restore it, so re-initialize the command queue to receive 15006a5f6fa3SHuazhong Tan * this higher reset event. 15016a5f6fa3SHuazhong Tan */ 15026a5f6fa3SHuazhong Tan hclgevf_cmd_init(hdev); 15036a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "failed to reset VF\n"); 1504cf1f2129SHuazhong Tan if (hclgevf_is_reset_pending(hdev)) 1505cf1f2129SHuazhong Tan hclgevf_reset_task_schedule(hdev); 15066a5f6fa3SHuazhong Tan 15076a5f6fa3SHuazhong Tan return ret; 15086988eb2aSSalil Mehta } 15096988eb2aSSalil Mehta 1510720bd583SHuazhong Tan static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1511720bd583SHuazhong Tan unsigned long *addr) 1512720bd583SHuazhong Tan { 1513720bd583SHuazhong Tan enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1514720bd583SHuazhong Tan 1515dea846e8SHuazhong Tan /* return the highest priority reset level amongst all */ 1516b90fcc5bSHuazhong Tan if (test_bit(HNAE3_VF_RESET, addr)) { 1517b90fcc5bSHuazhong Tan rst_level = HNAE3_VF_RESET; 1518b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_RESET, addr); 1519b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1520b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1521b90fcc5bSHuazhong Tan } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1522dea846e8SHuazhong Tan rst_level = HNAE3_VF_FULL_RESET; 1523dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FULL_RESET, addr); 1524dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1525aa5c4f17SHuazhong Tan } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1526aa5c4f17SHuazhong Tan rst_level = HNAE3_VF_PF_FUNC_RESET; 1527aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1528aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1529dea846e8SHuazhong Tan } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1530dea846e8SHuazhong Tan rst_level = HNAE3_VF_FUNC_RESET; 1531dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 15326ff3cf07SHuazhong Tan } else if (test_bit(HNAE3_FLR_RESET, addr)) { 15336ff3cf07SHuazhong Tan rst_level = HNAE3_FLR_RESET; 15346ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_RESET, addr); 1535720bd583SHuazhong Tan } 1536720bd583SHuazhong Tan 1537720bd583SHuazhong Tan return rst_level; 1538720bd583SHuazhong Tan } 1539720bd583SHuazhong Tan 15406ae4e733SShiju Jose static void hclgevf_reset_event(struct pci_dev *pdev, 15416ae4e733SShiju Jose struct hnae3_handle *handle) 15426d4c3981SSalil Mehta { 15436ff3cf07SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 15446ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 15456d4c3981SSalil Mehta 15466d4c3981SSalil Mehta dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 15476d4c3981SSalil Mehta 15486ff3cf07SHuazhong Tan if (hdev->default_reset_request) 15490742ed7cSHuazhong Tan hdev->reset_level = 1550720bd583SHuazhong Tan hclgevf_get_reset_level(hdev, 1551720bd583SHuazhong Tan &hdev->default_reset_request); 1552720bd583SHuazhong Tan else 1553dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 15546d4c3981SSalil Mehta 1555436667d2SSalil Mehta /* reset of this VF requested */ 1556436667d2SSalil Mehta set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1557436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 15586d4c3981SSalil Mehta 15590742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 15606d4c3981SSalil Mehta } 15616d4c3981SSalil Mehta 1562720bd583SHuazhong Tan static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1563720bd583SHuazhong Tan enum hnae3_reset_type rst_type) 1564720bd583SHuazhong Tan { 1565720bd583SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1566720bd583SHuazhong Tan 1567720bd583SHuazhong Tan set_bit(rst_type, &hdev->default_reset_request); 1568720bd583SHuazhong Tan } 1569720bd583SHuazhong Tan 15706ff3cf07SHuazhong Tan static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 15716ff3cf07SHuazhong Tan { 15726ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_MS 100 15736ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_CNT 50 15746ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 15756ff3cf07SHuazhong Tan int cnt = 0; 15766ff3cf07SHuazhong Tan 15776ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 15786ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DONE, &hdev->flr_state); 15796ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request); 15806ff3cf07SHuazhong Tan hclgevf_reset_event(hdev->pdev, NULL); 15816ff3cf07SHuazhong Tan 15826ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) && 15836ff3cf07SHuazhong Tan cnt++ < HCLGEVF_FLR_WAIT_CNT) 15846ff3cf07SHuazhong Tan msleep(HCLGEVF_FLR_WAIT_MS); 15856ff3cf07SHuazhong Tan 15866ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state)) 15876ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 15886ff3cf07SHuazhong Tan "flr wait down timeout: %d\n", cnt); 15896ff3cf07SHuazhong Tan } 15906ff3cf07SHuazhong Tan 1591e2cb1decSSalil Mehta static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1592e2cb1decSSalil Mehta { 1593e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1594e2cb1decSSalil Mehta 1595e2cb1decSSalil Mehta return hdev->fw_version; 1596e2cb1decSSalil Mehta } 1597e2cb1decSSalil Mehta 1598e2cb1decSSalil Mehta static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1599e2cb1decSSalil Mehta { 1600e2cb1decSSalil Mehta struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1601e2cb1decSSalil Mehta 1602e2cb1decSSalil Mehta vector->vector_irq = pci_irq_vector(hdev->pdev, 1603e2cb1decSSalil Mehta HCLGEVF_MISC_VECTOR_NUM); 1604e2cb1decSSalil Mehta vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1605e2cb1decSSalil Mehta /* vector status always valid for Vector 0 */ 1606e2cb1decSSalil Mehta hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1607e2cb1decSSalil Mehta hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1608e2cb1decSSalil Mehta 1609e2cb1decSSalil Mehta hdev->num_msi_left -= 1; 1610e2cb1decSSalil Mehta hdev->num_msi_used += 1; 1611e2cb1decSSalil Mehta } 1612e2cb1decSSalil Mehta 161335a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 161435a1e503SSalil Mehta { 16157d600706SHuazhong Tan if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state)) { 161635a1e503SSalil Mehta set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 161735a1e503SSalil Mehta schedule_work(&hdev->rst_service_task); 161835a1e503SSalil Mehta } 161935a1e503SSalil Mehta } 162035a1e503SSalil Mehta 162107a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1622e2cb1decSSalil Mehta { 162307a0556aSSalil Mehta if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) && 162407a0556aSSalil Mehta !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) { 162507a0556aSSalil Mehta set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1626e2cb1decSSalil Mehta schedule_work(&hdev->mbx_service_task); 1627e2cb1decSSalil Mehta } 162807a0556aSSalil Mehta } 1629e2cb1decSSalil Mehta 1630e2cb1decSSalil Mehta static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 1631e2cb1decSSalil Mehta { 1632e2cb1decSSalil Mehta if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 1633e2cb1decSSalil Mehta !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 1634e2cb1decSSalil Mehta schedule_work(&hdev->service_task); 1635e2cb1decSSalil Mehta } 1636e2cb1decSSalil Mehta 1637436667d2SSalil Mehta static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev) 1638436667d2SSalil Mehta { 163907a0556aSSalil Mehta /* if we have any pending mailbox event then schedule the mbx task */ 164007a0556aSSalil Mehta if (hdev->mbx_event_pending) 164107a0556aSSalil Mehta hclgevf_mbx_task_schedule(hdev); 164207a0556aSSalil Mehta 1643436667d2SSalil Mehta if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state)) 1644436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 1645436667d2SSalil Mehta } 1646436667d2SSalil Mehta 1647e2cb1decSSalil Mehta static void hclgevf_service_timer(struct timer_list *t) 1648e2cb1decSSalil Mehta { 1649e2cb1decSSalil Mehta struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 1650e2cb1decSSalil Mehta 1651e2cb1decSSalil Mehta mod_timer(&hdev->service_timer, jiffies + 5 * HZ); 1652e2cb1decSSalil Mehta 1653db01afebSliuzhongzhu hdev->stats_timer++; 1654e2cb1decSSalil Mehta hclgevf_task_schedule(hdev); 1655e2cb1decSSalil Mehta } 1656e2cb1decSSalil Mehta 165735a1e503SSalil Mehta static void hclgevf_reset_service_task(struct work_struct *work) 165835a1e503SSalil Mehta { 165935a1e503SSalil Mehta struct hclgevf_dev *hdev = 166035a1e503SSalil Mehta container_of(work, struct hclgevf_dev, rst_service_task); 1661a8dedb65SSalil Mehta int ret; 166235a1e503SSalil Mehta 166335a1e503SSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 166435a1e503SSalil Mehta return; 166535a1e503SSalil Mehta 166635a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 166735a1e503SSalil Mehta 1668436667d2SSalil Mehta if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1669436667d2SSalil Mehta &hdev->reset_state)) { 1670436667d2SSalil Mehta /* PF has initmated that it is about to reset the hardware. 1671436667d2SSalil Mehta * We now have to poll & check if harware has actually completed 1672436667d2SSalil Mehta * the reset sequence. On hardware reset completion, VF needs to 1673436667d2SSalil Mehta * reset the client and ae device. 167435a1e503SSalil Mehta */ 1675436667d2SSalil Mehta hdev->reset_attempts = 0; 1676436667d2SSalil Mehta 1677dea846e8SHuazhong Tan hdev->last_reset_time = jiffies; 1678dea846e8SHuazhong Tan while ((hdev->reset_type = 1679dea846e8SHuazhong Tan hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 1680dea846e8SHuazhong Tan != HNAE3_NONE_RESET) { 16816988eb2aSSalil Mehta ret = hclgevf_reset(hdev); 16826988eb2aSSalil Mehta if (ret) 1683dea846e8SHuazhong Tan dev_err(&hdev->pdev->dev, 1684dea846e8SHuazhong Tan "VF stack reset failed %d.\n", ret); 1685dea846e8SHuazhong Tan } 1686436667d2SSalil Mehta } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1687436667d2SSalil Mehta &hdev->reset_state)) { 1688436667d2SSalil Mehta /* we could be here when either of below happens: 1689436667d2SSalil Mehta * 1. reset was initiated due to watchdog timeout due to 1690436667d2SSalil Mehta * a. IMP was earlier reset and our TX got choked down and 1691436667d2SSalil Mehta * which resulted in watchdog reacting and inducing VF 1692436667d2SSalil Mehta * reset. This also means our cmdq would be unreliable. 1693436667d2SSalil Mehta * b. problem in TX due to other lower layer(example link 1694436667d2SSalil Mehta * layer not functioning properly etc.) 1695436667d2SSalil Mehta * 2. VF reset might have been initiated due to some config 1696436667d2SSalil Mehta * change. 1697436667d2SSalil Mehta * 1698436667d2SSalil Mehta * NOTE: Theres no clear way to detect above cases than to react 1699436667d2SSalil Mehta * to the response of PF for this reset request. PF will ack the 1700436667d2SSalil Mehta * 1b and 2. cases but we will not get any intimation about 1a 1701436667d2SSalil Mehta * from PF as cmdq would be in unreliable state i.e. mailbox 1702436667d2SSalil Mehta * communication between PF and VF would be broken. 1703436667d2SSalil Mehta */ 1704436667d2SSalil Mehta 1705436667d2SSalil Mehta /* if we are never geting into pending state it means either: 1706436667d2SSalil Mehta * 1. PF is not receiving our request which could be due to IMP 1707436667d2SSalil Mehta * reset 1708436667d2SSalil Mehta * 2. PF is screwed 1709436667d2SSalil Mehta * We cannot do much for 2. but to check first we can try reset 1710436667d2SSalil Mehta * our PCIe + stack and see if it alleviates the problem. 1711436667d2SSalil Mehta */ 1712436667d2SSalil Mehta if (hdev->reset_attempts > 3) { 1713436667d2SSalil Mehta /* prepare for full reset of stack + pcie interface */ 1714dea846e8SHuazhong Tan set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1715436667d2SSalil Mehta 1716436667d2SSalil Mehta /* "defer" schedule the reset task again */ 1717436667d2SSalil Mehta set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1718436667d2SSalil Mehta } else { 1719436667d2SSalil Mehta hdev->reset_attempts++; 1720436667d2SSalil Mehta 1721dea846e8SHuazhong Tan set_bit(hdev->reset_level, &hdev->reset_pending); 1722dea846e8SHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1723436667d2SSalil Mehta } 1724dea846e8SHuazhong Tan hclgevf_reset_task_schedule(hdev); 1725436667d2SSalil Mehta } 172635a1e503SSalil Mehta 172735a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 172835a1e503SSalil Mehta } 172935a1e503SSalil Mehta 1730e2cb1decSSalil Mehta static void hclgevf_mailbox_service_task(struct work_struct *work) 1731e2cb1decSSalil Mehta { 1732e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1733e2cb1decSSalil Mehta 1734e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 1735e2cb1decSSalil Mehta 1736e2cb1decSSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1737e2cb1decSSalil Mehta return; 1738e2cb1decSSalil Mehta 1739e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1740e2cb1decSSalil Mehta 174107a0556aSSalil Mehta hclgevf_mbx_async_handler(hdev); 1742e2cb1decSSalil Mehta 1743e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1744e2cb1decSSalil Mehta } 1745e2cb1decSSalil Mehta 1746a6d818e3SYunsheng Lin static void hclgevf_keep_alive_timer(struct timer_list *t) 1747a6d818e3SYunsheng Lin { 1748a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = from_timer(hdev, t, keep_alive_timer); 1749a6d818e3SYunsheng Lin 1750a6d818e3SYunsheng Lin schedule_work(&hdev->keep_alive_task); 1751a6d818e3SYunsheng Lin mod_timer(&hdev->keep_alive_timer, jiffies + 2 * HZ); 1752a6d818e3SYunsheng Lin } 1753a6d818e3SYunsheng Lin 1754a6d818e3SYunsheng Lin static void hclgevf_keep_alive_task(struct work_struct *work) 1755a6d818e3SYunsheng Lin { 1756a6d818e3SYunsheng Lin struct hclgevf_dev *hdev; 1757a6d818e3SYunsheng Lin u8 respmsg; 1758a6d818e3SYunsheng Lin int ret; 1759a6d818e3SYunsheng Lin 1760a6d818e3SYunsheng Lin hdev = container_of(work, struct hclgevf_dev, keep_alive_task); 1761c59a85c0SJian Shen 17621416d333SHuazhong Tan if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 1763c59a85c0SJian Shen return; 1764c59a85c0SJian Shen 1765a6d818e3SYunsheng Lin ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL, 1766a6d818e3SYunsheng Lin 0, false, &respmsg, sizeof(u8)); 1767a6d818e3SYunsheng Lin if (ret) 1768a6d818e3SYunsheng Lin dev_err(&hdev->pdev->dev, 1769a6d818e3SYunsheng Lin "VF sends keep alive cmd failed(=%d)\n", ret); 1770a6d818e3SYunsheng Lin } 1771a6d818e3SYunsheng Lin 1772e2cb1decSSalil Mehta static void hclgevf_service_task(struct work_struct *work) 1773e2cb1decSSalil Mehta { 1774db01afebSliuzhongzhu struct hnae3_handle *handle; 1775e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1776e2cb1decSSalil Mehta 1777e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, service_task); 1778db01afebSliuzhongzhu handle = &hdev->nic; 1779db01afebSliuzhongzhu 1780db01afebSliuzhongzhu if (hdev->stats_timer >= HCLGEVF_STATS_TIMER_INTERVAL) { 1781db01afebSliuzhongzhu hclgevf_tqps_update_stats(handle); 1782db01afebSliuzhongzhu hdev->stats_timer = 0; 1783db01afebSliuzhongzhu } 1784e2cb1decSSalil Mehta 1785e2cb1decSSalil Mehta /* request the link status from the PF. PF would be able to tell VF 1786e2cb1decSSalil Mehta * about such updates in future so we might remove this later 1787e2cb1decSSalil Mehta */ 1788e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1789e2cb1decSSalil Mehta 17909194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 17919194d18bSliuzhongzhu 1792436667d2SSalil Mehta hclgevf_deferred_task_schedule(hdev); 1793436667d2SSalil Mehta 1794e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1795e2cb1decSSalil Mehta } 1796e2cb1decSSalil Mehta 1797e2cb1decSSalil Mehta static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1798e2cb1decSSalil Mehta { 1799e2cb1decSSalil Mehta hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1800e2cb1decSSalil Mehta } 1801e2cb1decSSalil Mehta 1802b90fcc5bSHuazhong Tan static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1803b90fcc5bSHuazhong Tan u32 *clearval) 1804e2cb1decSSalil Mehta { 1805b90fcc5bSHuazhong Tan u32 cmdq_src_reg, rst_ing_reg; 1806e2cb1decSSalil Mehta 1807e2cb1decSSalil Mehta /* fetch the events from their corresponding regs */ 1808e2cb1decSSalil Mehta cmdq_src_reg = hclgevf_read_dev(&hdev->hw, 1809e2cb1decSSalil Mehta HCLGEVF_VECTOR0_CMDQ_SRC_REG); 1810e2cb1decSSalil Mehta 1811b90fcc5bSHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_src_reg) { 1812b90fcc5bSHuazhong Tan rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1813b90fcc5bSHuazhong Tan dev_info(&hdev->pdev->dev, 1814b90fcc5bSHuazhong Tan "receive reset interrupt 0x%x!\n", rst_ing_reg); 1815b90fcc5bSHuazhong Tan set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1816b90fcc5bSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1817ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1818b90fcc5bSHuazhong Tan cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RST_INT_B); 1819b90fcc5bSHuazhong Tan *clearval = cmdq_src_reg; 1820c88a6e7dSHuazhong Tan hdev->rst_stats.vf_rst_cnt++; 1821b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_RST; 1822b90fcc5bSHuazhong Tan } 1823b90fcc5bSHuazhong Tan 1824e2cb1decSSalil Mehta /* check for vector0 mailbox(=CMDQ RX) event source */ 1825e2cb1decSSalil Mehta if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 1826e2cb1decSSalil Mehta cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1827e2cb1decSSalil Mehta *clearval = cmdq_src_reg; 1828b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_MBX; 1829e2cb1decSSalil Mehta } 1830e2cb1decSSalil Mehta 1831e2cb1decSSalil Mehta dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 1832e2cb1decSSalil Mehta 1833b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_OTHER; 1834e2cb1decSSalil Mehta } 1835e2cb1decSSalil Mehta 1836e2cb1decSSalil Mehta static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1837e2cb1decSSalil Mehta { 1838e2cb1decSSalil Mehta writel(en ? 1 : 0, vector->addr); 1839e2cb1decSSalil Mehta } 1840e2cb1decSSalil Mehta 1841e2cb1decSSalil Mehta static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1842e2cb1decSSalil Mehta { 1843b90fcc5bSHuazhong Tan enum hclgevf_evt_cause event_cause; 1844e2cb1decSSalil Mehta struct hclgevf_dev *hdev = data; 1845e2cb1decSSalil Mehta u32 clearval; 1846e2cb1decSSalil Mehta 1847e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 1848b90fcc5bSHuazhong Tan event_cause = hclgevf_check_evt_cause(hdev, &clearval); 1849e2cb1decSSalil Mehta 1850b90fcc5bSHuazhong Tan switch (event_cause) { 1851b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_RST: 1852b90fcc5bSHuazhong Tan hclgevf_reset_task_schedule(hdev); 1853b90fcc5bSHuazhong Tan break; 1854b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_MBX: 185507a0556aSSalil Mehta hclgevf_mbx_handler(hdev); 1856b90fcc5bSHuazhong Tan break; 1857b90fcc5bSHuazhong Tan default: 1858b90fcc5bSHuazhong Tan break; 1859b90fcc5bSHuazhong Tan } 1860e2cb1decSSalil Mehta 1861b90fcc5bSHuazhong Tan if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 1862e2cb1decSSalil Mehta hclgevf_clear_event_cause(hdev, clearval); 1863e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 1864b90fcc5bSHuazhong Tan } 1865e2cb1decSSalil Mehta 1866e2cb1decSSalil Mehta return IRQ_HANDLED; 1867e2cb1decSSalil Mehta } 1868e2cb1decSSalil Mehta 1869e2cb1decSSalil Mehta static int hclgevf_configure(struct hclgevf_dev *hdev) 1870e2cb1decSSalil Mehta { 1871e2cb1decSSalil Mehta int ret; 1872e2cb1decSSalil Mehta 187392f11ea1SJian Shen /* get current port based vlan state from PF */ 187492f11ea1SJian Shen ret = hclgevf_get_port_base_vlan_filter_state(hdev); 187592f11ea1SJian Shen if (ret) 187692f11ea1SJian Shen return ret; 187792f11ea1SJian Shen 1878e2cb1decSSalil Mehta /* get queue configuration from PF */ 18796cee6fc3SJian Shen ret = hclgevf_get_queue_info(hdev); 1880e2cb1decSSalil Mehta if (ret) 1881e2cb1decSSalil Mehta return ret; 1882c0425944SPeng Li 1883c0425944SPeng Li /* get queue depth info from PF */ 1884c0425944SPeng Li ret = hclgevf_get_queue_depth(hdev); 1885c0425944SPeng Li if (ret) 1886c0425944SPeng Li return ret; 1887c0425944SPeng Li 18889c3e7130Sliuzhongzhu ret = hclgevf_get_pf_media_type(hdev); 18899c3e7130Sliuzhongzhu if (ret) 18909c3e7130Sliuzhongzhu return ret; 18919c3e7130Sliuzhongzhu 1892e2cb1decSSalil Mehta /* get tc configuration from PF */ 1893e2cb1decSSalil Mehta return hclgevf_get_tc_info(hdev); 1894e2cb1decSSalil Mehta } 1895e2cb1decSSalil Mehta 18967a01c897SSalil Mehta static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 18977a01c897SSalil Mehta { 18987a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 18991154bb26SPeng Li struct hclgevf_dev *hdev; 19007a01c897SSalil Mehta 19017a01c897SSalil Mehta hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 19027a01c897SSalil Mehta if (!hdev) 19037a01c897SSalil Mehta return -ENOMEM; 19047a01c897SSalil Mehta 19057a01c897SSalil Mehta hdev->pdev = pdev; 19067a01c897SSalil Mehta hdev->ae_dev = ae_dev; 19077a01c897SSalil Mehta ae_dev->priv = hdev; 19087a01c897SSalil Mehta 19097a01c897SSalil Mehta return 0; 19107a01c897SSalil Mehta } 19117a01c897SSalil Mehta 1912e2cb1decSSalil Mehta static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 1913e2cb1decSSalil Mehta { 1914e2cb1decSSalil Mehta struct hnae3_handle *roce = &hdev->roce; 1915e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 1916e2cb1decSSalil Mehta 191707acf909SJian Shen roce->rinfo.num_vectors = hdev->num_roce_msix; 1918e2cb1decSSalil Mehta 1919e2cb1decSSalil Mehta if (hdev->num_msi_left < roce->rinfo.num_vectors || 1920e2cb1decSSalil Mehta hdev->num_msi_left == 0) 1921e2cb1decSSalil Mehta return -EINVAL; 1922e2cb1decSSalil Mehta 192307acf909SJian Shen roce->rinfo.base_vector = hdev->roce_base_vector; 1924e2cb1decSSalil Mehta 1925e2cb1decSSalil Mehta roce->rinfo.netdev = nic->kinfo.netdev; 1926e2cb1decSSalil Mehta roce->rinfo.roce_io_base = hdev->hw.io_base; 1927e2cb1decSSalil Mehta 1928e2cb1decSSalil Mehta roce->pdev = nic->pdev; 1929e2cb1decSSalil Mehta roce->ae_algo = nic->ae_algo; 1930e2cb1decSSalil Mehta roce->numa_node_mask = nic->numa_node_mask; 1931e2cb1decSSalil Mehta 1932e2cb1decSSalil Mehta return 0; 1933e2cb1decSSalil Mehta } 1934e2cb1decSSalil Mehta 1935b26a6feaSPeng Li static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 1936b26a6feaSPeng Li { 1937b26a6feaSPeng Li struct hclgevf_cfg_gro_status_cmd *req; 1938b26a6feaSPeng Li struct hclgevf_desc desc; 1939b26a6feaSPeng Li int ret; 1940b26a6feaSPeng Li 1941b26a6feaSPeng Li if (!hnae3_dev_gro_supported(hdev)) 1942b26a6feaSPeng Li return 0; 1943b26a6feaSPeng Li 1944b26a6feaSPeng Li hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 1945b26a6feaSPeng Li false); 1946b26a6feaSPeng Li req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 1947b26a6feaSPeng Li 1948b26a6feaSPeng Li req->gro_en = cpu_to_le16(en ? 1 : 0); 1949b26a6feaSPeng Li 1950b26a6feaSPeng Li ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1951b26a6feaSPeng Li if (ret) 1952b26a6feaSPeng Li dev_err(&hdev->pdev->dev, 1953b26a6feaSPeng Li "VF GRO hardware config cmd failed, ret = %d.\n", ret); 1954b26a6feaSPeng Li 1955b26a6feaSPeng Li return ret; 1956b26a6feaSPeng Li } 1957b26a6feaSPeng Li 1958e2cb1decSSalil Mehta static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 1959e2cb1decSSalil Mehta { 1960e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1961e2cb1decSSalil Mehta int i, ret; 1962e2cb1decSSalil Mehta 1963e2cb1decSSalil Mehta rss_cfg->rss_size = hdev->rss_size_max; 1964e2cb1decSSalil Mehta 1965374ad291SJian Shen if (hdev->pdev->revision >= 0x21) { 1966472d7eceSJian Shen rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 1967472d7eceSJian Shen memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 1968374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 1969374ad291SJian Shen 1970374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 1971374ad291SJian Shen rss_cfg->rss_hash_key); 1972374ad291SJian Shen if (ret) 1973374ad291SJian Shen return ret; 1974d97b3072SJian Shen 1975d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = 1976d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1977d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = 1978d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1979d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = 1980d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1981d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = 1982d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1983d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = 1984d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1985d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = 1986d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1987d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = 1988d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1989d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = 1990d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1991d97b3072SJian Shen 1992d97b3072SJian Shen ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 1993d97b3072SJian Shen if (ret) 1994d97b3072SJian Shen return ret; 1995d97b3072SJian Shen 1996374ad291SJian Shen } 1997374ad291SJian Shen 1998e2cb1decSSalil Mehta /* Initialize RSS indirect table for each vport */ 1999e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 2000e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max; 2001e2cb1decSSalil Mehta 2002e2cb1decSSalil Mehta ret = hclgevf_set_rss_indir_table(hdev); 2003e2cb1decSSalil Mehta if (ret) 2004e2cb1decSSalil Mehta return ret; 2005e2cb1decSSalil Mehta 2006e2cb1decSSalil Mehta return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max); 2007e2cb1decSSalil Mehta } 2008e2cb1decSSalil Mehta 2009e2cb1decSSalil Mehta static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2010e2cb1decSSalil Mehta { 2011e2cb1decSSalil Mehta /* other vlan config(like, VLAN TX/RX offload) would also be added 2012e2cb1decSSalil Mehta * here later 2013e2cb1decSSalil Mehta */ 2014e2cb1decSSalil Mehta return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2015e2cb1decSSalil Mehta false); 2016e2cb1decSSalil Mehta } 2017e2cb1decSSalil Mehta 20188cdb992fSJian Shen static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 20198cdb992fSJian Shen { 20208cdb992fSJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 20218cdb992fSJian Shen 20228cdb992fSJian Shen if (enable) { 20238cdb992fSJian Shen mod_timer(&hdev->service_timer, jiffies + HZ); 20248cdb992fSJian Shen } else { 20258cdb992fSJian Shen del_timer_sync(&hdev->service_timer); 20268cdb992fSJian Shen cancel_work_sync(&hdev->service_task); 20278cdb992fSJian Shen clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 20288cdb992fSJian Shen } 20298cdb992fSJian Shen } 20308cdb992fSJian Shen 2031e2cb1decSSalil Mehta static int hclgevf_ae_start(struct hnae3_handle *handle) 2032e2cb1decSSalil Mehta { 2033e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2034e2cb1decSSalil Mehta 2035e2cb1decSSalil Mehta /* reset tqp stats */ 2036e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 2037e2cb1decSSalil Mehta 2038e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 2039e2cb1decSSalil Mehta 20409194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 20419194d18bSliuzhongzhu 2042e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2043e2cb1decSSalil Mehta 2044e2cb1decSSalil Mehta return 0; 2045e2cb1decSSalil Mehta } 2046e2cb1decSSalil Mehta 2047e2cb1decSSalil Mehta static void hclgevf_ae_stop(struct hnae3_handle *handle) 2048e2cb1decSSalil Mehta { 2049e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 205039cfbc9cSHuazhong Tan int i; 2051e2cb1decSSalil Mehta 20522f7e4896SFuyun Liang set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 20532f7e4896SFuyun Liang 2054146e92c1SHuazhong Tan if (hdev->reset_type != HNAE3_VF_RESET) 205539cfbc9cSHuazhong Tan for (i = 0; i < handle->kinfo.num_tqps; i++) 2056146e92c1SHuazhong Tan if (hclgevf_reset_tqp(handle, i)) 2057146e92c1SHuazhong Tan break; 205839cfbc9cSHuazhong Tan 2059e2cb1decSSalil Mehta /* reset tqp stats */ 2060e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 20618cc6c1f7SFuyun Liang hclgevf_update_link_status(hdev, 0); 2062e2cb1decSSalil Mehta } 2063e2cb1decSSalil Mehta 2064a6d818e3SYunsheng Lin static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2065a6d818e3SYunsheng Lin { 2066a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2067a6d818e3SYunsheng Lin u8 msg_data; 2068a6d818e3SYunsheng Lin 2069a6d818e3SYunsheng Lin msg_data = alive ? 1 : 0; 2070a6d818e3SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE, 2071a6d818e3SYunsheng Lin 0, &msg_data, 1, false, NULL, 0); 2072a6d818e3SYunsheng Lin } 2073a6d818e3SYunsheng Lin 2074a6d818e3SYunsheng Lin static int hclgevf_client_start(struct hnae3_handle *handle) 2075a6d818e3SYunsheng Lin { 2076a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2077e233516eSHuazhong Tan int ret; 2078e233516eSHuazhong Tan 2079e233516eSHuazhong Tan ret = hclgevf_set_alive(handle, true); 2080e233516eSHuazhong Tan if (ret) 2081e233516eSHuazhong Tan return ret; 2082a6d818e3SYunsheng Lin 2083a6d818e3SYunsheng Lin mod_timer(&hdev->keep_alive_timer, jiffies + 2 * HZ); 2084e233516eSHuazhong Tan 2085e233516eSHuazhong Tan return 0; 2086a6d818e3SYunsheng Lin } 2087a6d818e3SYunsheng Lin 2088a6d818e3SYunsheng Lin static void hclgevf_client_stop(struct hnae3_handle *handle) 2089a6d818e3SYunsheng Lin { 2090a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2091a6d818e3SYunsheng Lin int ret; 2092a6d818e3SYunsheng Lin 2093a6d818e3SYunsheng Lin ret = hclgevf_set_alive(handle, false); 2094a6d818e3SYunsheng Lin if (ret) 2095a6d818e3SYunsheng Lin dev_warn(&hdev->pdev->dev, 2096a6d818e3SYunsheng Lin "%s failed %d\n", __func__, ret); 2097a6d818e3SYunsheng Lin 2098a6d818e3SYunsheng Lin del_timer_sync(&hdev->keep_alive_timer); 2099a6d818e3SYunsheng Lin cancel_work_sync(&hdev->keep_alive_task); 2100a6d818e3SYunsheng Lin } 2101a6d818e3SYunsheng Lin 2102e2cb1decSSalil Mehta static void hclgevf_state_init(struct hclgevf_dev *hdev) 2103e2cb1decSSalil Mehta { 2104e2cb1decSSalil Mehta /* setup tasks for the MBX */ 2105e2cb1decSSalil Mehta INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 2106e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2107e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2108e2cb1decSSalil Mehta 2109e2cb1decSSalil Mehta /* setup tasks for service timer */ 2110e2cb1decSSalil Mehta timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 2111e2cb1decSSalil Mehta 2112e2cb1decSSalil Mehta INIT_WORK(&hdev->service_task, hclgevf_service_task); 2113e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2114e2cb1decSSalil Mehta 211535a1e503SSalil Mehta INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task); 211635a1e503SSalil Mehta 2117e2cb1decSSalil Mehta mutex_init(&hdev->mbx_resp.mbx_mutex); 2118e2cb1decSSalil Mehta 2119e2cb1decSSalil Mehta /* bring the device down */ 2120e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2121e2cb1decSSalil Mehta } 2122e2cb1decSSalil Mehta 2123e2cb1decSSalil Mehta static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2124e2cb1decSSalil Mehta { 2125e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2126e2cb1decSSalil Mehta 2127e233516eSHuazhong Tan if (hdev->keep_alive_timer.function) 2128e233516eSHuazhong Tan del_timer_sync(&hdev->keep_alive_timer); 2129e233516eSHuazhong Tan if (hdev->keep_alive_task.func) 2130e233516eSHuazhong Tan cancel_work_sync(&hdev->keep_alive_task); 2131e2cb1decSSalil Mehta if (hdev->service_timer.function) 2132e2cb1decSSalil Mehta del_timer_sync(&hdev->service_timer); 2133e2cb1decSSalil Mehta if (hdev->service_task.func) 2134e2cb1decSSalil Mehta cancel_work_sync(&hdev->service_task); 2135e2cb1decSSalil Mehta if (hdev->mbx_service_task.func) 2136e2cb1decSSalil Mehta cancel_work_sync(&hdev->mbx_service_task); 213735a1e503SSalil Mehta if (hdev->rst_service_task.func) 213835a1e503SSalil Mehta cancel_work_sync(&hdev->rst_service_task); 2139e2cb1decSSalil Mehta 2140e2cb1decSSalil Mehta mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2141e2cb1decSSalil Mehta } 2142e2cb1decSSalil Mehta 2143e2cb1decSSalil Mehta static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2144e2cb1decSSalil Mehta { 2145e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2146e2cb1decSSalil Mehta int vectors; 2147e2cb1decSSalil Mehta int i; 2148e2cb1decSSalil Mehta 214907acf909SJian Shen if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) 215007acf909SJian Shen vectors = pci_alloc_irq_vectors(pdev, 215107acf909SJian Shen hdev->roce_base_msix_offset + 1, 215207acf909SJian Shen hdev->num_msi, 215307acf909SJian Shen PCI_IRQ_MSIX); 215407acf909SJian Shen else 2155e2cb1decSSalil Mehta vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 2156e2cb1decSSalil Mehta PCI_IRQ_MSI | PCI_IRQ_MSIX); 215707acf909SJian Shen 2158e2cb1decSSalil Mehta if (vectors < 0) { 2159e2cb1decSSalil Mehta dev_err(&pdev->dev, 2160e2cb1decSSalil Mehta "failed(%d) to allocate MSI/MSI-X vectors\n", 2161e2cb1decSSalil Mehta vectors); 2162e2cb1decSSalil Mehta return vectors; 2163e2cb1decSSalil Mehta } 2164e2cb1decSSalil Mehta if (vectors < hdev->num_msi) 2165e2cb1decSSalil Mehta dev_warn(&hdev->pdev->dev, 2166e2cb1decSSalil Mehta "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2167e2cb1decSSalil Mehta hdev->num_msi, vectors); 2168e2cb1decSSalil Mehta 2169e2cb1decSSalil Mehta hdev->num_msi = vectors; 2170e2cb1decSSalil Mehta hdev->num_msi_left = vectors; 2171e2cb1decSSalil Mehta hdev->base_msi_vector = pdev->irq; 217207acf909SJian Shen hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2173e2cb1decSSalil Mehta 2174e2cb1decSSalil Mehta hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2175e2cb1decSSalil Mehta sizeof(u16), GFP_KERNEL); 2176e2cb1decSSalil Mehta if (!hdev->vector_status) { 2177e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2178e2cb1decSSalil Mehta return -ENOMEM; 2179e2cb1decSSalil Mehta } 2180e2cb1decSSalil Mehta 2181e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 2182e2cb1decSSalil Mehta hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2183e2cb1decSSalil Mehta 2184e2cb1decSSalil Mehta hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2185e2cb1decSSalil Mehta sizeof(int), GFP_KERNEL); 2186e2cb1decSSalil Mehta if (!hdev->vector_irq) { 2187862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2188e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2189e2cb1decSSalil Mehta return -ENOMEM; 2190e2cb1decSSalil Mehta } 2191e2cb1decSSalil Mehta 2192e2cb1decSSalil Mehta return 0; 2193e2cb1decSSalil Mehta } 2194e2cb1decSSalil Mehta 2195e2cb1decSSalil Mehta static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2196e2cb1decSSalil Mehta { 2197e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2198e2cb1decSSalil Mehta 2199862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2200862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_irq); 2201e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2202e2cb1decSSalil Mehta } 2203e2cb1decSSalil Mehta 2204e2cb1decSSalil Mehta static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2205e2cb1decSSalil Mehta { 2206e2cb1decSSalil Mehta int ret = 0; 2207e2cb1decSSalil Mehta 2208e2cb1decSSalil Mehta hclgevf_get_misc_vector(hdev); 2209e2cb1decSSalil Mehta 2210e2cb1decSSalil Mehta ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2211e2cb1decSSalil Mehta 0, "hclgevf_cmd", hdev); 2212e2cb1decSSalil Mehta if (ret) { 2213e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2214e2cb1decSSalil Mehta hdev->misc_vector.vector_irq); 2215e2cb1decSSalil Mehta return ret; 2216e2cb1decSSalil Mehta } 2217e2cb1decSSalil Mehta 22181819e409SXi Wang hclgevf_clear_event_cause(hdev, 0); 22191819e409SXi Wang 2220e2cb1decSSalil Mehta /* enable misc. vector(vector 0) */ 2221e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2222e2cb1decSSalil Mehta 2223e2cb1decSSalil Mehta return ret; 2224e2cb1decSSalil Mehta } 2225e2cb1decSSalil Mehta 2226e2cb1decSSalil Mehta static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2227e2cb1decSSalil Mehta { 2228e2cb1decSSalil Mehta /* disable misc vector(vector 0) */ 2229e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 22301819e409SXi Wang synchronize_irq(hdev->misc_vector.vector_irq); 2231e2cb1decSSalil Mehta free_irq(hdev->misc_vector.vector_irq, hdev); 2232e2cb1decSSalil Mehta hclgevf_free_vector(hdev, 0); 2233e2cb1decSSalil Mehta } 2234e2cb1decSSalil Mehta 2235bb87be87SYonglong Liu static void hclgevf_info_show(struct hclgevf_dev *hdev) 2236bb87be87SYonglong Liu { 2237bb87be87SYonglong Liu struct device *dev = &hdev->pdev->dev; 2238bb87be87SYonglong Liu 2239bb87be87SYonglong Liu dev_info(dev, "VF info begin:\n"); 2240bb87be87SYonglong Liu 2241bb87be87SYonglong Liu dev_info(dev, "Task queue pairs numbers: %d\n", hdev->num_tqps); 2242bb87be87SYonglong Liu dev_info(dev, "Desc num per TX queue: %d\n", hdev->num_tx_desc); 2243bb87be87SYonglong Liu dev_info(dev, "Desc num per RX queue: %d\n", hdev->num_rx_desc); 2244bb87be87SYonglong Liu dev_info(dev, "Numbers of vports: %d\n", hdev->num_alloc_vport); 2245bb87be87SYonglong Liu dev_info(dev, "HW tc map: %d\n", hdev->hw_tc_map); 2246bb87be87SYonglong Liu dev_info(dev, "PF media type of this VF: %d\n", 2247bb87be87SYonglong Liu hdev->hw.mac.media_type); 2248bb87be87SYonglong Liu 2249bb87be87SYonglong Liu dev_info(dev, "VF info end.\n"); 2250bb87be87SYonglong Liu } 2251bb87be87SYonglong Liu 2252e718a93fSPeng Li static int hclgevf_init_client_instance(struct hnae3_client *client, 2253e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2254e2cb1decSSalil Mehta { 2255e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2256e2cb1decSSalil Mehta int ret; 2257e2cb1decSSalil Mehta 2258e2cb1decSSalil Mehta switch (client->type) { 2259e2cb1decSSalil Mehta case HNAE3_CLIENT_KNIC: 2260e2cb1decSSalil Mehta hdev->nic_client = client; 2261e2cb1decSSalil Mehta hdev->nic.client = client; 2262e2cb1decSSalil Mehta 2263e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->nic); 2264e2cb1decSSalil Mehta if (ret) 226549dd8054SJian Shen goto clear_nic; 2266e2cb1decSSalil Mehta 2267d9f28fc2SJian Shen hnae3_set_client_init_flag(client, ae_dev, 1); 2268d9f28fc2SJian Shen 2269bb87be87SYonglong Liu if (netif_msg_drv(&hdev->nic)) 2270bb87be87SYonglong Liu hclgevf_info_show(hdev); 2271bb87be87SYonglong Liu 2272e2cb1decSSalil Mehta if (hdev->roce_client && hnae3_dev_roce_supported(hdev)) { 2273e2cb1decSSalil Mehta struct hnae3_client *rc = hdev->roce_client; 2274e2cb1decSSalil Mehta 2275e2cb1decSSalil Mehta ret = hclgevf_init_roce_base_info(hdev); 2276e2cb1decSSalil Mehta if (ret) 227749dd8054SJian Shen goto clear_roce; 2278e2cb1decSSalil Mehta ret = rc->ops->init_instance(&hdev->roce); 2279e2cb1decSSalil Mehta if (ret) 228049dd8054SJian Shen goto clear_roce; 2281d9f28fc2SJian Shen 2282d9f28fc2SJian Shen hnae3_set_client_init_flag(hdev->roce_client, ae_dev, 2283d9f28fc2SJian Shen 1); 2284e2cb1decSSalil Mehta } 2285e2cb1decSSalil Mehta break; 2286e2cb1decSSalil Mehta case HNAE3_CLIENT_UNIC: 2287e2cb1decSSalil Mehta hdev->nic_client = client; 2288e2cb1decSSalil Mehta hdev->nic.client = client; 2289e2cb1decSSalil Mehta 2290e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->nic); 2291e2cb1decSSalil Mehta if (ret) 229249dd8054SJian Shen goto clear_nic; 2293d9f28fc2SJian Shen 2294d9f28fc2SJian Shen hnae3_set_client_init_flag(client, ae_dev, 1); 2295e2cb1decSSalil Mehta break; 2296e2cb1decSSalil Mehta case HNAE3_CLIENT_ROCE: 2297544a7bcdSLijun Ou if (hnae3_dev_roce_supported(hdev)) { 2298e2cb1decSSalil Mehta hdev->roce_client = client; 2299e2cb1decSSalil Mehta hdev->roce.client = client; 2300544a7bcdSLijun Ou } 2301e2cb1decSSalil Mehta 2302544a7bcdSLijun Ou if (hdev->roce_client && hdev->nic_client) { 2303e2cb1decSSalil Mehta ret = hclgevf_init_roce_base_info(hdev); 2304e2cb1decSSalil Mehta if (ret) 230549dd8054SJian Shen goto clear_roce; 2306e2cb1decSSalil Mehta 2307e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->roce); 2308e2cb1decSSalil Mehta if (ret) 230949dd8054SJian Shen goto clear_roce; 2310e2cb1decSSalil Mehta } 2311d9f28fc2SJian Shen 2312d9f28fc2SJian Shen hnae3_set_client_init_flag(client, ae_dev, 1); 2313fa7a4bd5SJian Shen break; 2314fa7a4bd5SJian Shen default: 2315fa7a4bd5SJian Shen return -EINVAL; 2316e2cb1decSSalil Mehta } 2317e2cb1decSSalil Mehta 2318e2cb1decSSalil Mehta return 0; 231949dd8054SJian Shen 232049dd8054SJian Shen clear_nic: 232149dd8054SJian Shen hdev->nic_client = NULL; 232249dd8054SJian Shen hdev->nic.client = NULL; 232349dd8054SJian Shen return ret; 232449dd8054SJian Shen clear_roce: 232549dd8054SJian Shen hdev->roce_client = NULL; 232649dd8054SJian Shen hdev->roce.client = NULL; 232749dd8054SJian Shen return ret; 2328e2cb1decSSalil Mehta } 2329e2cb1decSSalil Mehta 2330e718a93fSPeng Li static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2331e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2332e2cb1decSSalil Mehta { 2333e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2334e718a93fSPeng Li 2335e2cb1decSSalil Mehta /* un-init roce, if it exists */ 233649dd8054SJian Shen if (hdev->roce_client) { 2337e2cb1decSSalil Mehta hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 233849dd8054SJian Shen hdev->roce_client = NULL; 233949dd8054SJian Shen hdev->roce.client = NULL; 234049dd8054SJian Shen } 2341e2cb1decSSalil Mehta 2342e2cb1decSSalil Mehta /* un-init nic/unic, if this was not called by roce client */ 234349dd8054SJian Shen if (client->ops->uninit_instance && hdev->nic_client && 234449dd8054SJian Shen client->type != HNAE3_CLIENT_ROCE) { 2345e2cb1decSSalil Mehta client->ops->uninit_instance(&hdev->nic, 0); 234649dd8054SJian Shen hdev->nic_client = NULL; 234749dd8054SJian Shen hdev->nic.client = NULL; 234849dd8054SJian Shen } 2349e2cb1decSSalil Mehta } 2350e2cb1decSSalil Mehta 2351e2cb1decSSalil Mehta static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2352e2cb1decSSalil Mehta { 2353e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2354e2cb1decSSalil Mehta struct hclgevf_hw *hw; 2355e2cb1decSSalil Mehta int ret; 2356e2cb1decSSalil Mehta 2357e2cb1decSSalil Mehta ret = pci_enable_device(pdev); 2358e2cb1decSSalil Mehta if (ret) { 2359e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed to enable PCI device\n"); 23603e249d3bSFuyun Liang return ret; 2361e2cb1decSSalil Mehta } 2362e2cb1decSSalil Mehta 2363e2cb1decSSalil Mehta ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2364e2cb1decSSalil Mehta if (ret) { 2365e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2366e2cb1decSSalil Mehta goto err_disable_device; 2367e2cb1decSSalil Mehta } 2368e2cb1decSSalil Mehta 2369e2cb1decSSalil Mehta ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2370e2cb1decSSalil Mehta if (ret) { 2371e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2372e2cb1decSSalil Mehta goto err_disable_device; 2373e2cb1decSSalil Mehta } 2374e2cb1decSSalil Mehta 2375e2cb1decSSalil Mehta pci_set_master(pdev); 2376e2cb1decSSalil Mehta hw = &hdev->hw; 2377e2cb1decSSalil Mehta hw->hdev = hdev; 23782e1ea493SPeng Li hw->io_base = pci_iomap(pdev, 2, 0); 2379e2cb1decSSalil Mehta if (!hw->io_base) { 2380e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't map configuration register space\n"); 2381e2cb1decSSalil Mehta ret = -ENOMEM; 2382e2cb1decSSalil Mehta goto err_clr_master; 2383e2cb1decSSalil Mehta } 2384e2cb1decSSalil Mehta 2385e2cb1decSSalil Mehta return 0; 2386e2cb1decSSalil Mehta 2387e2cb1decSSalil Mehta err_clr_master: 2388e2cb1decSSalil Mehta pci_clear_master(pdev); 2389e2cb1decSSalil Mehta pci_release_regions(pdev); 2390e2cb1decSSalil Mehta err_disable_device: 2391e2cb1decSSalil Mehta pci_disable_device(pdev); 23923e249d3bSFuyun Liang 2393e2cb1decSSalil Mehta return ret; 2394e2cb1decSSalil Mehta } 2395e2cb1decSSalil Mehta 2396e2cb1decSSalil Mehta static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2397e2cb1decSSalil Mehta { 2398e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2399e2cb1decSSalil Mehta 2400e2cb1decSSalil Mehta pci_iounmap(pdev, hdev->hw.io_base); 2401e2cb1decSSalil Mehta pci_clear_master(pdev); 2402e2cb1decSSalil Mehta pci_release_regions(pdev); 2403e2cb1decSSalil Mehta pci_disable_device(pdev); 2404e2cb1decSSalil Mehta } 2405e2cb1decSSalil Mehta 240607acf909SJian Shen static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 240707acf909SJian Shen { 240807acf909SJian Shen struct hclgevf_query_res_cmd *req; 240907acf909SJian Shen struct hclgevf_desc desc; 241007acf909SJian Shen int ret; 241107acf909SJian Shen 241207acf909SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 241307acf909SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 241407acf909SJian Shen if (ret) { 241507acf909SJian Shen dev_err(&hdev->pdev->dev, 241607acf909SJian Shen "query vf resource failed, ret = %d.\n", ret); 241707acf909SJian Shen return ret; 241807acf909SJian Shen } 241907acf909SJian Shen 242007acf909SJian Shen req = (struct hclgevf_query_res_cmd *)desc.data; 242107acf909SJian Shen 242207acf909SJian Shen if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) { 242307acf909SJian Shen hdev->roce_base_msix_offset = 242407acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 242507acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_M, 242607acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_S); 242707acf909SJian Shen hdev->num_roce_msix = 242807acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 242907acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 243007acf909SJian Shen 243107acf909SJian Shen /* VF should have NIC vectors and Roce vectors, NIC vectors 243207acf909SJian Shen * are queued before Roce vectors. The offset is fixed to 64. 243307acf909SJian Shen */ 243407acf909SJian Shen hdev->num_msi = hdev->num_roce_msix + 243507acf909SJian Shen hdev->roce_base_msix_offset; 243607acf909SJian Shen } else { 243707acf909SJian Shen hdev->num_msi = 243807acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 243907acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 244007acf909SJian Shen } 244107acf909SJian Shen 244207acf909SJian Shen return 0; 244307acf909SJian Shen } 244407acf909SJian Shen 2445862d969aSHuazhong Tan static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2446862d969aSHuazhong Tan { 2447862d969aSHuazhong Tan struct pci_dev *pdev = hdev->pdev; 2448862d969aSHuazhong Tan int ret = 0; 2449862d969aSHuazhong Tan 2450862d969aSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2451862d969aSHuazhong Tan test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2452862d969aSHuazhong Tan hclgevf_misc_irq_uninit(hdev); 2453862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2454862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2455862d969aSHuazhong Tan } 2456862d969aSHuazhong Tan 2457862d969aSHuazhong Tan if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2458862d969aSHuazhong Tan pci_set_master(pdev); 2459862d969aSHuazhong Tan ret = hclgevf_init_msi(hdev); 2460862d969aSHuazhong Tan if (ret) { 2461862d969aSHuazhong Tan dev_err(&pdev->dev, 2462862d969aSHuazhong Tan "failed(%d) to init MSI/MSI-X\n", ret); 2463862d969aSHuazhong Tan return ret; 2464862d969aSHuazhong Tan } 2465862d969aSHuazhong Tan 2466862d969aSHuazhong Tan ret = hclgevf_misc_irq_init(hdev); 2467862d969aSHuazhong Tan if (ret) { 2468862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2469862d969aSHuazhong Tan dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2470862d969aSHuazhong Tan ret); 2471862d969aSHuazhong Tan return ret; 2472862d969aSHuazhong Tan } 2473862d969aSHuazhong Tan 2474862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2475862d969aSHuazhong Tan } 2476862d969aSHuazhong Tan 2477862d969aSHuazhong Tan return ret; 2478862d969aSHuazhong Tan } 2479862d969aSHuazhong Tan 24809c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2481e2cb1decSSalil Mehta { 24827a01c897SSalil Mehta struct pci_dev *pdev = hdev->pdev; 2483e2cb1decSSalil Mehta int ret; 2484e2cb1decSSalil Mehta 2485862d969aSHuazhong Tan ret = hclgevf_pci_reset(hdev); 2486862d969aSHuazhong Tan if (ret) { 2487862d969aSHuazhong Tan dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2488862d969aSHuazhong Tan return ret; 2489862d969aSHuazhong Tan } 2490862d969aSHuazhong Tan 24919c6f7085SHuazhong Tan ret = hclgevf_cmd_init(hdev); 24929c6f7085SHuazhong Tan if (ret) { 24939c6f7085SHuazhong Tan dev_err(&pdev->dev, "cmd failed %d\n", ret); 24949c6f7085SHuazhong Tan return ret; 24957a01c897SSalil Mehta } 2496e2cb1decSSalil Mehta 24979c6f7085SHuazhong Tan ret = hclgevf_rss_init_hw(hdev); 24989c6f7085SHuazhong Tan if (ret) { 24999c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 25009c6f7085SHuazhong Tan "failed(%d) to initialize RSS\n", ret); 25019c6f7085SHuazhong Tan return ret; 25029c6f7085SHuazhong Tan } 25039c6f7085SHuazhong Tan 2504b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2505b26a6feaSPeng Li if (ret) 2506b26a6feaSPeng Li return ret; 2507b26a6feaSPeng Li 25089c6f7085SHuazhong Tan ret = hclgevf_init_vlan_config(hdev); 25099c6f7085SHuazhong Tan if (ret) { 25109c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 25119c6f7085SHuazhong Tan "failed(%d) to initialize VLAN config\n", ret); 25129c6f7085SHuazhong Tan return ret; 25139c6f7085SHuazhong Tan } 25149c6f7085SHuazhong Tan 25159c6f7085SHuazhong Tan dev_info(&hdev->pdev->dev, "Reset done\n"); 25169c6f7085SHuazhong Tan 25179c6f7085SHuazhong Tan return 0; 25189c6f7085SHuazhong Tan } 25199c6f7085SHuazhong Tan 25209c6f7085SHuazhong Tan static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 25219c6f7085SHuazhong Tan { 25229c6f7085SHuazhong Tan struct pci_dev *pdev = hdev->pdev; 25239c6f7085SHuazhong Tan int ret; 25249c6f7085SHuazhong Tan 2525e2cb1decSSalil Mehta ret = hclgevf_pci_init(hdev); 2526e2cb1decSSalil Mehta if (ret) { 2527e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI initialization failed\n"); 2528e2cb1decSSalil Mehta return ret; 2529e2cb1decSSalil Mehta } 2530e2cb1decSSalil Mehta 25318b0195a3SHuazhong Tan ret = hclgevf_cmd_queue_init(hdev); 25328b0195a3SHuazhong Tan if (ret) { 25338b0195a3SHuazhong Tan dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret); 25348b0195a3SHuazhong Tan goto err_cmd_queue_init; 25358b0195a3SHuazhong Tan } 25368b0195a3SHuazhong Tan 2537eddf0462SYunsheng Lin ret = hclgevf_cmd_init(hdev); 2538eddf0462SYunsheng Lin if (ret) 2539eddf0462SYunsheng Lin goto err_cmd_init; 2540eddf0462SYunsheng Lin 254107acf909SJian Shen /* Get vf resource */ 254207acf909SJian Shen ret = hclgevf_query_vf_resource(hdev); 254307acf909SJian Shen if (ret) { 254407acf909SJian Shen dev_err(&hdev->pdev->dev, 254507acf909SJian Shen "Query vf status error, ret = %d.\n", ret); 25468b0195a3SHuazhong Tan goto err_cmd_init; 254707acf909SJian Shen } 254807acf909SJian Shen 254907acf909SJian Shen ret = hclgevf_init_msi(hdev); 255007acf909SJian Shen if (ret) { 255107acf909SJian Shen dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 25528b0195a3SHuazhong Tan goto err_cmd_init; 255307acf909SJian Shen } 255407acf909SJian Shen 255507acf909SJian Shen hclgevf_state_init(hdev); 2556dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 255707acf909SJian Shen 2558e2cb1decSSalil Mehta ret = hclgevf_misc_irq_init(hdev); 2559e2cb1decSSalil Mehta if (ret) { 2560e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2561e2cb1decSSalil Mehta ret); 2562e2cb1decSSalil Mehta goto err_misc_irq_init; 2563e2cb1decSSalil Mehta } 2564e2cb1decSSalil Mehta 2565862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2566862d969aSHuazhong Tan 2567e2cb1decSSalil Mehta ret = hclgevf_configure(hdev); 2568e2cb1decSSalil Mehta if (ret) { 2569e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2570e2cb1decSSalil Mehta goto err_config; 2571e2cb1decSSalil Mehta } 2572e2cb1decSSalil Mehta 2573e2cb1decSSalil Mehta ret = hclgevf_alloc_tqps(hdev); 2574e2cb1decSSalil Mehta if (ret) { 2575e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2576e2cb1decSSalil Mehta goto err_config; 2577e2cb1decSSalil Mehta } 2578e2cb1decSSalil Mehta 2579e2cb1decSSalil Mehta ret = hclgevf_set_handle_info(hdev); 2580e2cb1decSSalil Mehta if (ret) { 2581e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 2582e2cb1decSSalil Mehta goto err_config; 2583e2cb1decSSalil Mehta } 2584e2cb1decSSalil Mehta 2585b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2586b26a6feaSPeng Li if (ret) 2587b26a6feaSPeng Li goto err_config; 2588b26a6feaSPeng Li 2589f01f5559SJian Shen /* vf is not allowed to enable unicast/multicast promisc mode. 2590f01f5559SJian Shen * For revision 0x20, default to disable broadcast promisc mode, 2591f01f5559SJian Shen * firmware makes sure broadcast packets can be accepted. 2592f01f5559SJian Shen * For revision 0x21, default to enable broadcast promisc mode. 2593f01f5559SJian Shen */ 2594f01f5559SJian Shen ret = hclgevf_set_promisc_mode(hdev, true); 2595f01f5559SJian Shen if (ret) 2596f01f5559SJian Shen goto err_config; 2597f01f5559SJian Shen 2598e2cb1decSSalil Mehta /* Initialize RSS for this VF */ 2599e2cb1decSSalil Mehta ret = hclgevf_rss_init_hw(hdev); 2600e2cb1decSSalil Mehta if (ret) { 2601e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2602e2cb1decSSalil Mehta "failed(%d) to initialize RSS\n", ret); 2603e2cb1decSSalil Mehta goto err_config; 2604e2cb1decSSalil Mehta } 2605e2cb1decSSalil Mehta 2606e2cb1decSSalil Mehta ret = hclgevf_init_vlan_config(hdev); 2607e2cb1decSSalil Mehta if (ret) { 2608e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2609e2cb1decSSalil Mehta "failed(%d) to initialize VLAN config\n", ret); 2610e2cb1decSSalil Mehta goto err_config; 2611e2cb1decSSalil Mehta } 2612e2cb1decSSalil Mehta 26130742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 2614e2cb1decSSalil Mehta pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME); 2615e2cb1decSSalil Mehta 2616e2cb1decSSalil Mehta return 0; 2617e2cb1decSSalil Mehta 2618e2cb1decSSalil Mehta err_config: 2619e2cb1decSSalil Mehta hclgevf_misc_irq_uninit(hdev); 2620e2cb1decSSalil Mehta err_misc_irq_init: 2621e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2622e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 262307acf909SJian Shen err_cmd_init: 26248b0195a3SHuazhong Tan hclgevf_cmd_uninit(hdev); 26258b0195a3SHuazhong Tan err_cmd_queue_init: 2626e2cb1decSSalil Mehta hclgevf_pci_uninit(hdev); 2627862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2628e2cb1decSSalil Mehta return ret; 2629e2cb1decSSalil Mehta } 2630e2cb1decSSalil Mehta 26317a01c897SSalil Mehta static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2632e2cb1decSSalil Mehta { 2633e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2634862d969aSHuazhong Tan 2635862d969aSHuazhong Tan if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2636eddf0462SYunsheng Lin hclgevf_misc_irq_uninit(hdev); 2637e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 26387a01c897SSalil Mehta } 26397a01c897SSalil Mehta 2640e3338205SHuazhong Tan hclgevf_pci_uninit(hdev); 2641862d969aSHuazhong Tan hclgevf_cmd_uninit(hdev); 2642862d969aSHuazhong Tan } 2643862d969aSHuazhong Tan 26447a01c897SSalil Mehta static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 26457a01c897SSalil Mehta { 26467a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 2647a6d818e3SYunsheng Lin struct hclgevf_dev *hdev; 26487a01c897SSalil Mehta int ret; 26497a01c897SSalil Mehta 26507a01c897SSalil Mehta ret = hclgevf_alloc_hdev(ae_dev); 26517a01c897SSalil Mehta if (ret) { 26527a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device allocation failed\n"); 26537a01c897SSalil Mehta return ret; 26547a01c897SSalil Mehta } 26557a01c897SSalil Mehta 26567a01c897SSalil Mehta ret = hclgevf_init_hdev(ae_dev->priv); 2657a6d818e3SYunsheng Lin if (ret) { 26587a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device initialization failed\n"); 26597a01c897SSalil Mehta return ret; 26607a01c897SSalil Mehta } 26617a01c897SSalil Mehta 2662a6d818e3SYunsheng Lin hdev = ae_dev->priv; 2663a6d818e3SYunsheng Lin timer_setup(&hdev->keep_alive_timer, hclgevf_keep_alive_timer, 0); 2664a6d818e3SYunsheng Lin INIT_WORK(&hdev->keep_alive_task, hclgevf_keep_alive_task); 2665a6d818e3SYunsheng Lin 2666a6d818e3SYunsheng Lin return 0; 2667a6d818e3SYunsheng Lin } 2668a6d818e3SYunsheng Lin 26697a01c897SSalil Mehta static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 26707a01c897SSalil Mehta { 26717a01c897SSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 26727a01c897SSalil Mehta 26737a01c897SSalil Mehta hclgevf_uninit_hdev(hdev); 2674e2cb1decSSalil Mehta ae_dev->priv = NULL; 2675e2cb1decSSalil Mehta } 2676e2cb1decSSalil Mehta 2677849e4607SPeng Li static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2678849e4607SPeng Li { 2679849e4607SPeng Li struct hnae3_handle *nic = &hdev->nic; 2680849e4607SPeng Li struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2681849e4607SPeng Li 26828be73621SHuazhong Tan return min_t(u32, hdev->rss_size_max, 26838be73621SHuazhong Tan hdev->num_tqps / kinfo->num_tc); 2684849e4607SPeng Li } 2685849e4607SPeng Li 2686849e4607SPeng Li /** 2687849e4607SPeng Li * hclgevf_get_channels - Get the current channels enabled and max supported. 2688849e4607SPeng Li * @handle: hardware information for network interface 2689849e4607SPeng Li * @ch: ethtool channels structure 2690849e4607SPeng Li * 2691849e4607SPeng Li * We don't support separate tx and rx queues as channels. The other count 2692849e4607SPeng Li * represents how many queues are being used for control. max_combined counts 2693849e4607SPeng Li * how many queue pairs we can support. They may not be mapped 1 to 1 with 2694849e4607SPeng Li * q_vectors since we support a lot more queue pairs than q_vectors. 2695849e4607SPeng Li **/ 2696849e4607SPeng Li static void hclgevf_get_channels(struct hnae3_handle *handle, 2697849e4607SPeng Li struct ethtool_channels *ch) 2698849e4607SPeng Li { 2699849e4607SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2700849e4607SPeng Li 2701849e4607SPeng Li ch->max_combined = hclgevf_get_max_channels(hdev); 2702849e4607SPeng Li ch->other_count = 0; 2703849e4607SPeng Li ch->max_other = 0; 27048be73621SHuazhong Tan ch->combined_count = handle->kinfo.rss_size; 2705849e4607SPeng Li } 2706849e4607SPeng Li 2707cc719218SPeng Li static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 27080d43bf45SHuazhong Tan u16 *alloc_tqps, u16 *max_rss_size) 2709cc719218SPeng Li { 2710cc719218SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2711cc719218SPeng Li 27120d43bf45SHuazhong Tan *alloc_tqps = hdev->num_tqps; 2713cc719218SPeng Li *max_rss_size = hdev->rss_size_max; 2714cc719218SPeng Li } 2715cc719218SPeng Li 2716175ec96bSFuyun Liang static int hclgevf_get_status(struct hnae3_handle *handle) 2717175ec96bSFuyun Liang { 2718175ec96bSFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2719175ec96bSFuyun Liang 2720175ec96bSFuyun Liang return hdev->hw.mac.link; 2721175ec96bSFuyun Liang } 2722175ec96bSFuyun Liang 27234a152de9SFuyun Liang static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 27244a152de9SFuyun Liang u8 *auto_neg, u32 *speed, 27254a152de9SFuyun Liang u8 *duplex) 27264a152de9SFuyun Liang { 27274a152de9SFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27284a152de9SFuyun Liang 27294a152de9SFuyun Liang if (speed) 27304a152de9SFuyun Liang *speed = hdev->hw.mac.speed; 27314a152de9SFuyun Liang if (duplex) 27324a152de9SFuyun Liang *duplex = hdev->hw.mac.duplex; 27334a152de9SFuyun Liang if (auto_neg) 27344a152de9SFuyun Liang *auto_neg = AUTONEG_DISABLE; 27354a152de9SFuyun Liang } 27364a152de9SFuyun Liang 27374a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 27384a152de9SFuyun Liang u8 duplex) 27394a152de9SFuyun Liang { 27404a152de9SFuyun Liang hdev->hw.mac.speed = speed; 27414a152de9SFuyun Liang hdev->hw.mac.duplex = duplex; 27424a152de9SFuyun Liang } 27434a152de9SFuyun Liang 27441731be4cSYonglong Liu static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 27455c9f6b39SPeng Li { 27465c9f6b39SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27475c9f6b39SPeng Li 27485c9f6b39SPeng Li return hclgevf_config_gro(hdev, enable); 27495c9f6b39SPeng Li } 27505c9f6b39SPeng Li 275188d10bd6SJian Shen static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 275288d10bd6SJian Shen u8 *module_type) 2753c136b884SPeng Li { 2754c136b884SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 275588d10bd6SJian Shen 2756c136b884SPeng Li if (media_type) 2757c136b884SPeng Li *media_type = hdev->hw.mac.media_type; 275888d10bd6SJian Shen 275988d10bd6SJian Shen if (module_type) 276088d10bd6SJian Shen *module_type = hdev->hw.mac.module_type; 2761c136b884SPeng Li } 2762c136b884SPeng Li 27634d60291bSHuazhong Tan static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 27644d60291bSHuazhong Tan { 27654d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27664d60291bSHuazhong Tan 2767aa5c4f17SHuazhong Tan return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 27684d60291bSHuazhong Tan } 27694d60291bSHuazhong Tan 27704d60291bSHuazhong Tan static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 27714d60291bSHuazhong Tan { 27724d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27734d60291bSHuazhong Tan 27744d60291bSHuazhong Tan return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 27754d60291bSHuazhong Tan } 27764d60291bSHuazhong Tan 27774d60291bSHuazhong Tan static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 27784d60291bSHuazhong Tan { 27794d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27804d60291bSHuazhong Tan 2781c88a6e7dSHuazhong Tan return hdev->rst_stats.hw_rst_done_cnt; 27824d60291bSHuazhong Tan } 27834d60291bSHuazhong Tan 27849194d18bSliuzhongzhu static void hclgevf_get_link_mode(struct hnae3_handle *handle, 27859194d18bSliuzhongzhu unsigned long *supported, 27869194d18bSliuzhongzhu unsigned long *advertising) 27879194d18bSliuzhongzhu { 27889194d18bSliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27899194d18bSliuzhongzhu 27909194d18bSliuzhongzhu *supported = hdev->hw.mac.supported; 27919194d18bSliuzhongzhu *advertising = hdev->hw.mac.advertising; 27929194d18bSliuzhongzhu } 27939194d18bSliuzhongzhu 27941600c3e5SJian Shen #define MAX_SEPARATE_NUM 4 27951600c3e5SJian Shen #define SEPARATOR_VALUE 0xFFFFFFFF 27961600c3e5SJian Shen #define REG_NUM_PER_LINE 4 27971600c3e5SJian Shen #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 27981600c3e5SJian Shen 27991600c3e5SJian Shen static int hclgevf_get_regs_len(struct hnae3_handle *handle) 28001600c3e5SJian Shen { 28011600c3e5SJian Shen int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 28021600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 28031600c3e5SJian Shen 28041600c3e5SJian Shen cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 28051600c3e5SJian Shen common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 28061600c3e5SJian Shen ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 28071600c3e5SJian Shen tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 28081600c3e5SJian Shen 28091600c3e5SJian Shen return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 28101600c3e5SJian Shen tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 28111600c3e5SJian Shen } 28121600c3e5SJian Shen 28131600c3e5SJian Shen static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 28141600c3e5SJian Shen void *data) 28151600c3e5SJian Shen { 28161600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 28171600c3e5SJian Shen int i, j, reg_um, separator_num; 28181600c3e5SJian Shen u32 *reg = data; 28191600c3e5SJian Shen 28201600c3e5SJian Shen *version = hdev->fw_version; 28211600c3e5SJian Shen 28221600c3e5SJian Shen /* fetching per-VF registers values from VF PCIe register space */ 28231600c3e5SJian Shen reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 28241600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 28251600c3e5SJian Shen for (i = 0; i < reg_um; i++) 28261600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 28271600c3e5SJian Shen for (i = 0; i < separator_num; i++) 28281600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 28291600c3e5SJian Shen 28301600c3e5SJian Shen reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 28311600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 28321600c3e5SJian Shen for (i = 0; i < reg_um; i++) 28331600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 28341600c3e5SJian Shen for (i = 0; i < separator_num; i++) 28351600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 28361600c3e5SJian Shen 28371600c3e5SJian Shen reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 28381600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 28391600c3e5SJian Shen for (j = 0; j < hdev->num_tqps; j++) { 28401600c3e5SJian Shen for (i = 0; i < reg_um; i++) 28411600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 28421600c3e5SJian Shen ring_reg_addr_list[i] + 28431600c3e5SJian Shen 0x200 * j); 28441600c3e5SJian Shen for (i = 0; i < separator_num; i++) 28451600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 28461600c3e5SJian Shen } 28471600c3e5SJian Shen 28481600c3e5SJian Shen reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 28491600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 28501600c3e5SJian Shen for (j = 0; j < hdev->num_msi_used - 1; j++) { 28511600c3e5SJian Shen for (i = 0; i < reg_um; i++) 28521600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 28531600c3e5SJian Shen tqp_intr_reg_addr_list[i] + 28541600c3e5SJian Shen 4 * j); 28551600c3e5SJian Shen for (i = 0; i < separator_num; i++) 28561600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 28571600c3e5SJian Shen } 28581600c3e5SJian Shen } 28591600c3e5SJian Shen 286092f11ea1SJian Shen void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 286192f11ea1SJian Shen u8 *port_base_vlan_info, u8 data_size) 286292f11ea1SJian Shen { 286392f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 286492f11ea1SJian Shen 286592f11ea1SJian Shen rtnl_lock(); 286692f11ea1SJian Shen hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 286792f11ea1SJian Shen rtnl_unlock(); 286892f11ea1SJian Shen 286992f11ea1SJian Shen /* send msg to PF and wait update port based vlan info */ 287092f11ea1SJian Shen hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 287192f11ea1SJian Shen HCLGE_MBX_PORT_BASE_VLAN_CFG, 287292f11ea1SJian Shen port_base_vlan_info, data_size, 287392f11ea1SJian Shen false, NULL, 0); 287492f11ea1SJian Shen 287592f11ea1SJian Shen if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 287692f11ea1SJian Shen nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 287792f11ea1SJian Shen else 287892f11ea1SJian Shen nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 287992f11ea1SJian Shen 288092f11ea1SJian Shen rtnl_lock(); 288192f11ea1SJian Shen hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 288292f11ea1SJian Shen rtnl_unlock(); 288392f11ea1SJian Shen } 288492f11ea1SJian Shen 2885e2cb1decSSalil Mehta static const struct hnae3_ae_ops hclgevf_ops = { 2886e2cb1decSSalil Mehta .init_ae_dev = hclgevf_init_ae_dev, 2887e2cb1decSSalil Mehta .uninit_ae_dev = hclgevf_uninit_ae_dev, 28886ff3cf07SHuazhong Tan .flr_prepare = hclgevf_flr_prepare, 28896ff3cf07SHuazhong Tan .flr_done = hclgevf_flr_done, 2890e718a93fSPeng Li .init_client_instance = hclgevf_init_client_instance, 2891e718a93fSPeng Li .uninit_client_instance = hclgevf_uninit_client_instance, 2892e2cb1decSSalil Mehta .start = hclgevf_ae_start, 2893e2cb1decSSalil Mehta .stop = hclgevf_ae_stop, 2894a6d818e3SYunsheng Lin .client_start = hclgevf_client_start, 2895a6d818e3SYunsheng Lin .client_stop = hclgevf_client_stop, 2896e2cb1decSSalil Mehta .map_ring_to_vector = hclgevf_map_ring_to_vector, 2897e2cb1decSSalil Mehta .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 2898e2cb1decSSalil Mehta .get_vector = hclgevf_get_vector, 28990d3e6631SYunsheng Lin .put_vector = hclgevf_put_vector, 2900e2cb1decSSalil Mehta .reset_queue = hclgevf_reset_tqp, 2901e2cb1decSSalil Mehta .get_mac_addr = hclgevf_get_mac_addr, 2902e2cb1decSSalil Mehta .set_mac_addr = hclgevf_set_mac_addr, 2903e2cb1decSSalil Mehta .add_uc_addr = hclgevf_add_uc_addr, 2904e2cb1decSSalil Mehta .rm_uc_addr = hclgevf_rm_uc_addr, 2905e2cb1decSSalil Mehta .add_mc_addr = hclgevf_add_mc_addr, 2906e2cb1decSSalil Mehta .rm_mc_addr = hclgevf_rm_mc_addr, 2907e2cb1decSSalil Mehta .get_stats = hclgevf_get_stats, 2908e2cb1decSSalil Mehta .update_stats = hclgevf_update_stats, 2909e2cb1decSSalil Mehta .get_strings = hclgevf_get_strings, 2910e2cb1decSSalil Mehta .get_sset_count = hclgevf_get_sset_count, 2911e2cb1decSSalil Mehta .get_rss_key_size = hclgevf_get_rss_key_size, 2912e2cb1decSSalil Mehta .get_rss_indir_size = hclgevf_get_rss_indir_size, 2913e2cb1decSSalil Mehta .get_rss = hclgevf_get_rss, 2914e2cb1decSSalil Mehta .set_rss = hclgevf_set_rss, 2915d97b3072SJian Shen .get_rss_tuple = hclgevf_get_rss_tuple, 2916d97b3072SJian Shen .set_rss_tuple = hclgevf_set_rss_tuple, 2917e2cb1decSSalil Mehta .get_tc_size = hclgevf_get_tc_size, 2918e2cb1decSSalil Mehta .get_fw_version = hclgevf_get_fw_version, 2919e2cb1decSSalil Mehta .set_vlan_filter = hclgevf_set_vlan_filter, 2920b2641e2aSYunsheng Lin .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 29216d4c3981SSalil Mehta .reset_event = hclgevf_reset_event, 2922720bd583SHuazhong Tan .set_default_reset_request = hclgevf_set_def_reset_request, 2923849e4607SPeng Li .get_channels = hclgevf_get_channels, 2924cc719218SPeng Li .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 29251600c3e5SJian Shen .get_regs_len = hclgevf_get_regs_len, 29261600c3e5SJian Shen .get_regs = hclgevf_get_regs, 2927175ec96bSFuyun Liang .get_status = hclgevf_get_status, 29284a152de9SFuyun Liang .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 2929c136b884SPeng Li .get_media_type = hclgevf_get_media_type, 29304d60291bSHuazhong Tan .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 29314d60291bSHuazhong Tan .ae_dev_resetting = hclgevf_ae_dev_resetting, 29324d60291bSHuazhong Tan .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 29335c9f6b39SPeng Li .set_gro_en = hclgevf_gro_en, 2934818f1675SYunsheng Lin .set_mtu = hclgevf_set_mtu, 29350c29d191Sliuzhongzhu .get_global_queue_id = hclgevf_get_qid_global, 29368cdb992fSJian Shen .set_timer_task = hclgevf_set_timer_task, 29379194d18bSliuzhongzhu .get_link_mode = hclgevf_get_link_mode, 2938e2cb1decSSalil Mehta }; 2939e2cb1decSSalil Mehta 2940e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf = { 2941e2cb1decSSalil Mehta .ops = &hclgevf_ops, 2942e2cb1decSSalil Mehta .pdev_id_table = ae_algovf_pci_tbl, 2943e2cb1decSSalil Mehta }; 2944e2cb1decSSalil Mehta 2945e2cb1decSSalil Mehta static int hclgevf_init(void) 2946e2cb1decSSalil Mehta { 2947e2cb1decSSalil Mehta pr_info("%s is initializing\n", HCLGEVF_NAME); 2948e2cb1decSSalil Mehta 2949854cf33aSFuyun Liang hnae3_register_ae_algo(&ae_algovf); 2950854cf33aSFuyun Liang 2951854cf33aSFuyun Liang return 0; 2952e2cb1decSSalil Mehta } 2953e2cb1decSSalil Mehta 2954e2cb1decSSalil Mehta static void hclgevf_exit(void) 2955e2cb1decSSalil Mehta { 2956e2cb1decSSalil Mehta hnae3_unregister_ae_algo(&ae_algovf); 2957e2cb1decSSalil Mehta } 2958e2cb1decSSalil Mehta module_init(hclgevf_init); 2959e2cb1decSSalil Mehta module_exit(hclgevf_exit); 2960e2cb1decSSalil Mehta 2961e2cb1decSSalil Mehta MODULE_LICENSE("GPL"); 2962e2cb1decSSalil Mehta MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 2963e2cb1decSSalil Mehta MODULE_DESCRIPTION("HCLGEVF Driver"); 2964e2cb1decSSalil Mehta MODULE_VERSION(HCLGEVF_MOD_VERSION); 2965