1e2cb1decSSalil Mehta // SPDX-License-Identifier: GPL-2.0+ 2e2cb1decSSalil Mehta // Copyright (c) 2016-2017 Hisilicon Limited. 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #include <linux/etherdevice.h> 56988eb2aSSalil Mehta #include <net/rtnetlink.h> 6e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 7e2cb1decSSalil Mehta #include "hclgevf_main.h" 8e2cb1decSSalil Mehta #include "hclge_mbx.h" 9e2cb1decSSalil Mehta #include "hnae3.h" 10e2cb1decSSalil Mehta 11e2cb1decSSalil Mehta #define HCLGEVF_NAME "hclgevf" 12e2cb1decSSalil Mehta 137a01c897SSalil Mehta static int hclgevf_init_hdev(struct hclgevf_dev *hdev); 147a01c897SSalil Mehta static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev); 15e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf; 16e2cb1decSSalil Mehta 17e2cb1decSSalil Mehta static const struct pci_device_id ae_algovf_pci_tbl[] = { 18e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 19e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 20e2cb1decSSalil Mehta /* required last entry */ 21e2cb1decSSalil Mehta {0, } 22e2cb1decSSalil Mehta }; 23e2cb1decSSalil Mehta 242f550a46SYunsheng Lin MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 252f550a46SYunsheng Lin 26e2cb1decSSalil Mehta static inline struct hclgevf_dev *hclgevf_ae_get_hdev( 27e2cb1decSSalil Mehta struct hnae3_handle *handle) 28e2cb1decSSalil Mehta { 29e2cb1decSSalil Mehta return container_of(handle, struct hclgevf_dev, nic); 30e2cb1decSSalil Mehta } 31e2cb1decSSalil Mehta 32e2cb1decSSalil Mehta static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 33e2cb1decSSalil Mehta { 34e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 35e2cb1decSSalil Mehta struct hnae3_queue *queue; 36e2cb1decSSalil Mehta struct hclgevf_desc desc; 37e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 38e2cb1decSSalil Mehta int status; 39e2cb1decSSalil Mehta int i; 40e2cb1decSSalil Mehta 41e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 42e2cb1decSSalil Mehta queue = handle->kinfo.tqp[i]; 43e2cb1decSSalil Mehta tqp = container_of(queue, struct hclgevf_tqp, q); 44e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 45e2cb1decSSalil Mehta HCLGEVF_OPC_QUERY_RX_STATUS, 46e2cb1decSSalil Mehta true); 47e2cb1decSSalil Mehta 48e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 49e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 50e2cb1decSSalil Mehta if (status) { 51e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 52e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 53e2cb1decSSalil Mehta status, i); 54e2cb1decSSalil Mehta return status; 55e2cb1decSSalil Mehta } 56e2cb1decSSalil Mehta tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 57cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 58e2cb1decSSalil Mehta 59e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 60e2cb1decSSalil Mehta true); 61e2cb1decSSalil Mehta 62e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 63e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 64e2cb1decSSalil Mehta if (status) { 65e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 66e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 67e2cb1decSSalil Mehta status, i); 68e2cb1decSSalil Mehta return status; 69e2cb1decSSalil Mehta } 70e2cb1decSSalil Mehta tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 71cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 72e2cb1decSSalil Mehta } 73e2cb1decSSalil Mehta 74e2cb1decSSalil Mehta return 0; 75e2cb1decSSalil Mehta } 76e2cb1decSSalil Mehta 77e2cb1decSSalil Mehta static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 78e2cb1decSSalil Mehta { 79e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo = &handle->kinfo; 80e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 81e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 82e2cb1decSSalil Mehta u64 *buff = data; 83e2cb1decSSalil Mehta int i; 84e2cb1decSSalil Mehta 85e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 86e2cb1decSSalil Mehta tqp = container_of(handle->kinfo.tqp[i], struct hclgevf_tqp, q); 87e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 88e2cb1decSSalil Mehta } 89e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 90e2cb1decSSalil Mehta tqp = container_of(handle->kinfo.tqp[i], struct hclgevf_tqp, q); 91e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 92e2cb1decSSalil Mehta } 93e2cb1decSSalil Mehta 94e2cb1decSSalil Mehta return buff; 95e2cb1decSSalil Mehta } 96e2cb1decSSalil Mehta 97e2cb1decSSalil Mehta static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 98e2cb1decSSalil Mehta { 99e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 100e2cb1decSSalil Mehta 101e2cb1decSSalil Mehta return hdev->num_tqps * 2; 102e2cb1decSSalil Mehta } 103e2cb1decSSalil Mehta 104e2cb1decSSalil Mehta static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 105e2cb1decSSalil Mehta { 106e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 107e2cb1decSSalil Mehta u8 *buff = data; 108e2cb1decSSalil Mehta int i = 0; 109e2cb1decSSalil Mehta 110e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 111e2cb1decSSalil Mehta struct hclgevf_tqp *tqp = container_of(handle->kinfo.tqp[i], 112e2cb1decSSalil Mehta struct hclgevf_tqp, q); 113a6c51c26SJian Shen snprintf(buff, ETH_GSTRING_LEN, "txq#%d_pktnum_rcd", 114e2cb1decSSalil Mehta tqp->index); 115e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 116e2cb1decSSalil Mehta } 117e2cb1decSSalil Mehta 118e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 119e2cb1decSSalil Mehta struct hclgevf_tqp *tqp = container_of(handle->kinfo.tqp[i], 120e2cb1decSSalil Mehta struct hclgevf_tqp, q); 121a6c51c26SJian Shen snprintf(buff, ETH_GSTRING_LEN, "rxq#%d_pktnum_rcd", 122e2cb1decSSalil Mehta tqp->index); 123e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 124e2cb1decSSalil Mehta } 125e2cb1decSSalil Mehta 126e2cb1decSSalil Mehta return buff; 127e2cb1decSSalil Mehta } 128e2cb1decSSalil Mehta 129e2cb1decSSalil Mehta static void hclgevf_update_stats(struct hnae3_handle *handle, 130e2cb1decSSalil Mehta struct net_device_stats *net_stats) 131e2cb1decSSalil Mehta { 132e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 133e2cb1decSSalil Mehta int status; 134e2cb1decSSalil Mehta 135e2cb1decSSalil Mehta status = hclgevf_tqps_update_stats(handle); 136e2cb1decSSalil Mehta if (status) 137e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 138e2cb1decSSalil Mehta "VF update of TQPS stats fail, status = %d.\n", 139e2cb1decSSalil Mehta status); 140e2cb1decSSalil Mehta } 141e2cb1decSSalil Mehta 142e2cb1decSSalil Mehta static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 143e2cb1decSSalil Mehta { 144e2cb1decSSalil Mehta if (strset == ETH_SS_TEST) 145e2cb1decSSalil Mehta return -EOPNOTSUPP; 146e2cb1decSSalil Mehta else if (strset == ETH_SS_STATS) 147e2cb1decSSalil Mehta return hclgevf_tqps_get_sset_count(handle, strset); 148e2cb1decSSalil Mehta 149e2cb1decSSalil Mehta return 0; 150e2cb1decSSalil Mehta } 151e2cb1decSSalil Mehta 152e2cb1decSSalil Mehta static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 153e2cb1decSSalil Mehta u8 *data) 154e2cb1decSSalil Mehta { 155e2cb1decSSalil Mehta u8 *p = (char *)data; 156e2cb1decSSalil Mehta 157e2cb1decSSalil Mehta if (strset == ETH_SS_STATS) 158e2cb1decSSalil Mehta p = hclgevf_tqps_get_strings(handle, p); 159e2cb1decSSalil Mehta } 160e2cb1decSSalil Mehta 161e2cb1decSSalil Mehta static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 162e2cb1decSSalil Mehta { 163e2cb1decSSalil Mehta hclgevf_tqps_get_stats(handle, data); 164e2cb1decSSalil Mehta } 165e2cb1decSSalil Mehta 166e2cb1decSSalil Mehta static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 167e2cb1decSSalil Mehta { 168e2cb1decSSalil Mehta u8 resp_msg; 169e2cb1decSSalil Mehta int status; 170e2cb1decSSalil Mehta 171e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 172e2cb1decSSalil Mehta true, &resp_msg, sizeof(u8)); 173e2cb1decSSalil Mehta if (status) { 174e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 175e2cb1decSSalil Mehta "VF request to get TC info from PF failed %d", 176e2cb1decSSalil Mehta status); 177e2cb1decSSalil Mehta return status; 178e2cb1decSSalil Mehta } 179e2cb1decSSalil Mehta 180e2cb1decSSalil Mehta hdev->hw_tc_map = resp_msg; 181e2cb1decSSalil Mehta 182e2cb1decSSalil Mehta return 0; 183e2cb1decSSalil Mehta } 184e2cb1decSSalil Mehta 185e2cb1decSSalil Mehta static int hclge_get_queue_info(struct hclgevf_dev *hdev) 186e2cb1decSSalil Mehta { 187e2cb1decSSalil Mehta #define HCLGEVF_TQPS_RSS_INFO_LEN 8 188e2cb1decSSalil Mehta u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 189e2cb1decSSalil Mehta int status; 190e2cb1decSSalil Mehta 191e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 192e2cb1decSSalil Mehta true, resp_msg, 193e2cb1decSSalil Mehta HCLGEVF_TQPS_RSS_INFO_LEN); 194e2cb1decSSalil Mehta if (status) { 195e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 196e2cb1decSSalil Mehta "VF request to get tqp info from PF failed %d", 197e2cb1decSSalil Mehta status); 198e2cb1decSSalil Mehta return status; 199e2cb1decSSalil Mehta } 200e2cb1decSSalil Mehta 201e2cb1decSSalil Mehta memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 202e2cb1decSSalil Mehta memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 203e2cb1decSSalil Mehta memcpy(&hdev->num_desc, &resp_msg[4], sizeof(u16)); 204e2cb1decSSalil Mehta memcpy(&hdev->rx_buf_len, &resp_msg[6], sizeof(u16)); 205e2cb1decSSalil Mehta 206e2cb1decSSalil Mehta return 0; 207e2cb1decSSalil Mehta } 208e2cb1decSSalil Mehta 209e2cb1decSSalil Mehta static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 210e2cb1decSSalil Mehta { 211e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 212e2cb1decSSalil Mehta int i; 213e2cb1decSSalil Mehta 2147a01c897SSalil Mehta /* if this is on going reset then we need to re-allocate the TPQs 2157a01c897SSalil Mehta * since we cannot assume we would get same number of TPQs back from PF 2167a01c897SSalil Mehta */ 2177a01c897SSalil Mehta if (hclgevf_dev_ongoing_reset(hdev)) 2187a01c897SSalil Mehta devm_kfree(&hdev->pdev->dev, hdev->htqp); 2197a01c897SSalil Mehta 220e2cb1decSSalil Mehta hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 221e2cb1decSSalil Mehta sizeof(struct hclgevf_tqp), GFP_KERNEL); 222e2cb1decSSalil Mehta if (!hdev->htqp) 223e2cb1decSSalil Mehta return -ENOMEM; 224e2cb1decSSalil Mehta 225e2cb1decSSalil Mehta tqp = hdev->htqp; 226e2cb1decSSalil Mehta 227e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 228e2cb1decSSalil Mehta tqp->dev = &hdev->pdev->dev; 229e2cb1decSSalil Mehta tqp->index = i; 230e2cb1decSSalil Mehta 231e2cb1decSSalil Mehta tqp->q.ae_algo = &ae_algovf; 232e2cb1decSSalil Mehta tqp->q.buf_size = hdev->rx_buf_len; 233e2cb1decSSalil Mehta tqp->q.desc_num = hdev->num_desc; 234e2cb1decSSalil Mehta tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 235e2cb1decSSalil Mehta i * HCLGEVF_TQP_REG_SIZE; 236e2cb1decSSalil Mehta 237e2cb1decSSalil Mehta tqp++; 238e2cb1decSSalil Mehta } 239e2cb1decSSalil Mehta 240e2cb1decSSalil Mehta return 0; 241e2cb1decSSalil Mehta } 242e2cb1decSSalil Mehta 243e2cb1decSSalil Mehta static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 244e2cb1decSSalil Mehta { 245e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 246e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo; 247e2cb1decSSalil Mehta u16 new_tqps = hdev->num_tqps; 248e2cb1decSSalil Mehta int i; 249e2cb1decSSalil Mehta 250e2cb1decSSalil Mehta kinfo = &nic->kinfo; 251e2cb1decSSalil Mehta kinfo->num_tc = 0; 252e2cb1decSSalil Mehta kinfo->num_desc = hdev->num_desc; 253e2cb1decSSalil Mehta kinfo->rx_buf_len = hdev->rx_buf_len; 254e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 255e2cb1decSSalil Mehta if (hdev->hw_tc_map & BIT(i)) 256e2cb1decSSalil Mehta kinfo->num_tc++; 257e2cb1decSSalil Mehta 258e2cb1decSSalil Mehta kinfo->rss_size 259e2cb1decSSalil Mehta = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 260e2cb1decSSalil Mehta new_tqps = kinfo->rss_size * kinfo->num_tc; 261e2cb1decSSalil Mehta kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 262e2cb1decSSalil Mehta 2637a01c897SSalil Mehta /* if this is on going reset then we need to re-allocate the hnae queues 2647a01c897SSalil Mehta * as well since number of TPQs from PF might have changed. 2657a01c897SSalil Mehta */ 2667a01c897SSalil Mehta if (hclgevf_dev_ongoing_reset(hdev)) 2677a01c897SSalil Mehta devm_kfree(&hdev->pdev->dev, kinfo->tqp); 2687a01c897SSalil Mehta 269e2cb1decSSalil Mehta kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 270e2cb1decSSalil Mehta sizeof(struct hnae3_queue *), GFP_KERNEL); 271e2cb1decSSalil Mehta if (!kinfo->tqp) 272e2cb1decSSalil Mehta return -ENOMEM; 273e2cb1decSSalil Mehta 274e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 275e2cb1decSSalil Mehta hdev->htqp[i].q.handle = &hdev->nic; 276e2cb1decSSalil Mehta hdev->htqp[i].q.tqp_index = i; 277e2cb1decSSalil Mehta kinfo->tqp[i] = &hdev->htqp[i].q; 278e2cb1decSSalil Mehta } 279e2cb1decSSalil Mehta 280e2cb1decSSalil Mehta return 0; 281e2cb1decSSalil Mehta } 282e2cb1decSSalil Mehta 283e2cb1decSSalil Mehta static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 284e2cb1decSSalil Mehta { 285e2cb1decSSalil Mehta int status; 286e2cb1decSSalil Mehta u8 resp_msg; 287e2cb1decSSalil Mehta 288e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 289e2cb1decSSalil Mehta 0, false, &resp_msg, sizeof(u8)); 290e2cb1decSSalil Mehta if (status) 291e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 292e2cb1decSSalil Mehta "VF failed to fetch link status(%d) from PF", status); 293e2cb1decSSalil Mehta } 294e2cb1decSSalil Mehta 295e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 296e2cb1decSSalil Mehta { 297e2cb1decSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 298e2cb1decSSalil Mehta struct hnae3_client *client; 299e2cb1decSSalil Mehta 300e2cb1decSSalil Mehta client = handle->client; 301e2cb1decSSalil Mehta 302e2cb1decSSalil Mehta if (link_state != hdev->hw.mac.link) { 303e2cb1decSSalil Mehta client->ops->link_status_change(handle, !!link_state); 304e2cb1decSSalil Mehta hdev->hw.mac.link = link_state; 305e2cb1decSSalil Mehta } 306e2cb1decSSalil Mehta } 307e2cb1decSSalil Mehta 308e2cb1decSSalil Mehta static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 309e2cb1decSSalil Mehta { 310e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 311e2cb1decSSalil Mehta int ret; 312e2cb1decSSalil Mehta 313e2cb1decSSalil Mehta nic->ae_algo = &ae_algovf; 314e2cb1decSSalil Mehta nic->pdev = hdev->pdev; 315e2cb1decSSalil Mehta nic->numa_node_mask = hdev->numa_node_mask; 316424eb834SSalil Mehta nic->flags |= HNAE3_SUPPORT_VF; 317e2cb1decSSalil Mehta 318e2cb1decSSalil Mehta if (hdev->ae_dev->dev_type != HNAE3_DEV_KNIC) { 319e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "unsupported device type %d\n", 320e2cb1decSSalil Mehta hdev->ae_dev->dev_type); 321e2cb1decSSalil Mehta return -EINVAL; 322e2cb1decSSalil Mehta } 323e2cb1decSSalil Mehta 324e2cb1decSSalil Mehta ret = hclgevf_knic_setup(hdev); 325e2cb1decSSalil Mehta if (ret) 326e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 327e2cb1decSSalil Mehta ret); 328e2cb1decSSalil Mehta return ret; 329e2cb1decSSalil Mehta } 330e2cb1decSSalil Mehta 331e2cb1decSSalil Mehta static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 332e2cb1decSSalil Mehta { 333e2cb1decSSalil Mehta hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 334e2cb1decSSalil Mehta hdev->num_msi_left += 1; 335e2cb1decSSalil Mehta hdev->num_msi_used -= 1; 336e2cb1decSSalil Mehta } 337e2cb1decSSalil Mehta 338e2cb1decSSalil Mehta static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 339e2cb1decSSalil Mehta struct hnae3_vector_info *vector_info) 340e2cb1decSSalil Mehta { 341e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 342e2cb1decSSalil Mehta struct hnae3_vector_info *vector = vector_info; 343e2cb1decSSalil Mehta int alloc = 0; 344e2cb1decSSalil Mehta int i, j; 345e2cb1decSSalil Mehta 346e2cb1decSSalil Mehta vector_num = min(hdev->num_msi_left, vector_num); 347e2cb1decSSalil Mehta 348e2cb1decSSalil Mehta for (j = 0; j < vector_num; j++) { 349e2cb1decSSalil Mehta for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 350e2cb1decSSalil Mehta if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 351e2cb1decSSalil Mehta vector->vector = pci_irq_vector(hdev->pdev, i); 352e2cb1decSSalil Mehta vector->io_addr = hdev->hw.io_base + 353e2cb1decSSalil Mehta HCLGEVF_VECTOR_REG_BASE + 354e2cb1decSSalil Mehta (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 355e2cb1decSSalil Mehta hdev->vector_status[i] = 0; 356e2cb1decSSalil Mehta hdev->vector_irq[i] = vector->vector; 357e2cb1decSSalil Mehta 358e2cb1decSSalil Mehta vector++; 359e2cb1decSSalil Mehta alloc++; 360e2cb1decSSalil Mehta 361e2cb1decSSalil Mehta break; 362e2cb1decSSalil Mehta } 363e2cb1decSSalil Mehta } 364e2cb1decSSalil Mehta } 365e2cb1decSSalil Mehta hdev->num_msi_left -= alloc; 366e2cb1decSSalil Mehta hdev->num_msi_used += alloc; 367e2cb1decSSalil Mehta 368e2cb1decSSalil Mehta return alloc; 369e2cb1decSSalil Mehta } 370e2cb1decSSalil Mehta 371e2cb1decSSalil Mehta static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 372e2cb1decSSalil Mehta { 373e2cb1decSSalil Mehta int i; 374e2cb1decSSalil Mehta 375e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 376e2cb1decSSalil Mehta if (vector == hdev->vector_irq[i]) 377e2cb1decSSalil Mehta return i; 378e2cb1decSSalil Mehta 379e2cb1decSSalil Mehta return -EINVAL; 380e2cb1decSSalil Mehta } 381e2cb1decSSalil Mehta 382e2cb1decSSalil Mehta static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 383e2cb1decSSalil Mehta { 384e2cb1decSSalil Mehta return HCLGEVF_RSS_KEY_SIZE; 385e2cb1decSSalil Mehta } 386e2cb1decSSalil Mehta 387e2cb1decSSalil Mehta static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 388e2cb1decSSalil Mehta { 389e2cb1decSSalil Mehta return HCLGEVF_RSS_IND_TBL_SIZE; 390e2cb1decSSalil Mehta } 391e2cb1decSSalil Mehta 392e2cb1decSSalil Mehta static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 393e2cb1decSSalil Mehta { 394e2cb1decSSalil Mehta const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 395e2cb1decSSalil Mehta struct hclgevf_rss_indirection_table_cmd *req; 396e2cb1decSSalil Mehta struct hclgevf_desc desc; 397e2cb1decSSalil Mehta int status; 398e2cb1decSSalil Mehta int i, j; 399e2cb1decSSalil Mehta 400e2cb1decSSalil Mehta req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 401e2cb1decSSalil Mehta 402e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 403e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 404e2cb1decSSalil Mehta false); 405e2cb1decSSalil Mehta req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 406e2cb1decSSalil Mehta req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 407e2cb1decSSalil Mehta for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 408e2cb1decSSalil Mehta req->rss_result[j] = 409e2cb1decSSalil Mehta indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 410e2cb1decSSalil Mehta 411e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 412e2cb1decSSalil Mehta if (status) { 413e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 414e2cb1decSSalil Mehta "VF failed(=%d) to set RSS indirection table\n", 415e2cb1decSSalil Mehta status); 416e2cb1decSSalil Mehta return status; 417e2cb1decSSalil Mehta } 418e2cb1decSSalil Mehta } 419e2cb1decSSalil Mehta 420e2cb1decSSalil Mehta return 0; 421e2cb1decSSalil Mehta } 422e2cb1decSSalil Mehta 423e2cb1decSSalil Mehta static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 424e2cb1decSSalil Mehta { 425e2cb1decSSalil Mehta struct hclgevf_rss_tc_mode_cmd *req; 426e2cb1decSSalil Mehta u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 427e2cb1decSSalil Mehta u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 428e2cb1decSSalil Mehta u16 tc_size[HCLGEVF_MAX_TC_NUM]; 429e2cb1decSSalil Mehta struct hclgevf_desc desc; 430e2cb1decSSalil Mehta u16 roundup_size; 431e2cb1decSSalil Mehta int status; 432e2cb1decSSalil Mehta int i; 433e2cb1decSSalil Mehta 434e2cb1decSSalil Mehta req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 435e2cb1decSSalil Mehta 436e2cb1decSSalil Mehta roundup_size = roundup_pow_of_two(rss_size); 437e2cb1decSSalil Mehta roundup_size = ilog2(roundup_size); 438e2cb1decSSalil Mehta 439e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 440e2cb1decSSalil Mehta tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 441e2cb1decSSalil Mehta tc_size[i] = roundup_size; 442e2cb1decSSalil Mehta tc_offset[i] = rss_size * i; 443e2cb1decSSalil Mehta } 444e2cb1decSSalil Mehta 445e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 446e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 447e2cb1decSSalil Mehta hnae_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 448e2cb1decSSalil Mehta (tc_valid[i] & 0x1)); 449e2cb1decSSalil Mehta hnae_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 450e2cb1decSSalil Mehta HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 451e2cb1decSSalil Mehta hnae_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 452e2cb1decSSalil Mehta HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 453e2cb1decSSalil Mehta } 454e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 455e2cb1decSSalil Mehta if (status) 456e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 457e2cb1decSSalil Mehta "VF failed(=%d) to set rss tc mode\n", status); 458e2cb1decSSalil Mehta 459e2cb1decSSalil Mehta return status; 460e2cb1decSSalil Mehta } 461e2cb1decSSalil Mehta 462e2cb1decSSalil Mehta static int hclgevf_get_rss_hw_cfg(struct hnae3_handle *handle, u8 *hash, 463e2cb1decSSalil Mehta u8 *key) 464e2cb1decSSalil Mehta { 465e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 466e2cb1decSSalil Mehta struct hclgevf_rss_config_cmd *req; 467e2cb1decSSalil Mehta int lkup_times = key ? 3 : 1; 468e2cb1decSSalil Mehta struct hclgevf_desc desc; 469e2cb1decSSalil Mehta int key_offset; 470e2cb1decSSalil Mehta int key_size; 471e2cb1decSSalil Mehta int status; 472e2cb1decSSalil Mehta 473e2cb1decSSalil Mehta req = (struct hclgevf_rss_config_cmd *)desc.data; 474e2cb1decSSalil Mehta lkup_times = (lkup_times == 3) ? 3 : ((hash) ? 1 : 0); 475e2cb1decSSalil Mehta 476e2cb1decSSalil Mehta for (key_offset = 0; key_offset < lkup_times; key_offset++) { 477e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 478e2cb1decSSalil Mehta HCLGEVF_OPC_RSS_GENERIC_CONFIG, 479e2cb1decSSalil Mehta true); 480e2cb1decSSalil Mehta req->hash_config |= (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET); 481e2cb1decSSalil Mehta 482e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 483e2cb1decSSalil Mehta if (status) { 484e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 485e2cb1decSSalil Mehta "failed to get hardware RSS cfg, status = %d\n", 486e2cb1decSSalil Mehta status); 487e2cb1decSSalil Mehta return status; 488e2cb1decSSalil Mehta } 489e2cb1decSSalil Mehta 490e2cb1decSSalil Mehta if (key_offset == 2) 491e2cb1decSSalil Mehta key_size = 492e2cb1decSSalil Mehta HCLGEVF_RSS_KEY_SIZE - HCLGEVF_RSS_HASH_KEY_NUM * 2; 493e2cb1decSSalil Mehta else 494e2cb1decSSalil Mehta key_size = HCLGEVF_RSS_HASH_KEY_NUM; 495e2cb1decSSalil Mehta 496e2cb1decSSalil Mehta if (key) 497e2cb1decSSalil Mehta memcpy(key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, 498e2cb1decSSalil Mehta req->hash_key, 499e2cb1decSSalil Mehta key_size); 500e2cb1decSSalil Mehta } 501e2cb1decSSalil Mehta 502e2cb1decSSalil Mehta if (hash) { 503e2cb1decSSalil Mehta if ((req->hash_config & 0xf) == HCLGEVF_RSS_HASH_ALGO_TOEPLITZ) 504e2cb1decSSalil Mehta *hash = ETH_RSS_HASH_TOP; 505e2cb1decSSalil Mehta else 506e2cb1decSSalil Mehta *hash = ETH_RSS_HASH_UNKNOWN; 507e2cb1decSSalil Mehta } 508e2cb1decSSalil Mehta 509e2cb1decSSalil Mehta return 0; 510e2cb1decSSalil Mehta } 511e2cb1decSSalil Mehta 512e2cb1decSSalil Mehta static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 513e2cb1decSSalil Mehta u8 *hfunc) 514e2cb1decSSalil Mehta { 515e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 516e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 517e2cb1decSSalil Mehta int i; 518e2cb1decSSalil Mehta 519e2cb1decSSalil Mehta if (indir) 520e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 521e2cb1decSSalil Mehta indir[i] = rss_cfg->rss_indirection_tbl[i]; 522e2cb1decSSalil Mehta 523e2cb1decSSalil Mehta return hclgevf_get_rss_hw_cfg(handle, hfunc, key); 524e2cb1decSSalil Mehta } 525e2cb1decSSalil Mehta 526e2cb1decSSalil Mehta static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 527e2cb1decSSalil Mehta const u8 *key, const u8 hfunc) 528e2cb1decSSalil Mehta { 529e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 530e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 531e2cb1decSSalil Mehta int i; 532e2cb1decSSalil Mehta 533e2cb1decSSalil Mehta /* update the shadow RSS table with user specified qids */ 534e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 535e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = indir[i]; 536e2cb1decSSalil Mehta 537e2cb1decSSalil Mehta /* update the hardware */ 538e2cb1decSSalil Mehta return hclgevf_set_rss_indir_table(hdev); 539e2cb1decSSalil Mehta } 540e2cb1decSSalil Mehta 541e2cb1decSSalil Mehta static int hclgevf_get_tc_size(struct hnae3_handle *handle) 542e2cb1decSSalil Mehta { 543e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 544e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 545e2cb1decSSalil Mehta 546e2cb1decSSalil Mehta return rss_cfg->rss_size; 547e2cb1decSSalil Mehta } 548e2cb1decSSalil Mehta 549e2cb1decSSalil Mehta static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 550e2cb1decSSalil Mehta int vector, 551e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 552e2cb1decSSalil Mehta { 553e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 554e2cb1decSSalil Mehta struct hnae3_ring_chain_node *node; 555e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 556e2cb1decSSalil Mehta struct hclgevf_desc desc; 5575d02a58dSYunsheng Lin int i = 0, vector_id; 558e2cb1decSSalil Mehta int status; 559e2cb1decSSalil Mehta u8 type; 560e2cb1decSSalil Mehta 561e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 562e2cb1decSSalil Mehta vector_id = hclgevf_get_vector_index(hdev, vector); 563e2cb1decSSalil Mehta if (vector_id < 0) { 564e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 565e2cb1decSSalil Mehta "Get vector index fail. ret =%d\n", vector_id); 566e2cb1decSSalil Mehta return vector_id; 567e2cb1decSSalil Mehta } 568e2cb1decSSalil Mehta 569e2cb1decSSalil Mehta for (node = ring_chain; node; node = node->next) { 5705d02a58dSYunsheng Lin int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 5715d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 5725d02a58dSYunsheng Lin 5735d02a58dSYunsheng Lin if (i == 0) { 5745d02a58dSYunsheng Lin hclgevf_cmd_setup_basic_desc(&desc, 5755d02a58dSYunsheng Lin HCLGEVF_OPC_MBX_VF_TO_PF, 5765d02a58dSYunsheng Lin false); 5775d02a58dSYunsheng Lin type = en ? 5785d02a58dSYunsheng Lin HCLGE_MBX_MAP_RING_TO_VECTOR : 5795d02a58dSYunsheng Lin HCLGE_MBX_UNMAP_RING_TO_VECTOR; 5805d02a58dSYunsheng Lin req->msg[0] = type; 5815d02a58dSYunsheng Lin req->msg[1] = vector_id; 5825d02a58dSYunsheng Lin } 5835d02a58dSYunsheng Lin 5845d02a58dSYunsheng Lin req->msg[idx_offset] = 585e2cb1decSSalil Mehta hnae_get_bit(node->flag, HNAE3_RING_TYPE_B); 5865d02a58dSYunsheng Lin req->msg[idx_offset + 1] = node->tqp_index; 5875d02a58dSYunsheng Lin req->msg[idx_offset + 2] = hnae_get_field(node->int_gl_idx, 58879eee410SFuyun Liang HNAE3_RING_GL_IDX_M, 58979eee410SFuyun Liang HNAE3_RING_GL_IDX_S); 59079eee410SFuyun Liang 5915d02a58dSYunsheng Lin i++; 5925d02a58dSYunsheng Lin if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 5935d02a58dSYunsheng Lin HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 5945d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 5955d02a58dSYunsheng Lin !node->next) { 596e2cb1decSSalil Mehta req->msg[2] = i; 597e2cb1decSSalil Mehta 598e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 599e2cb1decSSalil Mehta if (status) { 600e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 601e2cb1decSSalil Mehta "Map TQP fail, status is %d.\n", 602e2cb1decSSalil Mehta status); 603e2cb1decSSalil Mehta return status; 604e2cb1decSSalil Mehta } 605e2cb1decSSalil Mehta i = 0; 606e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 607e2cb1decSSalil Mehta HCLGEVF_OPC_MBX_VF_TO_PF, 608e2cb1decSSalil Mehta false); 609e2cb1decSSalil Mehta req->msg[0] = type; 610e2cb1decSSalil Mehta req->msg[1] = vector_id; 611e2cb1decSSalil Mehta } 612e2cb1decSSalil Mehta } 613e2cb1decSSalil Mehta 614e2cb1decSSalil Mehta return 0; 615e2cb1decSSalil Mehta } 616e2cb1decSSalil Mehta 617e2cb1decSSalil Mehta static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 618e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 619e2cb1decSSalil Mehta { 620e2cb1decSSalil Mehta return hclgevf_bind_ring_to_vector(handle, true, vector, ring_chain); 621e2cb1decSSalil Mehta } 622e2cb1decSSalil Mehta 623e2cb1decSSalil Mehta static int hclgevf_unmap_ring_from_vector( 624e2cb1decSSalil Mehta struct hnae3_handle *handle, 625e2cb1decSSalil Mehta int vector, 626e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 627e2cb1decSSalil Mehta { 628e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 629e2cb1decSSalil Mehta int ret, vector_id; 630e2cb1decSSalil Mehta 631e2cb1decSSalil Mehta vector_id = hclgevf_get_vector_index(hdev, vector); 632e2cb1decSSalil Mehta if (vector_id < 0) { 633e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 634e2cb1decSSalil Mehta "Get vector index fail. ret =%d\n", vector_id); 635e2cb1decSSalil Mehta return vector_id; 636e2cb1decSSalil Mehta } 637e2cb1decSSalil Mehta 638e2cb1decSSalil Mehta ret = hclgevf_bind_ring_to_vector(handle, false, vector, ring_chain); 6390d3e6631SYunsheng Lin if (ret) 640e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 641e2cb1decSSalil Mehta "Unmap ring from vector fail. vector=%d, ret =%d\n", 642e2cb1decSSalil Mehta vector_id, 643e2cb1decSSalil Mehta ret); 6440d3e6631SYunsheng Lin 645e2cb1decSSalil Mehta return ret; 646e2cb1decSSalil Mehta } 647e2cb1decSSalil Mehta 6480d3e6631SYunsheng Lin static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 6490d3e6631SYunsheng Lin { 6500d3e6631SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 6510d3e6631SYunsheng Lin 652e2cb1decSSalil Mehta hclgevf_free_vector(hdev, vector); 653e2cb1decSSalil Mehta 654e2cb1decSSalil Mehta return 0; 655e2cb1decSSalil Mehta } 656e2cb1decSSalil Mehta 657e2cb1decSSalil Mehta static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, u32 en) 658e2cb1decSSalil Mehta { 659e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 660e2cb1decSSalil Mehta struct hclgevf_desc desc; 661e2cb1decSSalil Mehta int status; 662e2cb1decSSalil Mehta 663e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 664e2cb1decSSalil Mehta 665e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 666e2cb1decSSalil Mehta req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 667e2cb1decSSalil Mehta req->msg[1] = en; 668e2cb1decSSalil Mehta 669e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 670e2cb1decSSalil Mehta if (status) 671e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 672e2cb1decSSalil Mehta "Set promisc mode fail, status is %d.\n", status); 673e2cb1decSSalil Mehta 674e2cb1decSSalil Mehta return status; 675e2cb1decSSalil Mehta } 676e2cb1decSSalil Mehta 677e2cb1decSSalil Mehta static void hclgevf_set_promisc_mode(struct hnae3_handle *handle, u32 en) 678e2cb1decSSalil Mehta { 679e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 680e2cb1decSSalil Mehta 681e2cb1decSSalil Mehta hclgevf_cmd_set_promisc_mode(hdev, en); 682e2cb1decSSalil Mehta } 683e2cb1decSSalil Mehta 684e2cb1decSSalil Mehta static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, int tqp_id, 685e2cb1decSSalil Mehta int stream_id, bool enable) 686e2cb1decSSalil Mehta { 687e2cb1decSSalil Mehta struct hclgevf_cfg_com_tqp_queue_cmd *req; 688e2cb1decSSalil Mehta struct hclgevf_desc desc; 689e2cb1decSSalil Mehta int status; 690e2cb1decSSalil Mehta 691e2cb1decSSalil Mehta req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 692e2cb1decSSalil Mehta 693e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 694e2cb1decSSalil Mehta false); 695e2cb1decSSalil Mehta req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 696e2cb1decSSalil Mehta req->stream_id = cpu_to_le16(stream_id); 697e2cb1decSSalil Mehta req->enable |= enable << HCLGEVF_TQP_ENABLE_B; 698e2cb1decSSalil Mehta 699e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 700e2cb1decSSalil Mehta if (status) 701e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 702e2cb1decSSalil Mehta "TQP enable fail, status =%d.\n", status); 703e2cb1decSSalil Mehta 704e2cb1decSSalil Mehta return status; 705e2cb1decSSalil Mehta } 706e2cb1decSSalil Mehta 707e2cb1decSSalil Mehta static int hclgevf_get_queue_id(struct hnae3_queue *queue) 708e2cb1decSSalil Mehta { 709e2cb1decSSalil Mehta struct hclgevf_tqp *tqp = container_of(queue, struct hclgevf_tqp, q); 710e2cb1decSSalil Mehta 711e2cb1decSSalil Mehta return tqp->index; 712e2cb1decSSalil Mehta } 713e2cb1decSSalil Mehta 714e2cb1decSSalil Mehta static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 715e2cb1decSSalil Mehta { 716e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 717e2cb1decSSalil Mehta struct hnae3_queue *queue; 718e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 719e2cb1decSSalil Mehta int i; 720e2cb1decSSalil Mehta 721e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 722e2cb1decSSalil Mehta queue = handle->kinfo.tqp[i]; 723e2cb1decSSalil Mehta tqp = container_of(queue, struct hclgevf_tqp, q); 724e2cb1decSSalil Mehta memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 725e2cb1decSSalil Mehta } 726e2cb1decSSalil Mehta } 727e2cb1decSSalil Mehta 728e2cb1decSSalil Mehta static int hclgevf_cfg_func_mta_filter(struct hnae3_handle *handle, bool en) 729e2cb1decSSalil Mehta { 730e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 731e2cb1decSSalil Mehta u8 msg[2] = {0}; 732e2cb1decSSalil Mehta 733e2cb1decSSalil Mehta msg[0] = en; 734e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 735e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_FUNC_MTA_ENABLE, 736e2cb1decSSalil Mehta msg, 1, false, NULL, 0); 737e2cb1decSSalil Mehta } 738e2cb1decSSalil Mehta 739e2cb1decSSalil Mehta static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 740e2cb1decSSalil Mehta { 741e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 742e2cb1decSSalil Mehta 743e2cb1decSSalil Mehta ether_addr_copy(p, hdev->hw.mac.mac_addr); 744e2cb1decSSalil Mehta } 745e2cb1decSSalil Mehta 74659098055SFuyun Liang static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 74759098055SFuyun Liang bool is_first) 748e2cb1decSSalil Mehta { 749e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 750e2cb1decSSalil Mehta u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 751e2cb1decSSalil Mehta u8 *new_mac_addr = (u8 *)p; 752e2cb1decSSalil Mehta u8 msg_data[ETH_ALEN * 2]; 75359098055SFuyun Liang u16 subcode; 754e2cb1decSSalil Mehta int status; 755e2cb1decSSalil Mehta 756e2cb1decSSalil Mehta ether_addr_copy(msg_data, new_mac_addr); 757e2cb1decSSalil Mehta ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 758e2cb1decSSalil Mehta 75959098055SFuyun Liang subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 76059098055SFuyun Liang HCLGE_MBX_MAC_VLAN_UC_MODIFY; 76159098055SFuyun Liang 762e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 76359098055SFuyun Liang subcode, msg_data, ETH_ALEN * 2, 7642097fdefSJian Shen true, NULL, 0); 765e2cb1decSSalil Mehta if (!status) 766e2cb1decSSalil Mehta ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 767e2cb1decSSalil Mehta 768e2cb1decSSalil Mehta return status; 769e2cb1decSSalil Mehta } 770e2cb1decSSalil Mehta 771e2cb1decSSalil Mehta static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 772e2cb1decSSalil Mehta const unsigned char *addr) 773e2cb1decSSalil Mehta { 774e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 775e2cb1decSSalil Mehta 776e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 777e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_ADD, 778e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 779e2cb1decSSalil Mehta } 780e2cb1decSSalil Mehta 781e2cb1decSSalil Mehta static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 782e2cb1decSSalil Mehta const unsigned char *addr) 783e2cb1decSSalil Mehta { 784e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 785e2cb1decSSalil Mehta 786e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 787e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_REMOVE, 788e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 789e2cb1decSSalil Mehta } 790e2cb1decSSalil Mehta 791e2cb1decSSalil Mehta static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 792e2cb1decSSalil Mehta const unsigned char *addr) 793e2cb1decSSalil Mehta { 794e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 795e2cb1decSSalil Mehta 796e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 797e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_ADD, 798e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 799e2cb1decSSalil Mehta } 800e2cb1decSSalil Mehta 801e2cb1decSSalil Mehta static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 802e2cb1decSSalil Mehta const unsigned char *addr) 803e2cb1decSSalil Mehta { 804e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 805e2cb1decSSalil Mehta 806e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 807e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_REMOVE, 808e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 809e2cb1decSSalil Mehta } 810e2cb1decSSalil Mehta 811e2cb1decSSalil Mehta static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 812e2cb1decSSalil Mehta __be16 proto, u16 vlan_id, 813e2cb1decSSalil Mehta bool is_kill) 814e2cb1decSSalil Mehta { 815e2cb1decSSalil Mehta #define HCLGEVF_VLAN_MBX_MSG_LEN 5 816e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 817e2cb1decSSalil Mehta u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 818e2cb1decSSalil Mehta 819e2cb1decSSalil Mehta if (vlan_id > 4095) 820e2cb1decSSalil Mehta return -EINVAL; 821e2cb1decSSalil Mehta 822e2cb1decSSalil Mehta if (proto != htons(ETH_P_8021Q)) 823e2cb1decSSalil Mehta return -EPROTONOSUPPORT; 824e2cb1decSSalil Mehta 825e2cb1decSSalil Mehta msg_data[0] = is_kill; 826e2cb1decSSalil Mehta memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 827e2cb1decSSalil Mehta memcpy(&msg_data[3], &proto, sizeof(proto)); 828e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 829e2cb1decSSalil Mehta HCLGE_MBX_VLAN_FILTER, msg_data, 830e2cb1decSSalil Mehta HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 831e2cb1decSSalil Mehta } 832e2cb1decSSalil Mehta 833e2cb1decSSalil Mehta static void hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 834e2cb1decSSalil Mehta { 835e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 836e2cb1decSSalil Mehta u8 msg_data[2]; 8371a426f8bSPeng Li int ret; 838e2cb1decSSalil Mehta 839e2cb1decSSalil Mehta memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 840e2cb1decSSalil Mehta 8411a426f8bSPeng Li /* disable vf queue before send queue reset msg to PF */ 8421a426f8bSPeng Li ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 8431a426f8bSPeng Li if (ret) 8441a426f8bSPeng Li return; 8451a426f8bSPeng Li 8461a426f8bSPeng Li hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 8471a426f8bSPeng Li 2, true, NULL, 0); 848e2cb1decSSalil Mehta } 849e2cb1decSSalil Mehta 8506988eb2aSSalil Mehta static int hclgevf_notify_client(struct hclgevf_dev *hdev, 8516988eb2aSSalil Mehta enum hnae3_reset_notify_type type) 8526988eb2aSSalil Mehta { 8536988eb2aSSalil Mehta struct hnae3_client *client = hdev->nic_client; 8546988eb2aSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 8556988eb2aSSalil Mehta 8566988eb2aSSalil Mehta if (!client->ops->reset_notify) 8576988eb2aSSalil Mehta return -EOPNOTSUPP; 8586988eb2aSSalil Mehta 8596988eb2aSSalil Mehta return client->ops->reset_notify(handle, type); 8606988eb2aSSalil Mehta } 8616988eb2aSSalil Mehta 8626988eb2aSSalil Mehta static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 8636988eb2aSSalil Mehta { 8646988eb2aSSalil Mehta #define HCLGEVF_RESET_WAIT_MS 500 8656988eb2aSSalil Mehta #define HCLGEVF_RESET_WAIT_CNT 20 8666988eb2aSSalil Mehta u32 val, cnt = 0; 8676988eb2aSSalil Mehta 8686988eb2aSSalil Mehta /* wait to check the hardware reset completion status */ 8696988eb2aSSalil Mehta val = hclgevf_read_dev(&hdev->hw, HCLGEVF_FUN_RST_ING); 8706988eb2aSSalil Mehta while (hnae_get_bit(val, HCLGEVF_FUN_RST_ING_B) && 8716988eb2aSSalil Mehta (cnt < HCLGEVF_RESET_WAIT_CNT)) { 8726988eb2aSSalil Mehta msleep(HCLGEVF_RESET_WAIT_MS); 8736988eb2aSSalil Mehta val = hclgevf_read_dev(&hdev->hw, HCLGEVF_FUN_RST_ING); 8746988eb2aSSalil Mehta cnt++; 8756988eb2aSSalil Mehta } 8766988eb2aSSalil Mehta 8776988eb2aSSalil Mehta /* hardware completion status should be available by this time */ 8786988eb2aSSalil Mehta if (cnt >= HCLGEVF_RESET_WAIT_CNT) { 8796988eb2aSSalil Mehta dev_warn(&hdev->pdev->dev, 8806988eb2aSSalil Mehta "could'nt get reset done status from h/w, timeout!\n"); 8816988eb2aSSalil Mehta return -EBUSY; 8826988eb2aSSalil Mehta } 8836988eb2aSSalil Mehta 8846988eb2aSSalil Mehta /* we will wait a bit more to let reset of the stack to complete. This 8856988eb2aSSalil Mehta * might happen in case reset assertion was made by PF. Yes, this also 8866988eb2aSSalil Mehta * means we might end up waiting bit more even for VF reset. 8876988eb2aSSalil Mehta */ 8886988eb2aSSalil Mehta msleep(5000); 8896988eb2aSSalil Mehta 8906988eb2aSSalil Mehta return 0; 8916988eb2aSSalil Mehta } 8926988eb2aSSalil Mehta 8936988eb2aSSalil Mehta static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 8946988eb2aSSalil Mehta { 8957a01c897SSalil Mehta int ret; 8967a01c897SSalil Mehta 8976988eb2aSSalil Mehta /* uninitialize the nic client */ 8986988eb2aSSalil Mehta hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 8996988eb2aSSalil Mehta 9007a01c897SSalil Mehta /* re-initialize the hclge device */ 9017a01c897SSalil Mehta ret = hclgevf_init_hdev(hdev); 9027a01c897SSalil Mehta if (ret) { 9037a01c897SSalil Mehta dev_err(&hdev->pdev->dev, 9047a01c897SSalil Mehta "hclge device re-init failed, VF is disabled!\n"); 9057a01c897SSalil Mehta return ret; 9067a01c897SSalil Mehta } 9076988eb2aSSalil Mehta 9086988eb2aSSalil Mehta /* bring up the nic client again */ 9096988eb2aSSalil Mehta hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 9106988eb2aSSalil Mehta 9116988eb2aSSalil Mehta return 0; 9126988eb2aSSalil Mehta } 9136988eb2aSSalil Mehta 9146988eb2aSSalil Mehta static int hclgevf_reset(struct hclgevf_dev *hdev) 9156988eb2aSSalil Mehta { 9166988eb2aSSalil Mehta int ret; 9176988eb2aSSalil Mehta 9186988eb2aSSalil Mehta rtnl_lock(); 9196988eb2aSSalil Mehta 9206988eb2aSSalil Mehta /* bring down the nic to stop any ongoing TX/RX */ 9216988eb2aSSalil Mehta hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 9226988eb2aSSalil Mehta 9236988eb2aSSalil Mehta /* check if VF could successfully fetch the hardware reset completion 9246988eb2aSSalil Mehta * status from the hardware 9256988eb2aSSalil Mehta */ 9266988eb2aSSalil Mehta ret = hclgevf_reset_wait(hdev); 9276988eb2aSSalil Mehta if (ret) { 9286988eb2aSSalil Mehta /* can't do much in this situation, will disable VF */ 9296988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, 9306988eb2aSSalil Mehta "VF failed(=%d) to fetch H/W reset completion status\n", 9316988eb2aSSalil Mehta ret); 9326988eb2aSSalil Mehta 9336988eb2aSSalil Mehta dev_warn(&hdev->pdev->dev, "VF reset failed, disabling VF!\n"); 9346988eb2aSSalil Mehta hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 9356988eb2aSSalil Mehta 9366988eb2aSSalil Mehta rtnl_unlock(); 9376988eb2aSSalil Mehta return ret; 9386988eb2aSSalil Mehta } 9396988eb2aSSalil Mehta 9406988eb2aSSalil Mehta /* now, re-initialize the nic client and ae device*/ 9416988eb2aSSalil Mehta ret = hclgevf_reset_stack(hdev); 9426988eb2aSSalil Mehta if (ret) 9436988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 9446988eb2aSSalil Mehta 9456988eb2aSSalil Mehta /* bring up the nic to enable TX/RX again */ 9466988eb2aSSalil Mehta hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 9476988eb2aSSalil Mehta 9486988eb2aSSalil Mehta rtnl_unlock(); 9496988eb2aSSalil Mehta 9506988eb2aSSalil Mehta return ret; 9516988eb2aSSalil Mehta } 9526988eb2aSSalil Mehta 953a8dedb65SSalil Mehta static int hclgevf_do_reset(struct hclgevf_dev *hdev) 954a8dedb65SSalil Mehta { 955a8dedb65SSalil Mehta int status; 956a8dedb65SSalil Mehta u8 respmsg; 957a8dedb65SSalil Mehta 958a8dedb65SSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 959a8dedb65SSalil Mehta 0, false, &respmsg, sizeof(u8)); 960a8dedb65SSalil Mehta if (status) 961a8dedb65SSalil Mehta dev_err(&hdev->pdev->dev, 962a8dedb65SSalil Mehta "VF reset request to PF failed(=%d)\n", status); 963a8dedb65SSalil Mehta 964a8dedb65SSalil Mehta return status; 965a8dedb65SSalil Mehta } 966a8dedb65SSalil Mehta 9676d4c3981SSalil Mehta static void hclgevf_reset_event(struct hnae3_handle *handle) 9686d4c3981SSalil Mehta { 9696d4c3981SSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 9706d4c3981SSalil Mehta 9716d4c3981SSalil Mehta dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 9726d4c3981SSalil Mehta 9736d4c3981SSalil Mehta handle->reset_level = HNAE3_VF_RESET; 9746d4c3981SSalil Mehta 975436667d2SSalil Mehta /* reset of this VF requested */ 976436667d2SSalil Mehta set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 977436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 9786d4c3981SSalil Mehta 9796d4c3981SSalil Mehta handle->last_reset_time = jiffies; 9806d4c3981SSalil Mehta } 9816d4c3981SSalil Mehta 982e2cb1decSSalil Mehta static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 983e2cb1decSSalil Mehta { 984e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 985e2cb1decSSalil Mehta 986e2cb1decSSalil Mehta return hdev->fw_version; 987e2cb1decSSalil Mehta } 988e2cb1decSSalil Mehta 989e2cb1decSSalil Mehta static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 990e2cb1decSSalil Mehta { 991e2cb1decSSalil Mehta struct hclgevf_misc_vector *vector = &hdev->misc_vector; 992e2cb1decSSalil Mehta 993e2cb1decSSalil Mehta vector->vector_irq = pci_irq_vector(hdev->pdev, 994e2cb1decSSalil Mehta HCLGEVF_MISC_VECTOR_NUM); 995e2cb1decSSalil Mehta vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 996e2cb1decSSalil Mehta /* vector status always valid for Vector 0 */ 997e2cb1decSSalil Mehta hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 998e2cb1decSSalil Mehta hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 999e2cb1decSSalil Mehta 1000e2cb1decSSalil Mehta hdev->num_msi_left -= 1; 1001e2cb1decSSalil Mehta hdev->num_msi_used += 1; 1002e2cb1decSSalil Mehta } 1003e2cb1decSSalil Mehta 100435a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 100535a1e503SSalil Mehta { 100635a1e503SSalil Mehta if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) && 100735a1e503SSalil Mehta !test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) { 100835a1e503SSalil Mehta set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 100935a1e503SSalil Mehta schedule_work(&hdev->rst_service_task); 101035a1e503SSalil Mehta } 101135a1e503SSalil Mehta } 101235a1e503SSalil Mehta 1013e2cb1decSSalil Mehta static void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1014e2cb1decSSalil Mehta { 1015e2cb1decSSalil Mehta if (!test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state)) 1016e2cb1decSSalil Mehta schedule_work(&hdev->mbx_service_task); 1017e2cb1decSSalil Mehta } 1018e2cb1decSSalil Mehta 1019e2cb1decSSalil Mehta static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 1020e2cb1decSSalil Mehta { 1021e2cb1decSSalil Mehta if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 1022e2cb1decSSalil Mehta !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 1023e2cb1decSSalil Mehta schedule_work(&hdev->service_task); 1024e2cb1decSSalil Mehta } 1025e2cb1decSSalil Mehta 1026436667d2SSalil Mehta static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev) 1027436667d2SSalil Mehta { 1028436667d2SSalil Mehta if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state)) 1029436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 1030436667d2SSalil Mehta } 1031436667d2SSalil Mehta 1032e2cb1decSSalil Mehta static void hclgevf_service_timer(struct timer_list *t) 1033e2cb1decSSalil Mehta { 1034e2cb1decSSalil Mehta struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 1035e2cb1decSSalil Mehta 1036e2cb1decSSalil Mehta mod_timer(&hdev->service_timer, jiffies + 5 * HZ); 1037e2cb1decSSalil Mehta 1038e2cb1decSSalil Mehta hclgevf_task_schedule(hdev); 1039e2cb1decSSalil Mehta } 1040e2cb1decSSalil Mehta 104135a1e503SSalil Mehta static void hclgevf_reset_service_task(struct work_struct *work) 104235a1e503SSalil Mehta { 104335a1e503SSalil Mehta struct hclgevf_dev *hdev = 104435a1e503SSalil Mehta container_of(work, struct hclgevf_dev, rst_service_task); 1045a8dedb65SSalil Mehta int ret; 104635a1e503SSalil Mehta 104735a1e503SSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 104835a1e503SSalil Mehta return; 104935a1e503SSalil Mehta 105035a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 105135a1e503SSalil Mehta 1052436667d2SSalil Mehta if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1053436667d2SSalil Mehta &hdev->reset_state)) { 1054436667d2SSalil Mehta /* PF has initmated that it is about to reset the hardware. 1055436667d2SSalil Mehta * We now have to poll & check if harware has actually completed 1056436667d2SSalil Mehta * the reset sequence. On hardware reset completion, VF needs to 1057436667d2SSalil Mehta * reset the client and ae device. 105835a1e503SSalil Mehta */ 1059436667d2SSalil Mehta hdev->reset_attempts = 0; 1060436667d2SSalil Mehta 10616988eb2aSSalil Mehta ret = hclgevf_reset(hdev); 10626988eb2aSSalil Mehta if (ret) 10636988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, "VF stack reset failed.\n"); 1064436667d2SSalil Mehta } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1065436667d2SSalil Mehta &hdev->reset_state)) { 1066436667d2SSalil Mehta /* we could be here when either of below happens: 1067436667d2SSalil Mehta * 1. reset was initiated due to watchdog timeout due to 1068436667d2SSalil Mehta * a. IMP was earlier reset and our TX got choked down and 1069436667d2SSalil Mehta * which resulted in watchdog reacting and inducing VF 1070436667d2SSalil Mehta * reset. This also means our cmdq would be unreliable. 1071436667d2SSalil Mehta * b. problem in TX due to other lower layer(example link 1072436667d2SSalil Mehta * layer not functioning properly etc.) 1073436667d2SSalil Mehta * 2. VF reset might have been initiated due to some config 1074436667d2SSalil Mehta * change. 1075436667d2SSalil Mehta * 1076436667d2SSalil Mehta * NOTE: Theres no clear way to detect above cases than to react 1077436667d2SSalil Mehta * to the response of PF for this reset request. PF will ack the 1078436667d2SSalil Mehta * 1b and 2. cases but we will not get any intimation about 1a 1079436667d2SSalil Mehta * from PF as cmdq would be in unreliable state i.e. mailbox 1080436667d2SSalil Mehta * communication between PF and VF would be broken. 1081436667d2SSalil Mehta */ 1082436667d2SSalil Mehta 1083436667d2SSalil Mehta /* if we are never geting into pending state it means either: 1084436667d2SSalil Mehta * 1. PF is not receiving our request which could be due to IMP 1085436667d2SSalil Mehta * reset 1086436667d2SSalil Mehta * 2. PF is screwed 1087436667d2SSalil Mehta * We cannot do much for 2. but to check first we can try reset 1088436667d2SSalil Mehta * our PCIe + stack and see if it alleviates the problem. 1089436667d2SSalil Mehta */ 1090436667d2SSalil Mehta if (hdev->reset_attempts > 3) { 1091436667d2SSalil Mehta /* prepare for full reset of stack + pcie interface */ 1092436667d2SSalil Mehta hdev->nic.reset_level = HNAE3_VF_FULL_RESET; 1093436667d2SSalil Mehta 1094436667d2SSalil Mehta /* "defer" schedule the reset task again */ 1095436667d2SSalil Mehta set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1096436667d2SSalil Mehta } else { 1097436667d2SSalil Mehta hdev->reset_attempts++; 1098436667d2SSalil Mehta 1099436667d2SSalil Mehta /* request PF for resetting this VF via mailbox */ 1100a8dedb65SSalil Mehta ret = hclgevf_do_reset(hdev); 1101a8dedb65SSalil Mehta if (ret) 1102a8dedb65SSalil Mehta dev_warn(&hdev->pdev->dev, 1103a8dedb65SSalil Mehta "VF rst fail, stack will call\n"); 1104436667d2SSalil Mehta } 1105436667d2SSalil Mehta } 110635a1e503SSalil Mehta 110735a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 110835a1e503SSalil Mehta } 110935a1e503SSalil Mehta 1110e2cb1decSSalil Mehta static void hclgevf_mailbox_service_task(struct work_struct *work) 1111e2cb1decSSalil Mehta { 1112e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1113e2cb1decSSalil Mehta 1114e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 1115e2cb1decSSalil Mehta 1116e2cb1decSSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1117e2cb1decSSalil Mehta return; 1118e2cb1decSSalil Mehta 1119e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1120e2cb1decSSalil Mehta 1121e2cb1decSSalil Mehta hclgevf_mbx_handler(hdev); 1122e2cb1decSSalil Mehta 1123e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1124e2cb1decSSalil Mehta } 1125e2cb1decSSalil Mehta 1126e2cb1decSSalil Mehta static void hclgevf_service_task(struct work_struct *work) 1127e2cb1decSSalil Mehta { 1128e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1129e2cb1decSSalil Mehta 1130e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, service_task); 1131e2cb1decSSalil Mehta 1132e2cb1decSSalil Mehta /* request the link status from the PF. PF would be able to tell VF 1133e2cb1decSSalil Mehta * about such updates in future so we might remove this later 1134e2cb1decSSalil Mehta */ 1135e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1136e2cb1decSSalil Mehta 1137436667d2SSalil Mehta hclgevf_deferred_task_schedule(hdev); 1138436667d2SSalil Mehta 1139e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1140e2cb1decSSalil Mehta } 1141e2cb1decSSalil Mehta 1142e2cb1decSSalil Mehta static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1143e2cb1decSSalil Mehta { 1144e2cb1decSSalil Mehta hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1145e2cb1decSSalil Mehta } 1146e2cb1decSSalil Mehta 1147e2cb1decSSalil Mehta static bool hclgevf_check_event_cause(struct hclgevf_dev *hdev, u32 *clearval) 1148e2cb1decSSalil Mehta { 1149e2cb1decSSalil Mehta u32 cmdq_src_reg; 1150e2cb1decSSalil Mehta 1151e2cb1decSSalil Mehta /* fetch the events from their corresponding regs */ 1152e2cb1decSSalil Mehta cmdq_src_reg = hclgevf_read_dev(&hdev->hw, 1153e2cb1decSSalil Mehta HCLGEVF_VECTOR0_CMDQ_SRC_REG); 1154e2cb1decSSalil Mehta 1155e2cb1decSSalil Mehta /* check for vector0 mailbox(=CMDQ RX) event source */ 1156e2cb1decSSalil Mehta if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 1157e2cb1decSSalil Mehta cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1158e2cb1decSSalil Mehta *clearval = cmdq_src_reg; 1159e2cb1decSSalil Mehta return true; 1160e2cb1decSSalil Mehta } 1161e2cb1decSSalil Mehta 1162e2cb1decSSalil Mehta dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 1163e2cb1decSSalil Mehta 1164e2cb1decSSalil Mehta return false; 1165e2cb1decSSalil Mehta } 1166e2cb1decSSalil Mehta 1167e2cb1decSSalil Mehta static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1168e2cb1decSSalil Mehta { 1169e2cb1decSSalil Mehta writel(en ? 1 : 0, vector->addr); 1170e2cb1decSSalil Mehta } 1171e2cb1decSSalil Mehta 1172e2cb1decSSalil Mehta static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1173e2cb1decSSalil Mehta { 1174e2cb1decSSalil Mehta struct hclgevf_dev *hdev = data; 1175e2cb1decSSalil Mehta u32 clearval; 1176e2cb1decSSalil Mehta 1177e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 1178e2cb1decSSalil Mehta if (!hclgevf_check_event_cause(hdev, &clearval)) 1179e2cb1decSSalil Mehta goto skip_sched; 1180e2cb1decSSalil Mehta 1181e2cb1decSSalil Mehta /* schedule the VF mailbox service task, if not already scheduled */ 1182e2cb1decSSalil Mehta hclgevf_mbx_task_schedule(hdev); 1183e2cb1decSSalil Mehta 1184e2cb1decSSalil Mehta hclgevf_clear_event_cause(hdev, clearval); 1185e2cb1decSSalil Mehta 1186e2cb1decSSalil Mehta skip_sched: 1187e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 1188e2cb1decSSalil Mehta 1189e2cb1decSSalil Mehta return IRQ_HANDLED; 1190e2cb1decSSalil Mehta } 1191e2cb1decSSalil Mehta 1192e2cb1decSSalil Mehta static int hclgevf_configure(struct hclgevf_dev *hdev) 1193e2cb1decSSalil Mehta { 1194e2cb1decSSalil Mehta int ret; 1195e2cb1decSSalil Mehta 1196e2cb1decSSalil Mehta /* get queue configuration from PF */ 1197e2cb1decSSalil Mehta ret = hclge_get_queue_info(hdev); 1198e2cb1decSSalil Mehta if (ret) 1199e2cb1decSSalil Mehta return ret; 1200e2cb1decSSalil Mehta /* get tc configuration from PF */ 1201e2cb1decSSalil Mehta return hclgevf_get_tc_info(hdev); 1202e2cb1decSSalil Mehta } 1203e2cb1decSSalil Mehta 12047a01c897SSalil Mehta static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 12057a01c897SSalil Mehta { 12067a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 12077a01c897SSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 12087a01c897SSalil Mehta 12097a01c897SSalil Mehta hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 12107a01c897SSalil Mehta if (!hdev) 12117a01c897SSalil Mehta return -ENOMEM; 12127a01c897SSalil Mehta 12137a01c897SSalil Mehta hdev->pdev = pdev; 12147a01c897SSalil Mehta hdev->ae_dev = ae_dev; 12157a01c897SSalil Mehta ae_dev->priv = hdev; 12167a01c897SSalil Mehta 12177a01c897SSalil Mehta return 0; 12187a01c897SSalil Mehta } 12197a01c897SSalil Mehta 1220e2cb1decSSalil Mehta static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 1221e2cb1decSSalil Mehta { 1222e2cb1decSSalil Mehta struct hnae3_handle *roce = &hdev->roce; 1223e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 1224e2cb1decSSalil Mehta 1225e2cb1decSSalil Mehta roce->rinfo.num_vectors = HCLGEVF_ROCEE_VECTOR_NUM; 1226e2cb1decSSalil Mehta 1227e2cb1decSSalil Mehta if (hdev->num_msi_left < roce->rinfo.num_vectors || 1228e2cb1decSSalil Mehta hdev->num_msi_left == 0) 1229e2cb1decSSalil Mehta return -EINVAL; 1230e2cb1decSSalil Mehta 1231e2cb1decSSalil Mehta roce->rinfo.base_vector = 1232e2cb1decSSalil Mehta hdev->vector_status[hdev->num_msi_used]; 1233e2cb1decSSalil Mehta 1234e2cb1decSSalil Mehta roce->rinfo.netdev = nic->kinfo.netdev; 1235e2cb1decSSalil Mehta roce->rinfo.roce_io_base = hdev->hw.io_base; 1236e2cb1decSSalil Mehta 1237e2cb1decSSalil Mehta roce->pdev = nic->pdev; 1238e2cb1decSSalil Mehta roce->ae_algo = nic->ae_algo; 1239e2cb1decSSalil Mehta roce->numa_node_mask = nic->numa_node_mask; 1240e2cb1decSSalil Mehta 1241e2cb1decSSalil Mehta return 0; 1242e2cb1decSSalil Mehta } 1243e2cb1decSSalil Mehta 1244e2cb1decSSalil Mehta static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 1245e2cb1decSSalil Mehta { 1246e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1247e2cb1decSSalil Mehta int i, ret; 1248e2cb1decSSalil Mehta 1249e2cb1decSSalil Mehta rss_cfg->rss_size = hdev->rss_size_max; 1250e2cb1decSSalil Mehta 1251e2cb1decSSalil Mehta /* Initialize RSS indirect table for each vport */ 1252e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 1253e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max; 1254e2cb1decSSalil Mehta 1255e2cb1decSSalil Mehta ret = hclgevf_set_rss_indir_table(hdev); 1256e2cb1decSSalil Mehta if (ret) 1257e2cb1decSSalil Mehta return ret; 1258e2cb1decSSalil Mehta 1259e2cb1decSSalil Mehta return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max); 1260e2cb1decSSalil Mehta } 1261e2cb1decSSalil Mehta 1262e2cb1decSSalil Mehta static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 1263e2cb1decSSalil Mehta { 1264e2cb1decSSalil Mehta /* other vlan config(like, VLAN TX/RX offload) would also be added 1265e2cb1decSSalil Mehta * here later 1266e2cb1decSSalil Mehta */ 1267e2cb1decSSalil Mehta return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 1268e2cb1decSSalil Mehta false); 1269e2cb1decSSalil Mehta } 1270e2cb1decSSalil Mehta 1271e2cb1decSSalil Mehta static int hclgevf_ae_start(struct hnae3_handle *handle) 1272e2cb1decSSalil Mehta { 1273e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1274e2cb1decSSalil Mehta int i, queue_id; 1275e2cb1decSSalil Mehta 1276e2cb1decSSalil Mehta for (i = 0; i < handle->kinfo.num_tqps; i++) { 1277e2cb1decSSalil Mehta /* ring enable */ 1278e2cb1decSSalil Mehta queue_id = hclgevf_get_queue_id(handle->kinfo.tqp[i]); 1279e2cb1decSSalil Mehta if (queue_id < 0) { 1280e2cb1decSSalil Mehta dev_warn(&hdev->pdev->dev, 1281e2cb1decSSalil Mehta "Get invalid queue id, ignore it\n"); 1282e2cb1decSSalil Mehta continue; 1283e2cb1decSSalil Mehta } 1284e2cb1decSSalil Mehta 1285e2cb1decSSalil Mehta hclgevf_tqp_enable(hdev, queue_id, 0, true); 1286e2cb1decSSalil Mehta } 1287e2cb1decSSalil Mehta 1288e2cb1decSSalil Mehta /* reset tqp stats */ 1289e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 1290e2cb1decSSalil Mehta 1291e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1292e2cb1decSSalil Mehta 1293e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1294e2cb1decSSalil Mehta mod_timer(&hdev->service_timer, jiffies + HZ); 1295e2cb1decSSalil Mehta 1296e2cb1decSSalil Mehta return 0; 1297e2cb1decSSalil Mehta } 1298e2cb1decSSalil Mehta 1299e2cb1decSSalil Mehta static void hclgevf_ae_stop(struct hnae3_handle *handle) 1300e2cb1decSSalil Mehta { 1301e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1302e2cb1decSSalil Mehta int i, queue_id; 1303e2cb1decSSalil Mehta 1304e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 1305e2cb1decSSalil Mehta /* Ring disable */ 1306e2cb1decSSalil Mehta queue_id = hclgevf_get_queue_id(handle->kinfo.tqp[i]); 1307e2cb1decSSalil Mehta if (queue_id < 0) { 1308e2cb1decSSalil Mehta dev_warn(&hdev->pdev->dev, 1309e2cb1decSSalil Mehta "Get invalid queue id, ignore it\n"); 1310e2cb1decSSalil Mehta continue; 1311e2cb1decSSalil Mehta } 1312e2cb1decSSalil Mehta 1313e2cb1decSSalil Mehta hclgevf_tqp_enable(hdev, queue_id, 0, false); 1314e2cb1decSSalil Mehta } 1315e2cb1decSSalil Mehta 1316e2cb1decSSalil Mehta /* reset tqp stats */ 1317e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 13188cc6c1f7SFuyun Liang del_timer_sync(&hdev->service_timer); 13198cc6c1f7SFuyun Liang cancel_work_sync(&hdev->service_task); 13208cc6c1f7SFuyun Liang hclgevf_update_link_status(hdev, 0); 1321e2cb1decSSalil Mehta } 1322e2cb1decSSalil Mehta 1323e2cb1decSSalil Mehta static void hclgevf_state_init(struct hclgevf_dev *hdev) 1324e2cb1decSSalil Mehta { 13257a01c897SSalil Mehta /* if this is on going reset then skip this initialization */ 13267a01c897SSalil Mehta if (hclgevf_dev_ongoing_reset(hdev)) 13277a01c897SSalil Mehta return; 13287a01c897SSalil Mehta 1329e2cb1decSSalil Mehta /* setup tasks for the MBX */ 1330e2cb1decSSalil Mehta INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 1331e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1332e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1333e2cb1decSSalil Mehta 1334e2cb1decSSalil Mehta /* setup tasks for service timer */ 1335e2cb1decSSalil Mehta timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 1336e2cb1decSSalil Mehta 1337e2cb1decSSalil Mehta INIT_WORK(&hdev->service_task, hclgevf_service_task); 1338e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1339e2cb1decSSalil Mehta 134035a1e503SSalil Mehta INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task); 134135a1e503SSalil Mehta 1342e2cb1decSSalil Mehta mutex_init(&hdev->mbx_resp.mbx_mutex); 1343e2cb1decSSalil Mehta 1344e2cb1decSSalil Mehta /* bring the device down */ 1345e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1346e2cb1decSSalil Mehta } 1347e2cb1decSSalil Mehta 1348e2cb1decSSalil Mehta static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 1349e2cb1decSSalil Mehta { 1350e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1351e2cb1decSSalil Mehta 1352e2cb1decSSalil Mehta if (hdev->service_timer.function) 1353e2cb1decSSalil Mehta del_timer_sync(&hdev->service_timer); 1354e2cb1decSSalil Mehta if (hdev->service_task.func) 1355e2cb1decSSalil Mehta cancel_work_sync(&hdev->service_task); 1356e2cb1decSSalil Mehta if (hdev->mbx_service_task.func) 1357e2cb1decSSalil Mehta cancel_work_sync(&hdev->mbx_service_task); 135835a1e503SSalil Mehta if (hdev->rst_service_task.func) 135935a1e503SSalil Mehta cancel_work_sync(&hdev->rst_service_task); 1360e2cb1decSSalil Mehta 1361e2cb1decSSalil Mehta mutex_destroy(&hdev->mbx_resp.mbx_mutex); 1362e2cb1decSSalil Mehta } 1363e2cb1decSSalil Mehta 1364e2cb1decSSalil Mehta static int hclgevf_init_msi(struct hclgevf_dev *hdev) 1365e2cb1decSSalil Mehta { 1366e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 1367e2cb1decSSalil Mehta int vectors; 1368e2cb1decSSalil Mehta int i; 1369e2cb1decSSalil Mehta 13707a01c897SSalil Mehta /* if this is on going reset then skip this initialization */ 13717a01c897SSalil Mehta if (hclgevf_dev_ongoing_reset(hdev)) 13727a01c897SSalil Mehta return 0; 13737a01c897SSalil Mehta 1374e2cb1decSSalil Mehta hdev->num_msi = HCLGEVF_MAX_VF_VECTOR_NUM; 1375e2cb1decSSalil Mehta 1376e2cb1decSSalil Mehta vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 1377e2cb1decSSalil Mehta PCI_IRQ_MSI | PCI_IRQ_MSIX); 1378e2cb1decSSalil Mehta if (vectors < 0) { 1379e2cb1decSSalil Mehta dev_err(&pdev->dev, 1380e2cb1decSSalil Mehta "failed(%d) to allocate MSI/MSI-X vectors\n", 1381e2cb1decSSalil Mehta vectors); 1382e2cb1decSSalil Mehta return vectors; 1383e2cb1decSSalil Mehta } 1384e2cb1decSSalil Mehta if (vectors < hdev->num_msi) 1385e2cb1decSSalil Mehta dev_warn(&hdev->pdev->dev, 1386e2cb1decSSalil Mehta "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 1387e2cb1decSSalil Mehta hdev->num_msi, vectors); 1388e2cb1decSSalil Mehta 1389e2cb1decSSalil Mehta hdev->num_msi = vectors; 1390e2cb1decSSalil Mehta hdev->num_msi_left = vectors; 1391e2cb1decSSalil Mehta hdev->base_msi_vector = pdev->irq; 1392e2cb1decSSalil Mehta 1393e2cb1decSSalil Mehta hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 1394e2cb1decSSalil Mehta sizeof(u16), GFP_KERNEL); 1395e2cb1decSSalil Mehta if (!hdev->vector_status) { 1396e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 1397e2cb1decSSalil Mehta return -ENOMEM; 1398e2cb1decSSalil Mehta } 1399e2cb1decSSalil Mehta 1400e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 1401e2cb1decSSalil Mehta hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 1402e2cb1decSSalil Mehta 1403e2cb1decSSalil Mehta hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 1404e2cb1decSSalil Mehta sizeof(int), GFP_KERNEL); 1405e2cb1decSSalil Mehta if (!hdev->vector_irq) { 1406e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 1407e2cb1decSSalil Mehta return -ENOMEM; 1408e2cb1decSSalil Mehta } 1409e2cb1decSSalil Mehta 1410e2cb1decSSalil Mehta return 0; 1411e2cb1decSSalil Mehta } 1412e2cb1decSSalil Mehta 1413e2cb1decSSalil Mehta static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 1414e2cb1decSSalil Mehta { 1415e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 1416e2cb1decSSalil Mehta 1417e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 1418e2cb1decSSalil Mehta } 1419e2cb1decSSalil Mehta 1420e2cb1decSSalil Mehta static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 1421e2cb1decSSalil Mehta { 1422e2cb1decSSalil Mehta int ret = 0; 1423e2cb1decSSalil Mehta 14247a01c897SSalil Mehta /* if this is on going reset then skip this initialization */ 14257a01c897SSalil Mehta if (hclgevf_dev_ongoing_reset(hdev)) 14267a01c897SSalil Mehta return 0; 14277a01c897SSalil Mehta 1428e2cb1decSSalil Mehta hclgevf_get_misc_vector(hdev); 1429e2cb1decSSalil Mehta 1430e2cb1decSSalil Mehta ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 1431e2cb1decSSalil Mehta 0, "hclgevf_cmd", hdev); 1432e2cb1decSSalil Mehta if (ret) { 1433e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 1434e2cb1decSSalil Mehta hdev->misc_vector.vector_irq); 1435e2cb1decSSalil Mehta return ret; 1436e2cb1decSSalil Mehta } 1437e2cb1decSSalil Mehta 1438e2cb1decSSalil Mehta /* enable misc. vector(vector 0) */ 1439e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 1440e2cb1decSSalil Mehta 1441e2cb1decSSalil Mehta return ret; 1442e2cb1decSSalil Mehta } 1443e2cb1decSSalil Mehta 1444e2cb1decSSalil Mehta static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 1445e2cb1decSSalil Mehta { 1446e2cb1decSSalil Mehta /* disable misc vector(vector 0) */ 1447e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 1448e2cb1decSSalil Mehta free_irq(hdev->misc_vector.vector_irq, hdev); 1449e2cb1decSSalil Mehta hclgevf_free_vector(hdev, 0); 1450e2cb1decSSalil Mehta } 1451e2cb1decSSalil Mehta 1452e2cb1decSSalil Mehta static int hclgevf_init_instance(struct hclgevf_dev *hdev, 1453e2cb1decSSalil Mehta struct hnae3_client *client) 1454e2cb1decSSalil Mehta { 1455e2cb1decSSalil Mehta int ret; 1456e2cb1decSSalil Mehta 1457e2cb1decSSalil Mehta switch (client->type) { 1458e2cb1decSSalil Mehta case HNAE3_CLIENT_KNIC: 1459e2cb1decSSalil Mehta hdev->nic_client = client; 1460e2cb1decSSalil Mehta hdev->nic.client = client; 1461e2cb1decSSalil Mehta 1462e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->nic); 1463e2cb1decSSalil Mehta if (ret) 1464e2cb1decSSalil Mehta return ret; 1465e2cb1decSSalil Mehta 1466e2cb1decSSalil Mehta if (hdev->roce_client && hnae3_dev_roce_supported(hdev)) { 1467e2cb1decSSalil Mehta struct hnae3_client *rc = hdev->roce_client; 1468e2cb1decSSalil Mehta 1469e2cb1decSSalil Mehta ret = hclgevf_init_roce_base_info(hdev); 1470e2cb1decSSalil Mehta if (ret) 1471e2cb1decSSalil Mehta return ret; 1472e2cb1decSSalil Mehta ret = rc->ops->init_instance(&hdev->roce); 1473e2cb1decSSalil Mehta if (ret) 1474e2cb1decSSalil Mehta return ret; 1475e2cb1decSSalil Mehta } 1476e2cb1decSSalil Mehta break; 1477e2cb1decSSalil Mehta case HNAE3_CLIENT_UNIC: 1478e2cb1decSSalil Mehta hdev->nic_client = client; 1479e2cb1decSSalil Mehta hdev->nic.client = client; 1480e2cb1decSSalil Mehta 1481e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->nic); 1482e2cb1decSSalil Mehta if (ret) 1483e2cb1decSSalil Mehta return ret; 1484e2cb1decSSalil Mehta break; 1485e2cb1decSSalil Mehta case HNAE3_CLIENT_ROCE: 1486e2cb1decSSalil Mehta hdev->roce_client = client; 1487e2cb1decSSalil Mehta hdev->roce.client = client; 1488e2cb1decSSalil Mehta 1489e2cb1decSSalil Mehta if (hdev->roce_client && hnae3_dev_roce_supported(hdev)) { 1490e2cb1decSSalil Mehta ret = hclgevf_init_roce_base_info(hdev); 1491e2cb1decSSalil Mehta if (ret) 1492e2cb1decSSalil Mehta return ret; 1493e2cb1decSSalil Mehta 1494e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->roce); 1495e2cb1decSSalil Mehta if (ret) 1496e2cb1decSSalil Mehta return ret; 1497e2cb1decSSalil Mehta } 1498e2cb1decSSalil Mehta } 1499e2cb1decSSalil Mehta 1500e2cb1decSSalil Mehta return 0; 1501e2cb1decSSalil Mehta } 1502e2cb1decSSalil Mehta 1503e2cb1decSSalil Mehta static void hclgevf_uninit_instance(struct hclgevf_dev *hdev, 1504e2cb1decSSalil Mehta struct hnae3_client *client) 1505e2cb1decSSalil Mehta { 1506e2cb1decSSalil Mehta /* un-init roce, if it exists */ 1507e2cb1decSSalil Mehta if (hdev->roce_client) 1508e2cb1decSSalil Mehta hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 1509e2cb1decSSalil Mehta 1510e2cb1decSSalil Mehta /* un-init nic/unic, if this was not called by roce client */ 1511e2cb1decSSalil Mehta if ((client->ops->uninit_instance) && 1512e2cb1decSSalil Mehta (client->type != HNAE3_CLIENT_ROCE)) 1513e2cb1decSSalil Mehta client->ops->uninit_instance(&hdev->nic, 0); 1514e2cb1decSSalil Mehta } 1515e2cb1decSSalil Mehta 1516e2cb1decSSalil Mehta static int hclgevf_register_client(struct hnae3_client *client, 1517e2cb1decSSalil Mehta struct hnae3_ae_dev *ae_dev) 1518e2cb1decSSalil Mehta { 1519e2cb1decSSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 1520e2cb1decSSalil Mehta 1521e2cb1decSSalil Mehta return hclgevf_init_instance(hdev, client); 1522e2cb1decSSalil Mehta } 1523e2cb1decSSalil Mehta 1524e2cb1decSSalil Mehta static void hclgevf_unregister_client(struct hnae3_client *client, 1525e2cb1decSSalil Mehta struct hnae3_ae_dev *ae_dev) 1526e2cb1decSSalil Mehta { 1527e2cb1decSSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 1528e2cb1decSSalil Mehta 1529e2cb1decSSalil Mehta hclgevf_uninit_instance(hdev, client); 1530e2cb1decSSalil Mehta } 1531e2cb1decSSalil Mehta 1532e2cb1decSSalil Mehta static int hclgevf_pci_init(struct hclgevf_dev *hdev) 1533e2cb1decSSalil Mehta { 1534e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 1535e2cb1decSSalil Mehta struct hclgevf_hw *hw; 1536e2cb1decSSalil Mehta int ret; 1537e2cb1decSSalil Mehta 15387a01c897SSalil Mehta /* check if we need to skip initialization of pci. This will happen if 15397a01c897SSalil Mehta * device is undergoing VF reset. Otherwise, we would need to 15407a01c897SSalil Mehta * re-initialize pci interface again i.e. when device is not going 15417a01c897SSalil Mehta * through *any* reset or actually undergoing full reset. 15427a01c897SSalil Mehta */ 15437a01c897SSalil Mehta if (hclgevf_dev_ongoing_reset(hdev)) 15447a01c897SSalil Mehta return 0; 15457a01c897SSalil Mehta 1546e2cb1decSSalil Mehta ret = pci_enable_device(pdev); 1547e2cb1decSSalil Mehta if (ret) { 1548e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed to enable PCI device\n"); 1549e2cb1decSSalil Mehta goto err_no_drvdata; 1550e2cb1decSSalil Mehta } 1551e2cb1decSSalil Mehta 1552e2cb1decSSalil Mehta ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 1553e2cb1decSSalil Mehta if (ret) { 1554e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 1555e2cb1decSSalil Mehta goto err_disable_device; 1556e2cb1decSSalil Mehta } 1557e2cb1decSSalil Mehta 1558e2cb1decSSalil Mehta ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 1559e2cb1decSSalil Mehta if (ret) { 1560e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 1561e2cb1decSSalil Mehta goto err_disable_device; 1562e2cb1decSSalil Mehta } 1563e2cb1decSSalil Mehta 1564e2cb1decSSalil Mehta pci_set_master(pdev); 1565e2cb1decSSalil Mehta hw = &hdev->hw; 1566e2cb1decSSalil Mehta hw->hdev = hdev; 15672e1ea493SPeng Li hw->io_base = pci_iomap(pdev, 2, 0); 1568e2cb1decSSalil Mehta if (!hw->io_base) { 1569e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't map configuration register space\n"); 1570e2cb1decSSalil Mehta ret = -ENOMEM; 1571e2cb1decSSalil Mehta goto err_clr_master; 1572e2cb1decSSalil Mehta } 1573e2cb1decSSalil Mehta 1574e2cb1decSSalil Mehta return 0; 1575e2cb1decSSalil Mehta 1576e2cb1decSSalil Mehta err_clr_master: 1577e2cb1decSSalil Mehta pci_clear_master(pdev); 1578e2cb1decSSalil Mehta pci_release_regions(pdev); 1579e2cb1decSSalil Mehta err_disable_device: 1580e2cb1decSSalil Mehta pci_disable_device(pdev); 1581e2cb1decSSalil Mehta err_no_drvdata: 1582e2cb1decSSalil Mehta pci_set_drvdata(pdev, NULL); 1583e2cb1decSSalil Mehta return ret; 1584e2cb1decSSalil Mehta } 1585e2cb1decSSalil Mehta 1586e2cb1decSSalil Mehta static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 1587e2cb1decSSalil Mehta { 1588e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 1589e2cb1decSSalil Mehta 1590e2cb1decSSalil Mehta pci_iounmap(pdev, hdev->hw.io_base); 1591e2cb1decSSalil Mehta pci_clear_master(pdev); 1592e2cb1decSSalil Mehta pci_release_regions(pdev); 1593e2cb1decSSalil Mehta pci_disable_device(pdev); 1594e2cb1decSSalil Mehta pci_set_drvdata(pdev, NULL); 1595e2cb1decSSalil Mehta } 1596e2cb1decSSalil Mehta 15977a01c897SSalil Mehta static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 1598e2cb1decSSalil Mehta { 15997a01c897SSalil Mehta struct pci_dev *pdev = hdev->pdev; 1600e2cb1decSSalil Mehta int ret; 1601e2cb1decSSalil Mehta 16027a01c897SSalil Mehta /* check if device is on-going full reset(i.e. pcie as well) */ 16037a01c897SSalil Mehta if (hclgevf_dev_ongoing_full_reset(hdev)) { 16047a01c897SSalil Mehta dev_warn(&pdev->dev, "device is going full reset\n"); 16057a01c897SSalil Mehta hclgevf_uninit_hdev(hdev); 16067a01c897SSalil Mehta } 1607e2cb1decSSalil Mehta 1608e2cb1decSSalil Mehta ret = hclgevf_pci_init(hdev); 1609e2cb1decSSalil Mehta if (ret) { 1610e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI initialization failed\n"); 1611e2cb1decSSalil Mehta return ret; 1612e2cb1decSSalil Mehta } 1613e2cb1decSSalil Mehta 1614e2cb1decSSalil Mehta ret = hclgevf_init_msi(hdev); 1615e2cb1decSSalil Mehta if (ret) { 1616e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 1617e2cb1decSSalil Mehta goto err_irq_init; 1618e2cb1decSSalil Mehta } 1619e2cb1decSSalil Mehta 1620e2cb1decSSalil Mehta hclgevf_state_init(hdev); 1621e2cb1decSSalil Mehta 1622e2cb1decSSalil Mehta ret = hclgevf_misc_irq_init(hdev); 1623e2cb1decSSalil Mehta if (ret) { 1624e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 1625e2cb1decSSalil Mehta ret); 1626e2cb1decSSalil Mehta goto err_misc_irq_init; 1627e2cb1decSSalil Mehta } 1628e2cb1decSSalil Mehta 1629e2cb1decSSalil Mehta ret = hclgevf_cmd_init(hdev); 1630e2cb1decSSalil Mehta if (ret) 1631e2cb1decSSalil Mehta goto err_cmd_init; 1632e2cb1decSSalil Mehta 1633e2cb1decSSalil Mehta ret = hclgevf_configure(hdev); 1634e2cb1decSSalil Mehta if (ret) { 1635e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 1636e2cb1decSSalil Mehta goto err_config; 1637e2cb1decSSalil Mehta } 1638e2cb1decSSalil Mehta 1639e2cb1decSSalil Mehta ret = hclgevf_alloc_tqps(hdev); 1640e2cb1decSSalil Mehta if (ret) { 1641e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 1642e2cb1decSSalil Mehta goto err_config; 1643e2cb1decSSalil Mehta } 1644e2cb1decSSalil Mehta 1645e2cb1decSSalil Mehta ret = hclgevf_set_handle_info(hdev); 1646e2cb1decSSalil Mehta if (ret) { 1647e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 1648e2cb1decSSalil Mehta goto err_config; 1649e2cb1decSSalil Mehta } 1650e2cb1decSSalil Mehta 1651e2cb1decSSalil Mehta /* Initialize VF's MTA */ 1652e2cb1decSSalil Mehta hdev->accept_mta_mc = true; 1653e2cb1decSSalil Mehta ret = hclgevf_cfg_func_mta_filter(&hdev->nic, hdev->accept_mta_mc); 1654e2cb1decSSalil Mehta if (ret) { 1655e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1656e2cb1decSSalil Mehta "failed(%d) to set mta filter mode\n", ret); 1657e2cb1decSSalil Mehta goto err_config; 1658e2cb1decSSalil Mehta } 1659e2cb1decSSalil Mehta 1660e2cb1decSSalil Mehta /* Initialize RSS for this VF */ 1661e2cb1decSSalil Mehta ret = hclgevf_rss_init_hw(hdev); 1662e2cb1decSSalil Mehta if (ret) { 1663e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1664e2cb1decSSalil Mehta "failed(%d) to initialize RSS\n", ret); 1665e2cb1decSSalil Mehta goto err_config; 1666e2cb1decSSalil Mehta } 1667e2cb1decSSalil Mehta 1668e2cb1decSSalil Mehta ret = hclgevf_init_vlan_config(hdev); 1669e2cb1decSSalil Mehta if (ret) { 1670e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1671e2cb1decSSalil Mehta "failed(%d) to initialize VLAN config\n", ret); 1672e2cb1decSSalil Mehta goto err_config; 1673e2cb1decSSalil Mehta } 1674e2cb1decSSalil Mehta 1675e2cb1decSSalil Mehta pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME); 1676e2cb1decSSalil Mehta 1677e2cb1decSSalil Mehta return 0; 1678e2cb1decSSalil Mehta 1679e2cb1decSSalil Mehta err_config: 1680e2cb1decSSalil Mehta hclgevf_cmd_uninit(hdev); 1681e2cb1decSSalil Mehta err_cmd_init: 1682e2cb1decSSalil Mehta hclgevf_misc_irq_uninit(hdev); 1683e2cb1decSSalil Mehta err_misc_irq_init: 1684e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 1685e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 1686e2cb1decSSalil Mehta err_irq_init: 1687e2cb1decSSalil Mehta hclgevf_pci_uninit(hdev); 1688e2cb1decSSalil Mehta return ret; 1689e2cb1decSSalil Mehta } 1690e2cb1decSSalil Mehta 16917a01c897SSalil Mehta static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 1692e2cb1decSSalil Mehta { 1693e2cb1decSSalil Mehta hclgevf_cmd_uninit(hdev); 1694e2cb1decSSalil Mehta hclgevf_misc_irq_uninit(hdev); 1695e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 1696e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 1697e2cb1decSSalil Mehta hclgevf_pci_uninit(hdev); 16987a01c897SSalil Mehta } 16997a01c897SSalil Mehta 17007a01c897SSalil Mehta static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 17017a01c897SSalil Mehta { 17027a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 17037a01c897SSalil Mehta int ret; 17047a01c897SSalil Mehta 17057a01c897SSalil Mehta ret = hclgevf_alloc_hdev(ae_dev); 17067a01c897SSalil Mehta if (ret) { 17077a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device allocation failed\n"); 17087a01c897SSalil Mehta return ret; 17097a01c897SSalil Mehta } 17107a01c897SSalil Mehta 17117a01c897SSalil Mehta ret = hclgevf_init_hdev(ae_dev->priv); 17127a01c897SSalil Mehta if (ret) 17137a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device initialization failed\n"); 17147a01c897SSalil Mehta 17157a01c897SSalil Mehta return ret; 17167a01c897SSalil Mehta } 17177a01c897SSalil Mehta 17187a01c897SSalil Mehta static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 17197a01c897SSalil Mehta { 17207a01c897SSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 17217a01c897SSalil Mehta 17227a01c897SSalil Mehta hclgevf_uninit_hdev(hdev); 1723e2cb1decSSalil Mehta ae_dev->priv = NULL; 1724e2cb1decSSalil Mehta } 1725e2cb1decSSalil Mehta 1726849e4607SPeng Li static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 1727849e4607SPeng Li { 1728849e4607SPeng Li struct hnae3_handle *nic = &hdev->nic; 1729849e4607SPeng Li struct hnae3_knic_private_info *kinfo = &nic->kinfo; 1730849e4607SPeng Li 1731849e4607SPeng Li return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps); 1732849e4607SPeng Li } 1733849e4607SPeng Li 1734849e4607SPeng Li /** 1735849e4607SPeng Li * hclgevf_get_channels - Get the current channels enabled and max supported. 1736849e4607SPeng Li * @handle: hardware information for network interface 1737849e4607SPeng Li * @ch: ethtool channels structure 1738849e4607SPeng Li * 1739849e4607SPeng Li * We don't support separate tx and rx queues as channels. The other count 1740849e4607SPeng Li * represents how many queues are being used for control. max_combined counts 1741849e4607SPeng Li * how many queue pairs we can support. They may not be mapped 1 to 1 with 1742849e4607SPeng Li * q_vectors since we support a lot more queue pairs than q_vectors. 1743849e4607SPeng Li **/ 1744849e4607SPeng Li static void hclgevf_get_channels(struct hnae3_handle *handle, 1745849e4607SPeng Li struct ethtool_channels *ch) 1746849e4607SPeng Li { 1747849e4607SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1748849e4607SPeng Li 1749849e4607SPeng Li ch->max_combined = hclgevf_get_max_channels(hdev); 1750849e4607SPeng Li ch->other_count = 0; 1751849e4607SPeng Li ch->max_other = 0; 1752849e4607SPeng Li ch->combined_count = hdev->num_tqps; 1753849e4607SPeng Li } 1754849e4607SPeng Li 1755cc719218SPeng Li static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 1756cc719218SPeng Li u16 *free_tqps, u16 *max_rss_size) 1757cc719218SPeng Li { 1758cc719218SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1759cc719218SPeng Li 1760cc719218SPeng Li *free_tqps = 0; 1761cc719218SPeng Li *max_rss_size = hdev->rss_size_max; 1762cc719218SPeng Li } 1763cc719218SPeng Li 1764175ec96bSFuyun Liang static int hclgevf_get_status(struct hnae3_handle *handle) 1765175ec96bSFuyun Liang { 1766175ec96bSFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1767175ec96bSFuyun Liang 1768175ec96bSFuyun Liang return hdev->hw.mac.link; 1769175ec96bSFuyun Liang } 1770175ec96bSFuyun Liang 17714a152de9SFuyun Liang static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 17724a152de9SFuyun Liang u8 *auto_neg, u32 *speed, 17734a152de9SFuyun Liang u8 *duplex) 17744a152de9SFuyun Liang { 17754a152de9SFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 17764a152de9SFuyun Liang 17774a152de9SFuyun Liang if (speed) 17784a152de9SFuyun Liang *speed = hdev->hw.mac.speed; 17794a152de9SFuyun Liang if (duplex) 17804a152de9SFuyun Liang *duplex = hdev->hw.mac.duplex; 17814a152de9SFuyun Liang if (auto_neg) 17824a152de9SFuyun Liang *auto_neg = AUTONEG_DISABLE; 17834a152de9SFuyun Liang } 17844a152de9SFuyun Liang 17854a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 17864a152de9SFuyun Liang u8 duplex) 17874a152de9SFuyun Liang { 17884a152de9SFuyun Liang hdev->hw.mac.speed = speed; 17894a152de9SFuyun Liang hdev->hw.mac.duplex = duplex; 17904a152de9SFuyun Liang } 17914a152de9SFuyun Liang 1792e2cb1decSSalil Mehta static const struct hnae3_ae_ops hclgevf_ops = { 1793e2cb1decSSalil Mehta .init_ae_dev = hclgevf_init_ae_dev, 1794e2cb1decSSalil Mehta .uninit_ae_dev = hclgevf_uninit_ae_dev, 1795e2cb1decSSalil Mehta .init_client_instance = hclgevf_register_client, 1796e2cb1decSSalil Mehta .uninit_client_instance = hclgevf_unregister_client, 1797e2cb1decSSalil Mehta .start = hclgevf_ae_start, 1798e2cb1decSSalil Mehta .stop = hclgevf_ae_stop, 1799e2cb1decSSalil Mehta .map_ring_to_vector = hclgevf_map_ring_to_vector, 1800e2cb1decSSalil Mehta .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 1801e2cb1decSSalil Mehta .get_vector = hclgevf_get_vector, 18020d3e6631SYunsheng Lin .put_vector = hclgevf_put_vector, 1803e2cb1decSSalil Mehta .reset_queue = hclgevf_reset_tqp, 1804e2cb1decSSalil Mehta .set_promisc_mode = hclgevf_set_promisc_mode, 1805e2cb1decSSalil Mehta .get_mac_addr = hclgevf_get_mac_addr, 1806e2cb1decSSalil Mehta .set_mac_addr = hclgevf_set_mac_addr, 1807e2cb1decSSalil Mehta .add_uc_addr = hclgevf_add_uc_addr, 1808e2cb1decSSalil Mehta .rm_uc_addr = hclgevf_rm_uc_addr, 1809e2cb1decSSalil Mehta .add_mc_addr = hclgevf_add_mc_addr, 1810e2cb1decSSalil Mehta .rm_mc_addr = hclgevf_rm_mc_addr, 1811e2cb1decSSalil Mehta .get_stats = hclgevf_get_stats, 1812e2cb1decSSalil Mehta .update_stats = hclgevf_update_stats, 1813e2cb1decSSalil Mehta .get_strings = hclgevf_get_strings, 1814e2cb1decSSalil Mehta .get_sset_count = hclgevf_get_sset_count, 1815e2cb1decSSalil Mehta .get_rss_key_size = hclgevf_get_rss_key_size, 1816e2cb1decSSalil Mehta .get_rss_indir_size = hclgevf_get_rss_indir_size, 1817e2cb1decSSalil Mehta .get_rss = hclgevf_get_rss, 1818e2cb1decSSalil Mehta .set_rss = hclgevf_set_rss, 1819e2cb1decSSalil Mehta .get_tc_size = hclgevf_get_tc_size, 1820e2cb1decSSalil Mehta .get_fw_version = hclgevf_get_fw_version, 1821e2cb1decSSalil Mehta .set_vlan_filter = hclgevf_set_vlan_filter, 18226d4c3981SSalil Mehta .reset_event = hclgevf_reset_event, 1823849e4607SPeng Li .get_channels = hclgevf_get_channels, 1824cc719218SPeng Li .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 1825175ec96bSFuyun Liang .get_status = hclgevf_get_status, 18264a152de9SFuyun Liang .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 1827e2cb1decSSalil Mehta }; 1828e2cb1decSSalil Mehta 1829e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf = { 1830e2cb1decSSalil Mehta .ops = &hclgevf_ops, 1831e2cb1decSSalil Mehta .name = HCLGEVF_NAME, 1832e2cb1decSSalil Mehta .pdev_id_table = ae_algovf_pci_tbl, 1833e2cb1decSSalil Mehta }; 1834e2cb1decSSalil Mehta 1835e2cb1decSSalil Mehta static int hclgevf_init(void) 1836e2cb1decSSalil Mehta { 1837e2cb1decSSalil Mehta pr_info("%s is initializing\n", HCLGEVF_NAME); 1838e2cb1decSSalil Mehta 1839e2cb1decSSalil Mehta return hnae3_register_ae_algo(&ae_algovf); 1840e2cb1decSSalil Mehta } 1841e2cb1decSSalil Mehta 1842e2cb1decSSalil Mehta static void hclgevf_exit(void) 1843e2cb1decSSalil Mehta { 1844e2cb1decSSalil Mehta hnae3_unregister_ae_algo(&ae_algovf); 1845e2cb1decSSalil Mehta } 1846e2cb1decSSalil Mehta module_init(hclgevf_init); 1847e2cb1decSSalil Mehta module_exit(hclgevf_exit); 1848e2cb1decSSalil Mehta 1849e2cb1decSSalil Mehta MODULE_LICENSE("GPL"); 1850e2cb1decSSalil Mehta MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 1851e2cb1decSSalil Mehta MODULE_DESCRIPTION("HCLGEVF Driver"); 1852e2cb1decSSalil Mehta MODULE_VERSION(HCLGEVF_MOD_VERSION); 1853