1e2cb1decSSalil Mehta // SPDX-License-Identifier: GPL-2.0+ 2e2cb1decSSalil Mehta // Copyright (c) 2016-2017 Hisilicon Limited. 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #include <linux/etherdevice.h> 5aa5c4f17SHuazhong Tan #include <linux/iopoll.h> 66988eb2aSSalil Mehta #include <net/rtnetlink.h> 7e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 8e2cb1decSSalil Mehta #include "hclgevf_main.h" 9e2cb1decSSalil Mehta #include "hclge_mbx.h" 10e2cb1decSSalil Mehta #include "hnae3.h" 11e2cb1decSSalil Mehta 12e2cb1decSSalil Mehta #define HCLGEVF_NAME "hclgevf" 13e2cb1decSSalil Mehta 14bbe6540eSHuazhong Tan #define HCLGEVF_RESET_MAX_FAIL_CNT 5 15bbe6540eSHuazhong Tan 169c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 17e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf; 18e2cb1decSSalil Mehta 19e2cb1decSSalil Mehta static const struct pci_device_id ae_algovf_pci_tbl[] = { 20e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 21e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 22e2cb1decSSalil Mehta /* required last entry */ 23e2cb1decSSalil Mehta {0, } 24e2cb1decSSalil Mehta }; 25e2cb1decSSalil Mehta 26472d7eceSJian Shen static const u8 hclgevf_hash_key[] = { 27472d7eceSJian Shen 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 28472d7eceSJian Shen 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 29472d7eceSJian Shen 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 30472d7eceSJian Shen 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 31472d7eceSJian Shen 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 32472d7eceSJian Shen }; 33472d7eceSJian Shen 342f550a46SYunsheng Lin MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 352f550a46SYunsheng Lin 361600c3e5SJian Shen static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 371600c3e5SJian Shen HCLGEVF_CMDQ_TX_ADDR_H_REG, 381600c3e5SJian Shen HCLGEVF_CMDQ_TX_DEPTH_REG, 391600c3e5SJian Shen HCLGEVF_CMDQ_TX_TAIL_REG, 401600c3e5SJian Shen HCLGEVF_CMDQ_TX_HEAD_REG, 411600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_L_REG, 421600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_H_REG, 431600c3e5SJian Shen HCLGEVF_CMDQ_RX_DEPTH_REG, 441600c3e5SJian Shen HCLGEVF_CMDQ_RX_TAIL_REG, 451600c3e5SJian Shen HCLGEVF_CMDQ_RX_HEAD_REG, 461600c3e5SJian Shen HCLGEVF_VECTOR0_CMDQ_SRC_REG, 471600c3e5SJian Shen HCLGEVF_CMDQ_INTR_STS_REG, 481600c3e5SJian Shen HCLGEVF_CMDQ_INTR_EN_REG, 491600c3e5SJian Shen HCLGEVF_CMDQ_INTR_GEN_REG}; 501600c3e5SJian Shen 511600c3e5SJian Shen static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 521600c3e5SJian Shen HCLGEVF_RST_ING, 531600c3e5SJian Shen HCLGEVF_GRO_EN_REG}; 541600c3e5SJian Shen 551600c3e5SJian Shen static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 561600c3e5SJian Shen HCLGEVF_RING_RX_ADDR_H_REG, 571600c3e5SJian Shen HCLGEVF_RING_RX_BD_NUM_REG, 581600c3e5SJian Shen HCLGEVF_RING_RX_BD_LENGTH_REG, 591600c3e5SJian Shen HCLGEVF_RING_RX_MERGE_EN_REG, 601600c3e5SJian Shen HCLGEVF_RING_RX_TAIL_REG, 611600c3e5SJian Shen HCLGEVF_RING_RX_HEAD_REG, 621600c3e5SJian Shen HCLGEVF_RING_RX_FBD_NUM_REG, 631600c3e5SJian Shen HCLGEVF_RING_RX_OFFSET_REG, 641600c3e5SJian Shen HCLGEVF_RING_RX_FBD_OFFSET_REG, 651600c3e5SJian Shen HCLGEVF_RING_RX_STASH_REG, 661600c3e5SJian Shen HCLGEVF_RING_RX_BD_ERR_REG, 671600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_L_REG, 681600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_H_REG, 691600c3e5SJian Shen HCLGEVF_RING_TX_BD_NUM_REG, 701600c3e5SJian Shen HCLGEVF_RING_TX_PRIORITY_REG, 711600c3e5SJian Shen HCLGEVF_RING_TX_TC_REG, 721600c3e5SJian Shen HCLGEVF_RING_TX_MERGE_EN_REG, 731600c3e5SJian Shen HCLGEVF_RING_TX_TAIL_REG, 741600c3e5SJian Shen HCLGEVF_RING_TX_HEAD_REG, 751600c3e5SJian Shen HCLGEVF_RING_TX_FBD_NUM_REG, 761600c3e5SJian Shen HCLGEVF_RING_TX_OFFSET_REG, 771600c3e5SJian Shen HCLGEVF_RING_TX_EBD_NUM_REG, 781600c3e5SJian Shen HCLGEVF_RING_TX_EBD_OFFSET_REG, 791600c3e5SJian Shen HCLGEVF_RING_TX_BD_ERR_REG, 801600c3e5SJian Shen HCLGEVF_RING_EN_REG}; 811600c3e5SJian Shen 821600c3e5SJian Shen static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 831600c3e5SJian Shen HCLGEVF_TQP_INTR_GL0_REG, 841600c3e5SJian Shen HCLGEVF_TQP_INTR_GL1_REG, 851600c3e5SJian Shen HCLGEVF_TQP_INTR_GL2_REG, 861600c3e5SJian Shen HCLGEVF_TQP_INTR_RL_REG}; 871600c3e5SJian Shen 889b2f3477SWeihang Li static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 89e2cb1decSSalil Mehta { 90eed9535fSPeng Li if (!handle->client) 91eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, nic); 92eed9535fSPeng Li else if (handle->client->type == HNAE3_CLIENT_ROCE) 93eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, roce); 94eed9535fSPeng Li else 95e2cb1decSSalil Mehta return container_of(handle, struct hclgevf_dev, nic); 96e2cb1decSSalil Mehta } 97e2cb1decSSalil Mehta 98e2cb1decSSalil Mehta static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 99e2cb1decSSalil Mehta { 100b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 101e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 102e2cb1decSSalil Mehta struct hclgevf_desc desc; 103e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 104e2cb1decSSalil Mehta int status; 105e2cb1decSSalil Mehta int i; 106e2cb1decSSalil Mehta 107b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 108b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 109e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 110e2cb1decSSalil Mehta HCLGEVF_OPC_QUERY_RX_STATUS, 111e2cb1decSSalil Mehta true); 112e2cb1decSSalil Mehta 113e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 114e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 115e2cb1decSSalil Mehta if (status) { 116e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 117e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 118e2cb1decSSalil Mehta status, i); 119e2cb1decSSalil Mehta return status; 120e2cb1decSSalil Mehta } 121e2cb1decSSalil Mehta tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 122cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 123e2cb1decSSalil Mehta 124e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 125e2cb1decSSalil Mehta true); 126e2cb1decSSalil Mehta 127e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 128e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 129e2cb1decSSalil Mehta if (status) { 130e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 131e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 132e2cb1decSSalil Mehta status, i); 133e2cb1decSSalil Mehta return status; 134e2cb1decSSalil Mehta } 135e2cb1decSSalil Mehta tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 136cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 137e2cb1decSSalil Mehta } 138e2cb1decSSalil Mehta 139e2cb1decSSalil Mehta return 0; 140e2cb1decSSalil Mehta } 141e2cb1decSSalil Mehta 142e2cb1decSSalil Mehta static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 143e2cb1decSSalil Mehta { 144e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo = &handle->kinfo; 145e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 146e2cb1decSSalil Mehta u64 *buff = data; 147e2cb1decSSalil Mehta int i; 148e2cb1decSSalil Mehta 149b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 150b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 151e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 152e2cb1decSSalil Mehta } 153e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 154b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 155e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 156e2cb1decSSalil Mehta } 157e2cb1decSSalil Mehta 158e2cb1decSSalil Mehta return buff; 159e2cb1decSSalil Mehta } 160e2cb1decSSalil Mehta 161e2cb1decSSalil Mehta static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 162e2cb1decSSalil Mehta { 163b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 164e2cb1decSSalil Mehta 165b4f1d303SJian Shen return kinfo->num_tqps * 2; 166e2cb1decSSalil Mehta } 167e2cb1decSSalil Mehta 168e2cb1decSSalil Mehta static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 169e2cb1decSSalil Mehta { 170b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 171e2cb1decSSalil Mehta u8 *buff = data; 172e2cb1decSSalil Mehta int i = 0; 173e2cb1decSSalil Mehta 174b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 175b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 176e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1770c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 178e2cb1decSSalil Mehta tqp->index); 179e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 180e2cb1decSSalil Mehta } 181e2cb1decSSalil Mehta 182b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 183b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 184e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1850c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 186e2cb1decSSalil Mehta tqp->index); 187e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 188e2cb1decSSalil Mehta } 189e2cb1decSSalil Mehta 190e2cb1decSSalil Mehta return buff; 191e2cb1decSSalil Mehta } 192e2cb1decSSalil Mehta 193e2cb1decSSalil Mehta static void hclgevf_update_stats(struct hnae3_handle *handle, 194e2cb1decSSalil Mehta struct net_device_stats *net_stats) 195e2cb1decSSalil Mehta { 196e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 197e2cb1decSSalil Mehta int status; 198e2cb1decSSalil Mehta 199e2cb1decSSalil Mehta status = hclgevf_tqps_update_stats(handle); 200e2cb1decSSalil Mehta if (status) 201e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 202e2cb1decSSalil Mehta "VF update of TQPS stats fail, status = %d.\n", 203e2cb1decSSalil Mehta status); 204e2cb1decSSalil Mehta } 205e2cb1decSSalil Mehta 206e2cb1decSSalil Mehta static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 207e2cb1decSSalil Mehta { 208e2cb1decSSalil Mehta if (strset == ETH_SS_TEST) 209e2cb1decSSalil Mehta return -EOPNOTSUPP; 210e2cb1decSSalil Mehta else if (strset == ETH_SS_STATS) 211e2cb1decSSalil Mehta return hclgevf_tqps_get_sset_count(handle, strset); 212e2cb1decSSalil Mehta 213e2cb1decSSalil Mehta return 0; 214e2cb1decSSalil Mehta } 215e2cb1decSSalil Mehta 216e2cb1decSSalil Mehta static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 217e2cb1decSSalil Mehta u8 *data) 218e2cb1decSSalil Mehta { 219e2cb1decSSalil Mehta u8 *p = (char *)data; 220e2cb1decSSalil Mehta 221e2cb1decSSalil Mehta if (strset == ETH_SS_STATS) 222e2cb1decSSalil Mehta p = hclgevf_tqps_get_strings(handle, p); 223e2cb1decSSalil Mehta } 224e2cb1decSSalil Mehta 225e2cb1decSSalil Mehta static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 226e2cb1decSSalil Mehta { 227e2cb1decSSalil Mehta hclgevf_tqps_get_stats(handle, data); 228e2cb1decSSalil Mehta } 229e2cb1decSSalil Mehta 230e2cb1decSSalil Mehta static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 231e2cb1decSSalil Mehta { 232e2cb1decSSalil Mehta u8 resp_msg; 233e2cb1decSSalil Mehta int status; 234e2cb1decSSalil Mehta 235e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 23663cbf7a9SYufeng Mo true, &resp_msg, sizeof(resp_msg)); 237e2cb1decSSalil Mehta if (status) { 238e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 239e2cb1decSSalil Mehta "VF request to get TC info from PF failed %d", 240e2cb1decSSalil Mehta status); 241e2cb1decSSalil Mehta return status; 242e2cb1decSSalil Mehta } 243e2cb1decSSalil Mehta 244e2cb1decSSalil Mehta hdev->hw_tc_map = resp_msg; 245e2cb1decSSalil Mehta 246e2cb1decSSalil Mehta return 0; 247e2cb1decSSalil Mehta } 248e2cb1decSSalil Mehta 24992f11ea1SJian Shen static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 25092f11ea1SJian Shen { 25192f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 25292f11ea1SJian Shen u8 resp_msg; 25392f11ea1SJian Shen int ret; 25492f11ea1SJian Shen 25592f11ea1SJian Shen ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 25692f11ea1SJian Shen HCLGE_MBX_GET_PORT_BASE_VLAN_STATE, 25792f11ea1SJian Shen NULL, 0, true, &resp_msg, sizeof(u8)); 25892f11ea1SJian Shen if (ret) { 25992f11ea1SJian Shen dev_err(&hdev->pdev->dev, 26092f11ea1SJian Shen "VF request to get port based vlan state failed %d", 26192f11ea1SJian Shen ret); 26292f11ea1SJian Shen return ret; 26392f11ea1SJian Shen } 26492f11ea1SJian Shen 26592f11ea1SJian Shen nic->port_base_vlan_state = resp_msg; 26692f11ea1SJian Shen 26792f11ea1SJian Shen return 0; 26892f11ea1SJian Shen } 26992f11ea1SJian Shen 2706cee6fc3SJian Shen static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 271e2cb1decSSalil Mehta { 272c0425944SPeng Li #define HCLGEVF_TQPS_RSS_INFO_LEN 6 273e2cb1decSSalil Mehta u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 274e2cb1decSSalil Mehta int status; 275e2cb1decSSalil Mehta 276e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 277e2cb1decSSalil Mehta true, resp_msg, 278e2cb1decSSalil Mehta HCLGEVF_TQPS_RSS_INFO_LEN); 279e2cb1decSSalil Mehta if (status) { 280e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 281e2cb1decSSalil Mehta "VF request to get tqp info from PF failed %d", 282e2cb1decSSalil Mehta status); 283e2cb1decSSalil Mehta return status; 284e2cb1decSSalil Mehta } 285e2cb1decSSalil Mehta 286e2cb1decSSalil Mehta memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 287e2cb1decSSalil Mehta memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 288c0425944SPeng Li memcpy(&hdev->rx_buf_len, &resp_msg[4], sizeof(u16)); 289c0425944SPeng Li 290c0425944SPeng Li return 0; 291c0425944SPeng Li } 292c0425944SPeng Li 293c0425944SPeng Li static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 294c0425944SPeng Li { 295c0425944SPeng Li #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 296c0425944SPeng Li u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 297c0425944SPeng Li int ret; 298c0425944SPeng Li 299c0425944SPeng Li ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QDEPTH, 0, NULL, 0, 300c0425944SPeng Li true, resp_msg, 301c0425944SPeng Li HCLGEVF_TQPS_DEPTH_INFO_LEN); 302c0425944SPeng Li if (ret) { 303c0425944SPeng Li dev_err(&hdev->pdev->dev, 304c0425944SPeng Li "VF request to get tqp depth info from PF failed %d", 305c0425944SPeng Li ret); 306c0425944SPeng Li return ret; 307c0425944SPeng Li } 308c0425944SPeng Li 309c0425944SPeng Li memcpy(&hdev->num_tx_desc, &resp_msg[0], sizeof(u16)); 310c0425944SPeng Li memcpy(&hdev->num_rx_desc, &resp_msg[2], sizeof(u16)); 311e2cb1decSSalil Mehta 312e2cb1decSSalil Mehta return 0; 313e2cb1decSSalil Mehta } 314e2cb1decSSalil Mehta 3150c29d191Sliuzhongzhu static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 3160c29d191Sliuzhongzhu { 3170c29d191Sliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3180c29d191Sliuzhongzhu u8 msg_data[2], resp_data[2]; 3190c29d191Sliuzhongzhu u16 qid_in_pf = 0; 3200c29d191Sliuzhongzhu int ret; 3210c29d191Sliuzhongzhu 3220c29d191Sliuzhongzhu memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 3230c29d191Sliuzhongzhu 3240c29d191Sliuzhongzhu ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data, 32563cbf7a9SYufeng Mo sizeof(msg_data), true, resp_data, 32663cbf7a9SYufeng Mo sizeof(resp_data)); 3270c29d191Sliuzhongzhu if (!ret) 3280c29d191Sliuzhongzhu qid_in_pf = *(u16 *)resp_data; 3290c29d191Sliuzhongzhu 3300c29d191Sliuzhongzhu return qid_in_pf; 3310c29d191Sliuzhongzhu } 3320c29d191Sliuzhongzhu 3339c3e7130Sliuzhongzhu static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 3349c3e7130Sliuzhongzhu { 33588d10bd6SJian Shen u8 resp_msg[2]; 3369c3e7130Sliuzhongzhu int ret; 3379c3e7130Sliuzhongzhu 3389c3e7130Sliuzhongzhu ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_MEDIA_TYPE, 0, NULL, 0, 33988d10bd6SJian Shen true, resp_msg, sizeof(resp_msg)); 3409c3e7130Sliuzhongzhu if (ret) { 3419c3e7130Sliuzhongzhu dev_err(&hdev->pdev->dev, 3429c3e7130Sliuzhongzhu "VF request to get the pf port media type failed %d", 3439c3e7130Sliuzhongzhu ret); 3449c3e7130Sliuzhongzhu return ret; 3459c3e7130Sliuzhongzhu } 3469c3e7130Sliuzhongzhu 34788d10bd6SJian Shen hdev->hw.mac.media_type = resp_msg[0]; 34888d10bd6SJian Shen hdev->hw.mac.module_type = resp_msg[1]; 3499c3e7130Sliuzhongzhu 3509c3e7130Sliuzhongzhu return 0; 3519c3e7130Sliuzhongzhu } 3529c3e7130Sliuzhongzhu 353e2cb1decSSalil Mehta static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 354e2cb1decSSalil Mehta { 355e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 356e2cb1decSSalil Mehta int i; 357e2cb1decSSalil Mehta 358e2cb1decSSalil Mehta hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 359e2cb1decSSalil Mehta sizeof(struct hclgevf_tqp), GFP_KERNEL); 360e2cb1decSSalil Mehta if (!hdev->htqp) 361e2cb1decSSalil Mehta return -ENOMEM; 362e2cb1decSSalil Mehta 363e2cb1decSSalil Mehta tqp = hdev->htqp; 364e2cb1decSSalil Mehta 365e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 366e2cb1decSSalil Mehta tqp->dev = &hdev->pdev->dev; 367e2cb1decSSalil Mehta tqp->index = i; 368e2cb1decSSalil Mehta 369e2cb1decSSalil Mehta tqp->q.ae_algo = &ae_algovf; 370e2cb1decSSalil Mehta tqp->q.buf_size = hdev->rx_buf_len; 371c0425944SPeng Li tqp->q.tx_desc_num = hdev->num_tx_desc; 372c0425944SPeng Li tqp->q.rx_desc_num = hdev->num_rx_desc; 373e2cb1decSSalil Mehta tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 374e2cb1decSSalil Mehta i * HCLGEVF_TQP_REG_SIZE; 375e2cb1decSSalil Mehta 376e2cb1decSSalil Mehta tqp++; 377e2cb1decSSalil Mehta } 378e2cb1decSSalil Mehta 379e2cb1decSSalil Mehta return 0; 380e2cb1decSSalil Mehta } 381e2cb1decSSalil Mehta 382e2cb1decSSalil Mehta static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 383e2cb1decSSalil Mehta { 384e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 385e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo; 386e2cb1decSSalil Mehta u16 new_tqps = hdev->num_tqps; 387ebaf1908SWeihang Li unsigned int i; 388e2cb1decSSalil Mehta 389e2cb1decSSalil Mehta kinfo = &nic->kinfo; 390e2cb1decSSalil Mehta kinfo->num_tc = 0; 391c0425944SPeng Li kinfo->num_tx_desc = hdev->num_tx_desc; 392c0425944SPeng Li kinfo->num_rx_desc = hdev->num_rx_desc; 393e2cb1decSSalil Mehta kinfo->rx_buf_len = hdev->rx_buf_len; 394e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 395e2cb1decSSalil Mehta if (hdev->hw_tc_map & BIT(i)) 396e2cb1decSSalil Mehta kinfo->num_tc++; 397e2cb1decSSalil Mehta 398e2cb1decSSalil Mehta kinfo->rss_size 399e2cb1decSSalil Mehta = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 400e2cb1decSSalil Mehta new_tqps = kinfo->rss_size * kinfo->num_tc; 401e2cb1decSSalil Mehta kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 402e2cb1decSSalil Mehta 403e2cb1decSSalil Mehta kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 404e2cb1decSSalil Mehta sizeof(struct hnae3_queue *), GFP_KERNEL); 405e2cb1decSSalil Mehta if (!kinfo->tqp) 406e2cb1decSSalil Mehta return -ENOMEM; 407e2cb1decSSalil Mehta 408e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 409e2cb1decSSalil Mehta hdev->htqp[i].q.handle = &hdev->nic; 410e2cb1decSSalil Mehta hdev->htqp[i].q.tqp_index = i; 411e2cb1decSSalil Mehta kinfo->tqp[i] = &hdev->htqp[i].q; 412e2cb1decSSalil Mehta } 413e2cb1decSSalil Mehta 414e2cb1decSSalil Mehta return 0; 415e2cb1decSSalil Mehta } 416e2cb1decSSalil Mehta 417e2cb1decSSalil Mehta static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 418e2cb1decSSalil Mehta { 419e2cb1decSSalil Mehta int status; 420e2cb1decSSalil Mehta u8 resp_msg; 421e2cb1decSSalil Mehta 422e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 42363cbf7a9SYufeng Mo 0, false, &resp_msg, sizeof(resp_msg)); 424e2cb1decSSalil Mehta if (status) 425e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 426e2cb1decSSalil Mehta "VF failed to fetch link status(%d) from PF", status); 427e2cb1decSSalil Mehta } 428e2cb1decSSalil Mehta 429e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 430e2cb1decSSalil Mehta { 43145e92b7eSPeng Li struct hnae3_handle *rhandle = &hdev->roce; 432e2cb1decSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 43345e92b7eSPeng Li struct hnae3_client *rclient; 434e2cb1decSSalil Mehta struct hnae3_client *client; 435e2cb1decSSalil Mehta 436e2cb1decSSalil Mehta client = handle->client; 43745e92b7eSPeng Li rclient = hdev->roce_client; 438e2cb1decSSalil Mehta 439582d37bbSPeng Li link_state = 440582d37bbSPeng Li test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 441582d37bbSPeng Li 442e2cb1decSSalil Mehta if (link_state != hdev->hw.mac.link) { 443e2cb1decSSalil Mehta client->ops->link_status_change(handle, !!link_state); 44445e92b7eSPeng Li if (rclient && rclient->ops->link_status_change) 44545e92b7eSPeng Li rclient->ops->link_status_change(rhandle, !!link_state); 446e2cb1decSSalil Mehta hdev->hw.mac.link = link_state; 447e2cb1decSSalil Mehta } 448e2cb1decSSalil Mehta } 449e2cb1decSSalil Mehta 450538abaf3SYueHaibing static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 4519194d18bSliuzhongzhu { 4529194d18bSliuzhongzhu #define HCLGEVF_ADVERTISING 0 4539194d18bSliuzhongzhu #define HCLGEVF_SUPPORTED 1 4549194d18bSliuzhongzhu u8 send_msg; 4559194d18bSliuzhongzhu u8 resp_msg; 4569194d18bSliuzhongzhu 4579194d18bSliuzhongzhu send_msg = HCLGEVF_ADVERTISING; 45863cbf7a9SYufeng Mo hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 45963cbf7a9SYufeng Mo &send_msg, sizeof(send_msg), false, 46063cbf7a9SYufeng Mo &resp_msg, sizeof(resp_msg)); 4619194d18bSliuzhongzhu send_msg = HCLGEVF_SUPPORTED; 46263cbf7a9SYufeng Mo hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 46363cbf7a9SYufeng Mo &send_msg, sizeof(send_msg), false, 46463cbf7a9SYufeng Mo &resp_msg, sizeof(resp_msg)); 4659194d18bSliuzhongzhu } 4669194d18bSliuzhongzhu 467e2cb1decSSalil Mehta static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 468e2cb1decSSalil Mehta { 469e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 470e2cb1decSSalil Mehta int ret; 471e2cb1decSSalil Mehta 472e2cb1decSSalil Mehta nic->ae_algo = &ae_algovf; 473e2cb1decSSalil Mehta nic->pdev = hdev->pdev; 474e2cb1decSSalil Mehta nic->numa_node_mask = hdev->numa_node_mask; 475424eb834SSalil Mehta nic->flags |= HNAE3_SUPPORT_VF; 476e2cb1decSSalil Mehta 477e2cb1decSSalil Mehta ret = hclgevf_knic_setup(hdev); 478e2cb1decSSalil Mehta if (ret) 479e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 480e2cb1decSSalil Mehta ret); 481e2cb1decSSalil Mehta return ret; 482e2cb1decSSalil Mehta } 483e2cb1decSSalil Mehta 484e2cb1decSSalil Mehta static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 485e2cb1decSSalil Mehta { 48636cbbdf6SPeng Li if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 48736cbbdf6SPeng Li dev_warn(&hdev->pdev->dev, 48836cbbdf6SPeng Li "vector(vector_id %d) has been freed.\n", vector_id); 48936cbbdf6SPeng Li return; 49036cbbdf6SPeng Li } 49136cbbdf6SPeng Li 492e2cb1decSSalil Mehta hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 493e2cb1decSSalil Mehta hdev->num_msi_left += 1; 494e2cb1decSSalil Mehta hdev->num_msi_used -= 1; 495e2cb1decSSalil Mehta } 496e2cb1decSSalil Mehta 497e2cb1decSSalil Mehta static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 498e2cb1decSSalil Mehta struct hnae3_vector_info *vector_info) 499e2cb1decSSalil Mehta { 500e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 501e2cb1decSSalil Mehta struct hnae3_vector_info *vector = vector_info; 502e2cb1decSSalil Mehta int alloc = 0; 503e2cb1decSSalil Mehta int i, j; 504e2cb1decSSalil Mehta 505e2cb1decSSalil Mehta vector_num = min(hdev->num_msi_left, vector_num); 506e2cb1decSSalil Mehta 507e2cb1decSSalil Mehta for (j = 0; j < vector_num; j++) { 508e2cb1decSSalil Mehta for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 509e2cb1decSSalil Mehta if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 510e2cb1decSSalil Mehta vector->vector = pci_irq_vector(hdev->pdev, i); 511e2cb1decSSalil Mehta vector->io_addr = hdev->hw.io_base + 512e2cb1decSSalil Mehta HCLGEVF_VECTOR_REG_BASE + 513e2cb1decSSalil Mehta (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 514e2cb1decSSalil Mehta hdev->vector_status[i] = 0; 515e2cb1decSSalil Mehta hdev->vector_irq[i] = vector->vector; 516e2cb1decSSalil Mehta 517e2cb1decSSalil Mehta vector++; 518e2cb1decSSalil Mehta alloc++; 519e2cb1decSSalil Mehta 520e2cb1decSSalil Mehta break; 521e2cb1decSSalil Mehta } 522e2cb1decSSalil Mehta } 523e2cb1decSSalil Mehta } 524e2cb1decSSalil Mehta hdev->num_msi_left -= alloc; 525e2cb1decSSalil Mehta hdev->num_msi_used += alloc; 526e2cb1decSSalil Mehta 527e2cb1decSSalil Mehta return alloc; 528e2cb1decSSalil Mehta } 529e2cb1decSSalil Mehta 530e2cb1decSSalil Mehta static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 531e2cb1decSSalil Mehta { 532e2cb1decSSalil Mehta int i; 533e2cb1decSSalil Mehta 534e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 535e2cb1decSSalil Mehta if (vector == hdev->vector_irq[i]) 536e2cb1decSSalil Mehta return i; 537e2cb1decSSalil Mehta 538e2cb1decSSalil Mehta return -EINVAL; 539e2cb1decSSalil Mehta } 540e2cb1decSSalil Mehta 541374ad291SJian Shen static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 542374ad291SJian Shen const u8 hfunc, const u8 *key) 543374ad291SJian Shen { 544374ad291SJian Shen struct hclgevf_rss_config_cmd *req; 545ebaf1908SWeihang Li unsigned int key_offset = 0; 546374ad291SJian Shen struct hclgevf_desc desc; 5473caf772bSYufeng Mo int key_counts; 548374ad291SJian Shen int key_size; 549374ad291SJian Shen int ret; 550374ad291SJian Shen 5513caf772bSYufeng Mo key_counts = HCLGEVF_RSS_KEY_SIZE; 552374ad291SJian Shen req = (struct hclgevf_rss_config_cmd *)desc.data; 553374ad291SJian Shen 5543caf772bSYufeng Mo while (key_counts) { 555374ad291SJian Shen hclgevf_cmd_setup_basic_desc(&desc, 556374ad291SJian Shen HCLGEVF_OPC_RSS_GENERIC_CONFIG, 557374ad291SJian Shen false); 558374ad291SJian Shen 559374ad291SJian Shen req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 560374ad291SJian Shen req->hash_config |= 561374ad291SJian Shen (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 562374ad291SJian Shen 5633caf772bSYufeng Mo key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts); 564374ad291SJian Shen memcpy(req->hash_key, 565374ad291SJian Shen key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 566374ad291SJian Shen 5673caf772bSYufeng Mo key_counts -= key_size; 5683caf772bSYufeng Mo key_offset++; 569374ad291SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 570374ad291SJian Shen if (ret) { 571374ad291SJian Shen dev_err(&hdev->pdev->dev, 572374ad291SJian Shen "Configure RSS config fail, status = %d\n", 573374ad291SJian Shen ret); 574374ad291SJian Shen return ret; 575374ad291SJian Shen } 576374ad291SJian Shen } 577374ad291SJian Shen 578374ad291SJian Shen return 0; 579374ad291SJian Shen } 580374ad291SJian Shen 581e2cb1decSSalil Mehta static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 582e2cb1decSSalil Mehta { 583e2cb1decSSalil Mehta return HCLGEVF_RSS_KEY_SIZE; 584e2cb1decSSalil Mehta } 585e2cb1decSSalil Mehta 586e2cb1decSSalil Mehta static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 587e2cb1decSSalil Mehta { 588e2cb1decSSalil Mehta return HCLGEVF_RSS_IND_TBL_SIZE; 589e2cb1decSSalil Mehta } 590e2cb1decSSalil Mehta 591e2cb1decSSalil Mehta static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 592e2cb1decSSalil Mehta { 593e2cb1decSSalil Mehta const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 594e2cb1decSSalil Mehta struct hclgevf_rss_indirection_table_cmd *req; 595e2cb1decSSalil Mehta struct hclgevf_desc desc; 596e2cb1decSSalil Mehta int status; 597e2cb1decSSalil Mehta int i, j; 598e2cb1decSSalil Mehta 599e2cb1decSSalil Mehta req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 600e2cb1decSSalil Mehta 601e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 602e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 603e2cb1decSSalil Mehta false); 604e2cb1decSSalil Mehta req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 605e2cb1decSSalil Mehta req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 606e2cb1decSSalil Mehta for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 607e2cb1decSSalil Mehta req->rss_result[j] = 608e2cb1decSSalil Mehta indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 609e2cb1decSSalil Mehta 610e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 611e2cb1decSSalil Mehta if (status) { 612e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 613e2cb1decSSalil Mehta "VF failed(=%d) to set RSS indirection table\n", 614e2cb1decSSalil Mehta status); 615e2cb1decSSalil Mehta return status; 616e2cb1decSSalil Mehta } 617e2cb1decSSalil Mehta } 618e2cb1decSSalil Mehta 619e2cb1decSSalil Mehta return 0; 620e2cb1decSSalil Mehta } 621e2cb1decSSalil Mehta 622e2cb1decSSalil Mehta static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 623e2cb1decSSalil Mehta { 624e2cb1decSSalil Mehta struct hclgevf_rss_tc_mode_cmd *req; 625e2cb1decSSalil Mehta u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 626e2cb1decSSalil Mehta u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 627e2cb1decSSalil Mehta u16 tc_size[HCLGEVF_MAX_TC_NUM]; 628e2cb1decSSalil Mehta struct hclgevf_desc desc; 629e2cb1decSSalil Mehta u16 roundup_size; 630e2cb1decSSalil Mehta int status; 631ebaf1908SWeihang Li unsigned int i; 632e2cb1decSSalil Mehta 633e2cb1decSSalil Mehta req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 634e2cb1decSSalil Mehta 635e2cb1decSSalil Mehta roundup_size = roundup_pow_of_two(rss_size); 636e2cb1decSSalil Mehta roundup_size = ilog2(roundup_size); 637e2cb1decSSalil Mehta 638e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 639e2cb1decSSalil Mehta tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 640e2cb1decSSalil Mehta tc_size[i] = roundup_size; 641e2cb1decSSalil Mehta tc_offset[i] = rss_size * i; 642e2cb1decSSalil Mehta } 643e2cb1decSSalil Mehta 644e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 645e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 646e4e87715SPeng Li hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 647e2cb1decSSalil Mehta (tc_valid[i] & 0x1)); 648e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 649e2cb1decSSalil Mehta HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 650e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 651e2cb1decSSalil Mehta HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 652e2cb1decSSalil Mehta } 653e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 654e2cb1decSSalil Mehta if (status) 655e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 656e2cb1decSSalil Mehta "VF failed(=%d) to set rss tc mode\n", status); 657e2cb1decSSalil Mehta 658e2cb1decSSalil Mehta return status; 659e2cb1decSSalil Mehta } 660e2cb1decSSalil Mehta 661a638b1d8SJian Shen /* for revision 0x20, vf shared the same rss config with pf */ 662a638b1d8SJian Shen static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 663a638b1d8SJian Shen { 664a638b1d8SJian Shen #define HCLGEVF_RSS_MBX_RESP_LEN 8 665a638b1d8SJian Shen 666a638b1d8SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 667a638b1d8SJian Shen u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 668a638b1d8SJian Shen u16 msg_num, hash_key_index; 669a638b1d8SJian Shen u8 index; 670a638b1d8SJian Shen int ret; 671a638b1d8SJian Shen 672a638b1d8SJian Shen msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 673a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN; 674a638b1d8SJian Shen for (index = 0; index < msg_num; index++) { 675a638b1d8SJian Shen ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_RSS_KEY, 0, 676a638b1d8SJian Shen &index, sizeof(index), 677a638b1d8SJian Shen true, resp_msg, 678a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN); 679a638b1d8SJian Shen if (ret) { 680a638b1d8SJian Shen dev_err(&hdev->pdev->dev, 681a638b1d8SJian Shen "VF get rss hash key from PF failed, ret=%d", 682a638b1d8SJian Shen ret); 683a638b1d8SJian Shen return ret; 684a638b1d8SJian Shen } 685a638b1d8SJian Shen 686a638b1d8SJian Shen hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 687a638b1d8SJian Shen if (index == msg_num - 1) 688a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 689a638b1d8SJian Shen &resp_msg[0], 690a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE - hash_key_index); 691a638b1d8SJian Shen else 692a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 693a638b1d8SJian Shen &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 694a638b1d8SJian Shen } 695a638b1d8SJian Shen 696a638b1d8SJian Shen return 0; 697a638b1d8SJian Shen } 698a638b1d8SJian Shen 699e2cb1decSSalil Mehta static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 700e2cb1decSSalil Mehta u8 *hfunc) 701e2cb1decSSalil Mehta { 702e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 703e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 704a638b1d8SJian Shen int i, ret; 705e2cb1decSSalil Mehta 706374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 707374ad291SJian Shen /* Get hash algorithm */ 708374ad291SJian Shen if (hfunc) { 709374ad291SJian Shen switch (rss_cfg->hash_algo) { 710374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 711374ad291SJian Shen *hfunc = ETH_RSS_HASH_TOP; 712374ad291SJian Shen break; 713374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 714374ad291SJian Shen *hfunc = ETH_RSS_HASH_XOR; 715374ad291SJian Shen break; 716374ad291SJian Shen default: 717374ad291SJian Shen *hfunc = ETH_RSS_HASH_UNKNOWN; 718374ad291SJian Shen break; 719374ad291SJian Shen } 720374ad291SJian Shen } 721374ad291SJian Shen 722374ad291SJian Shen /* Get the RSS Key required by the user */ 723374ad291SJian Shen if (key) 724374ad291SJian Shen memcpy(key, rss_cfg->rss_hash_key, 725374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 726a638b1d8SJian Shen } else { 727a638b1d8SJian Shen if (hfunc) 728a638b1d8SJian Shen *hfunc = ETH_RSS_HASH_TOP; 729a638b1d8SJian Shen if (key) { 730a638b1d8SJian Shen ret = hclgevf_get_rss_hash_key(hdev); 731a638b1d8SJian Shen if (ret) 732a638b1d8SJian Shen return ret; 733a638b1d8SJian Shen memcpy(key, rss_cfg->rss_hash_key, 734a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE); 735a638b1d8SJian Shen } 736374ad291SJian Shen } 737374ad291SJian Shen 738e2cb1decSSalil Mehta if (indir) 739e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 740e2cb1decSSalil Mehta indir[i] = rss_cfg->rss_indirection_tbl[i]; 741e2cb1decSSalil Mehta 742374ad291SJian Shen return 0; 743e2cb1decSSalil Mehta } 744e2cb1decSSalil Mehta 745e2cb1decSSalil Mehta static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 746e2cb1decSSalil Mehta const u8 *key, const u8 hfunc) 747e2cb1decSSalil Mehta { 748e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 749e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 750374ad291SJian Shen int ret, i; 751374ad291SJian Shen 752374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 753374ad291SJian Shen /* Set the RSS Hash Key if specififed by the user */ 754374ad291SJian Shen if (key) { 755374ad291SJian Shen switch (hfunc) { 756374ad291SJian Shen case ETH_RSS_HASH_TOP: 757374ad291SJian Shen rss_cfg->hash_algo = 758374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 759374ad291SJian Shen break; 760374ad291SJian Shen case ETH_RSS_HASH_XOR: 761374ad291SJian Shen rss_cfg->hash_algo = 762374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_SIMPLE; 763374ad291SJian Shen break; 764374ad291SJian Shen case ETH_RSS_HASH_NO_CHANGE: 765374ad291SJian Shen break; 766374ad291SJian Shen default: 767374ad291SJian Shen return -EINVAL; 768374ad291SJian Shen } 769374ad291SJian Shen 770374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 771374ad291SJian Shen key); 772374ad291SJian Shen if (ret) 773374ad291SJian Shen return ret; 774374ad291SJian Shen 775374ad291SJian Shen /* Update the shadow RSS key with user specified qids */ 776374ad291SJian Shen memcpy(rss_cfg->rss_hash_key, key, 777374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 778374ad291SJian Shen } 779374ad291SJian Shen } 780e2cb1decSSalil Mehta 781e2cb1decSSalil Mehta /* update the shadow RSS table with user specified qids */ 782e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 783e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = indir[i]; 784e2cb1decSSalil Mehta 785e2cb1decSSalil Mehta /* update the hardware */ 786e2cb1decSSalil Mehta return hclgevf_set_rss_indir_table(hdev); 787e2cb1decSSalil Mehta } 788e2cb1decSSalil Mehta 789d97b3072SJian Shen static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 790d97b3072SJian Shen { 791d97b3072SJian Shen u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 792d97b3072SJian Shen 793d97b3072SJian Shen if (nfc->data & RXH_L4_B_2_3) 794d97b3072SJian Shen hash_sets |= HCLGEVF_D_PORT_BIT; 795d97b3072SJian Shen else 796d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_PORT_BIT; 797d97b3072SJian Shen 798d97b3072SJian Shen if (nfc->data & RXH_IP_SRC) 799d97b3072SJian Shen hash_sets |= HCLGEVF_S_IP_BIT; 800d97b3072SJian Shen else 801d97b3072SJian Shen hash_sets &= ~HCLGEVF_S_IP_BIT; 802d97b3072SJian Shen 803d97b3072SJian Shen if (nfc->data & RXH_IP_DST) 804d97b3072SJian Shen hash_sets |= HCLGEVF_D_IP_BIT; 805d97b3072SJian Shen else 806d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_IP_BIT; 807d97b3072SJian Shen 808d97b3072SJian Shen if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 809d97b3072SJian Shen hash_sets |= HCLGEVF_V_TAG_BIT; 810d97b3072SJian Shen 811d97b3072SJian Shen return hash_sets; 812d97b3072SJian Shen } 813d97b3072SJian Shen 814d97b3072SJian Shen static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 815d97b3072SJian Shen struct ethtool_rxnfc *nfc) 816d97b3072SJian Shen { 817d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 818d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 819d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 820d97b3072SJian Shen struct hclgevf_desc desc; 821d97b3072SJian Shen u8 tuple_sets; 822d97b3072SJian Shen int ret; 823d97b3072SJian Shen 824d97b3072SJian Shen if (handle->pdev->revision == 0x20) 825d97b3072SJian Shen return -EOPNOTSUPP; 826d97b3072SJian Shen 827d97b3072SJian Shen if (nfc->data & 828d97b3072SJian Shen ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 829d97b3072SJian Shen return -EINVAL; 830d97b3072SJian Shen 831d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 832d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 833d97b3072SJian Shen 834d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 835d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 836d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 837d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 838d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 839d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 840d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 841d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 842d97b3072SJian Shen 843d97b3072SJian Shen tuple_sets = hclgevf_get_rss_hash_bits(nfc); 844d97b3072SJian Shen switch (nfc->flow_type) { 845d97b3072SJian Shen case TCP_V4_FLOW: 846d97b3072SJian Shen req->ipv4_tcp_en = tuple_sets; 847d97b3072SJian Shen break; 848d97b3072SJian Shen case TCP_V6_FLOW: 849d97b3072SJian Shen req->ipv6_tcp_en = tuple_sets; 850d97b3072SJian Shen break; 851d97b3072SJian Shen case UDP_V4_FLOW: 852d97b3072SJian Shen req->ipv4_udp_en = tuple_sets; 853d97b3072SJian Shen break; 854d97b3072SJian Shen case UDP_V6_FLOW: 855d97b3072SJian Shen req->ipv6_udp_en = tuple_sets; 856d97b3072SJian Shen break; 857d97b3072SJian Shen case SCTP_V4_FLOW: 858d97b3072SJian Shen req->ipv4_sctp_en = tuple_sets; 859d97b3072SJian Shen break; 860d97b3072SJian Shen case SCTP_V6_FLOW: 861d97b3072SJian Shen if ((nfc->data & RXH_L4_B_0_1) || 862d97b3072SJian Shen (nfc->data & RXH_L4_B_2_3)) 863d97b3072SJian Shen return -EINVAL; 864d97b3072SJian Shen 865d97b3072SJian Shen req->ipv6_sctp_en = tuple_sets; 866d97b3072SJian Shen break; 867d97b3072SJian Shen case IPV4_FLOW: 868d97b3072SJian Shen req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 869d97b3072SJian Shen break; 870d97b3072SJian Shen case IPV6_FLOW: 871d97b3072SJian Shen req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 872d97b3072SJian Shen break; 873d97b3072SJian Shen default: 874d97b3072SJian Shen return -EINVAL; 875d97b3072SJian Shen } 876d97b3072SJian Shen 877d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 878d97b3072SJian Shen if (ret) { 879d97b3072SJian Shen dev_err(&hdev->pdev->dev, 880d97b3072SJian Shen "Set rss tuple fail, status = %d\n", ret); 881d97b3072SJian Shen return ret; 882d97b3072SJian Shen } 883d97b3072SJian Shen 884d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 885d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 886d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 887d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 888d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 889d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 890d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 891d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 892d97b3072SJian Shen return 0; 893d97b3072SJian Shen } 894d97b3072SJian Shen 895d97b3072SJian Shen static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 896d97b3072SJian Shen struct ethtool_rxnfc *nfc) 897d97b3072SJian Shen { 898d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 899d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 900d97b3072SJian Shen u8 tuple_sets; 901d97b3072SJian Shen 902d97b3072SJian Shen if (handle->pdev->revision == 0x20) 903d97b3072SJian Shen return -EOPNOTSUPP; 904d97b3072SJian Shen 905d97b3072SJian Shen nfc->data = 0; 906d97b3072SJian Shen 907d97b3072SJian Shen switch (nfc->flow_type) { 908d97b3072SJian Shen case TCP_V4_FLOW: 909d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 910d97b3072SJian Shen break; 911d97b3072SJian Shen case UDP_V4_FLOW: 912d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 913d97b3072SJian Shen break; 914d97b3072SJian Shen case TCP_V6_FLOW: 915d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 916d97b3072SJian Shen break; 917d97b3072SJian Shen case UDP_V6_FLOW: 918d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 919d97b3072SJian Shen break; 920d97b3072SJian Shen case SCTP_V4_FLOW: 921d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 922d97b3072SJian Shen break; 923d97b3072SJian Shen case SCTP_V6_FLOW: 924d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 925d97b3072SJian Shen break; 926d97b3072SJian Shen case IPV4_FLOW: 927d97b3072SJian Shen case IPV6_FLOW: 928d97b3072SJian Shen tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 929d97b3072SJian Shen break; 930d97b3072SJian Shen default: 931d97b3072SJian Shen return -EINVAL; 932d97b3072SJian Shen } 933d97b3072SJian Shen 934d97b3072SJian Shen if (!tuple_sets) 935d97b3072SJian Shen return 0; 936d97b3072SJian Shen 937d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_PORT_BIT) 938d97b3072SJian Shen nfc->data |= RXH_L4_B_2_3; 939d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_PORT_BIT) 940d97b3072SJian Shen nfc->data |= RXH_L4_B_0_1; 941d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_IP_BIT) 942d97b3072SJian Shen nfc->data |= RXH_IP_DST; 943d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_IP_BIT) 944d97b3072SJian Shen nfc->data |= RXH_IP_SRC; 945d97b3072SJian Shen 946d97b3072SJian Shen return 0; 947d97b3072SJian Shen } 948d97b3072SJian Shen 949d97b3072SJian Shen static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 950d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg) 951d97b3072SJian Shen { 952d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 953d97b3072SJian Shen struct hclgevf_desc desc; 954d97b3072SJian Shen int ret; 955d97b3072SJian Shen 956d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 957d97b3072SJian Shen 958d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 959d97b3072SJian Shen 960d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 961d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 962d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 963d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 964d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 965d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 966d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 967d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 968d97b3072SJian Shen 969d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 970d97b3072SJian Shen if (ret) 971d97b3072SJian Shen dev_err(&hdev->pdev->dev, 972d97b3072SJian Shen "Configure rss input fail, status = %d\n", ret); 973d97b3072SJian Shen return ret; 974d97b3072SJian Shen } 975d97b3072SJian Shen 976e2cb1decSSalil Mehta static int hclgevf_get_tc_size(struct hnae3_handle *handle) 977e2cb1decSSalil Mehta { 978e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 979e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 980e2cb1decSSalil Mehta 981e2cb1decSSalil Mehta return rss_cfg->rss_size; 982e2cb1decSSalil Mehta } 983e2cb1decSSalil Mehta 984e2cb1decSSalil Mehta static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 985b204bc74SPeng Li int vector_id, 986e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 987e2cb1decSSalil Mehta { 988e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 989e2cb1decSSalil Mehta struct hnae3_ring_chain_node *node; 990e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 991e2cb1decSSalil Mehta struct hclgevf_desc desc; 992b204bc74SPeng Li int i = 0; 993e2cb1decSSalil Mehta int status; 994e2cb1decSSalil Mehta u8 type; 995e2cb1decSSalil Mehta 996e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 997c09ba484SPeng Li type = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 998c09ba484SPeng Li HCLGE_MBX_UNMAP_RING_TO_VECTOR; 999e2cb1decSSalil Mehta 1000e2cb1decSSalil Mehta for (node = ring_chain; node; node = node->next) { 10015d02a58dSYunsheng Lin int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 10025d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 10035d02a58dSYunsheng Lin 10045d02a58dSYunsheng Lin if (i == 0) { 10055d02a58dSYunsheng Lin hclgevf_cmd_setup_basic_desc(&desc, 10065d02a58dSYunsheng Lin HCLGEVF_OPC_MBX_VF_TO_PF, 10075d02a58dSYunsheng Lin false); 10085d02a58dSYunsheng Lin req->msg[0] = type; 10095d02a58dSYunsheng Lin req->msg[1] = vector_id; 10105d02a58dSYunsheng Lin } 10115d02a58dSYunsheng Lin 10125d02a58dSYunsheng Lin req->msg[idx_offset] = 1013e4e87715SPeng Li hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 10145d02a58dSYunsheng Lin req->msg[idx_offset + 1] = node->tqp_index; 1015e4e87715SPeng Li req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 101679eee410SFuyun Liang HNAE3_RING_GL_IDX_M, 101779eee410SFuyun Liang HNAE3_RING_GL_IDX_S); 101879eee410SFuyun Liang 10195d02a58dSYunsheng Lin i++; 10205d02a58dSYunsheng Lin if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 10215d02a58dSYunsheng Lin HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 10225d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 10235d02a58dSYunsheng Lin !node->next) { 1024e2cb1decSSalil Mehta req->msg[2] = i; 1025e2cb1decSSalil Mehta 1026e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1027e2cb1decSSalil Mehta if (status) { 1028e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1029e2cb1decSSalil Mehta "Map TQP fail, status is %d.\n", 1030e2cb1decSSalil Mehta status); 1031e2cb1decSSalil Mehta return status; 1032e2cb1decSSalil Mehta } 1033e2cb1decSSalil Mehta i = 0; 1034e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 1035e2cb1decSSalil Mehta HCLGEVF_OPC_MBX_VF_TO_PF, 1036e2cb1decSSalil Mehta false); 1037e2cb1decSSalil Mehta req->msg[0] = type; 1038e2cb1decSSalil Mehta req->msg[1] = vector_id; 1039e2cb1decSSalil Mehta } 1040e2cb1decSSalil Mehta } 1041e2cb1decSSalil Mehta 1042e2cb1decSSalil Mehta return 0; 1043e2cb1decSSalil Mehta } 1044e2cb1decSSalil Mehta 1045e2cb1decSSalil Mehta static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1046e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1047e2cb1decSSalil Mehta { 1048b204bc74SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1049b204bc74SPeng Li int vector_id; 1050b204bc74SPeng Li 1051b204bc74SPeng Li vector_id = hclgevf_get_vector_index(hdev, vector); 1052b204bc74SPeng Li if (vector_id < 0) { 1053b204bc74SPeng Li dev_err(&handle->pdev->dev, 1054b204bc74SPeng Li "Get vector index fail. ret =%d\n", vector_id); 1055b204bc74SPeng Li return vector_id; 1056b204bc74SPeng Li } 1057b204bc74SPeng Li 1058b204bc74SPeng Li return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1059e2cb1decSSalil Mehta } 1060e2cb1decSSalil Mehta 1061e2cb1decSSalil Mehta static int hclgevf_unmap_ring_from_vector( 1062e2cb1decSSalil Mehta struct hnae3_handle *handle, 1063e2cb1decSSalil Mehta int vector, 1064e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1065e2cb1decSSalil Mehta { 1066e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1067e2cb1decSSalil Mehta int ret, vector_id; 1068e2cb1decSSalil Mehta 1069dea846e8SHuazhong Tan if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1070dea846e8SHuazhong Tan return 0; 1071dea846e8SHuazhong Tan 1072e2cb1decSSalil Mehta vector_id = hclgevf_get_vector_index(hdev, vector); 1073e2cb1decSSalil Mehta if (vector_id < 0) { 1074e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1075e2cb1decSSalil Mehta "Get vector index fail. ret =%d\n", vector_id); 1076e2cb1decSSalil Mehta return vector_id; 1077e2cb1decSSalil Mehta } 1078e2cb1decSSalil Mehta 1079b204bc74SPeng Li ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 10800d3e6631SYunsheng Lin if (ret) 1081e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1082e2cb1decSSalil Mehta "Unmap ring from vector fail. vector=%d, ret =%d\n", 1083e2cb1decSSalil Mehta vector_id, 1084e2cb1decSSalil Mehta ret); 10850d3e6631SYunsheng Lin 1086e2cb1decSSalil Mehta return ret; 1087e2cb1decSSalil Mehta } 1088e2cb1decSSalil Mehta 10890d3e6631SYunsheng Lin static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 10900d3e6631SYunsheng Lin { 10910d3e6631SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 109203718db9SYunsheng Lin int vector_id; 10930d3e6631SYunsheng Lin 109403718db9SYunsheng Lin vector_id = hclgevf_get_vector_index(hdev, vector); 109503718db9SYunsheng Lin if (vector_id < 0) { 109603718db9SYunsheng Lin dev_err(&handle->pdev->dev, 109703718db9SYunsheng Lin "hclgevf_put_vector get vector index fail. ret =%d\n", 109803718db9SYunsheng Lin vector_id); 109903718db9SYunsheng Lin return vector_id; 110003718db9SYunsheng Lin } 110103718db9SYunsheng Lin 110203718db9SYunsheng Lin hclgevf_free_vector(hdev, vector_id); 1103e2cb1decSSalil Mehta 1104e2cb1decSSalil Mehta return 0; 1105e2cb1decSSalil Mehta } 1106e2cb1decSSalil Mehta 11073b75c3dfSPeng Li static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1108f01f5559SJian Shen bool en_bc_pmc) 1109e2cb1decSSalil Mehta { 1110e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 1111e2cb1decSSalil Mehta struct hclgevf_desc desc; 1112f01f5559SJian Shen int ret; 1113e2cb1decSSalil Mehta 1114e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1115e2cb1decSSalil Mehta 1116e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 1117e2cb1decSSalil Mehta req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 1118f01f5559SJian Shen req->msg[1] = en_bc_pmc ? 1 : 0; 1119e2cb1decSSalil Mehta 1120f01f5559SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1121f01f5559SJian Shen if (ret) 1122e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1123f01f5559SJian Shen "Set promisc mode fail, status is %d.\n", ret); 1124e2cb1decSSalil Mehta 1125f01f5559SJian Shen return ret; 1126e2cb1decSSalil Mehta } 1127e2cb1decSSalil Mehta 1128f01f5559SJian Shen static int hclgevf_set_promisc_mode(struct hclgevf_dev *hdev, bool en_bc_pmc) 1129e2cb1decSSalil Mehta { 1130f01f5559SJian Shen return hclgevf_cmd_set_promisc_mode(hdev, en_bc_pmc); 1131e2cb1decSSalil Mehta } 1132e2cb1decSSalil Mehta 1133ebaf1908SWeihang Li static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, unsigned int tqp_id, 1134e2cb1decSSalil Mehta int stream_id, bool enable) 1135e2cb1decSSalil Mehta { 1136e2cb1decSSalil Mehta struct hclgevf_cfg_com_tqp_queue_cmd *req; 1137e2cb1decSSalil Mehta struct hclgevf_desc desc; 1138e2cb1decSSalil Mehta int status; 1139e2cb1decSSalil Mehta 1140e2cb1decSSalil Mehta req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1141e2cb1decSSalil Mehta 1142e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1143e2cb1decSSalil Mehta false); 1144e2cb1decSSalil Mehta req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1145e2cb1decSSalil Mehta req->stream_id = cpu_to_le16(stream_id); 1146ebaf1908SWeihang Li if (enable) 1147ebaf1908SWeihang Li req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 1148e2cb1decSSalil Mehta 1149e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1150e2cb1decSSalil Mehta if (status) 1151e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1152e2cb1decSSalil Mehta "TQP enable fail, status =%d.\n", status); 1153e2cb1decSSalil Mehta 1154e2cb1decSSalil Mehta return status; 1155e2cb1decSSalil Mehta } 1156e2cb1decSSalil Mehta 1157e2cb1decSSalil Mehta static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1158e2cb1decSSalil Mehta { 1159b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1160e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 1161e2cb1decSSalil Mehta int i; 1162e2cb1decSSalil Mehta 1163b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 1164b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1165e2cb1decSSalil Mehta memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1166e2cb1decSSalil Mehta } 1167e2cb1decSSalil Mehta } 1168e2cb1decSSalil Mehta 1169e2cb1decSSalil Mehta static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1170e2cb1decSSalil Mehta { 1171e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1172e2cb1decSSalil Mehta 1173e2cb1decSSalil Mehta ether_addr_copy(p, hdev->hw.mac.mac_addr); 1174e2cb1decSSalil Mehta } 1175e2cb1decSSalil Mehta 117659098055SFuyun Liang static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 117759098055SFuyun Liang bool is_first) 1178e2cb1decSSalil Mehta { 1179e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1180e2cb1decSSalil Mehta u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1181e2cb1decSSalil Mehta u8 *new_mac_addr = (u8 *)p; 1182e2cb1decSSalil Mehta u8 msg_data[ETH_ALEN * 2]; 118359098055SFuyun Liang u16 subcode; 1184e2cb1decSSalil Mehta int status; 1185e2cb1decSSalil Mehta 1186e2cb1decSSalil Mehta ether_addr_copy(msg_data, new_mac_addr); 1187e2cb1decSSalil Mehta ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 1188e2cb1decSSalil Mehta 118959098055SFuyun Liang subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 119059098055SFuyun Liang HCLGE_MBX_MAC_VLAN_UC_MODIFY; 119159098055SFuyun Liang 1192e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 119363cbf7a9SYufeng Mo subcode, msg_data, sizeof(msg_data), 11942097fdefSJian Shen true, NULL, 0); 1195e2cb1decSSalil Mehta if (!status) 1196e2cb1decSSalil Mehta ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1197e2cb1decSSalil Mehta 1198e2cb1decSSalil Mehta return status; 1199e2cb1decSSalil Mehta } 1200e2cb1decSSalil Mehta 1201e2cb1decSSalil Mehta static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1202e2cb1decSSalil Mehta const unsigned char *addr) 1203e2cb1decSSalil Mehta { 1204e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1205e2cb1decSSalil Mehta 1206e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1207e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_ADD, 1208e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1209e2cb1decSSalil Mehta } 1210e2cb1decSSalil Mehta 1211e2cb1decSSalil Mehta static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1212e2cb1decSSalil Mehta const unsigned char *addr) 1213e2cb1decSSalil Mehta { 1214e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1215e2cb1decSSalil Mehta 1216e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1217e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1218e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1219e2cb1decSSalil Mehta } 1220e2cb1decSSalil Mehta 1221e2cb1decSSalil Mehta static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1222e2cb1decSSalil Mehta const unsigned char *addr) 1223e2cb1decSSalil Mehta { 1224e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1225e2cb1decSSalil Mehta 1226e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1227e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_ADD, 1228e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1229e2cb1decSSalil Mehta } 1230e2cb1decSSalil Mehta 1231e2cb1decSSalil Mehta static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1232e2cb1decSSalil Mehta const unsigned char *addr) 1233e2cb1decSSalil Mehta { 1234e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1235e2cb1decSSalil Mehta 1236e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1237e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1238e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1239e2cb1decSSalil Mehta } 1240e2cb1decSSalil Mehta 1241e2cb1decSSalil Mehta static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1242e2cb1decSSalil Mehta __be16 proto, u16 vlan_id, 1243e2cb1decSSalil Mehta bool is_kill) 1244e2cb1decSSalil Mehta { 1245e2cb1decSSalil Mehta #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1246e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1247e2cb1decSSalil Mehta u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1248fe4144d4SJian Shen int ret; 1249e2cb1decSSalil Mehta 1250b37ce587SYufeng Mo if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1251e2cb1decSSalil Mehta return -EINVAL; 1252e2cb1decSSalil Mehta 1253e2cb1decSSalil Mehta if (proto != htons(ETH_P_8021Q)) 1254e2cb1decSSalil Mehta return -EPROTONOSUPPORT; 1255e2cb1decSSalil Mehta 1256fe4144d4SJian Shen /* When device is resetting, firmware is unable to handle 1257fe4144d4SJian Shen * mailbox. Just record the vlan id, and remove it after 1258fe4144d4SJian Shen * reset finished. 1259fe4144d4SJian Shen */ 1260fe4144d4SJian Shen if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) && is_kill) { 1261fe4144d4SJian Shen set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1262fe4144d4SJian Shen return -EBUSY; 1263fe4144d4SJian Shen } 1264fe4144d4SJian Shen 1265e2cb1decSSalil Mehta msg_data[0] = is_kill; 1266e2cb1decSSalil Mehta memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1267e2cb1decSSalil Mehta memcpy(&msg_data[3], &proto, sizeof(proto)); 1268fe4144d4SJian Shen ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1269e2cb1decSSalil Mehta HCLGE_MBX_VLAN_FILTER, msg_data, 1270e2cb1decSSalil Mehta HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 1271fe4144d4SJian Shen 1272fe4144d4SJian Shen /* When remove hw vlan filter failed, record the vlan id, 1273fe4144d4SJian Shen * and try to remove it from hw later, to be consistence 1274fe4144d4SJian Shen * with stack. 1275fe4144d4SJian Shen */ 1276fe4144d4SJian Shen if (is_kill && ret) 1277fe4144d4SJian Shen set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1278fe4144d4SJian Shen 1279fe4144d4SJian Shen return ret; 1280fe4144d4SJian Shen } 1281fe4144d4SJian Shen 1282fe4144d4SJian Shen static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1283fe4144d4SJian Shen { 1284fe4144d4SJian Shen #define HCLGEVF_MAX_SYNC_COUNT 60 1285fe4144d4SJian Shen struct hnae3_handle *handle = &hdev->nic; 1286fe4144d4SJian Shen int ret, sync_cnt = 0; 1287fe4144d4SJian Shen u16 vlan_id; 1288fe4144d4SJian Shen 1289fe4144d4SJian Shen vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1290fe4144d4SJian Shen while (vlan_id != VLAN_N_VID) { 1291fe4144d4SJian Shen ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1292fe4144d4SJian Shen vlan_id, true); 1293fe4144d4SJian Shen if (ret) 1294fe4144d4SJian Shen return; 1295fe4144d4SJian Shen 1296fe4144d4SJian Shen clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1297fe4144d4SJian Shen sync_cnt++; 1298fe4144d4SJian Shen if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1299fe4144d4SJian Shen return; 1300fe4144d4SJian Shen 1301fe4144d4SJian Shen vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1302fe4144d4SJian Shen } 1303e2cb1decSSalil Mehta } 1304e2cb1decSSalil Mehta 1305b2641e2aSYunsheng Lin static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1306b2641e2aSYunsheng Lin { 1307b2641e2aSYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1308b2641e2aSYunsheng Lin u8 msg_data; 1309b2641e2aSYunsheng Lin 1310b2641e2aSYunsheng Lin msg_data = enable ? 1 : 0; 1311b2641e2aSYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1312b2641e2aSYunsheng Lin HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1313b2641e2aSYunsheng Lin 1, false, NULL, 0); 1314b2641e2aSYunsheng Lin } 1315b2641e2aSYunsheng Lin 13167fa6be4fSHuazhong Tan static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1317e2cb1decSSalil Mehta { 1318e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1319e2cb1decSSalil Mehta u8 msg_data[2]; 13201a426f8bSPeng Li int ret; 1321e2cb1decSSalil Mehta 132263cbf7a9SYufeng Mo memcpy(msg_data, &queue_id, sizeof(queue_id)); 1323e2cb1decSSalil Mehta 13241a426f8bSPeng Li /* disable vf queue before send queue reset msg to PF */ 13251a426f8bSPeng Li ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 13261a426f8bSPeng Li if (ret) 13277fa6be4fSHuazhong Tan return ret; 13281a426f8bSPeng Li 13297fa6be4fSHuazhong Tan return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 133063cbf7a9SYufeng Mo sizeof(msg_data), true, NULL, 0); 1331e2cb1decSSalil Mehta } 1332e2cb1decSSalil Mehta 1333818f1675SYunsheng Lin static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1334818f1675SYunsheng Lin { 1335818f1675SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1336818f1675SYunsheng Lin 1337818f1675SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu, 1338818f1675SYunsheng Lin sizeof(new_mtu), true, NULL, 0); 1339818f1675SYunsheng Lin } 1340818f1675SYunsheng Lin 13416988eb2aSSalil Mehta static int hclgevf_notify_client(struct hclgevf_dev *hdev, 13426988eb2aSSalil Mehta enum hnae3_reset_notify_type type) 13436988eb2aSSalil Mehta { 13446988eb2aSSalil Mehta struct hnae3_client *client = hdev->nic_client; 13456988eb2aSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 13466a5f6fa3SHuazhong Tan int ret; 13476988eb2aSSalil Mehta 134825d1817cSHuazhong Tan if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 134925d1817cSHuazhong Tan !client) 135025d1817cSHuazhong Tan return 0; 135125d1817cSHuazhong Tan 13526988eb2aSSalil Mehta if (!client->ops->reset_notify) 13536988eb2aSSalil Mehta return -EOPNOTSUPP; 13546988eb2aSSalil Mehta 13556a5f6fa3SHuazhong Tan ret = client->ops->reset_notify(handle, type); 13566a5f6fa3SHuazhong Tan if (ret) 13576a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 13586a5f6fa3SHuazhong Tan type, ret); 13596a5f6fa3SHuazhong Tan 13606a5f6fa3SHuazhong Tan return ret; 13616988eb2aSSalil Mehta } 13626988eb2aSSalil Mehta 13636ff3cf07SHuazhong Tan static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 13646ff3cf07SHuazhong Tan { 13656ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 13666ff3cf07SHuazhong Tan 13676ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DONE, &hdev->flr_state); 13686ff3cf07SHuazhong Tan } 13696ff3cf07SHuazhong Tan 13706ff3cf07SHuazhong Tan static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev, 13716ff3cf07SHuazhong Tan unsigned long delay_us, 13726ff3cf07SHuazhong Tan unsigned long wait_cnt) 13736ff3cf07SHuazhong Tan { 13746ff3cf07SHuazhong Tan unsigned long cnt = 0; 13756ff3cf07SHuazhong Tan 13766ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) && 13776ff3cf07SHuazhong Tan cnt++ < wait_cnt) 13786ff3cf07SHuazhong Tan usleep_range(delay_us, delay_us * 2); 13796ff3cf07SHuazhong Tan 13806ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) { 13816ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 13826ff3cf07SHuazhong Tan "flr wait timeout\n"); 13836ff3cf07SHuazhong Tan return -ETIMEDOUT; 13846ff3cf07SHuazhong Tan } 13856ff3cf07SHuazhong Tan 13866ff3cf07SHuazhong Tan return 0; 13876ff3cf07SHuazhong Tan } 13886ff3cf07SHuazhong Tan 13896988eb2aSSalil Mehta static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 13906988eb2aSSalil Mehta { 1391aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_US 20000 1392aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_CNT 2000 1393aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1394aa5c4f17SHuazhong Tan (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1395aa5c4f17SHuazhong Tan 1396aa5c4f17SHuazhong Tan u32 val; 1397aa5c4f17SHuazhong Tan int ret; 13986988eb2aSSalil Mehta 13996ff3cf07SHuazhong Tan if (hdev->reset_type == HNAE3_FLR_RESET) 14006ff3cf07SHuazhong Tan return hclgevf_flr_poll_timeout(hdev, 14016ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_US, 14026ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_CNT); 140372e2fb07SHuazhong Tan else if (hdev->reset_type == HNAE3_VF_RESET) 140472e2fb07SHuazhong Tan ret = readl_poll_timeout(hdev->hw.io_base + 140572e2fb07SHuazhong Tan HCLGEVF_VF_RST_ING, val, 140672e2fb07SHuazhong Tan !(val & HCLGEVF_VF_RST_ING_BIT), 140772e2fb07SHuazhong Tan HCLGEVF_RESET_WAIT_US, 140872e2fb07SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 140972e2fb07SHuazhong Tan else 141072e2fb07SHuazhong Tan ret = readl_poll_timeout(hdev->hw.io_base + 141172e2fb07SHuazhong Tan HCLGEVF_RST_ING, val, 1412aa5c4f17SHuazhong Tan !(val & HCLGEVF_RST_ING_BITS), 1413aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_US, 1414aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 14156988eb2aSSalil Mehta 14166988eb2aSSalil Mehta /* hardware completion status should be available by this time */ 1417aa5c4f17SHuazhong Tan if (ret) { 1418aa5c4f17SHuazhong Tan dev_err(&hdev->pdev->dev, 14196988eb2aSSalil Mehta "could'nt get reset done status from h/w, timeout!\n"); 1420aa5c4f17SHuazhong Tan return ret; 14216988eb2aSSalil Mehta } 14226988eb2aSSalil Mehta 14236988eb2aSSalil Mehta /* we will wait a bit more to let reset of the stack to complete. This 14246988eb2aSSalil Mehta * might happen in case reset assertion was made by PF. Yes, this also 14256988eb2aSSalil Mehta * means we might end up waiting bit more even for VF reset. 14266988eb2aSSalil Mehta */ 14276988eb2aSSalil Mehta msleep(5000); 14286988eb2aSSalil Mehta 14296988eb2aSSalil Mehta return 0; 14306988eb2aSSalil Mehta } 14316988eb2aSSalil Mehta 14326b428b4fSHuazhong Tan static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable) 14336b428b4fSHuazhong Tan { 14346b428b4fSHuazhong Tan u32 reg_val; 14356b428b4fSHuazhong Tan 14366b428b4fSHuazhong Tan reg_val = hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG); 14376b428b4fSHuazhong Tan if (enable) 14386b428b4fSHuazhong Tan reg_val |= HCLGEVF_NIC_SW_RST_RDY; 14396b428b4fSHuazhong Tan else 14406b428b4fSHuazhong Tan reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; 14416b428b4fSHuazhong Tan 14426b428b4fSHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 14436b428b4fSHuazhong Tan reg_val); 14446b428b4fSHuazhong Tan } 14456b428b4fSHuazhong Tan 14466988eb2aSSalil Mehta static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 14476988eb2aSSalil Mehta { 14487a01c897SSalil Mehta int ret; 14497a01c897SSalil Mehta 14506988eb2aSSalil Mehta /* uninitialize the nic client */ 14516a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 14526a5f6fa3SHuazhong Tan if (ret) 14536a5f6fa3SHuazhong Tan return ret; 14546988eb2aSSalil Mehta 14557a01c897SSalil Mehta /* re-initialize the hclge device */ 14569c6f7085SHuazhong Tan ret = hclgevf_reset_hdev(hdev); 14577a01c897SSalil Mehta if (ret) { 14587a01c897SSalil Mehta dev_err(&hdev->pdev->dev, 14597a01c897SSalil Mehta "hclge device re-init failed, VF is disabled!\n"); 14607a01c897SSalil Mehta return ret; 14617a01c897SSalil Mehta } 14626988eb2aSSalil Mehta 14636988eb2aSSalil Mehta /* bring up the nic client again */ 14646a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 14656a5f6fa3SHuazhong Tan if (ret) 14666a5f6fa3SHuazhong Tan return ret; 14676988eb2aSSalil Mehta 14686b428b4fSHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT); 14696b428b4fSHuazhong Tan if (ret) 14706b428b4fSHuazhong Tan return ret; 14716b428b4fSHuazhong Tan 14726b428b4fSHuazhong Tan /* clear handshake status with IMP */ 14736b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, false); 14746b428b4fSHuazhong Tan 14756b428b4fSHuazhong Tan return 0; 14766988eb2aSSalil Mehta } 14776988eb2aSSalil Mehta 1478dea846e8SHuazhong Tan static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1479dea846e8SHuazhong Tan { 1480ada13ee3SHuazhong Tan #define HCLGEVF_RESET_SYNC_TIME 100 1481ada13ee3SHuazhong Tan 1482dea846e8SHuazhong Tan int ret = 0; 1483dea846e8SHuazhong Tan 1484dea846e8SHuazhong Tan switch (hdev->reset_type) { 1485dea846e8SHuazhong Tan case HNAE3_VF_FUNC_RESET: 1486dea846e8SHuazhong Tan ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1487dea846e8SHuazhong Tan 0, true, NULL, sizeof(u8)); 1488c88a6e7dSHuazhong Tan hdev->rst_stats.vf_func_rst_cnt++; 1489dea846e8SHuazhong Tan break; 14906ff3cf07SHuazhong Tan case HNAE3_FLR_RESET: 14916ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1492c88a6e7dSHuazhong Tan hdev->rst_stats.flr_rst_cnt++; 14936ff3cf07SHuazhong Tan break; 1494dea846e8SHuazhong Tan default: 1495dea846e8SHuazhong Tan break; 1496dea846e8SHuazhong Tan } 1497dea846e8SHuazhong Tan 1498ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1499ada13ee3SHuazhong Tan /* inform hardware that preparatory work is done */ 1500ada13ee3SHuazhong Tan msleep(HCLGEVF_RESET_SYNC_TIME); 15016b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, true); 1502dea846e8SHuazhong Tan dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1503dea846e8SHuazhong Tan hdev->reset_type, ret); 1504dea846e8SHuazhong Tan 1505dea846e8SHuazhong Tan return ret; 1506dea846e8SHuazhong Tan } 1507dea846e8SHuazhong Tan 1508bbe6540eSHuazhong Tan static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1509bbe6540eSHuazhong Tan { 15106b428b4fSHuazhong Tan /* recover handshake status with IMP when reset fail */ 15116b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, true); 1512bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt++; 1513bbe6540eSHuazhong Tan dev_err(&hdev->pdev->dev, "failed to reset VF(%d)\n", 1514bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt); 1515bbe6540eSHuazhong Tan 1516bbe6540eSHuazhong Tan if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1517bbe6540eSHuazhong Tan set_bit(hdev->reset_type, &hdev->reset_pending); 1518bbe6540eSHuazhong Tan 1519bbe6540eSHuazhong Tan if (hclgevf_is_reset_pending(hdev)) { 1520bbe6540eSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1521bbe6540eSHuazhong Tan hclgevf_reset_task_schedule(hdev); 1522bbe6540eSHuazhong Tan } 1523bbe6540eSHuazhong Tan } 1524bbe6540eSHuazhong Tan 15256988eb2aSSalil Mehta static int hclgevf_reset(struct hclgevf_dev *hdev) 15266988eb2aSSalil Mehta { 1527dea846e8SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 15286988eb2aSSalil Mehta int ret; 15296988eb2aSSalil Mehta 1530dea846e8SHuazhong Tan /* Initialize ae_dev reset status as well, in case enet layer wants to 1531dea846e8SHuazhong Tan * know if device is undergoing reset 1532dea846e8SHuazhong Tan */ 1533dea846e8SHuazhong Tan ae_dev->reset_type = hdev->reset_type; 1534c88a6e7dSHuazhong Tan hdev->rst_stats.rst_cnt++; 15356988eb2aSSalil Mehta rtnl_lock(); 15366988eb2aSSalil Mehta 15376988eb2aSSalil Mehta /* bring down the nic to stop any ongoing TX/RX */ 15386a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 15396a5f6fa3SHuazhong Tan if (ret) 15406a5f6fa3SHuazhong Tan goto err_reset_lock; 15416988eb2aSSalil Mehta 154229118ab9SHuazhong Tan rtnl_unlock(); 154329118ab9SHuazhong Tan 15446a5f6fa3SHuazhong Tan ret = hclgevf_reset_prepare_wait(hdev); 15456a5f6fa3SHuazhong Tan if (ret) 15466a5f6fa3SHuazhong Tan goto err_reset; 1547dea846e8SHuazhong Tan 15486988eb2aSSalil Mehta /* check if VF could successfully fetch the hardware reset completion 15496988eb2aSSalil Mehta * status from the hardware 15506988eb2aSSalil Mehta */ 15516988eb2aSSalil Mehta ret = hclgevf_reset_wait(hdev); 15526988eb2aSSalil Mehta if (ret) { 15536988eb2aSSalil Mehta /* can't do much in this situation, will disable VF */ 15546988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, 15556988eb2aSSalil Mehta "VF failed(=%d) to fetch H/W reset completion status\n", 15566988eb2aSSalil Mehta ret); 15576a5f6fa3SHuazhong Tan goto err_reset; 15586988eb2aSSalil Mehta } 15596988eb2aSSalil Mehta 1560c88a6e7dSHuazhong Tan hdev->rst_stats.hw_rst_done_cnt++; 1561c88a6e7dSHuazhong Tan 156229118ab9SHuazhong Tan rtnl_lock(); 156329118ab9SHuazhong Tan 15646988eb2aSSalil Mehta /* now, re-initialize the nic client and ae device*/ 15656988eb2aSSalil Mehta ret = hclgevf_reset_stack(hdev); 15666a5f6fa3SHuazhong Tan if (ret) { 15676988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 15686a5f6fa3SHuazhong Tan goto err_reset_lock; 15696a5f6fa3SHuazhong Tan } 15706988eb2aSSalil Mehta 15716988eb2aSSalil Mehta /* bring up the nic to enable TX/RX again */ 15726a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 15736a5f6fa3SHuazhong Tan if (ret) 15746a5f6fa3SHuazhong Tan goto err_reset_lock; 15756988eb2aSSalil Mehta 15766988eb2aSSalil Mehta rtnl_unlock(); 15776988eb2aSSalil Mehta 1578b644a8d4SHuazhong Tan hdev->last_reset_time = jiffies; 1579b644a8d4SHuazhong Tan ae_dev->reset_type = HNAE3_NONE_RESET; 1580c88a6e7dSHuazhong Tan hdev->rst_stats.rst_done_cnt++; 1581bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt = 0; 1582b644a8d4SHuazhong Tan 15836988eb2aSSalil Mehta return ret; 15846a5f6fa3SHuazhong Tan err_reset_lock: 15856a5f6fa3SHuazhong Tan rtnl_unlock(); 15866a5f6fa3SHuazhong Tan err_reset: 1587bbe6540eSHuazhong Tan hclgevf_reset_err_handle(hdev); 15886a5f6fa3SHuazhong Tan 15896a5f6fa3SHuazhong Tan return ret; 15906988eb2aSSalil Mehta } 15916988eb2aSSalil Mehta 1592720bd583SHuazhong Tan static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1593720bd583SHuazhong Tan unsigned long *addr) 1594720bd583SHuazhong Tan { 1595720bd583SHuazhong Tan enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1596720bd583SHuazhong Tan 1597dea846e8SHuazhong Tan /* return the highest priority reset level amongst all */ 1598b90fcc5bSHuazhong Tan if (test_bit(HNAE3_VF_RESET, addr)) { 1599b90fcc5bSHuazhong Tan rst_level = HNAE3_VF_RESET; 1600b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_RESET, addr); 1601b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1602b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1603b90fcc5bSHuazhong Tan } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1604dea846e8SHuazhong Tan rst_level = HNAE3_VF_FULL_RESET; 1605dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FULL_RESET, addr); 1606dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1607aa5c4f17SHuazhong Tan } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1608aa5c4f17SHuazhong Tan rst_level = HNAE3_VF_PF_FUNC_RESET; 1609aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1610aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1611dea846e8SHuazhong Tan } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1612dea846e8SHuazhong Tan rst_level = HNAE3_VF_FUNC_RESET; 1613dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 16146ff3cf07SHuazhong Tan } else if (test_bit(HNAE3_FLR_RESET, addr)) { 16156ff3cf07SHuazhong Tan rst_level = HNAE3_FLR_RESET; 16166ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_RESET, addr); 1617720bd583SHuazhong Tan } 1618720bd583SHuazhong Tan 1619720bd583SHuazhong Tan return rst_level; 1620720bd583SHuazhong Tan } 1621720bd583SHuazhong Tan 16226ae4e733SShiju Jose static void hclgevf_reset_event(struct pci_dev *pdev, 16236ae4e733SShiju Jose struct hnae3_handle *handle) 16246d4c3981SSalil Mehta { 16256ff3cf07SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 16266ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 16276d4c3981SSalil Mehta 16286d4c3981SSalil Mehta dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 16296d4c3981SSalil Mehta 16306ff3cf07SHuazhong Tan if (hdev->default_reset_request) 16310742ed7cSHuazhong Tan hdev->reset_level = 1632720bd583SHuazhong Tan hclgevf_get_reset_level(hdev, 1633720bd583SHuazhong Tan &hdev->default_reset_request); 1634720bd583SHuazhong Tan else 1635dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 16366d4c3981SSalil Mehta 1637436667d2SSalil Mehta /* reset of this VF requested */ 1638436667d2SSalil Mehta set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1639436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 16406d4c3981SSalil Mehta 16410742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 16426d4c3981SSalil Mehta } 16436d4c3981SSalil Mehta 1644720bd583SHuazhong Tan static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1645720bd583SHuazhong Tan enum hnae3_reset_type rst_type) 1646720bd583SHuazhong Tan { 1647720bd583SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1648720bd583SHuazhong Tan 1649720bd583SHuazhong Tan set_bit(rst_type, &hdev->default_reset_request); 1650720bd583SHuazhong Tan } 1651720bd583SHuazhong Tan 16526ff3cf07SHuazhong Tan static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 16536ff3cf07SHuazhong Tan { 16546ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_MS 100 16556ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_CNT 50 16566ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 16576ff3cf07SHuazhong Tan int cnt = 0; 16586ff3cf07SHuazhong Tan 16596ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 16606ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DONE, &hdev->flr_state); 16616ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request); 16626ff3cf07SHuazhong Tan hclgevf_reset_event(hdev->pdev, NULL); 16636ff3cf07SHuazhong Tan 16646ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) && 16656ff3cf07SHuazhong Tan cnt++ < HCLGEVF_FLR_WAIT_CNT) 16666ff3cf07SHuazhong Tan msleep(HCLGEVF_FLR_WAIT_MS); 16676ff3cf07SHuazhong Tan 16686ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state)) 16696ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 16706ff3cf07SHuazhong Tan "flr wait down timeout: %d\n", cnt); 16716ff3cf07SHuazhong Tan } 16726ff3cf07SHuazhong Tan 1673e2cb1decSSalil Mehta static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1674e2cb1decSSalil Mehta { 1675e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1676e2cb1decSSalil Mehta 1677e2cb1decSSalil Mehta return hdev->fw_version; 1678e2cb1decSSalil Mehta } 1679e2cb1decSSalil Mehta 1680e2cb1decSSalil Mehta static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1681e2cb1decSSalil Mehta { 1682e2cb1decSSalil Mehta struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1683e2cb1decSSalil Mehta 1684e2cb1decSSalil Mehta vector->vector_irq = pci_irq_vector(hdev->pdev, 1685e2cb1decSSalil Mehta HCLGEVF_MISC_VECTOR_NUM); 1686e2cb1decSSalil Mehta vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1687e2cb1decSSalil Mehta /* vector status always valid for Vector 0 */ 1688e2cb1decSSalil Mehta hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1689e2cb1decSSalil Mehta hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1690e2cb1decSSalil Mehta 1691e2cb1decSSalil Mehta hdev->num_msi_left -= 1; 1692e2cb1decSSalil Mehta hdev->num_msi_used += 1; 1693e2cb1decSSalil Mehta } 1694e2cb1decSSalil Mehta 169535a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 169635a1e503SSalil Mehta { 1697acfc3d55SHuazhong Tan if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) && 1698acfc3d55SHuazhong Tan !test_bit(HCLGEVF_STATE_REMOVING, &hdev->state)) { 169935a1e503SSalil Mehta set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 170035a1e503SSalil Mehta schedule_work(&hdev->rst_service_task); 170135a1e503SSalil Mehta } 170235a1e503SSalil Mehta } 170335a1e503SSalil Mehta 170407a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1705e2cb1decSSalil Mehta { 170607a0556aSSalil Mehta if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) && 170707a0556aSSalil Mehta !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) { 170807a0556aSSalil Mehta set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1709e2cb1decSSalil Mehta schedule_work(&hdev->mbx_service_task); 1710e2cb1decSSalil Mehta } 171107a0556aSSalil Mehta } 1712e2cb1decSSalil Mehta 1713e2cb1decSSalil Mehta static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 1714e2cb1decSSalil Mehta { 1715e2cb1decSSalil Mehta if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 1716e2cb1decSSalil Mehta !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 1717e2cb1decSSalil Mehta schedule_work(&hdev->service_task); 1718e2cb1decSSalil Mehta } 1719e2cb1decSSalil Mehta 1720436667d2SSalil Mehta static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev) 1721436667d2SSalil Mehta { 172207a0556aSSalil Mehta /* if we have any pending mailbox event then schedule the mbx task */ 172307a0556aSSalil Mehta if (hdev->mbx_event_pending) 172407a0556aSSalil Mehta hclgevf_mbx_task_schedule(hdev); 172507a0556aSSalil Mehta 1726436667d2SSalil Mehta if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state)) 1727436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 1728436667d2SSalil Mehta } 1729436667d2SSalil Mehta 1730e2cb1decSSalil Mehta static void hclgevf_service_timer(struct timer_list *t) 1731e2cb1decSSalil Mehta { 1732e2cb1decSSalil Mehta struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 1733e2cb1decSSalil Mehta 1734b37ce587SYufeng Mo mod_timer(&hdev->service_timer, jiffies + 1735b37ce587SYufeng Mo HCLGEVF_GENERAL_TASK_INTERVAL * HZ); 1736e2cb1decSSalil Mehta 1737db01afebSliuzhongzhu hdev->stats_timer++; 1738e2cb1decSSalil Mehta hclgevf_task_schedule(hdev); 1739e2cb1decSSalil Mehta } 1740e2cb1decSSalil Mehta 174135a1e503SSalil Mehta static void hclgevf_reset_service_task(struct work_struct *work) 174235a1e503SSalil Mehta { 174335a1e503SSalil Mehta struct hclgevf_dev *hdev = 174435a1e503SSalil Mehta container_of(work, struct hclgevf_dev, rst_service_task); 1745a8dedb65SSalil Mehta int ret; 174635a1e503SSalil Mehta 174735a1e503SSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 174835a1e503SSalil Mehta return; 174935a1e503SSalil Mehta 175035a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 175135a1e503SSalil Mehta 1752436667d2SSalil Mehta if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1753436667d2SSalil Mehta &hdev->reset_state)) { 1754436667d2SSalil Mehta /* PF has initmated that it is about to reset the hardware. 17559b2f3477SWeihang Li * We now have to poll & check if hardware has actually 17569b2f3477SWeihang Li * completed the reset sequence. On hardware reset completion, 17579b2f3477SWeihang Li * VF needs to reset the client and ae device. 175835a1e503SSalil Mehta */ 1759436667d2SSalil Mehta hdev->reset_attempts = 0; 1760436667d2SSalil Mehta 1761dea846e8SHuazhong Tan hdev->last_reset_time = jiffies; 1762dea846e8SHuazhong Tan while ((hdev->reset_type = 1763dea846e8SHuazhong Tan hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 1764dea846e8SHuazhong Tan != HNAE3_NONE_RESET) { 17656988eb2aSSalil Mehta ret = hclgevf_reset(hdev); 17666988eb2aSSalil Mehta if (ret) 1767dea846e8SHuazhong Tan dev_err(&hdev->pdev->dev, 1768dea846e8SHuazhong Tan "VF stack reset failed %d.\n", ret); 1769dea846e8SHuazhong Tan } 1770436667d2SSalil Mehta } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1771436667d2SSalil Mehta &hdev->reset_state)) { 1772436667d2SSalil Mehta /* we could be here when either of below happens: 17739b2f3477SWeihang Li * 1. reset was initiated due to watchdog timeout caused by 1774436667d2SSalil Mehta * a. IMP was earlier reset and our TX got choked down and 1775436667d2SSalil Mehta * which resulted in watchdog reacting and inducing VF 1776436667d2SSalil Mehta * reset. This also means our cmdq would be unreliable. 1777436667d2SSalil Mehta * b. problem in TX due to other lower layer(example link 1778436667d2SSalil Mehta * layer not functioning properly etc.) 1779436667d2SSalil Mehta * 2. VF reset might have been initiated due to some config 1780436667d2SSalil Mehta * change. 1781436667d2SSalil Mehta * 1782436667d2SSalil Mehta * NOTE: Theres no clear way to detect above cases than to react 1783436667d2SSalil Mehta * to the response of PF for this reset request. PF will ack the 1784436667d2SSalil Mehta * 1b and 2. cases but we will not get any intimation about 1a 1785436667d2SSalil Mehta * from PF as cmdq would be in unreliable state i.e. mailbox 1786436667d2SSalil Mehta * communication between PF and VF would be broken. 1787436667d2SSalil Mehta */ 1788436667d2SSalil Mehta 1789436667d2SSalil Mehta /* if we are never geting into pending state it means either: 1790436667d2SSalil Mehta * 1. PF is not receiving our request which could be due to IMP 1791436667d2SSalil Mehta * reset 1792436667d2SSalil Mehta * 2. PF is screwed 1793436667d2SSalil Mehta * We cannot do much for 2. but to check first we can try reset 1794436667d2SSalil Mehta * our PCIe + stack and see if it alleviates the problem. 1795436667d2SSalil Mehta */ 1796436667d2SSalil Mehta if (hdev->reset_attempts > 3) { 1797436667d2SSalil Mehta /* prepare for full reset of stack + pcie interface */ 1798dea846e8SHuazhong Tan set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1799436667d2SSalil Mehta 1800436667d2SSalil Mehta /* "defer" schedule the reset task again */ 1801436667d2SSalil Mehta set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1802436667d2SSalil Mehta } else { 1803436667d2SSalil Mehta hdev->reset_attempts++; 1804436667d2SSalil Mehta 1805dea846e8SHuazhong Tan set_bit(hdev->reset_level, &hdev->reset_pending); 1806dea846e8SHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1807436667d2SSalil Mehta } 1808dea846e8SHuazhong Tan hclgevf_reset_task_schedule(hdev); 1809436667d2SSalil Mehta } 181035a1e503SSalil Mehta 181135a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 181235a1e503SSalil Mehta } 181335a1e503SSalil Mehta 1814e2cb1decSSalil Mehta static void hclgevf_mailbox_service_task(struct work_struct *work) 1815e2cb1decSSalil Mehta { 1816e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1817e2cb1decSSalil Mehta 1818e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 1819e2cb1decSSalil Mehta 1820e2cb1decSSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1821e2cb1decSSalil Mehta return; 1822e2cb1decSSalil Mehta 1823e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1824e2cb1decSSalil Mehta 182507a0556aSSalil Mehta hclgevf_mbx_async_handler(hdev); 1826e2cb1decSSalil Mehta 1827e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1828e2cb1decSSalil Mehta } 1829e2cb1decSSalil Mehta 1830a6d818e3SYunsheng Lin static void hclgevf_keep_alive_timer(struct timer_list *t) 1831a6d818e3SYunsheng Lin { 1832a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = from_timer(hdev, t, keep_alive_timer); 1833a6d818e3SYunsheng Lin 1834a6d818e3SYunsheng Lin schedule_work(&hdev->keep_alive_task); 1835b37ce587SYufeng Mo mod_timer(&hdev->keep_alive_timer, jiffies + 1836b37ce587SYufeng Mo HCLGEVF_KEEP_ALIVE_TASK_INTERVAL * HZ); 1837a6d818e3SYunsheng Lin } 1838a6d818e3SYunsheng Lin 1839a6d818e3SYunsheng Lin static void hclgevf_keep_alive_task(struct work_struct *work) 1840a6d818e3SYunsheng Lin { 1841a6d818e3SYunsheng Lin struct hclgevf_dev *hdev; 1842a6d818e3SYunsheng Lin u8 respmsg; 1843a6d818e3SYunsheng Lin int ret; 1844a6d818e3SYunsheng Lin 1845a6d818e3SYunsheng Lin hdev = container_of(work, struct hclgevf_dev, keep_alive_task); 1846c59a85c0SJian Shen 18471416d333SHuazhong Tan if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 1848c59a85c0SJian Shen return; 1849c59a85c0SJian Shen 1850a6d818e3SYunsheng Lin ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL, 185163cbf7a9SYufeng Mo 0, false, &respmsg, sizeof(respmsg)); 1852a6d818e3SYunsheng Lin if (ret) 1853a6d818e3SYunsheng Lin dev_err(&hdev->pdev->dev, 1854a6d818e3SYunsheng Lin "VF sends keep alive cmd failed(=%d)\n", ret); 1855a6d818e3SYunsheng Lin } 1856a6d818e3SYunsheng Lin 1857e2cb1decSSalil Mehta static void hclgevf_service_task(struct work_struct *work) 1858e2cb1decSSalil Mehta { 1859db01afebSliuzhongzhu struct hnae3_handle *handle; 1860e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1861e2cb1decSSalil Mehta 1862e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, service_task); 1863db01afebSliuzhongzhu handle = &hdev->nic; 1864db01afebSliuzhongzhu 1865db01afebSliuzhongzhu if (hdev->stats_timer >= HCLGEVF_STATS_TIMER_INTERVAL) { 1866db01afebSliuzhongzhu hclgevf_tqps_update_stats(handle); 1867db01afebSliuzhongzhu hdev->stats_timer = 0; 1868db01afebSliuzhongzhu } 1869e2cb1decSSalil Mehta 1870e2cb1decSSalil Mehta /* request the link status from the PF. PF would be able to tell VF 1871e2cb1decSSalil Mehta * about such updates in future so we might remove this later 1872e2cb1decSSalil Mehta */ 1873e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1874e2cb1decSSalil Mehta 18759194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 18769194d18bSliuzhongzhu 1877fe4144d4SJian Shen hclgevf_sync_vlan_filter(hdev); 1878fe4144d4SJian Shen 1879436667d2SSalil Mehta hclgevf_deferred_task_schedule(hdev); 1880436667d2SSalil Mehta 1881e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1882e2cb1decSSalil Mehta } 1883e2cb1decSSalil Mehta 1884e2cb1decSSalil Mehta static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1885e2cb1decSSalil Mehta { 1886e2cb1decSSalil Mehta hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1887e2cb1decSSalil Mehta } 1888e2cb1decSSalil Mehta 1889b90fcc5bSHuazhong Tan static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1890b90fcc5bSHuazhong Tan u32 *clearval) 1891e2cb1decSSalil Mehta { 189272e2fb07SHuazhong Tan u32 val, cmdq_src_reg, rst_ing_reg; 1893e2cb1decSSalil Mehta 1894e2cb1decSSalil Mehta /* fetch the events from their corresponding regs */ 1895e2cb1decSSalil Mehta cmdq_src_reg = hclgevf_read_dev(&hdev->hw, 1896e2cb1decSSalil Mehta HCLGEVF_VECTOR0_CMDQ_SRC_REG); 1897e2cb1decSSalil Mehta 1898b90fcc5bSHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_src_reg) { 1899b90fcc5bSHuazhong Tan rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1900b90fcc5bSHuazhong Tan dev_info(&hdev->pdev->dev, 1901b90fcc5bSHuazhong Tan "receive reset interrupt 0x%x!\n", rst_ing_reg); 1902b90fcc5bSHuazhong Tan set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1903b90fcc5bSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1904ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1905b90fcc5bSHuazhong Tan cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RST_INT_B); 1906b90fcc5bSHuazhong Tan *clearval = cmdq_src_reg; 1907c88a6e7dSHuazhong Tan hdev->rst_stats.vf_rst_cnt++; 190872e2fb07SHuazhong Tan /* set up VF hardware reset status, its PF will clear 190972e2fb07SHuazhong Tan * this status when PF has initialized done. 191072e2fb07SHuazhong Tan */ 191172e2fb07SHuazhong Tan val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING); 191272e2fb07SHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING, 191372e2fb07SHuazhong Tan val | HCLGEVF_VF_RST_ING_BIT); 1914b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_RST; 1915b90fcc5bSHuazhong Tan } 1916b90fcc5bSHuazhong Tan 1917e2cb1decSSalil Mehta /* check for vector0 mailbox(=CMDQ RX) event source */ 1918e2cb1decSSalil Mehta if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 1919e2cb1decSSalil Mehta cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1920e2cb1decSSalil Mehta *clearval = cmdq_src_reg; 1921b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_MBX; 1922e2cb1decSSalil Mehta } 1923e2cb1decSSalil Mehta 1924e2cb1decSSalil Mehta dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 1925e2cb1decSSalil Mehta 1926b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_OTHER; 1927e2cb1decSSalil Mehta } 1928e2cb1decSSalil Mehta 1929e2cb1decSSalil Mehta static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1930e2cb1decSSalil Mehta { 1931e2cb1decSSalil Mehta writel(en ? 1 : 0, vector->addr); 1932e2cb1decSSalil Mehta } 1933e2cb1decSSalil Mehta 1934e2cb1decSSalil Mehta static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1935e2cb1decSSalil Mehta { 1936b90fcc5bSHuazhong Tan enum hclgevf_evt_cause event_cause; 1937e2cb1decSSalil Mehta struct hclgevf_dev *hdev = data; 1938e2cb1decSSalil Mehta u32 clearval; 1939e2cb1decSSalil Mehta 1940e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 1941b90fcc5bSHuazhong Tan event_cause = hclgevf_check_evt_cause(hdev, &clearval); 1942e2cb1decSSalil Mehta 1943b90fcc5bSHuazhong Tan switch (event_cause) { 1944b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_RST: 1945b90fcc5bSHuazhong Tan hclgevf_reset_task_schedule(hdev); 1946b90fcc5bSHuazhong Tan break; 1947b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_MBX: 194807a0556aSSalil Mehta hclgevf_mbx_handler(hdev); 1949b90fcc5bSHuazhong Tan break; 1950b90fcc5bSHuazhong Tan default: 1951b90fcc5bSHuazhong Tan break; 1952b90fcc5bSHuazhong Tan } 1953e2cb1decSSalil Mehta 1954b90fcc5bSHuazhong Tan if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 1955e2cb1decSSalil Mehta hclgevf_clear_event_cause(hdev, clearval); 1956e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 1957b90fcc5bSHuazhong Tan } 1958e2cb1decSSalil Mehta 1959e2cb1decSSalil Mehta return IRQ_HANDLED; 1960e2cb1decSSalil Mehta } 1961e2cb1decSSalil Mehta 1962e2cb1decSSalil Mehta static int hclgevf_configure(struct hclgevf_dev *hdev) 1963e2cb1decSSalil Mehta { 1964e2cb1decSSalil Mehta int ret; 1965e2cb1decSSalil Mehta 196692f11ea1SJian Shen /* get current port based vlan state from PF */ 196792f11ea1SJian Shen ret = hclgevf_get_port_base_vlan_filter_state(hdev); 196892f11ea1SJian Shen if (ret) 196992f11ea1SJian Shen return ret; 197092f11ea1SJian Shen 1971e2cb1decSSalil Mehta /* get queue configuration from PF */ 19726cee6fc3SJian Shen ret = hclgevf_get_queue_info(hdev); 1973e2cb1decSSalil Mehta if (ret) 1974e2cb1decSSalil Mehta return ret; 1975c0425944SPeng Li 1976c0425944SPeng Li /* get queue depth info from PF */ 1977c0425944SPeng Li ret = hclgevf_get_queue_depth(hdev); 1978c0425944SPeng Li if (ret) 1979c0425944SPeng Li return ret; 1980c0425944SPeng Li 19819c3e7130Sliuzhongzhu ret = hclgevf_get_pf_media_type(hdev); 19829c3e7130Sliuzhongzhu if (ret) 19839c3e7130Sliuzhongzhu return ret; 19849c3e7130Sliuzhongzhu 1985e2cb1decSSalil Mehta /* get tc configuration from PF */ 1986e2cb1decSSalil Mehta return hclgevf_get_tc_info(hdev); 1987e2cb1decSSalil Mehta } 1988e2cb1decSSalil Mehta 19897a01c897SSalil Mehta static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 19907a01c897SSalil Mehta { 19917a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 19921154bb26SPeng Li struct hclgevf_dev *hdev; 19937a01c897SSalil Mehta 19947a01c897SSalil Mehta hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 19957a01c897SSalil Mehta if (!hdev) 19967a01c897SSalil Mehta return -ENOMEM; 19977a01c897SSalil Mehta 19987a01c897SSalil Mehta hdev->pdev = pdev; 19997a01c897SSalil Mehta hdev->ae_dev = ae_dev; 20007a01c897SSalil Mehta ae_dev->priv = hdev; 20017a01c897SSalil Mehta 20027a01c897SSalil Mehta return 0; 20037a01c897SSalil Mehta } 20047a01c897SSalil Mehta 2005e2cb1decSSalil Mehta static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 2006e2cb1decSSalil Mehta { 2007e2cb1decSSalil Mehta struct hnae3_handle *roce = &hdev->roce; 2008e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 2009e2cb1decSSalil Mehta 201007acf909SJian Shen roce->rinfo.num_vectors = hdev->num_roce_msix; 2011e2cb1decSSalil Mehta 2012e2cb1decSSalil Mehta if (hdev->num_msi_left < roce->rinfo.num_vectors || 2013e2cb1decSSalil Mehta hdev->num_msi_left == 0) 2014e2cb1decSSalil Mehta return -EINVAL; 2015e2cb1decSSalil Mehta 201607acf909SJian Shen roce->rinfo.base_vector = hdev->roce_base_vector; 2017e2cb1decSSalil Mehta 2018e2cb1decSSalil Mehta roce->rinfo.netdev = nic->kinfo.netdev; 2019e2cb1decSSalil Mehta roce->rinfo.roce_io_base = hdev->hw.io_base; 2020e2cb1decSSalil Mehta 2021e2cb1decSSalil Mehta roce->pdev = nic->pdev; 2022e2cb1decSSalil Mehta roce->ae_algo = nic->ae_algo; 2023e2cb1decSSalil Mehta roce->numa_node_mask = nic->numa_node_mask; 2024e2cb1decSSalil Mehta 2025e2cb1decSSalil Mehta return 0; 2026e2cb1decSSalil Mehta } 2027e2cb1decSSalil Mehta 2028b26a6feaSPeng Li static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 2029b26a6feaSPeng Li { 2030b26a6feaSPeng Li struct hclgevf_cfg_gro_status_cmd *req; 2031b26a6feaSPeng Li struct hclgevf_desc desc; 2032b26a6feaSPeng Li int ret; 2033b26a6feaSPeng Li 2034b26a6feaSPeng Li if (!hnae3_dev_gro_supported(hdev)) 2035b26a6feaSPeng Li return 0; 2036b26a6feaSPeng Li 2037b26a6feaSPeng Li hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 2038b26a6feaSPeng Li false); 2039b26a6feaSPeng Li req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2040b26a6feaSPeng Li 2041b26a6feaSPeng Li req->gro_en = cpu_to_le16(en ? 1 : 0); 2042b26a6feaSPeng Li 2043b26a6feaSPeng Li ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2044b26a6feaSPeng Li if (ret) 2045b26a6feaSPeng Li dev_err(&hdev->pdev->dev, 2046b26a6feaSPeng Li "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2047b26a6feaSPeng Li 2048b26a6feaSPeng Li return ret; 2049b26a6feaSPeng Li } 2050b26a6feaSPeng Li 2051e2cb1decSSalil Mehta static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2052e2cb1decSSalil Mehta { 2053e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2054e2cb1decSSalil Mehta int i, ret; 2055e2cb1decSSalil Mehta 2056e2cb1decSSalil Mehta rss_cfg->rss_size = hdev->rss_size_max; 2057e2cb1decSSalil Mehta 2058374ad291SJian Shen if (hdev->pdev->revision >= 0x21) { 2059472d7eceSJian Shen rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 2060472d7eceSJian Shen memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 2061374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 2062374ad291SJian Shen 2063374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 2064374ad291SJian Shen rss_cfg->rss_hash_key); 2065374ad291SJian Shen if (ret) 2066374ad291SJian Shen return ret; 2067d97b3072SJian Shen 2068d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = 2069d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2070d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = 2071d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2072d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = 2073d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2074d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = 2075d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2076d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = 2077d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2078d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = 2079d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2080d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = 2081d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2082d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = 2083d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2084d97b3072SJian Shen 2085d97b3072SJian Shen ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 2086d97b3072SJian Shen if (ret) 2087d97b3072SJian Shen return ret; 2088d97b3072SJian Shen 2089374ad291SJian Shen } 2090374ad291SJian Shen 20919b2f3477SWeihang Li /* Initialize RSS indirect table */ 2092e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 2093e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max; 2094e2cb1decSSalil Mehta 2095e2cb1decSSalil Mehta ret = hclgevf_set_rss_indir_table(hdev); 2096e2cb1decSSalil Mehta if (ret) 2097e2cb1decSSalil Mehta return ret; 2098e2cb1decSSalil Mehta 2099e2cb1decSSalil Mehta return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max); 2100e2cb1decSSalil Mehta } 2101e2cb1decSSalil Mehta 2102e2cb1decSSalil Mehta static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2103e2cb1decSSalil Mehta { 2104e2cb1decSSalil Mehta return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2105e2cb1decSSalil Mehta false); 2106e2cb1decSSalil Mehta } 2107e2cb1decSSalil Mehta 21088cdb992fSJian Shen static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 21098cdb992fSJian Shen { 21108cdb992fSJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 21118cdb992fSJian Shen 21128cdb992fSJian Shen if (enable) { 21138cdb992fSJian Shen mod_timer(&hdev->service_timer, jiffies + HZ); 21148cdb992fSJian Shen } else { 21158cdb992fSJian Shen del_timer_sync(&hdev->service_timer); 21168cdb992fSJian Shen cancel_work_sync(&hdev->service_task); 21178cdb992fSJian Shen clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 21188cdb992fSJian Shen } 21198cdb992fSJian Shen } 21208cdb992fSJian Shen 2121e2cb1decSSalil Mehta static int hclgevf_ae_start(struct hnae3_handle *handle) 2122e2cb1decSSalil Mehta { 2123e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2124e2cb1decSSalil Mehta 2125e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 2126e2cb1decSSalil Mehta 2127e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 2128e2cb1decSSalil Mehta 21299194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 21309194d18bSliuzhongzhu 2131e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2132e2cb1decSSalil Mehta 2133e2cb1decSSalil Mehta return 0; 2134e2cb1decSSalil Mehta } 2135e2cb1decSSalil Mehta 2136e2cb1decSSalil Mehta static void hclgevf_ae_stop(struct hnae3_handle *handle) 2137e2cb1decSSalil Mehta { 2138e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 213939cfbc9cSHuazhong Tan int i; 2140e2cb1decSSalil Mehta 21412f7e4896SFuyun Liang set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 21422f7e4896SFuyun Liang 2143146e92c1SHuazhong Tan if (hdev->reset_type != HNAE3_VF_RESET) 214439cfbc9cSHuazhong Tan for (i = 0; i < handle->kinfo.num_tqps; i++) 2145146e92c1SHuazhong Tan if (hclgevf_reset_tqp(handle, i)) 2146146e92c1SHuazhong Tan break; 214739cfbc9cSHuazhong Tan 2148e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 21498cc6c1f7SFuyun Liang hclgevf_update_link_status(hdev, 0); 2150e2cb1decSSalil Mehta } 2151e2cb1decSSalil Mehta 2152a6d818e3SYunsheng Lin static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2153a6d818e3SYunsheng Lin { 2154a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2155a6d818e3SYunsheng Lin u8 msg_data; 2156a6d818e3SYunsheng Lin 2157a6d818e3SYunsheng Lin msg_data = alive ? 1 : 0; 2158a6d818e3SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE, 2159a6d818e3SYunsheng Lin 0, &msg_data, 1, false, NULL, 0); 2160a6d818e3SYunsheng Lin } 2161a6d818e3SYunsheng Lin 2162a6d818e3SYunsheng Lin static int hclgevf_client_start(struct hnae3_handle *handle) 2163a6d818e3SYunsheng Lin { 2164a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2165e233516eSHuazhong Tan int ret; 2166e233516eSHuazhong Tan 2167e233516eSHuazhong Tan ret = hclgevf_set_alive(handle, true); 2168e233516eSHuazhong Tan if (ret) 2169e233516eSHuazhong Tan return ret; 2170a6d818e3SYunsheng Lin 2171b37ce587SYufeng Mo mod_timer(&hdev->keep_alive_timer, jiffies + 2172b37ce587SYufeng Mo HCLGEVF_KEEP_ALIVE_TASK_INTERVAL * HZ); 2173e233516eSHuazhong Tan 2174e233516eSHuazhong Tan return 0; 2175a6d818e3SYunsheng Lin } 2176a6d818e3SYunsheng Lin 2177a6d818e3SYunsheng Lin static void hclgevf_client_stop(struct hnae3_handle *handle) 2178a6d818e3SYunsheng Lin { 2179a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2180a6d818e3SYunsheng Lin int ret; 2181a6d818e3SYunsheng Lin 2182a6d818e3SYunsheng Lin ret = hclgevf_set_alive(handle, false); 2183a6d818e3SYunsheng Lin if (ret) 2184a6d818e3SYunsheng Lin dev_warn(&hdev->pdev->dev, 2185a6d818e3SYunsheng Lin "%s failed %d\n", __func__, ret); 2186a6d818e3SYunsheng Lin 2187a6d818e3SYunsheng Lin del_timer_sync(&hdev->keep_alive_timer); 2188a6d818e3SYunsheng Lin cancel_work_sync(&hdev->keep_alive_task); 2189a6d818e3SYunsheng Lin } 2190a6d818e3SYunsheng Lin 2191e2cb1decSSalil Mehta static void hclgevf_state_init(struct hclgevf_dev *hdev) 2192e2cb1decSSalil Mehta { 2193e2cb1decSSalil Mehta /* setup tasks for the MBX */ 2194e2cb1decSSalil Mehta INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 2195e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2196e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2197e2cb1decSSalil Mehta 2198e2cb1decSSalil Mehta /* setup tasks for service timer */ 2199e2cb1decSSalil Mehta timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 2200e2cb1decSSalil Mehta 2201e2cb1decSSalil Mehta INIT_WORK(&hdev->service_task, hclgevf_service_task); 2202e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2203e2cb1decSSalil Mehta 220435a1e503SSalil Mehta INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task); 220535a1e503SSalil Mehta 2206e2cb1decSSalil Mehta mutex_init(&hdev->mbx_resp.mbx_mutex); 2207e2cb1decSSalil Mehta 2208e2cb1decSSalil Mehta /* bring the device down */ 2209e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2210e2cb1decSSalil Mehta } 2211e2cb1decSSalil Mehta 2212e2cb1decSSalil Mehta static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2213e2cb1decSSalil Mehta { 2214e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2215acfc3d55SHuazhong Tan set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2216e2cb1decSSalil Mehta 2217e233516eSHuazhong Tan if (hdev->keep_alive_timer.function) 2218e233516eSHuazhong Tan del_timer_sync(&hdev->keep_alive_timer); 2219e233516eSHuazhong Tan if (hdev->keep_alive_task.func) 2220e233516eSHuazhong Tan cancel_work_sync(&hdev->keep_alive_task); 2221e2cb1decSSalil Mehta if (hdev->service_timer.function) 2222e2cb1decSSalil Mehta del_timer_sync(&hdev->service_timer); 2223e2cb1decSSalil Mehta if (hdev->service_task.func) 2224e2cb1decSSalil Mehta cancel_work_sync(&hdev->service_task); 2225e2cb1decSSalil Mehta if (hdev->mbx_service_task.func) 2226e2cb1decSSalil Mehta cancel_work_sync(&hdev->mbx_service_task); 222735a1e503SSalil Mehta if (hdev->rst_service_task.func) 222835a1e503SSalil Mehta cancel_work_sync(&hdev->rst_service_task); 2229e2cb1decSSalil Mehta 2230e2cb1decSSalil Mehta mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2231e2cb1decSSalil Mehta } 2232e2cb1decSSalil Mehta 2233e2cb1decSSalil Mehta static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2234e2cb1decSSalil Mehta { 2235e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2236e2cb1decSSalil Mehta int vectors; 2237e2cb1decSSalil Mehta int i; 2238e2cb1decSSalil Mehta 223907acf909SJian Shen if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) 224007acf909SJian Shen vectors = pci_alloc_irq_vectors(pdev, 224107acf909SJian Shen hdev->roce_base_msix_offset + 1, 224207acf909SJian Shen hdev->num_msi, 224307acf909SJian Shen PCI_IRQ_MSIX); 224407acf909SJian Shen else 2245e2cb1decSSalil Mehta vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 2246e2cb1decSSalil Mehta PCI_IRQ_MSI | PCI_IRQ_MSIX); 224707acf909SJian Shen 2248e2cb1decSSalil Mehta if (vectors < 0) { 2249e2cb1decSSalil Mehta dev_err(&pdev->dev, 2250e2cb1decSSalil Mehta "failed(%d) to allocate MSI/MSI-X vectors\n", 2251e2cb1decSSalil Mehta vectors); 2252e2cb1decSSalil Mehta return vectors; 2253e2cb1decSSalil Mehta } 2254e2cb1decSSalil Mehta if (vectors < hdev->num_msi) 2255e2cb1decSSalil Mehta dev_warn(&hdev->pdev->dev, 2256e2cb1decSSalil Mehta "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2257e2cb1decSSalil Mehta hdev->num_msi, vectors); 2258e2cb1decSSalil Mehta 2259e2cb1decSSalil Mehta hdev->num_msi = vectors; 2260e2cb1decSSalil Mehta hdev->num_msi_left = vectors; 2261e2cb1decSSalil Mehta hdev->base_msi_vector = pdev->irq; 226207acf909SJian Shen hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2263e2cb1decSSalil Mehta 2264e2cb1decSSalil Mehta hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2265e2cb1decSSalil Mehta sizeof(u16), GFP_KERNEL); 2266e2cb1decSSalil Mehta if (!hdev->vector_status) { 2267e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2268e2cb1decSSalil Mehta return -ENOMEM; 2269e2cb1decSSalil Mehta } 2270e2cb1decSSalil Mehta 2271e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 2272e2cb1decSSalil Mehta hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2273e2cb1decSSalil Mehta 2274e2cb1decSSalil Mehta hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2275e2cb1decSSalil Mehta sizeof(int), GFP_KERNEL); 2276e2cb1decSSalil Mehta if (!hdev->vector_irq) { 2277862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2278e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2279e2cb1decSSalil Mehta return -ENOMEM; 2280e2cb1decSSalil Mehta } 2281e2cb1decSSalil Mehta 2282e2cb1decSSalil Mehta return 0; 2283e2cb1decSSalil Mehta } 2284e2cb1decSSalil Mehta 2285e2cb1decSSalil Mehta static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2286e2cb1decSSalil Mehta { 2287e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2288e2cb1decSSalil Mehta 2289862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2290862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_irq); 2291e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2292e2cb1decSSalil Mehta } 2293e2cb1decSSalil Mehta 2294e2cb1decSSalil Mehta static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2295e2cb1decSSalil Mehta { 2296e2cb1decSSalil Mehta int ret = 0; 2297e2cb1decSSalil Mehta 2298e2cb1decSSalil Mehta hclgevf_get_misc_vector(hdev); 2299e2cb1decSSalil Mehta 2300e2cb1decSSalil Mehta ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2301e2cb1decSSalil Mehta 0, "hclgevf_cmd", hdev); 2302e2cb1decSSalil Mehta if (ret) { 2303e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2304e2cb1decSSalil Mehta hdev->misc_vector.vector_irq); 2305e2cb1decSSalil Mehta return ret; 2306e2cb1decSSalil Mehta } 2307e2cb1decSSalil Mehta 23081819e409SXi Wang hclgevf_clear_event_cause(hdev, 0); 23091819e409SXi Wang 2310e2cb1decSSalil Mehta /* enable misc. vector(vector 0) */ 2311e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2312e2cb1decSSalil Mehta 2313e2cb1decSSalil Mehta return ret; 2314e2cb1decSSalil Mehta } 2315e2cb1decSSalil Mehta 2316e2cb1decSSalil Mehta static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2317e2cb1decSSalil Mehta { 2318e2cb1decSSalil Mehta /* disable misc vector(vector 0) */ 2319e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 23201819e409SXi Wang synchronize_irq(hdev->misc_vector.vector_irq); 2321e2cb1decSSalil Mehta free_irq(hdev->misc_vector.vector_irq, hdev); 2322e2cb1decSSalil Mehta hclgevf_free_vector(hdev, 0); 2323e2cb1decSSalil Mehta } 2324e2cb1decSSalil Mehta 2325bb87be87SYonglong Liu static void hclgevf_info_show(struct hclgevf_dev *hdev) 2326bb87be87SYonglong Liu { 2327bb87be87SYonglong Liu struct device *dev = &hdev->pdev->dev; 2328bb87be87SYonglong Liu 2329bb87be87SYonglong Liu dev_info(dev, "VF info begin:\n"); 2330bb87be87SYonglong Liu 2331bb87be87SYonglong Liu dev_info(dev, "Task queue pairs numbers: %d\n", hdev->num_tqps); 2332bb87be87SYonglong Liu dev_info(dev, "Desc num per TX queue: %d\n", hdev->num_tx_desc); 2333bb87be87SYonglong Liu dev_info(dev, "Desc num per RX queue: %d\n", hdev->num_rx_desc); 2334bb87be87SYonglong Liu dev_info(dev, "Numbers of vports: %d\n", hdev->num_alloc_vport); 2335bb87be87SYonglong Liu dev_info(dev, "HW tc map: %d\n", hdev->hw_tc_map); 2336bb87be87SYonglong Liu dev_info(dev, "PF media type of this VF: %d\n", 2337bb87be87SYonglong Liu hdev->hw.mac.media_type); 2338bb87be87SYonglong Liu 2339bb87be87SYonglong Liu dev_info(dev, "VF info end.\n"); 2340bb87be87SYonglong Liu } 2341bb87be87SYonglong Liu 23421db58f86SHuazhong Tan static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 23431db58f86SHuazhong Tan struct hnae3_client *client) 23441db58f86SHuazhong Tan { 23451db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 23461db58f86SHuazhong Tan int ret; 23471db58f86SHuazhong Tan 23481db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->nic); 23491db58f86SHuazhong Tan if (ret) 23501db58f86SHuazhong Tan return ret; 23511db58f86SHuazhong Tan 23521db58f86SHuazhong Tan set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 23531db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 23541db58f86SHuazhong Tan 23551db58f86SHuazhong Tan if (netif_msg_drv(&hdev->nic)) 23561db58f86SHuazhong Tan hclgevf_info_show(hdev); 23571db58f86SHuazhong Tan 23581db58f86SHuazhong Tan return 0; 23591db58f86SHuazhong Tan } 23601db58f86SHuazhong Tan 23611db58f86SHuazhong Tan static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 23621db58f86SHuazhong Tan struct hnae3_client *client) 23631db58f86SHuazhong Tan { 23641db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 23651db58f86SHuazhong Tan int ret; 23661db58f86SHuazhong Tan 23671db58f86SHuazhong Tan if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 23681db58f86SHuazhong Tan !hdev->nic_client) 23691db58f86SHuazhong Tan return 0; 23701db58f86SHuazhong Tan 23711db58f86SHuazhong Tan ret = hclgevf_init_roce_base_info(hdev); 23721db58f86SHuazhong Tan if (ret) 23731db58f86SHuazhong Tan return ret; 23741db58f86SHuazhong Tan 23751db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->roce); 23761db58f86SHuazhong Tan if (ret) 23771db58f86SHuazhong Tan return ret; 23781db58f86SHuazhong Tan 23791db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 23801db58f86SHuazhong Tan 23811db58f86SHuazhong Tan return 0; 23821db58f86SHuazhong Tan } 23831db58f86SHuazhong Tan 2384e718a93fSPeng Li static int hclgevf_init_client_instance(struct hnae3_client *client, 2385e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2386e2cb1decSSalil Mehta { 2387e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2388e2cb1decSSalil Mehta int ret; 2389e2cb1decSSalil Mehta 2390e2cb1decSSalil Mehta switch (client->type) { 2391e2cb1decSSalil Mehta case HNAE3_CLIENT_KNIC: 2392e2cb1decSSalil Mehta hdev->nic_client = client; 2393e2cb1decSSalil Mehta hdev->nic.client = client; 2394e2cb1decSSalil Mehta 23951db58f86SHuazhong Tan ret = hclgevf_init_nic_client_instance(ae_dev, client); 2396e2cb1decSSalil Mehta if (ret) 239749dd8054SJian Shen goto clear_nic; 2398e2cb1decSSalil Mehta 23991db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, 24001db58f86SHuazhong Tan hdev->roce_client); 2401e2cb1decSSalil Mehta if (ret) 240249dd8054SJian Shen goto clear_roce; 2403d9f28fc2SJian Shen 2404e2cb1decSSalil Mehta break; 2405e2cb1decSSalil Mehta case HNAE3_CLIENT_ROCE: 2406544a7bcdSLijun Ou if (hnae3_dev_roce_supported(hdev)) { 2407e2cb1decSSalil Mehta hdev->roce_client = client; 2408e2cb1decSSalil Mehta hdev->roce.client = client; 2409544a7bcdSLijun Ou } 2410e2cb1decSSalil Mehta 24111db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, client); 2412e2cb1decSSalil Mehta if (ret) 241349dd8054SJian Shen goto clear_roce; 2414e2cb1decSSalil Mehta 2415fa7a4bd5SJian Shen break; 2416fa7a4bd5SJian Shen default: 2417fa7a4bd5SJian Shen return -EINVAL; 2418e2cb1decSSalil Mehta } 2419e2cb1decSSalil Mehta 2420e2cb1decSSalil Mehta return 0; 242149dd8054SJian Shen 242249dd8054SJian Shen clear_nic: 242349dd8054SJian Shen hdev->nic_client = NULL; 242449dd8054SJian Shen hdev->nic.client = NULL; 242549dd8054SJian Shen return ret; 242649dd8054SJian Shen clear_roce: 242749dd8054SJian Shen hdev->roce_client = NULL; 242849dd8054SJian Shen hdev->roce.client = NULL; 242949dd8054SJian Shen return ret; 2430e2cb1decSSalil Mehta } 2431e2cb1decSSalil Mehta 2432e718a93fSPeng Li static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2433e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2434e2cb1decSSalil Mehta { 2435e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2436e718a93fSPeng Li 2437e2cb1decSSalil Mehta /* un-init roce, if it exists */ 243849dd8054SJian Shen if (hdev->roce_client) { 2439e2cb1decSSalil Mehta hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 244049dd8054SJian Shen hdev->roce_client = NULL; 244149dd8054SJian Shen hdev->roce.client = NULL; 244249dd8054SJian Shen } 2443e2cb1decSSalil Mehta 2444e2cb1decSSalil Mehta /* un-init nic/unic, if this was not called by roce client */ 244549dd8054SJian Shen if (client->ops->uninit_instance && hdev->nic_client && 244649dd8054SJian Shen client->type != HNAE3_CLIENT_ROCE) { 244725d1817cSHuazhong Tan clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 244825d1817cSHuazhong Tan 2449e2cb1decSSalil Mehta client->ops->uninit_instance(&hdev->nic, 0); 245049dd8054SJian Shen hdev->nic_client = NULL; 245149dd8054SJian Shen hdev->nic.client = NULL; 245249dd8054SJian Shen } 2453e2cb1decSSalil Mehta } 2454e2cb1decSSalil Mehta 2455e2cb1decSSalil Mehta static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2456e2cb1decSSalil Mehta { 2457e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2458e2cb1decSSalil Mehta struct hclgevf_hw *hw; 2459e2cb1decSSalil Mehta int ret; 2460e2cb1decSSalil Mehta 2461e2cb1decSSalil Mehta ret = pci_enable_device(pdev); 2462e2cb1decSSalil Mehta if (ret) { 2463e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed to enable PCI device\n"); 24643e249d3bSFuyun Liang return ret; 2465e2cb1decSSalil Mehta } 2466e2cb1decSSalil Mehta 2467e2cb1decSSalil Mehta ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2468e2cb1decSSalil Mehta if (ret) { 2469e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2470e2cb1decSSalil Mehta goto err_disable_device; 2471e2cb1decSSalil Mehta } 2472e2cb1decSSalil Mehta 2473e2cb1decSSalil Mehta ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2474e2cb1decSSalil Mehta if (ret) { 2475e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2476e2cb1decSSalil Mehta goto err_disable_device; 2477e2cb1decSSalil Mehta } 2478e2cb1decSSalil Mehta 2479e2cb1decSSalil Mehta pci_set_master(pdev); 2480e2cb1decSSalil Mehta hw = &hdev->hw; 2481e2cb1decSSalil Mehta hw->hdev = hdev; 24822e1ea493SPeng Li hw->io_base = pci_iomap(pdev, 2, 0); 2483e2cb1decSSalil Mehta if (!hw->io_base) { 2484e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't map configuration register space\n"); 2485e2cb1decSSalil Mehta ret = -ENOMEM; 2486e2cb1decSSalil Mehta goto err_clr_master; 2487e2cb1decSSalil Mehta } 2488e2cb1decSSalil Mehta 2489e2cb1decSSalil Mehta return 0; 2490e2cb1decSSalil Mehta 2491e2cb1decSSalil Mehta err_clr_master: 2492e2cb1decSSalil Mehta pci_clear_master(pdev); 2493e2cb1decSSalil Mehta pci_release_regions(pdev); 2494e2cb1decSSalil Mehta err_disable_device: 2495e2cb1decSSalil Mehta pci_disable_device(pdev); 24963e249d3bSFuyun Liang 2497e2cb1decSSalil Mehta return ret; 2498e2cb1decSSalil Mehta } 2499e2cb1decSSalil Mehta 2500e2cb1decSSalil Mehta static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2501e2cb1decSSalil Mehta { 2502e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2503e2cb1decSSalil Mehta 2504e2cb1decSSalil Mehta pci_iounmap(pdev, hdev->hw.io_base); 2505e2cb1decSSalil Mehta pci_clear_master(pdev); 2506e2cb1decSSalil Mehta pci_release_regions(pdev); 2507e2cb1decSSalil Mehta pci_disable_device(pdev); 2508e2cb1decSSalil Mehta } 2509e2cb1decSSalil Mehta 251007acf909SJian Shen static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 251107acf909SJian Shen { 251207acf909SJian Shen struct hclgevf_query_res_cmd *req; 251307acf909SJian Shen struct hclgevf_desc desc; 251407acf909SJian Shen int ret; 251507acf909SJian Shen 251607acf909SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 251707acf909SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 251807acf909SJian Shen if (ret) { 251907acf909SJian Shen dev_err(&hdev->pdev->dev, 252007acf909SJian Shen "query vf resource failed, ret = %d.\n", ret); 252107acf909SJian Shen return ret; 252207acf909SJian Shen } 252307acf909SJian Shen 252407acf909SJian Shen req = (struct hclgevf_query_res_cmd *)desc.data; 252507acf909SJian Shen 252607acf909SJian Shen if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) { 252707acf909SJian Shen hdev->roce_base_msix_offset = 252807acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 252907acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_M, 253007acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_S); 253107acf909SJian Shen hdev->num_roce_msix = 253207acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 253307acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 253407acf909SJian Shen 253507acf909SJian Shen /* VF should have NIC vectors and Roce vectors, NIC vectors 253607acf909SJian Shen * are queued before Roce vectors. The offset is fixed to 64. 253707acf909SJian Shen */ 253807acf909SJian Shen hdev->num_msi = hdev->num_roce_msix + 253907acf909SJian Shen hdev->roce_base_msix_offset; 254007acf909SJian Shen } else { 254107acf909SJian Shen hdev->num_msi = 254207acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 254307acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 254407acf909SJian Shen } 254507acf909SJian Shen 254607acf909SJian Shen return 0; 254707acf909SJian Shen } 254807acf909SJian Shen 2549862d969aSHuazhong Tan static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2550862d969aSHuazhong Tan { 2551862d969aSHuazhong Tan struct pci_dev *pdev = hdev->pdev; 2552862d969aSHuazhong Tan int ret = 0; 2553862d969aSHuazhong Tan 2554862d969aSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2555862d969aSHuazhong Tan test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2556862d969aSHuazhong Tan hclgevf_misc_irq_uninit(hdev); 2557862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2558862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2559862d969aSHuazhong Tan } 2560862d969aSHuazhong Tan 2561862d969aSHuazhong Tan if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2562862d969aSHuazhong Tan pci_set_master(pdev); 2563862d969aSHuazhong Tan ret = hclgevf_init_msi(hdev); 2564862d969aSHuazhong Tan if (ret) { 2565862d969aSHuazhong Tan dev_err(&pdev->dev, 2566862d969aSHuazhong Tan "failed(%d) to init MSI/MSI-X\n", ret); 2567862d969aSHuazhong Tan return ret; 2568862d969aSHuazhong Tan } 2569862d969aSHuazhong Tan 2570862d969aSHuazhong Tan ret = hclgevf_misc_irq_init(hdev); 2571862d969aSHuazhong Tan if (ret) { 2572862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2573862d969aSHuazhong Tan dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2574862d969aSHuazhong Tan ret); 2575862d969aSHuazhong Tan return ret; 2576862d969aSHuazhong Tan } 2577862d969aSHuazhong Tan 2578862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2579862d969aSHuazhong Tan } 2580862d969aSHuazhong Tan 2581862d969aSHuazhong Tan return ret; 2582862d969aSHuazhong Tan } 2583862d969aSHuazhong Tan 25849c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2585e2cb1decSSalil Mehta { 25867a01c897SSalil Mehta struct pci_dev *pdev = hdev->pdev; 2587e2cb1decSSalil Mehta int ret; 2588e2cb1decSSalil Mehta 2589862d969aSHuazhong Tan ret = hclgevf_pci_reset(hdev); 2590862d969aSHuazhong Tan if (ret) { 2591862d969aSHuazhong Tan dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2592862d969aSHuazhong Tan return ret; 2593862d969aSHuazhong Tan } 2594862d969aSHuazhong Tan 25959c6f7085SHuazhong Tan ret = hclgevf_cmd_init(hdev); 25969c6f7085SHuazhong Tan if (ret) { 25979c6f7085SHuazhong Tan dev_err(&pdev->dev, "cmd failed %d\n", ret); 25989c6f7085SHuazhong Tan return ret; 25997a01c897SSalil Mehta } 2600e2cb1decSSalil Mehta 26019c6f7085SHuazhong Tan ret = hclgevf_rss_init_hw(hdev); 26029c6f7085SHuazhong Tan if (ret) { 26039c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 26049c6f7085SHuazhong Tan "failed(%d) to initialize RSS\n", ret); 26059c6f7085SHuazhong Tan return ret; 26069c6f7085SHuazhong Tan } 26079c6f7085SHuazhong Tan 2608b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2609b26a6feaSPeng Li if (ret) 2610b26a6feaSPeng Li return ret; 2611b26a6feaSPeng Li 26129c6f7085SHuazhong Tan ret = hclgevf_init_vlan_config(hdev); 26139c6f7085SHuazhong Tan if (ret) { 26149c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 26159c6f7085SHuazhong Tan "failed(%d) to initialize VLAN config\n", ret); 26169c6f7085SHuazhong Tan return ret; 26179c6f7085SHuazhong Tan } 26189c6f7085SHuazhong Tan 26192d5066fcSJian Shen if (pdev->revision >= 0x21) { 26202d5066fcSJian Shen ret = hclgevf_set_promisc_mode(hdev, true); 26212d5066fcSJian Shen if (ret) 26222d5066fcSJian Shen return ret; 26232d5066fcSJian Shen } 26242d5066fcSJian Shen 26259c6f7085SHuazhong Tan dev_info(&hdev->pdev->dev, "Reset done\n"); 26269c6f7085SHuazhong Tan 26279c6f7085SHuazhong Tan return 0; 26289c6f7085SHuazhong Tan } 26299c6f7085SHuazhong Tan 26309c6f7085SHuazhong Tan static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 26319c6f7085SHuazhong Tan { 26329c6f7085SHuazhong Tan struct pci_dev *pdev = hdev->pdev; 26339c6f7085SHuazhong Tan int ret; 26349c6f7085SHuazhong Tan 2635e2cb1decSSalil Mehta ret = hclgevf_pci_init(hdev); 2636e2cb1decSSalil Mehta if (ret) { 2637e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI initialization failed\n"); 2638e2cb1decSSalil Mehta return ret; 2639e2cb1decSSalil Mehta } 2640e2cb1decSSalil Mehta 26418b0195a3SHuazhong Tan ret = hclgevf_cmd_queue_init(hdev); 26428b0195a3SHuazhong Tan if (ret) { 26438b0195a3SHuazhong Tan dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret); 26448b0195a3SHuazhong Tan goto err_cmd_queue_init; 26458b0195a3SHuazhong Tan } 26468b0195a3SHuazhong Tan 2647eddf0462SYunsheng Lin ret = hclgevf_cmd_init(hdev); 2648eddf0462SYunsheng Lin if (ret) 2649eddf0462SYunsheng Lin goto err_cmd_init; 2650eddf0462SYunsheng Lin 265107acf909SJian Shen /* Get vf resource */ 265207acf909SJian Shen ret = hclgevf_query_vf_resource(hdev); 265307acf909SJian Shen if (ret) { 265407acf909SJian Shen dev_err(&hdev->pdev->dev, 265507acf909SJian Shen "Query vf status error, ret = %d.\n", ret); 26568b0195a3SHuazhong Tan goto err_cmd_init; 265707acf909SJian Shen } 265807acf909SJian Shen 265907acf909SJian Shen ret = hclgevf_init_msi(hdev); 266007acf909SJian Shen if (ret) { 266107acf909SJian Shen dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 26628b0195a3SHuazhong Tan goto err_cmd_init; 266307acf909SJian Shen } 266407acf909SJian Shen 266507acf909SJian Shen hclgevf_state_init(hdev); 2666dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 266707acf909SJian Shen 2668e2cb1decSSalil Mehta ret = hclgevf_misc_irq_init(hdev); 2669e2cb1decSSalil Mehta if (ret) { 2670e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2671e2cb1decSSalil Mehta ret); 2672e2cb1decSSalil Mehta goto err_misc_irq_init; 2673e2cb1decSSalil Mehta } 2674e2cb1decSSalil Mehta 2675862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2676862d969aSHuazhong Tan 2677e2cb1decSSalil Mehta ret = hclgevf_configure(hdev); 2678e2cb1decSSalil Mehta if (ret) { 2679e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2680e2cb1decSSalil Mehta goto err_config; 2681e2cb1decSSalil Mehta } 2682e2cb1decSSalil Mehta 2683e2cb1decSSalil Mehta ret = hclgevf_alloc_tqps(hdev); 2684e2cb1decSSalil Mehta if (ret) { 2685e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2686e2cb1decSSalil Mehta goto err_config; 2687e2cb1decSSalil Mehta } 2688e2cb1decSSalil Mehta 2689e2cb1decSSalil Mehta ret = hclgevf_set_handle_info(hdev); 2690e2cb1decSSalil Mehta if (ret) { 2691e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 2692e2cb1decSSalil Mehta goto err_config; 2693e2cb1decSSalil Mehta } 2694e2cb1decSSalil Mehta 2695b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2696b26a6feaSPeng Li if (ret) 2697b26a6feaSPeng Li goto err_config; 2698b26a6feaSPeng Li 2699f01f5559SJian Shen /* vf is not allowed to enable unicast/multicast promisc mode. 2700f01f5559SJian Shen * For revision 0x20, default to disable broadcast promisc mode, 2701f01f5559SJian Shen * firmware makes sure broadcast packets can be accepted. 2702f01f5559SJian Shen * For revision 0x21, default to enable broadcast promisc mode. 2703f01f5559SJian Shen */ 27042d5066fcSJian Shen if (pdev->revision >= 0x21) { 2705f01f5559SJian Shen ret = hclgevf_set_promisc_mode(hdev, true); 2706f01f5559SJian Shen if (ret) 2707f01f5559SJian Shen goto err_config; 27082d5066fcSJian Shen } 2709f01f5559SJian Shen 2710e2cb1decSSalil Mehta /* Initialize RSS for this VF */ 2711e2cb1decSSalil Mehta ret = hclgevf_rss_init_hw(hdev); 2712e2cb1decSSalil Mehta if (ret) { 2713e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2714e2cb1decSSalil Mehta "failed(%d) to initialize RSS\n", ret); 2715e2cb1decSSalil Mehta goto err_config; 2716e2cb1decSSalil Mehta } 2717e2cb1decSSalil Mehta 2718e2cb1decSSalil Mehta ret = hclgevf_init_vlan_config(hdev); 2719e2cb1decSSalil Mehta if (ret) { 2720e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2721e2cb1decSSalil Mehta "failed(%d) to initialize VLAN config\n", ret); 2722e2cb1decSSalil Mehta goto err_config; 2723e2cb1decSSalil Mehta } 2724e2cb1decSSalil Mehta 27250742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 272608d80a4cSHuazhong Tan dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 272708d80a4cSHuazhong Tan HCLGEVF_DRIVER_NAME); 2728e2cb1decSSalil Mehta 2729e2cb1decSSalil Mehta return 0; 2730e2cb1decSSalil Mehta 2731e2cb1decSSalil Mehta err_config: 2732e2cb1decSSalil Mehta hclgevf_misc_irq_uninit(hdev); 2733e2cb1decSSalil Mehta err_misc_irq_init: 2734e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2735e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 273607acf909SJian Shen err_cmd_init: 27378b0195a3SHuazhong Tan hclgevf_cmd_uninit(hdev); 27388b0195a3SHuazhong Tan err_cmd_queue_init: 2739e2cb1decSSalil Mehta hclgevf_pci_uninit(hdev); 2740862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2741e2cb1decSSalil Mehta return ret; 2742e2cb1decSSalil Mehta } 2743e2cb1decSSalil Mehta 27447a01c897SSalil Mehta static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2745e2cb1decSSalil Mehta { 2746e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2747862d969aSHuazhong Tan 2748862d969aSHuazhong Tan if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2749eddf0462SYunsheng Lin hclgevf_misc_irq_uninit(hdev); 2750e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 27517a01c897SSalil Mehta } 27527a01c897SSalil Mehta 2753e3338205SHuazhong Tan hclgevf_pci_uninit(hdev); 2754862d969aSHuazhong Tan hclgevf_cmd_uninit(hdev); 2755862d969aSHuazhong Tan } 2756862d969aSHuazhong Tan 27577a01c897SSalil Mehta static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 27587a01c897SSalil Mehta { 27597a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 2760a6d818e3SYunsheng Lin struct hclgevf_dev *hdev; 27617a01c897SSalil Mehta int ret; 27627a01c897SSalil Mehta 27637a01c897SSalil Mehta ret = hclgevf_alloc_hdev(ae_dev); 27647a01c897SSalil Mehta if (ret) { 27657a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device allocation failed\n"); 27667a01c897SSalil Mehta return ret; 27677a01c897SSalil Mehta } 27687a01c897SSalil Mehta 27697a01c897SSalil Mehta ret = hclgevf_init_hdev(ae_dev->priv); 2770a6d818e3SYunsheng Lin if (ret) { 27717a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device initialization failed\n"); 27727a01c897SSalil Mehta return ret; 27737a01c897SSalil Mehta } 27747a01c897SSalil Mehta 2775a6d818e3SYunsheng Lin hdev = ae_dev->priv; 2776a6d818e3SYunsheng Lin timer_setup(&hdev->keep_alive_timer, hclgevf_keep_alive_timer, 0); 2777a6d818e3SYunsheng Lin INIT_WORK(&hdev->keep_alive_task, hclgevf_keep_alive_task); 2778a6d818e3SYunsheng Lin 2779a6d818e3SYunsheng Lin return 0; 2780a6d818e3SYunsheng Lin } 2781a6d818e3SYunsheng Lin 27827a01c897SSalil Mehta static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 27837a01c897SSalil Mehta { 27847a01c897SSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 27857a01c897SSalil Mehta 27867a01c897SSalil Mehta hclgevf_uninit_hdev(hdev); 2787e2cb1decSSalil Mehta ae_dev->priv = NULL; 2788e2cb1decSSalil Mehta } 2789e2cb1decSSalil Mehta 2790849e4607SPeng Li static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2791849e4607SPeng Li { 2792849e4607SPeng Li struct hnae3_handle *nic = &hdev->nic; 2793849e4607SPeng Li struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2794849e4607SPeng Li 27958be73621SHuazhong Tan return min_t(u32, hdev->rss_size_max, 27968be73621SHuazhong Tan hdev->num_tqps / kinfo->num_tc); 2797849e4607SPeng Li } 2798849e4607SPeng Li 2799849e4607SPeng Li /** 2800849e4607SPeng Li * hclgevf_get_channels - Get the current channels enabled and max supported. 2801849e4607SPeng Li * @handle: hardware information for network interface 2802849e4607SPeng Li * @ch: ethtool channels structure 2803849e4607SPeng Li * 2804849e4607SPeng Li * We don't support separate tx and rx queues as channels. The other count 2805849e4607SPeng Li * represents how many queues are being used for control. max_combined counts 2806849e4607SPeng Li * how many queue pairs we can support. They may not be mapped 1 to 1 with 2807849e4607SPeng Li * q_vectors since we support a lot more queue pairs than q_vectors. 2808849e4607SPeng Li **/ 2809849e4607SPeng Li static void hclgevf_get_channels(struct hnae3_handle *handle, 2810849e4607SPeng Li struct ethtool_channels *ch) 2811849e4607SPeng Li { 2812849e4607SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2813849e4607SPeng Li 2814849e4607SPeng Li ch->max_combined = hclgevf_get_max_channels(hdev); 2815849e4607SPeng Li ch->other_count = 0; 2816849e4607SPeng Li ch->max_other = 0; 28178be73621SHuazhong Tan ch->combined_count = handle->kinfo.rss_size; 2818849e4607SPeng Li } 2819849e4607SPeng Li 2820cc719218SPeng Li static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 28210d43bf45SHuazhong Tan u16 *alloc_tqps, u16 *max_rss_size) 2822cc719218SPeng Li { 2823cc719218SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2824cc719218SPeng Li 28250d43bf45SHuazhong Tan *alloc_tqps = hdev->num_tqps; 2826cc719218SPeng Li *max_rss_size = hdev->rss_size_max; 2827cc719218SPeng Li } 2828cc719218SPeng Li 2829175ec96bSFuyun Liang static int hclgevf_get_status(struct hnae3_handle *handle) 2830175ec96bSFuyun Liang { 2831175ec96bSFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2832175ec96bSFuyun Liang 2833175ec96bSFuyun Liang return hdev->hw.mac.link; 2834175ec96bSFuyun Liang } 2835175ec96bSFuyun Liang 28364a152de9SFuyun Liang static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 28374a152de9SFuyun Liang u8 *auto_neg, u32 *speed, 28384a152de9SFuyun Liang u8 *duplex) 28394a152de9SFuyun Liang { 28404a152de9SFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 28414a152de9SFuyun Liang 28424a152de9SFuyun Liang if (speed) 28434a152de9SFuyun Liang *speed = hdev->hw.mac.speed; 28444a152de9SFuyun Liang if (duplex) 28454a152de9SFuyun Liang *duplex = hdev->hw.mac.duplex; 28464a152de9SFuyun Liang if (auto_neg) 28474a152de9SFuyun Liang *auto_neg = AUTONEG_DISABLE; 28484a152de9SFuyun Liang } 28494a152de9SFuyun Liang 28504a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 28514a152de9SFuyun Liang u8 duplex) 28524a152de9SFuyun Liang { 28534a152de9SFuyun Liang hdev->hw.mac.speed = speed; 28544a152de9SFuyun Liang hdev->hw.mac.duplex = duplex; 28554a152de9SFuyun Liang } 28564a152de9SFuyun Liang 28571731be4cSYonglong Liu static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 28585c9f6b39SPeng Li { 28595c9f6b39SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 28605c9f6b39SPeng Li 28615c9f6b39SPeng Li return hclgevf_config_gro(hdev, enable); 28625c9f6b39SPeng Li } 28635c9f6b39SPeng Li 286488d10bd6SJian Shen static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 286588d10bd6SJian Shen u8 *module_type) 2866c136b884SPeng Li { 2867c136b884SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 286888d10bd6SJian Shen 2869c136b884SPeng Li if (media_type) 2870c136b884SPeng Li *media_type = hdev->hw.mac.media_type; 287188d10bd6SJian Shen 287288d10bd6SJian Shen if (module_type) 287388d10bd6SJian Shen *module_type = hdev->hw.mac.module_type; 2874c136b884SPeng Li } 2875c136b884SPeng Li 28764d60291bSHuazhong Tan static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 28774d60291bSHuazhong Tan { 28784d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 28794d60291bSHuazhong Tan 2880aa5c4f17SHuazhong Tan return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 28814d60291bSHuazhong Tan } 28824d60291bSHuazhong Tan 28834d60291bSHuazhong Tan static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 28844d60291bSHuazhong Tan { 28854d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 28864d60291bSHuazhong Tan 28874d60291bSHuazhong Tan return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 28884d60291bSHuazhong Tan } 28894d60291bSHuazhong Tan 28904d60291bSHuazhong Tan static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 28914d60291bSHuazhong Tan { 28924d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 28934d60291bSHuazhong Tan 2894c88a6e7dSHuazhong Tan return hdev->rst_stats.hw_rst_done_cnt; 28954d60291bSHuazhong Tan } 28964d60291bSHuazhong Tan 28979194d18bSliuzhongzhu static void hclgevf_get_link_mode(struct hnae3_handle *handle, 28989194d18bSliuzhongzhu unsigned long *supported, 28999194d18bSliuzhongzhu unsigned long *advertising) 29009194d18bSliuzhongzhu { 29019194d18bSliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 29029194d18bSliuzhongzhu 29039194d18bSliuzhongzhu *supported = hdev->hw.mac.supported; 29049194d18bSliuzhongzhu *advertising = hdev->hw.mac.advertising; 29059194d18bSliuzhongzhu } 29069194d18bSliuzhongzhu 29071600c3e5SJian Shen #define MAX_SEPARATE_NUM 4 29081600c3e5SJian Shen #define SEPARATOR_VALUE 0xFFFFFFFF 29091600c3e5SJian Shen #define REG_NUM_PER_LINE 4 29101600c3e5SJian Shen #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 29111600c3e5SJian Shen 29121600c3e5SJian Shen static int hclgevf_get_regs_len(struct hnae3_handle *handle) 29131600c3e5SJian Shen { 29141600c3e5SJian Shen int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 29151600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 29161600c3e5SJian Shen 29171600c3e5SJian Shen cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 29181600c3e5SJian Shen common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 29191600c3e5SJian Shen ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 29201600c3e5SJian Shen tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 29211600c3e5SJian Shen 29221600c3e5SJian Shen return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 29231600c3e5SJian Shen tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 29241600c3e5SJian Shen } 29251600c3e5SJian Shen 29261600c3e5SJian Shen static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 29271600c3e5SJian Shen void *data) 29281600c3e5SJian Shen { 29291600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 29301600c3e5SJian Shen int i, j, reg_um, separator_num; 29311600c3e5SJian Shen u32 *reg = data; 29321600c3e5SJian Shen 29331600c3e5SJian Shen *version = hdev->fw_version; 29341600c3e5SJian Shen 29351600c3e5SJian Shen /* fetching per-VF registers values from VF PCIe register space */ 29361600c3e5SJian Shen reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 29371600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 29381600c3e5SJian Shen for (i = 0; i < reg_um; i++) 29391600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 29401600c3e5SJian Shen for (i = 0; i < separator_num; i++) 29411600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 29421600c3e5SJian Shen 29431600c3e5SJian Shen reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 29441600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 29451600c3e5SJian Shen for (i = 0; i < reg_um; i++) 29461600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 29471600c3e5SJian Shen for (i = 0; i < separator_num; i++) 29481600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 29491600c3e5SJian Shen 29501600c3e5SJian Shen reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 29511600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 29521600c3e5SJian Shen for (j = 0; j < hdev->num_tqps; j++) { 29531600c3e5SJian Shen for (i = 0; i < reg_um; i++) 29541600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 29551600c3e5SJian Shen ring_reg_addr_list[i] + 29561600c3e5SJian Shen 0x200 * j); 29571600c3e5SJian Shen for (i = 0; i < separator_num; i++) 29581600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 29591600c3e5SJian Shen } 29601600c3e5SJian Shen 29611600c3e5SJian Shen reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 29621600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 29631600c3e5SJian Shen for (j = 0; j < hdev->num_msi_used - 1; j++) { 29641600c3e5SJian Shen for (i = 0; i < reg_um; i++) 29651600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 29661600c3e5SJian Shen tqp_intr_reg_addr_list[i] + 29671600c3e5SJian Shen 4 * j); 29681600c3e5SJian Shen for (i = 0; i < separator_num; i++) 29691600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 29701600c3e5SJian Shen } 29711600c3e5SJian Shen } 29721600c3e5SJian Shen 297392f11ea1SJian Shen void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 297492f11ea1SJian Shen u8 *port_base_vlan_info, u8 data_size) 297592f11ea1SJian Shen { 297692f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 297792f11ea1SJian Shen 297892f11ea1SJian Shen rtnl_lock(); 297992f11ea1SJian Shen hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 298092f11ea1SJian Shen rtnl_unlock(); 298192f11ea1SJian Shen 298292f11ea1SJian Shen /* send msg to PF and wait update port based vlan info */ 298392f11ea1SJian Shen hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 298492f11ea1SJian Shen HCLGE_MBX_PORT_BASE_VLAN_CFG, 298592f11ea1SJian Shen port_base_vlan_info, data_size, 298692f11ea1SJian Shen false, NULL, 0); 298792f11ea1SJian Shen 298892f11ea1SJian Shen if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 298992f11ea1SJian Shen nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 299092f11ea1SJian Shen else 299192f11ea1SJian Shen nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 299292f11ea1SJian Shen 299392f11ea1SJian Shen rtnl_lock(); 299492f11ea1SJian Shen hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 299592f11ea1SJian Shen rtnl_unlock(); 299692f11ea1SJian Shen } 299792f11ea1SJian Shen 2998e2cb1decSSalil Mehta static const struct hnae3_ae_ops hclgevf_ops = { 2999e2cb1decSSalil Mehta .init_ae_dev = hclgevf_init_ae_dev, 3000e2cb1decSSalil Mehta .uninit_ae_dev = hclgevf_uninit_ae_dev, 30016ff3cf07SHuazhong Tan .flr_prepare = hclgevf_flr_prepare, 30026ff3cf07SHuazhong Tan .flr_done = hclgevf_flr_done, 3003e718a93fSPeng Li .init_client_instance = hclgevf_init_client_instance, 3004e718a93fSPeng Li .uninit_client_instance = hclgevf_uninit_client_instance, 3005e2cb1decSSalil Mehta .start = hclgevf_ae_start, 3006e2cb1decSSalil Mehta .stop = hclgevf_ae_stop, 3007a6d818e3SYunsheng Lin .client_start = hclgevf_client_start, 3008a6d818e3SYunsheng Lin .client_stop = hclgevf_client_stop, 3009e2cb1decSSalil Mehta .map_ring_to_vector = hclgevf_map_ring_to_vector, 3010e2cb1decSSalil Mehta .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 3011e2cb1decSSalil Mehta .get_vector = hclgevf_get_vector, 30120d3e6631SYunsheng Lin .put_vector = hclgevf_put_vector, 3013e2cb1decSSalil Mehta .reset_queue = hclgevf_reset_tqp, 3014e2cb1decSSalil Mehta .get_mac_addr = hclgevf_get_mac_addr, 3015e2cb1decSSalil Mehta .set_mac_addr = hclgevf_set_mac_addr, 3016e2cb1decSSalil Mehta .add_uc_addr = hclgevf_add_uc_addr, 3017e2cb1decSSalil Mehta .rm_uc_addr = hclgevf_rm_uc_addr, 3018e2cb1decSSalil Mehta .add_mc_addr = hclgevf_add_mc_addr, 3019e2cb1decSSalil Mehta .rm_mc_addr = hclgevf_rm_mc_addr, 3020e2cb1decSSalil Mehta .get_stats = hclgevf_get_stats, 3021e2cb1decSSalil Mehta .update_stats = hclgevf_update_stats, 3022e2cb1decSSalil Mehta .get_strings = hclgevf_get_strings, 3023e2cb1decSSalil Mehta .get_sset_count = hclgevf_get_sset_count, 3024e2cb1decSSalil Mehta .get_rss_key_size = hclgevf_get_rss_key_size, 3025e2cb1decSSalil Mehta .get_rss_indir_size = hclgevf_get_rss_indir_size, 3026e2cb1decSSalil Mehta .get_rss = hclgevf_get_rss, 3027e2cb1decSSalil Mehta .set_rss = hclgevf_set_rss, 3028d97b3072SJian Shen .get_rss_tuple = hclgevf_get_rss_tuple, 3029d97b3072SJian Shen .set_rss_tuple = hclgevf_set_rss_tuple, 3030e2cb1decSSalil Mehta .get_tc_size = hclgevf_get_tc_size, 3031e2cb1decSSalil Mehta .get_fw_version = hclgevf_get_fw_version, 3032e2cb1decSSalil Mehta .set_vlan_filter = hclgevf_set_vlan_filter, 3033b2641e2aSYunsheng Lin .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 30346d4c3981SSalil Mehta .reset_event = hclgevf_reset_event, 3035720bd583SHuazhong Tan .set_default_reset_request = hclgevf_set_def_reset_request, 3036849e4607SPeng Li .get_channels = hclgevf_get_channels, 3037cc719218SPeng Li .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 30381600c3e5SJian Shen .get_regs_len = hclgevf_get_regs_len, 30391600c3e5SJian Shen .get_regs = hclgevf_get_regs, 3040175ec96bSFuyun Liang .get_status = hclgevf_get_status, 30414a152de9SFuyun Liang .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3042c136b884SPeng Li .get_media_type = hclgevf_get_media_type, 30434d60291bSHuazhong Tan .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 30444d60291bSHuazhong Tan .ae_dev_resetting = hclgevf_ae_dev_resetting, 30454d60291bSHuazhong Tan .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 30465c9f6b39SPeng Li .set_gro_en = hclgevf_gro_en, 3047818f1675SYunsheng Lin .set_mtu = hclgevf_set_mtu, 30480c29d191Sliuzhongzhu .get_global_queue_id = hclgevf_get_qid_global, 30498cdb992fSJian Shen .set_timer_task = hclgevf_set_timer_task, 30509194d18bSliuzhongzhu .get_link_mode = hclgevf_get_link_mode, 3051e2cb1decSSalil Mehta }; 3052e2cb1decSSalil Mehta 3053e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf = { 3054e2cb1decSSalil Mehta .ops = &hclgevf_ops, 3055e2cb1decSSalil Mehta .pdev_id_table = ae_algovf_pci_tbl, 3056e2cb1decSSalil Mehta }; 3057e2cb1decSSalil Mehta 3058e2cb1decSSalil Mehta static int hclgevf_init(void) 3059e2cb1decSSalil Mehta { 3060e2cb1decSSalil Mehta pr_info("%s is initializing\n", HCLGEVF_NAME); 3061e2cb1decSSalil Mehta 3062854cf33aSFuyun Liang hnae3_register_ae_algo(&ae_algovf); 3063854cf33aSFuyun Liang 3064854cf33aSFuyun Liang return 0; 3065e2cb1decSSalil Mehta } 3066e2cb1decSSalil Mehta 3067e2cb1decSSalil Mehta static void hclgevf_exit(void) 3068e2cb1decSSalil Mehta { 3069e2cb1decSSalil Mehta hnae3_unregister_ae_algo(&ae_algovf); 3070e2cb1decSSalil Mehta } 3071e2cb1decSSalil Mehta module_init(hclgevf_init); 3072e2cb1decSSalil Mehta module_exit(hclgevf_exit); 3073e2cb1decSSalil Mehta 3074e2cb1decSSalil Mehta MODULE_LICENSE("GPL"); 3075e2cb1decSSalil Mehta MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3076e2cb1decSSalil Mehta MODULE_DESCRIPTION("HCLGEVF Driver"); 3077e2cb1decSSalil Mehta MODULE_VERSION(HCLGEVF_MOD_VERSION); 3078