1e2cb1decSSalil Mehta // SPDX-License-Identifier: GPL-2.0+ 2e2cb1decSSalil Mehta // Copyright (c) 2016-2017 Hisilicon Limited. 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #include <linux/etherdevice.h> 5aa5c4f17SHuazhong Tan #include <linux/iopoll.h> 66988eb2aSSalil Mehta #include <net/rtnetlink.h> 7e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 8e2cb1decSSalil Mehta #include "hclgevf_main.h" 9e2cb1decSSalil Mehta #include "hclge_mbx.h" 10e2cb1decSSalil Mehta #include "hnae3.h" 11e2cb1decSSalil Mehta 12e2cb1decSSalil Mehta #define HCLGEVF_NAME "hclgevf" 13e2cb1decSSalil Mehta 149c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 15e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf; 16e2cb1decSSalil Mehta 17e2cb1decSSalil Mehta static const struct pci_device_id ae_algovf_pci_tbl[] = { 18e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 19e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 20e2cb1decSSalil Mehta /* required last entry */ 21e2cb1decSSalil Mehta {0, } 22e2cb1decSSalil Mehta }; 23e2cb1decSSalil Mehta 24472d7eceSJian Shen static const u8 hclgevf_hash_key[] = { 25472d7eceSJian Shen 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 26472d7eceSJian Shen 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 27472d7eceSJian Shen 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 28472d7eceSJian Shen 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 29472d7eceSJian Shen 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 30472d7eceSJian Shen }; 31472d7eceSJian Shen 322f550a46SYunsheng Lin MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 332f550a46SYunsheng Lin 341600c3e5SJian Shen static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 351600c3e5SJian Shen HCLGEVF_CMDQ_TX_ADDR_H_REG, 361600c3e5SJian Shen HCLGEVF_CMDQ_TX_DEPTH_REG, 371600c3e5SJian Shen HCLGEVF_CMDQ_TX_TAIL_REG, 381600c3e5SJian Shen HCLGEVF_CMDQ_TX_HEAD_REG, 391600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_L_REG, 401600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_H_REG, 411600c3e5SJian Shen HCLGEVF_CMDQ_RX_DEPTH_REG, 421600c3e5SJian Shen HCLGEVF_CMDQ_RX_TAIL_REG, 431600c3e5SJian Shen HCLGEVF_CMDQ_RX_HEAD_REG, 441600c3e5SJian Shen HCLGEVF_VECTOR0_CMDQ_SRC_REG, 451600c3e5SJian Shen HCLGEVF_CMDQ_INTR_STS_REG, 461600c3e5SJian Shen HCLGEVF_CMDQ_INTR_EN_REG, 471600c3e5SJian Shen HCLGEVF_CMDQ_INTR_GEN_REG}; 481600c3e5SJian Shen 491600c3e5SJian Shen static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 501600c3e5SJian Shen HCLGEVF_RST_ING, 511600c3e5SJian Shen HCLGEVF_GRO_EN_REG}; 521600c3e5SJian Shen 531600c3e5SJian Shen static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 541600c3e5SJian Shen HCLGEVF_RING_RX_ADDR_H_REG, 551600c3e5SJian Shen HCLGEVF_RING_RX_BD_NUM_REG, 561600c3e5SJian Shen HCLGEVF_RING_RX_BD_LENGTH_REG, 571600c3e5SJian Shen HCLGEVF_RING_RX_MERGE_EN_REG, 581600c3e5SJian Shen HCLGEVF_RING_RX_TAIL_REG, 591600c3e5SJian Shen HCLGEVF_RING_RX_HEAD_REG, 601600c3e5SJian Shen HCLGEVF_RING_RX_FBD_NUM_REG, 611600c3e5SJian Shen HCLGEVF_RING_RX_OFFSET_REG, 621600c3e5SJian Shen HCLGEVF_RING_RX_FBD_OFFSET_REG, 631600c3e5SJian Shen HCLGEVF_RING_RX_STASH_REG, 641600c3e5SJian Shen HCLGEVF_RING_RX_BD_ERR_REG, 651600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_L_REG, 661600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_H_REG, 671600c3e5SJian Shen HCLGEVF_RING_TX_BD_NUM_REG, 681600c3e5SJian Shen HCLGEVF_RING_TX_PRIORITY_REG, 691600c3e5SJian Shen HCLGEVF_RING_TX_TC_REG, 701600c3e5SJian Shen HCLGEVF_RING_TX_MERGE_EN_REG, 711600c3e5SJian Shen HCLGEVF_RING_TX_TAIL_REG, 721600c3e5SJian Shen HCLGEVF_RING_TX_HEAD_REG, 731600c3e5SJian Shen HCLGEVF_RING_TX_FBD_NUM_REG, 741600c3e5SJian Shen HCLGEVF_RING_TX_OFFSET_REG, 751600c3e5SJian Shen HCLGEVF_RING_TX_EBD_NUM_REG, 761600c3e5SJian Shen HCLGEVF_RING_TX_EBD_OFFSET_REG, 771600c3e5SJian Shen HCLGEVF_RING_TX_BD_ERR_REG, 781600c3e5SJian Shen HCLGEVF_RING_EN_REG}; 791600c3e5SJian Shen 801600c3e5SJian Shen static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 811600c3e5SJian Shen HCLGEVF_TQP_INTR_GL0_REG, 821600c3e5SJian Shen HCLGEVF_TQP_INTR_GL1_REG, 831600c3e5SJian Shen HCLGEVF_TQP_INTR_GL2_REG, 841600c3e5SJian Shen HCLGEVF_TQP_INTR_RL_REG}; 851600c3e5SJian Shen 86e2cb1decSSalil Mehta static inline struct hclgevf_dev *hclgevf_ae_get_hdev( 87e2cb1decSSalil Mehta struct hnae3_handle *handle) 88e2cb1decSSalil Mehta { 89eed9535fSPeng Li if (!handle->client) 90eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, nic); 91eed9535fSPeng Li else if (handle->client->type == HNAE3_CLIENT_ROCE) 92eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, roce); 93eed9535fSPeng Li else 94e2cb1decSSalil Mehta return container_of(handle, struct hclgevf_dev, nic); 95e2cb1decSSalil Mehta } 96e2cb1decSSalil Mehta 97e2cb1decSSalil Mehta static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 98e2cb1decSSalil Mehta { 99b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 100e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 101e2cb1decSSalil Mehta struct hclgevf_desc desc; 102e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 103e2cb1decSSalil Mehta int status; 104e2cb1decSSalil Mehta int i; 105e2cb1decSSalil Mehta 106b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 107b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 108e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 109e2cb1decSSalil Mehta HCLGEVF_OPC_QUERY_RX_STATUS, 110e2cb1decSSalil Mehta true); 111e2cb1decSSalil Mehta 112e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 113e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 114e2cb1decSSalil Mehta if (status) { 115e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 116e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 117e2cb1decSSalil Mehta status, i); 118e2cb1decSSalil Mehta return status; 119e2cb1decSSalil Mehta } 120e2cb1decSSalil Mehta tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 121cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 122e2cb1decSSalil Mehta 123e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 124e2cb1decSSalil Mehta true); 125e2cb1decSSalil Mehta 126e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 127e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 128e2cb1decSSalil Mehta if (status) { 129e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 130e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 131e2cb1decSSalil Mehta status, i); 132e2cb1decSSalil Mehta return status; 133e2cb1decSSalil Mehta } 134e2cb1decSSalil Mehta tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 135cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 136e2cb1decSSalil Mehta } 137e2cb1decSSalil Mehta 138e2cb1decSSalil Mehta return 0; 139e2cb1decSSalil Mehta } 140e2cb1decSSalil Mehta 141e2cb1decSSalil Mehta static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 142e2cb1decSSalil Mehta { 143e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo = &handle->kinfo; 144e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 145e2cb1decSSalil Mehta u64 *buff = data; 146e2cb1decSSalil Mehta int i; 147e2cb1decSSalil Mehta 148b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 149b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 150e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 151e2cb1decSSalil Mehta } 152e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 153b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 154e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 155e2cb1decSSalil Mehta } 156e2cb1decSSalil Mehta 157e2cb1decSSalil Mehta return buff; 158e2cb1decSSalil Mehta } 159e2cb1decSSalil Mehta 160e2cb1decSSalil Mehta static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 161e2cb1decSSalil Mehta { 162b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 163e2cb1decSSalil Mehta 164b4f1d303SJian Shen return kinfo->num_tqps * 2; 165e2cb1decSSalil Mehta } 166e2cb1decSSalil Mehta 167e2cb1decSSalil Mehta static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 168e2cb1decSSalil Mehta { 169b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 170e2cb1decSSalil Mehta u8 *buff = data; 171e2cb1decSSalil Mehta int i = 0; 172e2cb1decSSalil Mehta 173b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 174b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 175e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1760c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 177e2cb1decSSalil Mehta tqp->index); 178e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 179e2cb1decSSalil Mehta } 180e2cb1decSSalil Mehta 181b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 182b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 183e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1840c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 185e2cb1decSSalil Mehta tqp->index); 186e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 187e2cb1decSSalil Mehta } 188e2cb1decSSalil Mehta 189e2cb1decSSalil Mehta return buff; 190e2cb1decSSalil Mehta } 191e2cb1decSSalil Mehta 192e2cb1decSSalil Mehta static void hclgevf_update_stats(struct hnae3_handle *handle, 193e2cb1decSSalil Mehta struct net_device_stats *net_stats) 194e2cb1decSSalil Mehta { 195e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 196e2cb1decSSalil Mehta int status; 197e2cb1decSSalil Mehta 198e2cb1decSSalil Mehta status = hclgevf_tqps_update_stats(handle); 199e2cb1decSSalil Mehta if (status) 200e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 201e2cb1decSSalil Mehta "VF update of TQPS stats fail, status = %d.\n", 202e2cb1decSSalil Mehta status); 203e2cb1decSSalil Mehta } 204e2cb1decSSalil Mehta 205e2cb1decSSalil Mehta static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 206e2cb1decSSalil Mehta { 207e2cb1decSSalil Mehta if (strset == ETH_SS_TEST) 208e2cb1decSSalil Mehta return -EOPNOTSUPP; 209e2cb1decSSalil Mehta else if (strset == ETH_SS_STATS) 210e2cb1decSSalil Mehta return hclgevf_tqps_get_sset_count(handle, strset); 211e2cb1decSSalil Mehta 212e2cb1decSSalil Mehta return 0; 213e2cb1decSSalil Mehta } 214e2cb1decSSalil Mehta 215e2cb1decSSalil Mehta static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 216e2cb1decSSalil Mehta u8 *data) 217e2cb1decSSalil Mehta { 218e2cb1decSSalil Mehta u8 *p = (char *)data; 219e2cb1decSSalil Mehta 220e2cb1decSSalil Mehta if (strset == ETH_SS_STATS) 221e2cb1decSSalil Mehta p = hclgevf_tqps_get_strings(handle, p); 222e2cb1decSSalil Mehta } 223e2cb1decSSalil Mehta 224e2cb1decSSalil Mehta static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 225e2cb1decSSalil Mehta { 226e2cb1decSSalil Mehta hclgevf_tqps_get_stats(handle, data); 227e2cb1decSSalil Mehta } 228e2cb1decSSalil Mehta 229e2cb1decSSalil Mehta static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 230e2cb1decSSalil Mehta { 231e2cb1decSSalil Mehta u8 resp_msg; 232e2cb1decSSalil Mehta int status; 233e2cb1decSSalil Mehta 234e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 23563cbf7a9SYufeng Mo true, &resp_msg, sizeof(resp_msg)); 236e2cb1decSSalil Mehta if (status) { 237e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 238e2cb1decSSalil Mehta "VF request to get TC info from PF failed %d", 239e2cb1decSSalil Mehta status); 240e2cb1decSSalil Mehta return status; 241e2cb1decSSalil Mehta } 242e2cb1decSSalil Mehta 243e2cb1decSSalil Mehta hdev->hw_tc_map = resp_msg; 244e2cb1decSSalil Mehta 245e2cb1decSSalil Mehta return 0; 246e2cb1decSSalil Mehta } 247e2cb1decSSalil Mehta 24892f11ea1SJian Shen static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 24992f11ea1SJian Shen { 25092f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 25192f11ea1SJian Shen u8 resp_msg; 25292f11ea1SJian Shen int ret; 25392f11ea1SJian Shen 25492f11ea1SJian Shen ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 25592f11ea1SJian Shen HCLGE_MBX_GET_PORT_BASE_VLAN_STATE, 25692f11ea1SJian Shen NULL, 0, true, &resp_msg, sizeof(u8)); 25792f11ea1SJian Shen if (ret) { 25892f11ea1SJian Shen dev_err(&hdev->pdev->dev, 25992f11ea1SJian Shen "VF request to get port based vlan state failed %d", 26092f11ea1SJian Shen ret); 26192f11ea1SJian Shen return ret; 26292f11ea1SJian Shen } 26392f11ea1SJian Shen 26492f11ea1SJian Shen nic->port_base_vlan_state = resp_msg; 26592f11ea1SJian Shen 26692f11ea1SJian Shen return 0; 26792f11ea1SJian Shen } 26892f11ea1SJian Shen 2696cee6fc3SJian Shen static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 270e2cb1decSSalil Mehta { 271c0425944SPeng Li #define HCLGEVF_TQPS_RSS_INFO_LEN 6 272e2cb1decSSalil Mehta u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 273e2cb1decSSalil Mehta int status; 274e2cb1decSSalil Mehta 275e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 276e2cb1decSSalil Mehta true, resp_msg, 277e2cb1decSSalil Mehta HCLGEVF_TQPS_RSS_INFO_LEN); 278e2cb1decSSalil Mehta if (status) { 279e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 280e2cb1decSSalil Mehta "VF request to get tqp info from PF failed %d", 281e2cb1decSSalil Mehta status); 282e2cb1decSSalil Mehta return status; 283e2cb1decSSalil Mehta } 284e2cb1decSSalil Mehta 285e2cb1decSSalil Mehta memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 286e2cb1decSSalil Mehta memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 287c0425944SPeng Li memcpy(&hdev->rx_buf_len, &resp_msg[4], sizeof(u16)); 288c0425944SPeng Li 289c0425944SPeng Li return 0; 290c0425944SPeng Li } 291c0425944SPeng Li 292c0425944SPeng Li static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 293c0425944SPeng Li { 294c0425944SPeng Li #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 295c0425944SPeng Li u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 296c0425944SPeng Li int ret; 297c0425944SPeng Li 298c0425944SPeng Li ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QDEPTH, 0, NULL, 0, 299c0425944SPeng Li true, resp_msg, 300c0425944SPeng Li HCLGEVF_TQPS_DEPTH_INFO_LEN); 301c0425944SPeng Li if (ret) { 302c0425944SPeng Li dev_err(&hdev->pdev->dev, 303c0425944SPeng Li "VF request to get tqp depth info from PF failed %d", 304c0425944SPeng Li ret); 305c0425944SPeng Li return ret; 306c0425944SPeng Li } 307c0425944SPeng Li 308c0425944SPeng Li memcpy(&hdev->num_tx_desc, &resp_msg[0], sizeof(u16)); 309c0425944SPeng Li memcpy(&hdev->num_rx_desc, &resp_msg[2], sizeof(u16)); 310e2cb1decSSalil Mehta 311e2cb1decSSalil Mehta return 0; 312e2cb1decSSalil Mehta } 313e2cb1decSSalil Mehta 3140c29d191Sliuzhongzhu static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 3150c29d191Sliuzhongzhu { 3160c29d191Sliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3170c29d191Sliuzhongzhu u8 msg_data[2], resp_data[2]; 3180c29d191Sliuzhongzhu u16 qid_in_pf = 0; 3190c29d191Sliuzhongzhu int ret; 3200c29d191Sliuzhongzhu 3210c29d191Sliuzhongzhu memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 3220c29d191Sliuzhongzhu 3230c29d191Sliuzhongzhu ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data, 32463cbf7a9SYufeng Mo sizeof(msg_data), true, resp_data, 32563cbf7a9SYufeng Mo sizeof(resp_data)); 3260c29d191Sliuzhongzhu if (!ret) 3270c29d191Sliuzhongzhu qid_in_pf = *(u16 *)resp_data; 3280c29d191Sliuzhongzhu 3290c29d191Sliuzhongzhu return qid_in_pf; 3300c29d191Sliuzhongzhu } 3310c29d191Sliuzhongzhu 3329c3e7130Sliuzhongzhu static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 3339c3e7130Sliuzhongzhu { 33488d10bd6SJian Shen u8 resp_msg[2]; 3359c3e7130Sliuzhongzhu int ret; 3369c3e7130Sliuzhongzhu 3379c3e7130Sliuzhongzhu ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_MEDIA_TYPE, 0, NULL, 0, 33888d10bd6SJian Shen true, resp_msg, sizeof(resp_msg)); 3399c3e7130Sliuzhongzhu if (ret) { 3409c3e7130Sliuzhongzhu dev_err(&hdev->pdev->dev, 3419c3e7130Sliuzhongzhu "VF request to get the pf port media type failed %d", 3429c3e7130Sliuzhongzhu ret); 3439c3e7130Sliuzhongzhu return ret; 3449c3e7130Sliuzhongzhu } 3459c3e7130Sliuzhongzhu 34688d10bd6SJian Shen hdev->hw.mac.media_type = resp_msg[0]; 34788d10bd6SJian Shen hdev->hw.mac.module_type = resp_msg[1]; 3489c3e7130Sliuzhongzhu 3499c3e7130Sliuzhongzhu return 0; 3509c3e7130Sliuzhongzhu } 3519c3e7130Sliuzhongzhu 352e2cb1decSSalil Mehta static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 353e2cb1decSSalil Mehta { 354e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 355e2cb1decSSalil Mehta int i; 356e2cb1decSSalil Mehta 357e2cb1decSSalil Mehta hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 358e2cb1decSSalil Mehta sizeof(struct hclgevf_tqp), GFP_KERNEL); 359e2cb1decSSalil Mehta if (!hdev->htqp) 360e2cb1decSSalil Mehta return -ENOMEM; 361e2cb1decSSalil Mehta 362e2cb1decSSalil Mehta tqp = hdev->htqp; 363e2cb1decSSalil Mehta 364e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 365e2cb1decSSalil Mehta tqp->dev = &hdev->pdev->dev; 366e2cb1decSSalil Mehta tqp->index = i; 367e2cb1decSSalil Mehta 368e2cb1decSSalil Mehta tqp->q.ae_algo = &ae_algovf; 369e2cb1decSSalil Mehta tqp->q.buf_size = hdev->rx_buf_len; 370c0425944SPeng Li tqp->q.tx_desc_num = hdev->num_tx_desc; 371c0425944SPeng Li tqp->q.rx_desc_num = hdev->num_rx_desc; 372e2cb1decSSalil Mehta tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 373e2cb1decSSalil Mehta i * HCLGEVF_TQP_REG_SIZE; 374e2cb1decSSalil Mehta 375e2cb1decSSalil Mehta tqp++; 376e2cb1decSSalil Mehta } 377e2cb1decSSalil Mehta 378e2cb1decSSalil Mehta return 0; 379e2cb1decSSalil Mehta } 380e2cb1decSSalil Mehta 381e2cb1decSSalil Mehta static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 382e2cb1decSSalil Mehta { 383e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 384e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo; 385e2cb1decSSalil Mehta u16 new_tqps = hdev->num_tqps; 386e2cb1decSSalil Mehta int i; 387e2cb1decSSalil Mehta 388e2cb1decSSalil Mehta kinfo = &nic->kinfo; 389e2cb1decSSalil Mehta kinfo->num_tc = 0; 390c0425944SPeng Li kinfo->num_tx_desc = hdev->num_tx_desc; 391c0425944SPeng Li kinfo->num_rx_desc = hdev->num_rx_desc; 392e2cb1decSSalil Mehta kinfo->rx_buf_len = hdev->rx_buf_len; 393e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 394e2cb1decSSalil Mehta if (hdev->hw_tc_map & BIT(i)) 395e2cb1decSSalil Mehta kinfo->num_tc++; 396e2cb1decSSalil Mehta 397e2cb1decSSalil Mehta kinfo->rss_size 398e2cb1decSSalil Mehta = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 399e2cb1decSSalil Mehta new_tqps = kinfo->rss_size * kinfo->num_tc; 400e2cb1decSSalil Mehta kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 401e2cb1decSSalil Mehta 402e2cb1decSSalil Mehta kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 403e2cb1decSSalil Mehta sizeof(struct hnae3_queue *), GFP_KERNEL); 404e2cb1decSSalil Mehta if (!kinfo->tqp) 405e2cb1decSSalil Mehta return -ENOMEM; 406e2cb1decSSalil Mehta 407e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 408e2cb1decSSalil Mehta hdev->htqp[i].q.handle = &hdev->nic; 409e2cb1decSSalil Mehta hdev->htqp[i].q.tqp_index = i; 410e2cb1decSSalil Mehta kinfo->tqp[i] = &hdev->htqp[i].q; 411e2cb1decSSalil Mehta } 412e2cb1decSSalil Mehta 413e2cb1decSSalil Mehta return 0; 414e2cb1decSSalil Mehta } 415e2cb1decSSalil Mehta 416e2cb1decSSalil Mehta static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 417e2cb1decSSalil Mehta { 418e2cb1decSSalil Mehta int status; 419e2cb1decSSalil Mehta u8 resp_msg; 420e2cb1decSSalil Mehta 421e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 42263cbf7a9SYufeng Mo 0, false, &resp_msg, sizeof(resp_msg)); 423e2cb1decSSalil Mehta if (status) 424e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 425e2cb1decSSalil Mehta "VF failed to fetch link status(%d) from PF", status); 426e2cb1decSSalil Mehta } 427e2cb1decSSalil Mehta 428e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 429e2cb1decSSalil Mehta { 43045e92b7eSPeng Li struct hnae3_handle *rhandle = &hdev->roce; 431e2cb1decSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 43245e92b7eSPeng Li struct hnae3_client *rclient; 433e2cb1decSSalil Mehta struct hnae3_client *client; 434e2cb1decSSalil Mehta 435e2cb1decSSalil Mehta client = handle->client; 43645e92b7eSPeng Li rclient = hdev->roce_client; 437e2cb1decSSalil Mehta 438582d37bbSPeng Li link_state = 439582d37bbSPeng Li test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 440582d37bbSPeng Li 441e2cb1decSSalil Mehta if (link_state != hdev->hw.mac.link) { 442e2cb1decSSalil Mehta client->ops->link_status_change(handle, !!link_state); 44345e92b7eSPeng Li if (rclient && rclient->ops->link_status_change) 44445e92b7eSPeng Li rclient->ops->link_status_change(rhandle, !!link_state); 445e2cb1decSSalil Mehta hdev->hw.mac.link = link_state; 446e2cb1decSSalil Mehta } 447e2cb1decSSalil Mehta } 448e2cb1decSSalil Mehta 449538abaf3SYueHaibing static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 4509194d18bSliuzhongzhu { 4519194d18bSliuzhongzhu #define HCLGEVF_ADVERTISING 0 4529194d18bSliuzhongzhu #define HCLGEVF_SUPPORTED 1 4539194d18bSliuzhongzhu u8 send_msg; 4549194d18bSliuzhongzhu u8 resp_msg; 4559194d18bSliuzhongzhu 4569194d18bSliuzhongzhu send_msg = HCLGEVF_ADVERTISING; 45763cbf7a9SYufeng Mo hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 45863cbf7a9SYufeng Mo &send_msg, sizeof(send_msg), false, 45963cbf7a9SYufeng Mo &resp_msg, sizeof(resp_msg)); 4609194d18bSliuzhongzhu send_msg = HCLGEVF_SUPPORTED; 46163cbf7a9SYufeng Mo hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 46263cbf7a9SYufeng Mo &send_msg, sizeof(send_msg), false, 46363cbf7a9SYufeng Mo &resp_msg, sizeof(resp_msg)); 4649194d18bSliuzhongzhu } 4659194d18bSliuzhongzhu 466e2cb1decSSalil Mehta static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 467e2cb1decSSalil Mehta { 468e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 469e2cb1decSSalil Mehta int ret; 470e2cb1decSSalil Mehta 471e2cb1decSSalil Mehta nic->ae_algo = &ae_algovf; 472e2cb1decSSalil Mehta nic->pdev = hdev->pdev; 473e2cb1decSSalil Mehta nic->numa_node_mask = hdev->numa_node_mask; 474424eb834SSalil Mehta nic->flags |= HNAE3_SUPPORT_VF; 475e2cb1decSSalil Mehta 476e2cb1decSSalil Mehta ret = hclgevf_knic_setup(hdev); 477e2cb1decSSalil Mehta if (ret) 478e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 479e2cb1decSSalil Mehta ret); 480e2cb1decSSalil Mehta return ret; 481e2cb1decSSalil Mehta } 482e2cb1decSSalil Mehta 483e2cb1decSSalil Mehta static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 484e2cb1decSSalil Mehta { 48536cbbdf6SPeng Li if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 48636cbbdf6SPeng Li dev_warn(&hdev->pdev->dev, 48736cbbdf6SPeng Li "vector(vector_id %d) has been freed.\n", vector_id); 48836cbbdf6SPeng Li return; 48936cbbdf6SPeng Li } 49036cbbdf6SPeng Li 491e2cb1decSSalil Mehta hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 492e2cb1decSSalil Mehta hdev->num_msi_left += 1; 493e2cb1decSSalil Mehta hdev->num_msi_used -= 1; 494e2cb1decSSalil Mehta } 495e2cb1decSSalil Mehta 496e2cb1decSSalil Mehta static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 497e2cb1decSSalil Mehta struct hnae3_vector_info *vector_info) 498e2cb1decSSalil Mehta { 499e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 500e2cb1decSSalil Mehta struct hnae3_vector_info *vector = vector_info; 501e2cb1decSSalil Mehta int alloc = 0; 502e2cb1decSSalil Mehta int i, j; 503e2cb1decSSalil Mehta 504e2cb1decSSalil Mehta vector_num = min(hdev->num_msi_left, vector_num); 505e2cb1decSSalil Mehta 506e2cb1decSSalil Mehta for (j = 0; j < vector_num; j++) { 507e2cb1decSSalil Mehta for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 508e2cb1decSSalil Mehta if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 509e2cb1decSSalil Mehta vector->vector = pci_irq_vector(hdev->pdev, i); 510e2cb1decSSalil Mehta vector->io_addr = hdev->hw.io_base + 511e2cb1decSSalil Mehta HCLGEVF_VECTOR_REG_BASE + 512e2cb1decSSalil Mehta (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 513e2cb1decSSalil Mehta hdev->vector_status[i] = 0; 514e2cb1decSSalil Mehta hdev->vector_irq[i] = vector->vector; 515e2cb1decSSalil Mehta 516e2cb1decSSalil Mehta vector++; 517e2cb1decSSalil Mehta alloc++; 518e2cb1decSSalil Mehta 519e2cb1decSSalil Mehta break; 520e2cb1decSSalil Mehta } 521e2cb1decSSalil Mehta } 522e2cb1decSSalil Mehta } 523e2cb1decSSalil Mehta hdev->num_msi_left -= alloc; 524e2cb1decSSalil Mehta hdev->num_msi_used += alloc; 525e2cb1decSSalil Mehta 526e2cb1decSSalil Mehta return alloc; 527e2cb1decSSalil Mehta } 528e2cb1decSSalil Mehta 529e2cb1decSSalil Mehta static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 530e2cb1decSSalil Mehta { 531e2cb1decSSalil Mehta int i; 532e2cb1decSSalil Mehta 533e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 534e2cb1decSSalil Mehta if (vector == hdev->vector_irq[i]) 535e2cb1decSSalil Mehta return i; 536e2cb1decSSalil Mehta 537e2cb1decSSalil Mehta return -EINVAL; 538e2cb1decSSalil Mehta } 539e2cb1decSSalil Mehta 540374ad291SJian Shen static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 541374ad291SJian Shen const u8 hfunc, const u8 *key) 542374ad291SJian Shen { 543374ad291SJian Shen struct hclgevf_rss_config_cmd *req; 544374ad291SJian Shen struct hclgevf_desc desc; 5453caf772bSYufeng Mo int key_offset = 0; 5463caf772bSYufeng Mo int key_counts; 547374ad291SJian Shen int key_size; 548374ad291SJian Shen int ret; 549374ad291SJian Shen 5503caf772bSYufeng Mo key_counts = HCLGEVF_RSS_KEY_SIZE; 551374ad291SJian Shen req = (struct hclgevf_rss_config_cmd *)desc.data; 552374ad291SJian Shen 5533caf772bSYufeng Mo while (key_counts) { 554374ad291SJian Shen hclgevf_cmd_setup_basic_desc(&desc, 555374ad291SJian Shen HCLGEVF_OPC_RSS_GENERIC_CONFIG, 556374ad291SJian Shen false); 557374ad291SJian Shen 558374ad291SJian Shen req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 559374ad291SJian Shen req->hash_config |= 560374ad291SJian Shen (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 561374ad291SJian Shen 5623caf772bSYufeng Mo key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts); 563374ad291SJian Shen memcpy(req->hash_key, 564374ad291SJian Shen key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 565374ad291SJian Shen 5663caf772bSYufeng Mo key_counts -= key_size; 5673caf772bSYufeng Mo key_offset++; 568374ad291SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 569374ad291SJian Shen if (ret) { 570374ad291SJian Shen dev_err(&hdev->pdev->dev, 571374ad291SJian Shen "Configure RSS config fail, status = %d\n", 572374ad291SJian Shen ret); 573374ad291SJian Shen return ret; 574374ad291SJian Shen } 575374ad291SJian Shen } 576374ad291SJian Shen 577374ad291SJian Shen return 0; 578374ad291SJian Shen } 579374ad291SJian Shen 580e2cb1decSSalil Mehta static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 581e2cb1decSSalil Mehta { 582e2cb1decSSalil Mehta return HCLGEVF_RSS_KEY_SIZE; 583e2cb1decSSalil Mehta } 584e2cb1decSSalil Mehta 585e2cb1decSSalil Mehta static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 586e2cb1decSSalil Mehta { 587e2cb1decSSalil Mehta return HCLGEVF_RSS_IND_TBL_SIZE; 588e2cb1decSSalil Mehta } 589e2cb1decSSalil Mehta 590e2cb1decSSalil Mehta static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 591e2cb1decSSalil Mehta { 592e2cb1decSSalil Mehta const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 593e2cb1decSSalil Mehta struct hclgevf_rss_indirection_table_cmd *req; 594e2cb1decSSalil Mehta struct hclgevf_desc desc; 595e2cb1decSSalil Mehta int status; 596e2cb1decSSalil Mehta int i, j; 597e2cb1decSSalil Mehta 598e2cb1decSSalil Mehta req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 599e2cb1decSSalil Mehta 600e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 601e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 602e2cb1decSSalil Mehta false); 603e2cb1decSSalil Mehta req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 604e2cb1decSSalil Mehta req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 605e2cb1decSSalil Mehta for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 606e2cb1decSSalil Mehta req->rss_result[j] = 607e2cb1decSSalil Mehta indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 608e2cb1decSSalil Mehta 609e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 610e2cb1decSSalil Mehta if (status) { 611e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 612e2cb1decSSalil Mehta "VF failed(=%d) to set RSS indirection table\n", 613e2cb1decSSalil Mehta status); 614e2cb1decSSalil Mehta return status; 615e2cb1decSSalil Mehta } 616e2cb1decSSalil Mehta } 617e2cb1decSSalil Mehta 618e2cb1decSSalil Mehta return 0; 619e2cb1decSSalil Mehta } 620e2cb1decSSalil Mehta 621e2cb1decSSalil Mehta static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 622e2cb1decSSalil Mehta { 623e2cb1decSSalil Mehta struct hclgevf_rss_tc_mode_cmd *req; 624e2cb1decSSalil Mehta u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 625e2cb1decSSalil Mehta u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 626e2cb1decSSalil Mehta u16 tc_size[HCLGEVF_MAX_TC_NUM]; 627e2cb1decSSalil Mehta struct hclgevf_desc desc; 628e2cb1decSSalil Mehta u16 roundup_size; 629e2cb1decSSalil Mehta int status; 630e2cb1decSSalil Mehta int i; 631e2cb1decSSalil Mehta 632e2cb1decSSalil Mehta req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 633e2cb1decSSalil Mehta 634e2cb1decSSalil Mehta roundup_size = roundup_pow_of_two(rss_size); 635e2cb1decSSalil Mehta roundup_size = ilog2(roundup_size); 636e2cb1decSSalil Mehta 637e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 638e2cb1decSSalil Mehta tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 639e2cb1decSSalil Mehta tc_size[i] = roundup_size; 640e2cb1decSSalil Mehta tc_offset[i] = rss_size * i; 641e2cb1decSSalil Mehta } 642e2cb1decSSalil Mehta 643e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 644e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 645e4e87715SPeng Li hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 646e2cb1decSSalil Mehta (tc_valid[i] & 0x1)); 647e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 648e2cb1decSSalil Mehta HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 649e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 650e2cb1decSSalil Mehta HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 651e2cb1decSSalil Mehta } 652e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 653e2cb1decSSalil Mehta if (status) 654e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 655e2cb1decSSalil Mehta "VF failed(=%d) to set rss tc mode\n", status); 656e2cb1decSSalil Mehta 657e2cb1decSSalil Mehta return status; 658e2cb1decSSalil Mehta } 659e2cb1decSSalil Mehta 660a638b1d8SJian Shen /* for revision 0x20, vf shared the same rss config with pf */ 661a638b1d8SJian Shen static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 662a638b1d8SJian Shen { 663a638b1d8SJian Shen #define HCLGEVF_RSS_MBX_RESP_LEN 8 664a638b1d8SJian Shen 665a638b1d8SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 666a638b1d8SJian Shen u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 667a638b1d8SJian Shen u16 msg_num, hash_key_index; 668a638b1d8SJian Shen u8 index; 669a638b1d8SJian Shen int ret; 670a638b1d8SJian Shen 671a638b1d8SJian Shen msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 672a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN; 673a638b1d8SJian Shen for (index = 0; index < msg_num; index++) { 674a638b1d8SJian Shen ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_RSS_KEY, 0, 675a638b1d8SJian Shen &index, sizeof(index), 676a638b1d8SJian Shen true, resp_msg, 677a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN); 678a638b1d8SJian Shen if (ret) { 679a638b1d8SJian Shen dev_err(&hdev->pdev->dev, 680a638b1d8SJian Shen "VF get rss hash key from PF failed, ret=%d", 681a638b1d8SJian Shen ret); 682a638b1d8SJian Shen return ret; 683a638b1d8SJian Shen } 684a638b1d8SJian Shen 685a638b1d8SJian Shen hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 686a638b1d8SJian Shen if (index == msg_num - 1) 687a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 688a638b1d8SJian Shen &resp_msg[0], 689a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE - hash_key_index); 690a638b1d8SJian Shen else 691a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 692a638b1d8SJian Shen &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 693a638b1d8SJian Shen } 694a638b1d8SJian Shen 695a638b1d8SJian Shen return 0; 696a638b1d8SJian Shen } 697a638b1d8SJian Shen 698e2cb1decSSalil Mehta static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 699e2cb1decSSalil Mehta u8 *hfunc) 700e2cb1decSSalil Mehta { 701e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 702e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 703a638b1d8SJian Shen int i, ret; 704e2cb1decSSalil Mehta 705374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 706374ad291SJian Shen /* Get hash algorithm */ 707374ad291SJian Shen if (hfunc) { 708374ad291SJian Shen switch (rss_cfg->hash_algo) { 709374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 710374ad291SJian Shen *hfunc = ETH_RSS_HASH_TOP; 711374ad291SJian Shen break; 712374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 713374ad291SJian Shen *hfunc = ETH_RSS_HASH_XOR; 714374ad291SJian Shen break; 715374ad291SJian Shen default: 716374ad291SJian Shen *hfunc = ETH_RSS_HASH_UNKNOWN; 717374ad291SJian Shen break; 718374ad291SJian Shen } 719374ad291SJian Shen } 720374ad291SJian Shen 721374ad291SJian Shen /* Get the RSS Key required by the user */ 722374ad291SJian Shen if (key) 723374ad291SJian Shen memcpy(key, rss_cfg->rss_hash_key, 724374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 725a638b1d8SJian Shen } else { 726a638b1d8SJian Shen if (hfunc) 727a638b1d8SJian Shen *hfunc = ETH_RSS_HASH_TOP; 728a638b1d8SJian Shen if (key) { 729a638b1d8SJian Shen ret = hclgevf_get_rss_hash_key(hdev); 730a638b1d8SJian Shen if (ret) 731a638b1d8SJian Shen return ret; 732a638b1d8SJian Shen memcpy(key, rss_cfg->rss_hash_key, 733a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE); 734a638b1d8SJian Shen } 735374ad291SJian Shen } 736374ad291SJian Shen 737e2cb1decSSalil Mehta if (indir) 738e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 739e2cb1decSSalil Mehta indir[i] = rss_cfg->rss_indirection_tbl[i]; 740e2cb1decSSalil Mehta 741374ad291SJian Shen return 0; 742e2cb1decSSalil Mehta } 743e2cb1decSSalil Mehta 744e2cb1decSSalil Mehta static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 745e2cb1decSSalil Mehta const u8 *key, const u8 hfunc) 746e2cb1decSSalil Mehta { 747e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 748e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 749374ad291SJian Shen int ret, i; 750374ad291SJian Shen 751374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 752374ad291SJian Shen /* Set the RSS Hash Key if specififed by the user */ 753374ad291SJian Shen if (key) { 754374ad291SJian Shen switch (hfunc) { 755374ad291SJian Shen case ETH_RSS_HASH_TOP: 756374ad291SJian Shen rss_cfg->hash_algo = 757374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 758374ad291SJian Shen break; 759374ad291SJian Shen case ETH_RSS_HASH_XOR: 760374ad291SJian Shen rss_cfg->hash_algo = 761374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_SIMPLE; 762374ad291SJian Shen break; 763374ad291SJian Shen case ETH_RSS_HASH_NO_CHANGE: 764374ad291SJian Shen break; 765374ad291SJian Shen default: 766374ad291SJian Shen return -EINVAL; 767374ad291SJian Shen } 768374ad291SJian Shen 769374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 770374ad291SJian Shen key); 771374ad291SJian Shen if (ret) 772374ad291SJian Shen return ret; 773374ad291SJian Shen 774374ad291SJian Shen /* Update the shadow RSS key with user specified qids */ 775374ad291SJian Shen memcpy(rss_cfg->rss_hash_key, key, 776374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 777374ad291SJian Shen } 778374ad291SJian Shen } 779e2cb1decSSalil Mehta 780e2cb1decSSalil Mehta /* update the shadow RSS table with user specified qids */ 781e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 782e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = indir[i]; 783e2cb1decSSalil Mehta 784e2cb1decSSalil Mehta /* update the hardware */ 785e2cb1decSSalil Mehta return hclgevf_set_rss_indir_table(hdev); 786e2cb1decSSalil Mehta } 787e2cb1decSSalil Mehta 788d97b3072SJian Shen static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 789d97b3072SJian Shen { 790d97b3072SJian Shen u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 791d97b3072SJian Shen 792d97b3072SJian Shen if (nfc->data & RXH_L4_B_2_3) 793d97b3072SJian Shen hash_sets |= HCLGEVF_D_PORT_BIT; 794d97b3072SJian Shen else 795d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_PORT_BIT; 796d97b3072SJian Shen 797d97b3072SJian Shen if (nfc->data & RXH_IP_SRC) 798d97b3072SJian Shen hash_sets |= HCLGEVF_S_IP_BIT; 799d97b3072SJian Shen else 800d97b3072SJian Shen hash_sets &= ~HCLGEVF_S_IP_BIT; 801d97b3072SJian Shen 802d97b3072SJian Shen if (nfc->data & RXH_IP_DST) 803d97b3072SJian Shen hash_sets |= HCLGEVF_D_IP_BIT; 804d97b3072SJian Shen else 805d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_IP_BIT; 806d97b3072SJian Shen 807d97b3072SJian Shen if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 808d97b3072SJian Shen hash_sets |= HCLGEVF_V_TAG_BIT; 809d97b3072SJian Shen 810d97b3072SJian Shen return hash_sets; 811d97b3072SJian Shen } 812d97b3072SJian Shen 813d97b3072SJian Shen static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 814d97b3072SJian Shen struct ethtool_rxnfc *nfc) 815d97b3072SJian Shen { 816d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 817d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 818d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 819d97b3072SJian Shen struct hclgevf_desc desc; 820d97b3072SJian Shen u8 tuple_sets; 821d97b3072SJian Shen int ret; 822d97b3072SJian Shen 823d97b3072SJian Shen if (handle->pdev->revision == 0x20) 824d97b3072SJian Shen return -EOPNOTSUPP; 825d97b3072SJian Shen 826d97b3072SJian Shen if (nfc->data & 827d97b3072SJian Shen ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 828d97b3072SJian Shen return -EINVAL; 829d97b3072SJian Shen 830d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 831d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 832d97b3072SJian Shen 833d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 834d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 835d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 836d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 837d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 838d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 839d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 840d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 841d97b3072SJian Shen 842d97b3072SJian Shen tuple_sets = hclgevf_get_rss_hash_bits(nfc); 843d97b3072SJian Shen switch (nfc->flow_type) { 844d97b3072SJian Shen case TCP_V4_FLOW: 845d97b3072SJian Shen req->ipv4_tcp_en = tuple_sets; 846d97b3072SJian Shen break; 847d97b3072SJian Shen case TCP_V6_FLOW: 848d97b3072SJian Shen req->ipv6_tcp_en = tuple_sets; 849d97b3072SJian Shen break; 850d97b3072SJian Shen case UDP_V4_FLOW: 851d97b3072SJian Shen req->ipv4_udp_en = tuple_sets; 852d97b3072SJian Shen break; 853d97b3072SJian Shen case UDP_V6_FLOW: 854d97b3072SJian Shen req->ipv6_udp_en = tuple_sets; 855d97b3072SJian Shen break; 856d97b3072SJian Shen case SCTP_V4_FLOW: 857d97b3072SJian Shen req->ipv4_sctp_en = tuple_sets; 858d97b3072SJian Shen break; 859d97b3072SJian Shen case SCTP_V6_FLOW: 860d97b3072SJian Shen if ((nfc->data & RXH_L4_B_0_1) || 861d97b3072SJian Shen (nfc->data & RXH_L4_B_2_3)) 862d97b3072SJian Shen return -EINVAL; 863d97b3072SJian Shen 864d97b3072SJian Shen req->ipv6_sctp_en = tuple_sets; 865d97b3072SJian Shen break; 866d97b3072SJian Shen case IPV4_FLOW: 867d97b3072SJian Shen req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 868d97b3072SJian Shen break; 869d97b3072SJian Shen case IPV6_FLOW: 870d97b3072SJian Shen req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 871d97b3072SJian Shen break; 872d97b3072SJian Shen default: 873d97b3072SJian Shen return -EINVAL; 874d97b3072SJian Shen } 875d97b3072SJian Shen 876d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 877d97b3072SJian Shen if (ret) { 878d97b3072SJian Shen dev_err(&hdev->pdev->dev, 879d97b3072SJian Shen "Set rss tuple fail, status = %d\n", ret); 880d97b3072SJian Shen return ret; 881d97b3072SJian Shen } 882d97b3072SJian Shen 883d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 884d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 885d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 886d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 887d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 888d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 889d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 890d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 891d97b3072SJian Shen return 0; 892d97b3072SJian Shen } 893d97b3072SJian Shen 894d97b3072SJian Shen static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 895d97b3072SJian Shen struct ethtool_rxnfc *nfc) 896d97b3072SJian Shen { 897d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 898d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 899d97b3072SJian Shen u8 tuple_sets; 900d97b3072SJian Shen 901d97b3072SJian Shen if (handle->pdev->revision == 0x20) 902d97b3072SJian Shen return -EOPNOTSUPP; 903d97b3072SJian Shen 904d97b3072SJian Shen nfc->data = 0; 905d97b3072SJian Shen 906d97b3072SJian Shen switch (nfc->flow_type) { 907d97b3072SJian Shen case TCP_V4_FLOW: 908d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 909d97b3072SJian Shen break; 910d97b3072SJian Shen case UDP_V4_FLOW: 911d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 912d97b3072SJian Shen break; 913d97b3072SJian Shen case TCP_V6_FLOW: 914d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 915d97b3072SJian Shen break; 916d97b3072SJian Shen case UDP_V6_FLOW: 917d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 918d97b3072SJian Shen break; 919d97b3072SJian Shen case SCTP_V4_FLOW: 920d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 921d97b3072SJian Shen break; 922d97b3072SJian Shen case SCTP_V6_FLOW: 923d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 924d97b3072SJian Shen break; 925d97b3072SJian Shen case IPV4_FLOW: 926d97b3072SJian Shen case IPV6_FLOW: 927d97b3072SJian Shen tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 928d97b3072SJian Shen break; 929d97b3072SJian Shen default: 930d97b3072SJian Shen return -EINVAL; 931d97b3072SJian Shen } 932d97b3072SJian Shen 933d97b3072SJian Shen if (!tuple_sets) 934d97b3072SJian Shen return 0; 935d97b3072SJian Shen 936d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_PORT_BIT) 937d97b3072SJian Shen nfc->data |= RXH_L4_B_2_3; 938d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_PORT_BIT) 939d97b3072SJian Shen nfc->data |= RXH_L4_B_0_1; 940d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_IP_BIT) 941d97b3072SJian Shen nfc->data |= RXH_IP_DST; 942d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_IP_BIT) 943d97b3072SJian Shen nfc->data |= RXH_IP_SRC; 944d97b3072SJian Shen 945d97b3072SJian Shen return 0; 946d97b3072SJian Shen } 947d97b3072SJian Shen 948d97b3072SJian Shen static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 949d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg) 950d97b3072SJian Shen { 951d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 952d97b3072SJian Shen struct hclgevf_desc desc; 953d97b3072SJian Shen int ret; 954d97b3072SJian Shen 955d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 956d97b3072SJian Shen 957d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 958d97b3072SJian Shen 959d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 960d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 961d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 962d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 963d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 964d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 965d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 966d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 967d97b3072SJian Shen 968d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 969d97b3072SJian Shen if (ret) 970d97b3072SJian Shen dev_err(&hdev->pdev->dev, 971d97b3072SJian Shen "Configure rss input fail, status = %d\n", ret); 972d97b3072SJian Shen return ret; 973d97b3072SJian Shen } 974d97b3072SJian Shen 975e2cb1decSSalil Mehta static int hclgevf_get_tc_size(struct hnae3_handle *handle) 976e2cb1decSSalil Mehta { 977e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 978e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 979e2cb1decSSalil Mehta 980e2cb1decSSalil Mehta return rss_cfg->rss_size; 981e2cb1decSSalil Mehta } 982e2cb1decSSalil Mehta 983e2cb1decSSalil Mehta static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 984b204bc74SPeng Li int vector_id, 985e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 986e2cb1decSSalil Mehta { 987e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 988e2cb1decSSalil Mehta struct hnae3_ring_chain_node *node; 989e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 990e2cb1decSSalil Mehta struct hclgevf_desc desc; 991b204bc74SPeng Li int i = 0; 992e2cb1decSSalil Mehta int status; 993e2cb1decSSalil Mehta u8 type; 994e2cb1decSSalil Mehta 995e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 996e2cb1decSSalil Mehta 997e2cb1decSSalil Mehta for (node = ring_chain; node; node = node->next) { 9985d02a58dSYunsheng Lin int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 9995d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 10005d02a58dSYunsheng Lin 10015d02a58dSYunsheng Lin if (i == 0) { 10025d02a58dSYunsheng Lin hclgevf_cmd_setup_basic_desc(&desc, 10035d02a58dSYunsheng Lin HCLGEVF_OPC_MBX_VF_TO_PF, 10045d02a58dSYunsheng Lin false); 10055d02a58dSYunsheng Lin type = en ? 10065d02a58dSYunsheng Lin HCLGE_MBX_MAP_RING_TO_VECTOR : 10075d02a58dSYunsheng Lin HCLGE_MBX_UNMAP_RING_TO_VECTOR; 10085d02a58dSYunsheng Lin req->msg[0] = type; 10095d02a58dSYunsheng Lin req->msg[1] = vector_id; 10105d02a58dSYunsheng Lin } 10115d02a58dSYunsheng Lin 10125d02a58dSYunsheng Lin req->msg[idx_offset] = 1013e4e87715SPeng Li hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 10145d02a58dSYunsheng Lin req->msg[idx_offset + 1] = node->tqp_index; 1015e4e87715SPeng Li req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 101679eee410SFuyun Liang HNAE3_RING_GL_IDX_M, 101779eee410SFuyun Liang HNAE3_RING_GL_IDX_S); 101879eee410SFuyun Liang 10195d02a58dSYunsheng Lin i++; 10205d02a58dSYunsheng Lin if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 10215d02a58dSYunsheng Lin HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 10225d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 10235d02a58dSYunsheng Lin !node->next) { 1024e2cb1decSSalil Mehta req->msg[2] = i; 1025e2cb1decSSalil Mehta 1026e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1027e2cb1decSSalil Mehta if (status) { 1028e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1029e2cb1decSSalil Mehta "Map TQP fail, status is %d.\n", 1030e2cb1decSSalil Mehta status); 1031e2cb1decSSalil Mehta return status; 1032e2cb1decSSalil Mehta } 1033e2cb1decSSalil Mehta i = 0; 1034e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 1035e2cb1decSSalil Mehta HCLGEVF_OPC_MBX_VF_TO_PF, 1036e2cb1decSSalil Mehta false); 1037e2cb1decSSalil Mehta req->msg[0] = type; 1038e2cb1decSSalil Mehta req->msg[1] = vector_id; 1039e2cb1decSSalil Mehta } 1040e2cb1decSSalil Mehta } 1041e2cb1decSSalil Mehta 1042e2cb1decSSalil Mehta return 0; 1043e2cb1decSSalil Mehta } 1044e2cb1decSSalil Mehta 1045e2cb1decSSalil Mehta static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1046e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1047e2cb1decSSalil Mehta { 1048b204bc74SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1049b204bc74SPeng Li int vector_id; 1050b204bc74SPeng Li 1051b204bc74SPeng Li vector_id = hclgevf_get_vector_index(hdev, vector); 1052b204bc74SPeng Li if (vector_id < 0) { 1053b204bc74SPeng Li dev_err(&handle->pdev->dev, 1054b204bc74SPeng Li "Get vector index fail. ret =%d\n", vector_id); 1055b204bc74SPeng Li return vector_id; 1056b204bc74SPeng Li } 1057b204bc74SPeng Li 1058b204bc74SPeng Li return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1059e2cb1decSSalil Mehta } 1060e2cb1decSSalil Mehta 1061e2cb1decSSalil Mehta static int hclgevf_unmap_ring_from_vector( 1062e2cb1decSSalil Mehta struct hnae3_handle *handle, 1063e2cb1decSSalil Mehta int vector, 1064e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1065e2cb1decSSalil Mehta { 1066e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1067e2cb1decSSalil Mehta int ret, vector_id; 1068e2cb1decSSalil Mehta 1069dea846e8SHuazhong Tan if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1070dea846e8SHuazhong Tan return 0; 1071dea846e8SHuazhong Tan 1072e2cb1decSSalil Mehta vector_id = hclgevf_get_vector_index(hdev, vector); 1073e2cb1decSSalil Mehta if (vector_id < 0) { 1074e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1075e2cb1decSSalil Mehta "Get vector index fail. ret =%d\n", vector_id); 1076e2cb1decSSalil Mehta return vector_id; 1077e2cb1decSSalil Mehta } 1078e2cb1decSSalil Mehta 1079b204bc74SPeng Li ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 10800d3e6631SYunsheng Lin if (ret) 1081e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1082e2cb1decSSalil Mehta "Unmap ring from vector fail. vector=%d, ret =%d\n", 1083e2cb1decSSalil Mehta vector_id, 1084e2cb1decSSalil Mehta ret); 10850d3e6631SYunsheng Lin 1086e2cb1decSSalil Mehta return ret; 1087e2cb1decSSalil Mehta } 1088e2cb1decSSalil Mehta 10890d3e6631SYunsheng Lin static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 10900d3e6631SYunsheng Lin { 10910d3e6631SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 109203718db9SYunsheng Lin int vector_id; 10930d3e6631SYunsheng Lin 109403718db9SYunsheng Lin vector_id = hclgevf_get_vector_index(hdev, vector); 109503718db9SYunsheng Lin if (vector_id < 0) { 109603718db9SYunsheng Lin dev_err(&handle->pdev->dev, 109703718db9SYunsheng Lin "hclgevf_put_vector get vector index fail. ret =%d\n", 109803718db9SYunsheng Lin vector_id); 109903718db9SYunsheng Lin return vector_id; 110003718db9SYunsheng Lin } 110103718db9SYunsheng Lin 110203718db9SYunsheng Lin hclgevf_free_vector(hdev, vector_id); 1103e2cb1decSSalil Mehta 1104e2cb1decSSalil Mehta return 0; 1105e2cb1decSSalil Mehta } 1106e2cb1decSSalil Mehta 11073b75c3dfSPeng Li static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1108f01f5559SJian Shen bool en_bc_pmc) 1109e2cb1decSSalil Mehta { 1110e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 1111e2cb1decSSalil Mehta struct hclgevf_desc desc; 1112f01f5559SJian Shen int ret; 1113e2cb1decSSalil Mehta 1114e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1115e2cb1decSSalil Mehta 1116e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 1117e2cb1decSSalil Mehta req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 1118f01f5559SJian Shen req->msg[1] = en_bc_pmc ? 1 : 0; 1119e2cb1decSSalil Mehta 1120f01f5559SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1121f01f5559SJian Shen if (ret) 1122e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1123f01f5559SJian Shen "Set promisc mode fail, status is %d.\n", ret); 1124e2cb1decSSalil Mehta 1125f01f5559SJian Shen return ret; 1126e2cb1decSSalil Mehta } 1127e2cb1decSSalil Mehta 1128f01f5559SJian Shen static int hclgevf_set_promisc_mode(struct hclgevf_dev *hdev, bool en_bc_pmc) 1129e2cb1decSSalil Mehta { 1130f01f5559SJian Shen return hclgevf_cmd_set_promisc_mode(hdev, en_bc_pmc); 1131e2cb1decSSalil Mehta } 1132e2cb1decSSalil Mehta 1133e2cb1decSSalil Mehta static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, int tqp_id, 1134e2cb1decSSalil Mehta int stream_id, bool enable) 1135e2cb1decSSalil Mehta { 1136e2cb1decSSalil Mehta struct hclgevf_cfg_com_tqp_queue_cmd *req; 1137e2cb1decSSalil Mehta struct hclgevf_desc desc; 1138e2cb1decSSalil Mehta int status; 1139e2cb1decSSalil Mehta 1140e2cb1decSSalil Mehta req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1141e2cb1decSSalil Mehta 1142e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1143e2cb1decSSalil Mehta false); 1144e2cb1decSSalil Mehta req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1145e2cb1decSSalil Mehta req->stream_id = cpu_to_le16(stream_id); 1146e2cb1decSSalil Mehta req->enable |= enable << HCLGEVF_TQP_ENABLE_B; 1147e2cb1decSSalil Mehta 1148e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1149e2cb1decSSalil Mehta if (status) 1150e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1151e2cb1decSSalil Mehta "TQP enable fail, status =%d.\n", status); 1152e2cb1decSSalil Mehta 1153e2cb1decSSalil Mehta return status; 1154e2cb1decSSalil Mehta } 1155e2cb1decSSalil Mehta 1156e2cb1decSSalil Mehta static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1157e2cb1decSSalil Mehta { 1158b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1159e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 1160e2cb1decSSalil Mehta int i; 1161e2cb1decSSalil Mehta 1162b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 1163b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1164e2cb1decSSalil Mehta memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1165e2cb1decSSalil Mehta } 1166e2cb1decSSalil Mehta } 1167e2cb1decSSalil Mehta 1168e2cb1decSSalil Mehta static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1169e2cb1decSSalil Mehta { 1170e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1171e2cb1decSSalil Mehta 1172e2cb1decSSalil Mehta ether_addr_copy(p, hdev->hw.mac.mac_addr); 1173e2cb1decSSalil Mehta } 1174e2cb1decSSalil Mehta 117559098055SFuyun Liang static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 117659098055SFuyun Liang bool is_first) 1177e2cb1decSSalil Mehta { 1178e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1179e2cb1decSSalil Mehta u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1180e2cb1decSSalil Mehta u8 *new_mac_addr = (u8 *)p; 1181e2cb1decSSalil Mehta u8 msg_data[ETH_ALEN * 2]; 118259098055SFuyun Liang u16 subcode; 1183e2cb1decSSalil Mehta int status; 1184e2cb1decSSalil Mehta 1185e2cb1decSSalil Mehta ether_addr_copy(msg_data, new_mac_addr); 1186e2cb1decSSalil Mehta ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 1187e2cb1decSSalil Mehta 118859098055SFuyun Liang subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 118959098055SFuyun Liang HCLGE_MBX_MAC_VLAN_UC_MODIFY; 119059098055SFuyun Liang 1191e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 119263cbf7a9SYufeng Mo subcode, msg_data, sizeof(msg_data), 11932097fdefSJian Shen true, NULL, 0); 1194e2cb1decSSalil Mehta if (!status) 1195e2cb1decSSalil Mehta ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1196e2cb1decSSalil Mehta 1197e2cb1decSSalil Mehta return status; 1198e2cb1decSSalil Mehta } 1199e2cb1decSSalil Mehta 1200e2cb1decSSalil Mehta static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1201e2cb1decSSalil Mehta const unsigned char *addr) 1202e2cb1decSSalil Mehta { 1203e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1204e2cb1decSSalil Mehta 1205e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1206e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_ADD, 1207e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1208e2cb1decSSalil Mehta } 1209e2cb1decSSalil Mehta 1210e2cb1decSSalil Mehta static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1211e2cb1decSSalil Mehta const unsigned char *addr) 1212e2cb1decSSalil Mehta { 1213e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1214e2cb1decSSalil Mehta 1215e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1216e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1217e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1218e2cb1decSSalil Mehta } 1219e2cb1decSSalil Mehta 1220e2cb1decSSalil Mehta static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1221e2cb1decSSalil Mehta const unsigned char *addr) 1222e2cb1decSSalil Mehta { 1223e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1224e2cb1decSSalil Mehta 1225e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1226e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_ADD, 1227e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1228e2cb1decSSalil Mehta } 1229e2cb1decSSalil Mehta 1230e2cb1decSSalil Mehta static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1231e2cb1decSSalil Mehta const unsigned char *addr) 1232e2cb1decSSalil Mehta { 1233e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1234e2cb1decSSalil Mehta 1235e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1236e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1237e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1238e2cb1decSSalil Mehta } 1239e2cb1decSSalil Mehta 1240e2cb1decSSalil Mehta static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1241e2cb1decSSalil Mehta __be16 proto, u16 vlan_id, 1242e2cb1decSSalil Mehta bool is_kill) 1243e2cb1decSSalil Mehta { 1244e2cb1decSSalil Mehta #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1245e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1246e2cb1decSSalil Mehta u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1247e2cb1decSSalil Mehta 1248b37ce587SYufeng Mo if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1249e2cb1decSSalil Mehta return -EINVAL; 1250e2cb1decSSalil Mehta 1251e2cb1decSSalil Mehta if (proto != htons(ETH_P_8021Q)) 1252e2cb1decSSalil Mehta return -EPROTONOSUPPORT; 1253e2cb1decSSalil Mehta 1254e2cb1decSSalil Mehta msg_data[0] = is_kill; 1255e2cb1decSSalil Mehta memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1256e2cb1decSSalil Mehta memcpy(&msg_data[3], &proto, sizeof(proto)); 1257e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1258e2cb1decSSalil Mehta HCLGE_MBX_VLAN_FILTER, msg_data, 1259e2cb1decSSalil Mehta HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 1260e2cb1decSSalil Mehta } 1261e2cb1decSSalil Mehta 1262b2641e2aSYunsheng Lin static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1263b2641e2aSYunsheng Lin { 1264b2641e2aSYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1265b2641e2aSYunsheng Lin u8 msg_data; 1266b2641e2aSYunsheng Lin 1267b2641e2aSYunsheng Lin msg_data = enable ? 1 : 0; 1268b2641e2aSYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1269b2641e2aSYunsheng Lin HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1270b2641e2aSYunsheng Lin 1, false, NULL, 0); 1271b2641e2aSYunsheng Lin } 1272b2641e2aSYunsheng Lin 12737fa6be4fSHuazhong Tan static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1274e2cb1decSSalil Mehta { 1275e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1276e2cb1decSSalil Mehta u8 msg_data[2]; 12771a426f8bSPeng Li int ret; 1278e2cb1decSSalil Mehta 127963cbf7a9SYufeng Mo memcpy(msg_data, &queue_id, sizeof(queue_id)); 1280e2cb1decSSalil Mehta 12811a426f8bSPeng Li /* disable vf queue before send queue reset msg to PF */ 12821a426f8bSPeng Li ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 12831a426f8bSPeng Li if (ret) 12847fa6be4fSHuazhong Tan return ret; 12851a426f8bSPeng Li 12867fa6be4fSHuazhong Tan return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 128763cbf7a9SYufeng Mo sizeof(msg_data), true, NULL, 0); 1288e2cb1decSSalil Mehta } 1289e2cb1decSSalil Mehta 1290818f1675SYunsheng Lin static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1291818f1675SYunsheng Lin { 1292818f1675SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1293818f1675SYunsheng Lin 1294818f1675SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu, 1295818f1675SYunsheng Lin sizeof(new_mtu), true, NULL, 0); 1296818f1675SYunsheng Lin } 1297818f1675SYunsheng Lin 12986988eb2aSSalil Mehta static int hclgevf_notify_client(struct hclgevf_dev *hdev, 12996988eb2aSSalil Mehta enum hnae3_reset_notify_type type) 13006988eb2aSSalil Mehta { 13016988eb2aSSalil Mehta struct hnae3_client *client = hdev->nic_client; 13026988eb2aSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 13036a5f6fa3SHuazhong Tan int ret; 13046988eb2aSSalil Mehta 130525d1817cSHuazhong Tan if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 130625d1817cSHuazhong Tan !client) 130725d1817cSHuazhong Tan return 0; 130825d1817cSHuazhong Tan 13096988eb2aSSalil Mehta if (!client->ops->reset_notify) 13106988eb2aSSalil Mehta return -EOPNOTSUPP; 13116988eb2aSSalil Mehta 13126a5f6fa3SHuazhong Tan ret = client->ops->reset_notify(handle, type); 13136a5f6fa3SHuazhong Tan if (ret) 13146a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 13156a5f6fa3SHuazhong Tan type, ret); 13166a5f6fa3SHuazhong Tan 13176a5f6fa3SHuazhong Tan return ret; 13186988eb2aSSalil Mehta } 13196988eb2aSSalil Mehta 13206ff3cf07SHuazhong Tan static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 13216ff3cf07SHuazhong Tan { 13226ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 13236ff3cf07SHuazhong Tan 13246ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DONE, &hdev->flr_state); 13256ff3cf07SHuazhong Tan } 13266ff3cf07SHuazhong Tan 13276ff3cf07SHuazhong Tan static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev, 13286ff3cf07SHuazhong Tan unsigned long delay_us, 13296ff3cf07SHuazhong Tan unsigned long wait_cnt) 13306ff3cf07SHuazhong Tan { 13316ff3cf07SHuazhong Tan unsigned long cnt = 0; 13326ff3cf07SHuazhong Tan 13336ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) && 13346ff3cf07SHuazhong Tan cnt++ < wait_cnt) 13356ff3cf07SHuazhong Tan usleep_range(delay_us, delay_us * 2); 13366ff3cf07SHuazhong Tan 13376ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) { 13386ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 13396ff3cf07SHuazhong Tan "flr wait timeout\n"); 13406ff3cf07SHuazhong Tan return -ETIMEDOUT; 13416ff3cf07SHuazhong Tan } 13426ff3cf07SHuazhong Tan 13436ff3cf07SHuazhong Tan return 0; 13446ff3cf07SHuazhong Tan } 13456ff3cf07SHuazhong Tan 13466988eb2aSSalil Mehta static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 13476988eb2aSSalil Mehta { 1348aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_US 20000 1349aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_CNT 2000 1350aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1351aa5c4f17SHuazhong Tan (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1352aa5c4f17SHuazhong Tan 1353aa5c4f17SHuazhong Tan u32 val; 1354aa5c4f17SHuazhong Tan int ret; 13556988eb2aSSalil Mehta 13566988eb2aSSalil Mehta /* wait to check the hardware reset completion status */ 1357aa5c4f17SHuazhong Tan val = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1358aa5c4f17SHuazhong Tan dev_info(&hdev->pdev->dev, "checking vf resetting status: %x\n", val); 1359aa5c4f17SHuazhong Tan 13606ff3cf07SHuazhong Tan if (hdev->reset_type == HNAE3_FLR_RESET) 13616ff3cf07SHuazhong Tan return hclgevf_flr_poll_timeout(hdev, 13626ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_US, 13636ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_CNT); 13646ff3cf07SHuazhong Tan 1365aa5c4f17SHuazhong Tan ret = readl_poll_timeout(hdev->hw.io_base + HCLGEVF_RST_ING, val, 1366aa5c4f17SHuazhong Tan !(val & HCLGEVF_RST_ING_BITS), 1367aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_US, 1368aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 13696988eb2aSSalil Mehta 13706988eb2aSSalil Mehta /* hardware completion status should be available by this time */ 1371aa5c4f17SHuazhong Tan if (ret) { 1372aa5c4f17SHuazhong Tan dev_err(&hdev->pdev->dev, 13736988eb2aSSalil Mehta "could'nt get reset done status from h/w, timeout!\n"); 1374aa5c4f17SHuazhong Tan return ret; 13756988eb2aSSalil Mehta } 13766988eb2aSSalil Mehta 13776988eb2aSSalil Mehta /* we will wait a bit more to let reset of the stack to complete. This 13786988eb2aSSalil Mehta * might happen in case reset assertion was made by PF. Yes, this also 13796988eb2aSSalil Mehta * means we might end up waiting bit more even for VF reset. 13806988eb2aSSalil Mehta */ 13816988eb2aSSalil Mehta msleep(5000); 13826988eb2aSSalil Mehta 13836988eb2aSSalil Mehta return 0; 13846988eb2aSSalil Mehta } 13856988eb2aSSalil Mehta 13866988eb2aSSalil Mehta static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 13876988eb2aSSalil Mehta { 13887a01c897SSalil Mehta int ret; 13897a01c897SSalil Mehta 13906988eb2aSSalil Mehta /* uninitialize the nic client */ 13916a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 13926a5f6fa3SHuazhong Tan if (ret) 13936a5f6fa3SHuazhong Tan return ret; 13946988eb2aSSalil Mehta 13957a01c897SSalil Mehta /* re-initialize the hclge device */ 13969c6f7085SHuazhong Tan ret = hclgevf_reset_hdev(hdev); 13977a01c897SSalil Mehta if (ret) { 13987a01c897SSalil Mehta dev_err(&hdev->pdev->dev, 13997a01c897SSalil Mehta "hclge device re-init failed, VF is disabled!\n"); 14007a01c897SSalil Mehta return ret; 14017a01c897SSalil Mehta } 14026988eb2aSSalil Mehta 14036988eb2aSSalil Mehta /* bring up the nic client again */ 14046a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 14056a5f6fa3SHuazhong Tan if (ret) 14066a5f6fa3SHuazhong Tan return ret; 14076988eb2aSSalil Mehta 14081f609492SYunsheng Lin return hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT); 14096988eb2aSSalil Mehta } 14106988eb2aSSalil Mehta 1411dea846e8SHuazhong Tan static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1412dea846e8SHuazhong Tan { 1413ada13ee3SHuazhong Tan #define HCLGEVF_RESET_SYNC_TIME 100 1414ada13ee3SHuazhong Tan 1415dea846e8SHuazhong Tan int ret = 0; 1416dea846e8SHuazhong Tan 1417dea846e8SHuazhong Tan switch (hdev->reset_type) { 1418dea846e8SHuazhong Tan case HNAE3_VF_FUNC_RESET: 1419dea846e8SHuazhong Tan ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1420dea846e8SHuazhong Tan 0, true, NULL, sizeof(u8)); 1421c88a6e7dSHuazhong Tan hdev->rst_stats.vf_func_rst_cnt++; 1422dea846e8SHuazhong Tan break; 14236ff3cf07SHuazhong Tan case HNAE3_FLR_RESET: 14246ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1425c88a6e7dSHuazhong Tan hdev->rst_stats.flr_rst_cnt++; 14266ff3cf07SHuazhong Tan break; 1427dea846e8SHuazhong Tan default: 1428dea846e8SHuazhong Tan break; 1429dea846e8SHuazhong Tan } 1430dea846e8SHuazhong Tan 1431ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1432ada13ee3SHuazhong Tan /* inform hardware that preparatory work is done */ 1433ada13ee3SHuazhong Tan msleep(HCLGEVF_RESET_SYNC_TIME); 1434ada13ee3SHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 1435ada13ee3SHuazhong Tan HCLGEVF_NIC_CMQ_ENABLE); 1436dea846e8SHuazhong Tan dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1437dea846e8SHuazhong Tan hdev->reset_type, ret); 1438dea846e8SHuazhong Tan 1439dea846e8SHuazhong Tan return ret; 1440dea846e8SHuazhong Tan } 1441dea846e8SHuazhong Tan 14426988eb2aSSalil Mehta static int hclgevf_reset(struct hclgevf_dev *hdev) 14436988eb2aSSalil Mehta { 1444dea846e8SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 14456988eb2aSSalil Mehta int ret; 14466988eb2aSSalil Mehta 1447dea846e8SHuazhong Tan /* Initialize ae_dev reset status as well, in case enet layer wants to 1448dea846e8SHuazhong Tan * know if device is undergoing reset 1449dea846e8SHuazhong Tan */ 1450dea846e8SHuazhong Tan ae_dev->reset_type = hdev->reset_type; 1451c88a6e7dSHuazhong Tan hdev->rst_stats.rst_cnt++; 14526988eb2aSSalil Mehta rtnl_lock(); 14536988eb2aSSalil Mehta 14546988eb2aSSalil Mehta /* bring down the nic to stop any ongoing TX/RX */ 14556a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 14566a5f6fa3SHuazhong Tan if (ret) 14576a5f6fa3SHuazhong Tan goto err_reset_lock; 14586988eb2aSSalil Mehta 145929118ab9SHuazhong Tan rtnl_unlock(); 146029118ab9SHuazhong Tan 14616a5f6fa3SHuazhong Tan ret = hclgevf_reset_prepare_wait(hdev); 14626a5f6fa3SHuazhong Tan if (ret) 14636a5f6fa3SHuazhong Tan goto err_reset; 1464dea846e8SHuazhong Tan 14656988eb2aSSalil Mehta /* check if VF could successfully fetch the hardware reset completion 14666988eb2aSSalil Mehta * status from the hardware 14676988eb2aSSalil Mehta */ 14686988eb2aSSalil Mehta ret = hclgevf_reset_wait(hdev); 14696988eb2aSSalil Mehta if (ret) { 14706988eb2aSSalil Mehta /* can't do much in this situation, will disable VF */ 14716988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, 14726988eb2aSSalil Mehta "VF failed(=%d) to fetch H/W reset completion status\n", 14736988eb2aSSalil Mehta ret); 14746a5f6fa3SHuazhong Tan goto err_reset; 14756988eb2aSSalil Mehta } 14766988eb2aSSalil Mehta 1477c88a6e7dSHuazhong Tan hdev->rst_stats.hw_rst_done_cnt++; 1478c88a6e7dSHuazhong Tan 147929118ab9SHuazhong Tan rtnl_lock(); 148029118ab9SHuazhong Tan 14816988eb2aSSalil Mehta /* now, re-initialize the nic client and ae device*/ 14826988eb2aSSalil Mehta ret = hclgevf_reset_stack(hdev); 14836a5f6fa3SHuazhong Tan if (ret) { 14846988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 14856a5f6fa3SHuazhong Tan goto err_reset_lock; 14866a5f6fa3SHuazhong Tan } 14876988eb2aSSalil Mehta 14886988eb2aSSalil Mehta /* bring up the nic to enable TX/RX again */ 14896a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 14906a5f6fa3SHuazhong Tan if (ret) 14916a5f6fa3SHuazhong Tan goto err_reset_lock; 14926988eb2aSSalil Mehta 14936988eb2aSSalil Mehta rtnl_unlock(); 14946988eb2aSSalil Mehta 1495b644a8d4SHuazhong Tan hdev->last_reset_time = jiffies; 1496b644a8d4SHuazhong Tan ae_dev->reset_type = HNAE3_NONE_RESET; 1497c88a6e7dSHuazhong Tan hdev->rst_stats.rst_done_cnt++; 1498b644a8d4SHuazhong Tan 14996988eb2aSSalil Mehta return ret; 15006a5f6fa3SHuazhong Tan err_reset_lock: 15016a5f6fa3SHuazhong Tan rtnl_unlock(); 15026a5f6fa3SHuazhong Tan err_reset: 15036a5f6fa3SHuazhong Tan /* When VF reset failed, only the higher level reset asserted by PF 15046a5f6fa3SHuazhong Tan * can restore it, so re-initialize the command queue to receive 15056a5f6fa3SHuazhong Tan * this higher reset event. 15066a5f6fa3SHuazhong Tan */ 15076a5f6fa3SHuazhong Tan hclgevf_cmd_init(hdev); 15086a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "failed to reset VF\n"); 1509cf1f2129SHuazhong Tan if (hclgevf_is_reset_pending(hdev)) 1510cf1f2129SHuazhong Tan hclgevf_reset_task_schedule(hdev); 15116a5f6fa3SHuazhong Tan 15126a5f6fa3SHuazhong Tan return ret; 15136988eb2aSSalil Mehta } 15146988eb2aSSalil Mehta 1515720bd583SHuazhong Tan static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1516720bd583SHuazhong Tan unsigned long *addr) 1517720bd583SHuazhong Tan { 1518720bd583SHuazhong Tan enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1519720bd583SHuazhong Tan 1520dea846e8SHuazhong Tan /* return the highest priority reset level amongst all */ 1521b90fcc5bSHuazhong Tan if (test_bit(HNAE3_VF_RESET, addr)) { 1522b90fcc5bSHuazhong Tan rst_level = HNAE3_VF_RESET; 1523b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_RESET, addr); 1524b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1525b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1526b90fcc5bSHuazhong Tan } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1527dea846e8SHuazhong Tan rst_level = HNAE3_VF_FULL_RESET; 1528dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FULL_RESET, addr); 1529dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1530aa5c4f17SHuazhong Tan } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1531aa5c4f17SHuazhong Tan rst_level = HNAE3_VF_PF_FUNC_RESET; 1532aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1533aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1534dea846e8SHuazhong Tan } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1535dea846e8SHuazhong Tan rst_level = HNAE3_VF_FUNC_RESET; 1536dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 15376ff3cf07SHuazhong Tan } else if (test_bit(HNAE3_FLR_RESET, addr)) { 15386ff3cf07SHuazhong Tan rst_level = HNAE3_FLR_RESET; 15396ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_RESET, addr); 1540720bd583SHuazhong Tan } 1541720bd583SHuazhong Tan 1542720bd583SHuazhong Tan return rst_level; 1543720bd583SHuazhong Tan } 1544720bd583SHuazhong Tan 15456ae4e733SShiju Jose static void hclgevf_reset_event(struct pci_dev *pdev, 15466ae4e733SShiju Jose struct hnae3_handle *handle) 15476d4c3981SSalil Mehta { 15486ff3cf07SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 15496ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 15506d4c3981SSalil Mehta 15516d4c3981SSalil Mehta dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 15526d4c3981SSalil Mehta 15536ff3cf07SHuazhong Tan if (hdev->default_reset_request) 15540742ed7cSHuazhong Tan hdev->reset_level = 1555720bd583SHuazhong Tan hclgevf_get_reset_level(hdev, 1556720bd583SHuazhong Tan &hdev->default_reset_request); 1557720bd583SHuazhong Tan else 1558dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 15596d4c3981SSalil Mehta 1560436667d2SSalil Mehta /* reset of this VF requested */ 1561436667d2SSalil Mehta set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1562436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 15636d4c3981SSalil Mehta 15640742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 15656d4c3981SSalil Mehta } 15666d4c3981SSalil Mehta 1567720bd583SHuazhong Tan static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1568720bd583SHuazhong Tan enum hnae3_reset_type rst_type) 1569720bd583SHuazhong Tan { 1570720bd583SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1571720bd583SHuazhong Tan 1572720bd583SHuazhong Tan set_bit(rst_type, &hdev->default_reset_request); 1573720bd583SHuazhong Tan } 1574720bd583SHuazhong Tan 15756ff3cf07SHuazhong Tan static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 15766ff3cf07SHuazhong Tan { 15776ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_MS 100 15786ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_CNT 50 15796ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 15806ff3cf07SHuazhong Tan int cnt = 0; 15816ff3cf07SHuazhong Tan 15826ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 15836ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DONE, &hdev->flr_state); 15846ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request); 15856ff3cf07SHuazhong Tan hclgevf_reset_event(hdev->pdev, NULL); 15866ff3cf07SHuazhong Tan 15876ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) && 15886ff3cf07SHuazhong Tan cnt++ < HCLGEVF_FLR_WAIT_CNT) 15896ff3cf07SHuazhong Tan msleep(HCLGEVF_FLR_WAIT_MS); 15906ff3cf07SHuazhong Tan 15916ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state)) 15926ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 15936ff3cf07SHuazhong Tan "flr wait down timeout: %d\n", cnt); 15946ff3cf07SHuazhong Tan } 15956ff3cf07SHuazhong Tan 1596e2cb1decSSalil Mehta static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1597e2cb1decSSalil Mehta { 1598e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1599e2cb1decSSalil Mehta 1600e2cb1decSSalil Mehta return hdev->fw_version; 1601e2cb1decSSalil Mehta } 1602e2cb1decSSalil Mehta 1603e2cb1decSSalil Mehta static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1604e2cb1decSSalil Mehta { 1605e2cb1decSSalil Mehta struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1606e2cb1decSSalil Mehta 1607e2cb1decSSalil Mehta vector->vector_irq = pci_irq_vector(hdev->pdev, 1608e2cb1decSSalil Mehta HCLGEVF_MISC_VECTOR_NUM); 1609e2cb1decSSalil Mehta vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1610e2cb1decSSalil Mehta /* vector status always valid for Vector 0 */ 1611e2cb1decSSalil Mehta hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1612e2cb1decSSalil Mehta hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1613e2cb1decSSalil Mehta 1614e2cb1decSSalil Mehta hdev->num_msi_left -= 1; 1615e2cb1decSSalil Mehta hdev->num_msi_used += 1; 1616e2cb1decSSalil Mehta } 1617e2cb1decSSalil Mehta 161835a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 161935a1e503SSalil Mehta { 1620acfc3d55SHuazhong Tan if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) && 1621acfc3d55SHuazhong Tan !test_bit(HCLGEVF_STATE_REMOVING, &hdev->state)) { 162235a1e503SSalil Mehta set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 162335a1e503SSalil Mehta schedule_work(&hdev->rst_service_task); 162435a1e503SSalil Mehta } 162535a1e503SSalil Mehta } 162635a1e503SSalil Mehta 162707a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1628e2cb1decSSalil Mehta { 162907a0556aSSalil Mehta if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) && 163007a0556aSSalil Mehta !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) { 163107a0556aSSalil Mehta set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1632e2cb1decSSalil Mehta schedule_work(&hdev->mbx_service_task); 1633e2cb1decSSalil Mehta } 163407a0556aSSalil Mehta } 1635e2cb1decSSalil Mehta 1636e2cb1decSSalil Mehta static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 1637e2cb1decSSalil Mehta { 1638e2cb1decSSalil Mehta if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 1639e2cb1decSSalil Mehta !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 1640e2cb1decSSalil Mehta schedule_work(&hdev->service_task); 1641e2cb1decSSalil Mehta } 1642e2cb1decSSalil Mehta 1643436667d2SSalil Mehta static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev) 1644436667d2SSalil Mehta { 164507a0556aSSalil Mehta /* if we have any pending mailbox event then schedule the mbx task */ 164607a0556aSSalil Mehta if (hdev->mbx_event_pending) 164707a0556aSSalil Mehta hclgevf_mbx_task_schedule(hdev); 164807a0556aSSalil Mehta 1649436667d2SSalil Mehta if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state)) 1650436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 1651436667d2SSalil Mehta } 1652436667d2SSalil Mehta 1653e2cb1decSSalil Mehta static void hclgevf_service_timer(struct timer_list *t) 1654e2cb1decSSalil Mehta { 1655e2cb1decSSalil Mehta struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 1656e2cb1decSSalil Mehta 1657b37ce587SYufeng Mo mod_timer(&hdev->service_timer, jiffies + 1658b37ce587SYufeng Mo HCLGEVF_GENERAL_TASK_INTERVAL * HZ); 1659e2cb1decSSalil Mehta 1660db01afebSliuzhongzhu hdev->stats_timer++; 1661e2cb1decSSalil Mehta hclgevf_task_schedule(hdev); 1662e2cb1decSSalil Mehta } 1663e2cb1decSSalil Mehta 166435a1e503SSalil Mehta static void hclgevf_reset_service_task(struct work_struct *work) 166535a1e503SSalil Mehta { 166635a1e503SSalil Mehta struct hclgevf_dev *hdev = 166735a1e503SSalil Mehta container_of(work, struct hclgevf_dev, rst_service_task); 1668a8dedb65SSalil Mehta int ret; 166935a1e503SSalil Mehta 167035a1e503SSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 167135a1e503SSalil Mehta return; 167235a1e503SSalil Mehta 167335a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 167435a1e503SSalil Mehta 1675436667d2SSalil Mehta if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1676436667d2SSalil Mehta &hdev->reset_state)) { 1677436667d2SSalil Mehta /* PF has initmated that it is about to reset the hardware. 1678436667d2SSalil Mehta * We now have to poll & check if harware has actually completed 1679436667d2SSalil Mehta * the reset sequence. On hardware reset completion, VF needs to 1680436667d2SSalil Mehta * reset the client and ae device. 168135a1e503SSalil Mehta */ 1682436667d2SSalil Mehta hdev->reset_attempts = 0; 1683436667d2SSalil Mehta 1684dea846e8SHuazhong Tan hdev->last_reset_time = jiffies; 1685dea846e8SHuazhong Tan while ((hdev->reset_type = 1686dea846e8SHuazhong Tan hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 1687dea846e8SHuazhong Tan != HNAE3_NONE_RESET) { 16886988eb2aSSalil Mehta ret = hclgevf_reset(hdev); 16896988eb2aSSalil Mehta if (ret) 1690dea846e8SHuazhong Tan dev_err(&hdev->pdev->dev, 1691dea846e8SHuazhong Tan "VF stack reset failed %d.\n", ret); 1692dea846e8SHuazhong Tan } 1693436667d2SSalil Mehta } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1694436667d2SSalil Mehta &hdev->reset_state)) { 1695436667d2SSalil Mehta /* we could be here when either of below happens: 1696436667d2SSalil Mehta * 1. reset was initiated due to watchdog timeout due to 1697436667d2SSalil Mehta * a. IMP was earlier reset and our TX got choked down and 1698436667d2SSalil Mehta * which resulted in watchdog reacting and inducing VF 1699436667d2SSalil Mehta * reset. This also means our cmdq would be unreliable. 1700436667d2SSalil Mehta * b. problem in TX due to other lower layer(example link 1701436667d2SSalil Mehta * layer not functioning properly etc.) 1702436667d2SSalil Mehta * 2. VF reset might have been initiated due to some config 1703436667d2SSalil Mehta * change. 1704436667d2SSalil Mehta * 1705436667d2SSalil Mehta * NOTE: Theres no clear way to detect above cases than to react 1706436667d2SSalil Mehta * to the response of PF for this reset request. PF will ack the 1707436667d2SSalil Mehta * 1b and 2. cases but we will not get any intimation about 1a 1708436667d2SSalil Mehta * from PF as cmdq would be in unreliable state i.e. mailbox 1709436667d2SSalil Mehta * communication between PF and VF would be broken. 1710436667d2SSalil Mehta */ 1711436667d2SSalil Mehta 1712436667d2SSalil Mehta /* if we are never geting into pending state it means either: 1713436667d2SSalil Mehta * 1. PF is not receiving our request which could be due to IMP 1714436667d2SSalil Mehta * reset 1715436667d2SSalil Mehta * 2. PF is screwed 1716436667d2SSalil Mehta * We cannot do much for 2. but to check first we can try reset 1717436667d2SSalil Mehta * our PCIe + stack and see if it alleviates the problem. 1718436667d2SSalil Mehta */ 1719436667d2SSalil Mehta if (hdev->reset_attempts > 3) { 1720436667d2SSalil Mehta /* prepare for full reset of stack + pcie interface */ 1721dea846e8SHuazhong Tan set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1722436667d2SSalil Mehta 1723436667d2SSalil Mehta /* "defer" schedule the reset task again */ 1724436667d2SSalil Mehta set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1725436667d2SSalil Mehta } else { 1726436667d2SSalil Mehta hdev->reset_attempts++; 1727436667d2SSalil Mehta 1728dea846e8SHuazhong Tan set_bit(hdev->reset_level, &hdev->reset_pending); 1729dea846e8SHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1730436667d2SSalil Mehta } 1731dea846e8SHuazhong Tan hclgevf_reset_task_schedule(hdev); 1732436667d2SSalil Mehta } 173335a1e503SSalil Mehta 173435a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 173535a1e503SSalil Mehta } 173635a1e503SSalil Mehta 1737e2cb1decSSalil Mehta static void hclgevf_mailbox_service_task(struct work_struct *work) 1738e2cb1decSSalil Mehta { 1739e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1740e2cb1decSSalil Mehta 1741e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 1742e2cb1decSSalil Mehta 1743e2cb1decSSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1744e2cb1decSSalil Mehta return; 1745e2cb1decSSalil Mehta 1746e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1747e2cb1decSSalil Mehta 174807a0556aSSalil Mehta hclgevf_mbx_async_handler(hdev); 1749e2cb1decSSalil Mehta 1750e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1751e2cb1decSSalil Mehta } 1752e2cb1decSSalil Mehta 1753a6d818e3SYunsheng Lin static void hclgevf_keep_alive_timer(struct timer_list *t) 1754a6d818e3SYunsheng Lin { 1755a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = from_timer(hdev, t, keep_alive_timer); 1756a6d818e3SYunsheng Lin 1757a6d818e3SYunsheng Lin schedule_work(&hdev->keep_alive_task); 1758b37ce587SYufeng Mo mod_timer(&hdev->keep_alive_timer, jiffies + 1759b37ce587SYufeng Mo HCLGEVF_KEEP_ALIVE_TASK_INTERVAL * HZ); 1760a6d818e3SYunsheng Lin } 1761a6d818e3SYunsheng Lin 1762a6d818e3SYunsheng Lin static void hclgevf_keep_alive_task(struct work_struct *work) 1763a6d818e3SYunsheng Lin { 1764a6d818e3SYunsheng Lin struct hclgevf_dev *hdev; 1765a6d818e3SYunsheng Lin u8 respmsg; 1766a6d818e3SYunsheng Lin int ret; 1767a6d818e3SYunsheng Lin 1768a6d818e3SYunsheng Lin hdev = container_of(work, struct hclgevf_dev, keep_alive_task); 1769c59a85c0SJian Shen 17701416d333SHuazhong Tan if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 1771c59a85c0SJian Shen return; 1772c59a85c0SJian Shen 1773a6d818e3SYunsheng Lin ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL, 177463cbf7a9SYufeng Mo 0, false, &respmsg, sizeof(respmsg)); 1775a6d818e3SYunsheng Lin if (ret) 1776a6d818e3SYunsheng Lin dev_err(&hdev->pdev->dev, 1777a6d818e3SYunsheng Lin "VF sends keep alive cmd failed(=%d)\n", ret); 1778a6d818e3SYunsheng Lin } 1779a6d818e3SYunsheng Lin 1780e2cb1decSSalil Mehta static void hclgevf_service_task(struct work_struct *work) 1781e2cb1decSSalil Mehta { 1782db01afebSliuzhongzhu struct hnae3_handle *handle; 1783e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1784e2cb1decSSalil Mehta 1785e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, service_task); 1786db01afebSliuzhongzhu handle = &hdev->nic; 1787db01afebSliuzhongzhu 1788db01afebSliuzhongzhu if (hdev->stats_timer >= HCLGEVF_STATS_TIMER_INTERVAL) { 1789db01afebSliuzhongzhu hclgevf_tqps_update_stats(handle); 1790db01afebSliuzhongzhu hdev->stats_timer = 0; 1791db01afebSliuzhongzhu } 1792e2cb1decSSalil Mehta 1793e2cb1decSSalil Mehta /* request the link status from the PF. PF would be able to tell VF 1794e2cb1decSSalil Mehta * about such updates in future so we might remove this later 1795e2cb1decSSalil Mehta */ 1796e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1797e2cb1decSSalil Mehta 17989194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 17999194d18bSliuzhongzhu 1800436667d2SSalil Mehta hclgevf_deferred_task_schedule(hdev); 1801436667d2SSalil Mehta 1802e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1803e2cb1decSSalil Mehta } 1804e2cb1decSSalil Mehta 1805e2cb1decSSalil Mehta static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1806e2cb1decSSalil Mehta { 1807e2cb1decSSalil Mehta hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1808e2cb1decSSalil Mehta } 1809e2cb1decSSalil Mehta 1810b90fcc5bSHuazhong Tan static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1811b90fcc5bSHuazhong Tan u32 *clearval) 1812e2cb1decSSalil Mehta { 1813b90fcc5bSHuazhong Tan u32 cmdq_src_reg, rst_ing_reg; 1814e2cb1decSSalil Mehta 1815e2cb1decSSalil Mehta /* fetch the events from their corresponding regs */ 1816e2cb1decSSalil Mehta cmdq_src_reg = hclgevf_read_dev(&hdev->hw, 1817e2cb1decSSalil Mehta HCLGEVF_VECTOR0_CMDQ_SRC_REG); 1818e2cb1decSSalil Mehta 1819b90fcc5bSHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_src_reg) { 1820b90fcc5bSHuazhong Tan rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1821b90fcc5bSHuazhong Tan dev_info(&hdev->pdev->dev, 1822b90fcc5bSHuazhong Tan "receive reset interrupt 0x%x!\n", rst_ing_reg); 1823b90fcc5bSHuazhong Tan set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1824b90fcc5bSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1825ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1826b90fcc5bSHuazhong Tan cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RST_INT_B); 1827b90fcc5bSHuazhong Tan *clearval = cmdq_src_reg; 1828c88a6e7dSHuazhong Tan hdev->rst_stats.vf_rst_cnt++; 1829b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_RST; 1830b90fcc5bSHuazhong Tan } 1831b90fcc5bSHuazhong Tan 1832e2cb1decSSalil Mehta /* check for vector0 mailbox(=CMDQ RX) event source */ 1833e2cb1decSSalil Mehta if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 1834e2cb1decSSalil Mehta cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1835e2cb1decSSalil Mehta *clearval = cmdq_src_reg; 1836b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_MBX; 1837e2cb1decSSalil Mehta } 1838e2cb1decSSalil Mehta 1839e2cb1decSSalil Mehta dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 1840e2cb1decSSalil Mehta 1841b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_OTHER; 1842e2cb1decSSalil Mehta } 1843e2cb1decSSalil Mehta 1844e2cb1decSSalil Mehta static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1845e2cb1decSSalil Mehta { 1846e2cb1decSSalil Mehta writel(en ? 1 : 0, vector->addr); 1847e2cb1decSSalil Mehta } 1848e2cb1decSSalil Mehta 1849e2cb1decSSalil Mehta static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1850e2cb1decSSalil Mehta { 1851b90fcc5bSHuazhong Tan enum hclgevf_evt_cause event_cause; 1852e2cb1decSSalil Mehta struct hclgevf_dev *hdev = data; 1853e2cb1decSSalil Mehta u32 clearval; 1854e2cb1decSSalil Mehta 1855e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 1856b90fcc5bSHuazhong Tan event_cause = hclgevf_check_evt_cause(hdev, &clearval); 1857e2cb1decSSalil Mehta 1858b90fcc5bSHuazhong Tan switch (event_cause) { 1859b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_RST: 1860b90fcc5bSHuazhong Tan hclgevf_reset_task_schedule(hdev); 1861b90fcc5bSHuazhong Tan break; 1862b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_MBX: 186307a0556aSSalil Mehta hclgevf_mbx_handler(hdev); 1864b90fcc5bSHuazhong Tan break; 1865b90fcc5bSHuazhong Tan default: 1866b90fcc5bSHuazhong Tan break; 1867b90fcc5bSHuazhong Tan } 1868e2cb1decSSalil Mehta 1869b90fcc5bSHuazhong Tan if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 1870e2cb1decSSalil Mehta hclgevf_clear_event_cause(hdev, clearval); 1871e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 1872b90fcc5bSHuazhong Tan } 1873e2cb1decSSalil Mehta 1874e2cb1decSSalil Mehta return IRQ_HANDLED; 1875e2cb1decSSalil Mehta } 1876e2cb1decSSalil Mehta 1877e2cb1decSSalil Mehta static int hclgevf_configure(struct hclgevf_dev *hdev) 1878e2cb1decSSalil Mehta { 1879e2cb1decSSalil Mehta int ret; 1880e2cb1decSSalil Mehta 188192f11ea1SJian Shen /* get current port based vlan state from PF */ 188292f11ea1SJian Shen ret = hclgevf_get_port_base_vlan_filter_state(hdev); 188392f11ea1SJian Shen if (ret) 188492f11ea1SJian Shen return ret; 188592f11ea1SJian Shen 1886e2cb1decSSalil Mehta /* get queue configuration from PF */ 18876cee6fc3SJian Shen ret = hclgevf_get_queue_info(hdev); 1888e2cb1decSSalil Mehta if (ret) 1889e2cb1decSSalil Mehta return ret; 1890c0425944SPeng Li 1891c0425944SPeng Li /* get queue depth info from PF */ 1892c0425944SPeng Li ret = hclgevf_get_queue_depth(hdev); 1893c0425944SPeng Li if (ret) 1894c0425944SPeng Li return ret; 1895c0425944SPeng Li 18969c3e7130Sliuzhongzhu ret = hclgevf_get_pf_media_type(hdev); 18979c3e7130Sliuzhongzhu if (ret) 18989c3e7130Sliuzhongzhu return ret; 18999c3e7130Sliuzhongzhu 1900e2cb1decSSalil Mehta /* get tc configuration from PF */ 1901e2cb1decSSalil Mehta return hclgevf_get_tc_info(hdev); 1902e2cb1decSSalil Mehta } 1903e2cb1decSSalil Mehta 19047a01c897SSalil Mehta static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 19057a01c897SSalil Mehta { 19067a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 19071154bb26SPeng Li struct hclgevf_dev *hdev; 19087a01c897SSalil Mehta 19097a01c897SSalil Mehta hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 19107a01c897SSalil Mehta if (!hdev) 19117a01c897SSalil Mehta return -ENOMEM; 19127a01c897SSalil Mehta 19137a01c897SSalil Mehta hdev->pdev = pdev; 19147a01c897SSalil Mehta hdev->ae_dev = ae_dev; 19157a01c897SSalil Mehta ae_dev->priv = hdev; 19167a01c897SSalil Mehta 19177a01c897SSalil Mehta return 0; 19187a01c897SSalil Mehta } 19197a01c897SSalil Mehta 1920e2cb1decSSalil Mehta static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 1921e2cb1decSSalil Mehta { 1922e2cb1decSSalil Mehta struct hnae3_handle *roce = &hdev->roce; 1923e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 1924e2cb1decSSalil Mehta 192507acf909SJian Shen roce->rinfo.num_vectors = hdev->num_roce_msix; 1926e2cb1decSSalil Mehta 1927e2cb1decSSalil Mehta if (hdev->num_msi_left < roce->rinfo.num_vectors || 1928e2cb1decSSalil Mehta hdev->num_msi_left == 0) 1929e2cb1decSSalil Mehta return -EINVAL; 1930e2cb1decSSalil Mehta 193107acf909SJian Shen roce->rinfo.base_vector = hdev->roce_base_vector; 1932e2cb1decSSalil Mehta 1933e2cb1decSSalil Mehta roce->rinfo.netdev = nic->kinfo.netdev; 1934e2cb1decSSalil Mehta roce->rinfo.roce_io_base = hdev->hw.io_base; 1935e2cb1decSSalil Mehta 1936e2cb1decSSalil Mehta roce->pdev = nic->pdev; 1937e2cb1decSSalil Mehta roce->ae_algo = nic->ae_algo; 1938e2cb1decSSalil Mehta roce->numa_node_mask = nic->numa_node_mask; 1939e2cb1decSSalil Mehta 1940e2cb1decSSalil Mehta return 0; 1941e2cb1decSSalil Mehta } 1942e2cb1decSSalil Mehta 1943b26a6feaSPeng Li static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 1944b26a6feaSPeng Li { 1945b26a6feaSPeng Li struct hclgevf_cfg_gro_status_cmd *req; 1946b26a6feaSPeng Li struct hclgevf_desc desc; 1947b26a6feaSPeng Li int ret; 1948b26a6feaSPeng Li 1949b26a6feaSPeng Li if (!hnae3_dev_gro_supported(hdev)) 1950b26a6feaSPeng Li return 0; 1951b26a6feaSPeng Li 1952b26a6feaSPeng Li hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 1953b26a6feaSPeng Li false); 1954b26a6feaSPeng Li req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 1955b26a6feaSPeng Li 1956b26a6feaSPeng Li req->gro_en = cpu_to_le16(en ? 1 : 0); 1957b26a6feaSPeng Li 1958b26a6feaSPeng Li ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1959b26a6feaSPeng Li if (ret) 1960b26a6feaSPeng Li dev_err(&hdev->pdev->dev, 1961b26a6feaSPeng Li "VF GRO hardware config cmd failed, ret = %d.\n", ret); 1962b26a6feaSPeng Li 1963b26a6feaSPeng Li return ret; 1964b26a6feaSPeng Li } 1965b26a6feaSPeng Li 1966e2cb1decSSalil Mehta static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 1967e2cb1decSSalil Mehta { 1968e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1969e2cb1decSSalil Mehta int i, ret; 1970e2cb1decSSalil Mehta 1971e2cb1decSSalil Mehta rss_cfg->rss_size = hdev->rss_size_max; 1972e2cb1decSSalil Mehta 1973374ad291SJian Shen if (hdev->pdev->revision >= 0x21) { 1974472d7eceSJian Shen rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 1975472d7eceSJian Shen memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 1976374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 1977374ad291SJian Shen 1978374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 1979374ad291SJian Shen rss_cfg->rss_hash_key); 1980374ad291SJian Shen if (ret) 1981374ad291SJian Shen return ret; 1982d97b3072SJian Shen 1983d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = 1984d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1985d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = 1986d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1987d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = 1988d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1989d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = 1990d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1991d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = 1992d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1993d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = 1994d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1995d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = 1996d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1997d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = 1998d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1999d97b3072SJian Shen 2000d97b3072SJian Shen ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 2001d97b3072SJian Shen if (ret) 2002d97b3072SJian Shen return ret; 2003d97b3072SJian Shen 2004374ad291SJian Shen } 2005374ad291SJian Shen 2006e2cb1decSSalil Mehta /* Initialize RSS indirect table for each vport */ 2007e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 2008e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max; 2009e2cb1decSSalil Mehta 2010e2cb1decSSalil Mehta ret = hclgevf_set_rss_indir_table(hdev); 2011e2cb1decSSalil Mehta if (ret) 2012e2cb1decSSalil Mehta return ret; 2013e2cb1decSSalil Mehta 2014e2cb1decSSalil Mehta return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max); 2015e2cb1decSSalil Mehta } 2016e2cb1decSSalil Mehta 2017e2cb1decSSalil Mehta static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2018e2cb1decSSalil Mehta { 2019e2cb1decSSalil Mehta /* other vlan config(like, VLAN TX/RX offload) would also be added 2020e2cb1decSSalil Mehta * here later 2021e2cb1decSSalil Mehta */ 2022e2cb1decSSalil Mehta return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2023e2cb1decSSalil Mehta false); 2024e2cb1decSSalil Mehta } 2025e2cb1decSSalil Mehta 20268cdb992fSJian Shen static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 20278cdb992fSJian Shen { 20288cdb992fSJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 20298cdb992fSJian Shen 20308cdb992fSJian Shen if (enable) { 20318cdb992fSJian Shen mod_timer(&hdev->service_timer, jiffies + HZ); 20328cdb992fSJian Shen } else { 20338cdb992fSJian Shen del_timer_sync(&hdev->service_timer); 20348cdb992fSJian Shen cancel_work_sync(&hdev->service_task); 20358cdb992fSJian Shen clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 20368cdb992fSJian Shen } 20378cdb992fSJian Shen } 20388cdb992fSJian Shen 2039e2cb1decSSalil Mehta static int hclgevf_ae_start(struct hnae3_handle *handle) 2040e2cb1decSSalil Mehta { 2041e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2042e2cb1decSSalil Mehta 2043e2cb1decSSalil Mehta /* reset tqp stats */ 2044e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 2045e2cb1decSSalil Mehta 2046e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 2047e2cb1decSSalil Mehta 20489194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 20499194d18bSliuzhongzhu 2050e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2051e2cb1decSSalil Mehta 2052e2cb1decSSalil Mehta return 0; 2053e2cb1decSSalil Mehta } 2054e2cb1decSSalil Mehta 2055e2cb1decSSalil Mehta static void hclgevf_ae_stop(struct hnae3_handle *handle) 2056e2cb1decSSalil Mehta { 2057e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 205839cfbc9cSHuazhong Tan int i; 2059e2cb1decSSalil Mehta 20602f7e4896SFuyun Liang set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 20612f7e4896SFuyun Liang 2062146e92c1SHuazhong Tan if (hdev->reset_type != HNAE3_VF_RESET) 206339cfbc9cSHuazhong Tan for (i = 0; i < handle->kinfo.num_tqps; i++) 2064146e92c1SHuazhong Tan if (hclgevf_reset_tqp(handle, i)) 2065146e92c1SHuazhong Tan break; 206639cfbc9cSHuazhong Tan 2067e2cb1decSSalil Mehta /* reset tqp stats */ 2068e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 20698cc6c1f7SFuyun Liang hclgevf_update_link_status(hdev, 0); 2070e2cb1decSSalil Mehta } 2071e2cb1decSSalil Mehta 2072a6d818e3SYunsheng Lin static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2073a6d818e3SYunsheng Lin { 2074a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2075a6d818e3SYunsheng Lin u8 msg_data; 2076a6d818e3SYunsheng Lin 2077a6d818e3SYunsheng Lin msg_data = alive ? 1 : 0; 2078a6d818e3SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE, 2079a6d818e3SYunsheng Lin 0, &msg_data, 1, false, NULL, 0); 2080a6d818e3SYunsheng Lin } 2081a6d818e3SYunsheng Lin 2082a6d818e3SYunsheng Lin static int hclgevf_client_start(struct hnae3_handle *handle) 2083a6d818e3SYunsheng Lin { 2084a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2085e233516eSHuazhong Tan int ret; 2086e233516eSHuazhong Tan 2087e233516eSHuazhong Tan ret = hclgevf_set_alive(handle, true); 2088e233516eSHuazhong Tan if (ret) 2089e233516eSHuazhong Tan return ret; 2090a6d818e3SYunsheng Lin 2091b37ce587SYufeng Mo mod_timer(&hdev->keep_alive_timer, jiffies + 2092b37ce587SYufeng Mo HCLGEVF_KEEP_ALIVE_TASK_INTERVAL * HZ); 2093e233516eSHuazhong Tan 2094e233516eSHuazhong Tan return 0; 2095a6d818e3SYunsheng Lin } 2096a6d818e3SYunsheng Lin 2097a6d818e3SYunsheng Lin static void hclgevf_client_stop(struct hnae3_handle *handle) 2098a6d818e3SYunsheng Lin { 2099a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2100a6d818e3SYunsheng Lin int ret; 2101a6d818e3SYunsheng Lin 2102a6d818e3SYunsheng Lin ret = hclgevf_set_alive(handle, false); 2103a6d818e3SYunsheng Lin if (ret) 2104a6d818e3SYunsheng Lin dev_warn(&hdev->pdev->dev, 2105a6d818e3SYunsheng Lin "%s failed %d\n", __func__, ret); 2106a6d818e3SYunsheng Lin 2107a6d818e3SYunsheng Lin del_timer_sync(&hdev->keep_alive_timer); 2108a6d818e3SYunsheng Lin cancel_work_sync(&hdev->keep_alive_task); 2109a6d818e3SYunsheng Lin } 2110a6d818e3SYunsheng Lin 2111e2cb1decSSalil Mehta static void hclgevf_state_init(struct hclgevf_dev *hdev) 2112e2cb1decSSalil Mehta { 2113e2cb1decSSalil Mehta /* setup tasks for the MBX */ 2114e2cb1decSSalil Mehta INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 2115e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2116e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2117e2cb1decSSalil Mehta 2118e2cb1decSSalil Mehta /* setup tasks for service timer */ 2119e2cb1decSSalil Mehta timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 2120e2cb1decSSalil Mehta 2121e2cb1decSSalil Mehta INIT_WORK(&hdev->service_task, hclgevf_service_task); 2122e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2123e2cb1decSSalil Mehta 212435a1e503SSalil Mehta INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task); 212535a1e503SSalil Mehta 2126e2cb1decSSalil Mehta mutex_init(&hdev->mbx_resp.mbx_mutex); 2127e2cb1decSSalil Mehta 2128e2cb1decSSalil Mehta /* bring the device down */ 2129e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2130e2cb1decSSalil Mehta } 2131e2cb1decSSalil Mehta 2132e2cb1decSSalil Mehta static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2133e2cb1decSSalil Mehta { 2134e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2135acfc3d55SHuazhong Tan set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2136e2cb1decSSalil Mehta 2137e233516eSHuazhong Tan if (hdev->keep_alive_timer.function) 2138e233516eSHuazhong Tan del_timer_sync(&hdev->keep_alive_timer); 2139e233516eSHuazhong Tan if (hdev->keep_alive_task.func) 2140e233516eSHuazhong Tan cancel_work_sync(&hdev->keep_alive_task); 2141e2cb1decSSalil Mehta if (hdev->service_timer.function) 2142e2cb1decSSalil Mehta del_timer_sync(&hdev->service_timer); 2143e2cb1decSSalil Mehta if (hdev->service_task.func) 2144e2cb1decSSalil Mehta cancel_work_sync(&hdev->service_task); 2145e2cb1decSSalil Mehta if (hdev->mbx_service_task.func) 2146e2cb1decSSalil Mehta cancel_work_sync(&hdev->mbx_service_task); 214735a1e503SSalil Mehta if (hdev->rst_service_task.func) 214835a1e503SSalil Mehta cancel_work_sync(&hdev->rst_service_task); 2149e2cb1decSSalil Mehta 2150e2cb1decSSalil Mehta mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2151e2cb1decSSalil Mehta } 2152e2cb1decSSalil Mehta 2153e2cb1decSSalil Mehta static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2154e2cb1decSSalil Mehta { 2155e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2156e2cb1decSSalil Mehta int vectors; 2157e2cb1decSSalil Mehta int i; 2158e2cb1decSSalil Mehta 215907acf909SJian Shen if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) 216007acf909SJian Shen vectors = pci_alloc_irq_vectors(pdev, 216107acf909SJian Shen hdev->roce_base_msix_offset + 1, 216207acf909SJian Shen hdev->num_msi, 216307acf909SJian Shen PCI_IRQ_MSIX); 216407acf909SJian Shen else 2165e2cb1decSSalil Mehta vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 2166e2cb1decSSalil Mehta PCI_IRQ_MSI | PCI_IRQ_MSIX); 216707acf909SJian Shen 2168e2cb1decSSalil Mehta if (vectors < 0) { 2169e2cb1decSSalil Mehta dev_err(&pdev->dev, 2170e2cb1decSSalil Mehta "failed(%d) to allocate MSI/MSI-X vectors\n", 2171e2cb1decSSalil Mehta vectors); 2172e2cb1decSSalil Mehta return vectors; 2173e2cb1decSSalil Mehta } 2174e2cb1decSSalil Mehta if (vectors < hdev->num_msi) 2175e2cb1decSSalil Mehta dev_warn(&hdev->pdev->dev, 2176e2cb1decSSalil Mehta "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2177e2cb1decSSalil Mehta hdev->num_msi, vectors); 2178e2cb1decSSalil Mehta 2179e2cb1decSSalil Mehta hdev->num_msi = vectors; 2180e2cb1decSSalil Mehta hdev->num_msi_left = vectors; 2181e2cb1decSSalil Mehta hdev->base_msi_vector = pdev->irq; 218207acf909SJian Shen hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2183e2cb1decSSalil Mehta 2184e2cb1decSSalil Mehta hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2185e2cb1decSSalil Mehta sizeof(u16), GFP_KERNEL); 2186e2cb1decSSalil Mehta if (!hdev->vector_status) { 2187e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2188e2cb1decSSalil Mehta return -ENOMEM; 2189e2cb1decSSalil Mehta } 2190e2cb1decSSalil Mehta 2191e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 2192e2cb1decSSalil Mehta hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2193e2cb1decSSalil Mehta 2194e2cb1decSSalil Mehta hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2195e2cb1decSSalil Mehta sizeof(int), GFP_KERNEL); 2196e2cb1decSSalil Mehta if (!hdev->vector_irq) { 2197862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2198e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2199e2cb1decSSalil Mehta return -ENOMEM; 2200e2cb1decSSalil Mehta } 2201e2cb1decSSalil Mehta 2202e2cb1decSSalil Mehta return 0; 2203e2cb1decSSalil Mehta } 2204e2cb1decSSalil Mehta 2205e2cb1decSSalil Mehta static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2206e2cb1decSSalil Mehta { 2207e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2208e2cb1decSSalil Mehta 2209862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2210862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_irq); 2211e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2212e2cb1decSSalil Mehta } 2213e2cb1decSSalil Mehta 2214e2cb1decSSalil Mehta static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2215e2cb1decSSalil Mehta { 2216e2cb1decSSalil Mehta int ret = 0; 2217e2cb1decSSalil Mehta 2218e2cb1decSSalil Mehta hclgevf_get_misc_vector(hdev); 2219e2cb1decSSalil Mehta 2220e2cb1decSSalil Mehta ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2221e2cb1decSSalil Mehta 0, "hclgevf_cmd", hdev); 2222e2cb1decSSalil Mehta if (ret) { 2223e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2224e2cb1decSSalil Mehta hdev->misc_vector.vector_irq); 2225e2cb1decSSalil Mehta return ret; 2226e2cb1decSSalil Mehta } 2227e2cb1decSSalil Mehta 22281819e409SXi Wang hclgevf_clear_event_cause(hdev, 0); 22291819e409SXi Wang 2230e2cb1decSSalil Mehta /* enable misc. vector(vector 0) */ 2231e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2232e2cb1decSSalil Mehta 2233e2cb1decSSalil Mehta return ret; 2234e2cb1decSSalil Mehta } 2235e2cb1decSSalil Mehta 2236e2cb1decSSalil Mehta static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2237e2cb1decSSalil Mehta { 2238e2cb1decSSalil Mehta /* disable misc vector(vector 0) */ 2239e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 22401819e409SXi Wang synchronize_irq(hdev->misc_vector.vector_irq); 2241e2cb1decSSalil Mehta free_irq(hdev->misc_vector.vector_irq, hdev); 2242e2cb1decSSalil Mehta hclgevf_free_vector(hdev, 0); 2243e2cb1decSSalil Mehta } 2244e2cb1decSSalil Mehta 2245bb87be87SYonglong Liu static void hclgevf_info_show(struct hclgevf_dev *hdev) 2246bb87be87SYonglong Liu { 2247bb87be87SYonglong Liu struct device *dev = &hdev->pdev->dev; 2248bb87be87SYonglong Liu 2249bb87be87SYonglong Liu dev_info(dev, "VF info begin:\n"); 2250bb87be87SYonglong Liu 2251bb87be87SYonglong Liu dev_info(dev, "Task queue pairs numbers: %d\n", hdev->num_tqps); 2252bb87be87SYonglong Liu dev_info(dev, "Desc num per TX queue: %d\n", hdev->num_tx_desc); 2253bb87be87SYonglong Liu dev_info(dev, "Desc num per RX queue: %d\n", hdev->num_rx_desc); 2254bb87be87SYonglong Liu dev_info(dev, "Numbers of vports: %d\n", hdev->num_alloc_vport); 2255bb87be87SYonglong Liu dev_info(dev, "HW tc map: %d\n", hdev->hw_tc_map); 2256bb87be87SYonglong Liu dev_info(dev, "PF media type of this VF: %d\n", 2257bb87be87SYonglong Liu hdev->hw.mac.media_type); 2258bb87be87SYonglong Liu 2259bb87be87SYonglong Liu dev_info(dev, "VF info end.\n"); 2260bb87be87SYonglong Liu } 2261bb87be87SYonglong Liu 22621db58f86SHuazhong Tan static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 22631db58f86SHuazhong Tan struct hnae3_client *client) 22641db58f86SHuazhong Tan { 22651db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 22661db58f86SHuazhong Tan int ret; 22671db58f86SHuazhong Tan 22681db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->nic); 22691db58f86SHuazhong Tan if (ret) 22701db58f86SHuazhong Tan return ret; 22711db58f86SHuazhong Tan 22721db58f86SHuazhong Tan set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 22731db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 22741db58f86SHuazhong Tan 22751db58f86SHuazhong Tan if (netif_msg_drv(&hdev->nic)) 22761db58f86SHuazhong Tan hclgevf_info_show(hdev); 22771db58f86SHuazhong Tan 22781db58f86SHuazhong Tan return 0; 22791db58f86SHuazhong Tan } 22801db58f86SHuazhong Tan 22811db58f86SHuazhong Tan static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 22821db58f86SHuazhong Tan struct hnae3_client *client) 22831db58f86SHuazhong Tan { 22841db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 22851db58f86SHuazhong Tan int ret; 22861db58f86SHuazhong Tan 22871db58f86SHuazhong Tan if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 22881db58f86SHuazhong Tan !hdev->nic_client) 22891db58f86SHuazhong Tan return 0; 22901db58f86SHuazhong Tan 22911db58f86SHuazhong Tan ret = hclgevf_init_roce_base_info(hdev); 22921db58f86SHuazhong Tan if (ret) 22931db58f86SHuazhong Tan return ret; 22941db58f86SHuazhong Tan 22951db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->roce); 22961db58f86SHuazhong Tan if (ret) 22971db58f86SHuazhong Tan return ret; 22981db58f86SHuazhong Tan 22991db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 23001db58f86SHuazhong Tan 23011db58f86SHuazhong Tan return 0; 23021db58f86SHuazhong Tan } 23031db58f86SHuazhong Tan 2304e718a93fSPeng Li static int hclgevf_init_client_instance(struct hnae3_client *client, 2305e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2306e2cb1decSSalil Mehta { 2307e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2308e2cb1decSSalil Mehta int ret; 2309e2cb1decSSalil Mehta 2310e2cb1decSSalil Mehta switch (client->type) { 2311e2cb1decSSalil Mehta case HNAE3_CLIENT_KNIC: 2312e2cb1decSSalil Mehta hdev->nic_client = client; 2313e2cb1decSSalil Mehta hdev->nic.client = client; 2314e2cb1decSSalil Mehta 23151db58f86SHuazhong Tan ret = hclgevf_init_nic_client_instance(ae_dev, client); 2316e2cb1decSSalil Mehta if (ret) 231749dd8054SJian Shen goto clear_nic; 2318e2cb1decSSalil Mehta 23191db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, 23201db58f86SHuazhong Tan hdev->roce_client); 2321e2cb1decSSalil Mehta if (ret) 232249dd8054SJian Shen goto clear_roce; 2323d9f28fc2SJian Shen 2324e2cb1decSSalil Mehta break; 2325e2cb1decSSalil Mehta case HNAE3_CLIENT_ROCE: 2326544a7bcdSLijun Ou if (hnae3_dev_roce_supported(hdev)) { 2327e2cb1decSSalil Mehta hdev->roce_client = client; 2328e2cb1decSSalil Mehta hdev->roce.client = client; 2329544a7bcdSLijun Ou } 2330e2cb1decSSalil Mehta 23311db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, client); 2332e2cb1decSSalil Mehta if (ret) 233349dd8054SJian Shen goto clear_roce; 2334e2cb1decSSalil Mehta 2335fa7a4bd5SJian Shen break; 2336fa7a4bd5SJian Shen default: 2337fa7a4bd5SJian Shen return -EINVAL; 2338e2cb1decSSalil Mehta } 2339e2cb1decSSalil Mehta 2340e2cb1decSSalil Mehta return 0; 234149dd8054SJian Shen 234249dd8054SJian Shen clear_nic: 234349dd8054SJian Shen hdev->nic_client = NULL; 234449dd8054SJian Shen hdev->nic.client = NULL; 234549dd8054SJian Shen return ret; 234649dd8054SJian Shen clear_roce: 234749dd8054SJian Shen hdev->roce_client = NULL; 234849dd8054SJian Shen hdev->roce.client = NULL; 234949dd8054SJian Shen return ret; 2350e2cb1decSSalil Mehta } 2351e2cb1decSSalil Mehta 2352e718a93fSPeng Li static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2353e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2354e2cb1decSSalil Mehta { 2355e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2356e718a93fSPeng Li 2357e2cb1decSSalil Mehta /* un-init roce, if it exists */ 235849dd8054SJian Shen if (hdev->roce_client) { 2359e2cb1decSSalil Mehta hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 236049dd8054SJian Shen hdev->roce_client = NULL; 236149dd8054SJian Shen hdev->roce.client = NULL; 236249dd8054SJian Shen } 2363e2cb1decSSalil Mehta 2364e2cb1decSSalil Mehta /* un-init nic/unic, if this was not called by roce client */ 236549dd8054SJian Shen if (client->ops->uninit_instance && hdev->nic_client && 236649dd8054SJian Shen client->type != HNAE3_CLIENT_ROCE) { 236725d1817cSHuazhong Tan clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 236825d1817cSHuazhong Tan 2369e2cb1decSSalil Mehta client->ops->uninit_instance(&hdev->nic, 0); 237049dd8054SJian Shen hdev->nic_client = NULL; 237149dd8054SJian Shen hdev->nic.client = NULL; 237249dd8054SJian Shen } 2373e2cb1decSSalil Mehta } 2374e2cb1decSSalil Mehta 2375e2cb1decSSalil Mehta static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2376e2cb1decSSalil Mehta { 2377e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2378e2cb1decSSalil Mehta struct hclgevf_hw *hw; 2379e2cb1decSSalil Mehta int ret; 2380e2cb1decSSalil Mehta 2381e2cb1decSSalil Mehta ret = pci_enable_device(pdev); 2382e2cb1decSSalil Mehta if (ret) { 2383e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed to enable PCI device\n"); 23843e249d3bSFuyun Liang return ret; 2385e2cb1decSSalil Mehta } 2386e2cb1decSSalil Mehta 2387e2cb1decSSalil Mehta ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2388e2cb1decSSalil Mehta if (ret) { 2389e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2390e2cb1decSSalil Mehta goto err_disable_device; 2391e2cb1decSSalil Mehta } 2392e2cb1decSSalil Mehta 2393e2cb1decSSalil Mehta ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2394e2cb1decSSalil Mehta if (ret) { 2395e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2396e2cb1decSSalil Mehta goto err_disable_device; 2397e2cb1decSSalil Mehta } 2398e2cb1decSSalil Mehta 2399e2cb1decSSalil Mehta pci_set_master(pdev); 2400e2cb1decSSalil Mehta hw = &hdev->hw; 2401e2cb1decSSalil Mehta hw->hdev = hdev; 24022e1ea493SPeng Li hw->io_base = pci_iomap(pdev, 2, 0); 2403e2cb1decSSalil Mehta if (!hw->io_base) { 2404e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't map configuration register space\n"); 2405e2cb1decSSalil Mehta ret = -ENOMEM; 2406e2cb1decSSalil Mehta goto err_clr_master; 2407e2cb1decSSalil Mehta } 2408e2cb1decSSalil Mehta 2409e2cb1decSSalil Mehta return 0; 2410e2cb1decSSalil Mehta 2411e2cb1decSSalil Mehta err_clr_master: 2412e2cb1decSSalil Mehta pci_clear_master(pdev); 2413e2cb1decSSalil Mehta pci_release_regions(pdev); 2414e2cb1decSSalil Mehta err_disable_device: 2415e2cb1decSSalil Mehta pci_disable_device(pdev); 24163e249d3bSFuyun Liang 2417e2cb1decSSalil Mehta return ret; 2418e2cb1decSSalil Mehta } 2419e2cb1decSSalil Mehta 2420e2cb1decSSalil Mehta static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2421e2cb1decSSalil Mehta { 2422e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2423e2cb1decSSalil Mehta 2424e2cb1decSSalil Mehta pci_iounmap(pdev, hdev->hw.io_base); 2425e2cb1decSSalil Mehta pci_clear_master(pdev); 2426e2cb1decSSalil Mehta pci_release_regions(pdev); 2427e2cb1decSSalil Mehta pci_disable_device(pdev); 2428e2cb1decSSalil Mehta } 2429e2cb1decSSalil Mehta 243007acf909SJian Shen static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 243107acf909SJian Shen { 243207acf909SJian Shen struct hclgevf_query_res_cmd *req; 243307acf909SJian Shen struct hclgevf_desc desc; 243407acf909SJian Shen int ret; 243507acf909SJian Shen 243607acf909SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 243707acf909SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 243807acf909SJian Shen if (ret) { 243907acf909SJian Shen dev_err(&hdev->pdev->dev, 244007acf909SJian Shen "query vf resource failed, ret = %d.\n", ret); 244107acf909SJian Shen return ret; 244207acf909SJian Shen } 244307acf909SJian Shen 244407acf909SJian Shen req = (struct hclgevf_query_res_cmd *)desc.data; 244507acf909SJian Shen 244607acf909SJian Shen if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) { 244707acf909SJian Shen hdev->roce_base_msix_offset = 244807acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 244907acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_M, 245007acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_S); 245107acf909SJian Shen hdev->num_roce_msix = 245207acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 245307acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 245407acf909SJian Shen 245507acf909SJian Shen /* VF should have NIC vectors and Roce vectors, NIC vectors 245607acf909SJian Shen * are queued before Roce vectors. The offset is fixed to 64. 245707acf909SJian Shen */ 245807acf909SJian Shen hdev->num_msi = hdev->num_roce_msix + 245907acf909SJian Shen hdev->roce_base_msix_offset; 246007acf909SJian Shen } else { 246107acf909SJian Shen hdev->num_msi = 246207acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 246307acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 246407acf909SJian Shen } 246507acf909SJian Shen 246607acf909SJian Shen return 0; 246707acf909SJian Shen } 246807acf909SJian Shen 2469862d969aSHuazhong Tan static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2470862d969aSHuazhong Tan { 2471862d969aSHuazhong Tan struct pci_dev *pdev = hdev->pdev; 2472862d969aSHuazhong Tan int ret = 0; 2473862d969aSHuazhong Tan 2474862d969aSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2475862d969aSHuazhong Tan test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2476862d969aSHuazhong Tan hclgevf_misc_irq_uninit(hdev); 2477862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2478862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2479862d969aSHuazhong Tan } 2480862d969aSHuazhong Tan 2481862d969aSHuazhong Tan if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2482862d969aSHuazhong Tan pci_set_master(pdev); 2483862d969aSHuazhong Tan ret = hclgevf_init_msi(hdev); 2484862d969aSHuazhong Tan if (ret) { 2485862d969aSHuazhong Tan dev_err(&pdev->dev, 2486862d969aSHuazhong Tan "failed(%d) to init MSI/MSI-X\n", ret); 2487862d969aSHuazhong Tan return ret; 2488862d969aSHuazhong Tan } 2489862d969aSHuazhong Tan 2490862d969aSHuazhong Tan ret = hclgevf_misc_irq_init(hdev); 2491862d969aSHuazhong Tan if (ret) { 2492862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2493862d969aSHuazhong Tan dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2494862d969aSHuazhong Tan ret); 2495862d969aSHuazhong Tan return ret; 2496862d969aSHuazhong Tan } 2497862d969aSHuazhong Tan 2498862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2499862d969aSHuazhong Tan } 2500862d969aSHuazhong Tan 2501862d969aSHuazhong Tan return ret; 2502862d969aSHuazhong Tan } 2503862d969aSHuazhong Tan 25049c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2505e2cb1decSSalil Mehta { 25067a01c897SSalil Mehta struct pci_dev *pdev = hdev->pdev; 2507e2cb1decSSalil Mehta int ret; 2508e2cb1decSSalil Mehta 2509862d969aSHuazhong Tan ret = hclgevf_pci_reset(hdev); 2510862d969aSHuazhong Tan if (ret) { 2511862d969aSHuazhong Tan dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2512862d969aSHuazhong Tan return ret; 2513862d969aSHuazhong Tan } 2514862d969aSHuazhong Tan 25159c6f7085SHuazhong Tan ret = hclgevf_cmd_init(hdev); 25169c6f7085SHuazhong Tan if (ret) { 25179c6f7085SHuazhong Tan dev_err(&pdev->dev, "cmd failed %d\n", ret); 25189c6f7085SHuazhong Tan return ret; 25197a01c897SSalil Mehta } 2520e2cb1decSSalil Mehta 25219c6f7085SHuazhong Tan ret = hclgevf_rss_init_hw(hdev); 25229c6f7085SHuazhong Tan if (ret) { 25239c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 25249c6f7085SHuazhong Tan "failed(%d) to initialize RSS\n", ret); 25259c6f7085SHuazhong Tan return ret; 25269c6f7085SHuazhong Tan } 25279c6f7085SHuazhong Tan 2528b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2529b26a6feaSPeng Li if (ret) 2530b26a6feaSPeng Li return ret; 2531b26a6feaSPeng Li 25329c6f7085SHuazhong Tan ret = hclgevf_init_vlan_config(hdev); 25339c6f7085SHuazhong Tan if (ret) { 25349c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 25359c6f7085SHuazhong Tan "failed(%d) to initialize VLAN config\n", ret); 25369c6f7085SHuazhong Tan return ret; 25379c6f7085SHuazhong Tan } 25389c6f7085SHuazhong Tan 25399c6f7085SHuazhong Tan dev_info(&hdev->pdev->dev, "Reset done\n"); 25409c6f7085SHuazhong Tan 25419c6f7085SHuazhong Tan return 0; 25429c6f7085SHuazhong Tan } 25439c6f7085SHuazhong Tan 25449c6f7085SHuazhong Tan static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 25459c6f7085SHuazhong Tan { 25469c6f7085SHuazhong Tan struct pci_dev *pdev = hdev->pdev; 25479c6f7085SHuazhong Tan int ret; 25489c6f7085SHuazhong Tan 2549e2cb1decSSalil Mehta ret = hclgevf_pci_init(hdev); 2550e2cb1decSSalil Mehta if (ret) { 2551e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI initialization failed\n"); 2552e2cb1decSSalil Mehta return ret; 2553e2cb1decSSalil Mehta } 2554e2cb1decSSalil Mehta 25558b0195a3SHuazhong Tan ret = hclgevf_cmd_queue_init(hdev); 25568b0195a3SHuazhong Tan if (ret) { 25578b0195a3SHuazhong Tan dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret); 25588b0195a3SHuazhong Tan goto err_cmd_queue_init; 25598b0195a3SHuazhong Tan } 25608b0195a3SHuazhong Tan 2561eddf0462SYunsheng Lin ret = hclgevf_cmd_init(hdev); 2562eddf0462SYunsheng Lin if (ret) 2563eddf0462SYunsheng Lin goto err_cmd_init; 2564eddf0462SYunsheng Lin 256507acf909SJian Shen /* Get vf resource */ 256607acf909SJian Shen ret = hclgevf_query_vf_resource(hdev); 256707acf909SJian Shen if (ret) { 256807acf909SJian Shen dev_err(&hdev->pdev->dev, 256907acf909SJian Shen "Query vf status error, ret = %d.\n", ret); 25708b0195a3SHuazhong Tan goto err_cmd_init; 257107acf909SJian Shen } 257207acf909SJian Shen 257307acf909SJian Shen ret = hclgevf_init_msi(hdev); 257407acf909SJian Shen if (ret) { 257507acf909SJian Shen dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 25768b0195a3SHuazhong Tan goto err_cmd_init; 257707acf909SJian Shen } 257807acf909SJian Shen 257907acf909SJian Shen hclgevf_state_init(hdev); 2580dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 258107acf909SJian Shen 2582e2cb1decSSalil Mehta ret = hclgevf_misc_irq_init(hdev); 2583e2cb1decSSalil Mehta if (ret) { 2584e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2585e2cb1decSSalil Mehta ret); 2586e2cb1decSSalil Mehta goto err_misc_irq_init; 2587e2cb1decSSalil Mehta } 2588e2cb1decSSalil Mehta 2589862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2590862d969aSHuazhong Tan 2591e2cb1decSSalil Mehta ret = hclgevf_configure(hdev); 2592e2cb1decSSalil Mehta if (ret) { 2593e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2594e2cb1decSSalil Mehta goto err_config; 2595e2cb1decSSalil Mehta } 2596e2cb1decSSalil Mehta 2597e2cb1decSSalil Mehta ret = hclgevf_alloc_tqps(hdev); 2598e2cb1decSSalil Mehta if (ret) { 2599e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2600e2cb1decSSalil Mehta goto err_config; 2601e2cb1decSSalil Mehta } 2602e2cb1decSSalil Mehta 2603e2cb1decSSalil Mehta ret = hclgevf_set_handle_info(hdev); 2604e2cb1decSSalil Mehta if (ret) { 2605e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 2606e2cb1decSSalil Mehta goto err_config; 2607e2cb1decSSalil Mehta } 2608e2cb1decSSalil Mehta 2609b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2610b26a6feaSPeng Li if (ret) 2611b26a6feaSPeng Li goto err_config; 2612b26a6feaSPeng Li 2613f01f5559SJian Shen /* vf is not allowed to enable unicast/multicast promisc mode. 2614f01f5559SJian Shen * For revision 0x20, default to disable broadcast promisc mode, 2615f01f5559SJian Shen * firmware makes sure broadcast packets can be accepted. 2616f01f5559SJian Shen * For revision 0x21, default to enable broadcast promisc mode. 2617f01f5559SJian Shen */ 2618f01f5559SJian Shen ret = hclgevf_set_promisc_mode(hdev, true); 2619f01f5559SJian Shen if (ret) 2620f01f5559SJian Shen goto err_config; 2621f01f5559SJian Shen 2622e2cb1decSSalil Mehta /* Initialize RSS for this VF */ 2623e2cb1decSSalil Mehta ret = hclgevf_rss_init_hw(hdev); 2624e2cb1decSSalil Mehta if (ret) { 2625e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2626e2cb1decSSalil Mehta "failed(%d) to initialize RSS\n", ret); 2627e2cb1decSSalil Mehta goto err_config; 2628e2cb1decSSalil Mehta } 2629e2cb1decSSalil Mehta 2630e2cb1decSSalil Mehta ret = hclgevf_init_vlan_config(hdev); 2631e2cb1decSSalil Mehta if (ret) { 2632e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2633e2cb1decSSalil Mehta "failed(%d) to initialize VLAN config\n", ret); 2634e2cb1decSSalil Mehta goto err_config; 2635e2cb1decSSalil Mehta } 2636e2cb1decSSalil Mehta 26370742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 2638e2cb1decSSalil Mehta pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME); 2639e2cb1decSSalil Mehta 2640e2cb1decSSalil Mehta return 0; 2641e2cb1decSSalil Mehta 2642e2cb1decSSalil Mehta err_config: 2643e2cb1decSSalil Mehta hclgevf_misc_irq_uninit(hdev); 2644e2cb1decSSalil Mehta err_misc_irq_init: 2645e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2646e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 264707acf909SJian Shen err_cmd_init: 26488b0195a3SHuazhong Tan hclgevf_cmd_uninit(hdev); 26498b0195a3SHuazhong Tan err_cmd_queue_init: 2650e2cb1decSSalil Mehta hclgevf_pci_uninit(hdev); 2651862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2652e2cb1decSSalil Mehta return ret; 2653e2cb1decSSalil Mehta } 2654e2cb1decSSalil Mehta 26557a01c897SSalil Mehta static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2656e2cb1decSSalil Mehta { 2657e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2658862d969aSHuazhong Tan 2659862d969aSHuazhong Tan if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2660eddf0462SYunsheng Lin hclgevf_misc_irq_uninit(hdev); 2661e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 26627a01c897SSalil Mehta } 26637a01c897SSalil Mehta 2664e3338205SHuazhong Tan hclgevf_pci_uninit(hdev); 2665862d969aSHuazhong Tan hclgevf_cmd_uninit(hdev); 2666862d969aSHuazhong Tan } 2667862d969aSHuazhong Tan 26687a01c897SSalil Mehta static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 26697a01c897SSalil Mehta { 26707a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 2671a6d818e3SYunsheng Lin struct hclgevf_dev *hdev; 26727a01c897SSalil Mehta int ret; 26737a01c897SSalil Mehta 26747a01c897SSalil Mehta ret = hclgevf_alloc_hdev(ae_dev); 26757a01c897SSalil Mehta if (ret) { 26767a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device allocation failed\n"); 26777a01c897SSalil Mehta return ret; 26787a01c897SSalil Mehta } 26797a01c897SSalil Mehta 26807a01c897SSalil Mehta ret = hclgevf_init_hdev(ae_dev->priv); 2681a6d818e3SYunsheng Lin if (ret) { 26827a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device initialization failed\n"); 26837a01c897SSalil Mehta return ret; 26847a01c897SSalil Mehta } 26857a01c897SSalil Mehta 2686a6d818e3SYunsheng Lin hdev = ae_dev->priv; 2687a6d818e3SYunsheng Lin timer_setup(&hdev->keep_alive_timer, hclgevf_keep_alive_timer, 0); 2688a6d818e3SYunsheng Lin INIT_WORK(&hdev->keep_alive_task, hclgevf_keep_alive_task); 2689a6d818e3SYunsheng Lin 2690a6d818e3SYunsheng Lin return 0; 2691a6d818e3SYunsheng Lin } 2692a6d818e3SYunsheng Lin 26937a01c897SSalil Mehta static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 26947a01c897SSalil Mehta { 26957a01c897SSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 26967a01c897SSalil Mehta 26977a01c897SSalil Mehta hclgevf_uninit_hdev(hdev); 2698e2cb1decSSalil Mehta ae_dev->priv = NULL; 2699e2cb1decSSalil Mehta } 2700e2cb1decSSalil Mehta 2701849e4607SPeng Li static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2702849e4607SPeng Li { 2703849e4607SPeng Li struct hnae3_handle *nic = &hdev->nic; 2704849e4607SPeng Li struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2705849e4607SPeng Li 27068be73621SHuazhong Tan return min_t(u32, hdev->rss_size_max, 27078be73621SHuazhong Tan hdev->num_tqps / kinfo->num_tc); 2708849e4607SPeng Li } 2709849e4607SPeng Li 2710849e4607SPeng Li /** 2711849e4607SPeng Li * hclgevf_get_channels - Get the current channels enabled and max supported. 2712849e4607SPeng Li * @handle: hardware information for network interface 2713849e4607SPeng Li * @ch: ethtool channels structure 2714849e4607SPeng Li * 2715849e4607SPeng Li * We don't support separate tx and rx queues as channels. The other count 2716849e4607SPeng Li * represents how many queues are being used for control. max_combined counts 2717849e4607SPeng Li * how many queue pairs we can support. They may not be mapped 1 to 1 with 2718849e4607SPeng Li * q_vectors since we support a lot more queue pairs than q_vectors. 2719849e4607SPeng Li **/ 2720849e4607SPeng Li static void hclgevf_get_channels(struct hnae3_handle *handle, 2721849e4607SPeng Li struct ethtool_channels *ch) 2722849e4607SPeng Li { 2723849e4607SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2724849e4607SPeng Li 2725849e4607SPeng Li ch->max_combined = hclgevf_get_max_channels(hdev); 2726849e4607SPeng Li ch->other_count = 0; 2727849e4607SPeng Li ch->max_other = 0; 27288be73621SHuazhong Tan ch->combined_count = handle->kinfo.rss_size; 2729849e4607SPeng Li } 2730849e4607SPeng Li 2731cc719218SPeng Li static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 27320d43bf45SHuazhong Tan u16 *alloc_tqps, u16 *max_rss_size) 2733cc719218SPeng Li { 2734cc719218SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2735cc719218SPeng Li 27360d43bf45SHuazhong Tan *alloc_tqps = hdev->num_tqps; 2737cc719218SPeng Li *max_rss_size = hdev->rss_size_max; 2738cc719218SPeng Li } 2739cc719218SPeng Li 2740175ec96bSFuyun Liang static int hclgevf_get_status(struct hnae3_handle *handle) 2741175ec96bSFuyun Liang { 2742175ec96bSFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2743175ec96bSFuyun Liang 2744175ec96bSFuyun Liang return hdev->hw.mac.link; 2745175ec96bSFuyun Liang } 2746175ec96bSFuyun Liang 27474a152de9SFuyun Liang static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 27484a152de9SFuyun Liang u8 *auto_neg, u32 *speed, 27494a152de9SFuyun Liang u8 *duplex) 27504a152de9SFuyun Liang { 27514a152de9SFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27524a152de9SFuyun Liang 27534a152de9SFuyun Liang if (speed) 27544a152de9SFuyun Liang *speed = hdev->hw.mac.speed; 27554a152de9SFuyun Liang if (duplex) 27564a152de9SFuyun Liang *duplex = hdev->hw.mac.duplex; 27574a152de9SFuyun Liang if (auto_neg) 27584a152de9SFuyun Liang *auto_neg = AUTONEG_DISABLE; 27594a152de9SFuyun Liang } 27604a152de9SFuyun Liang 27614a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 27624a152de9SFuyun Liang u8 duplex) 27634a152de9SFuyun Liang { 27644a152de9SFuyun Liang hdev->hw.mac.speed = speed; 27654a152de9SFuyun Liang hdev->hw.mac.duplex = duplex; 27664a152de9SFuyun Liang } 27674a152de9SFuyun Liang 27681731be4cSYonglong Liu static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 27695c9f6b39SPeng Li { 27705c9f6b39SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27715c9f6b39SPeng Li 27725c9f6b39SPeng Li return hclgevf_config_gro(hdev, enable); 27735c9f6b39SPeng Li } 27745c9f6b39SPeng Li 277588d10bd6SJian Shen static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 277688d10bd6SJian Shen u8 *module_type) 2777c136b884SPeng Li { 2778c136b884SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 277988d10bd6SJian Shen 2780c136b884SPeng Li if (media_type) 2781c136b884SPeng Li *media_type = hdev->hw.mac.media_type; 278288d10bd6SJian Shen 278388d10bd6SJian Shen if (module_type) 278488d10bd6SJian Shen *module_type = hdev->hw.mac.module_type; 2785c136b884SPeng Li } 2786c136b884SPeng Li 27874d60291bSHuazhong Tan static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 27884d60291bSHuazhong Tan { 27894d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27904d60291bSHuazhong Tan 2791aa5c4f17SHuazhong Tan return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 27924d60291bSHuazhong Tan } 27934d60291bSHuazhong Tan 27944d60291bSHuazhong Tan static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 27954d60291bSHuazhong Tan { 27964d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 27974d60291bSHuazhong Tan 27984d60291bSHuazhong Tan return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 27994d60291bSHuazhong Tan } 28004d60291bSHuazhong Tan 28014d60291bSHuazhong Tan static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 28024d60291bSHuazhong Tan { 28034d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 28044d60291bSHuazhong Tan 2805c88a6e7dSHuazhong Tan return hdev->rst_stats.hw_rst_done_cnt; 28064d60291bSHuazhong Tan } 28074d60291bSHuazhong Tan 28089194d18bSliuzhongzhu static void hclgevf_get_link_mode(struct hnae3_handle *handle, 28099194d18bSliuzhongzhu unsigned long *supported, 28109194d18bSliuzhongzhu unsigned long *advertising) 28119194d18bSliuzhongzhu { 28129194d18bSliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 28139194d18bSliuzhongzhu 28149194d18bSliuzhongzhu *supported = hdev->hw.mac.supported; 28159194d18bSliuzhongzhu *advertising = hdev->hw.mac.advertising; 28169194d18bSliuzhongzhu } 28179194d18bSliuzhongzhu 28181600c3e5SJian Shen #define MAX_SEPARATE_NUM 4 28191600c3e5SJian Shen #define SEPARATOR_VALUE 0xFFFFFFFF 28201600c3e5SJian Shen #define REG_NUM_PER_LINE 4 28211600c3e5SJian Shen #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 28221600c3e5SJian Shen 28231600c3e5SJian Shen static int hclgevf_get_regs_len(struct hnae3_handle *handle) 28241600c3e5SJian Shen { 28251600c3e5SJian Shen int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 28261600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 28271600c3e5SJian Shen 28281600c3e5SJian Shen cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 28291600c3e5SJian Shen common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 28301600c3e5SJian Shen ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 28311600c3e5SJian Shen tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 28321600c3e5SJian Shen 28331600c3e5SJian Shen return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 28341600c3e5SJian Shen tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 28351600c3e5SJian Shen } 28361600c3e5SJian Shen 28371600c3e5SJian Shen static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 28381600c3e5SJian Shen void *data) 28391600c3e5SJian Shen { 28401600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 28411600c3e5SJian Shen int i, j, reg_um, separator_num; 28421600c3e5SJian Shen u32 *reg = data; 28431600c3e5SJian Shen 28441600c3e5SJian Shen *version = hdev->fw_version; 28451600c3e5SJian Shen 28461600c3e5SJian Shen /* fetching per-VF registers values from VF PCIe register space */ 28471600c3e5SJian Shen reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 28481600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 28491600c3e5SJian Shen for (i = 0; i < reg_um; i++) 28501600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 28511600c3e5SJian Shen for (i = 0; i < separator_num; i++) 28521600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 28531600c3e5SJian Shen 28541600c3e5SJian Shen reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 28551600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 28561600c3e5SJian Shen for (i = 0; i < reg_um; i++) 28571600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 28581600c3e5SJian Shen for (i = 0; i < separator_num; i++) 28591600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 28601600c3e5SJian Shen 28611600c3e5SJian Shen reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 28621600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 28631600c3e5SJian Shen for (j = 0; j < hdev->num_tqps; j++) { 28641600c3e5SJian Shen for (i = 0; i < reg_um; i++) 28651600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 28661600c3e5SJian Shen ring_reg_addr_list[i] + 28671600c3e5SJian Shen 0x200 * j); 28681600c3e5SJian Shen for (i = 0; i < separator_num; i++) 28691600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 28701600c3e5SJian Shen } 28711600c3e5SJian Shen 28721600c3e5SJian Shen reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 28731600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 28741600c3e5SJian Shen for (j = 0; j < hdev->num_msi_used - 1; j++) { 28751600c3e5SJian Shen for (i = 0; i < reg_um; i++) 28761600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 28771600c3e5SJian Shen tqp_intr_reg_addr_list[i] + 28781600c3e5SJian Shen 4 * j); 28791600c3e5SJian Shen for (i = 0; i < separator_num; i++) 28801600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 28811600c3e5SJian Shen } 28821600c3e5SJian Shen } 28831600c3e5SJian Shen 288492f11ea1SJian Shen void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 288592f11ea1SJian Shen u8 *port_base_vlan_info, u8 data_size) 288692f11ea1SJian Shen { 288792f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 288892f11ea1SJian Shen 288992f11ea1SJian Shen rtnl_lock(); 289092f11ea1SJian Shen hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 289192f11ea1SJian Shen rtnl_unlock(); 289292f11ea1SJian Shen 289392f11ea1SJian Shen /* send msg to PF and wait update port based vlan info */ 289492f11ea1SJian Shen hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 289592f11ea1SJian Shen HCLGE_MBX_PORT_BASE_VLAN_CFG, 289692f11ea1SJian Shen port_base_vlan_info, data_size, 289792f11ea1SJian Shen false, NULL, 0); 289892f11ea1SJian Shen 289992f11ea1SJian Shen if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 290092f11ea1SJian Shen nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 290192f11ea1SJian Shen else 290292f11ea1SJian Shen nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 290392f11ea1SJian Shen 290492f11ea1SJian Shen rtnl_lock(); 290592f11ea1SJian Shen hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 290692f11ea1SJian Shen rtnl_unlock(); 290792f11ea1SJian Shen } 290892f11ea1SJian Shen 2909e2cb1decSSalil Mehta static const struct hnae3_ae_ops hclgevf_ops = { 2910e2cb1decSSalil Mehta .init_ae_dev = hclgevf_init_ae_dev, 2911e2cb1decSSalil Mehta .uninit_ae_dev = hclgevf_uninit_ae_dev, 29126ff3cf07SHuazhong Tan .flr_prepare = hclgevf_flr_prepare, 29136ff3cf07SHuazhong Tan .flr_done = hclgevf_flr_done, 2914e718a93fSPeng Li .init_client_instance = hclgevf_init_client_instance, 2915e718a93fSPeng Li .uninit_client_instance = hclgevf_uninit_client_instance, 2916e2cb1decSSalil Mehta .start = hclgevf_ae_start, 2917e2cb1decSSalil Mehta .stop = hclgevf_ae_stop, 2918a6d818e3SYunsheng Lin .client_start = hclgevf_client_start, 2919a6d818e3SYunsheng Lin .client_stop = hclgevf_client_stop, 2920e2cb1decSSalil Mehta .map_ring_to_vector = hclgevf_map_ring_to_vector, 2921e2cb1decSSalil Mehta .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 2922e2cb1decSSalil Mehta .get_vector = hclgevf_get_vector, 29230d3e6631SYunsheng Lin .put_vector = hclgevf_put_vector, 2924e2cb1decSSalil Mehta .reset_queue = hclgevf_reset_tqp, 2925e2cb1decSSalil Mehta .get_mac_addr = hclgevf_get_mac_addr, 2926e2cb1decSSalil Mehta .set_mac_addr = hclgevf_set_mac_addr, 2927e2cb1decSSalil Mehta .add_uc_addr = hclgevf_add_uc_addr, 2928e2cb1decSSalil Mehta .rm_uc_addr = hclgevf_rm_uc_addr, 2929e2cb1decSSalil Mehta .add_mc_addr = hclgevf_add_mc_addr, 2930e2cb1decSSalil Mehta .rm_mc_addr = hclgevf_rm_mc_addr, 2931e2cb1decSSalil Mehta .get_stats = hclgevf_get_stats, 2932e2cb1decSSalil Mehta .update_stats = hclgevf_update_stats, 2933e2cb1decSSalil Mehta .get_strings = hclgevf_get_strings, 2934e2cb1decSSalil Mehta .get_sset_count = hclgevf_get_sset_count, 2935e2cb1decSSalil Mehta .get_rss_key_size = hclgevf_get_rss_key_size, 2936e2cb1decSSalil Mehta .get_rss_indir_size = hclgevf_get_rss_indir_size, 2937e2cb1decSSalil Mehta .get_rss = hclgevf_get_rss, 2938e2cb1decSSalil Mehta .set_rss = hclgevf_set_rss, 2939d97b3072SJian Shen .get_rss_tuple = hclgevf_get_rss_tuple, 2940d97b3072SJian Shen .set_rss_tuple = hclgevf_set_rss_tuple, 2941e2cb1decSSalil Mehta .get_tc_size = hclgevf_get_tc_size, 2942e2cb1decSSalil Mehta .get_fw_version = hclgevf_get_fw_version, 2943e2cb1decSSalil Mehta .set_vlan_filter = hclgevf_set_vlan_filter, 2944b2641e2aSYunsheng Lin .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 29456d4c3981SSalil Mehta .reset_event = hclgevf_reset_event, 2946720bd583SHuazhong Tan .set_default_reset_request = hclgevf_set_def_reset_request, 2947849e4607SPeng Li .get_channels = hclgevf_get_channels, 2948cc719218SPeng Li .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 29491600c3e5SJian Shen .get_regs_len = hclgevf_get_regs_len, 29501600c3e5SJian Shen .get_regs = hclgevf_get_regs, 2951175ec96bSFuyun Liang .get_status = hclgevf_get_status, 29524a152de9SFuyun Liang .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 2953c136b884SPeng Li .get_media_type = hclgevf_get_media_type, 29544d60291bSHuazhong Tan .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 29554d60291bSHuazhong Tan .ae_dev_resetting = hclgevf_ae_dev_resetting, 29564d60291bSHuazhong Tan .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 29575c9f6b39SPeng Li .set_gro_en = hclgevf_gro_en, 2958818f1675SYunsheng Lin .set_mtu = hclgevf_set_mtu, 29590c29d191Sliuzhongzhu .get_global_queue_id = hclgevf_get_qid_global, 29608cdb992fSJian Shen .set_timer_task = hclgevf_set_timer_task, 29619194d18bSliuzhongzhu .get_link_mode = hclgevf_get_link_mode, 2962e2cb1decSSalil Mehta }; 2963e2cb1decSSalil Mehta 2964e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf = { 2965e2cb1decSSalil Mehta .ops = &hclgevf_ops, 2966e2cb1decSSalil Mehta .pdev_id_table = ae_algovf_pci_tbl, 2967e2cb1decSSalil Mehta }; 2968e2cb1decSSalil Mehta 2969e2cb1decSSalil Mehta static int hclgevf_init(void) 2970e2cb1decSSalil Mehta { 2971e2cb1decSSalil Mehta pr_info("%s is initializing\n", HCLGEVF_NAME); 2972e2cb1decSSalil Mehta 2973854cf33aSFuyun Liang hnae3_register_ae_algo(&ae_algovf); 2974854cf33aSFuyun Liang 2975854cf33aSFuyun Liang return 0; 2976e2cb1decSSalil Mehta } 2977e2cb1decSSalil Mehta 2978e2cb1decSSalil Mehta static void hclgevf_exit(void) 2979e2cb1decSSalil Mehta { 2980e2cb1decSSalil Mehta hnae3_unregister_ae_algo(&ae_algovf); 2981e2cb1decSSalil Mehta } 2982e2cb1decSSalil Mehta module_init(hclgevf_init); 2983e2cb1decSSalil Mehta module_exit(hclgevf_exit); 2984e2cb1decSSalil Mehta 2985e2cb1decSSalil Mehta MODULE_LICENSE("GPL"); 2986e2cb1decSSalil Mehta MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 2987e2cb1decSSalil Mehta MODULE_DESCRIPTION("HCLGEVF Driver"); 2988e2cb1decSSalil Mehta MODULE_VERSION(HCLGEVF_MOD_VERSION); 2989