1e2cb1decSSalil Mehta // SPDX-License-Identifier: GPL-2.0+ 2e2cb1decSSalil Mehta // Copyright (c) 2016-2017 Hisilicon Limited. 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #include <linux/etherdevice.h> 5aa5c4f17SHuazhong Tan #include <linux/iopoll.h> 66988eb2aSSalil Mehta #include <net/rtnetlink.h> 7e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 8e2cb1decSSalil Mehta #include "hclgevf_main.h" 9e2cb1decSSalil Mehta #include "hclge_mbx.h" 10e2cb1decSSalil Mehta #include "hnae3.h" 11cd624299SYufeng Mo #include "hclgevf_devlink.h" 12027733b1SJie Wang #include "hclge_comm_rss.h" 13e2cb1decSSalil Mehta 14e2cb1decSSalil Mehta #define HCLGEVF_NAME "hclgevf" 15e2cb1decSSalil Mehta 16bbe6540eSHuazhong Tan #define HCLGEVF_RESET_MAX_FAIL_CNT 5 17bbe6540eSHuazhong Tan 189c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 195e7414cdSJian Shen static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 205e7414cdSJian Shen unsigned long delay); 215e7414cdSJian Shen 22e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf; 23e2cb1decSSalil Mehta 240ea68902SYunsheng Lin static struct workqueue_struct *hclgevf_wq; 250ea68902SYunsheng Lin 26e2cb1decSSalil Mehta static const struct pci_device_id ae_algovf_pci_tbl[] = { 27c155e22bSGuangbin Huang {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0}, 28c155e22bSGuangbin Huang {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 29c155e22bSGuangbin Huang HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 30e2cb1decSSalil Mehta /* required last entry */ 31e2cb1decSSalil Mehta {0, } 32e2cb1decSSalil Mehta }; 33e2cb1decSSalil Mehta 342f550a46SYunsheng Lin MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 352f550a46SYunsheng Lin 36cb413bfaSJie Wang static const u32 cmdq_reg_addr_list[] = {HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG, 37cb413bfaSJie Wang HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG, 38cb413bfaSJie Wang HCLGE_COMM_NIC_CSQ_DEPTH_REG, 39cb413bfaSJie Wang HCLGE_COMM_NIC_CSQ_TAIL_REG, 40cb413bfaSJie Wang HCLGE_COMM_NIC_CSQ_HEAD_REG, 41cb413bfaSJie Wang HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG, 42cb413bfaSJie Wang HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG, 43cb413bfaSJie Wang HCLGE_COMM_NIC_CRQ_DEPTH_REG, 44cb413bfaSJie Wang HCLGE_COMM_NIC_CRQ_TAIL_REG, 45cb413bfaSJie Wang HCLGE_COMM_NIC_CRQ_HEAD_REG, 46cb413bfaSJie Wang HCLGE_COMM_VECTOR0_CMDQ_SRC_REG, 47cb413bfaSJie Wang HCLGE_COMM_VECTOR0_CMDQ_STATE_REG, 48cb413bfaSJie Wang HCLGE_COMM_CMDQ_INTR_EN_REG, 49cb413bfaSJie Wang HCLGE_COMM_CMDQ_INTR_GEN_REG}; 501600c3e5SJian Shen 511600c3e5SJian Shen static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 521600c3e5SJian Shen HCLGEVF_RST_ING, 531600c3e5SJian Shen HCLGEVF_GRO_EN_REG}; 541600c3e5SJian Shen 551600c3e5SJian Shen static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 561600c3e5SJian Shen HCLGEVF_RING_RX_ADDR_H_REG, 571600c3e5SJian Shen HCLGEVF_RING_RX_BD_NUM_REG, 581600c3e5SJian Shen HCLGEVF_RING_RX_BD_LENGTH_REG, 591600c3e5SJian Shen HCLGEVF_RING_RX_MERGE_EN_REG, 601600c3e5SJian Shen HCLGEVF_RING_RX_TAIL_REG, 611600c3e5SJian Shen HCLGEVF_RING_RX_HEAD_REG, 621600c3e5SJian Shen HCLGEVF_RING_RX_FBD_NUM_REG, 631600c3e5SJian Shen HCLGEVF_RING_RX_OFFSET_REG, 641600c3e5SJian Shen HCLGEVF_RING_RX_FBD_OFFSET_REG, 651600c3e5SJian Shen HCLGEVF_RING_RX_STASH_REG, 661600c3e5SJian Shen HCLGEVF_RING_RX_BD_ERR_REG, 671600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_L_REG, 681600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_H_REG, 691600c3e5SJian Shen HCLGEVF_RING_TX_BD_NUM_REG, 701600c3e5SJian Shen HCLGEVF_RING_TX_PRIORITY_REG, 711600c3e5SJian Shen HCLGEVF_RING_TX_TC_REG, 721600c3e5SJian Shen HCLGEVF_RING_TX_MERGE_EN_REG, 731600c3e5SJian Shen HCLGEVF_RING_TX_TAIL_REG, 741600c3e5SJian Shen HCLGEVF_RING_TX_HEAD_REG, 751600c3e5SJian Shen HCLGEVF_RING_TX_FBD_NUM_REG, 761600c3e5SJian Shen HCLGEVF_RING_TX_OFFSET_REG, 771600c3e5SJian Shen HCLGEVF_RING_TX_EBD_NUM_REG, 781600c3e5SJian Shen HCLGEVF_RING_TX_EBD_OFFSET_REG, 791600c3e5SJian Shen HCLGEVF_RING_TX_BD_ERR_REG, 801600c3e5SJian Shen HCLGEVF_RING_EN_REG}; 811600c3e5SJian Shen 821600c3e5SJian Shen static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 831600c3e5SJian Shen HCLGEVF_TQP_INTR_GL0_REG, 841600c3e5SJian Shen HCLGEVF_TQP_INTR_GL1_REG, 851600c3e5SJian Shen HCLGEVF_TQP_INTR_GL2_REG, 861600c3e5SJian Shen HCLGEVF_TQP_INTR_RL_REG}; 871600c3e5SJian Shen 88aab8d1c6SJie Wang /* hclgevf_cmd_send - send command to command queue 89aab8d1c6SJie Wang * @hw: pointer to the hw struct 90aab8d1c6SJie Wang * @desc: prefilled descriptor for describing the command 91aab8d1c6SJie Wang * @num : the number of descriptors to be sent 92aab8d1c6SJie Wang * 93aab8d1c6SJie Wang * This is the main send command for command queue, it 94aab8d1c6SJie Wang * sends the queue, cleans the queue, etc 95aab8d1c6SJie Wang */ 96aab8d1c6SJie Wang int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclge_desc *desc, int num) 97aab8d1c6SJie Wang { 989970308fSJie Wang return hclge_comm_cmd_send(&hw->hw, desc, num); 99aab8d1c6SJie Wang } 100aab8d1c6SJie Wang 101aab8d1c6SJie Wang void hclgevf_arq_init(struct hclgevf_dev *hdev) 102aab8d1c6SJie Wang { 103aab8d1c6SJie Wang struct hclge_comm_cmq *cmdq = &hdev->hw.hw.cmq; 104aab8d1c6SJie Wang 105aab8d1c6SJie Wang spin_lock(&cmdq->crq.lock); 106aab8d1c6SJie Wang /* initialize the pointers of async rx queue of mailbox */ 107aab8d1c6SJie Wang hdev->arq.hdev = hdev; 108aab8d1c6SJie Wang hdev->arq.head = 0; 109aab8d1c6SJie Wang hdev->arq.tail = 0; 110aab8d1c6SJie Wang atomic_set(&hdev->arq.count, 0); 111aab8d1c6SJie Wang spin_unlock(&cmdq->crq.lock); 112aab8d1c6SJie Wang } 113aab8d1c6SJie Wang 1149b2f3477SWeihang Li static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 115e2cb1decSSalil Mehta { 116eed9535fSPeng Li if (!handle->client) 117eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, nic); 118eed9535fSPeng Li else if (handle->client->type == HNAE3_CLIENT_ROCE) 119eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, roce); 120eed9535fSPeng Li else 121e2cb1decSSalil Mehta return container_of(handle, struct hclgevf_dev, nic); 122e2cb1decSSalil Mehta } 123e2cb1decSSalil Mehta 124e2cb1decSSalil Mehta static void hclgevf_update_stats(struct hnae3_handle *handle, 125e2cb1decSSalil Mehta struct net_device_stats *net_stats) 126e2cb1decSSalil Mehta { 127e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 128e2cb1decSSalil Mehta int status; 129e2cb1decSSalil Mehta 1304afc310cSJie Wang status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 131e2cb1decSSalil Mehta if (status) 132e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 133e2cb1decSSalil Mehta "VF update of TQPS stats fail, status = %d.\n", 134e2cb1decSSalil Mehta status); 135e2cb1decSSalil Mehta } 136e2cb1decSSalil Mehta 137e2cb1decSSalil Mehta static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 138e2cb1decSSalil Mehta { 139e2cb1decSSalil Mehta if (strset == ETH_SS_TEST) 140e2cb1decSSalil Mehta return -EOPNOTSUPP; 141e2cb1decSSalil Mehta else if (strset == ETH_SS_STATS) 1424afc310cSJie Wang return hclge_comm_tqps_get_sset_count(handle); 143e2cb1decSSalil Mehta 144e2cb1decSSalil Mehta return 0; 145e2cb1decSSalil Mehta } 146e2cb1decSSalil Mehta 147e2cb1decSSalil Mehta static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 148e2cb1decSSalil Mehta u8 *data) 149e2cb1decSSalil Mehta { 150e2cb1decSSalil Mehta u8 *p = (char *)data; 151e2cb1decSSalil Mehta 152e2cb1decSSalil Mehta if (strset == ETH_SS_STATS) 1534afc310cSJie Wang p = hclge_comm_tqps_get_strings(handle, p); 154e2cb1decSSalil Mehta } 155e2cb1decSSalil Mehta 156e2cb1decSSalil Mehta static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 157e2cb1decSSalil Mehta { 1584afc310cSJie Wang hclge_comm_tqps_get_stats(handle, data); 159e2cb1decSSalil Mehta } 160e2cb1decSSalil Mehta 161d3410018SYufeng Mo static void hclgevf_build_send_msg(struct hclge_vf_to_pf_msg *msg, u8 code, 162d3410018SYufeng Mo u8 subcode) 163d3410018SYufeng Mo { 164d3410018SYufeng Mo if (msg) { 165d3410018SYufeng Mo memset(msg, 0, sizeof(struct hclge_vf_to_pf_msg)); 166d3410018SYufeng Mo msg->code = code; 167d3410018SYufeng Mo msg->subcode = subcode; 168d3410018SYufeng Mo } 169d3410018SYufeng Mo } 170d3410018SYufeng Mo 17132e6d104SJian Shen static int hclgevf_get_basic_info(struct hclgevf_dev *hdev) 172e2cb1decSSalil Mehta { 17332e6d104SJian Shen struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 17432e6d104SJian Shen u8 resp_msg[HCLGE_MBX_MAX_RESP_DATA_SIZE]; 17532e6d104SJian Shen struct hclge_basic_info *basic_info; 176d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 17732e6d104SJian Shen unsigned long caps; 178e2cb1decSSalil Mehta int status; 179e2cb1decSSalil Mehta 18032e6d104SJian Shen hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_BASIC_INFO, 0); 18132e6d104SJian Shen status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 182d3410018SYufeng Mo sizeof(resp_msg)); 183e2cb1decSSalil Mehta if (status) { 184e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 18532e6d104SJian Shen "failed to get basic info from pf, ret = %d", status); 186e2cb1decSSalil Mehta return status; 187e2cb1decSSalil Mehta } 188e2cb1decSSalil Mehta 18932e6d104SJian Shen basic_info = (struct hclge_basic_info *)resp_msg; 19032e6d104SJian Shen 19132e6d104SJian Shen hdev->hw_tc_map = basic_info->hw_tc_map; 19232e6d104SJian Shen hdev->mbx_api_version = basic_info->mbx_api_version; 19332e6d104SJian Shen caps = basic_info->pf_caps; 19432e6d104SJian Shen if (test_bit(HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B, &caps)) 19532e6d104SJian Shen set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps); 196e2cb1decSSalil Mehta 197e2cb1decSSalil Mehta return 0; 198e2cb1decSSalil Mehta } 199e2cb1decSSalil Mehta 20092f11ea1SJian Shen static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 20192f11ea1SJian Shen { 20292f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 203d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 20492f11ea1SJian Shen u8 resp_msg; 20592f11ea1SJian Shen int ret; 20692f11ea1SJian Shen 207d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 208d3410018SYufeng Mo HCLGE_MBX_GET_PORT_BASE_VLAN_STATE); 209d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg, 210d3410018SYufeng Mo sizeof(u8)); 21192f11ea1SJian Shen if (ret) { 21292f11ea1SJian Shen dev_err(&hdev->pdev->dev, 21392f11ea1SJian Shen "VF request to get port based vlan state failed %d", 21492f11ea1SJian Shen ret); 21592f11ea1SJian Shen return ret; 21692f11ea1SJian Shen } 21792f11ea1SJian Shen 21892f11ea1SJian Shen nic->port_base_vlan_state = resp_msg; 21992f11ea1SJian Shen 22092f11ea1SJian Shen return 0; 22192f11ea1SJian Shen } 22292f11ea1SJian Shen 2236cee6fc3SJian Shen static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 224e2cb1decSSalil Mehta { 225c0425944SPeng Li #define HCLGEVF_TQPS_RSS_INFO_LEN 6 226d3410018SYufeng Mo #define HCLGEVF_TQPS_ALLOC_OFFSET 0 227d3410018SYufeng Mo #define HCLGEVF_TQPS_RSS_SIZE_OFFSET 2 228d3410018SYufeng Mo #define HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET 4 229d3410018SYufeng Mo 230e2cb1decSSalil Mehta u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 231d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 232e2cb1decSSalil Mehta int status; 233e2cb1decSSalil Mehta 234d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QINFO, 0); 235d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 236e2cb1decSSalil Mehta HCLGEVF_TQPS_RSS_INFO_LEN); 237e2cb1decSSalil Mehta if (status) { 238e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 239e2cb1decSSalil Mehta "VF request to get tqp info from PF failed %d", 240e2cb1decSSalil Mehta status); 241e2cb1decSSalil Mehta return status; 242e2cb1decSSalil Mehta } 243e2cb1decSSalil Mehta 244d3410018SYufeng Mo memcpy(&hdev->num_tqps, &resp_msg[HCLGEVF_TQPS_ALLOC_OFFSET], 245d3410018SYufeng Mo sizeof(u16)); 246d3410018SYufeng Mo memcpy(&hdev->rss_size_max, &resp_msg[HCLGEVF_TQPS_RSS_SIZE_OFFSET], 247d3410018SYufeng Mo sizeof(u16)); 248d3410018SYufeng Mo memcpy(&hdev->rx_buf_len, &resp_msg[HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET], 249d3410018SYufeng Mo sizeof(u16)); 250c0425944SPeng Li 251c0425944SPeng Li return 0; 252c0425944SPeng Li } 253c0425944SPeng Li 254c0425944SPeng Li static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 255c0425944SPeng Li { 256c0425944SPeng Li #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 257d3410018SYufeng Mo #define HCLGEVF_TQPS_NUM_TX_DESC_OFFSET 0 258d3410018SYufeng Mo #define HCLGEVF_TQPS_NUM_RX_DESC_OFFSET 2 259d3410018SYufeng Mo 260c0425944SPeng Li u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 261d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 262c0425944SPeng Li int ret; 263c0425944SPeng Li 264d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QDEPTH, 0); 265d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 266c0425944SPeng Li HCLGEVF_TQPS_DEPTH_INFO_LEN); 267c0425944SPeng Li if (ret) { 268c0425944SPeng Li dev_err(&hdev->pdev->dev, 269c0425944SPeng Li "VF request to get tqp depth info from PF failed %d", 270c0425944SPeng Li ret); 271c0425944SPeng Li return ret; 272c0425944SPeng Li } 273c0425944SPeng Li 274d3410018SYufeng Mo memcpy(&hdev->num_tx_desc, &resp_msg[HCLGEVF_TQPS_NUM_TX_DESC_OFFSET], 275d3410018SYufeng Mo sizeof(u16)); 276d3410018SYufeng Mo memcpy(&hdev->num_rx_desc, &resp_msg[HCLGEVF_TQPS_NUM_RX_DESC_OFFSET], 277d3410018SYufeng Mo sizeof(u16)); 278e2cb1decSSalil Mehta 279e2cb1decSSalil Mehta return 0; 280e2cb1decSSalil Mehta } 281e2cb1decSSalil Mehta 2820c29d191Sliuzhongzhu static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 2830c29d191Sliuzhongzhu { 2840c29d191Sliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 285d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 2860c29d191Sliuzhongzhu u16 qid_in_pf = 0; 287d3410018SYufeng Mo u8 resp_data[2]; 2880c29d191Sliuzhongzhu int ret; 2890c29d191Sliuzhongzhu 290d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QID_IN_PF, 0); 291d3410018SYufeng Mo memcpy(send_msg.data, &queue_id, sizeof(queue_id)); 292d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_data, 29363cbf7a9SYufeng Mo sizeof(resp_data)); 2940c29d191Sliuzhongzhu if (!ret) 2950c29d191Sliuzhongzhu qid_in_pf = *(u16 *)resp_data; 2960c29d191Sliuzhongzhu 2970c29d191Sliuzhongzhu return qid_in_pf; 2980c29d191Sliuzhongzhu } 2990c29d191Sliuzhongzhu 3009c3e7130Sliuzhongzhu static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 3019c3e7130Sliuzhongzhu { 302d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 30388d10bd6SJian Shen u8 resp_msg[2]; 3049c3e7130Sliuzhongzhu int ret; 3059c3e7130Sliuzhongzhu 306d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MEDIA_TYPE, 0); 307d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 308d3410018SYufeng Mo sizeof(resp_msg)); 3099c3e7130Sliuzhongzhu if (ret) { 3109c3e7130Sliuzhongzhu dev_err(&hdev->pdev->dev, 3119c3e7130Sliuzhongzhu "VF request to get the pf port media type failed %d", 3129c3e7130Sliuzhongzhu ret); 3139c3e7130Sliuzhongzhu return ret; 3149c3e7130Sliuzhongzhu } 3159c3e7130Sliuzhongzhu 31688d10bd6SJian Shen hdev->hw.mac.media_type = resp_msg[0]; 31788d10bd6SJian Shen hdev->hw.mac.module_type = resp_msg[1]; 3189c3e7130Sliuzhongzhu 3199c3e7130Sliuzhongzhu return 0; 3209c3e7130Sliuzhongzhu } 3219c3e7130Sliuzhongzhu 322e2cb1decSSalil Mehta static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 323e2cb1decSSalil Mehta { 3244afc310cSJie Wang struct hclge_comm_tqp *tqp; 325e2cb1decSSalil Mehta int i; 326e2cb1decSSalil Mehta 327e2cb1decSSalil Mehta hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 3284afc310cSJie Wang sizeof(struct hclge_comm_tqp), GFP_KERNEL); 329e2cb1decSSalil Mehta if (!hdev->htqp) 330e2cb1decSSalil Mehta return -ENOMEM; 331e2cb1decSSalil Mehta 332e2cb1decSSalil Mehta tqp = hdev->htqp; 333e2cb1decSSalil Mehta 334e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 335e2cb1decSSalil Mehta tqp->dev = &hdev->pdev->dev; 336e2cb1decSSalil Mehta tqp->index = i; 337e2cb1decSSalil Mehta 338e2cb1decSSalil Mehta tqp->q.ae_algo = &ae_algovf; 339e2cb1decSSalil Mehta tqp->q.buf_size = hdev->rx_buf_len; 340c0425944SPeng Li tqp->q.tx_desc_num = hdev->num_tx_desc; 341c0425944SPeng Li tqp->q.rx_desc_num = hdev->num_rx_desc; 3429a5ef4aaSYonglong Liu 3439a5ef4aaSYonglong Liu /* need an extended offset to configure queues >= 3449a5ef4aaSYonglong Liu * HCLGEVF_TQP_MAX_SIZE_DEV_V2. 3459a5ef4aaSYonglong Liu */ 3469a5ef4aaSYonglong Liu if (i < HCLGEVF_TQP_MAX_SIZE_DEV_V2) 347076bb537SJie Wang tqp->q.io_base = hdev->hw.hw.io_base + 3489a5ef4aaSYonglong Liu HCLGEVF_TQP_REG_OFFSET + 349e2cb1decSSalil Mehta i * HCLGEVF_TQP_REG_SIZE; 3509a5ef4aaSYonglong Liu else 351076bb537SJie Wang tqp->q.io_base = hdev->hw.hw.io_base + 3529a5ef4aaSYonglong Liu HCLGEVF_TQP_REG_OFFSET + 3539a5ef4aaSYonglong Liu HCLGEVF_TQP_EXT_REG_OFFSET + 3549a5ef4aaSYonglong Liu (i - HCLGEVF_TQP_MAX_SIZE_DEV_V2) * 3559a5ef4aaSYonglong Liu HCLGEVF_TQP_REG_SIZE; 356e2cb1decSSalil Mehta 357e2cb1decSSalil Mehta tqp++; 358e2cb1decSSalil Mehta } 359e2cb1decSSalil Mehta 360e2cb1decSSalil Mehta return 0; 361e2cb1decSSalil Mehta } 362e2cb1decSSalil Mehta 363e2cb1decSSalil Mehta static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 364e2cb1decSSalil Mehta { 365e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 366e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo; 367e2cb1decSSalil Mehta u16 new_tqps = hdev->num_tqps; 368ebaf1908SWeihang Li unsigned int i; 36935244430SJian Shen u8 num_tc = 0; 370e2cb1decSSalil Mehta 371e2cb1decSSalil Mehta kinfo = &nic->kinfo; 372c0425944SPeng Li kinfo->num_tx_desc = hdev->num_tx_desc; 373c0425944SPeng Li kinfo->num_rx_desc = hdev->num_rx_desc; 374e2cb1decSSalil Mehta kinfo->rx_buf_len = hdev->rx_buf_len; 37593969dc1SJie Wang for (i = 0; i < HCLGE_COMM_MAX_TC_NUM; i++) 376e2cb1decSSalil Mehta if (hdev->hw_tc_map & BIT(i)) 37735244430SJian Shen num_tc++; 378e2cb1decSSalil Mehta 37935244430SJian Shen num_tc = num_tc ? num_tc : 1; 38035244430SJian Shen kinfo->tc_info.num_tc = num_tc; 38135244430SJian Shen kinfo->rss_size = min_t(u16, hdev->rss_size_max, new_tqps / num_tc); 38235244430SJian Shen new_tqps = kinfo->rss_size * num_tc; 383e2cb1decSSalil Mehta kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 384e2cb1decSSalil Mehta 385e2cb1decSSalil Mehta kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 386e2cb1decSSalil Mehta sizeof(struct hnae3_queue *), GFP_KERNEL); 387e2cb1decSSalil Mehta if (!kinfo->tqp) 388e2cb1decSSalil Mehta return -ENOMEM; 389e2cb1decSSalil Mehta 390e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 391e2cb1decSSalil Mehta hdev->htqp[i].q.handle = &hdev->nic; 392e2cb1decSSalil Mehta hdev->htqp[i].q.tqp_index = i; 393e2cb1decSSalil Mehta kinfo->tqp[i] = &hdev->htqp[i].q; 394e2cb1decSSalil Mehta } 395e2cb1decSSalil Mehta 396580a05f9SYonglong Liu /* after init the max rss_size and tqps, adjust the default tqp numbers 397580a05f9SYonglong Liu * and rss size with the actual vector numbers 398580a05f9SYonglong Liu */ 399580a05f9SYonglong Liu kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps); 40035244430SJian Shen kinfo->rss_size = min_t(u16, kinfo->num_tqps / num_tc, 401580a05f9SYonglong Liu kinfo->rss_size); 402580a05f9SYonglong Liu 403e2cb1decSSalil Mehta return 0; 404e2cb1decSSalil Mehta } 405e2cb1decSSalil Mehta 406e2cb1decSSalil Mehta static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 407e2cb1decSSalil Mehta { 408d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 409e2cb1decSSalil Mehta int status; 410e2cb1decSSalil Mehta 411d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_STATUS, 0); 412d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 413e2cb1decSSalil Mehta if (status) 414e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 415e2cb1decSSalil Mehta "VF failed to fetch link status(%d) from PF", status); 416e2cb1decSSalil Mehta } 417e2cb1decSSalil Mehta 418e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 419e2cb1decSSalil Mehta { 42045e92b7eSPeng Li struct hnae3_handle *rhandle = &hdev->roce; 421e2cb1decSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 42245e92b7eSPeng Li struct hnae3_client *rclient; 423e2cb1decSSalil Mehta struct hnae3_client *client; 424e2cb1decSSalil Mehta 425ff200099SYunsheng Lin if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state)) 426ff200099SYunsheng Lin return; 427ff200099SYunsheng Lin 428e2cb1decSSalil Mehta client = handle->client; 42945e92b7eSPeng Li rclient = hdev->roce_client; 430e2cb1decSSalil Mehta 431582d37bbSPeng Li link_state = 432582d37bbSPeng Li test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 433e2cb1decSSalil Mehta if (link_state != hdev->hw.mac.link) { 434b15c072aSYonglong Liu hdev->hw.mac.link = link_state; 435e2cb1decSSalil Mehta client->ops->link_status_change(handle, !!link_state); 43645e92b7eSPeng Li if (rclient && rclient->ops->link_status_change) 43745e92b7eSPeng Li rclient->ops->link_status_change(rhandle, !!link_state); 438e2cb1decSSalil Mehta } 439ff200099SYunsheng Lin 440ff200099SYunsheng Lin clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state); 441e2cb1decSSalil Mehta } 442e2cb1decSSalil Mehta 443538abaf3SYueHaibing static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 4449194d18bSliuzhongzhu { 4459194d18bSliuzhongzhu #define HCLGEVF_ADVERTISING 0 4469194d18bSliuzhongzhu #define HCLGEVF_SUPPORTED 1 4479194d18bSliuzhongzhu 448d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 449d3410018SYufeng Mo 450d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_MODE, 0); 451d3410018SYufeng Mo send_msg.data[0] = HCLGEVF_ADVERTISING; 452d3410018SYufeng Mo hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 453d3410018SYufeng Mo send_msg.data[0] = HCLGEVF_SUPPORTED; 454d3410018SYufeng Mo hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 4559194d18bSliuzhongzhu } 4569194d18bSliuzhongzhu 457e2cb1decSSalil Mehta static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 458e2cb1decSSalil Mehta { 459e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 460e2cb1decSSalil Mehta int ret; 461e2cb1decSSalil Mehta 462e2cb1decSSalil Mehta nic->ae_algo = &ae_algovf; 463e2cb1decSSalil Mehta nic->pdev = hdev->pdev; 464e2cb1decSSalil Mehta nic->numa_node_mask = hdev->numa_node_mask; 465424eb834SSalil Mehta nic->flags |= HNAE3_SUPPORT_VF; 466076bb537SJie Wang nic->kinfo.io_base = hdev->hw.hw.io_base; 467e2cb1decSSalil Mehta 468e2cb1decSSalil Mehta ret = hclgevf_knic_setup(hdev); 469e2cb1decSSalil Mehta if (ret) 470e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 471e2cb1decSSalil Mehta ret); 472e2cb1decSSalil Mehta return ret; 473e2cb1decSSalil Mehta } 474e2cb1decSSalil Mehta 475e2cb1decSSalil Mehta static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 476e2cb1decSSalil Mehta { 47736cbbdf6SPeng Li if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 47836cbbdf6SPeng Li dev_warn(&hdev->pdev->dev, 47936cbbdf6SPeng Li "vector(vector_id %d) has been freed.\n", vector_id); 48036cbbdf6SPeng Li return; 48136cbbdf6SPeng Li } 48236cbbdf6SPeng Li 483e2cb1decSSalil Mehta hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 484e2cb1decSSalil Mehta hdev->num_msi_left += 1; 485e2cb1decSSalil Mehta hdev->num_msi_used -= 1; 486e2cb1decSSalil Mehta } 487e2cb1decSSalil Mehta 488e2cb1decSSalil Mehta static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 489e2cb1decSSalil Mehta struct hnae3_vector_info *vector_info) 490e2cb1decSSalil Mehta { 491e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 492e2cb1decSSalil Mehta struct hnae3_vector_info *vector = vector_info; 493e2cb1decSSalil Mehta int alloc = 0; 494e2cb1decSSalil Mehta int i, j; 495e2cb1decSSalil Mehta 496580a05f9SYonglong Liu vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num); 497e2cb1decSSalil Mehta vector_num = min(hdev->num_msi_left, vector_num); 498e2cb1decSSalil Mehta 499e2cb1decSSalil Mehta for (j = 0; j < vector_num; j++) { 500e2cb1decSSalil Mehta for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 501e2cb1decSSalil Mehta if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 502e2cb1decSSalil Mehta vector->vector = pci_irq_vector(hdev->pdev, i); 503076bb537SJie Wang vector->io_addr = hdev->hw.hw.io_base + 504e2cb1decSSalil Mehta HCLGEVF_VECTOR_REG_BASE + 505e2cb1decSSalil Mehta (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 506e2cb1decSSalil Mehta hdev->vector_status[i] = 0; 507e2cb1decSSalil Mehta hdev->vector_irq[i] = vector->vector; 508e2cb1decSSalil Mehta 509e2cb1decSSalil Mehta vector++; 510e2cb1decSSalil Mehta alloc++; 511e2cb1decSSalil Mehta 512e2cb1decSSalil Mehta break; 513e2cb1decSSalil Mehta } 514e2cb1decSSalil Mehta } 515e2cb1decSSalil Mehta } 516e2cb1decSSalil Mehta hdev->num_msi_left -= alloc; 517e2cb1decSSalil Mehta hdev->num_msi_used += alloc; 518e2cb1decSSalil Mehta 519e2cb1decSSalil Mehta return alloc; 520e2cb1decSSalil Mehta } 521e2cb1decSSalil Mehta 522e2cb1decSSalil Mehta static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 523e2cb1decSSalil Mehta { 524e2cb1decSSalil Mehta int i; 525e2cb1decSSalil Mehta 526e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 527e2cb1decSSalil Mehta if (vector == hdev->vector_irq[i]) 528e2cb1decSSalil Mehta return i; 529e2cb1decSSalil Mehta 530e2cb1decSSalil Mehta return -EINVAL; 531e2cb1decSSalil Mehta } 532e2cb1decSSalil Mehta 533a638b1d8SJian Shen /* for revision 0x20, vf shared the same rss config with pf */ 534a638b1d8SJian Shen static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 535a638b1d8SJian Shen { 536a638b1d8SJian Shen #define HCLGEVF_RSS_MBX_RESP_LEN 8 537027733b1SJie Wang struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 538a638b1d8SJian Shen u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 539d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 540a638b1d8SJian Shen u16 msg_num, hash_key_index; 541a638b1d8SJian Shen u8 index; 542a638b1d8SJian Shen int ret; 543a638b1d8SJian Shen 544d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_RSS_KEY, 0); 5457428d6c9SJie Wang msg_num = (HCLGE_COMM_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 546a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN; 547a638b1d8SJian Shen for (index = 0; index < msg_num; index++) { 548d3410018SYufeng Mo send_msg.data[0] = index; 549d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 550a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN); 551a638b1d8SJian Shen if (ret) { 552a638b1d8SJian Shen dev_err(&hdev->pdev->dev, 553a638b1d8SJian Shen "VF get rss hash key from PF failed, ret=%d", 554a638b1d8SJian Shen ret); 555a638b1d8SJian Shen return ret; 556a638b1d8SJian Shen } 557a638b1d8SJian Shen 558a638b1d8SJian Shen hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 559a638b1d8SJian Shen if (index == msg_num - 1) 560a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 561a638b1d8SJian Shen &resp_msg[0], 5627428d6c9SJie Wang HCLGE_COMM_RSS_KEY_SIZE - hash_key_index); 563a638b1d8SJian Shen else 564a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 565a638b1d8SJian Shen &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 566a638b1d8SJian Shen } 567a638b1d8SJian Shen 568a638b1d8SJian Shen return 0; 569a638b1d8SJian Shen } 570a638b1d8SJian Shen 571e2cb1decSSalil Mehta static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 572e2cb1decSSalil Mehta u8 *hfunc) 573e2cb1decSSalil Mehta { 574e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 575027733b1SJie Wang struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 5767428d6c9SJie Wang int ret; 577e2cb1decSSalil Mehta 578295ba232SGuangbin Huang if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 5797428d6c9SJie Wang hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc); 580a638b1d8SJian Shen } else { 581a638b1d8SJian Shen if (hfunc) 582a638b1d8SJian Shen *hfunc = ETH_RSS_HASH_TOP; 583a638b1d8SJian Shen if (key) { 584a638b1d8SJian Shen ret = hclgevf_get_rss_hash_key(hdev); 585a638b1d8SJian Shen if (ret) 586a638b1d8SJian Shen return ret; 587a638b1d8SJian Shen memcpy(key, rss_cfg->rss_hash_key, 5887428d6c9SJie Wang HCLGE_COMM_RSS_KEY_SIZE); 589a638b1d8SJian Shen } 590374ad291SJian Shen } 591374ad291SJian Shen 5927428d6c9SJie Wang hclge_comm_get_rss_indir_tbl(rss_cfg, indir, 5937428d6c9SJie Wang hdev->ae_dev->dev_specs.rss_ind_tbl_size); 594e2cb1decSSalil Mehta 595374ad291SJian Shen return 0; 596e2cb1decSSalil Mehta } 597e2cb1decSSalil Mehta 598e2cb1decSSalil Mehta static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 599e2cb1decSSalil Mehta const u8 *key, const u8 hfunc) 600e2cb1decSSalil Mehta { 601e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 602027733b1SJie Wang struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 603374ad291SJian Shen int ret, i; 604374ad291SJian Shen 605295ba232SGuangbin Huang if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 60693969dc1SJie Wang ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, 60793969dc1SJie Wang hfunc); 608374ad291SJian Shen if (ret) 609374ad291SJian Shen return ret; 610374ad291SJian Shen } 611e2cb1decSSalil Mehta 612e2cb1decSSalil Mehta /* update the shadow RSS table with user specified qids */ 61387ce161eSGuangbin Huang for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 614e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = indir[i]; 615e2cb1decSSalil Mehta 616e2cb1decSSalil Mehta /* update the hardware */ 6177428d6c9SJie Wang return hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 6187428d6c9SJie Wang rss_cfg->rss_indirection_tbl); 6195fd0e7b4SHuazhong Tan } 6205fd0e7b4SHuazhong Tan 6215fd0e7b4SHuazhong Tan static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 6225fd0e7b4SHuazhong Tan struct ethtool_rxnfc *nfc) 6235fd0e7b4SHuazhong Tan { 6245fd0e7b4SHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 6255fd0e7b4SHuazhong Tan int ret; 6265fd0e7b4SHuazhong Tan 6275fd0e7b4SHuazhong Tan if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 6285fd0e7b4SHuazhong Tan return -EOPNOTSUPP; 6295fd0e7b4SHuazhong Tan 63093969dc1SJie Wang ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw, 63193969dc1SJie Wang &hdev->rss_cfg, nfc); 63293969dc1SJie Wang if (ret) 6335fd0e7b4SHuazhong Tan dev_err(&hdev->pdev->dev, 63493969dc1SJie Wang "failed to set rss tuple, ret = %d.\n", ret); 6355fd0e7b4SHuazhong Tan 636d97b3072SJian Shen return ret; 637d97b3072SJian Shen } 638d97b3072SJian Shen 639d97b3072SJian Shen static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 640d97b3072SJian Shen struct ethtool_rxnfc *nfc) 641d97b3072SJian Shen { 642d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 643d97b3072SJian Shen u8 tuple_sets; 64473f7767eSJian Shen int ret; 645d97b3072SJian Shen 646295ba232SGuangbin Huang if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 647d97b3072SJian Shen return -EOPNOTSUPP; 648d97b3072SJian Shen 649d97b3072SJian Shen nfc->data = 0; 650d97b3072SJian Shen 651027733b1SJie Wang ret = hclge_comm_get_rss_tuple(&hdev->rss_cfg, nfc->flow_type, 65273f7767eSJian Shen &tuple_sets); 65373f7767eSJian Shen if (ret || !tuple_sets) 65473f7767eSJian Shen return ret; 655d97b3072SJian Shen 6567428d6c9SJie Wang nfc->data = hclge_comm_convert_rss_tuple(tuple_sets); 657d97b3072SJian Shen 658d97b3072SJian Shen return 0; 659d97b3072SJian Shen } 660d97b3072SJian Shen 661e2cb1decSSalil Mehta static int hclgevf_get_tc_size(struct hnae3_handle *handle) 662e2cb1decSSalil Mehta { 663e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 664027733b1SJie Wang struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 665e2cb1decSSalil Mehta 666e2cb1decSSalil Mehta return rss_cfg->rss_size; 667e2cb1decSSalil Mehta } 668e2cb1decSSalil Mehta 669e2cb1decSSalil Mehta static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 670b204bc74SPeng Li int vector_id, 671e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 672e2cb1decSSalil Mehta { 673e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 674d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 675e2cb1decSSalil Mehta struct hnae3_ring_chain_node *node; 676e2cb1decSSalil Mehta int status; 677d3410018SYufeng Mo int i = 0; 678e2cb1decSSalil Mehta 679d3410018SYufeng Mo memset(&send_msg, 0, sizeof(send_msg)); 680d3410018SYufeng Mo send_msg.code = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 681c09ba484SPeng Li HCLGE_MBX_UNMAP_RING_TO_VECTOR; 682d3410018SYufeng Mo send_msg.vector_id = vector_id; 683e2cb1decSSalil Mehta 684e2cb1decSSalil Mehta for (node = ring_chain; node; node = node->next) { 685d3410018SYufeng Mo send_msg.param[i].ring_type = 686e4e87715SPeng Li hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 687d3410018SYufeng Mo 688d3410018SYufeng Mo send_msg.param[i].tqp_index = node->tqp_index; 689d3410018SYufeng Mo send_msg.param[i].int_gl_index = 690d3410018SYufeng Mo hnae3_get_field(node->int_gl_idx, 69179eee410SFuyun Liang HNAE3_RING_GL_IDX_M, 69279eee410SFuyun Liang HNAE3_RING_GL_IDX_S); 69379eee410SFuyun Liang 6945d02a58dSYunsheng Lin i++; 695d3410018SYufeng Mo if (i == HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM || !node->next) { 696d3410018SYufeng Mo send_msg.ring_num = i; 697e2cb1decSSalil Mehta 698d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, false, 699d3410018SYufeng Mo NULL, 0); 700e2cb1decSSalil Mehta if (status) { 701e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 702e2cb1decSSalil Mehta "Map TQP fail, status is %d.\n", 703e2cb1decSSalil Mehta status); 704e2cb1decSSalil Mehta return status; 705e2cb1decSSalil Mehta } 706e2cb1decSSalil Mehta i = 0; 707e2cb1decSSalil Mehta } 708e2cb1decSSalil Mehta } 709e2cb1decSSalil Mehta 710e2cb1decSSalil Mehta return 0; 711e2cb1decSSalil Mehta } 712e2cb1decSSalil Mehta 713e2cb1decSSalil Mehta static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 714e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 715e2cb1decSSalil Mehta { 716b204bc74SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 717b204bc74SPeng Li int vector_id; 718b204bc74SPeng Li 719b204bc74SPeng Li vector_id = hclgevf_get_vector_index(hdev, vector); 720b204bc74SPeng Li if (vector_id < 0) { 721b204bc74SPeng Li dev_err(&handle->pdev->dev, 722b204bc74SPeng Li "Get vector index fail. ret =%d\n", vector_id); 723b204bc74SPeng Li return vector_id; 724b204bc74SPeng Li } 725b204bc74SPeng Li 726b204bc74SPeng Li return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 727e2cb1decSSalil Mehta } 728e2cb1decSSalil Mehta 729e2cb1decSSalil Mehta static int hclgevf_unmap_ring_from_vector( 730e2cb1decSSalil Mehta struct hnae3_handle *handle, 731e2cb1decSSalil Mehta int vector, 732e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 733e2cb1decSSalil Mehta { 734e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 735e2cb1decSSalil Mehta int ret, vector_id; 736e2cb1decSSalil Mehta 737dea846e8SHuazhong Tan if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 738dea846e8SHuazhong Tan return 0; 739dea846e8SHuazhong Tan 740e2cb1decSSalil Mehta vector_id = hclgevf_get_vector_index(hdev, vector); 741e2cb1decSSalil Mehta if (vector_id < 0) { 742e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 743e2cb1decSSalil Mehta "Get vector index fail. ret =%d\n", vector_id); 744e2cb1decSSalil Mehta return vector_id; 745e2cb1decSSalil Mehta } 746e2cb1decSSalil Mehta 747b204bc74SPeng Li ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 7480d3e6631SYunsheng Lin if (ret) 749e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 750e2cb1decSSalil Mehta "Unmap ring from vector fail. vector=%d, ret =%d\n", 751e2cb1decSSalil Mehta vector_id, 752e2cb1decSSalil Mehta ret); 7530d3e6631SYunsheng Lin 754e2cb1decSSalil Mehta return ret; 755e2cb1decSSalil Mehta } 756e2cb1decSSalil Mehta 7570d3e6631SYunsheng Lin static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 7580d3e6631SYunsheng Lin { 7590d3e6631SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 76003718db9SYunsheng Lin int vector_id; 7610d3e6631SYunsheng Lin 76203718db9SYunsheng Lin vector_id = hclgevf_get_vector_index(hdev, vector); 76303718db9SYunsheng Lin if (vector_id < 0) { 76403718db9SYunsheng Lin dev_err(&handle->pdev->dev, 76503718db9SYunsheng Lin "hclgevf_put_vector get vector index fail. ret =%d\n", 76603718db9SYunsheng Lin vector_id); 76703718db9SYunsheng Lin return vector_id; 76803718db9SYunsheng Lin } 76903718db9SYunsheng Lin 77003718db9SYunsheng Lin hclgevf_free_vector(hdev, vector_id); 771e2cb1decSSalil Mehta 772e2cb1decSSalil Mehta return 0; 773e2cb1decSSalil Mehta } 774e2cb1decSSalil Mehta 7753b75c3dfSPeng Li static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 776e196ec75SJian Shen bool en_uc_pmc, bool en_mc_pmc, 777f01f5559SJian Shen bool en_bc_pmc) 778e2cb1decSSalil Mehta { 7795e7414cdSJian Shen struct hnae3_handle *handle = &hdev->nic; 780d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 781f01f5559SJian Shen int ret; 782e2cb1decSSalil Mehta 783d3410018SYufeng Mo memset(&send_msg, 0, sizeof(send_msg)); 784d3410018SYufeng Mo send_msg.code = HCLGE_MBX_SET_PROMISC_MODE; 785d3410018SYufeng Mo send_msg.en_bc = en_bc_pmc ? 1 : 0; 786d3410018SYufeng Mo send_msg.en_uc = en_uc_pmc ? 1 : 0; 787d3410018SYufeng Mo send_msg.en_mc = en_mc_pmc ? 1 : 0; 7885e7414cdSJian Shen send_msg.en_limit_promisc = test_bit(HNAE3_PFLAG_LIMIT_PROMISC, 7895e7414cdSJian Shen &handle->priv_flags) ? 1 : 0; 790e2cb1decSSalil Mehta 791d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 792f01f5559SJian Shen if (ret) 793e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 794f01f5559SJian Shen "Set promisc mode fail, status is %d.\n", ret); 795e2cb1decSSalil Mehta 796f01f5559SJian Shen return ret; 797e2cb1decSSalil Mehta } 798e2cb1decSSalil Mehta 799e196ec75SJian Shen static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 800e196ec75SJian Shen bool en_mc_pmc) 801e2cb1decSSalil Mehta { 802e196ec75SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 803e196ec75SJian Shen bool en_bc_pmc; 804e196ec75SJian Shen 805295ba232SGuangbin Huang en_bc_pmc = hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2; 806e196ec75SJian Shen 807e196ec75SJian Shen return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc, 808e196ec75SJian Shen en_bc_pmc); 809e2cb1decSSalil Mehta } 810e2cb1decSSalil Mehta 811c631c696SJian Shen static void hclgevf_request_update_promisc_mode(struct hnae3_handle *handle) 812c631c696SJian Shen { 813c631c696SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 814c631c696SJian Shen 815c631c696SJian Shen set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 8165e7414cdSJian Shen hclgevf_task_schedule(hdev, 0); 817c631c696SJian Shen } 818c631c696SJian Shen 819c631c696SJian Shen static void hclgevf_sync_promisc_mode(struct hclgevf_dev *hdev) 820c631c696SJian Shen { 821c631c696SJian Shen struct hnae3_handle *handle = &hdev->nic; 822c631c696SJian Shen bool en_uc_pmc = handle->netdev_flags & HNAE3_UPE; 823c631c696SJian Shen bool en_mc_pmc = handle->netdev_flags & HNAE3_MPE; 824c631c696SJian Shen int ret; 825c631c696SJian Shen 826c631c696SJian Shen if (test_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state)) { 827c631c696SJian Shen ret = hclgevf_set_promisc_mode(handle, en_uc_pmc, en_mc_pmc); 828c631c696SJian Shen if (!ret) 829c631c696SJian Shen clear_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 830c631c696SJian Shen } 831c631c696SJian Shen } 832c631c696SJian Shen 8338fa86551SYufeng Mo static int hclgevf_tqp_enable_cmd_send(struct hclgevf_dev *hdev, u16 tqp_id, 8348fa86551SYufeng Mo u16 stream_id, bool enable) 835e2cb1decSSalil Mehta { 836e2cb1decSSalil Mehta struct hclgevf_cfg_com_tqp_queue_cmd *req; 8376befad60SJie Wang struct hclge_desc desc; 838e2cb1decSSalil Mehta 839e2cb1decSSalil Mehta req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 840e2cb1decSSalil Mehta 841*43710bfeSJie Wang hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); 842e2cb1decSSalil Mehta req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 843e2cb1decSSalil Mehta req->stream_id = cpu_to_le16(stream_id); 844ebaf1908SWeihang Li if (enable) 845ebaf1908SWeihang Li req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 846e2cb1decSSalil Mehta 8478fa86551SYufeng Mo return hclgevf_cmd_send(&hdev->hw, &desc, 1); 8488fa86551SYufeng Mo } 849e2cb1decSSalil Mehta 8508fa86551SYufeng Mo static int hclgevf_tqp_enable(struct hnae3_handle *handle, bool enable) 8518fa86551SYufeng Mo { 8528fa86551SYufeng Mo struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 8538fa86551SYufeng Mo int ret; 8548fa86551SYufeng Mo u16 i; 8558fa86551SYufeng Mo 8568fa86551SYufeng Mo for (i = 0; i < handle->kinfo.num_tqps; i++) { 8578fa86551SYufeng Mo ret = hclgevf_tqp_enable_cmd_send(hdev, i, 0, enable); 8588fa86551SYufeng Mo if (ret) 8598fa86551SYufeng Mo return ret; 8608fa86551SYufeng Mo } 8618fa86551SYufeng Mo 8628fa86551SYufeng Mo return 0; 863e2cb1decSSalil Mehta } 864e2cb1decSSalil Mehta 8658e6de441SHuazhong Tan static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p) 8668e6de441SHuazhong Tan { 867d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 8688e6de441SHuazhong Tan u8 host_mac[ETH_ALEN]; 8698e6de441SHuazhong Tan int status; 8708e6de441SHuazhong Tan 871d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MAC_ADDR, 0); 872d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, true, host_mac, 873d3410018SYufeng Mo ETH_ALEN); 8748e6de441SHuazhong Tan if (status) { 8758e6de441SHuazhong Tan dev_err(&hdev->pdev->dev, 8768e6de441SHuazhong Tan "fail to get VF MAC from host %d", status); 8778e6de441SHuazhong Tan return status; 8788e6de441SHuazhong Tan } 8798e6de441SHuazhong Tan 8808e6de441SHuazhong Tan ether_addr_copy(p, host_mac); 8818e6de441SHuazhong Tan 8828e6de441SHuazhong Tan return 0; 8838e6de441SHuazhong Tan } 8848e6de441SHuazhong Tan 885e2cb1decSSalil Mehta static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 886e2cb1decSSalil Mehta { 887e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 8888e6de441SHuazhong Tan u8 host_mac_addr[ETH_ALEN]; 889e2cb1decSSalil Mehta 8908e6de441SHuazhong Tan if (hclgevf_get_host_mac_addr(hdev, host_mac_addr)) 8918e6de441SHuazhong Tan return; 8928e6de441SHuazhong Tan 8938e6de441SHuazhong Tan hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr); 8948e6de441SHuazhong Tan if (hdev->has_pf_mac) 8958e6de441SHuazhong Tan ether_addr_copy(p, host_mac_addr); 8968e6de441SHuazhong Tan else 897e2cb1decSSalil Mehta ether_addr_copy(p, hdev->hw.mac.mac_addr); 898e2cb1decSSalil Mehta } 899e2cb1decSSalil Mehta 90076660757SJakub Kicinski static int hclgevf_set_mac_addr(struct hnae3_handle *handle, const void *p, 90159098055SFuyun Liang bool is_first) 902e2cb1decSSalil Mehta { 903e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 904e2cb1decSSalil Mehta u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 905d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 906e2cb1decSSalil Mehta u8 *new_mac_addr = (u8 *)p; 907e2cb1decSSalil Mehta int status; 908e2cb1decSSalil Mehta 909d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 0); 910ee4bcd3bSJian Shen send_msg.subcode = HCLGE_MBX_MAC_VLAN_UC_MODIFY; 911d3410018SYufeng Mo ether_addr_copy(send_msg.data, new_mac_addr); 912ee4bcd3bSJian Shen if (is_first && !hdev->has_pf_mac) 913ee4bcd3bSJian Shen eth_zero_addr(&send_msg.data[ETH_ALEN]); 914ee4bcd3bSJian Shen else 915d3410018SYufeng Mo ether_addr_copy(&send_msg.data[ETH_ALEN], old_mac_addr); 916d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 917e2cb1decSSalil Mehta if (!status) 918e2cb1decSSalil Mehta ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 919e2cb1decSSalil Mehta 920e2cb1decSSalil Mehta return status; 921e2cb1decSSalil Mehta } 922e2cb1decSSalil Mehta 923ee4bcd3bSJian Shen static struct hclgevf_mac_addr_node * 924ee4bcd3bSJian Shen hclgevf_find_mac_node(struct list_head *list, const u8 *mac_addr) 925ee4bcd3bSJian Shen { 926ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp; 927ee4bcd3bSJian Shen 928ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, list, node) 929ee4bcd3bSJian Shen if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 930ee4bcd3bSJian Shen return mac_node; 931ee4bcd3bSJian Shen 932ee4bcd3bSJian Shen return NULL; 933ee4bcd3bSJian Shen } 934ee4bcd3bSJian Shen 935ee4bcd3bSJian Shen static void hclgevf_update_mac_node(struct hclgevf_mac_addr_node *mac_node, 936ee4bcd3bSJian Shen enum HCLGEVF_MAC_NODE_STATE state) 937ee4bcd3bSJian Shen { 938ee4bcd3bSJian Shen switch (state) { 939ee4bcd3bSJian Shen /* from set_rx_mode or tmp_add_list */ 940ee4bcd3bSJian Shen case HCLGEVF_MAC_TO_ADD: 941ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_DEL) 942ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_ACTIVE; 943ee4bcd3bSJian Shen break; 944ee4bcd3bSJian Shen /* only from set_rx_mode */ 945ee4bcd3bSJian Shen case HCLGEVF_MAC_TO_DEL: 946ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 947ee4bcd3bSJian Shen list_del(&mac_node->node); 948ee4bcd3bSJian Shen kfree(mac_node); 949ee4bcd3bSJian Shen } else { 950ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_TO_DEL; 951ee4bcd3bSJian Shen } 952ee4bcd3bSJian Shen break; 953ee4bcd3bSJian Shen /* only from tmp_add_list, the mac_node->state won't be 954ee4bcd3bSJian Shen * HCLGEVF_MAC_ACTIVE 955ee4bcd3bSJian Shen */ 956ee4bcd3bSJian Shen case HCLGEVF_MAC_ACTIVE: 957ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) 958ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_ACTIVE; 959ee4bcd3bSJian Shen break; 960ee4bcd3bSJian Shen } 961ee4bcd3bSJian Shen } 962ee4bcd3bSJian Shen 963ee4bcd3bSJian Shen static int hclgevf_update_mac_list(struct hnae3_handle *handle, 964ee4bcd3bSJian Shen enum HCLGEVF_MAC_NODE_STATE state, 965ee4bcd3bSJian Shen enum HCLGEVF_MAC_ADDR_TYPE mac_type, 966e2cb1decSSalil Mehta const unsigned char *addr) 967e2cb1decSSalil Mehta { 968e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 969ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node; 970ee4bcd3bSJian Shen struct list_head *list; 971e2cb1decSSalil Mehta 972ee4bcd3bSJian Shen list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 973ee4bcd3bSJian Shen &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 974ee4bcd3bSJian Shen 975ee4bcd3bSJian Shen spin_lock_bh(&hdev->mac_table.mac_list_lock); 976ee4bcd3bSJian Shen 977ee4bcd3bSJian Shen /* if the mac addr is already in the mac list, no need to add a new 978ee4bcd3bSJian Shen * one into it, just check the mac addr state, convert it to a new 979ee4bcd3bSJian Shen * new state, or just remove it, or do nothing. 980ee4bcd3bSJian Shen */ 981ee4bcd3bSJian Shen mac_node = hclgevf_find_mac_node(list, addr); 982ee4bcd3bSJian Shen if (mac_node) { 983ee4bcd3bSJian Shen hclgevf_update_mac_node(mac_node, state); 984ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 985ee4bcd3bSJian Shen return 0; 986ee4bcd3bSJian Shen } 987ee4bcd3bSJian Shen /* if this address is never added, unnecessary to delete */ 988ee4bcd3bSJian Shen if (state == HCLGEVF_MAC_TO_DEL) { 989ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 990ee4bcd3bSJian Shen return -ENOENT; 991ee4bcd3bSJian Shen } 992ee4bcd3bSJian Shen 993ee4bcd3bSJian Shen mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 994ee4bcd3bSJian Shen if (!mac_node) { 995ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 996ee4bcd3bSJian Shen return -ENOMEM; 997ee4bcd3bSJian Shen } 998ee4bcd3bSJian Shen 999ee4bcd3bSJian Shen mac_node->state = state; 1000ee4bcd3bSJian Shen ether_addr_copy(mac_node->mac_addr, addr); 1001ee4bcd3bSJian Shen list_add_tail(&mac_node->node, list); 1002ee4bcd3bSJian Shen 1003ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1004ee4bcd3bSJian Shen return 0; 1005ee4bcd3bSJian Shen } 1006ee4bcd3bSJian Shen 1007ee4bcd3bSJian Shen static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1008ee4bcd3bSJian Shen const unsigned char *addr) 1009ee4bcd3bSJian Shen { 1010ee4bcd3bSJian Shen return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1011ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_UC, addr); 1012e2cb1decSSalil Mehta } 1013e2cb1decSSalil Mehta 1014e2cb1decSSalil Mehta static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1015e2cb1decSSalil Mehta const unsigned char *addr) 1016e2cb1decSSalil Mehta { 1017ee4bcd3bSJian Shen return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1018ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_UC, addr); 1019e2cb1decSSalil Mehta } 1020e2cb1decSSalil Mehta 1021e2cb1decSSalil Mehta static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1022e2cb1decSSalil Mehta const unsigned char *addr) 1023e2cb1decSSalil Mehta { 1024ee4bcd3bSJian Shen return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1025ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_MC, addr); 1026e2cb1decSSalil Mehta } 1027e2cb1decSSalil Mehta 1028e2cb1decSSalil Mehta static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1029e2cb1decSSalil Mehta const unsigned char *addr) 1030e2cb1decSSalil Mehta { 1031ee4bcd3bSJian Shen return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1032ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_MC, addr); 1033ee4bcd3bSJian Shen } 1034e2cb1decSSalil Mehta 1035ee4bcd3bSJian Shen static int hclgevf_add_del_mac_addr(struct hclgevf_dev *hdev, 1036ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, 1037ee4bcd3bSJian Shen enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1038ee4bcd3bSJian Shen { 1039ee4bcd3bSJian Shen struct hclge_vf_to_pf_msg send_msg; 1040ee4bcd3bSJian Shen u8 code, subcode; 1041ee4bcd3bSJian Shen 1042ee4bcd3bSJian Shen if (mac_type == HCLGEVF_MAC_ADDR_UC) { 1043ee4bcd3bSJian Shen code = HCLGE_MBX_SET_UNICAST; 1044ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1045ee4bcd3bSJian Shen subcode = HCLGE_MBX_MAC_VLAN_UC_ADD; 1046ee4bcd3bSJian Shen else 1047ee4bcd3bSJian Shen subcode = HCLGE_MBX_MAC_VLAN_UC_REMOVE; 1048ee4bcd3bSJian Shen } else { 1049ee4bcd3bSJian Shen code = HCLGE_MBX_SET_MULTICAST; 1050ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1051ee4bcd3bSJian Shen subcode = HCLGE_MBX_MAC_VLAN_MC_ADD; 1052ee4bcd3bSJian Shen else 1053ee4bcd3bSJian Shen subcode = HCLGE_MBX_MAC_VLAN_MC_REMOVE; 1054ee4bcd3bSJian Shen } 1055ee4bcd3bSJian Shen 1056ee4bcd3bSJian Shen hclgevf_build_send_msg(&send_msg, code, subcode); 1057ee4bcd3bSJian Shen ether_addr_copy(send_msg.data, mac_node->mac_addr); 1058d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1059e2cb1decSSalil Mehta } 1060e2cb1decSSalil Mehta 1061ee4bcd3bSJian Shen static void hclgevf_config_mac_list(struct hclgevf_dev *hdev, 1062ee4bcd3bSJian Shen struct list_head *list, 1063ee4bcd3bSJian Shen enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1064ee4bcd3bSJian Shen { 10654f331fdaSYufeng Mo char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 1066ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp; 1067ee4bcd3bSJian Shen int ret; 1068ee4bcd3bSJian Shen 1069ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, list, node) { 1070ee4bcd3bSJian Shen ret = hclgevf_add_del_mac_addr(hdev, mac_node, mac_type); 1071ee4bcd3bSJian Shen if (ret) { 10724f331fdaSYufeng Mo hnae3_format_mac_addr(format_mac_addr, 10734f331fdaSYufeng Mo mac_node->mac_addr); 1074ee4bcd3bSJian Shen dev_err(&hdev->pdev->dev, 10754f331fdaSYufeng Mo "failed to configure mac %s, state = %d, ret = %d\n", 10764f331fdaSYufeng Mo format_mac_addr, mac_node->state, ret); 1077ee4bcd3bSJian Shen return; 1078ee4bcd3bSJian Shen } 1079ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1080ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_ACTIVE; 1081ee4bcd3bSJian Shen } else { 1082ee4bcd3bSJian Shen list_del(&mac_node->node); 1083ee4bcd3bSJian Shen kfree(mac_node); 1084ee4bcd3bSJian Shen } 1085ee4bcd3bSJian Shen } 1086ee4bcd3bSJian Shen } 1087ee4bcd3bSJian Shen 1088ee4bcd3bSJian Shen static void hclgevf_sync_from_add_list(struct list_head *add_list, 1089ee4bcd3bSJian Shen struct list_head *mac_list) 1090ee4bcd3bSJian Shen { 1091ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1092ee4bcd3bSJian Shen 1093ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, add_list, node) { 1094ee4bcd3bSJian Shen /* if the mac address from tmp_add_list is not in the 1095ee4bcd3bSJian Shen * uc/mc_mac_list, it means have received a TO_DEL request 1096ee4bcd3bSJian Shen * during the time window of sending mac config request to PF 1097ee4bcd3bSJian Shen * If mac_node state is ACTIVE, then change its state to TO_DEL, 1098ee4bcd3bSJian Shen * then it will be removed at next time. If is TO_ADD, it means 1099ee4bcd3bSJian Shen * send TO_ADD request failed, so just remove the mac node. 1100ee4bcd3bSJian Shen */ 1101ee4bcd3bSJian Shen new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1102ee4bcd3bSJian Shen if (new_node) { 1103ee4bcd3bSJian Shen hclgevf_update_mac_node(new_node, mac_node->state); 1104ee4bcd3bSJian Shen list_del(&mac_node->node); 1105ee4bcd3bSJian Shen kfree(mac_node); 1106ee4bcd3bSJian Shen } else if (mac_node->state == HCLGEVF_MAC_ACTIVE) { 1107ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_TO_DEL; 110849768ce9SBaokun Li list_move_tail(&mac_node->node, mac_list); 1109ee4bcd3bSJian Shen } else { 1110ee4bcd3bSJian Shen list_del(&mac_node->node); 1111ee4bcd3bSJian Shen kfree(mac_node); 1112ee4bcd3bSJian Shen } 1113ee4bcd3bSJian Shen } 1114ee4bcd3bSJian Shen } 1115ee4bcd3bSJian Shen 1116ee4bcd3bSJian Shen static void hclgevf_sync_from_del_list(struct list_head *del_list, 1117ee4bcd3bSJian Shen struct list_head *mac_list) 1118ee4bcd3bSJian Shen { 1119ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1120ee4bcd3bSJian Shen 1121ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, del_list, node) { 1122ee4bcd3bSJian Shen new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1123ee4bcd3bSJian Shen if (new_node) { 1124ee4bcd3bSJian Shen /* If the mac addr is exist in the mac list, it means 1125ee4bcd3bSJian Shen * received a new request TO_ADD during the time window 1126ee4bcd3bSJian Shen * of sending mac addr configurrequest to PF, so just 1127ee4bcd3bSJian Shen * change the mac state to ACTIVE. 1128ee4bcd3bSJian Shen */ 1129ee4bcd3bSJian Shen new_node->state = HCLGEVF_MAC_ACTIVE; 1130ee4bcd3bSJian Shen list_del(&mac_node->node); 1131ee4bcd3bSJian Shen kfree(mac_node); 1132ee4bcd3bSJian Shen } else { 113349768ce9SBaokun Li list_move_tail(&mac_node->node, mac_list); 1134ee4bcd3bSJian Shen } 1135ee4bcd3bSJian Shen } 1136ee4bcd3bSJian Shen } 1137ee4bcd3bSJian Shen 1138ee4bcd3bSJian Shen static void hclgevf_clear_list(struct list_head *list) 1139ee4bcd3bSJian Shen { 1140ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp; 1141ee4bcd3bSJian Shen 1142ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, list, node) { 1143ee4bcd3bSJian Shen list_del(&mac_node->node); 1144ee4bcd3bSJian Shen kfree(mac_node); 1145ee4bcd3bSJian Shen } 1146ee4bcd3bSJian Shen } 1147ee4bcd3bSJian Shen 1148ee4bcd3bSJian Shen static void hclgevf_sync_mac_list(struct hclgevf_dev *hdev, 1149ee4bcd3bSJian Shen enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1150ee4bcd3bSJian Shen { 1151ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1152ee4bcd3bSJian Shen struct list_head tmp_add_list, tmp_del_list; 1153ee4bcd3bSJian Shen struct list_head *list; 1154ee4bcd3bSJian Shen 1155ee4bcd3bSJian Shen INIT_LIST_HEAD(&tmp_add_list); 1156ee4bcd3bSJian Shen INIT_LIST_HEAD(&tmp_del_list); 1157ee4bcd3bSJian Shen 1158ee4bcd3bSJian Shen /* move the mac addr to the tmp_add_list and tmp_del_list, then 1159ee4bcd3bSJian Shen * we can add/delete these mac addr outside the spin lock 1160ee4bcd3bSJian Shen */ 1161ee4bcd3bSJian Shen list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1162ee4bcd3bSJian Shen &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1163ee4bcd3bSJian Shen 1164ee4bcd3bSJian Shen spin_lock_bh(&hdev->mac_table.mac_list_lock); 1165ee4bcd3bSJian Shen 1166ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, list, node) { 1167ee4bcd3bSJian Shen switch (mac_node->state) { 1168ee4bcd3bSJian Shen case HCLGEVF_MAC_TO_DEL: 116949768ce9SBaokun Li list_move_tail(&mac_node->node, &tmp_del_list); 1170ee4bcd3bSJian Shen break; 1171ee4bcd3bSJian Shen case HCLGEVF_MAC_TO_ADD: 1172ee4bcd3bSJian Shen new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 1173ee4bcd3bSJian Shen if (!new_node) 1174ee4bcd3bSJian Shen goto stop_traverse; 1175ee4bcd3bSJian Shen 1176ee4bcd3bSJian Shen ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 1177ee4bcd3bSJian Shen new_node->state = mac_node->state; 1178ee4bcd3bSJian Shen list_add_tail(&new_node->node, &tmp_add_list); 1179ee4bcd3bSJian Shen break; 1180ee4bcd3bSJian Shen default: 1181ee4bcd3bSJian Shen break; 1182ee4bcd3bSJian Shen } 1183ee4bcd3bSJian Shen } 1184ee4bcd3bSJian Shen 1185ee4bcd3bSJian Shen stop_traverse: 1186ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1187ee4bcd3bSJian Shen 1188ee4bcd3bSJian Shen /* delete first, in order to get max mac table space for adding */ 1189ee4bcd3bSJian Shen hclgevf_config_mac_list(hdev, &tmp_del_list, mac_type); 1190ee4bcd3bSJian Shen hclgevf_config_mac_list(hdev, &tmp_add_list, mac_type); 1191ee4bcd3bSJian Shen 1192ee4bcd3bSJian Shen /* if some mac addresses were added/deleted fail, move back to the 1193ee4bcd3bSJian Shen * mac_list, and retry at next time. 1194ee4bcd3bSJian Shen */ 1195ee4bcd3bSJian Shen spin_lock_bh(&hdev->mac_table.mac_list_lock); 1196ee4bcd3bSJian Shen 1197ee4bcd3bSJian Shen hclgevf_sync_from_del_list(&tmp_del_list, list); 1198ee4bcd3bSJian Shen hclgevf_sync_from_add_list(&tmp_add_list, list); 1199ee4bcd3bSJian Shen 1200ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1201ee4bcd3bSJian Shen } 1202ee4bcd3bSJian Shen 1203ee4bcd3bSJian Shen static void hclgevf_sync_mac_table(struct hclgevf_dev *hdev) 1204ee4bcd3bSJian Shen { 1205ee4bcd3bSJian Shen hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_UC); 1206ee4bcd3bSJian Shen hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_MC); 1207ee4bcd3bSJian Shen } 1208ee4bcd3bSJian Shen 1209ee4bcd3bSJian Shen static void hclgevf_uninit_mac_list(struct hclgevf_dev *hdev) 1210ee4bcd3bSJian Shen { 1211ee4bcd3bSJian Shen spin_lock_bh(&hdev->mac_table.mac_list_lock); 1212ee4bcd3bSJian Shen 1213ee4bcd3bSJian Shen hclgevf_clear_list(&hdev->mac_table.uc_mac_list); 1214ee4bcd3bSJian Shen hclgevf_clear_list(&hdev->mac_table.mc_mac_list); 1215ee4bcd3bSJian Shen 1216ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1217ee4bcd3bSJian Shen } 1218ee4bcd3bSJian Shen 1219fa6a262aSJian Shen static int hclgevf_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 1220fa6a262aSJian Shen { 1221fa6a262aSJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1222fa6a262aSJian Shen struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 1223fa6a262aSJian Shen struct hclge_vf_to_pf_msg send_msg; 1224fa6a262aSJian Shen 1225fa6a262aSJian Shen if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 1226fa6a262aSJian Shen return -EOPNOTSUPP; 1227fa6a262aSJian Shen 1228fa6a262aSJian Shen hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1229fa6a262aSJian Shen HCLGE_MBX_ENABLE_VLAN_FILTER); 1230fa6a262aSJian Shen send_msg.data[0] = enable ? 1 : 0; 1231fa6a262aSJian Shen 1232fa6a262aSJian Shen return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1233fa6a262aSJian Shen } 1234fa6a262aSJian Shen 1235e2cb1decSSalil Mehta static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1236e2cb1decSSalil Mehta __be16 proto, u16 vlan_id, 1237e2cb1decSSalil Mehta bool is_kill) 1238e2cb1decSSalil Mehta { 1239d3410018SYufeng Mo #define HCLGEVF_VLAN_MBX_IS_KILL_OFFSET 0 1240d3410018SYufeng Mo #define HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET 1 1241d3410018SYufeng Mo #define HCLGEVF_VLAN_MBX_PROTO_OFFSET 3 1242d3410018SYufeng Mo 1243e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1244d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1245fe4144d4SJian Shen int ret; 1246e2cb1decSSalil Mehta 1247b37ce587SYufeng Mo if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1248e2cb1decSSalil Mehta return -EINVAL; 1249e2cb1decSSalil Mehta 1250e2cb1decSSalil Mehta if (proto != htons(ETH_P_8021Q)) 1251e2cb1decSSalil Mehta return -EPROTONOSUPPORT; 1252e2cb1decSSalil Mehta 1253b7b5d25bSGuojia Liao /* When device is resetting or reset failed, firmware is unable to 1254b7b5d25bSGuojia Liao * handle mailbox. Just record the vlan id, and remove it after 1255fe4144d4SJian Shen * reset finished. 1256fe4144d4SJian Shen */ 1257b7b5d25bSGuojia Liao if ((test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 1258b7b5d25bSGuojia Liao test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) && is_kill) { 1259fe4144d4SJian Shen set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1260fe4144d4SJian Shen return -EBUSY; 1261fe4144d4SJian Shen } 1262fe4144d4SJian Shen 1263d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1264d3410018SYufeng Mo HCLGE_MBX_VLAN_FILTER); 1265d3410018SYufeng Mo send_msg.data[HCLGEVF_VLAN_MBX_IS_KILL_OFFSET] = is_kill; 1266d3410018SYufeng Mo memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET], &vlan_id, 1267d3410018SYufeng Mo sizeof(vlan_id)); 1268d3410018SYufeng Mo memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_PROTO_OFFSET], &proto, 1269d3410018SYufeng Mo sizeof(proto)); 127046ee7350SGuojia Liao /* when remove hw vlan filter failed, record the vlan id, 1271fe4144d4SJian Shen * and try to remove it from hw later, to be consistence 1272fe4144d4SJian Shen * with stack. 1273fe4144d4SJian Shen */ 1274d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1275fe4144d4SJian Shen if (is_kill && ret) 1276fe4144d4SJian Shen set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1277fe4144d4SJian Shen 1278fe4144d4SJian Shen return ret; 1279fe4144d4SJian Shen } 1280fe4144d4SJian Shen 1281fe4144d4SJian Shen static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1282fe4144d4SJian Shen { 1283fe4144d4SJian Shen #define HCLGEVF_MAX_SYNC_COUNT 60 1284fe4144d4SJian Shen struct hnae3_handle *handle = &hdev->nic; 1285fe4144d4SJian Shen int ret, sync_cnt = 0; 1286fe4144d4SJian Shen u16 vlan_id; 1287fe4144d4SJian Shen 1288fe4144d4SJian Shen vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1289fe4144d4SJian Shen while (vlan_id != VLAN_N_VID) { 1290fe4144d4SJian Shen ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1291fe4144d4SJian Shen vlan_id, true); 1292fe4144d4SJian Shen if (ret) 1293fe4144d4SJian Shen return; 1294fe4144d4SJian Shen 1295fe4144d4SJian Shen clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1296fe4144d4SJian Shen sync_cnt++; 1297fe4144d4SJian Shen if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1298fe4144d4SJian Shen return; 1299fe4144d4SJian Shen 1300fe4144d4SJian Shen vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1301fe4144d4SJian Shen } 1302e2cb1decSSalil Mehta } 1303e2cb1decSSalil Mehta 1304b2641e2aSYunsheng Lin static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1305b2641e2aSYunsheng Lin { 1306b2641e2aSYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1307d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1308b2641e2aSYunsheng Lin 1309d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1310d3410018SYufeng Mo HCLGE_MBX_VLAN_RX_OFF_CFG); 1311d3410018SYufeng Mo send_msg.data[0] = enable ? 1 : 0; 1312d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1313b2641e2aSYunsheng Lin } 1314b2641e2aSYunsheng Lin 13158fa86551SYufeng Mo static int hclgevf_reset_tqp(struct hnae3_handle *handle) 1316e2cb1decSSalil Mehta { 13178fa86551SYufeng Mo #define HCLGEVF_RESET_ALL_QUEUE_DONE 1U 1318e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1319d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 13208fa86551SYufeng Mo u8 return_status = 0; 13211a426f8bSPeng Li int ret; 13228fa86551SYufeng Mo u16 i; 1323e2cb1decSSalil Mehta 13241a426f8bSPeng Li /* disable vf queue before send queue reset msg to PF */ 13258fa86551SYufeng Mo ret = hclgevf_tqp_enable(handle, false); 13268fa86551SYufeng Mo if (ret) { 13278fa86551SYufeng Mo dev_err(&hdev->pdev->dev, "failed to disable tqp, ret = %d\n", 13288fa86551SYufeng Mo ret); 13297fa6be4fSHuazhong Tan return ret; 13308fa86551SYufeng Mo } 13311a426f8bSPeng Li 1332d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 13338fa86551SYufeng Mo 13348fa86551SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &return_status, 13358fa86551SYufeng Mo sizeof(return_status)); 13368fa86551SYufeng Mo if (ret || return_status == HCLGEVF_RESET_ALL_QUEUE_DONE) 13378fa86551SYufeng Mo return ret; 13388fa86551SYufeng Mo 13398fa86551SYufeng Mo for (i = 1; i < handle->kinfo.num_tqps; i++) { 13408fa86551SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 13418fa86551SYufeng Mo memcpy(send_msg.data, &i, sizeof(i)); 13428fa86551SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 13438fa86551SYufeng Mo if (ret) 13448fa86551SYufeng Mo return ret; 13458fa86551SYufeng Mo } 13468fa86551SYufeng Mo 13478fa86551SYufeng Mo return 0; 1348e2cb1decSSalil Mehta } 1349e2cb1decSSalil Mehta 1350818f1675SYunsheng Lin static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1351818f1675SYunsheng Lin { 1352818f1675SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1353d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1354818f1675SYunsheng Lin 1355d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MTU, 0); 1356d3410018SYufeng Mo memcpy(send_msg.data, &new_mtu, sizeof(new_mtu)); 1357d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1358818f1675SYunsheng Lin } 1359818f1675SYunsheng Lin 13606988eb2aSSalil Mehta static int hclgevf_notify_client(struct hclgevf_dev *hdev, 13616988eb2aSSalil Mehta enum hnae3_reset_notify_type type) 13626988eb2aSSalil Mehta { 13636988eb2aSSalil Mehta struct hnae3_client *client = hdev->nic_client; 13646988eb2aSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 13656a5f6fa3SHuazhong Tan int ret; 13666988eb2aSSalil Mehta 136725d1817cSHuazhong Tan if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 136825d1817cSHuazhong Tan !client) 136925d1817cSHuazhong Tan return 0; 137025d1817cSHuazhong Tan 13716988eb2aSSalil Mehta if (!client->ops->reset_notify) 13726988eb2aSSalil Mehta return -EOPNOTSUPP; 13736988eb2aSSalil Mehta 13746a5f6fa3SHuazhong Tan ret = client->ops->reset_notify(handle, type); 13756a5f6fa3SHuazhong Tan if (ret) 13766a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 13776a5f6fa3SHuazhong Tan type, ret); 13786a5f6fa3SHuazhong Tan 13796a5f6fa3SHuazhong Tan return ret; 13806988eb2aSSalil Mehta } 13816988eb2aSSalil Mehta 1382fe735c84SHuazhong Tan static int hclgevf_notify_roce_client(struct hclgevf_dev *hdev, 1383fe735c84SHuazhong Tan enum hnae3_reset_notify_type type) 1384fe735c84SHuazhong Tan { 1385fe735c84SHuazhong Tan struct hnae3_client *client = hdev->roce_client; 1386fe735c84SHuazhong Tan struct hnae3_handle *handle = &hdev->roce; 1387fe735c84SHuazhong Tan int ret; 1388fe735c84SHuazhong Tan 1389fe735c84SHuazhong Tan if (!test_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state) || !client) 1390fe735c84SHuazhong Tan return 0; 1391fe735c84SHuazhong Tan 1392fe735c84SHuazhong Tan if (!client->ops->reset_notify) 1393fe735c84SHuazhong Tan return -EOPNOTSUPP; 1394fe735c84SHuazhong Tan 1395fe735c84SHuazhong Tan ret = client->ops->reset_notify(handle, type); 1396fe735c84SHuazhong Tan if (ret) 1397fe735c84SHuazhong Tan dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 1398fe735c84SHuazhong Tan type, ret); 1399fe735c84SHuazhong Tan return ret; 1400fe735c84SHuazhong Tan } 1401fe735c84SHuazhong Tan 14026988eb2aSSalil Mehta static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 14036988eb2aSSalil Mehta { 1404aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_US 20000 1405aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_CNT 2000 1406aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1407aa5c4f17SHuazhong Tan (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1408aa5c4f17SHuazhong Tan 1409aa5c4f17SHuazhong Tan u32 val; 1410aa5c4f17SHuazhong Tan int ret; 14116988eb2aSSalil Mehta 1412f28368bbSHuazhong Tan if (hdev->reset_type == HNAE3_VF_RESET) 1413076bb537SJie Wang ret = readl_poll_timeout(hdev->hw.hw.io_base + 141472e2fb07SHuazhong Tan HCLGEVF_VF_RST_ING, val, 141572e2fb07SHuazhong Tan !(val & HCLGEVF_VF_RST_ING_BIT), 141672e2fb07SHuazhong Tan HCLGEVF_RESET_WAIT_US, 141772e2fb07SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 141872e2fb07SHuazhong Tan else 1419076bb537SJie Wang ret = readl_poll_timeout(hdev->hw.hw.io_base + 142072e2fb07SHuazhong Tan HCLGEVF_RST_ING, val, 1421aa5c4f17SHuazhong Tan !(val & HCLGEVF_RST_ING_BITS), 1422aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_US, 1423aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 14246988eb2aSSalil Mehta 14256988eb2aSSalil Mehta /* hardware completion status should be available by this time */ 1426aa5c4f17SHuazhong Tan if (ret) { 1427aa5c4f17SHuazhong Tan dev_err(&hdev->pdev->dev, 14288912fd6aSColin Ian King "couldn't get reset done status from h/w, timeout!\n"); 1429aa5c4f17SHuazhong Tan return ret; 14306988eb2aSSalil Mehta } 14316988eb2aSSalil Mehta 14326988eb2aSSalil Mehta /* we will wait a bit more to let reset of the stack to complete. This 14336988eb2aSSalil Mehta * might happen in case reset assertion was made by PF. Yes, this also 14346988eb2aSSalil Mehta * means we might end up waiting bit more even for VF reset. 14356988eb2aSSalil Mehta */ 14366988eb2aSSalil Mehta msleep(5000); 14376988eb2aSSalil Mehta 14386988eb2aSSalil Mehta return 0; 14396988eb2aSSalil Mehta } 14406988eb2aSSalil Mehta 14416b428b4fSHuazhong Tan static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable) 14426b428b4fSHuazhong Tan { 14436b428b4fSHuazhong Tan u32 reg_val; 14446b428b4fSHuazhong Tan 1445cb413bfaSJie Wang reg_val = hclgevf_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG); 14466b428b4fSHuazhong Tan if (enable) 14476b428b4fSHuazhong Tan reg_val |= HCLGEVF_NIC_SW_RST_RDY; 14486b428b4fSHuazhong Tan else 14496b428b4fSHuazhong Tan reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; 14506b428b4fSHuazhong Tan 1451cb413bfaSJie Wang hclgevf_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, 14526b428b4fSHuazhong Tan reg_val); 14536b428b4fSHuazhong Tan } 14546b428b4fSHuazhong Tan 14556988eb2aSSalil Mehta static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 14566988eb2aSSalil Mehta { 14577a01c897SSalil Mehta int ret; 14587a01c897SSalil Mehta 14596988eb2aSSalil Mehta /* uninitialize the nic client */ 14606a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 14616a5f6fa3SHuazhong Tan if (ret) 14626a5f6fa3SHuazhong Tan return ret; 14636988eb2aSSalil Mehta 14647a01c897SSalil Mehta /* re-initialize the hclge device */ 14659c6f7085SHuazhong Tan ret = hclgevf_reset_hdev(hdev); 14667a01c897SSalil Mehta if (ret) { 14677a01c897SSalil Mehta dev_err(&hdev->pdev->dev, 14687a01c897SSalil Mehta "hclge device re-init failed, VF is disabled!\n"); 14697a01c897SSalil Mehta return ret; 14707a01c897SSalil Mehta } 14716988eb2aSSalil Mehta 14726988eb2aSSalil Mehta /* bring up the nic client again */ 14736a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 14746a5f6fa3SHuazhong Tan if (ret) 14756a5f6fa3SHuazhong Tan return ret; 14766988eb2aSSalil Mehta 14776b428b4fSHuazhong Tan /* clear handshake status with IMP */ 14786b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, false); 14796b428b4fSHuazhong Tan 14801cc9bc6eSHuazhong Tan /* bring up the nic to enable TX/RX again */ 14811cc9bc6eSHuazhong Tan return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 14826988eb2aSSalil Mehta } 14836988eb2aSSalil Mehta 1484dea846e8SHuazhong Tan static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1485dea846e8SHuazhong Tan { 1486ada13ee3SHuazhong Tan #define HCLGEVF_RESET_SYNC_TIME 100 1487ada13ee3SHuazhong Tan 1488f28368bbSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FUNC_RESET) { 1489d41884eeSHuazhong Tan struct hclge_vf_to_pf_msg send_msg; 1490d41884eeSHuazhong Tan int ret; 1491d41884eeSHuazhong Tan 1492d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_RESET, 0); 1493d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1494cddd5648SHuazhong Tan if (ret) { 1495cddd5648SHuazhong Tan dev_err(&hdev->pdev->dev, 1496cddd5648SHuazhong Tan "failed to assert VF reset, ret = %d\n", ret); 1497cddd5648SHuazhong Tan return ret; 1498cddd5648SHuazhong Tan } 1499c88a6e7dSHuazhong Tan hdev->rst_stats.vf_func_rst_cnt++; 1500dea846e8SHuazhong Tan } 1501dea846e8SHuazhong Tan 1502076bb537SJie Wang set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 1503ada13ee3SHuazhong Tan /* inform hardware that preparatory work is done */ 1504ada13ee3SHuazhong Tan msleep(HCLGEVF_RESET_SYNC_TIME); 15056b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, true); 1506d41884eeSHuazhong Tan dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done\n", 1507d41884eeSHuazhong Tan hdev->reset_type); 1508dea846e8SHuazhong Tan 1509d41884eeSHuazhong Tan return 0; 1510dea846e8SHuazhong Tan } 1511dea846e8SHuazhong Tan 15123d77d0cbSHuazhong Tan static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev) 15133d77d0cbSHuazhong Tan { 15143d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "VF function reset count: %u\n", 15153d77d0cbSHuazhong Tan hdev->rst_stats.vf_func_rst_cnt); 15163d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "FLR reset count: %u\n", 15173d77d0cbSHuazhong Tan hdev->rst_stats.flr_rst_cnt); 15183d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "VF reset count: %u\n", 15193d77d0cbSHuazhong Tan hdev->rst_stats.vf_rst_cnt); 15203d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "reset done count: %u\n", 15213d77d0cbSHuazhong Tan hdev->rst_stats.rst_done_cnt); 15223d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "HW reset done count: %u\n", 15233d77d0cbSHuazhong Tan hdev->rst_stats.hw_rst_done_cnt); 15243d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "reset count: %u\n", 15253d77d0cbSHuazhong Tan hdev->rst_stats.rst_cnt); 15263d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "reset fail count: %u\n", 15273d77d0cbSHuazhong Tan hdev->rst_stats.rst_fail_cnt); 15283d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n", 15293d77d0cbSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE)); 15303d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n", 1531cb413bfaSJie Wang hclgevf_read_dev(&hdev->hw, HCLGE_COMM_VECTOR0_CMDQ_STATE_REG)); 15323d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n", 1533cb413bfaSJie Wang hclgevf_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG)); 15343d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n", 15353d77d0cbSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING)); 15363d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state); 15373d77d0cbSHuazhong Tan } 15383d77d0cbSHuazhong Tan 1539bbe6540eSHuazhong Tan static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1540bbe6540eSHuazhong Tan { 15416b428b4fSHuazhong Tan /* recover handshake status with IMP when reset fail */ 15426b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, true); 1543bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt++; 1544adcf738bSGuojia Liao dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n", 1545bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt); 1546bbe6540eSHuazhong Tan 1547bbe6540eSHuazhong Tan if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1548bbe6540eSHuazhong Tan set_bit(hdev->reset_type, &hdev->reset_pending); 1549bbe6540eSHuazhong Tan 1550bbe6540eSHuazhong Tan if (hclgevf_is_reset_pending(hdev)) { 1551bbe6540eSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1552bbe6540eSHuazhong Tan hclgevf_reset_task_schedule(hdev); 15533d77d0cbSHuazhong Tan } else { 1554d5432455SGuojia Liao set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 15553d77d0cbSHuazhong Tan hclgevf_dump_rst_info(hdev); 1556bbe6540eSHuazhong Tan } 1557bbe6540eSHuazhong Tan } 1558bbe6540eSHuazhong Tan 15591cc9bc6eSHuazhong Tan static int hclgevf_reset_prepare(struct hclgevf_dev *hdev) 15606988eb2aSSalil Mehta { 15616988eb2aSSalil Mehta int ret; 15626988eb2aSSalil Mehta 1563c88a6e7dSHuazhong Tan hdev->rst_stats.rst_cnt++; 15646988eb2aSSalil Mehta 1565fe735c84SHuazhong Tan /* perform reset of the stack & ae device for a client */ 1566fe735c84SHuazhong Tan ret = hclgevf_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 1567fe735c84SHuazhong Tan if (ret) 1568fe735c84SHuazhong Tan return ret; 1569fe735c84SHuazhong Tan 15701cc9bc6eSHuazhong Tan rtnl_lock(); 15716988eb2aSSalil Mehta /* bring down the nic to stop any ongoing TX/RX */ 15726a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 157329118ab9SHuazhong Tan rtnl_unlock(); 15746a5f6fa3SHuazhong Tan if (ret) 15751cc9bc6eSHuazhong Tan return ret; 1576dea846e8SHuazhong Tan 15771cc9bc6eSHuazhong Tan return hclgevf_reset_prepare_wait(hdev); 15786988eb2aSSalil Mehta } 15796988eb2aSSalil Mehta 15801cc9bc6eSHuazhong Tan static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev) 15811cc9bc6eSHuazhong Tan { 15821cc9bc6eSHuazhong Tan int ret; 15831cc9bc6eSHuazhong Tan 1584c88a6e7dSHuazhong Tan hdev->rst_stats.hw_rst_done_cnt++; 1585fe735c84SHuazhong Tan ret = hclgevf_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 1586fe735c84SHuazhong Tan if (ret) 1587fe735c84SHuazhong Tan return ret; 1588c88a6e7dSHuazhong Tan 158929118ab9SHuazhong Tan rtnl_lock(); 15906988eb2aSSalil Mehta /* now, re-initialize the nic client and ae device */ 15916988eb2aSSalil Mehta ret = hclgevf_reset_stack(hdev); 15921cc9bc6eSHuazhong Tan rtnl_unlock(); 15936a5f6fa3SHuazhong Tan if (ret) { 15946988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 15951cc9bc6eSHuazhong Tan return ret; 15966a5f6fa3SHuazhong Tan } 15976988eb2aSSalil Mehta 1598fe735c84SHuazhong Tan ret = hclgevf_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 1599fe735c84SHuazhong Tan /* ignore RoCE notify error if it fails HCLGEVF_RESET_MAX_FAIL_CNT - 1 1600fe735c84SHuazhong Tan * times 1601fe735c84SHuazhong Tan */ 1602fe735c84SHuazhong Tan if (ret && 1603fe735c84SHuazhong Tan hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT - 1) 1604fe735c84SHuazhong Tan return ret; 1605fe735c84SHuazhong Tan 1606fe735c84SHuazhong Tan ret = hclgevf_notify_roce_client(hdev, HNAE3_UP_CLIENT); 1607fe735c84SHuazhong Tan if (ret) 1608fe735c84SHuazhong Tan return ret; 1609fe735c84SHuazhong Tan 1610b644a8d4SHuazhong Tan hdev->last_reset_time = jiffies; 1611c88a6e7dSHuazhong Tan hdev->rst_stats.rst_done_cnt++; 1612bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt = 0; 1613d5432455SGuojia Liao clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1614b644a8d4SHuazhong Tan 16151cc9bc6eSHuazhong Tan return 0; 16161cc9bc6eSHuazhong Tan } 16171cc9bc6eSHuazhong Tan 16181cc9bc6eSHuazhong Tan static void hclgevf_reset(struct hclgevf_dev *hdev) 16191cc9bc6eSHuazhong Tan { 16201cc9bc6eSHuazhong Tan if (hclgevf_reset_prepare(hdev)) 16211cc9bc6eSHuazhong Tan goto err_reset; 16221cc9bc6eSHuazhong Tan 16231cc9bc6eSHuazhong Tan /* check if VF could successfully fetch the hardware reset completion 16241cc9bc6eSHuazhong Tan * status from the hardware 16251cc9bc6eSHuazhong Tan */ 16261cc9bc6eSHuazhong Tan if (hclgevf_reset_wait(hdev)) { 16271cc9bc6eSHuazhong Tan /* can't do much in this situation, will disable VF */ 16281cc9bc6eSHuazhong Tan dev_err(&hdev->pdev->dev, 16291cc9bc6eSHuazhong Tan "failed to fetch H/W reset completion status\n"); 16301cc9bc6eSHuazhong Tan goto err_reset; 16311cc9bc6eSHuazhong Tan } 16321cc9bc6eSHuazhong Tan 16331cc9bc6eSHuazhong Tan if (hclgevf_reset_rebuild(hdev)) 16341cc9bc6eSHuazhong Tan goto err_reset; 16351cc9bc6eSHuazhong Tan 16361cc9bc6eSHuazhong Tan return; 16371cc9bc6eSHuazhong Tan 16386a5f6fa3SHuazhong Tan err_reset: 1639bbe6540eSHuazhong Tan hclgevf_reset_err_handle(hdev); 16406988eb2aSSalil Mehta } 16416988eb2aSSalil Mehta 1642720bd583SHuazhong Tan static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1643720bd583SHuazhong Tan unsigned long *addr) 1644720bd583SHuazhong Tan { 1645720bd583SHuazhong Tan enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1646720bd583SHuazhong Tan 1647dea846e8SHuazhong Tan /* return the highest priority reset level amongst all */ 1648b90fcc5bSHuazhong Tan if (test_bit(HNAE3_VF_RESET, addr)) { 1649b90fcc5bSHuazhong Tan rst_level = HNAE3_VF_RESET; 1650b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_RESET, addr); 1651b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1652b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1653b90fcc5bSHuazhong Tan } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1654dea846e8SHuazhong Tan rst_level = HNAE3_VF_FULL_RESET; 1655dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FULL_RESET, addr); 1656dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1657aa5c4f17SHuazhong Tan } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1658aa5c4f17SHuazhong Tan rst_level = HNAE3_VF_PF_FUNC_RESET; 1659aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1660aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1661dea846e8SHuazhong Tan } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1662dea846e8SHuazhong Tan rst_level = HNAE3_VF_FUNC_RESET; 1663dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 16646ff3cf07SHuazhong Tan } else if (test_bit(HNAE3_FLR_RESET, addr)) { 16656ff3cf07SHuazhong Tan rst_level = HNAE3_FLR_RESET; 16666ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_RESET, addr); 1667720bd583SHuazhong Tan } 1668720bd583SHuazhong Tan 1669720bd583SHuazhong Tan return rst_level; 1670720bd583SHuazhong Tan } 1671720bd583SHuazhong Tan 16726ae4e733SShiju Jose static void hclgevf_reset_event(struct pci_dev *pdev, 16736ae4e733SShiju Jose struct hnae3_handle *handle) 16746d4c3981SSalil Mehta { 16756ff3cf07SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 16766ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 16776d4c3981SSalil Mehta 16786d4c3981SSalil Mehta dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 16796d4c3981SSalil Mehta 16806ff3cf07SHuazhong Tan if (hdev->default_reset_request) 16810742ed7cSHuazhong Tan hdev->reset_level = 1682720bd583SHuazhong Tan hclgevf_get_reset_level(hdev, 1683720bd583SHuazhong Tan &hdev->default_reset_request); 1684720bd583SHuazhong Tan else 1685dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 16866d4c3981SSalil Mehta 1687436667d2SSalil Mehta /* reset of this VF requested */ 1688436667d2SSalil Mehta set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1689436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 16906d4c3981SSalil Mehta 16910742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 16926d4c3981SSalil Mehta } 16936d4c3981SSalil Mehta 1694720bd583SHuazhong Tan static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1695720bd583SHuazhong Tan enum hnae3_reset_type rst_type) 1696720bd583SHuazhong Tan { 1697720bd583SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1698720bd583SHuazhong Tan 1699720bd583SHuazhong Tan set_bit(rst_type, &hdev->default_reset_request); 1700720bd583SHuazhong Tan } 1701720bd583SHuazhong Tan 1702f28368bbSHuazhong Tan static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1703f28368bbSHuazhong Tan { 1704f28368bbSHuazhong Tan writel(en ? 1 : 0, vector->addr); 1705f28368bbSHuazhong Tan } 1706f28368bbSHuazhong Tan 1707bb1890d5SJiaran Zhang static void hclgevf_reset_prepare_general(struct hnae3_ae_dev *ae_dev, 1708bb1890d5SJiaran Zhang enum hnae3_reset_type rst_type) 17096ff3cf07SHuazhong Tan { 1710bb1890d5SJiaran Zhang #define HCLGEVF_RESET_RETRY_WAIT_MS 500 1711bb1890d5SJiaran Zhang #define HCLGEVF_RESET_RETRY_CNT 5 1712f28368bbSHuazhong Tan 17136ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1714f28368bbSHuazhong Tan int retry_cnt = 0; 1715f28368bbSHuazhong Tan int ret; 17166ff3cf07SHuazhong Tan 1717ed0e658cSJiaran Zhang while (retry_cnt++ < HCLGEVF_RESET_RETRY_CNT) { 1718f28368bbSHuazhong Tan down(&hdev->reset_sem); 1719f28368bbSHuazhong Tan set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1720bb1890d5SJiaran Zhang hdev->reset_type = rst_type; 1721f28368bbSHuazhong Tan ret = hclgevf_reset_prepare(hdev); 1722ed0e658cSJiaran Zhang if (!ret && !hdev->reset_pending) 1723ed0e658cSJiaran Zhang break; 1724ed0e658cSJiaran Zhang 17256ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 1726ed0e658cSJiaran Zhang "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n", 1727ed0e658cSJiaran Zhang ret, hdev->reset_pending, retry_cnt); 1728f28368bbSHuazhong Tan clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1729f28368bbSHuazhong Tan up(&hdev->reset_sem); 1730bb1890d5SJiaran Zhang msleep(HCLGEVF_RESET_RETRY_WAIT_MS); 1731f28368bbSHuazhong Tan } 1732f28368bbSHuazhong Tan 1733bb1890d5SJiaran Zhang /* disable misc vector before reset done */ 1734f28368bbSHuazhong Tan hclgevf_enable_vector(&hdev->misc_vector, false); 1735bb1890d5SJiaran Zhang 1736bb1890d5SJiaran Zhang if (hdev->reset_type == HNAE3_FLR_RESET) 1737f28368bbSHuazhong Tan hdev->rst_stats.flr_rst_cnt++; 1738f28368bbSHuazhong Tan } 1739f28368bbSHuazhong Tan 1740bb1890d5SJiaran Zhang static void hclgevf_reset_done(struct hnae3_ae_dev *ae_dev) 1741f28368bbSHuazhong Tan { 1742f28368bbSHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1743f28368bbSHuazhong Tan int ret; 1744f28368bbSHuazhong Tan 1745f28368bbSHuazhong Tan hclgevf_enable_vector(&hdev->misc_vector, true); 1746f28368bbSHuazhong Tan 1747f28368bbSHuazhong Tan ret = hclgevf_reset_rebuild(hdev); 1748f28368bbSHuazhong Tan if (ret) 1749f28368bbSHuazhong Tan dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", 1750f28368bbSHuazhong Tan ret); 1751f28368bbSHuazhong Tan 1752f28368bbSHuazhong Tan hdev->reset_type = HNAE3_NONE_RESET; 1753f28368bbSHuazhong Tan clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1754f28368bbSHuazhong Tan up(&hdev->reset_sem); 17556ff3cf07SHuazhong Tan } 17566ff3cf07SHuazhong Tan 1757e2cb1decSSalil Mehta static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1758e2cb1decSSalil Mehta { 1759e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1760e2cb1decSSalil Mehta 1761e2cb1decSSalil Mehta return hdev->fw_version; 1762e2cb1decSSalil Mehta } 1763e2cb1decSSalil Mehta 1764e2cb1decSSalil Mehta static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1765e2cb1decSSalil Mehta { 1766e2cb1decSSalil Mehta struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1767e2cb1decSSalil Mehta 1768e2cb1decSSalil Mehta vector->vector_irq = pci_irq_vector(hdev->pdev, 1769e2cb1decSSalil Mehta HCLGEVF_MISC_VECTOR_NUM); 1770076bb537SJie Wang vector->addr = hdev->hw.hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1771e2cb1decSSalil Mehta /* vector status always valid for Vector 0 */ 1772e2cb1decSSalil Mehta hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1773e2cb1decSSalil Mehta hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1774e2cb1decSSalil Mehta 1775e2cb1decSSalil Mehta hdev->num_msi_left -= 1; 1776e2cb1decSSalil Mehta hdev->num_msi_used += 1; 1777e2cb1decSSalil Mehta } 1778e2cb1decSSalil Mehta 177935a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 178035a1e503SSalil Mehta { 1781ff200099SYunsheng Lin if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 17820251d196SGuangbin Huang test_bit(HCLGEVF_STATE_SERVICE_INITED, &hdev->state) && 1783ff200099SYunsheng Lin !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, 1784ff200099SYunsheng Lin &hdev->state)) 17850ea68902SYunsheng Lin mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 178635a1e503SSalil Mehta } 178735a1e503SSalil Mehta 178807a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1789e2cb1decSSalil Mehta { 1790ff200099SYunsheng Lin if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1791ff200099SYunsheng Lin !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, 1792ff200099SYunsheng Lin &hdev->state)) 17930ea68902SYunsheng Lin mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 179407a0556aSSalil Mehta } 1795e2cb1decSSalil Mehta 1796ff200099SYunsheng Lin static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 1797ff200099SYunsheng Lin unsigned long delay) 1798e2cb1decSSalil Mehta { 1799d5432455SGuojia Liao if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1800d5432455SGuojia Liao !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 18010ea68902SYunsheng Lin mod_delayed_work(hclgevf_wq, &hdev->service_task, delay); 1802e2cb1decSSalil Mehta } 1803e2cb1decSSalil Mehta 1804ff200099SYunsheng Lin static void hclgevf_reset_service_task(struct hclgevf_dev *hdev) 180535a1e503SSalil Mehta { 1806d6ad7c53SGuojia Liao #define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3 1807d6ad7c53SGuojia Liao 1808ff200099SYunsheng Lin if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state)) 1809ff200099SYunsheng Lin return; 1810ff200099SYunsheng Lin 1811f28368bbSHuazhong Tan down(&hdev->reset_sem); 1812f28368bbSHuazhong Tan set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 181335a1e503SSalil Mehta 1814436667d2SSalil Mehta if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1815436667d2SSalil Mehta &hdev->reset_state)) { 1816cd7e963dSSalil Mehta /* PF has intimated that it is about to reset the hardware. 18179b2f3477SWeihang Li * We now have to poll & check if hardware has actually 18189b2f3477SWeihang Li * completed the reset sequence. On hardware reset completion, 18199b2f3477SWeihang Li * VF needs to reset the client and ae device. 182035a1e503SSalil Mehta */ 1821436667d2SSalil Mehta hdev->reset_attempts = 0; 1822436667d2SSalil Mehta 1823dea846e8SHuazhong Tan hdev->last_reset_time = jiffies; 18241385cc81SYufeng Mo hdev->reset_type = 18251385cc81SYufeng Mo hclgevf_get_reset_level(hdev, &hdev->reset_pending); 18261385cc81SYufeng Mo if (hdev->reset_type != HNAE3_NONE_RESET) 18271cc9bc6eSHuazhong Tan hclgevf_reset(hdev); 1828436667d2SSalil Mehta } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1829436667d2SSalil Mehta &hdev->reset_state)) { 1830436667d2SSalil Mehta /* we could be here when either of below happens: 18319b2f3477SWeihang Li * 1. reset was initiated due to watchdog timeout caused by 1832436667d2SSalil Mehta * a. IMP was earlier reset and our TX got choked down and 1833436667d2SSalil Mehta * which resulted in watchdog reacting and inducing VF 1834436667d2SSalil Mehta * reset. This also means our cmdq would be unreliable. 1835436667d2SSalil Mehta * b. problem in TX due to other lower layer(example link 1836436667d2SSalil Mehta * layer not functioning properly etc.) 1837436667d2SSalil Mehta * 2. VF reset might have been initiated due to some config 1838436667d2SSalil Mehta * change. 1839436667d2SSalil Mehta * 1840436667d2SSalil Mehta * NOTE: Theres no clear way to detect above cases than to react 1841436667d2SSalil Mehta * to the response of PF for this reset request. PF will ack the 1842436667d2SSalil Mehta * 1b and 2. cases but we will not get any intimation about 1a 1843436667d2SSalil Mehta * from PF as cmdq would be in unreliable state i.e. mailbox 1844436667d2SSalil Mehta * communication between PF and VF would be broken. 184546ee7350SGuojia Liao * 184646ee7350SGuojia Liao * if we are never geting into pending state it means either: 1847436667d2SSalil Mehta * 1. PF is not receiving our request which could be due to IMP 1848436667d2SSalil Mehta * reset 1849436667d2SSalil Mehta * 2. PF is screwed 1850436667d2SSalil Mehta * We cannot do much for 2. but to check first we can try reset 1851436667d2SSalil Mehta * our PCIe + stack and see if it alleviates the problem. 1852436667d2SSalil Mehta */ 1853d6ad7c53SGuojia Liao if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) { 1854436667d2SSalil Mehta /* prepare for full reset of stack + pcie interface */ 1855dea846e8SHuazhong Tan set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1856436667d2SSalil Mehta 1857436667d2SSalil Mehta /* "defer" schedule the reset task again */ 1858436667d2SSalil Mehta set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1859436667d2SSalil Mehta } else { 1860436667d2SSalil Mehta hdev->reset_attempts++; 1861436667d2SSalil Mehta 1862dea846e8SHuazhong Tan set_bit(hdev->reset_level, &hdev->reset_pending); 1863dea846e8SHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1864436667d2SSalil Mehta } 1865dea846e8SHuazhong Tan hclgevf_reset_task_schedule(hdev); 1866436667d2SSalil Mehta } 186735a1e503SSalil Mehta 1868afb6afdbSHuazhong Tan hdev->reset_type = HNAE3_NONE_RESET; 186935a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1870f28368bbSHuazhong Tan up(&hdev->reset_sem); 187135a1e503SSalil Mehta } 187235a1e503SSalil Mehta 1873ff200099SYunsheng Lin static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev) 1874e2cb1decSSalil Mehta { 1875ff200099SYunsheng Lin if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state)) 1876ff200099SYunsheng Lin return; 1877e2cb1decSSalil Mehta 1878e2cb1decSSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1879e2cb1decSSalil Mehta return; 1880e2cb1decSSalil Mehta 188107a0556aSSalil Mehta hclgevf_mbx_async_handler(hdev); 1882e2cb1decSSalil Mehta 1883e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1884e2cb1decSSalil Mehta } 1885e2cb1decSSalil Mehta 1886ff200099SYunsheng Lin static void hclgevf_keep_alive(struct hclgevf_dev *hdev) 1887a6d818e3SYunsheng Lin { 1888d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1889a6d818e3SYunsheng Lin int ret; 1890a6d818e3SYunsheng Lin 1891076bb537SJie Wang if (test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state)) 1892c59a85c0SJian Shen return; 1893c59a85c0SJian Shen 1894d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_KEEP_ALIVE, 0); 1895d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1896a6d818e3SYunsheng Lin if (ret) 1897a6d818e3SYunsheng Lin dev_err(&hdev->pdev->dev, 1898a6d818e3SYunsheng Lin "VF sends keep alive cmd failed(=%d)\n", ret); 1899a6d818e3SYunsheng Lin } 1900a6d818e3SYunsheng Lin 1901ff200099SYunsheng Lin static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev) 1902e2cb1decSSalil Mehta { 1903ff200099SYunsheng Lin unsigned long delta = round_jiffies_relative(HZ); 1904ff200099SYunsheng Lin struct hnae3_handle *handle = &hdev->nic; 1905e2cb1decSSalil Mehta 1906e6394363SGuangbin Huang if (test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 1907e6394363SGuangbin Huang return; 1908e6394363SGuangbin Huang 1909ff200099SYunsheng Lin if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 1910ff200099SYunsheng Lin delta = jiffies - hdev->last_serv_processed; 1911db01afebSliuzhongzhu 1912ff200099SYunsheng Lin if (delta < round_jiffies_relative(HZ)) { 1913ff200099SYunsheng Lin delta = round_jiffies_relative(HZ) - delta; 1914ff200099SYunsheng Lin goto out; 1915db01afebSliuzhongzhu } 1916ff200099SYunsheng Lin } 1917ff200099SYunsheng Lin 1918ff200099SYunsheng Lin hdev->serv_processed_cnt++; 1919ff200099SYunsheng Lin if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL)) 1920ff200099SYunsheng Lin hclgevf_keep_alive(hdev); 1921ff200099SYunsheng Lin 1922ff200099SYunsheng Lin if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) { 1923ff200099SYunsheng Lin hdev->last_serv_processed = jiffies; 1924ff200099SYunsheng Lin goto out; 1925ff200099SYunsheng Lin } 1926ff200099SYunsheng Lin 1927ff200099SYunsheng Lin if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL)) 19284afc310cSJie Wang hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 1929e2cb1decSSalil Mehta 193001305e16SGuangbin Huang /* VF does not need to request link status when this bit is set, because 193101305e16SGuangbin Huang * PF will push its link status to VFs when link status changed. 1932e2cb1decSSalil Mehta */ 193301305e16SGuangbin Huang if (!test_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state)) 1934e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1935e2cb1decSSalil Mehta 19369194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 19379194d18bSliuzhongzhu 1938fe4144d4SJian Shen hclgevf_sync_vlan_filter(hdev); 1939fe4144d4SJian Shen 1940ee4bcd3bSJian Shen hclgevf_sync_mac_table(hdev); 1941ee4bcd3bSJian Shen 1942c631c696SJian Shen hclgevf_sync_promisc_mode(hdev); 1943c631c696SJian Shen 1944ff200099SYunsheng Lin hdev->last_serv_processed = jiffies; 1945436667d2SSalil Mehta 1946ff200099SYunsheng Lin out: 1947ff200099SYunsheng Lin hclgevf_task_schedule(hdev, delta); 1948ff200099SYunsheng Lin } 1949b3c3fe8eSYunsheng Lin 1950ff200099SYunsheng Lin static void hclgevf_service_task(struct work_struct *work) 1951ff200099SYunsheng Lin { 1952ff200099SYunsheng Lin struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev, 1953ff200099SYunsheng Lin service_task.work); 1954ff200099SYunsheng Lin 1955ff200099SYunsheng Lin hclgevf_reset_service_task(hdev); 1956ff200099SYunsheng Lin hclgevf_mailbox_service_task(hdev); 1957ff200099SYunsheng Lin hclgevf_periodic_service_task(hdev); 1958ff200099SYunsheng Lin 1959ff200099SYunsheng Lin /* Handle reset and mbx again in case periodical task delays the 1960ff200099SYunsheng Lin * handling by calling hclgevf_task_schedule() in 1961ff200099SYunsheng Lin * hclgevf_periodic_service_task() 1962ff200099SYunsheng Lin */ 1963ff200099SYunsheng Lin hclgevf_reset_service_task(hdev); 1964ff200099SYunsheng Lin hclgevf_mailbox_service_task(hdev); 1965e2cb1decSSalil Mehta } 1966e2cb1decSSalil Mehta 1967e2cb1decSSalil Mehta static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1968e2cb1decSSalil Mehta { 1969cb413bfaSJie Wang hclgevf_write_dev(&hdev->hw, HCLGE_COMM_VECTOR0_CMDQ_SRC_REG, regclr); 1970e2cb1decSSalil Mehta } 1971e2cb1decSSalil Mehta 1972b90fcc5bSHuazhong Tan static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1973b90fcc5bSHuazhong Tan u32 *clearval) 1974e2cb1decSSalil Mehta { 197513050921SHuazhong Tan u32 val, cmdq_stat_reg, rst_ing_reg; 1976e2cb1decSSalil Mehta 1977e2cb1decSSalil Mehta /* fetch the events from their corresponding regs */ 197813050921SHuazhong Tan cmdq_stat_reg = hclgevf_read_dev(&hdev->hw, 1979cb413bfaSJie Wang HCLGE_COMM_VECTOR0_CMDQ_STATE_REG); 198013050921SHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 1981b90fcc5bSHuazhong Tan rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1982b90fcc5bSHuazhong Tan dev_info(&hdev->pdev->dev, 1983b90fcc5bSHuazhong Tan "receive reset interrupt 0x%x!\n", rst_ing_reg); 1984b90fcc5bSHuazhong Tan set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1985b90fcc5bSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1986076bb537SJie Wang set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 198713050921SHuazhong Tan *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B); 1988c88a6e7dSHuazhong Tan hdev->rst_stats.vf_rst_cnt++; 198972e2fb07SHuazhong Tan /* set up VF hardware reset status, its PF will clear 199072e2fb07SHuazhong Tan * this status when PF has initialized done. 199172e2fb07SHuazhong Tan */ 199272e2fb07SHuazhong Tan val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING); 199372e2fb07SHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING, 199472e2fb07SHuazhong Tan val | HCLGEVF_VF_RST_ING_BIT); 1995b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_RST; 1996b90fcc5bSHuazhong Tan } 1997b90fcc5bSHuazhong Tan 1998e2cb1decSSalil Mehta /* check for vector0 mailbox(=CMDQ RX) event source */ 199913050921SHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 200013050921SHuazhong Tan /* for revision 0x21, clearing interrupt is writing bit 0 200113050921SHuazhong Tan * to the clear register, writing bit 1 means to keep the 200213050921SHuazhong Tan * old value. 200313050921SHuazhong Tan * for revision 0x20, the clear register is a read & write 200413050921SHuazhong Tan * register, so we should just write 0 to the bit we are 200513050921SHuazhong Tan * handling, and keep other bits as cmdq_stat_reg. 200613050921SHuazhong Tan */ 2007295ba232SGuangbin Huang if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) 200813050921SHuazhong Tan *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 200913050921SHuazhong Tan else 201013050921SHuazhong Tan *clearval = cmdq_stat_reg & 201113050921SHuazhong Tan ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 201213050921SHuazhong Tan 2013b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_MBX; 2014e2cb1decSSalil Mehta } 2015e2cb1decSSalil Mehta 2016e45afb39SHuazhong Tan /* print other vector0 event source */ 2017e45afb39SHuazhong Tan dev_info(&hdev->pdev->dev, 2018e45afb39SHuazhong Tan "vector 0 interrupt from unknown source, cmdq_src = %#x\n", 2019e45afb39SHuazhong Tan cmdq_stat_reg); 2020e2cb1decSSalil Mehta 2021b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_OTHER; 2022e2cb1decSSalil Mehta } 2023e2cb1decSSalil Mehta 2024e2cb1decSSalil Mehta static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 2025e2cb1decSSalil Mehta { 2026b90fcc5bSHuazhong Tan enum hclgevf_evt_cause event_cause; 2027e2cb1decSSalil Mehta struct hclgevf_dev *hdev = data; 2028e2cb1decSSalil Mehta u32 clearval; 2029e2cb1decSSalil Mehta 2030e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 2031b90fcc5bSHuazhong Tan event_cause = hclgevf_check_evt_cause(hdev, &clearval); 2032427900d2SJiaran Zhang if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) 2033427900d2SJiaran Zhang hclgevf_clear_event_cause(hdev, clearval); 2034e2cb1decSSalil Mehta 2035b90fcc5bSHuazhong Tan switch (event_cause) { 2036b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_RST: 2037b90fcc5bSHuazhong Tan hclgevf_reset_task_schedule(hdev); 2038b90fcc5bSHuazhong Tan break; 2039b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_MBX: 204007a0556aSSalil Mehta hclgevf_mbx_handler(hdev); 2041b90fcc5bSHuazhong Tan break; 2042b90fcc5bSHuazhong Tan default: 2043b90fcc5bSHuazhong Tan break; 2044b90fcc5bSHuazhong Tan } 2045e2cb1decSSalil Mehta 2046427900d2SJiaran Zhang if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) 2047e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2048e2cb1decSSalil Mehta 2049e2cb1decSSalil Mehta return IRQ_HANDLED; 2050e2cb1decSSalil Mehta } 2051e2cb1decSSalil Mehta 2052e2cb1decSSalil Mehta static int hclgevf_configure(struct hclgevf_dev *hdev) 2053e2cb1decSSalil Mehta { 2054e2cb1decSSalil Mehta int ret; 2055e2cb1decSSalil Mehta 20563462207dSYufeng Mo hdev->gro_en = true; 20573462207dSYufeng Mo 205832e6d104SJian Shen ret = hclgevf_get_basic_info(hdev); 205932e6d104SJian Shen if (ret) 206032e6d104SJian Shen return ret; 206132e6d104SJian Shen 206292f11ea1SJian Shen /* get current port based vlan state from PF */ 206392f11ea1SJian Shen ret = hclgevf_get_port_base_vlan_filter_state(hdev); 206492f11ea1SJian Shen if (ret) 206592f11ea1SJian Shen return ret; 206692f11ea1SJian Shen 2067e2cb1decSSalil Mehta /* get queue configuration from PF */ 20686cee6fc3SJian Shen ret = hclgevf_get_queue_info(hdev); 2069e2cb1decSSalil Mehta if (ret) 2070e2cb1decSSalil Mehta return ret; 2071c0425944SPeng Li 2072c0425944SPeng Li /* get queue depth info from PF */ 2073c0425944SPeng Li ret = hclgevf_get_queue_depth(hdev); 2074c0425944SPeng Li if (ret) 2075c0425944SPeng Li return ret; 2076c0425944SPeng Li 207732e6d104SJian Shen return hclgevf_get_pf_media_type(hdev); 2078e2cb1decSSalil Mehta } 2079e2cb1decSSalil Mehta 20807a01c897SSalil Mehta static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 20817a01c897SSalil Mehta { 20827a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 20831154bb26SPeng Li struct hclgevf_dev *hdev; 20847a01c897SSalil Mehta 20857a01c897SSalil Mehta hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 20867a01c897SSalil Mehta if (!hdev) 20877a01c897SSalil Mehta return -ENOMEM; 20887a01c897SSalil Mehta 20897a01c897SSalil Mehta hdev->pdev = pdev; 20907a01c897SSalil Mehta hdev->ae_dev = ae_dev; 20917a01c897SSalil Mehta ae_dev->priv = hdev; 20927a01c897SSalil Mehta 20937a01c897SSalil Mehta return 0; 20947a01c897SSalil Mehta } 20957a01c897SSalil Mehta 2096e2cb1decSSalil Mehta static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 2097e2cb1decSSalil Mehta { 2098e2cb1decSSalil Mehta struct hnae3_handle *roce = &hdev->roce; 2099e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 2100e2cb1decSSalil Mehta 210107acf909SJian Shen roce->rinfo.num_vectors = hdev->num_roce_msix; 2102e2cb1decSSalil Mehta 2103e2cb1decSSalil Mehta if (hdev->num_msi_left < roce->rinfo.num_vectors || 2104e2cb1decSSalil Mehta hdev->num_msi_left == 0) 2105e2cb1decSSalil Mehta return -EINVAL; 2106e2cb1decSSalil Mehta 2107beb27ca4SJie Wang roce->rinfo.base_vector = hdev->roce_base_msix_offset; 2108e2cb1decSSalil Mehta 2109e2cb1decSSalil Mehta roce->rinfo.netdev = nic->kinfo.netdev; 2110076bb537SJie Wang roce->rinfo.roce_io_base = hdev->hw.hw.io_base; 2111076bb537SJie Wang roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base; 2112e2cb1decSSalil Mehta 2113e2cb1decSSalil Mehta roce->pdev = nic->pdev; 2114e2cb1decSSalil Mehta roce->ae_algo = nic->ae_algo; 2115e2cb1decSSalil Mehta roce->numa_node_mask = nic->numa_node_mask; 2116e2cb1decSSalil Mehta 2117e2cb1decSSalil Mehta return 0; 2118e2cb1decSSalil Mehta } 2119e2cb1decSSalil Mehta 21203462207dSYufeng Mo static int hclgevf_config_gro(struct hclgevf_dev *hdev) 2121b26a6feaSPeng Li { 2122b26a6feaSPeng Li struct hclgevf_cfg_gro_status_cmd *req; 21236befad60SJie Wang struct hclge_desc desc; 2124b26a6feaSPeng Li int ret; 2125b26a6feaSPeng Li 2126b26a6feaSPeng Li if (!hnae3_dev_gro_supported(hdev)) 2127b26a6feaSPeng Li return 0; 2128b26a6feaSPeng Li 2129*43710bfeSJie Wang hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, 2130b26a6feaSPeng Li false); 2131b26a6feaSPeng Li req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2132b26a6feaSPeng Li 21333462207dSYufeng Mo req->gro_en = hdev->gro_en ? 1 : 0; 2134b26a6feaSPeng Li 2135b26a6feaSPeng Li ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2136b26a6feaSPeng Li if (ret) 2137b26a6feaSPeng Li dev_err(&hdev->pdev->dev, 2138b26a6feaSPeng Li "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2139b26a6feaSPeng Li 2140b26a6feaSPeng Li return ret; 2141b26a6feaSPeng Li } 2142b26a6feaSPeng Li 2143944de484SGuojia Liao static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2144944de484SGuojia Liao { 2145027733b1SJie Wang struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 214693969dc1SJie Wang u16 tc_offset[HCLGE_COMM_MAX_TC_NUM]; 214793969dc1SJie Wang u16 tc_valid[HCLGE_COMM_MAX_TC_NUM]; 214893969dc1SJie Wang u16 tc_size[HCLGE_COMM_MAX_TC_NUM]; 2149944de484SGuojia Liao int ret; 2150944de484SGuojia Liao 2151295ba232SGuangbin Huang if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 21527428d6c9SJie Wang ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, 21537428d6c9SJie Wang rss_cfg->rss_algo, 2154944de484SGuojia Liao rss_cfg->rss_hash_key); 2155944de484SGuojia Liao if (ret) 2156944de484SGuojia Liao return ret; 2157944de484SGuojia Liao 21587428d6c9SJie Wang ret = hclge_comm_set_rss_input_tuple(&hdev->nic, &hdev->hw.hw, 21597428d6c9SJie Wang false, rss_cfg); 2160944de484SGuojia Liao if (ret) 2161944de484SGuojia Liao return ret; 2162944de484SGuojia Liao } 2163e2cb1decSSalil Mehta 21647428d6c9SJie Wang ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 21657428d6c9SJie Wang rss_cfg->rss_indirection_tbl); 2166e2cb1decSSalil Mehta if (ret) 2167e2cb1decSSalil Mehta return ret; 2168e2cb1decSSalil Mehta 216993969dc1SJie Wang hclge_comm_get_rss_tc_info(rss_cfg->rss_size, hdev->hw_tc_map, 217093969dc1SJie Wang tc_offset, tc_valid, tc_size); 217193969dc1SJie Wang 217293969dc1SJie Wang return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, 217393969dc1SJie Wang tc_valid, tc_size); 2174e2cb1decSSalil Mehta } 2175e2cb1decSSalil Mehta 2176e2cb1decSSalil Mehta static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2177e2cb1decSSalil Mehta { 2178bbfd4506SJian Shen struct hnae3_handle *nic = &hdev->nic; 2179bbfd4506SJian Shen int ret; 2180bbfd4506SJian Shen 2181bbfd4506SJian Shen ret = hclgevf_en_hw_strip_rxvtag(nic, true); 2182bbfd4506SJian Shen if (ret) { 2183bbfd4506SJian Shen dev_err(&hdev->pdev->dev, 2184bbfd4506SJian Shen "failed to enable rx vlan offload, ret = %d\n", ret); 2185bbfd4506SJian Shen return ret; 2186bbfd4506SJian Shen } 2187bbfd4506SJian Shen 2188e2cb1decSSalil Mehta return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2189e2cb1decSSalil Mehta false); 2190e2cb1decSSalil Mehta } 2191e2cb1decSSalil Mehta 2192ff200099SYunsheng Lin static void hclgevf_flush_link_update(struct hclgevf_dev *hdev) 2193ff200099SYunsheng Lin { 2194ff200099SYunsheng Lin #define HCLGEVF_FLUSH_LINK_TIMEOUT 100000 2195ff200099SYunsheng Lin 2196ff200099SYunsheng Lin unsigned long last = hdev->serv_processed_cnt; 2197ff200099SYunsheng Lin int i = 0; 2198ff200099SYunsheng Lin 2199ff200099SYunsheng Lin while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) && 2200ff200099SYunsheng Lin i++ < HCLGEVF_FLUSH_LINK_TIMEOUT && 2201ff200099SYunsheng Lin last == hdev->serv_processed_cnt) 2202ff200099SYunsheng Lin usleep_range(1, 1); 2203ff200099SYunsheng Lin } 2204ff200099SYunsheng Lin 22058cdb992fSJian Shen static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 22068cdb992fSJian Shen { 22078cdb992fSJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 22088cdb992fSJian Shen 22098cdb992fSJian Shen if (enable) { 2210ff200099SYunsheng Lin hclgevf_task_schedule(hdev, 0); 22118cdb992fSJian Shen } else { 2212b3c3fe8eSYunsheng Lin set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2213ff200099SYunsheng Lin 2214ff200099SYunsheng Lin /* flush memory to make sure DOWN is seen by service task */ 2215ff200099SYunsheng Lin smp_mb__before_atomic(); 2216ff200099SYunsheng Lin hclgevf_flush_link_update(hdev); 22178cdb992fSJian Shen } 22188cdb992fSJian Shen } 22198cdb992fSJian Shen 2220e2cb1decSSalil Mehta static int hclgevf_ae_start(struct hnae3_handle *handle) 2221e2cb1decSSalil Mehta { 2222e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2223e2cb1decSSalil Mehta 2224ed7bedd2SGuangbin Huang clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 222501305e16SGuangbin Huang clear_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state); 2226ed7bedd2SGuangbin Huang 22274afc310cSJie Wang hclge_comm_reset_tqp_stats(handle); 2228e2cb1decSSalil Mehta 2229e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 2230e2cb1decSSalil Mehta 22319194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 22329194d18bSliuzhongzhu 2233e2cb1decSSalil Mehta return 0; 2234e2cb1decSSalil Mehta } 2235e2cb1decSSalil Mehta 2236e2cb1decSSalil Mehta static void hclgevf_ae_stop(struct hnae3_handle *handle) 2237e2cb1decSSalil Mehta { 2238e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2239e2cb1decSSalil Mehta 22402f7e4896SFuyun Liang set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 22412f7e4896SFuyun Liang 2242146e92c1SHuazhong Tan if (hdev->reset_type != HNAE3_VF_RESET) 22438fa86551SYufeng Mo hclgevf_reset_tqp(handle); 224439cfbc9cSHuazhong Tan 22454afc310cSJie Wang hclge_comm_reset_tqp_stats(handle); 22468cc6c1f7SFuyun Liang hclgevf_update_link_status(hdev, 0); 2247e2cb1decSSalil Mehta } 2248e2cb1decSSalil Mehta 2249a6d818e3SYunsheng Lin static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2250a6d818e3SYunsheng Lin { 2251d3410018SYufeng Mo #define HCLGEVF_STATE_ALIVE 1 2252d3410018SYufeng Mo #define HCLGEVF_STATE_NOT_ALIVE 0 2253a6d818e3SYunsheng Lin 2254d3410018SYufeng Mo struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2255d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 2256d3410018SYufeng Mo 2257d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_ALIVE, 0); 2258d3410018SYufeng Mo send_msg.data[0] = alive ? HCLGEVF_STATE_ALIVE : 2259d3410018SYufeng Mo HCLGEVF_STATE_NOT_ALIVE; 2260d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2261a6d818e3SYunsheng Lin } 2262a6d818e3SYunsheng Lin 2263a6d818e3SYunsheng Lin static int hclgevf_client_start(struct hnae3_handle *handle) 2264a6d818e3SYunsheng Lin { 2265f621df96SQinglang Miao return hclgevf_set_alive(handle, true); 2266a6d818e3SYunsheng Lin } 2267a6d818e3SYunsheng Lin 2268a6d818e3SYunsheng Lin static void hclgevf_client_stop(struct hnae3_handle *handle) 2269a6d818e3SYunsheng Lin { 2270a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2271a6d818e3SYunsheng Lin int ret; 2272a6d818e3SYunsheng Lin 2273a6d818e3SYunsheng Lin ret = hclgevf_set_alive(handle, false); 2274a6d818e3SYunsheng Lin if (ret) 2275a6d818e3SYunsheng Lin dev_warn(&hdev->pdev->dev, 2276a6d818e3SYunsheng Lin "%s failed %d\n", __func__, ret); 2277a6d818e3SYunsheng Lin } 2278a6d818e3SYunsheng Lin 2279e2cb1decSSalil Mehta static void hclgevf_state_init(struct hclgevf_dev *hdev) 2280e2cb1decSSalil Mehta { 2281e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2282e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2283d5432455SGuojia Liao clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 2284e2cb1decSSalil Mehta 2285b3c3fe8eSYunsheng Lin INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task); 228635a1e503SSalil Mehta 2287e2cb1decSSalil Mehta mutex_init(&hdev->mbx_resp.mbx_mutex); 2288f28368bbSHuazhong Tan sema_init(&hdev->reset_sem, 1); 2289e2cb1decSSalil Mehta 2290ee4bcd3bSJian Shen spin_lock_init(&hdev->mac_table.mac_list_lock); 2291ee4bcd3bSJian Shen INIT_LIST_HEAD(&hdev->mac_table.uc_mac_list); 2292ee4bcd3bSJian Shen INIT_LIST_HEAD(&hdev->mac_table.mc_mac_list); 2293ee4bcd3bSJian Shen 2294e2cb1decSSalil Mehta /* bring the device down */ 2295e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2296e2cb1decSSalil Mehta } 2297e2cb1decSSalil Mehta 2298e2cb1decSSalil Mehta static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2299e2cb1decSSalil Mehta { 2300e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2301acfc3d55SHuazhong Tan set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2302e2cb1decSSalil Mehta 2303b3c3fe8eSYunsheng Lin if (hdev->service_task.work.func) 2304b3c3fe8eSYunsheng Lin cancel_delayed_work_sync(&hdev->service_task); 2305e2cb1decSSalil Mehta 2306e2cb1decSSalil Mehta mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2307e2cb1decSSalil Mehta } 2308e2cb1decSSalil Mehta 2309e2cb1decSSalil Mehta static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2310e2cb1decSSalil Mehta { 2311e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2312e2cb1decSSalil Mehta int vectors; 2313e2cb1decSSalil Mehta int i; 2314e2cb1decSSalil Mehta 2315580a05f9SYonglong Liu if (hnae3_dev_roce_supported(hdev)) 231607acf909SJian Shen vectors = pci_alloc_irq_vectors(pdev, 231707acf909SJian Shen hdev->roce_base_msix_offset + 1, 231807acf909SJian Shen hdev->num_msi, 231907acf909SJian Shen PCI_IRQ_MSIX); 232007acf909SJian Shen else 2321580a05f9SYonglong Liu vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2322580a05f9SYonglong Liu hdev->num_msi, 2323e2cb1decSSalil Mehta PCI_IRQ_MSI | PCI_IRQ_MSIX); 232407acf909SJian Shen 2325e2cb1decSSalil Mehta if (vectors < 0) { 2326e2cb1decSSalil Mehta dev_err(&pdev->dev, 2327e2cb1decSSalil Mehta "failed(%d) to allocate MSI/MSI-X vectors\n", 2328e2cb1decSSalil Mehta vectors); 2329e2cb1decSSalil Mehta return vectors; 2330e2cb1decSSalil Mehta } 2331e2cb1decSSalil Mehta if (vectors < hdev->num_msi) 2332e2cb1decSSalil Mehta dev_warn(&hdev->pdev->dev, 2333adcf738bSGuojia Liao "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2334e2cb1decSSalil Mehta hdev->num_msi, vectors); 2335e2cb1decSSalil Mehta 2336e2cb1decSSalil Mehta hdev->num_msi = vectors; 2337e2cb1decSSalil Mehta hdev->num_msi_left = vectors; 2338580a05f9SYonglong Liu 2339e2cb1decSSalil Mehta hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2340e2cb1decSSalil Mehta sizeof(u16), GFP_KERNEL); 2341e2cb1decSSalil Mehta if (!hdev->vector_status) { 2342e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2343e2cb1decSSalil Mehta return -ENOMEM; 2344e2cb1decSSalil Mehta } 2345e2cb1decSSalil Mehta 2346e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 2347e2cb1decSSalil Mehta hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2348e2cb1decSSalil Mehta 2349e2cb1decSSalil Mehta hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2350e2cb1decSSalil Mehta sizeof(int), GFP_KERNEL); 2351e2cb1decSSalil Mehta if (!hdev->vector_irq) { 2352862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2353e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2354e2cb1decSSalil Mehta return -ENOMEM; 2355e2cb1decSSalil Mehta } 2356e2cb1decSSalil Mehta 2357e2cb1decSSalil Mehta return 0; 2358e2cb1decSSalil Mehta } 2359e2cb1decSSalil Mehta 2360e2cb1decSSalil Mehta static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2361e2cb1decSSalil Mehta { 2362e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2363e2cb1decSSalil Mehta 2364862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2365862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_irq); 2366e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2367e2cb1decSSalil Mehta } 2368e2cb1decSSalil Mehta 2369e2cb1decSSalil Mehta static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2370e2cb1decSSalil Mehta { 2371cdd332acSGuojia Liao int ret; 2372e2cb1decSSalil Mehta 2373e2cb1decSSalil Mehta hclgevf_get_misc_vector(hdev); 2374e2cb1decSSalil Mehta 2375f97c4d82SYonglong Liu snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 2376f97c4d82SYonglong Liu HCLGEVF_NAME, pci_name(hdev->pdev)); 2377e2cb1decSSalil Mehta ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2378f97c4d82SYonglong Liu 0, hdev->misc_vector.name, hdev); 2379e2cb1decSSalil Mehta if (ret) { 2380e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2381e2cb1decSSalil Mehta hdev->misc_vector.vector_irq); 2382e2cb1decSSalil Mehta return ret; 2383e2cb1decSSalil Mehta } 2384e2cb1decSSalil Mehta 23851819e409SXi Wang hclgevf_clear_event_cause(hdev, 0); 23861819e409SXi Wang 2387e2cb1decSSalil Mehta /* enable misc. vector(vector 0) */ 2388e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2389e2cb1decSSalil Mehta 2390e2cb1decSSalil Mehta return ret; 2391e2cb1decSSalil Mehta } 2392e2cb1decSSalil Mehta 2393e2cb1decSSalil Mehta static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2394e2cb1decSSalil Mehta { 2395e2cb1decSSalil Mehta /* disable misc vector(vector 0) */ 2396e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 23971819e409SXi Wang synchronize_irq(hdev->misc_vector.vector_irq); 2398e2cb1decSSalil Mehta free_irq(hdev->misc_vector.vector_irq, hdev); 2399e2cb1decSSalil Mehta hclgevf_free_vector(hdev, 0); 2400e2cb1decSSalil Mehta } 2401e2cb1decSSalil Mehta 2402bb87be87SYonglong Liu static void hclgevf_info_show(struct hclgevf_dev *hdev) 2403bb87be87SYonglong Liu { 2404bb87be87SYonglong Liu struct device *dev = &hdev->pdev->dev; 2405bb87be87SYonglong Liu 2406bb87be87SYonglong Liu dev_info(dev, "VF info begin:\n"); 2407bb87be87SYonglong Liu 2408adcf738bSGuojia Liao dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 2409adcf738bSGuojia Liao dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 2410adcf738bSGuojia Liao dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 2411adcf738bSGuojia Liao dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 2412adcf738bSGuojia Liao dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 2413adcf738bSGuojia Liao dev_info(dev, "PF media type of this VF: %u\n", 2414bb87be87SYonglong Liu hdev->hw.mac.media_type); 2415bb87be87SYonglong Liu 2416bb87be87SYonglong Liu dev_info(dev, "VF info end.\n"); 2417bb87be87SYonglong Liu } 2418bb87be87SYonglong Liu 24191db58f86SHuazhong Tan static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 24201db58f86SHuazhong Tan struct hnae3_client *client) 24211db58f86SHuazhong Tan { 24221db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 24234cd5beaaSGuangbin Huang int rst_cnt = hdev->rst_stats.rst_cnt; 24241db58f86SHuazhong Tan int ret; 24251db58f86SHuazhong Tan 24261db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->nic); 24271db58f86SHuazhong Tan if (ret) 24281db58f86SHuazhong Tan return ret; 24291db58f86SHuazhong Tan 24301db58f86SHuazhong Tan set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 24314cd5beaaSGuangbin Huang if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 24324cd5beaaSGuangbin Huang rst_cnt != hdev->rst_stats.rst_cnt) { 24334cd5beaaSGuangbin Huang clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 24344cd5beaaSGuangbin Huang 24354cd5beaaSGuangbin Huang client->ops->uninit_instance(&hdev->nic, 0); 24364cd5beaaSGuangbin Huang return -EBUSY; 24374cd5beaaSGuangbin Huang } 24384cd5beaaSGuangbin Huang 24391db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 24401db58f86SHuazhong Tan 24411db58f86SHuazhong Tan if (netif_msg_drv(&hdev->nic)) 24421db58f86SHuazhong Tan hclgevf_info_show(hdev); 24431db58f86SHuazhong Tan 24441db58f86SHuazhong Tan return 0; 24451db58f86SHuazhong Tan } 24461db58f86SHuazhong Tan 24471db58f86SHuazhong Tan static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 24481db58f86SHuazhong Tan struct hnae3_client *client) 24491db58f86SHuazhong Tan { 24501db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 24511db58f86SHuazhong Tan int ret; 24521db58f86SHuazhong Tan 24531db58f86SHuazhong Tan if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 24541db58f86SHuazhong Tan !hdev->nic_client) 24551db58f86SHuazhong Tan return 0; 24561db58f86SHuazhong Tan 24571db58f86SHuazhong Tan ret = hclgevf_init_roce_base_info(hdev); 24581db58f86SHuazhong Tan if (ret) 24591db58f86SHuazhong Tan return ret; 24601db58f86SHuazhong Tan 24611db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->roce); 24621db58f86SHuazhong Tan if (ret) 24631db58f86SHuazhong Tan return ret; 24641db58f86SHuazhong Tan 2465fe735c84SHuazhong Tan set_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 24661db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 24671db58f86SHuazhong Tan 24681db58f86SHuazhong Tan return 0; 24691db58f86SHuazhong Tan } 24701db58f86SHuazhong Tan 2471e718a93fSPeng Li static int hclgevf_init_client_instance(struct hnae3_client *client, 2472e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2473e2cb1decSSalil Mehta { 2474e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2475e2cb1decSSalil Mehta int ret; 2476e2cb1decSSalil Mehta 2477e2cb1decSSalil Mehta switch (client->type) { 2478e2cb1decSSalil Mehta case HNAE3_CLIENT_KNIC: 2479e2cb1decSSalil Mehta hdev->nic_client = client; 2480e2cb1decSSalil Mehta hdev->nic.client = client; 2481e2cb1decSSalil Mehta 24821db58f86SHuazhong Tan ret = hclgevf_init_nic_client_instance(ae_dev, client); 2483e2cb1decSSalil Mehta if (ret) 248449dd8054SJian Shen goto clear_nic; 2485e2cb1decSSalil Mehta 24861db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, 24871db58f86SHuazhong Tan hdev->roce_client); 2488e2cb1decSSalil Mehta if (ret) 248949dd8054SJian Shen goto clear_roce; 2490d9f28fc2SJian Shen 2491e2cb1decSSalil Mehta break; 2492e2cb1decSSalil Mehta case HNAE3_CLIENT_ROCE: 2493544a7bcdSLijun Ou if (hnae3_dev_roce_supported(hdev)) { 2494e2cb1decSSalil Mehta hdev->roce_client = client; 2495e2cb1decSSalil Mehta hdev->roce.client = client; 2496544a7bcdSLijun Ou } 2497e2cb1decSSalil Mehta 24981db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, client); 2499e2cb1decSSalil Mehta if (ret) 250049dd8054SJian Shen goto clear_roce; 2501e2cb1decSSalil Mehta 2502fa7a4bd5SJian Shen break; 2503fa7a4bd5SJian Shen default: 2504fa7a4bd5SJian Shen return -EINVAL; 2505e2cb1decSSalil Mehta } 2506e2cb1decSSalil Mehta 2507e2cb1decSSalil Mehta return 0; 250849dd8054SJian Shen 250949dd8054SJian Shen clear_nic: 251049dd8054SJian Shen hdev->nic_client = NULL; 251149dd8054SJian Shen hdev->nic.client = NULL; 251249dd8054SJian Shen return ret; 251349dd8054SJian Shen clear_roce: 251449dd8054SJian Shen hdev->roce_client = NULL; 251549dd8054SJian Shen hdev->roce.client = NULL; 251649dd8054SJian Shen return ret; 2517e2cb1decSSalil Mehta } 2518e2cb1decSSalil Mehta 2519e718a93fSPeng Li static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2520e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2521e2cb1decSSalil Mehta { 2522e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2523e718a93fSPeng Li 2524e2cb1decSSalil Mehta /* un-init roce, if it exists */ 252549dd8054SJian Shen if (hdev->roce_client) { 2526e140c798SYufeng Mo while (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 2527e140c798SYufeng Mo msleep(HCLGEVF_WAIT_RESET_DONE); 2528fe735c84SHuazhong Tan clear_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 2529e140c798SYufeng Mo 2530e2cb1decSSalil Mehta hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 253149dd8054SJian Shen hdev->roce_client = NULL; 253249dd8054SJian Shen hdev->roce.client = NULL; 253349dd8054SJian Shen } 2534e2cb1decSSalil Mehta 2535e2cb1decSSalil Mehta /* un-init nic/unic, if this was not called by roce client */ 253649dd8054SJian Shen if (client->ops->uninit_instance && hdev->nic_client && 253749dd8054SJian Shen client->type != HNAE3_CLIENT_ROCE) { 2538e140c798SYufeng Mo while (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 2539e140c798SYufeng Mo msleep(HCLGEVF_WAIT_RESET_DONE); 254025d1817cSHuazhong Tan clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 254125d1817cSHuazhong Tan 2542e2cb1decSSalil Mehta client->ops->uninit_instance(&hdev->nic, 0); 254349dd8054SJian Shen hdev->nic_client = NULL; 254449dd8054SJian Shen hdev->nic.client = NULL; 254549dd8054SJian Shen } 2546e2cb1decSSalil Mehta } 2547e2cb1decSSalil Mehta 254830ae7f8aSHuazhong Tan static int hclgevf_dev_mem_map(struct hclgevf_dev *hdev) 254930ae7f8aSHuazhong Tan { 255030ae7f8aSHuazhong Tan #define HCLGEVF_MEM_BAR 4 255130ae7f8aSHuazhong Tan 255230ae7f8aSHuazhong Tan struct pci_dev *pdev = hdev->pdev; 255330ae7f8aSHuazhong Tan struct hclgevf_hw *hw = &hdev->hw; 255430ae7f8aSHuazhong Tan 255530ae7f8aSHuazhong Tan /* for device does not have device memory, return directly */ 255630ae7f8aSHuazhong Tan if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGEVF_MEM_BAR))) 255730ae7f8aSHuazhong Tan return 0; 255830ae7f8aSHuazhong Tan 2559076bb537SJie Wang hw->hw.mem_base = 2560076bb537SJie Wang devm_ioremap_wc(&pdev->dev, 2561076bb537SJie Wang pci_resource_start(pdev, HCLGEVF_MEM_BAR), 256230ae7f8aSHuazhong Tan pci_resource_len(pdev, HCLGEVF_MEM_BAR)); 2563076bb537SJie Wang if (!hw->hw.mem_base) { 2564be419fcaSColin Ian King dev_err(&pdev->dev, "failed to map device memory\n"); 256530ae7f8aSHuazhong Tan return -EFAULT; 256630ae7f8aSHuazhong Tan } 256730ae7f8aSHuazhong Tan 256830ae7f8aSHuazhong Tan return 0; 256930ae7f8aSHuazhong Tan } 257030ae7f8aSHuazhong Tan 2571e2cb1decSSalil Mehta static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2572e2cb1decSSalil Mehta { 2573e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2574e2cb1decSSalil Mehta struct hclgevf_hw *hw; 2575e2cb1decSSalil Mehta int ret; 2576e2cb1decSSalil Mehta 2577e2cb1decSSalil Mehta ret = pci_enable_device(pdev); 2578e2cb1decSSalil Mehta if (ret) { 2579e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed to enable PCI device\n"); 25803e249d3bSFuyun Liang return ret; 2581e2cb1decSSalil Mehta } 2582e2cb1decSSalil Mehta 2583e2cb1decSSalil Mehta ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2584e2cb1decSSalil Mehta if (ret) { 2585e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2586e2cb1decSSalil Mehta goto err_disable_device; 2587e2cb1decSSalil Mehta } 2588e2cb1decSSalil Mehta 2589e2cb1decSSalil Mehta ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2590e2cb1decSSalil Mehta if (ret) { 2591e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2592e2cb1decSSalil Mehta goto err_disable_device; 2593e2cb1decSSalil Mehta } 2594e2cb1decSSalil Mehta 2595e2cb1decSSalil Mehta pci_set_master(pdev); 2596e2cb1decSSalil Mehta hw = &hdev->hw; 2597076bb537SJie Wang hw->hw.io_base = pci_iomap(pdev, 2, 0); 2598076bb537SJie Wang if (!hw->hw.io_base) { 2599e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't map configuration register space\n"); 2600e2cb1decSSalil Mehta ret = -ENOMEM; 2601e2cb1decSSalil Mehta goto err_clr_master; 2602e2cb1decSSalil Mehta } 2603e2cb1decSSalil Mehta 260430ae7f8aSHuazhong Tan ret = hclgevf_dev_mem_map(hdev); 260530ae7f8aSHuazhong Tan if (ret) 260630ae7f8aSHuazhong Tan goto err_unmap_io_base; 260730ae7f8aSHuazhong Tan 2608e2cb1decSSalil Mehta return 0; 2609e2cb1decSSalil Mehta 261030ae7f8aSHuazhong Tan err_unmap_io_base: 2611076bb537SJie Wang pci_iounmap(pdev, hdev->hw.hw.io_base); 2612e2cb1decSSalil Mehta err_clr_master: 2613e2cb1decSSalil Mehta pci_clear_master(pdev); 2614e2cb1decSSalil Mehta pci_release_regions(pdev); 2615e2cb1decSSalil Mehta err_disable_device: 2616e2cb1decSSalil Mehta pci_disable_device(pdev); 26173e249d3bSFuyun Liang 2618e2cb1decSSalil Mehta return ret; 2619e2cb1decSSalil Mehta } 2620e2cb1decSSalil Mehta 2621e2cb1decSSalil Mehta static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2622e2cb1decSSalil Mehta { 2623e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2624e2cb1decSSalil Mehta 2625076bb537SJie Wang if (hdev->hw.hw.mem_base) 2626076bb537SJie Wang devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base); 262730ae7f8aSHuazhong Tan 2628076bb537SJie Wang pci_iounmap(pdev, hdev->hw.hw.io_base); 2629e2cb1decSSalil Mehta pci_clear_master(pdev); 2630e2cb1decSSalil Mehta pci_release_regions(pdev); 2631e2cb1decSSalil Mehta pci_disable_device(pdev); 2632e2cb1decSSalil Mehta } 2633e2cb1decSSalil Mehta 263407acf909SJian Shen static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 263507acf909SJian Shen { 263607acf909SJian Shen struct hclgevf_query_res_cmd *req; 26376befad60SJie Wang struct hclge_desc desc; 263807acf909SJian Shen int ret; 263907acf909SJian Shen 2640*43710bfeSJie Wang hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RSRC, true); 264107acf909SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 264207acf909SJian Shen if (ret) { 264307acf909SJian Shen dev_err(&hdev->pdev->dev, 264407acf909SJian Shen "query vf resource failed, ret = %d.\n", ret); 264507acf909SJian Shen return ret; 264607acf909SJian Shen } 264707acf909SJian Shen 264807acf909SJian Shen req = (struct hclgevf_query_res_cmd *)desc.data; 264907acf909SJian Shen 2650580a05f9SYonglong Liu if (hnae3_dev_roce_supported(hdev)) { 265107acf909SJian Shen hdev->roce_base_msix_offset = 265260df7e91SHuazhong Tan hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee), 265307acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_M, 265407acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_S); 265507acf909SJian Shen hdev->num_roce_msix = 265660df7e91SHuazhong Tan hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 265707acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 265807acf909SJian Shen 2659580a05f9SYonglong Liu /* nic's msix numbers is always equals to the roce's. */ 2660580a05f9SYonglong Liu hdev->num_nic_msix = hdev->num_roce_msix; 2661580a05f9SYonglong Liu 266207acf909SJian Shen /* VF should have NIC vectors and Roce vectors, NIC vectors 266307acf909SJian Shen * are queued before Roce vectors. The offset is fixed to 64. 266407acf909SJian Shen */ 266507acf909SJian Shen hdev->num_msi = hdev->num_roce_msix + 266607acf909SJian Shen hdev->roce_base_msix_offset; 266707acf909SJian Shen } else { 266807acf909SJian Shen hdev->num_msi = 266960df7e91SHuazhong Tan hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 267007acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2671580a05f9SYonglong Liu 2672580a05f9SYonglong Liu hdev->num_nic_msix = hdev->num_msi; 2673580a05f9SYonglong Liu } 2674580a05f9SYonglong Liu 2675580a05f9SYonglong Liu if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) { 2676580a05f9SYonglong Liu dev_err(&hdev->pdev->dev, 2677580a05f9SYonglong Liu "Just %u msi resources, not enough for vf(min:2).\n", 2678580a05f9SYonglong Liu hdev->num_nic_msix); 2679580a05f9SYonglong Liu return -EINVAL; 268007acf909SJian Shen } 268107acf909SJian Shen 268207acf909SJian Shen return 0; 268307acf909SJian Shen } 268407acf909SJian Shen 2685af2aedc5SGuangbin Huang static void hclgevf_set_default_dev_specs(struct hclgevf_dev *hdev) 2686af2aedc5SGuangbin Huang { 2687af2aedc5SGuangbin Huang #define HCLGEVF_MAX_NON_TSO_BD_NUM 8U 2688af2aedc5SGuangbin Huang 2689af2aedc5SGuangbin Huang struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2690af2aedc5SGuangbin Huang 2691af2aedc5SGuangbin Huang ae_dev->dev_specs.max_non_tso_bd_num = 2692af2aedc5SGuangbin Huang HCLGEVF_MAX_NON_TSO_BD_NUM; 2693af2aedc5SGuangbin Huang ae_dev->dev_specs.rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 26947428d6c9SJie Wang ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 2695ab16b49cSHuazhong Tan ae_dev->dev_specs.max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 2696e070c8b9SYufeng Mo ae_dev->dev_specs.max_frm_size = HCLGEVF_MAC_MAX_FRAME; 2697af2aedc5SGuangbin Huang } 2698af2aedc5SGuangbin Huang 2699af2aedc5SGuangbin Huang static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev, 27006befad60SJie Wang struct hclge_desc *desc) 2701af2aedc5SGuangbin Huang { 2702af2aedc5SGuangbin Huang struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2703af2aedc5SGuangbin Huang struct hclgevf_dev_specs_0_cmd *req0; 2704ab16b49cSHuazhong Tan struct hclgevf_dev_specs_1_cmd *req1; 2705af2aedc5SGuangbin Huang 2706af2aedc5SGuangbin Huang req0 = (struct hclgevf_dev_specs_0_cmd *)desc[0].data; 2707ab16b49cSHuazhong Tan req1 = (struct hclgevf_dev_specs_1_cmd *)desc[1].data; 2708af2aedc5SGuangbin Huang 2709af2aedc5SGuangbin Huang ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 2710af2aedc5SGuangbin Huang ae_dev->dev_specs.rss_ind_tbl_size = 2711af2aedc5SGuangbin Huang le16_to_cpu(req0->rss_ind_tbl_size); 271291bfae25SHuazhong Tan ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 2713af2aedc5SGuangbin Huang ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 2714ab16b49cSHuazhong Tan ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 2715e070c8b9SYufeng Mo ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 2716af2aedc5SGuangbin Huang } 2717af2aedc5SGuangbin Huang 271813297028SGuangbin Huang static void hclgevf_check_dev_specs(struct hclgevf_dev *hdev) 271913297028SGuangbin Huang { 272013297028SGuangbin Huang struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 272113297028SGuangbin Huang 272213297028SGuangbin Huang if (!dev_specs->max_non_tso_bd_num) 272313297028SGuangbin Huang dev_specs->max_non_tso_bd_num = HCLGEVF_MAX_NON_TSO_BD_NUM; 272413297028SGuangbin Huang if (!dev_specs->rss_ind_tbl_size) 272513297028SGuangbin Huang dev_specs->rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 272613297028SGuangbin Huang if (!dev_specs->rss_key_size) 27277428d6c9SJie Wang dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 2728ab16b49cSHuazhong Tan if (!dev_specs->max_int_gl) 2729ab16b49cSHuazhong Tan dev_specs->max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 2730e070c8b9SYufeng Mo if (!dev_specs->max_frm_size) 2731e070c8b9SYufeng Mo dev_specs->max_frm_size = HCLGEVF_MAC_MAX_FRAME; 273213297028SGuangbin Huang } 273313297028SGuangbin Huang 2734af2aedc5SGuangbin Huang static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev) 2735af2aedc5SGuangbin Huang { 27366befad60SJie Wang struct hclge_desc desc[HCLGEVF_QUERY_DEV_SPECS_BD_NUM]; 2737af2aedc5SGuangbin Huang int ret; 2738af2aedc5SGuangbin Huang int i; 2739af2aedc5SGuangbin Huang 2740af2aedc5SGuangbin Huang /* set default specifications as devices lower than version V3 do not 2741af2aedc5SGuangbin Huang * support querying specifications from firmware. 2742af2aedc5SGuangbin Huang */ 2743af2aedc5SGuangbin Huang if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 2744af2aedc5SGuangbin Huang hclgevf_set_default_dev_specs(hdev); 2745af2aedc5SGuangbin Huang return 0; 2746af2aedc5SGuangbin Huang } 2747af2aedc5SGuangbin Huang 2748af2aedc5SGuangbin Huang for (i = 0; i < HCLGEVF_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 2749af2aedc5SGuangbin Huang hclgevf_cmd_setup_basic_desc(&desc[i], 2750*43710bfeSJie Wang HCLGE_OPC_QUERY_DEV_SPECS, true); 2751cb413bfaSJie Wang desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2752af2aedc5SGuangbin Huang } 2753*43710bfeSJie Wang hclgevf_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true); 2754af2aedc5SGuangbin Huang 2755af2aedc5SGuangbin Huang ret = hclgevf_cmd_send(&hdev->hw, desc, HCLGEVF_QUERY_DEV_SPECS_BD_NUM); 2756af2aedc5SGuangbin Huang if (ret) 2757af2aedc5SGuangbin Huang return ret; 2758af2aedc5SGuangbin Huang 2759af2aedc5SGuangbin Huang hclgevf_parse_dev_specs(hdev, desc); 276013297028SGuangbin Huang hclgevf_check_dev_specs(hdev); 2761af2aedc5SGuangbin Huang 2762af2aedc5SGuangbin Huang return 0; 2763af2aedc5SGuangbin Huang } 2764af2aedc5SGuangbin Huang 2765862d969aSHuazhong Tan static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2766862d969aSHuazhong Tan { 2767862d969aSHuazhong Tan struct pci_dev *pdev = hdev->pdev; 2768862d969aSHuazhong Tan int ret = 0; 2769862d969aSHuazhong Tan 2770862d969aSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2771862d969aSHuazhong Tan test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2772862d969aSHuazhong Tan hclgevf_misc_irq_uninit(hdev); 2773862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2774862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2775862d969aSHuazhong Tan } 2776862d969aSHuazhong Tan 2777862d969aSHuazhong Tan if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2778862d969aSHuazhong Tan pci_set_master(pdev); 2779862d969aSHuazhong Tan ret = hclgevf_init_msi(hdev); 2780862d969aSHuazhong Tan if (ret) { 2781862d969aSHuazhong Tan dev_err(&pdev->dev, 2782862d969aSHuazhong Tan "failed(%d) to init MSI/MSI-X\n", ret); 2783862d969aSHuazhong Tan return ret; 2784862d969aSHuazhong Tan } 2785862d969aSHuazhong Tan 2786862d969aSHuazhong Tan ret = hclgevf_misc_irq_init(hdev); 2787862d969aSHuazhong Tan if (ret) { 2788862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2789862d969aSHuazhong Tan dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2790862d969aSHuazhong Tan ret); 2791862d969aSHuazhong Tan return ret; 2792862d969aSHuazhong Tan } 2793862d969aSHuazhong Tan 2794862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2795862d969aSHuazhong Tan } 2796862d969aSHuazhong Tan 2797862d969aSHuazhong Tan return ret; 2798862d969aSHuazhong Tan } 2799862d969aSHuazhong Tan 2800039ba863SJian Shen static int hclgevf_clear_vport_list(struct hclgevf_dev *hdev) 2801039ba863SJian Shen { 2802039ba863SJian Shen struct hclge_vf_to_pf_msg send_msg; 2803039ba863SJian Shen 2804039ba863SJian Shen hclgevf_build_send_msg(&send_msg, HCLGE_MBX_HANDLE_VF_TBL, 2805039ba863SJian Shen HCLGE_MBX_VPORT_LIST_CLEAR); 2806039ba863SJian Shen return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2807039ba863SJian Shen } 2808039ba863SJian Shen 280979664077SHuazhong Tan static void hclgevf_init_rxd_adv_layout(struct hclgevf_dev *hdev) 281079664077SHuazhong Tan { 281179664077SHuazhong Tan if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 281279664077SHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 1); 281379664077SHuazhong Tan } 281479664077SHuazhong Tan 281579664077SHuazhong Tan static void hclgevf_uninit_rxd_adv_layout(struct hclgevf_dev *hdev) 281679664077SHuazhong Tan { 281779664077SHuazhong Tan if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 281879664077SHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 0); 281979664077SHuazhong Tan } 282079664077SHuazhong Tan 28219c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2822e2cb1decSSalil Mehta { 28237a01c897SSalil Mehta struct pci_dev *pdev = hdev->pdev; 2824e2cb1decSSalil Mehta int ret; 2825e2cb1decSSalil Mehta 2826862d969aSHuazhong Tan ret = hclgevf_pci_reset(hdev); 2827862d969aSHuazhong Tan if (ret) { 2828862d969aSHuazhong Tan dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2829862d969aSHuazhong Tan return ret; 2830862d969aSHuazhong Tan } 2831862d969aSHuazhong Tan 2832cb413bfaSJie Wang hclgevf_arq_init(hdev); 2833cb413bfaSJie Wang ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, 2834cb413bfaSJie Wang &hdev->fw_version, false, 2835cb413bfaSJie Wang hdev->reset_pending); 28369c6f7085SHuazhong Tan if (ret) { 28379c6f7085SHuazhong Tan dev_err(&pdev->dev, "cmd failed %d\n", ret); 28389c6f7085SHuazhong Tan return ret; 28397a01c897SSalil Mehta } 2840e2cb1decSSalil Mehta 28419c6f7085SHuazhong Tan ret = hclgevf_rss_init_hw(hdev); 28429c6f7085SHuazhong Tan if (ret) { 28439c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 28449c6f7085SHuazhong Tan "failed(%d) to initialize RSS\n", ret); 28459c6f7085SHuazhong Tan return ret; 28469c6f7085SHuazhong Tan } 28479c6f7085SHuazhong Tan 28483462207dSYufeng Mo ret = hclgevf_config_gro(hdev); 2849b26a6feaSPeng Li if (ret) 2850b26a6feaSPeng Li return ret; 2851b26a6feaSPeng Li 28529c6f7085SHuazhong Tan ret = hclgevf_init_vlan_config(hdev); 28539c6f7085SHuazhong Tan if (ret) { 28549c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 28559c6f7085SHuazhong Tan "failed(%d) to initialize VLAN config\n", ret); 28569c6f7085SHuazhong Tan return ret; 28579c6f7085SHuazhong Tan } 28589c6f7085SHuazhong Tan 2859c631c696SJian Shen set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 2860c631c696SJian Shen 286179664077SHuazhong Tan hclgevf_init_rxd_adv_layout(hdev); 286279664077SHuazhong Tan 28639c6f7085SHuazhong Tan dev_info(&hdev->pdev->dev, "Reset done\n"); 28649c6f7085SHuazhong Tan 28659c6f7085SHuazhong Tan return 0; 28669c6f7085SHuazhong Tan } 28679c6f7085SHuazhong Tan 28689c6f7085SHuazhong Tan static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 28699c6f7085SHuazhong Tan { 28709c6f7085SHuazhong Tan struct pci_dev *pdev = hdev->pdev; 28719c6f7085SHuazhong Tan int ret; 28729c6f7085SHuazhong Tan 2873e2cb1decSSalil Mehta ret = hclgevf_pci_init(hdev); 287460df7e91SHuazhong Tan if (ret) 2875e2cb1decSSalil Mehta return ret; 2876e2cb1decSSalil Mehta 2877cd624299SYufeng Mo ret = hclgevf_devlink_init(hdev); 2878cd624299SYufeng Mo if (ret) 2879cd624299SYufeng Mo goto err_devlink_init; 2880cd624299SYufeng Mo 2881cb413bfaSJie Wang ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw); 288260df7e91SHuazhong Tan if (ret) 28838b0195a3SHuazhong Tan goto err_cmd_queue_init; 28848b0195a3SHuazhong Tan 2885cb413bfaSJie Wang hclgevf_arq_init(hdev); 2886cb413bfaSJie Wang ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, 2887cb413bfaSJie Wang &hdev->fw_version, false, 2888cb413bfaSJie Wang hdev->reset_pending); 2889eddf0462SYunsheng Lin if (ret) 2890eddf0462SYunsheng Lin goto err_cmd_init; 2891eddf0462SYunsheng Lin 289207acf909SJian Shen /* Get vf resource */ 289307acf909SJian Shen ret = hclgevf_query_vf_resource(hdev); 289460df7e91SHuazhong Tan if (ret) 28958b0195a3SHuazhong Tan goto err_cmd_init; 289607acf909SJian Shen 2897af2aedc5SGuangbin Huang ret = hclgevf_query_dev_specs(hdev); 2898af2aedc5SGuangbin Huang if (ret) { 2899af2aedc5SGuangbin Huang dev_err(&pdev->dev, 2900af2aedc5SGuangbin Huang "failed to query dev specifications, ret = %d\n", ret); 2901af2aedc5SGuangbin Huang goto err_cmd_init; 2902af2aedc5SGuangbin Huang } 2903af2aedc5SGuangbin Huang 290407acf909SJian Shen ret = hclgevf_init_msi(hdev); 290507acf909SJian Shen if (ret) { 290607acf909SJian Shen dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 29078b0195a3SHuazhong Tan goto err_cmd_init; 290807acf909SJian Shen } 290907acf909SJian Shen 291007acf909SJian Shen hclgevf_state_init(hdev); 2911dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 2912afb6afdbSHuazhong Tan hdev->reset_type = HNAE3_NONE_RESET; 291307acf909SJian Shen 2914e2cb1decSSalil Mehta ret = hclgevf_misc_irq_init(hdev); 291560df7e91SHuazhong Tan if (ret) 2916e2cb1decSSalil Mehta goto err_misc_irq_init; 2917e2cb1decSSalil Mehta 2918862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2919862d969aSHuazhong Tan 2920e2cb1decSSalil Mehta ret = hclgevf_configure(hdev); 2921e2cb1decSSalil Mehta if (ret) { 2922e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2923e2cb1decSSalil Mehta goto err_config; 2924e2cb1decSSalil Mehta } 2925e2cb1decSSalil Mehta 2926e2cb1decSSalil Mehta ret = hclgevf_alloc_tqps(hdev); 2927e2cb1decSSalil Mehta if (ret) { 2928e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2929e2cb1decSSalil Mehta goto err_config; 2930e2cb1decSSalil Mehta } 2931e2cb1decSSalil Mehta 2932e2cb1decSSalil Mehta ret = hclgevf_set_handle_info(hdev); 293360df7e91SHuazhong Tan if (ret) 2934e2cb1decSSalil Mehta goto err_config; 2935e2cb1decSSalil Mehta 29363462207dSYufeng Mo ret = hclgevf_config_gro(hdev); 2937b26a6feaSPeng Li if (ret) 2938b26a6feaSPeng Li goto err_config; 2939b26a6feaSPeng Li 2940e2cb1decSSalil Mehta /* Initialize RSS for this VF */ 294193969dc1SJie Wang ret = hclge_comm_rss_init_cfg(&hdev->nic, hdev->ae_dev, 294293969dc1SJie Wang &hdev->rss_cfg); 294387ce161eSGuangbin Huang if (ret) { 294487ce161eSGuangbin Huang dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 294587ce161eSGuangbin Huang goto err_config; 294687ce161eSGuangbin Huang } 294787ce161eSGuangbin Huang 2948e2cb1decSSalil Mehta ret = hclgevf_rss_init_hw(hdev); 2949e2cb1decSSalil Mehta if (ret) { 2950e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2951e2cb1decSSalil Mehta "failed(%d) to initialize RSS\n", ret); 2952e2cb1decSSalil Mehta goto err_config; 2953e2cb1decSSalil Mehta } 2954e2cb1decSSalil Mehta 2955039ba863SJian Shen /* ensure vf tbl list as empty before init*/ 2956039ba863SJian Shen ret = hclgevf_clear_vport_list(hdev); 2957039ba863SJian Shen if (ret) { 2958039ba863SJian Shen dev_err(&pdev->dev, 2959039ba863SJian Shen "failed to clear tbl list configuration, ret = %d.\n", 2960039ba863SJian Shen ret); 2961039ba863SJian Shen goto err_config; 2962039ba863SJian Shen } 2963039ba863SJian Shen 2964e2cb1decSSalil Mehta ret = hclgevf_init_vlan_config(hdev); 2965e2cb1decSSalil Mehta if (ret) { 2966e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2967e2cb1decSSalil Mehta "failed(%d) to initialize VLAN config\n", ret); 2968e2cb1decSSalil Mehta goto err_config; 2969e2cb1decSSalil Mehta } 2970e2cb1decSSalil Mehta 297179664077SHuazhong Tan hclgevf_init_rxd_adv_layout(hdev); 297279664077SHuazhong Tan 29730251d196SGuangbin Huang set_bit(HCLGEVF_STATE_SERVICE_INITED, &hdev->state); 29740251d196SGuangbin Huang 29750742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 297608d80a4cSHuazhong Tan dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 297708d80a4cSHuazhong Tan HCLGEVF_DRIVER_NAME); 2978e2cb1decSSalil Mehta 2979ff200099SYunsheng Lin hclgevf_task_schedule(hdev, round_jiffies_relative(HZ)); 2980ff200099SYunsheng Lin 2981e2cb1decSSalil Mehta return 0; 2982e2cb1decSSalil Mehta 2983e2cb1decSSalil Mehta err_config: 2984e2cb1decSSalil Mehta hclgevf_misc_irq_uninit(hdev); 2985e2cb1decSSalil Mehta err_misc_irq_init: 2986e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2987e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 298807acf909SJian Shen err_cmd_init: 29899970308fSJie Wang hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 29908b0195a3SHuazhong Tan err_cmd_queue_init: 2991cd624299SYufeng Mo hclgevf_devlink_uninit(hdev); 2992cd624299SYufeng Mo err_devlink_init: 2993e2cb1decSSalil Mehta hclgevf_pci_uninit(hdev); 2994862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2995e2cb1decSSalil Mehta return ret; 2996e2cb1decSSalil Mehta } 2997e2cb1decSSalil Mehta 29987a01c897SSalil Mehta static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2999e2cb1decSSalil Mehta { 3000d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 3001d3410018SYufeng Mo 3002e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 300379664077SHuazhong Tan hclgevf_uninit_rxd_adv_layout(hdev); 3004862d969aSHuazhong Tan 3005d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_VF_UNINIT, 0); 3006d3410018SYufeng Mo hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 300723b4201dSJian Shen 3008862d969aSHuazhong Tan if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3009eddf0462SYunsheng Lin hclgevf_misc_irq_uninit(hdev); 3010e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 30117a01c897SSalil Mehta } 30127a01c897SSalil Mehta 30139970308fSJie Wang hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 3014cd624299SYufeng Mo hclgevf_devlink_uninit(hdev); 3015e3364c5fSZenghui Yu hclgevf_pci_uninit(hdev); 3016ee4bcd3bSJian Shen hclgevf_uninit_mac_list(hdev); 3017862d969aSHuazhong Tan } 3018862d969aSHuazhong Tan 30197a01c897SSalil Mehta static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 30207a01c897SSalil Mehta { 30217a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 30227a01c897SSalil Mehta int ret; 30237a01c897SSalil Mehta 30247a01c897SSalil Mehta ret = hclgevf_alloc_hdev(ae_dev); 30257a01c897SSalil Mehta if (ret) { 30267a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device allocation failed\n"); 30277a01c897SSalil Mehta return ret; 30287a01c897SSalil Mehta } 30297a01c897SSalil Mehta 30307a01c897SSalil Mehta ret = hclgevf_init_hdev(ae_dev->priv); 3031a6d818e3SYunsheng Lin if (ret) { 30327a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device initialization failed\n"); 30337a01c897SSalil Mehta return ret; 30347a01c897SSalil Mehta } 30357a01c897SSalil Mehta 3036a6d818e3SYunsheng Lin return 0; 3037a6d818e3SYunsheng Lin } 3038a6d818e3SYunsheng Lin 30397a01c897SSalil Mehta static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 30407a01c897SSalil Mehta { 30417a01c897SSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 30427a01c897SSalil Mehta 30437a01c897SSalil Mehta hclgevf_uninit_hdev(hdev); 3044e2cb1decSSalil Mehta ae_dev->priv = NULL; 3045e2cb1decSSalil Mehta } 3046e2cb1decSSalil Mehta 3047849e4607SPeng Li static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 3048849e4607SPeng Li { 3049849e4607SPeng Li struct hnae3_handle *nic = &hdev->nic; 3050849e4607SPeng Li struct hnae3_knic_private_info *kinfo = &nic->kinfo; 3051849e4607SPeng Li 30528be73621SHuazhong Tan return min_t(u32, hdev->rss_size_max, 305335244430SJian Shen hdev->num_tqps / kinfo->tc_info.num_tc); 3054849e4607SPeng Li } 3055849e4607SPeng Li 3056849e4607SPeng Li /** 3057849e4607SPeng Li * hclgevf_get_channels - Get the current channels enabled and max supported. 3058849e4607SPeng Li * @handle: hardware information for network interface 3059849e4607SPeng Li * @ch: ethtool channels structure 3060849e4607SPeng Li * 3061849e4607SPeng Li * We don't support separate tx and rx queues as channels. The other count 3062849e4607SPeng Li * represents how many queues are being used for control. max_combined counts 3063849e4607SPeng Li * how many queue pairs we can support. They may not be mapped 1 to 1 with 3064849e4607SPeng Li * q_vectors since we support a lot more queue pairs than q_vectors. 3065849e4607SPeng Li **/ 3066849e4607SPeng Li static void hclgevf_get_channels(struct hnae3_handle *handle, 3067849e4607SPeng Li struct ethtool_channels *ch) 3068849e4607SPeng Li { 3069849e4607SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3070849e4607SPeng Li 3071849e4607SPeng Li ch->max_combined = hclgevf_get_max_channels(hdev); 3072849e4607SPeng Li ch->other_count = 0; 3073849e4607SPeng Li ch->max_other = 0; 30748be73621SHuazhong Tan ch->combined_count = handle->kinfo.rss_size; 3075849e4607SPeng Li } 3076849e4607SPeng Li 3077cc719218SPeng Li static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 30780d43bf45SHuazhong Tan u16 *alloc_tqps, u16 *max_rss_size) 3079cc719218SPeng Li { 3080cc719218SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3081cc719218SPeng Li 30820d43bf45SHuazhong Tan *alloc_tqps = hdev->num_tqps; 3083cc719218SPeng Li *max_rss_size = hdev->rss_size_max; 3084cc719218SPeng Li } 3085cc719218SPeng Li 30864093d1a2SGuangbin Huang static void hclgevf_update_rss_size(struct hnae3_handle *handle, 30874093d1a2SGuangbin Huang u32 new_tqps_num) 30884093d1a2SGuangbin Huang { 30894093d1a2SGuangbin Huang struct hnae3_knic_private_info *kinfo = &handle->kinfo; 30904093d1a2SGuangbin Huang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 30914093d1a2SGuangbin Huang u16 max_rss_size; 30924093d1a2SGuangbin Huang 30934093d1a2SGuangbin Huang kinfo->req_rss_size = new_tqps_num; 30944093d1a2SGuangbin Huang 30954093d1a2SGuangbin Huang max_rss_size = min_t(u16, hdev->rss_size_max, 309635244430SJian Shen hdev->num_tqps / kinfo->tc_info.num_tc); 30974093d1a2SGuangbin Huang 30984093d1a2SGuangbin Huang /* Use the user's configuration when it is not larger than 30994093d1a2SGuangbin Huang * max_rss_size, otherwise, use the maximum specification value. 31004093d1a2SGuangbin Huang */ 31014093d1a2SGuangbin Huang if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 31024093d1a2SGuangbin Huang kinfo->req_rss_size <= max_rss_size) 31034093d1a2SGuangbin Huang kinfo->rss_size = kinfo->req_rss_size; 31044093d1a2SGuangbin Huang else if (kinfo->rss_size > max_rss_size || 31054093d1a2SGuangbin Huang (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) 31064093d1a2SGuangbin Huang kinfo->rss_size = max_rss_size; 31074093d1a2SGuangbin Huang 310835244430SJian Shen kinfo->num_tqps = kinfo->tc_info.num_tc * kinfo->rss_size; 31094093d1a2SGuangbin Huang } 31104093d1a2SGuangbin Huang 31114093d1a2SGuangbin Huang static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 31124093d1a2SGuangbin Huang bool rxfh_configured) 31134093d1a2SGuangbin Huang { 31144093d1a2SGuangbin Huang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 31154093d1a2SGuangbin Huang struct hnae3_knic_private_info *kinfo = &handle->kinfo; 311693969dc1SJie Wang u16 tc_offset[HCLGE_COMM_MAX_TC_NUM]; 311793969dc1SJie Wang u16 tc_valid[HCLGE_COMM_MAX_TC_NUM]; 311893969dc1SJie Wang u16 tc_size[HCLGE_COMM_MAX_TC_NUM]; 31194093d1a2SGuangbin Huang u16 cur_rss_size = kinfo->rss_size; 31204093d1a2SGuangbin Huang u16 cur_tqps = kinfo->num_tqps; 31214093d1a2SGuangbin Huang u32 *rss_indir; 31224093d1a2SGuangbin Huang unsigned int i; 31234093d1a2SGuangbin Huang int ret; 31244093d1a2SGuangbin Huang 31254093d1a2SGuangbin Huang hclgevf_update_rss_size(handle, new_tqps_num); 31264093d1a2SGuangbin Huang 312793969dc1SJie Wang hclge_comm_get_rss_tc_info(cur_rss_size, hdev->hw_tc_map, 312893969dc1SJie Wang tc_offset, tc_valid, tc_size); 312993969dc1SJie Wang ret = hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, 313093969dc1SJie Wang tc_valid, tc_size); 31314093d1a2SGuangbin Huang if (ret) 31324093d1a2SGuangbin Huang return ret; 31334093d1a2SGuangbin Huang 3134cd7e963dSSalil Mehta /* RSS indirection table has been configured by user */ 31354093d1a2SGuangbin Huang if (rxfh_configured) 31364093d1a2SGuangbin Huang goto out; 31374093d1a2SGuangbin Huang 31384093d1a2SGuangbin Huang /* Reinitializes the rss indirect table according to the new RSS size */ 313987ce161eSGuangbin Huang rss_indir = kcalloc(hdev->ae_dev->dev_specs.rss_ind_tbl_size, 314087ce161eSGuangbin Huang sizeof(u32), GFP_KERNEL); 31414093d1a2SGuangbin Huang if (!rss_indir) 31424093d1a2SGuangbin Huang return -ENOMEM; 31434093d1a2SGuangbin Huang 314487ce161eSGuangbin Huang for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 31454093d1a2SGuangbin Huang rss_indir[i] = i % kinfo->rss_size; 31464093d1a2SGuangbin Huang 3147944de484SGuojia Liao hdev->rss_cfg.rss_size = kinfo->rss_size; 3148944de484SGuojia Liao 31494093d1a2SGuangbin Huang ret = hclgevf_set_rss(handle, rss_indir, NULL, 0); 31504093d1a2SGuangbin Huang if (ret) 31514093d1a2SGuangbin Huang dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 31524093d1a2SGuangbin Huang ret); 31534093d1a2SGuangbin Huang 31544093d1a2SGuangbin Huang kfree(rss_indir); 31554093d1a2SGuangbin Huang 31564093d1a2SGuangbin Huang out: 31574093d1a2SGuangbin Huang if (!ret) 31584093d1a2SGuangbin Huang dev_info(&hdev->pdev->dev, 31594093d1a2SGuangbin Huang "Channels changed, rss_size from %u to %u, tqps from %u to %u", 31604093d1a2SGuangbin Huang cur_rss_size, kinfo->rss_size, 316135244430SJian Shen cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 31624093d1a2SGuangbin Huang 31634093d1a2SGuangbin Huang return ret; 31644093d1a2SGuangbin Huang } 31654093d1a2SGuangbin Huang 3166175ec96bSFuyun Liang static int hclgevf_get_status(struct hnae3_handle *handle) 3167175ec96bSFuyun Liang { 3168175ec96bSFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3169175ec96bSFuyun Liang 3170175ec96bSFuyun Liang return hdev->hw.mac.link; 3171175ec96bSFuyun Liang } 3172175ec96bSFuyun Liang 31734a152de9SFuyun Liang static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 31744a152de9SFuyun Liang u8 *auto_neg, u32 *speed, 31754a152de9SFuyun Liang u8 *duplex) 31764a152de9SFuyun Liang { 31774a152de9SFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 31784a152de9SFuyun Liang 31794a152de9SFuyun Liang if (speed) 31804a152de9SFuyun Liang *speed = hdev->hw.mac.speed; 31814a152de9SFuyun Liang if (duplex) 31824a152de9SFuyun Liang *duplex = hdev->hw.mac.duplex; 31834a152de9SFuyun Liang if (auto_neg) 31844a152de9SFuyun Liang *auto_neg = AUTONEG_DISABLE; 31854a152de9SFuyun Liang } 31864a152de9SFuyun Liang 31874a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 31884a152de9SFuyun Liang u8 duplex) 31894a152de9SFuyun Liang { 31904a152de9SFuyun Liang hdev->hw.mac.speed = speed; 31914a152de9SFuyun Liang hdev->hw.mac.duplex = duplex; 31924a152de9SFuyun Liang } 31934a152de9SFuyun Liang 31941731be4cSYonglong Liu static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 31955c9f6b39SPeng Li { 31965c9f6b39SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 31973462207dSYufeng Mo bool gro_en_old = hdev->gro_en; 31983462207dSYufeng Mo int ret; 31995c9f6b39SPeng Li 32003462207dSYufeng Mo hdev->gro_en = enable; 32013462207dSYufeng Mo ret = hclgevf_config_gro(hdev); 32023462207dSYufeng Mo if (ret) 32033462207dSYufeng Mo hdev->gro_en = gro_en_old; 32043462207dSYufeng Mo 32053462207dSYufeng Mo return ret; 32065c9f6b39SPeng Li } 32075c9f6b39SPeng Li 320888d10bd6SJian Shen static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 320988d10bd6SJian Shen u8 *module_type) 3210c136b884SPeng Li { 3211c136b884SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 321288d10bd6SJian Shen 3213c136b884SPeng Li if (media_type) 3214c136b884SPeng Li *media_type = hdev->hw.mac.media_type; 321588d10bd6SJian Shen 321688d10bd6SJian Shen if (module_type) 321788d10bd6SJian Shen *module_type = hdev->hw.mac.module_type; 3218c136b884SPeng Li } 3219c136b884SPeng Li 32204d60291bSHuazhong Tan static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 32214d60291bSHuazhong Tan { 32224d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 32234d60291bSHuazhong Tan 3224aa5c4f17SHuazhong Tan return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 32254d60291bSHuazhong Tan } 32264d60291bSHuazhong Tan 3227fe735c84SHuazhong Tan static bool hclgevf_get_cmdq_stat(struct hnae3_handle *handle) 3228fe735c84SHuazhong Tan { 3229fe735c84SHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3230fe735c84SHuazhong Tan 3231076bb537SJie Wang return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3232fe735c84SHuazhong Tan } 3233fe735c84SHuazhong Tan 32344d60291bSHuazhong Tan static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 32354d60291bSHuazhong Tan { 32364d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 32374d60291bSHuazhong Tan 32384d60291bSHuazhong Tan return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 32394d60291bSHuazhong Tan } 32404d60291bSHuazhong Tan 32414d60291bSHuazhong Tan static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 32424d60291bSHuazhong Tan { 32434d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 32444d60291bSHuazhong Tan 3245c88a6e7dSHuazhong Tan return hdev->rst_stats.hw_rst_done_cnt; 32464d60291bSHuazhong Tan } 32474d60291bSHuazhong Tan 32489194d18bSliuzhongzhu static void hclgevf_get_link_mode(struct hnae3_handle *handle, 32499194d18bSliuzhongzhu unsigned long *supported, 32509194d18bSliuzhongzhu unsigned long *advertising) 32519194d18bSliuzhongzhu { 32529194d18bSliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 32539194d18bSliuzhongzhu 32549194d18bSliuzhongzhu *supported = hdev->hw.mac.supported; 32559194d18bSliuzhongzhu *advertising = hdev->hw.mac.advertising; 32569194d18bSliuzhongzhu } 32579194d18bSliuzhongzhu 32581600c3e5SJian Shen #define MAX_SEPARATE_NUM 4 3259e407efddSHuazhong Tan #define SEPARATOR_VALUE 0xFDFCFBFA 32601600c3e5SJian Shen #define REG_NUM_PER_LINE 4 32611600c3e5SJian Shen #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 32621600c3e5SJian Shen 32631600c3e5SJian Shen static int hclgevf_get_regs_len(struct hnae3_handle *handle) 32641600c3e5SJian Shen { 32651600c3e5SJian Shen int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 32661600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 32671600c3e5SJian Shen 32681600c3e5SJian Shen cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 32691600c3e5SJian Shen common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 32701600c3e5SJian Shen ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 32711600c3e5SJian Shen tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 32721600c3e5SJian Shen 32731600c3e5SJian Shen return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 32741600c3e5SJian Shen tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 32751600c3e5SJian Shen } 32761600c3e5SJian Shen 32771600c3e5SJian Shen static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 32781600c3e5SJian Shen void *data) 32791600c3e5SJian Shen { 32801600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 32811600c3e5SJian Shen int i, j, reg_um, separator_num; 32821600c3e5SJian Shen u32 *reg = data; 32831600c3e5SJian Shen 32841600c3e5SJian Shen *version = hdev->fw_version; 32851600c3e5SJian Shen 32861600c3e5SJian Shen /* fetching per-VF registers values from VF PCIe register space */ 32871600c3e5SJian Shen reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 32881600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 32891600c3e5SJian Shen for (i = 0; i < reg_um; i++) 32901600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 32911600c3e5SJian Shen for (i = 0; i < separator_num; i++) 32921600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 32931600c3e5SJian Shen 32941600c3e5SJian Shen reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 32951600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 32961600c3e5SJian Shen for (i = 0; i < reg_um; i++) 32971600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 32981600c3e5SJian Shen for (i = 0; i < separator_num; i++) 32991600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 33001600c3e5SJian Shen 33011600c3e5SJian Shen reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 33021600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 33031600c3e5SJian Shen for (j = 0; j < hdev->num_tqps; j++) { 33041600c3e5SJian Shen for (i = 0; i < reg_um; i++) 33051600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 33061600c3e5SJian Shen ring_reg_addr_list[i] + 33071600c3e5SJian Shen 0x200 * j); 33081600c3e5SJian Shen for (i = 0; i < separator_num; i++) 33091600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 33101600c3e5SJian Shen } 33111600c3e5SJian Shen 33121600c3e5SJian Shen reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 33131600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 33141600c3e5SJian Shen for (j = 0; j < hdev->num_msi_used - 1; j++) { 33151600c3e5SJian Shen for (i = 0; i < reg_um; i++) 33161600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 33171600c3e5SJian Shen tqp_intr_reg_addr_list[i] + 33181600c3e5SJian Shen 4 * j); 33191600c3e5SJian Shen for (i = 0; i < separator_num; i++) 33201600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 33211600c3e5SJian Shen } 33221600c3e5SJian Shen } 33231600c3e5SJian Shen 332492f11ea1SJian Shen void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 332592f11ea1SJian Shen u8 *port_base_vlan_info, u8 data_size) 332692f11ea1SJian Shen { 332792f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 3328d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 3329a6f7bfdcSJian Shen int ret; 333092f11ea1SJian Shen 333192f11ea1SJian Shen rtnl_lock(); 3332a6f7bfdcSJian Shen 3333b7b5d25bSGuojia Liao if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 3334b7b5d25bSGuojia Liao test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) { 3335a6f7bfdcSJian Shen dev_warn(&hdev->pdev->dev, 3336a6f7bfdcSJian Shen "is resetting when updating port based vlan info\n"); 333792f11ea1SJian Shen rtnl_unlock(); 3338a6f7bfdcSJian Shen return; 3339a6f7bfdcSJian Shen } 3340a6f7bfdcSJian Shen 3341a6f7bfdcSJian Shen ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 3342a6f7bfdcSJian Shen if (ret) { 3343a6f7bfdcSJian Shen rtnl_unlock(); 3344a6f7bfdcSJian Shen return; 3345a6f7bfdcSJian Shen } 334692f11ea1SJian Shen 334792f11ea1SJian Shen /* send msg to PF and wait update port based vlan info */ 3348d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 3349d3410018SYufeng Mo HCLGE_MBX_PORT_BASE_VLAN_CFG); 3350d3410018SYufeng Mo memcpy(send_msg.data, port_base_vlan_info, data_size); 3351a6f7bfdcSJian Shen ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3352a6f7bfdcSJian Shen if (!ret) { 335392f11ea1SJian Shen if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 3354a6f7bfdcSJian Shen nic->port_base_vlan_state = state; 335592f11ea1SJian Shen else 335692f11ea1SJian Shen nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 3357a6f7bfdcSJian Shen } 335892f11ea1SJian Shen 335992f11ea1SJian Shen hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 336092f11ea1SJian Shen rtnl_unlock(); 336192f11ea1SJian Shen } 336292f11ea1SJian Shen 3363e2cb1decSSalil Mehta static const struct hnae3_ae_ops hclgevf_ops = { 3364e2cb1decSSalil Mehta .init_ae_dev = hclgevf_init_ae_dev, 3365e2cb1decSSalil Mehta .uninit_ae_dev = hclgevf_uninit_ae_dev, 3366bb1890d5SJiaran Zhang .reset_prepare = hclgevf_reset_prepare_general, 3367bb1890d5SJiaran Zhang .reset_done = hclgevf_reset_done, 3368e718a93fSPeng Li .init_client_instance = hclgevf_init_client_instance, 3369e718a93fSPeng Li .uninit_client_instance = hclgevf_uninit_client_instance, 3370e2cb1decSSalil Mehta .start = hclgevf_ae_start, 3371e2cb1decSSalil Mehta .stop = hclgevf_ae_stop, 3372a6d818e3SYunsheng Lin .client_start = hclgevf_client_start, 3373a6d818e3SYunsheng Lin .client_stop = hclgevf_client_stop, 3374e2cb1decSSalil Mehta .map_ring_to_vector = hclgevf_map_ring_to_vector, 3375e2cb1decSSalil Mehta .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 3376e2cb1decSSalil Mehta .get_vector = hclgevf_get_vector, 33770d3e6631SYunsheng Lin .put_vector = hclgevf_put_vector, 3378e2cb1decSSalil Mehta .reset_queue = hclgevf_reset_tqp, 3379e2cb1decSSalil Mehta .get_mac_addr = hclgevf_get_mac_addr, 3380e2cb1decSSalil Mehta .set_mac_addr = hclgevf_set_mac_addr, 3381e2cb1decSSalil Mehta .add_uc_addr = hclgevf_add_uc_addr, 3382e2cb1decSSalil Mehta .rm_uc_addr = hclgevf_rm_uc_addr, 3383e2cb1decSSalil Mehta .add_mc_addr = hclgevf_add_mc_addr, 3384e2cb1decSSalil Mehta .rm_mc_addr = hclgevf_rm_mc_addr, 3385e2cb1decSSalil Mehta .get_stats = hclgevf_get_stats, 3386e2cb1decSSalil Mehta .update_stats = hclgevf_update_stats, 3387e2cb1decSSalil Mehta .get_strings = hclgevf_get_strings, 3388e2cb1decSSalil Mehta .get_sset_count = hclgevf_get_sset_count, 3389027733b1SJie Wang .get_rss_key_size = hclge_comm_get_rss_key_size, 3390e2cb1decSSalil Mehta .get_rss = hclgevf_get_rss, 3391e2cb1decSSalil Mehta .set_rss = hclgevf_set_rss, 3392d97b3072SJian Shen .get_rss_tuple = hclgevf_get_rss_tuple, 3393d97b3072SJian Shen .set_rss_tuple = hclgevf_set_rss_tuple, 3394e2cb1decSSalil Mehta .get_tc_size = hclgevf_get_tc_size, 3395e2cb1decSSalil Mehta .get_fw_version = hclgevf_get_fw_version, 3396e2cb1decSSalil Mehta .set_vlan_filter = hclgevf_set_vlan_filter, 3397fa6a262aSJian Shen .enable_vlan_filter = hclgevf_enable_vlan_filter, 3398b2641e2aSYunsheng Lin .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 33996d4c3981SSalil Mehta .reset_event = hclgevf_reset_event, 3400720bd583SHuazhong Tan .set_default_reset_request = hclgevf_set_def_reset_request, 34014093d1a2SGuangbin Huang .set_channels = hclgevf_set_channels, 3402849e4607SPeng Li .get_channels = hclgevf_get_channels, 3403cc719218SPeng Li .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 34041600c3e5SJian Shen .get_regs_len = hclgevf_get_regs_len, 34051600c3e5SJian Shen .get_regs = hclgevf_get_regs, 3406175ec96bSFuyun Liang .get_status = hclgevf_get_status, 34074a152de9SFuyun Liang .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3408c136b884SPeng Li .get_media_type = hclgevf_get_media_type, 34094d60291bSHuazhong Tan .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 34104d60291bSHuazhong Tan .ae_dev_resetting = hclgevf_ae_dev_resetting, 34114d60291bSHuazhong Tan .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 34125c9f6b39SPeng Li .set_gro_en = hclgevf_gro_en, 3413818f1675SYunsheng Lin .set_mtu = hclgevf_set_mtu, 34140c29d191Sliuzhongzhu .get_global_queue_id = hclgevf_get_qid_global, 34158cdb992fSJian Shen .set_timer_task = hclgevf_set_timer_task, 34169194d18bSliuzhongzhu .get_link_mode = hclgevf_get_link_mode, 3417e196ec75SJian Shen .set_promisc_mode = hclgevf_set_promisc_mode, 3418c631c696SJian Shen .request_update_promisc_mode = hclgevf_request_update_promisc_mode, 3419fe735c84SHuazhong Tan .get_cmdq_stat = hclgevf_get_cmdq_stat, 3420e2cb1decSSalil Mehta }; 3421e2cb1decSSalil Mehta 3422e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf = { 3423e2cb1decSSalil Mehta .ops = &hclgevf_ops, 3424e2cb1decSSalil Mehta .pdev_id_table = ae_algovf_pci_tbl, 3425e2cb1decSSalil Mehta }; 3426e2cb1decSSalil Mehta 3427e2cb1decSSalil Mehta static int hclgevf_init(void) 3428e2cb1decSSalil Mehta { 3429e2cb1decSSalil Mehta pr_info("%s is initializing\n", HCLGEVF_NAME); 3430e2cb1decSSalil Mehta 3431f29da408SYufeng Mo hclgevf_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGEVF_NAME); 34320ea68902SYunsheng Lin if (!hclgevf_wq) { 34330ea68902SYunsheng Lin pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME); 34340ea68902SYunsheng Lin return -ENOMEM; 34350ea68902SYunsheng Lin } 34360ea68902SYunsheng Lin 3437854cf33aSFuyun Liang hnae3_register_ae_algo(&ae_algovf); 3438854cf33aSFuyun Liang 3439854cf33aSFuyun Liang return 0; 3440e2cb1decSSalil Mehta } 3441e2cb1decSSalil Mehta 3442e2cb1decSSalil Mehta static void hclgevf_exit(void) 3443e2cb1decSSalil Mehta { 3444e2cb1decSSalil Mehta hnae3_unregister_ae_algo(&ae_algovf); 34450ea68902SYunsheng Lin destroy_workqueue(hclgevf_wq); 3446e2cb1decSSalil Mehta } 3447e2cb1decSSalil Mehta module_init(hclgevf_init); 3448e2cb1decSSalil Mehta module_exit(hclgevf_exit); 3449e2cb1decSSalil Mehta 3450e2cb1decSSalil Mehta MODULE_LICENSE("GPL"); 3451e2cb1decSSalil Mehta MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3452e2cb1decSSalil Mehta MODULE_DESCRIPTION("HCLGEVF Driver"); 3453e2cb1decSSalil Mehta MODULE_VERSION(HCLGEVF_MOD_VERSION); 3454