1e2cb1decSSalil Mehta // SPDX-License-Identifier: GPL-2.0+ 2e2cb1decSSalil Mehta // Copyright (c) 2016-2017 Hisilicon Limited. 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #include <linux/etherdevice.h> 5aa5c4f17SHuazhong Tan #include <linux/iopoll.h> 66988eb2aSSalil Mehta #include <net/rtnetlink.h> 7e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 8e2cb1decSSalil Mehta #include "hclgevf_main.h" 9e2cb1decSSalil Mehta #include "hclge_mbx.h" 10e2cb1decSSalil Mehta #include "hnae3.h" 11e2cb1decSSalil Mehta 12e2cb1decSSalil Mehta #define HCLGEVF_NAME "hclgevf" 13e2cb1decSSalil Mehta 14bbe6540eSHuazhong Tan #define HCLGEVF_RESET_MAX_FAIL_CNT 5 15bbe6540eSHuazhong Tan 169c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 17e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf; 18e2cb1decSSalil Mehta 190ea68902SYunsheng Lin static struct workqueue_struct *hclgevf_wq; 200ea68902SYunsheng Lin 21e2cb1decSSalil Mehta static const struct pci_device_id ae_algovf_pci_tbl[] = { 22e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 23e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 24e2cb1decSSalil Mehta /* required last entry */ 25e2cb1decSSalil Mehta {0, } 26e2cb1decSSalil Mehta }; 27e2cb1decSSalil Mehta 28472d7eceSJian Shen static const u8 hclgevf_hash_key[] = { 29472d7eceSJian Shen 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 30472d7eceSJian Shen 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 31472d7eceSJian Shen 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 32472d7eceSJian Shen 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 33472d7eceSJian Shen 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 34472d7eceSJian Shen }; 35472d7eceSJian Shen 362f550a46SYunsheng Lin MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 372f550a46SYunsheng Lin 381600c3e5SJian Shen static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 391600c3e5SJian Shen HCLGEVF_CMDQ_TX_ADDR_H_REG, 401600c3e5SJian Shen HCLGEVF_CMDQ_TX_DEPTH_REG, 411600c3e5SJian Shen HCLGEVF_CMDQ_TX_TAIL_REG, 421600c3e5SJian Shen HCLGEVF_CMDQ_TX_HEAD_REG, 431600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_L_REG, 441600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_H_REG, 451600c3e5SJian Shen HCLGEVF_CMDQ_RX_DEPTH_REG, 461600c3e5SJian Shen HCLGEVF_CMDQ_RX_TAIL_REG, 471600c3e5SJian Shen HCLGEVF_CMDQ_RX_HEAD_REG, 481600c3e5SJian Shen HCLGEVF_VECTOR0_CMDQ_SRC_REG, 491600c3e5SJian Shen HCLGEVF_CMDQ_INTR_STS_REG, 501600c3e5SJian Shen HCLGEVF_CMDQ_INTR_EN_REG, 511600c3e5SJian Shen HCLGEVF_CMDQ_INTR_GEN_REG}; 521600c3e5SJian Shen 531600c3e5SJian Shen static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 541600c3e5SJian Shen HCLGEVF_RST_ING, 551600c3e5SJian Shen HCLGEVF_GRO_EN_REG}; 561600c3e5SJian Shen 571600c3e5SJian Shen static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 581600c3e5SJian Shen HCLGEVF_RING_RX_ADDR_H_REG, 591600c3e5SJian Shen HCLGEVF_RING_RX_BD_NUM_REG, 601600c3e5SJian Shen HCLGEVF_RING_RX_BD_LENGTH_REG, 611600c3e5SJian Shen HCLGEVF_RING_RX_MERGE_EN_REG, 621600c3e5SJian Shen HCLGEVF_RING_RX_TAIL_REG, 631600c3e5SJian Shen HCLGEVF_RING_RX_HEAD_REG, 641600c3e5SJian Shen HCLGEVF_RING_RX_FBD_NUM_REG, 651600c3e5SJian Shen HCLGEVF_RING_RX_OFFSET_REG, 661600c3e5SJian Shen HCLGEVF_RING_RX_FBD_OFFSET_REG, 671600c3e5SJian Shen HCLGEVF_RING_RX_STASH_REG, 681600c3e5SJian Shen HCLGEVF_RING_RX_BD_ERR_REG, 691600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_L_REG, 701600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_H_REG, 711600c3e5SJian Shen HCLGEVF_RING_TX_BD_NUM_REG, 721600c3e5SJian Shen HCLGEVF_RING_TX_PRIORITY_REG, 731600c3e5SJian Shen HCLGEVF_RING_TX_TC_REG, 741600c3e5SJian Shen HCLGEVF_RING_TX_MERGE_EN_REG, 751600c3e5SJian Shen HCLGEVF_RING_TX_TAIL_REG, 761600c3e5SJian Shen HCLGEVF_RING_TX_HEAD_REG, 771600c3e5SJian Shen HCLGEVF_RING_TX_FBD_NUM_REG, 781600c3e5SJian Shen HCLGEVF_RING_TX_OFFSET_REG, 791600c3e5SJian Shen HCLGEVF_RING_TX_EBD_NUM_REG, 801600c3e5SJian Shen HCLGEVF_RING_TX_EBD_OFFSET_REG, 811600c3e5SJian Shen HCLGEVF_RING_TX_BD_ERR_REG, 821600c3e5SJian Shen HCLGEVF_RING_EN_REG}; 831600c3e5SJian Shen 841600c3e5SJian Shen static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 851600c3e5SJian Shen HCLGEVF_TQP_INTR_GL0_REG, 861600c3e5SJian Shen HCLGEVF_TQP_INTR_GL1_REG, 871600c3e5SJian Shen HCLGEVF_TQP_INTR_GL2_REG, 881600c3e5SJian Shen HCLGEVF_TQP_INTR_RL_REG}; 891600c3e5SJian Shen 909b2f3477SWeihang Li static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 91e2cb1decSSalil Mehta { 92eed9535fSPeng Li if (!handle->client) 93eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, nic); 94eed9535fSPeng Li else if (handle->client->type == HNAE3_CLIENT_ROCE) 95eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, roce); 96eed9535fSPeng Li else 97e2cb1decSSalil Mehta return container_of(handle, struct hclgevf_dev, nic); 98e2cb1decSSalil Mehta } 99e2cb1decSSalil Mehta 100e2cb1decSSalil Mehta static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 101e2cb1decSSalil Mehta { 102b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 103e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 104e2cb1decSSalil Mehta struct hclgevf_desc desc; 105e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 106e2cb1decSSalil Mehta int status; 107e2cb1decSSalil Mehta int i; 108e2cb1decSSalil Mehta 109b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 110b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 111e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 112e2cb1decSSalil Mehta HCLGEVF_OPC_QUERY_RX_STATUS, 113e2cb1decSSalil Mehta true); 114e2cb1decSSalil Mehta 115e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 116e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 117e2cb1decSSalil Mehta if (status) { 118e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 119e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 120e2cb1decSSalil Mehta status, i); 121e2cb1decSSalil Mehta return status; 122e2cb1decSSalil Mehta } 123e2cb1decSSalil Mehta tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 124cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 125e2cb1decSSalil Mehta 126e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 127e2cb1decSSalil Mehta true); 128e2cb1decSSalil Mehta 129e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 130e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 131e2cb1decSSalil Mehta if (status) { 132e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 133e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 134e2cb1decSSalil Mehta status, i); 135e2cb1decSSalil Mehta return status; 136e2cb1decSSalil Mehta } 137e2cb1decSSalil Mehta tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 138cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 139e2cb1decSSalil Mehta } 140e2cb1decSSalil Mehta 141e2cb1decSSalil Mehta return 0; 142e2cb1decSSalil Mehta } 143e2cb1decSSalil Mehta 144e2cb1decSSalil Mehta static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 145e2cb1decSSalil Mehta { 146e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo = &handle->kinfo; 147e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 148e2cb1decSSalil Mehta u64 *buff = data; 149e2cb1decSSalil Mehta int i; 150e2cb1decSSalil Mehta 151b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 152b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 153e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 154e2cb1decSSalil Mehta } 155e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 156b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 157e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 158e2cb1decSSalil Mehta } 159e2cb1decSSalil Mehta 160e2cb1decSSalil Mehta return buff; 161e2cb1decSSalil Mehta } 162e2cb1decSSalil Mehta 163e2cb1decSSalil Mehta static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 164e2cb1decSSalil Mehta { 165b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 166e2cb1decSSalil Mehta 167b4f1d303SJian Shen return kinfo->num_tqps * 2; 168e2cb1decSSalil Mehta } 169e2cb1decSSalil Mehta 170e2cb1decSSalil Mehta static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 171e2cb1decSSalil Mehta { 172b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 173e2cb1decSSalil Mehta u8 *buff = data; 174e2cb1decSSalil Mehta int i = 0; 175e2cb1decSSalil Mehta 176b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 177b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 178e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1790c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 180e2cb1decSSalil Mehta tqp->index); 181e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 182e2cb1decSSalil Mehta } 183e2cb1decSSalil Mehta 184b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 185b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 186e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1870c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 188e2cb1decSSalil Mehta tqp->index); 189e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 190e2cb1decSSalil Mehta } 191e2cb1decSSalil Mehta 192e2cb1decSSalil Mehta return buff; 193e2cb1decSSalil Mehta } 194e2cb1decSSalil Mehta 195e2cb1decSSalil Mehta static void hclgevf_update_stats(struct hnae3_handle *handle, 196e2cb1decSSalil Mehta struct net_device_stats *net_stats) 197e2cb1decSSalil Mehta { 198e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 199e2cb1decSSalil Mehta int status; 200e2cb1decSSalil Mehta 201e2cb1decSSalil Mehta status = hclgevf_tqps_update_stats(handle); 202e2cb1decSSalil Mehta if (status) 203e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 204e2cb1decSSalil Mehta "VF update of TQPS stats fail, status = %d.\n", 205e2cb1decSSalil Mehta status); 206e2cb1decSSalil Mehta } 207e2cb1decSSalil Mehta 208e2cb1decSSalil Mehta static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 209e2cb1decSSalil Mehta { 210e2cb1decSSalil Mehta if (strset == ETH_SS_TEST) 211e2cb1decSSalil Mehta return -EOPNOTSUPP; 212e2cb1decSSalil Mehta else if (strset == ETH_SS_STATS) 213e2cb1decSSalil Mehta return hclgevf_tqps_get_sset_count(handle, strset); 214e2cb1decSSalil Mehta 215e2cb1decSSalil Mehta return 0; 216e2cb1decSSalil Mehta } 217e2cb1decSSalil Mehta 218e2cb1decSSalil Mehta static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 219e2cb1decSSalil Mehta u8 *data) 220e2cb1decSSalil Mehta { 221e2cb1decSSalil Mehta u8 *p = (char *)data; 222e2cb1decSSalil Mehta 223e2cb1decSSalil Mehta if (strset == ETH_SS_STATS) 224e2cb1decSSalil Mehta p = hclgevf_tqps_get_strings(handle, p); 225e2cb1decSSalil Mehta } 226e2cb1decSSalil Mehta 227e2cb1decSSalil Mehta static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 228e2cb1decSSalil Mehta { 229e2cb1decSSalil Mehta hclgevf_tqps_get_stats(handle, data); 230e2cb1decSSalil Mehta } 231e2cb1decSSalil Mehta 232e2cb1decSSalil Mehta static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 233e2cb1decSSalil Mehta { 234e2cb1decSSalil Mehta u8 resp_msg; 235e2cb1decSSalil Mehta int status; 236e2cb1decSSalil Mehta 237e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 23863cbf7a9SYufeng Mo true, &resp_msg, sizeof(resp_msg)); 239e2cb1decSSalil Mehta if (status) { 240e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 241e2cb1decSSalil Mehta "VF request to get TC info from PF failed %d", 242e2cb1decSSalil Mehta status); 243e2cb1decSSalil Mehta return status; 244e2cb1decSSalil Mehta } 245e2cb1decSSalil Mehta 246e2cb1decSSalil Mehta hdev->hw_tc_map = resp_msg; 247e2cb1decSSalil Mehta 248e2cb1decSSalil Mehta return 0; 249e2cb1decSSalil Mehta } 250e2cb1decSSalil Mehta 25192f11ea1SJian Shen static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 25292f11ea1SJian Shen { 25392f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 25492f11ea1SJian Shen u8 resp_msg; 25592f11ea1SJian Shen int ret; 25692f11ea1SJian Shen 25792f11ea1SJian Shen ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 25892f11ea1SJian Shen HCLGE_MBX_GET_PORT_BASE_VLAN_STATE, 25992f11ea1SJian Shen NULL, 0, true, &resp_msg, sizeof(u8)); 26092f11ea1SJian Shen if (ret) { 26192f11ea1SJian Shen dev_err(&hdev->pdev->dev, 26292f11ea1SJian Shen "VF request to get port based vlan state failed %d", 26392f11ea1SJian Shen ret); 26492f11ea1SJian Shen return ret; 26592f11ea1SJian Shen } 26692f11ea1SJian Shen 26792f11ea1SJian Shen nic->port_base_vlan_state = resp_msg; 26892f11ea1SJian Shen 26992f11ea1SJian Shen return 0; 27092f11ea1SJian Shen } 27192f11ea1SJian Shen 2726cee6fc3SJian Shen static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 273e2cb1decSSalil Mehta { 274c0425944SPeng Li #define HCLGEVF_TQPS_RSS_INFO_LEN 6 275e2cb1decSSalil Mehta u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 276e2cb1decSSalil Mehta int status; 277e2cb1decSSalil Mehta 278e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 279e2cb1decSSalil Mehta true, resp_msg, 280e2cb1decSSalil Mehta HCLGEVF_TQPS_RSS_INFO_LEN); 281e2cb1decSSalil Mehta if (status) { 282e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 283e2cb1decSSalil Mehta "VF request to get tqp info from PF failed %d", 284e2cb1decSSalil Mehta status); 285e2cb1decSSalil Mehta return status; 286e2cb1decSSalil Mehta } 287e2cb1decSSalil Mehta 288e2cb1decSSalil Mehta memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 289e2cb1decSSalil Mehta memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 290c0425944SPeng Li memcpy(&hdev->rx_buf_len, &resp_msg[4], sizeof(u16)); 291c0425944SPeng Li 292c0425944SPeng Li return 0; 293c0425944SPeng Li } 294c0425944SPeng Li 295c0425944SPeng Li static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 296c0425944SPeng Li { 297c0425944SPeng Li #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 298c0425944SPeng Li u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 299c0425944SPeng Li int ret; 300c0425944SPeng Li 301c0425944SPeng Li ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QDEPTH, 0, NULL, 0, 302c0425944SPeng Li true, resp_msg, 303c0425944SPeng Li HCLGEVF_TQPS_DEPTH_INFO_LEN); 304c0425944SPeng Li if (ret) { 305c0425944SPeng Li dev_err(&hdev->pdev->dev, 306c0425944SPeng Li "VF request to get tqp depth info from PF failed %d", 307c0425944SPeng Li ret); 308c0425944SPeng Li return ret; 309c0425944SPeng Li } 310c0425944SPeng Li 311c0425944SPeng Li memcpy(&hdev->num_tx_desc, &resp_msg[0], sizeof(u16)); 312c0425944SPeng Li memcpy(&hdev->num_rx_desc, &resp_msg[2], sizeof(u16)); 313e2cb1decSSalil Mehta 314e2cb1decSSalil Mehta return 0; 315e2cb1decSSalil Mehta } 316e2cb1decSSalil Mehta 3170c29d191Sliuzhongzhu static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 3180c29d191Sliuzhongzhu { 3190c29d191Sliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3200c29d191Sliuzhongzhu u8 msg_data[2], resp_data[2]; 3210c29d191Sliuzhongzhu u16 qid_in_pf = 0; 3220c29d191Sliuzhongzhu int ret; 3230c29d191Sliuzhongzhu 3240c29d191Sliuzhongzhu memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 3250c29d191Sliuzhongzhu 3260c29d191Sliuzhongzhu ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data, 32763cbf7a9SYufeng Mo sizeof(msg_data), true, resp_data, 32863cbf7a9SYufeng Mo sizeof(resp_data)); 3290c29d191Sliuzhongzhu if (!ret) 3300c29d191Sliuzhongzhu qid_in_pf = *(u16 *)resp_data; 3310c29d191Sliuzhongzhu 3320c29d191Sliuzhongzhu return qid_in_pf; 3330c29d191Sliuzhongzhu } 3340c29d191Sliuzhongzhu 3359c3e7130Sliuzhongzhu static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 3369c3e7130Sliuzhongzhu { 33788d10bd6SJian Shen u8 resp_msg[2]; 3389c3e7130Sliuzhongzhu int ret; 3399c3e7130Sliuzhongzhu 3409c3e7130Sliuzhongzhu ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_MEDIA_TYPE, 0, NULL, 0, 34188d10bd6SJian Shen true, resp_msg, sizeof(resp_msg)); 3429c3e7130Sliuzhongzhu if (ret) { 3439c3e7130Sliuzhongzhu dev_err(&hdev->pdev->dev, 3449c3e7130Sliuzhongzhu "VF request to get the pf port media type failed %d", 3459c3e7130Sliuzhongzhu ret); 3469c3e7130Sliuzhongzhu return ret; 3479c3e7130Sliuzhongzhu } 3489c3e7130Sliuzhongzhu 34988d10bd6SJian Shen hdev->hw.mac.media_type = resp_msg[0]; 35088d10bd6SJian Shen hdev->hw.mac.module_type = resp_msg[1]; 3519c3e7130Sliuzhongzhu 3529c3e7130Sliuzhongzhu return 0; 3539c3e7130Sliuzhongzhu } 3549c3e7130Sliuzhongzhu 355e2cb1decSSalil Mehta static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 356e2cb1decSSalil Mehta { 357e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 358e2cb1decSSalil Mehta int i; 359e2cb1decSSalil Mehta 360e2cb1decSSalil Mehta hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 361e2cb1decSSalil Mehta sizeof(struct hclgevf_tqp), GFP_KERNEL); 362e2cb1decSSalil Mehta if (!hdev->htqp) 363e2cb1decSSalil Mehta return -ENOMEM; 364e2cb1decSSalil Mehta 365e2cb1decSSalil Mehta tqp = hdev->htqp; 366e2cb1decSSalil Mehta 367e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 368e2cb1decSSalil Mehta tqp->dev = &hdev->pdev->dev; 369e2cb1decSSalil Mehta tqp->index = i; 370e2cb1decSSalil Mehta 371e2cb1decSSalil Mehta tqp->q.ae_algo = &ae_algovf; 372e2cb1decSSalil Mehta tqp->q.buf_size = hdev->rx_buf_len; 373c0425944SPeng Li tqp->q.tx_desc_num = hdev->num_tx_desc; 374c0425944SPeng Li tqp->q.rx_desc_num = hdev->num_rx_desc; 375e2cb1decSSalil Mehta tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 376e2cb1decSSalil Mehta i * HCLGEVF_TQP_REG_SIZE; 377e2cb1decSSalil Mehta 378e2cb1decSSalil Mehta tqp++; 379e2cb1decSSalil Mehta } 380e2cb1decSSalil Mehta 381e2cb1decSSalil Mehta return 0; 382e2cb1decSSalil Mehta } 383e2cb1decSSalil Mehta 384e2cb1decSSalil Mehta static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 385e2cb1decSSalil Mehta { 386e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 387e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo; 388e2cb1decSSalil Mehta u16 new_tqps = hdev->num_tqps; 389ebaf1908SWeihang Li unsigned int i; 390e2cb1decSSalil Mehta 391e2cb1decSSalil Mehta kinfo = &nic->kinfo; 392e2cb1decSSalil Mehta kinfo->num_tc = 0; 393c0425944SPeng Li kinfo->num_tx_desc = hdev->num_tx_desc; 394c0425944SPeng Li kinfo->num_rx_desc = hdev->num_rx_desc; 395e2cb1decSSalil Mehta kinfo->rx_buf_len = hdev->rx_buf_len; 396e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 397e2cb1decSSalil Mehta if (hdev->hw_tc_map & BIT(i)) 398e2cb1decSSalil Mehta kinfo->num_tc++; 399e2cb1decSSalil Mehta 400e2cb1decSSalil Mehta kinfo->rss_size 401e2cb1decSSalil Mehta = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 402e2cb1decSSalil Mehta new_tqps = kinfo->rss_size * kinfo->num_tc; 403e2cb1decSSalil Mehta kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 404e2cb1decSSalil Mehta 405e2cb1decSSalil Mehta kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 406e2cb1decSSalil Mehta sizeof(struct hnae3_queue *), GFP_KERNEL); 407e2cb1decSSalil Mehta if (!kinfo->tqp) 408e2cb1decSSalil Mehta return -ENOMEM; 409e2cb1decSSalil Mehta 410e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 411e2cb1decSSalil Mehta hdev->htqp[i].q.handle = &hdev->nic; 412e2cb1decSSalil Mehta hdev->htqp[i].q.tqp_index = i; 413e2cb1decSSalil Mehta kinfo->tqp[i] = &hdev->htqp[i].q; 414e2cb1decSSalil Mehta } 415e2cb1decSSalil Mehta 416580a05f9SYonglong Liu /* after init the max rss_size and tqps, adjust the default tqp numbers 417580a05f9SYonglong Liu * and rss size with the actual vector numbers 418580a05f9SYonglong Liu */ 419580a05f9SYonglong Liu kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps); 420580a05f9SYonglong Liu kinfo->rss_size = min_t(u16, kinfo->num_tqps / kinfo->num_tc, 421580a05f9SYonglong Liu kinfo->rss_size); 422580a05f9SYonglong Liu 423e2cb1decSSalil Mehta return 0; 424e2cb1decSSalil Mehta } 425e2cb1decSSalil Mehta 426e2cb1decSSalil Mehta static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 427e2cb1decSSalil Mehta { 428e2cb1decSSalil Mehta int status; 429e2cb1decSSalil Mehta u8 resp_msg; 430e2cb1decSSalil Mehta 431e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 43263cbf7a9SYufeng Mo 0, false, &resp_msg, sizeof(resp_msg)); 433e2cb1decSSalil Mehta if (status) 434e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 435e2cb1decSSalil Mehta "VF failed to fetch link status(%d) from PF", status); 436e2cb1decSSalil Mehta } 437e2cb1decSSalil Mehta 438e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 439e2cb1decSSalil Mehta { 44045e92b7eSPeng Li struct hnae3_handle *rhandle = &hdev->roce; 441e2cb1decSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 44245e92b7eSPeng Li struct hnae3_client *rclient; 443e2cb1decSSalil Mehta struct hnae3_client *client; 444e2cb1decSSalil Mehta 445ff200099SYunsheng Lin if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state)) 446ff200099SYunsheng Lin return; 447ff200099SYunsheng Lin 448e2cb1decSSalil Mehta client = handle->client; 44945e92b7eSPeng Li rclient = hdev->roce_client; 450e2cb1decSSalil Mehta 451582d37bbSPeng Li link_state = 452582d37bbSPeng Li test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 453582d37bbSPeng Li 454e2cb1decSSalil Mehta if (link_state != hdev->hw.mac.link) { 455e2cb1decSSalil Mehta client->ops->link_status_change(handle, !!link_state); 45645e92b7eSPeng Li if (rclient && rclient->ops->link_status_change) 45745e92b7eSPeng Li rclient->ops->link_status_change(rhandle, !!link_state); 458e2cb1decSSalil Mehta hdev->hw.mac.link = link_state; 459e2cb1decSSalil Mehta } 460ff200099SYunsheng Lin 461ff200099SYunsheng Lin clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state); 462e2cb1decSSalil Mehta } 463e2cb1decSSalil Mehta 464538abaf3SYueHaibing static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 4659194d18bSliuzhongzhu { 4669194d18bSliuzhongzhu #define HCLGEVF_ADVERTISING 0 4679194d18bSliuzhongzhu #define HCLGEVF_SUPPORTED 1 4689194d18bSliuzhongzhu u8 send_msg; 4699194d18bSliuzhongzhu u8 resp_msg; 4709194d18bSliuzhongzhu 4719194d18bSliuzhongzhu send_msg = HCLGEVF_ADVERTISING; 47263cbf7a9SYufeng Mo hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 47363cbf7a9SYufeng Mo &send_msg, sizeof(send_msg), false, 47463cbf7a9SYufeng Mo &resp_msg, sizeof(resp_msg)); 4759194d18bSliuzhongzhu send_msg = HCLGEVF_SUPPORTED; 47663cbf7a9SYufeng Mo hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 47763cbf7a9SYufeng Mo &send_msg, sizeof(send_msg), false, 47863cbf7a9SYufeng Mo &resp_msg, sizeof(resp_msg)); 4799194d18bSliuzhongzhu } 4809194d18bSliuzhongzhu 481e2cb1decSSalil Mehta static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 482e2cb1decSSalil Mehta { 483e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 484e2cb1decSSalil Mehta int ret; 485e2cb1decSSalil Mehta 486e2cb1decSSalil Mehta nic->ae_algo = &ae_algovf; 487e2cb1decSSalil Mehta nic->pdev = hdev->pdev; 488e2cb1decSSalil Mehta nic->numa_node_mask = hdev->numa_node_mask; 489424eb834SSalil Mehta nic->flags |= HNAE3_SUPPORT_VF; 490e2cb1decSSalil Mehta 491e2cb1decSSalil Mehta ret = hclgevf_knic_setup(hdev); 492e2cb1decSSalil Mehta if (ret) 493e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 494e2cb1decSSalil Mehta ret); 495e2cb1decSSalil Mehta return ret; 496e2cb1decSSalil Mehta } 497e2cb1decSSalil Mehta 498e2cb1decSSalil Mehta static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 499e2cb1decSSalil Mehta { 50036cbbdf6SPeng Li if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 50136cbbdf6SPeng Li dev_warn(&hdev->pdev->dev, 50236cbbdf6SPeng Li "vector(vector_id %d) has been freed.\n", vector_id); 50336cbbdf6SPeng Li return; 50436cbbdf6SPeng Li } 50536cbbdf6SPeng Li 506e2cb1decSSalil Mehta hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 507e2cb1decSSalil Mehta hdev->num_msi_left += 1; 508e2cb1decSSalil Mehta hdev->num_msi_used -= 1; 509e2cb1decSSalil Mehta } 510e2cb1decSSalil Mehta 511e2cb1decSSalil Mehta static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 512e2cb1decSSalil Mehta struct hnae3_vector_info *vector_info) 513e2cb1decSSalil Mehta { 514e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 515e2cb1decSSalil Mehta struct hnae3_vector_info *vector = vector_info; 516e2cb1decSSalil Mehta int alloc = 0; 517e2cb1decSSalil Mehta int i, j; 518e2cb1decSSalil Mehta 519580a05f9SYonglong Liu vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num); 520e2cb1decSSalil Mehta vector_num = min(hdev->num_msi_left, vector_num); 521e2cb1decSSalil Mehta 522e2cb1decSSalil Mehta for (j = 0; j < vector_num; j++) { 523e2cb1decSSalil Mehta for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 524e2cb1decSSalil Mehta if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 525e2cb1decSSalil Mehta vector->vector = pci_irq_vector(hdev->pdev, i); 526e2cb1decSSalil Mehta vector->io_addr = hdev->hw.io_base + 527e2cb1decSSalil Mehta HCLGEVF_VECTOR_REG_BASE + 528e2cb1decSSalil Mehta (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 529e2cb1decSSalil Mehta hdev->vector_status[i] = 0; 530e2cb1decSSalil Mehta hdev->vector_irq[i] = vector->vector; 531e2cb1decSSalil Mehta 532e2cb1decSSalil Mehta vector++; 533e2cb1decSSalil Mehta alloc++; 534e2cb1decSSalil Mehta 535e2cb1decSSalil Mehta break; 536e2cb1decSSalil Mehta } 537e2cb1decSSalil Mehta } 538e2cb1decSSalil Mehta } 539e2cb1decSSalil Mehta hdev->num_msi_left -= alloc; 540e2cb1decSSalil Mehta hdev->num_msi_used += alloc; 541e2cb1decSSalil Mehta 542e2cb1decSSalil Mehta return alloc; 543e2cb1decSSalil Mehta } 544e2cb1decSSalil Mehta 545e2cb1decSSalil Mehta static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 546e2cb1decSSalil Mehta { 547e2cb1decSSalil Mehta int i; 548e2cb1decSSalil Mehta 549e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 550e2cb1decSSalil Mehta if (vector == hdev->vector_irq[i]) 551e2cb1decSSalil Mehta return i; 552e2cb1decSSalil Mehta 553e2cb1decSSalil Mehta return -EINVAL; 554e2cb1decSSalil Mehta } 555e2cb1decSSalil Mehta 556374ad291SJian Shen static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 557374ad291SJian Shen const u8 hfunc, const u8 *key) 558374ad291SJian Shen { 559374ad291SJian Shen struct hclgevf_rss_config_cmd *req; 560ebaf1908SWeihang Li unsigned int key_offset = 0; 561374ad291SJian Shen struct hclgevf_desc desc; 5623caf772bSYufeng Mo int key_counts; 563374ad291SJian Shen int key_size; 564374ad291SJian Shen int ret; 565374ad291SJian Shen 5663caf772bSYufeng Mo key_counts = HCLGEVF_RSS_KEY_SIZE; 567374ad291SJian Shen req = (struct hclgevf_rss_config_cmd *)desc.data; 568374ad291SJian Shen 5693caf772bSYufeng Mo while (key_counts) { 570374ad291SJian Shen hclgevf_cmd_setup_basic_desc(&desc, 571374ad291SJian Shen HCLGEVF_OPC_RSS_GENERIC_CONFIG, 572374ad291SJian Shen false); 573374ad291SJian Shen 574374ad291SJian Shen req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 575374ad291SJian Shen req->hash_config |= 576374ad291SJian Shen (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 577374ad291SJian Shen 5783caf772bSYufeng Mo key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts); 579374ad291SJian Shen memcpy(req->hash_key, 580374ad291SJian Shen key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 581374ad291SJian Shen 5823caf772bSYufeng Mo key_counts -= key_size; 5833caf772bSYufeng Mo key_offset++; 584374ad291SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 585374ad291SJian Shen if (ret) { 586374ad291SJian Shen dev_err(&hdev->pdev->dev, 587374ad291SJian Shen "Configure RSS config fail, status = %d\n", 588374ad291SJian Shen ret); 589374ad291SJian Shen return ret; 590374ad291SJian Shen } 591374ad291SJian Shen } 592374ad291SJian Shen 593374ad291SJian Shen return 0; 594374ad291SJian Shen } 595374ad291SJian Shen 596e2cb1decSSalil Mehta static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 597e2cb1decSSalil Mehta { 598e2cb1decSSalil Mehta return HCLGEVF_RSS_KEY_SIZE; 599e2cb1decSSalil Mehta } 600e2cb1decSSalil Mehta 601e2cb1decSSalil Mehta static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 602e2cb1decSSalil Mehta { 603e2cb1decSSalil Mehta return HCLGEVF_RSS_IND_TBL_SIZE; 604e2cb1decSSalil Mehta } 605e2cb1decSSalil Mehta 606e2cb1decSSalil Mehta static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 607e2cb1decSSalil Mehta { 608e2cb1decSSalil Mehta const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 609e2cb1decSSalil Mehta struct hclgevf_rss_indirection_table_cmd *req; 610e2cb1decSSalil Mehta struct hclgevf_desc desc; 611e2cb1decSSalil Mehta int status; 612e2cb1decSSalil Mehta int i, j; 613e2cb1decSSalil Mehta 614e2cb1decSSalil Mehta req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 615e2cb1decSSalil Mehta 616e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 617e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 618e2cb1decSSalil Mehta false); 619e2cb1decSSalil Mehta req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 620e2cb1decSSalil Mehta req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 621e2cb1decSSalil Mehta for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 622e2cb1decSSalil Mehta req->rss_result[j] = 623e2cb1decSSalil Mehta indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 624e2cb1decSSalil Mehta 625e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 626e2cb1decSSalil Mehta if (status) { 627e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 628e2cb1decSSalil Mehta "VF failed(=%d) to set RSS indirection table\n", 629e2cb1decSSalil Mehta status); 630e2cb1decSSalil Mehta return status; 631e2cb1decSSalil Mehta } 632e2cb1decSSalil Mehta } 633e2cb1decSSalil Mehta 634e2cb1decSSalil Mehta return 0; 635e2cb1decSSalil Mehta } 636e2cb1decSSalil Mehta 637e2cb1decSSalil Mehta static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 638e2cb1decSSalil Mehta { 639e2cb1decSSalil Mehta struct hclgevf_rss_tc_mode_cmd *req; 640e2cb1decSSalil Mehta u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 641e2cb1decSSalil Mehta u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 642e2cb1decSSalil Mehta u16 tc_size[HCLGEVF_MAX_TC_NUM]; 643e2cb1decSSalil Mehta struct hclgevf_desc desc; 644e2cb1decSSalil Mehta u16 roundup_size; 645e2cb1decSSalil Mehta int status; 646ebaf1908SWeihang Li unsigned int i; 647e2cb1decSSalil Mehta 648e2cb1decSSalil Mehta req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 649e2cb1decSSalil Mehta 650e2cb1decSSalil Mehta roundup_size = roundup_pow_of_two(rss_size); 651e2cb1decSSalil Mehta roundup_size = ilog2(roundup_size); 652e2cb1decSSalil Mehta 653e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 654e2cb1decSSalil Mehta tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 655e2cb1decSSalil Mehta tc_size[i] = roundup_size; 656e2cb1decSSalil Mehta tc_offset[i] = rss_size * i; 657e2cb1decSSalil Mehta } 658e2cb1decSSalil Mehta 659e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 660e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 661e4e87715SPeng Li hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 662e2cb1decSSalil Mehta (tc_valid[i] & 0x1)); 663e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 664e2cb1decSSalil Mehta HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 665e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 666e2cb1decSSalil Mehta HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 667e2cb1decSSalil Mehta } 668e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 669e2cb1decSSalil Mehta if (status) 670e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 671e2cb1decSSalil Mehta "VF failed(=%d) to set rss tc mode\n", status); 672e2cb1decSSalil Mehta 673e2cb1decSSalil Mehta return status; 674e2cb1decSSalil Mehta } 675e2cb1decSSalil Mehta 676a638b1d8SJian Shen /* for revision 0x20, vf shared the same rss config with pf */ 677a638b1d8SJian Shen static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 678a638b1d8SJian Shen { 679a638b1d8SJian Shen #define HCLGEVF_RSS_MBX_RESP_LEN 8 680a638b1d8SJian Shen 681a638b1d8SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 682a638b1d8SJian Shen u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 683a638b1d8SJian Shen u16 msg_num, hash_key_index; 684a638b1d8SJian Shen u8 index; 685a638b1d8SJian Shen int ret; 686a638b1d8SJian Shen 687a638b1d8SJian Shen msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 688a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN; 689a638b1d8SJian Shen for (index = 0; index < msg_num; index++) { 690a638b1d8SJian Shen ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_RSS_KEY, 0, 691a638b1d8SJian Shen &index, sizeof(index), 692a638b1d8SJian Shen true, resp_msg, 693a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN); 694a638b1d8SJian Shen if (ret) { 695a638b1d8SJian Shen dev_err(&hdev->pdev->dev, 696a638b1d8SJian Shen "VF get rss hash key from PF failed, ret=%d", 697a638b1d8SJian Shen ret); 698a638b1d8SJian Shen return ret; 699a638b1d8SJian Shen } 700a638b1d8SJian Shen 701a638b1d8SJian Shen hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 702a638b1d8SJian Shen if (index == msg_num - 1) 703a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 704a638b1d8SJian Shen &resp_msg[0], 705a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE - hash_key_index); 706a638b1d8SJian Shen else 707a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 708a638b1d8SJian Shen &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 709a638b1d8SJian Shen } 710a638b1d8SJian Shen 711a638b1d8SJian Shen return 0; 712a638b1d8SJian Shen } 713a638b1d8SJian Shen 714e2cb1decSSalil Mehta static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 715e2cb1decSSalil Mehta u8 *hfunc) 716e2cb1decSSalil Mehta { 717e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 718e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 719a638b1d8SJian Shen int i, ret; 720e2cb1decSSalil Mehta 721374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 722374ad291SJian Shen /* Get hash algorithm */ 723374ad291SJian Shen if (hfunc) { 724374ad291SJian Shen switch (rss_cfg->hash_algo) { 725374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 726374ad291SJian Shen *hfunc = ETH_RSS_HASH_TOP; 727374ad291SJian Shen break; 728374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 729374ad291SJian Shen *hfunc = ETH_RSS_HASH_XOR; 730374ad291SJian Shen break; 731374ad291SJian Shen default: 732374ad291SJian Shen *hfunc = ETH_RSS_HASH_UNKNOWN; 733374ad291SJian Shen break; 734374ad291SJian Shen } 735374ad291SJian Shen } 736374ad291SJian Shen 737374ad291SJian Shen /* Get the RSS Key required by the user */ 738374ad291SJian Shen if (key) 739374ad291SJian Shen memcpy(key, rss_cfg->rss_hash_key, 740374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 741a638b1d8SJian Shen } else { 742a638b1d8SJian Shen if (hfunc) 743a638b1d8SJian Shen *hfunc = ETH_RSS_HASH_TOP; 744a638b1d8SJian Shen if (key) { 745a638b1d8SJian Shen ret = hclgevf_get_rss_hash_key(hdev); 746a638b1d8SJian Shen if (ret) 747a638b1d8SJian Shen return ret; 748a638b1d8SJian Shen memcpy(key, rss_cfg->rss_hash_key, 749a638b1d8SJian Shen HCLGEVF_RSS_KEY_SIZE); 750a638b1d8SJian Shen } 751374ad291SJian Shen } 752374ad291SJian Shen 753e2cb1decSSalil Mehta if (indir) 754e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 755e2cb1decSSalil Mehta indir[i] = rss_cfg->rss_indirection_tbl[i]; 756e2cb1decSSalil Mehta 757374ad291SJian Shen return 0; 758e2cb1decSSalil Mehta } 759e2cb1decSSalil Mehta 760e2cb1decSSalil Mehta static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 761e2cb1decSSalil Mehta const u8 *key, const u8 hfunc) 762e2cb1decSSalil Mehta { 763e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 764e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 765374ad291SJian Shen int ret, i; 766374ad291SJian Shen 767374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 768374ad291SJian Shen /* Set the RSS Hash Key if specififed by the user */ 769374ad291SJian Shen if (key) { 770374ad291SJian Shen switch (hfunc) { 771374ad291SJian Shen case ETH_RSS_HASH_TOP: 772374ad291SJian Shen rss_cfg->hash_algo = 773374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 774374ad291SJian Shen break; 775374ad291SJian Shen case ETH_RSS_HASH_XOR: 776374ad291SJian Shen rss_cfg->hash_algo = 777374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_SIMPLE; 778374ad291SJian Shen break; 779374ad291SJian Shen case ETH_RSS_HASH_NO_CHANGE: 780374ad291SJian Shen break; 781374ad291SJian Shen default: 782374ad291SJian Shen return -EINVAL; 783374ad291SJian Shen } 784374ad291SJian Shen 785374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 786374ad291SJian Shen key); 787374ad291SJian Shen if (ret) 788374ad291SJian Shen return ret; 789374ad291SJian Shen 790374ad291SJian Shen /* Update the shadow RSS key with user specified qids */ 791374ad291SJian Shen memcpy(rss_cfg->rss_hash_key, key, 792374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 793374ad291SJian Shen } 794374ad291SJian Shen } 795e2cb1decSSalil Mehta 796e2cb1decSSalil Mehta /* update the shadow RSS table with user specified qids */ 797e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 798e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = indir[i]; 799e2cb1decSSalil Mehta 800e2cb1decSSalil Mehta /* update the hardware */ 801e2cb1decSSalil Mehta return hclgevf_set_rss_indir_table(hdev); 802e2cb1decSSalil Mehta } 803e2cb1decSSalil Mehta 804d97b3072SJian Shen static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 805d97b3072SJian Shen { 806d97b3072SJian Shen u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 807d97b3072SJian Shen 808d97b3072SJian Shen if (nfc->data & RXH_L4_B_2_3) 809d97b3072SJian Shen hash_sets |= HCLGEVF_D_PORT_BIT; 810d97b3072SJian Shen else 811d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_PORT_BIT; 812d97b3072SJian Shen 813d97b3072SJian Shen if (nfc->data & RXH_IP_SRC) 814d97b3072SJian Shen hash_sets |= HCLGEVF_S_IP_BIT; 815d97b3072SJian Shen else 816d97b3072SJian Shen hash_sets &= ~HCLGEVF_S_IP_BIT; 817d97b3072SJian Shen 818d97b3072SJian Shen if (nfc->data & RXH_IP_DST) 819d97b3072SJian Shen hash_sets |= HCLGEVF_D_IP_BIT; 820d97b3072SJian Shen else 821d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_IP_BIT; 822d97b3072SJian Shen 823d97b3072SJian Shen if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 824d97b3072SJian Shen hash_sets |= HCLGEVF_V_TAG_BIT; 825d97b3072SJian Shen 826d97b3072SJian Shen return hash_sets; 827d97b3072SJian Shen } 828d97b3072SJian Shen 829d97b3072SJian Shen static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 830d97b3072SJian Shen struct ethtool_rxnfc *nfc) 831d97b3072SJian Shen { 832d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 833d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 834d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 835d97b3072SJian Shen struct hclgevf_desc desc; 836d97b3072SJian Shen u8 tuple_sets; 837d97b3072SJian Shen int ret; 838d97b3072SJian Shen 839d97b3072SJian Shen if (handle->pdev->revision == 0x20) 840d97b3072SJian Shen return -EOPNOTSUPP; 841d97b3072SJian Shen 842d97b3072SJian Shen if (nfc->data & 843d97b3072SJian Shen ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 844d97b3072SJian Shen return -EINVAL; 845d97b3072SJian Shen 846d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 847d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 848d97b3072SJian Shen 849d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 850d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 851d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 852d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 853d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 854d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 855d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 856d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 857d97b3072SJian Shen 858d97b3072SJian Shen tuple_sets = hclgevf_get_rss_hash_bits(nfc); 859d97b3072SJian Shen switch (nfc->flow_type) { 860d97b3072SJian Shen case TCP_V4_FLOW: 861d97b3072SJian Shen req->ipv4_tcp_en = tuple_sets; 862d97b3072SJian Shen break; 863d97b3072SJian Shen case TCP_V6_FLOW: 864d97b3072SJian Shen req->ipv6_tcp_en = tuple_sets; 865d97b3072SJian Shen break; 866d97b3072SJian Shen case UDP_V4_FLOW: 867d97b3072SJian Shen req->ipv4_udp_en = tuple_sets; 868d97b3072SJian Shen break; 869d97b3072SJian Shen case UDP_V6_FLOW: 870d97b3072SJian Shen req->ipv6_udp_en = tuple_sets; 871d97b3072SJian Shen break; 872d97b3072SJian Shen case SCTP_V4_FLOW: 873d97b3072SJian Shen req->ipv4_sctp_en = tuple_sets; 874d97b3072SJian Shen break; 875d97b3072SJian Shen case SCTP_V6_FLOW: 876d97b3072SJian Shen if ((nfc->data & RXH_L4_B_0_1) || 877d97b3072SJian Shen (nfc->data & RXH_L4_B_2_3)) 878d97b3072SJian Shen return -EINVAL; 879d97b3072SJian Shen 880d97b3072SJian Shen req->ipv6_sctp_en = tuple_sets; 881d97b3072SJian Shen break; 882d97b3072SJian Shen case IPV4_FLOW: 883d97b3072SJian Shen req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 884d97b3072SJian Shen break; 885d97b3072SJian Shen case IPV6_FLOW: 886d97b3072SJian Shen req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 887d97b3072SJian Shen break; 888d97b3072SJian Shen default: 889d97b3072SJian Shen return -EINVAL; 890d97b3072SJian Shen } 891d97b3072SJian Shen 892d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 893d97b3072SJian Shen if (ret) { 894d97b3072SJian Shen dev_err(&hdev->pdev->dev, 895d97b3072SJian Shen "Set rss tuple fail, status = %d\n", ret); 896d97b3072SJian Shen return ret; 897d97b3072SJian Shen } 898d97b3072SJian Shen 899d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 900d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 901d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 902d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 903d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 904d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 905d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 906d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 907d97b3072SJian Shen return 0; 908d97b3072SJian Shen } 909d97b3072SJian Shen 910d97b3072SJian Shen static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 911d97b3072SJian Shen struct ethtool_rxnfc *nfc) 912d97b3072SJian Shen { 913d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 914d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 915d97b3072SJian Shen u8 tuple_sets; 916d97b3072SJian Shen 917d97b3072SJian Shen if (handle->pdev->revision == 0x20) 918d97b3072SJian Shen return -EOPNOTSUPP; 919d97b3072SJian Shen 920d97b3072SJian Shen nfc->data = 0; 921d97b3072SJian Shen 922d97b3072SJian Shen switch (nfc->flow_type) { 923d97b3072SJian Shen case TCP_V4_FLOW: 924d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 925d97b3072SJian Shen break; 926d97b3072SJian Shen case UDP_V4_FLOW: 927d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 928d97b3072SJian Shen break; 929d97b3072SJian Shen case TCP_V6_FLOW: 930d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 931d97b3072SJian Shen break; 932d97b3072SJian Shen case UDP_V6_FLOW: 933d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 934d97b3072SJian Shen break; 935d97b3072SJian Shen case SCTP_V4_FLOW: 936d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 937d97b3072SJian Shen break; 938d97b3072SJian Shen case SCTP_V6_FLOW: 939d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 940d97b3072SJian Shen break; 941d97b3072SJian Shen case IPV4_FLOW: 942d97b3072SJian Shen case IPV6_FLOW: 943d97b3072SJian Shen tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 944d97b3072SJian Shen break; 945d97b3072SJian Shen default: 946d97b3072SJian Shen return -EINVAL; 947d97b3072SJian Shen } 948d97b3072SJian Shen 949d97b3072SJian Shen if (!tuple_sets) 950d97b3072SJian Shen return 0; 951d97b3072SJian Shen 952d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_PORT_BIT) 953d97b3072SJian Shen nfc->data |= RXH_L4_B_2_3; 954d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_PORT_BIT) 955d97b3072SJian Shen nfc->data |= RXH_L4_B_0_1; 956d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_IP_BIT) 957d97b3072SJian Shen nfc->data |= RXH_IP_DST; 958d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_IP_BIT) 959d97b3072SJian Shen nfc->data |= RXH_IP_SRC; 960d97b3072SJian Shen 961d97b3072SJian Shen return 0; 962d97b3072SJian Shen } 963d97b3072SJian Shen 964d97b3072SJian Shen static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 965d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg) 966d97b3072SJian Shen { 967d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 968d97b3072SJian Shen struct hclgevf_desc desc; 969d97b3072SJian Shen int ret; 970d97b3072SJian Shen 971d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 972d97b3072SJian Shen 973d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 974d97b3072SJian Shen 975d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 976d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 977d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 978d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 979d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 980d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 981d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 982d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 983d97b3072SJian Shen 984d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 985d97b3072SJian Shen if (ret) 986d97b3072SJian Shen dev_err(&hdev->pdev->dev, 987d97b3072SJian Shen "Configure rss input fail, status = %d\n", ret); 988d97b3072SJian Shen return ret; 989d97b3072SJian Shen } 990d97b3072SJian Shen 991e2cb1decSSalil Mehta static int hclgevf_get_tc_size(struct hnae3_handle *handle) 992e2cb1decSSalil Mehta { 993e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 994e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 995e2cb1decSSalil Mehta 996e2cb1decSSalil Mehta return rss_cfg->rss_size; 997e2cb1decSSalil Mehta } 998e2cb1decSSalil Mehta 999e2cb1decSSalil Mehta static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 1000b204bc74SPeng Li int vector_id, 1001e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1002e2cb1decSSalil Mehta { 1003e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1004e2cb1decSSalil Mehta struct hnae3_ring_chain_node *node; 1005e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 1006e2cb1decSSalil Mehta struct hclgevf_desc desc; 1007b204bc74SPeng Li int i = 0; 1008e2cb1decSSalil Mehta int status; 1009e2cb1decSSalil Mehta u8 type; 1010e2cb1decSSalil Mehta 1011e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1012c09ba484SPeng Li type = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 1013c09ba484SPeng Li HCLGE_MBX_UNMAP_RING_TO_VECTOR; 1014e2cb1decSSalil Mehta 1015e2cb1decSSalil Mehta for (node = ring_chain; node; node = node->next) { 10165d02a58dSYunsheng Lin int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 10175d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 10185d02a58dSYunsheng Lin 10195d02a58dSYunsheng Lin if (i == 0) { 10205d02a58dSYunsheng Lin hclgevf_cmd_setup_basic_desc(&desc, 10215d02a58dSYunsheng Lin HCLGEVF_OPC_MBX_VF_TO_PF, 10225d02a58dSYunsheng Lin false); 10235d02a58dSYunsheng Lin req->msg[0] = type; 10245d02a58dSYunsheng Lin req->msg[1] = vector_id; 10255d02a58dSYunsheng Lin } 10265d02a58dSYunsheng Lin 10275d02a58dSYunsheng Lin req->msg[idx_offset] = 1028e4e87715SPeng Li hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 10295d02a58dSYunsheng Lin req->msg[idx_offset + 1] = node->tqp_index; 1030e4e87715SPeng Li req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 103179eee410SFuyun Liang HNAE3_RING_GL_IDX_M, 103279eee410SFuyun Liang HNAE3_RING_GL_IDX_S); 103379eee410SFuyun Liang 10345d02a58dSYunsheng Lin i++; 10355d02a58dSYunsheng Lin if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 10365d02a58dSYunsheng Lin HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 10375d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 10385d02a58dSYunsheng Lin !node->next) { 1039e2cb1decSSalil Mehta req->msg[2] = i; 1040e2cb1decSSalil Mehta 1041e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1042e2cb1decSSalil Mehta if (status) { 1043e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1044e2cb1decSSalil Mehta "Map TQP fail, status is %d.\n", 1045e2cb1decSSalil Mehta status); 1046e2cb1decSSalil Mehta return status; 1047e2cb1decSSalil Mehta } 1048e2cb1decSSalil Mehta i = 0; 1049e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 1050e2cb1decSSalil Mehta HCLGEVF_OPC_MBX_VF_TO_PF, 1051e2cb1decSSalil Mehta false); 1052e2cb1decSSalil Mehta req->msg[0] = type; 1053e2cb1decSSalil Mehta req->msg[1] = vector_id; 1054e2cb1decSSalil Mehta } 1055e2cb1decSSalil Mehta } 1056e2cb1decSSalil Mehta 1057e2cb1decSSalil Mehta return 0; 1058e2cb1decSSalil Mehta } 1059e2cb1decSSalil Mehta 1060e2cb1decSSalil Mehta static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1061e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1062e2cb1decSSalil Mehta { 1063b204bc74SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1064b204bc74SPeng Li int vector_id; 1065b204bc74SPeng Li 1066b204bc74SPeng Li vector_id = hclgevf_get_vector_index(hdev, vector); 1067b204bc74SPeng Li if (vector_id < 0) { 1068b204bc74SPeng Li dev_err(&handle->pdev->dev, 1069b204bc74SPeng Li "Get vector index fail. ret =%d\n", vector_id); 1070b204bc74SPeng Li return vector_id; 1071b204bc74SPeng Li } 1072b204bc74SPeng Li 1073b204bc74SPeng Li return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1074e2cb1decSSalil Mehta } 1075e2cb1decSSalil Mehta 1076e2cb1decSSalil Mehta static int hclgevf_unmap_ring_from_vector( 1077e2cb1decSSalil Mehta struct hnae3_handle *handle, 1078e2cb1decSSalil Mehta int vector, 1079e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 1080e2cb1decSSalil Mehta { 1081e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1082e2cb1decSSalil Mehta int ret, vector_id; 1083e2cb1decSSalil Mehta 1084dea846e8SHuazhong Tan if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1085dea846e8SHuazhong Tan return 0; 1086dea846e8SHuazhong Tan 1087e2cb1decSSalil Mehta vector_id = hclgevf_get_vector_index(hdev, vector); 1088e2cb1decSSalil Mehta if (vector_id < 0) { 1089e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1090e2cb1decSSalil Mehta "Get vector index fail. ret =%d\n", vector_id); 1091e2cb1decSSalil Mehta return vector_id; 1092e2cb1decSSalil Mehta } 1093e2cb1decSSalil Mehta 1094b204bc74SPeng Li ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 10950d3e6631SYunsheng Lin if (ret) 1096e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 1097e2cb1decSSalil Mehta "Unmap ring from vector fail. vector=%d, ret =%d\n", 1098e2cb1decSSalil Mehta vector_id, 1099e2cb1decSSalil Mehta ret); 11000d3e6631SYunsheng Lin 1101e2cb1decSSalil Mehta return ret; 1102e2cb1decSSalil Mehta } 1103e2cb1decSSalil Mehta 11040d3e6631SYunsheng Lin static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 11050d3e6631SYunsheng Lin { 11060d3e6631SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 110703718db9SYunsheng Lin int vector_id; 11080d3e6631SYunsheng Lin 110903718db9SYunsheng Lin vector_id = hclgevf_get_vector_index(hdev, vector); 111003718db9SYunsheng Lin if (vector_id < 0) { 111103718db9SYunsheng Lin dev_err(&handle->pdev->dev, 111203718db9SYunsheng Lin "hclgevf_put_vector get vector index fail. ret =%d\n", 111303718db9SYunsheng Lin vector_id); 111403718db9SYunsheng Lin return vector_id; 111503718db9SYunsheng Lin } 111603718db9SYunsheng Lin 111703718db9SYunsheng Lin hclgevf_free_vector(hdev, vector_id); 1118e2cb1decSSalil Mehta 1119e2cb1decSSalil Mehta return 0; 1120e2cb1decSSalil Mehta } 1121e2cb1decSSalil Mehta 11223b75c3dfSPeng Li static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1123e196ec75SJian Shen bool en_uc_pmc, bool en_mc_pmc, 1124f01f5559SJian Shen bool en_bc_pmc) 1125e2cb1decSSalil Mehta { 1126e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 1127e2cb1decSSalil Mehta struct hclgevf_desc desc; 1128f01f5559SJian Shen int ret; 1129e2cb1decSSalil Mehta 1130e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1131e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 1132e2cb1decSSalil Mehta req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 1133f01f5559SJian Shen req->msg[1] = en_bc_pmc ? 1 : 0; 1134e196ec75SJian Shen req->msg[2] = en_uc_pmc ? 1 : 0; 1135e196ec75SJian Shen req->msg[3] = en_mc_pmc ? 1 : 0; 1136e2cb1decSSalil Mehta 1137f01f5559SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1138f01f5559SJian Shen if (ret) 1139e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1140f01f5559SJian Shen "Set promisc mode fail, status is %d.\n", ret); 1141e2cb1decSSalil Mehta 1142f01f5559SJian Shen return ret; 1143e2cb1decSSalil Mehta } 1144e2cb1decSSalil Mehta 1145e196ec75SJian Shen static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 1146e196ec75SJian Shen bool en_mc_pmc) 1147e2cb1decSSalil Mehta { 1148e196ec75SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1149e196ec75SJian Shen struct pci_dev *pdev = hdev->pdev; 1150e196ec75SJian Shen bool en_bc_pmc; 1151e196ec75SJian Shen 1152e196ec75SJian Shen en_bc_pmc = pdev->revision != 0x20; 1153e196ec75SJian Shen 1154e196ec75SJian Shen return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc, 1155e196ec75SJian Shen en_bc_pmc); 1156e2cb1decSSalil Mehta } 1157e2cb1decSSalil Mehta 1158ebaf1908SWeihang Li static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, unsigned int tqp_id, 1159e2cb1decSSalil Mehta int stream_id, bool enable) 1160e2cb1decSSalil Mehta { 1161e2cb1decSSalil Mehta struct hclgevf_cfg_com_tqp_queue_cmd *req; 1162e2cb1decSSalil Mehta struct hclgevf_desc desc; 1163e2cb1decSSalil Mehta int status; 1164e2cb1decSSalil Mehta 1165e2cb1decSSalil Mehta req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1166e2cb1decSSalil Mehta 1167e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1168e2cb1decSSalil Mehta false); 1169e2cb1decSSalil Mehta req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1170e2cb1decSSalil Mehta req->stream_id = cpu_to_le16(stream_id); 1171ebaf1908SWeihang Li if (enable) 1172ebaf1908SWeihang Li req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 1173e2cb1decSSalil Mehta 1174e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1175e2cb1decSSalil Mehta if (status) 1176e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1177e2cb1decSSalil Mehta "TQP enable fail, status =%d.\n", status); 1178e2cb1decSSalil Mehta 1179e2cb1decSSalil Mehta return status; 1180e2cb1decSSalil Mehta } 1181e2cb1decSSalil Mehta 1182e2cb1decSSalil Mehta static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1183e2cb1decSSalil Mehta { 1184b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1185e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 1186e2cb1decSSalil Mehta int i; 1187e2cb1decSSalil Mehta 1188b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 1189b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1190e2cb1decSSalil Mehta memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1191e2cb1decSSalil Mehta } 1192e2cb1decSSalil Mehta } 1193e2cb1decSSalil Mehta 11948e6de441SHuazhong Tan static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p) 11958e6de441SHuazhong Tan { 11968e6de441SHuazhong Tan u8 host_mac[ETH_ALEN]; 11978e6de441SHuazhong Tan int status; 11988e6de441SHuazhong Tan 11998e6de441SHuazhong Tan status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_MAC_ADDR, 0, NULL, 0, 12008e6de441SHuazhong Tan true, host_mac, ETH_ALEN); 12018e6de441SHuazhong Tan if (status) { 12028e6de441SHuazhong Tan dev_err(&hdev->pdev->dev, 12038e6de441SHuazhong Tan "fail to get VF MAC from host %d", status); 12048e6de441SHuazhong Tan return status; 12058e6de441SHuazhong Tan } 12068e6de441SHuazhong Tan 12078e6de441SHuazhong Tan ether_addr_copy(p, host_mac); 12088e6de441SHuazhong Tan 12098e6de441SHuazhong Tan return 0; 12108e6de441SHuazhong Tan } 12118e6de441SHuazhong Tan 1212e2cb1decSSalil Mehta static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1213e2cb1decSSalil Mehta { 1214e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 12158e6de441SHuazhong Tan u8 host_mac_addr[ETH_ALEN]; 1216e2cb1decSSalil Mehta 12178e6de441SHuazhong Tan if (hclgevf_get_host_mac_addr(hdev, host_mac_addr)) 12188e6de441SHuazhong Tan return; 12198e6de441SHuazhong Tan 12208e6de441SHuazhong Tan hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr); 12218e6de441SHuazhong Tan if (hdev->has_pf_mac) 12228e6de441SHuazhong Tan ether_addr_copy(p, host_mac_addr); 12238e6de441SHuazhong Tan else 1224e2cb1decSSalil Mehta ether_addr_copy(p, hdev->hw.mac.mac_addr); 1225e2cb1decSSalil Mehta } 1226e2cb1decSSalil Mehta 122759098055SFuyun Liang static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 122859098055SFuyun Liang bool is_first) 1229e2cb1decSSalil Mehta { 1230e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1231e2cb1decSSalil Mehta u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1232e2cb1decSSalil Mehta u8 *new_mac_addr = (u8 *)p; 1233e2cb1decSSalil Mehta u8 msg_data[ETH_ALEN * 2]; 123459098055SFuyun Liang u16 subcode; 1235e2cb1decSSalil Mehta int status; 1236e2cb1decSSalil Mehta 1237e2cb1decSSalil Mehta ether_addr_copy(msg_data, new_mac_addr); 1238e2cb1decSSalil Mehta ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 1239e2cb1decSSalil Mehta 124059098055SFuyun Liang subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 124159098055SFuyun Liang HCLGE_MBX_MAC_VLAN_UC_MODIFY; 124259098055SFuyun Liang 1243e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 124463cbf7a9SYufeng Mo subcode, msg_data, sizeof(msg_data), 12452097fdefSJian Shen true, NULL, 0); 1246e2cb1decSSalil Mehta if (!status) 1247e2cb1decSSalil Mehta ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1248e2cb1decSSalil Mehta 1249e2cb1decSSalil Mehta return status; 1250e2cb1decSSalil Mehta } 1251e2cb1decSSalil Mehta 1252e2cb1decSSalil Mehta static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1253e2cb1decSSalil Mehta const unsigned char *addr) 1254e2cb1decSSalil Mehta { 1255e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1256e2cb1decSSalil Mehta 1257e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1258e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_ADD, 1259e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1260e2cb1decSSalil Mehta } 1261e2cb1decSSalil Mehta 1262e2cb1decSSalil Mehta static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1263e2cb1decSSalil Mehta const unsigned char *addr) 1264e2cb1decSSalil Mehta { 1265e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1266e2cb1decSSalil Mehta 1267e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1268e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1269e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1270e2cb1decSSalil Mehta } 1271e2cb1decSSalil Mehta 1272e2cb1decSSalil Mehta static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1273e2cb1decSSalil Mehta const unsigned char *addr) 1274e2cb1decSSalil Mehta { 1275e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1276e2cb1decSSalil Mehta 1277e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1278e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_ADD, 1279e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1280e2cb1decSSalil Mehta } 1281e2cb1decSSalil Mehta 1282e2cb1decSSalil Mehta static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1283e2cb1decSSalil Mehta const unsigned char *addr) 1284e2cb1decSSalil Mehta { 1285e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1286e2cb1decSSalil Mehta 1287e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1288e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1289e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1290e2cb1decSSalil Mehta } 1291e2cb1decSSalil Mehta 1292e2cb1decSSalil Mehta static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1293e2cb1decSSalil Mehta __be16 proto, u16 vlan_id, 1294e2cb1decSSalil Mehta bool is_kill) 1295e2cb1decSSalil Mehta { 1296e2cb1decSSalil Mehta #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1297e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1298e2cb1decSSalil Mehta u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1299fe4144d4SJian Shen int ret; 1300e2cb1decSSalil Mehta 1301b37ce587SYufeng Mo if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1302e2cb1decSSalil Mehta return -EINVAL; 1303e2cb1decSSalil Mehta 1304e2cb1decSSalil Mehta if (proto != htons(ETH_P_8021Q)) 1305e2cb1decSSalil Mehta return -EPROTONOSUPPORT; 1306e2cb1decSSalil Mehta 1307fe4144d4SJian Shen /* When device is resetting, firmware is unable to handle 1308fe4144d4SJian Shen * mailbox. Just record the vlan id, and remove it after 1309fe4144d4SJian Shen * reset finished. 1310fe4144d4SJian Shen */ 1311fe4144d4SJian Shen if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) && is_kill) { 1312fe4144d4SJian Shen set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1313fe4144d4SJian Shen return -EBUSY; 1314fe4144d4SJian Shen } 1315fe4144d4SJian Shen 1316e2cb1decSSalil Mehta msg_data[0] = is_kill; 1317e2cb1decSSalil Mehta memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1318e2cb1decSSalil Mehta memcpy(&msg_data[3], &proto, sizeof(proto)); 131946ee7350SGuojia Liao /* when remove hw vlan filter failed, record the vlan id, 1320fe4144d4SJian Shen * and try to remove it from hw later, to be consistence 1321fe4144d4SJian Shen * with stack. 1322fe4144d4SJian Shen */ 1323e3105329SGuangbin Huang ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1324e3105329SGuangbin Huang HCLGE_MBX_VLAN_FILTER, msg_data, 1325e3105329SGuangbin Huang HCLGEVF_VLAN_MBX_MSG_LEN, true, NULL, 0); 1326fe4144d4SJian Shen if (is_kill && ret) 1327fe4144d4SJian Shen set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1328fe4144d4SJian Shen 1329fe4144d4SJian Shen return ret; 1330fe4144d4SJian Shen } 1331fe4144d4SJian Shen 1332fe4144d4SJian Shen static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1333fe4144d4SJian Shen { 1334fe4144d4SJian Shen #define HCLGEVF_MAX_SYNC_COUNT 60 1335fe4144d4SJian Shen struct hnae3_handle *handle = &hdev->nic; 1336fe4144d4SJian Shen int ret, sync_cnt = 0; 1337fe4144d4SJian Shen u16 vlan_id; 1338fe4144d4SJian Shen 1339fe4144d4SJian Shen vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1340fe4144d4SJian Shen while (vlan_id != VLAN_N_VID) { 1341fe4144d4SJian Shen ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1342fe4144d4SJian Shen vlan_id, true); 1343fe4144d4SJian Shen if (ret) 1344fe4144d4SJian Shen return; 1345fe4144d4SJian Shen 1346fe4144d4SJian Shen clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1347fe4144d4SJian Shen sync_cnt++; 1348fe4144d4SJian Shen if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1349fe4144d4SJian Shen return; 1350fe4144d4SJian Shen 1351fe4144d4SJian Shen vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1352fe4144d4SJian Shen } 1353e2cb1decSSalil Mehta } 1354e2cb1decSSalil Mehta 1355b2641e2aSYunsheng Lin static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1356b2641e2aSYunsheng Lin { 1357b2641e2aSYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1358b2641e2aSYunsheng Lin u8 msg_data; 1359b2641e2aSYunsheng Lin 1360b2641e2aSYunsheng Lin msg_data = enable ? 1 : 0; 1361b2641e2aSYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1362b2641e2aSYunsheng Lin HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1363b2641e2aSYunsheng Lin 1, false, NULL, 0); 1364b2641e2aSYunsheng Lin } 1365b2641e2aSYunsheng Lin 13667fa6be4fSHuazhong Tan static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1367e2cb1decSSalil Mehta { 1368e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1369e2cb1decSSalil Mehta u8 msg_data[2]; 13701a426f8bSPeng Li int ret; 1371e2cb1decSSalil Mehta 137263cbf7a9SYufeng Mo memcpy(msg_data, &queue_id, sizeof(queue_id)); 1373e2cb1decSSalil Mehta 13741a426f8bSPeng Li /* disable vf queue before send queue reset msg to PF */ 13751a426f8bSPeng Li ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 13761a426f8bSPeng Li if (ret) 13777fa6be4fSHuazhong Tan return ret; 13781a426f8bSPeng Li 13797fa6be4fSHuazhong Tan return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 138063cbf7a9SYufeng Mo sizeof(msg_data), true, NULL, 0); 1381e2cb1decSSalil Mehta } 1382e2cb1decSSalil Mehta 1383818f1675SYunsheng Lin static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1384818f1675SYunsheng Lin { 1385818f1675SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1386818f1675SYunsheng Lin 1387818f1675SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu, 1388818f1675SYunsheng Lin sizeof(new_mtu), true, NULL, 0); 1389818f1675SYunsheng Lin } 1390818f1675SYunsheng Lin 13916988eb2aSSalil Mehta static int hclgevf_notify_client(struct hclgevf_dev *hdev, 13926988eb2aSSalil Mehta enum hnae3_reset_notify_type type) 13936988eb2aSSalil Mehta { 13946988eb2aSSalil Mehta struct hnae3_client *client = hdev->nic_client; 13956988eb2aSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 13966a5f6fa3SHuazhong Tan int ret; 13976988eb2aSSalil Mehta 139825d1817cSHuazhong Tan if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 139925d1817cSHuazhong Tan !client) 140025d1817cSHuazhong Tan return 0; 140125d1817cSHuazhong Tan 14026988eb2aSSalil Mehta if (!client->ops->reset_notify) 14036988eb2aSSalil Mehta return -EOPNOTSUPP; 14046988eb2aSSalil Mehta 14056a5f6fa3SHuazhong Tan ret = client->ops->reset_notify(handle, type); 14066a5f6fa3SHuazhong Tan if (ret) 14076a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 14086a5f6fa3SHuazhong Tan type, ret); 14096a5f6fa3SHuazhong Tan 14106a5f6fa3SHuazhong Tan return ret; 14116988eb2aSSalil Mehta } 14126988eb2aSSalil Mehta 14136988eb2aSSalil Mehta static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 14146988eb2aSSalil Mehta { 1415aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_US 20000 1416aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_CNT 2000 1417aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1418aa5c4f17SHuazhong Tan (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1419aa5c4f17SHuazhong Tan 1420aa5c4f17SHuazhong Tan u32 val; 1421aa5c4f17SHuazhong Tan int ret; 14226988eb2aSSalil Mehta 1423f28368bbSHuazhong Tan if (hdev->reset_type == HNAE3_VF_RESET) 142472e2fb07SHuazhong Tan ret = readl_poll_timeout(hdev->hw.io_base + 142572e2fb07SHuazhong Tan HCLGEVF_VF_RST_ING, val, 142672e2fb07SHuazhong Tan !(val & HCLGEVF_VF_RST_ING_BIT), 142772e2fb07SHuazhong Tan HCLGEVF_RESET_WAIT_US, 142872e2fb07SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 142972e2fb07SHuazhong Tan else 143072e2fb07SHuazhong Tan ret = readl_poll_timeout(hdev->hw.io_base + 143172e2fb07SHuazhong Tan HCLGEVF_RST_ING, val, 1432aa5c4f17SHuazhong Tan !(val & HCLGEVF_RST_ING_BITS), 1433aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_US, 1434aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 14356988eb2aSSalil Mehta 14366988eb2aSSalil Mehta /* hardware completion status should be available by this time */ 1437aa5c4f17SHuazhong Tan if (ret) { 1438aa5c4f17SHuazhong Tan dev_err(&hdev->pdev->dev, 14396988eb2aSSalil Mehta "could'nt get reset done status from h/w, timeout!\n"); 1440aa5c4f17SHuazhong Tan return ret; 14416988eb2aSSalil Mehta } 14426988eb2aSSalil Mehta 14436988eb2aSSalil Mehta /* we will wait a bit more to let reset of the stack to complete. This 14446988eb2aSSalil Mehta * might happen in case reset assertion was made by PF. Yes, this also 14456988eb2aSSalil Mehta * means we might end up waiting bit more even for VF reset. 14466988eb2aSSalil Mehta */ 14476988eb2aSSalil Mehta msleep(5000); 14486988eb2aSSalil Mehta 14496988eb2aSSalil Mehta return 0; 14506988eb2aSSalil Mehta } 14516988eb2aSSalil Mehta 14526b428b4fSHuazhong Tan static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable) 14536b428b4fSHuazhong Tan { 14546b428b4fSHuazhong Tan u32 reg_val; 14556b428b4fSHuazhong Tan 14566b428b4fSHuazhong Tan reg_val = hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG); 14576b428b4fSHuazhong Tan if (enable) 14586b428b4fSHuazhong Tan reg_val |= HCLGEVF_NIC_SW_RST_RDY; 14596b428b4fSHuazhong Tan else 14606b428b4fSHuazhong Tan reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; 14616b428b4fSHuazhong Tan 14626b428b4fSHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 14636b428b4fSHuazhong Tan reg_val); 14646b428b4fSHuazhong Tan } 14656b428b4fSHuazhong Tan 14666988eb2aSSalil Mehta static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 14676988eb2aSSalil Mehta { 14687a01c897SSalil Mehta int ret; 14697a01c897SSalil Mehta 14706988eb2aSSalil Mehta /* uninitialize the nic client */ 14716a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 14726a5f6fa3SHuazhong Tan if (ret) 14736a5f6fa3SHuazhong Tan return ret; 14746988eb2aSSalil Mehta 14757a01c897SSalil Mehta /* re-initialize the hclge device */ 14769c6f7085SHuazhong Tan ret = hclgevf_reset_hdev(hdev); 14777a01c897SSalil Mehta if (ret) { 14787a01c897SSalil Mehta dev_err(&hdev->pdev->dev, 14797a01c897SSalil Mehta "hclge device re-init failed, VF is disabled!\n"); 14807a01c897SSalil Mehta return ret; 14817a01c897SSalil Mehta } 14826988eb2aSSalil Mehta 14836988eb2aSSalil Mehta /* bring up the nic client again */ 14846a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 14856a5f6fa3SHuazhong Tan if (ret) 14866a5f6fa3SHuazhong Tan return ret; 14876988eb2aSSalil Mehta 14886b428b4fSHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT); 14896b428b4fSHuazhong Tan if (ret) 14906b428b4fSHuazhong Tan return ret; 14916b428b4fSHuazhong Tan 14926b428b4fSHuazhong Tan /* clear handshake status with IMP */ 14936b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, false); 14946b428b4fSHuazhong Tan 14951cc9bc6eSHuazhong Tan /* bring up the nic to enable TX/RX again */ 14961cc9bc6eSHuazhong Tan return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 14976988eb2aSSalil Mehta } 14986988eb2aSSalil Mehta 1499dea846e8SHuazhong Tan static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1500dea846e8SHuazhong Tan { 1501ada13ee3SHuazhong Tan #define HCLGEVF_RESET_SYNC_TIME 100 1502ada13ee3SHuazhong Tan 1503dea846e8SHuazhong Tan int ret = 0; 1504dea846e8SHuazhong Tan 1505f28368bbSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FUNC_RESET) { 1506dea846e8SHuazhong Tan ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1507dea846e8SHuazhong Tan 0, true, NULL, sizeof(u8)); 1508c88a6e7dSHuazhong Tan hdev->rst_stats.vf_func_rst_cnt++; 1509dea846e8SHuazhong Tan } 1510dea846e8SHuazhong Tan 1511ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1512ada13ee3SHuazhong Tan /* inform hardware that preparatory work is done */ 1513ada13ee3SHuazhong Tan msleep(HCLGEVF_RESET_SYNC_TIME); 15146b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, true); 1515dea846e8SHuazhong Tan dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1516dea846e8SHuazhong Tan hdev->reset_type, ret); 1517dea846e8SHuazhong Tan 1518dea846e8SHuazhong Tan return ret; 1519dea846e8SHuazhong Tan } 1520dea846e8SHuazhong Tan 15213d77d0cbSHuazhong Tan static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev) 15223d77d0cbSHuazhong Tan { 15233d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "VF function reset count: %u\n", 15243d77d0cbSHuazhong Tan hdev->rst_stats.vf_func_rst_cnt); 15253d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "FLR reset count: %u\n", 15263d77d0cbSHuazhong Tan hdev->rst_stats.flr_rst_cnt); 15273d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "VF reset count: %u\n", 15283d77d0cbSHuazhong Tan hdev->rst_stats.vf_rst_cnt); 15293d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "reset done count: %u\n", 15303d77d0cbSHuazhong Tan hdev->rst_stats.rst_done_cnt); 15313d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "HW reset done count: %u\n", 15323d77d0cbSHuazhong Tan hdev->rst_stats.hw_rst_done_cnt); 15333d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "reset count: %u\n", 15343d77d0cbSHuazhong Tan hdev->rst_stats.rst_cnt); 15353d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "reset fail count: %u\n", 15363d77d0cbSHuazhong Tan hdev->rst_stats.rst_fail_cnt); 15373d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n", 15383d77d0cbSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE)); 15393d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n", 15403d77d0cbSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_STAT_REG)); 15413d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n", 15423d77d0cbSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_CMDQ_TX_DEPTH_REG)); 15433d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n", 15443d77d0cbSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING)); 15453d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state); 15463d77d0cbSHuazhong Tan } 15473d77d0cbSHuazhong Tan 1548bbe6540eSHuazhong Tan static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1549bbe6540eSHuazhong Tan { 15506b428b4fSHuazhong Tan /* recover handshake status with IMP when reset fail */ 15516b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, true); 1552bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt++; 1553adcf738bSGuojia Liao dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n", 1554bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt); 1555bbe6540eSHuazhong Tan 1556bbe6540eSHuazhong Tan if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1557bbe6540eSHuazhong Tan set_bit(hdev->reset_type, &hdev->reset_pending); 1558bbe6540eSHuazhong Tan 1559bbe6540eSHuazhong Tan if (hclgevf_is_reset_pending(hdev)) { 1560bbe6540eSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1561bbe6540eSHuazhong Tan hclgevf_reset_task_schedule(hdev); 15623d77d0cbSHuazhong Tan } else { 1563d5432455SGuojia Liao set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 15643d77d0cbSHuazhong Tan hclgevf_dump_rst_info(hdev); 1565bbe6540eSHuazhong Tan } 1566bbe6540eSHuazhong Tan } 1567bbe6540eSHuazhong Tan 15681cc9bc6eSHuazhong Tan static int hclgevf_reset_prepare(struct hclgevf_dev *hdev) 15696988eb2aSSalil Mehta { 1570dea846e8SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 15716988eb2aSSalil Mehta int ret; 15726988eb2aSSalil Mehta 1573dea846e8SHuazhong Tan /* Initialize ae_dev reset status as well, in case enet layer wants to 1574dea846e8SHuazhong Tan * know if device is undergoing reset 1575dea846e8SHuazhong Tan */ 1576dea846e8SHuazhong Tan ae_dev->reset_type = hdev->reset_type; 1577c88a6e7dSHuazhong Tan hdev->rst_stats.rst_cnt++; 15786988eb2aSSalil Mehta 15791cc9bc6eSHuazhong Tan rtnl_lock(); 15806988eb2aSSalil Mehta /* bring down the nic to stop any ongoing TX/RX */ 15816a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 158229118ab9SHuazhong Tan rtnl_unlock(); 15836a5f6fa3SHuazhong Tan if (ret) 15841cc9bc6eSHuazhong Tan return ret; 1585dea846e8SHuazhong Tan 15861cc9bc6eSHuazhong Tan return hclgevf_reset_prepare_wait(hdev); 15876988eb2aSSalil Mehta } 15886988eb2aSSalil Mehta 15891cc9bc6eSHuazhong Tan static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev) 15901cc9bc6eSHuazhong Tan { 15911cc9bc6eSHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 15921cc9bc6eSHuazhong Tan int ret; 15931cc9bc6eSHuazhong Tan 1594c88a6e7dSHuazhong Tan hdev->rst_stats.hw_rst_done_cnt++; 1595c88a6e7dSHuazhong Tan 159629118ab9SHuazhong Tan rtnl_lock(); 15976988eb2aSSalil Mehta /* now, re-initialize the nic client and ae device */ 15986988eb2aSSalil Mehta ret = hclgevf_reset_stack(hdev); 15991cc9bc6eSHuazhong Tan rtnl_unlock(); 16006a5f6fa3SHuazhong Tan if (ret) { 16016988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 16021cc9bc6eSHuazhong Tan return ret; 16036a5f6fa3SHuazhong Tan } 16046988eb2aSSalil Mehta 1605b644a8d4SHuazhong Tan hdev->last_reset_time = jiffies; 1606b644a8d4SHuazhong Tan ae_dev->reset_type = HNAE3_NONE_RESET; 1607c88a6e7dSHuazhong Tan hdev->rst_stats.rst_done_cnt++; 1608bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt = 0; 1609d5432455SGuojia Liao clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1610b644a8d4SHuazhong Tan 16111cc9bc6eSHuazhong Tan return 0; 16121cc9bc6eSHuazhong Tan } 16131cc9bc6eSHuazhong Tan 16141cc9bc6eSHuazhong Tan static void hclgevf_reset(struct hclgevf_dev *hdev) 16151cc9bc6eSHuazhong Tan { 16161cc9bc6eSHuazhong Tan if (hclgevf_reset_prepare(hdev)) 16171cc9bc6eSHuazhong Tan goto err_reset; 16181cc9bc6eSHuazhong Tan 16191cc9bc6eSHuazhong Tan /* check if VF could successfully fetch the hardware reset completion 16201cc9bc6eSHuazhong Tan * status from the hardware 16211cc9bc6eSHuazhong Tan */ 16221cc9bc6eSHuazhong Tan if (hclgevf_reset_wait(hdev)) { 16231cc9bc6eSHuazhong Tan /* can't do much in this situation, will disable VF */ 16241cc9bc6eSHuazhong Tan dev_err(&hdev->pdev->dev, 16251cc9bc6eSHuazhong Tan "failed to fetch H/W reset completion status\n"); 16261cc9bc6eSHuazhong Tan goto err_reset; 16271cc9bc6eSHuazhong Tan } 16281cc9bc6eSHuazhong Tan 16291cc9bc6eSHuazhong Tan if (hclgevf_reset_rebuild(hdev)) 16301cc9bc6eSHuazhong Tan goto err_reset; 16311cc9bc6eSHuazhong Tan 16321cc9bc6eSHuazhong Tan return; 16331cc9bc6eSHuazhong Tan 16346a5f6fa3SHuazhong Tan err_reset: 1635bbe6540eSHuazhong Tan hclgevf_reset_err_handle(hdev); 16366988eb2aSSalil Mehta } 16376988eb2aSSalil Mehta 1638720bd583SHuazhong Tan static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1639720bd583SHuazhong Tan unsigned long *addr) 1640720bd583SHuazhong Tan { 1641720bd583SHuazhong Tan enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1642720bd583SHuazhong Tan 1643dea846e8SHuazhong Tan /* return the highest priority reset level amongst all */ 1644b90fcc5bSHuazhong Tan if (test_bit(HNAE3_VF_RESET, addr)) { 1645b90fcc5bSHuazhong Tan rst_level = HNAE3_VF_RESET; 1646b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_RESET, addr); 1647b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1648b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1649b90fcc5bSHuazhong Tan } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1650dea846e8SHuazhong Tan rst_level = HNAE3_VF_FULL_RESET; 1651dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FULL_RESET, addr); 1652dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1653aa5c4f17SHuazhong Tan } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1654aa5c4f17SHuazhong Tan rst_level = HNAE3_VF_PF_FUNC_RESET; 1655aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1656aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1657dea846e8SHuazhong Tan } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1658dea846e8SHuazhong Tan rst_level = HNAE3_VF_FUNC_RESET; 1659dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 16606ff3cf07SHuazhong Tan } else if (test_bit(HNAE3_FLR_RESET, addr)) { 16616ff3cf07SHuazhong Tan rst_level = HNAE3_FLR_RESET; 16626ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_RESET, addr); 1663720bd583SHuazhong Tan } 1664720bd583SHuazhong Tan 1665720bd583SHuazhong Tan return rst_level; 1666720bd583SHuazhong Tan } 1667720bd583SHuazhong Tan 16686ae4e733SShiju Jose static void hclgevf_reset_event(struct pci_dev *pdev, 16696ae4e733SShiju Jose struct hnae3_handle *handle) 16706d4c3981SSalil Mehta { 16716ff3cf07SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 16726ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 16736d4c3981SSalil Mehta 16746d4c3981SSalil Mehta dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 16756d4c3981SSalil Mehta 16766ff3cf07SHuazhong Tan if (hdev->default_reset_request) 16770742ed7cSHuazhong Tan hdev->reset_level = 1678720bd583SHuazhong Tan hclgevf_get_reset_level(hdev, 1679720bd583SHuazhong Tan &hdev->default_reset_request); 1680720bd583SHuazhong Tan else 1681dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 16826d4c3981SSalil Mehta 1683436667d2SSalil Mehta /* reset of this VF requested */ 1684436667d2SSalil Mehta set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1685436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 16866d4c3981SSalil Mehta 16870742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 16886d4c3981SSalil Mehta } 16896d4c3981SSalil Mehta 1690720bd583SHuazhong Tan static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1691720bd583SHuazhong Tan enum hnae3_reset_type rst_type) 1692720bd583SHuazhong Tan { 1693720bd583SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1694720bd583SHuazhong Tan 1695720bd583SHuazhong Tan set_bit(rst_type, &hdev->default_reset_request); 1696720bd583SHuazhong Tan } 1697720bd583SHuazhong Tan 1698f28368bbSHuazhong Tan static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1699f28368bbSHuazhong Tan { 1700f28368bbSHuazhong Tan writel(en ? 1 : 0, vector->addr); 1701f28368bbSHuazhong Tan } 1702f28368bbSHuazhong Tan 17036ff3cf07SHuazhong Tan static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 17046ff3cf07SHuazhong Tan { 1705f28368bbSHuazhong Tan #define HCLGEVF_FLR_RETRY_WAIT_MS 500 1706f28368bbSHuazhong Tan #define HCLGEVF_FLR_RETRY_CNT 5 1707f28368bbSHuazhong Tan 17086ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1709f28368bbSHuazhong Tan int retry_cnt = 0; 1710f28368bbSHuazhong Tan int ret; 17116ff3cf07SHuazhong Tan 1712f28368bbSHuazhong Tan retry: 1713f28368bbSHuazhong Tan down(&hdev->reset_sem); 1714f28368bbSHuazhong Tan set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1715f28368bbSHuazhong Tan hdev->reset_type = HNAE3_FLR_RESET; 1716f28368bbSHuazhong Tan ret = hclgevf_reset_prepare(hdev); 1717f28368bbSHuazhong Tan if (ret) { 1718f28368bbSHuazhong Tan dev_err(&hdev->pdev->dev, "fail to prepare FLR, ret=%d\n", 1719f28368bbSHuazhong Tan ret); 1720f28368bbSHuazhong Tan if (hdev->reset_pending || 1721f28368bbSHuazhong Tan retry_cnt++ < HCLGEVF_FLR_RETRY_CNT) { 17226ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 1723f28368bbSHuazhong Tan "reset_pending:0x%lx, retry_cnt:%d\n", 1724f28368bbSHuazhong Tan hdev->reset_pending, retry_cnt); 1725f28368bbSHuazhong Tan clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1726f28368bbSHuazhong Tan up(&hdev->reset_sem); 1727f28368bbSHuazhong Tan msleep(HCLGEVF_FLR_RETRY_WAIT_MS); 1728f28368bbSHuazhong Tan goto retry; 1729f28368bbSHuazhong Tan } 1730f28368bbSHuazhong Tan } 1731f28368bbSHuazhong Tan 1732f28368bbSHuazhong Tan /* disable misc vector before FLR done */ 1733f28368bbSHuazhong Tan hclgevf_enable_vector(&hdev->misc_vector, false); 1734f28368bbSHuazhong Tan hdev->rst_stats.flr_rst_cnt++; 1735f28368bbSHuazhong Tan } 1736f28368bbSHuazhong Tan 1737f28368bbSHuazhong Tan static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 1738f28368bbSHuazhong Tan { 1739f28368bbSHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1740f28368bbSHuazhong Tan int ret; 1741f28368bbSHuazhong Tan 1742f28368bbSHuazhong Tan hclgevf_enable_vector(&hdev->misc_vector, true); 1743f28368bbSHuazhong Tan 1744f28368bbSHuazhong Tan ret = hclgevf_reset_rebuild(hdev); 1745f28368bbSHuazhong Tan if (ret) 1746f28368bbSHuazhong Tan dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", 1747f28368bbSHuazhong Tan ret); 1748f28368bbSHuazhong Tan 1749f28368bbSHuazhong Tan hdev->reset_type = HNAE3_NONE_RESET; 1750f28368bbSHuazhong Tan clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1751f28368bbSHuazhong Tan up(&hdev->reset_sem); 17526ff3cf07SHuazhong Tan } 17536ff3cf07SHuazhong Tan 1754e2cb1decSSalil Mehta static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1755e2cb1decSSalil Mehta { 1756e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1757e2cb1decSSalil Mehta 1758e2cb1decSSalil Mehta return hdev->fw_version; 1759e2cb1decSSalil Mehta } 1760e2cb1decSSalil Mehta 1761e2cb1decSSalil Mehta static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1762e2cb1decSSalil Mehta { 1763e2cb1decSSalil Mehta struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1764e2cb1decSSalil Mehta 1765e2cb1decSSalil Mehta vector->vector_irq = pci_irq_vector(hdev->pdev, 1766e2cb1decSSalil Mehta HCLGEVF_MISC_VECTOR_NUM); 1767e2cb1decSSalil Mehta vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1768e2cb1decSSalil Mehta /* vector status always valid for Vector 0 */ 1769e2cb1decSSalil Mehta hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1770e2cb1decSSalil Mehta hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1771e2cb1decSSalil Mehta 1772e2cb1decSSalil Mehta hdev->num_msi_left -= 1; 1773e2cb1decSSalil Mehta hdev->num_msi_used += 1; 1774e2cb1decSSalil Mehta } 1775e2cb1decSSalil Mehta 177635a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 177735a1e503SSalil Mehta { 1778ff200099SYunsheng Lin if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1779ff200099SYunsheng Lin !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, 1780ff200099SYunsheng Lin &hdev->state)) 17810ea68902SYunsheng Lin mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 178235a1e503SSalil Mehta } 178335a1e503SSalil Mehta 178407a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1785e2cb1decSSalil Mehta { 1786ff200099SYunsheng Lin if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1787ff200099SYunsheng Lin !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, 1788ff200099SYunsheng Lin &hdev->state)) 17890ea68902SYunsheng Lin mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 179007a0556aSSalil Mehta } 1791e2cb1decSSalil Mehta 1792ff200099SYunsheng Lin static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 1793ff200099SYunsheng Lin unsigned long delay) 1794e2cb1decSSalil Mehta { 1795d5432455SGuojia Liao if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1796d5432455SGuojia Liao !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 17970ea68902SYunsheng Lin mod_delayed_work(hclgevf_wq, &hdev->service_task, delay); 1798e2cb1decSSalil Mehta } 1799e2cb1decSSalil Mehta 1800ff200099SYunsheng Lin static void hclgevf_reset_service_task(struct hclgevf_dev *hdev) 180135a1e503SSalil Mehta { 1802d6ad7c53SGuojia Liao #define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3 1803d6ad7c53SGuojia Liao 1804ff200099SYunsheng Lin if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state)) 1805ff200099SYunsheng Lin return; 1806ff200099SYunsheng Lin 1807f28368bbSHuazhong Tan down(&hdev->reset_sem); 1808f28368bbSHuazhong Tan set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 180935a1e503SSalil Mehta 1810436667d2SSalil Mehta if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1811436667d2SSalil Mehta &hdev->reset_state)) { 1812436667d2SSalil Mehta /* PF has initmated that it is about to reset the hardware. 18139b2f3477SWeihang Li * We now have to poll & check if hardware has actually 18149b2f3477SWeihang Li * completed the reset sequence. On hardware reset completion, 18159b2f3477SWeihang Li * VF needs to reset the client and ae device. 181635a1e503SSalil Mehta */ 1817436667d2SSalil Mehta hdev->reset_attempts = 0; 1818436667d2SSalil Mehta 1819dea846e8SHuazhong Tan hdev->last_reset_time = jiffies; 1820dea846e8SHuazhong Tan while ((hdev->reset_type = 1821dea846e8SHuazhong Tan hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 18221cc9bc6eSHuazhong Tan != HNAE3_NONE_RESET) 18231cc9bc6eSHuazhong Tan hclgevf_reset(hdev); 1824436667d2SSalil Mehta } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1825436667d2SSalil Mehta &hdev->reset_state)) { 1826436667d2SSalil Mehta /* we could be here when either of below happens: 18279b2f3477SWeihang Li * 1. reset was initiated due to watchdog timeout caused by 1828436667d2SSalil Mehta * a. IMP was earlier reset and our TX got choked down and 1829436667d2SSalil Mehta * which resulted in watchdog reacting and inducing VF 1830436667d2SSalil Mehta * reset. This also means our cmdq would be unreliable. 1831436667d2SSalil Mehta * b. problem in TX due to other lower layer(example link 1832436667d2SSalil Mehta * layer not functioning properly etc.) 1833436667d2SSalil Mehta * 2. VF reset might have been initiated due to some config 1834436667d2SSalil Mehta * change. 1835436667d2SSalil Mehta * 1836436667d2SSalil Mehta * NOTE: Theres no clear way to detect above cases than to react 1837436667d2SSalil Mehta * to the response of PF for this reset request. PF will ack the 1838436667d2SSalil Mehta * 1b and 2. cases but we will not get any intimation about 1a 1839436667d2SSalil Mehta * from PF as cmdq would be in unreliable state i.e. mailbox 1840436667d2SSalil Mehta * communication between PF and VF would be broken. 184146ee7350SGuojia Liao * 184246ee7350SGuojia Liao * if we are never geting into pending state it means either: 1843436667d2SSalil Mehta * 1. PF is not receiving our request which could be due to IMP 1844436667d2SSalil Mehta * reset 1845436667d2SSalil Mehta * 2. PF is screwed 1846436667d2SSalil Mehta * We cannot do much for 2. but to check first we can try reset 1847436667d2SSalil Mehta * our PCIe + stack and see if it alleviates the problem. 1848436667d2SSalil Mehta */ 1849d6ad7c53SGuojia Liao if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) { 1850436667d2SSalil Mehta /* prepare for full reset of stack + pcie interface */ 1851dea846e8SHuazhong Tan set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1852436667d2SSalil Mehta 1853436667d2SSalil Mehta /* "defer" schedule the reset task again */ 1854436667d2SSalil Mehta set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1855436667d2SSalil Mehta } else { 1856436667d2SSalil Mehta hdev->reset_attempts++; 1857436667d2SSalil Mehta 1858dea846e8SHuazhong Tan set_bit(hdev->reset_level, &hdev->reset_pending); 1859dea846e8SHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1860436667d2SSalil Mehta } 1861dea846e8SHuazhong Tan hclgevf_reset_task_schedule(hdev); 1862436667d2SSalil Mehta } 186335a1e503SSalil Mehta 1864afb6afdbSHuazhong Tan hdev->reset_type = HNAE3_NONE_RESET; 186535a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1866f28368bbSHuazhong Tan up(&hdev->reset_sem); 186735a1e503SSalil Mehta } 186835a1e503SSalil Mehta 1869ff200099SYunsheng Lin static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev) 1870e2cb1decSSalil Mehta { 1871ff200099SYunsheng Lin if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state)) 1872ff200099SYunsheng Lin return; 1873e2cb1decSSalil Mehta 1874e2cb1decSSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1875e2cb1decSSalil Mehta return; 1876e2cb1decSSalil Mehta 187707a0556aSSalil Mehta hclgevf_mbx_async_handler(hdev); 1878e2cb1decSSalil Mehta 1879e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1880e2cb1decSSalil Mehta } 1881e2cb1decSSalil Mehta 1882ff200099SYunsheng Lin static void hclgevf_keep_alive(struct hclgevf_dev *hdev) 1883a6d818e3SYunsheng Lin { 1884a6d818e3SYunsheng Lin u8 respmsg; 1885a6d818e3SYunsheng Lin int ret; 1886a6d818e3SYunsheng Lin 18871416d333SHuazhong Tan if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 1888c59a85c0SJian Shen return; 1889c59a85c0SJian Shen 1890a6d818e3SYunsheng Lin ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL, 189163cbf7a9SYufeng Mo 0, false, &respmsg, sizeof(respmsg)); 1892a6d818e3SYunsheng Lin if (ret) 1893a6d818e3SYunsheng Lin dev_err(&hdev->pdev->dev, 1894a6d818e3SYunsheng Lin "VF sends keep alive cmd failed(=%d)\n", ret); 1895a6d818e3SYunsheng Lin } 1896a6d818e3SYunsheng Lin 1897ff200099SYunsheng Lin static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev) 1898e2cb1decSSalil Mehta { 1899ff200099SYunsheng Lin unsigned long delta = round_jiffies_relative(HZ); 1900ff200099SYunsheng Lin struct hnae3_handle *handle = &hdev->nic; 1901e2cb1decSSalil Mehta 1902ff200099SYunsheng Lin if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 1903ff200099SYunsheng Lin delta = jiffies - hdev->last_serv_processed; 1904db01afebSliuzhongzhu 1905ff200099SYunsheng Lin if (delta < round_jiffies_relative(HZ)) { 1906ff200099SYunsheng Lin delta = round_jiffies_relative(HZ) - delta; 1907ff200099SYunsheng Lin goto out; 1908db01afebSliuzhongzhu } 1909ff200099SYunsheng Lin } 1910ff200099SYunsheng Lin 1911ff200099SYunsheng Lin hdev->serv_processed_cnt++; 1912ff200099SYunsheng Lin if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL)) 1913ff200099SYunsheng Lin hclgevf_keep_alive(hdev); 1914ff200099SYunsheng Lin 1915ff200099SYunsheng Lin if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) { 1916ff200099SYunsheng Lin hdev->last_serv_processed = jiffies; 1917ff200099SYunsheng Lin goto out; 1918ff200099SYunsheng Lin } 1919ff200099SYunsheng Lin 1920ff200099SYunsheng Lin if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL)) 1921ff200099SYunsheng Lin hclgevf_tqps_update_stats(handle); 1922e2cb1decSSalil Mehta 1923e2cb1decSSalil Mehta /* request the link status from the PF. PF would be able to tell VF 1924e2cb1decSSalil Mehta * about such updates in future so we might remove this later 1925e2cb1decSSalil Mehta */ 1926e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1927e2cb1decSSalil Mehta 19289194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 19299194d18bSliuzhongzhu 1930fe4144d4SJian Shen hclgevf_sync_vlan_filter(hdev); 1931fe4144d4SJian Shen 1932ff200099SYunsheng Lin hdev->last_serv_processed = jiffies; 1933436667d2SSalil Mehta 1934ff200099SYunsheng Lin out: 1935ff200099SYunsheng Lin hclgevf_task_schedule(hdev, delta); 1936ff200099SYunsheng Lin } 1937b3c3fe8eSYunsheng Lin 1938ff200099SYunsheng Lin static void hclgevf_service_task(struct work_struct *work) 1939ff200099SYunsheng Lin { 1940ff200099SYunsheng Lin struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev, 1941ff200099SYunsheng Lin service_task.work); 1942ff200099SYunsheng Lin 1943ff200099SYunsheng Lin hclgevf_reset_service_task(hdev); 1944ff200099SYunsheng Lin hclgevf_mailbox_service_task(hdev); 1945ff200099SYunsheng Lin hclgevf_periodic_service_task(hdev); 1946ff200099SYunsheng Lin 1947ff200099SYunsheng Lin /* Handle reset and mbx again in case periodical task delays the 1948ff200099SYunsheng Lin * handling by calling hclgevf_task_schedule() in 1949ff200099SYunsheng Lin * hclgevf_periodic_service_task() 1950ff200099SYunsheng Lin */ 1951ff200099SYunsheng Lin hclgevf_reset_service_task(hdev); 1952ff200099SYunsheng Lin hclgevf_mailbox_service_task(hdev); 1953e2cb1decSSalil Mehta } 1954e2cb1decSSalil Mehta 1955e2cb1decSSalil Mehta static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1956e2cb1decSSalil Mehta { 1957e2cb1decSSalil Mehta hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1958e2cb1decSSalil Mehta } 1959e2cb1decSSalil Mehta 1960b90fcc5bSHuazhong Tan static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1961b90fcc5bSHuazhong Tan u32 *clearval) 1962e2cb1decSSalil Mehta { 196313050921SHuazhong Tan u32 val, cmdq_stat_reg, rst_ing_reg; 1964e2cb1decSSalil Mehta 1965e2cb1decSSalil Mehta /* fetch the events from their corresponding regs */ 196613050921SHuazhong Tan cmdq_stat_reg = hclgevf_read_dev(&hdev->hw, 196713050921SHuazhong Tan HCLGEVF_VECTOR0_CMDQ_STAT_REG); 1968e2cb1decSSalil Mehta 196913050921SHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 1970b90fcc5bSHuazhong Tan rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1971b90fcc5bSHuazhong Tan dev_info(&hdev->pdev->dev, 1972b90fcc5bSHuazhong Tan "receive reset interrupt 0x%x!\n", rst_ing_reg); 1973b90fcc5bSHuazhong Tan set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1974b90fcc5bSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1975ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 197613050921SHuazhong Tan *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B); 1977c88a6e7dSHuazhong Tan hdev->rst_stats.vf_rst_cnt++; 197872e2fb07SHuazhong Tan /* set up VF hardware reset status, its PF will clear 197972e2fb07SHuazhong Tan * this status when PF has initialized done. 198072e2fb07SHuazhong Tan */ 198172e2fb07SHuazhong Tan val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING); 198272e2fb07SHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING, 198372e2fb07SHuazhong Tan val | HCLGEVF_VF_RST_ING_BIT); 1984b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_RST; 1985b90fcc5bSHuazhong Tan } 1986b90fcc5bSHuazhong Tan 1987e2cb1decSSalil Mehta /* check for vector0 mailbox(=CMDQ RX) event source */ 198813050921SHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 198913050921SHuazhong Tan /* for revision 0x21, clearing interrupt is writing bit 0 199013050921SHuazhong Tan * to the clear register, writing bit 1 means to keep the 199113050921SHuazhong Tan * old value. 199213050921SHuazhong Tan * for revision 0x20, the clear register is a read & write 199313050921SHuazhong Tan * register, so we should just write 0 to the bit we are 199413050921SHuazhong Tan * handling, and keep other bits as cmdq_stat_reg. 199513050921SHuazhong Tan */ 199613050921SHuazhong Tan if (hdev->pdev->revision >= 0x21) 199713050921SHuazhong Tan *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 199813050921SHuazhong Tan else 199913050921SHuazhong Tan *clearval = cmdq_stat_reg & 200013050921SHuazhong Tan ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 200113050921SHuazhong Tan 2002b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_MBX; 2003e2cb1decSSalil Mehta } 2004e2cb1decSSalil Mehta 2005e2cb1decSSalil Mehta dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 2006e2cb1decSSalil Mehta 2007b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_OTHER; 2008e2cb1decSSalil Mehta } 2009e2cb1decSSalil Mehta 2010e2cb1decSSalil Mehta static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 2011e2cb1decSSalil Mehta { 2012b90fcc5bSHuazhong Tan enum hclgevf_evt_cause event_cause; 2013e2cb1decSSalil Mehta struct hclgevf_dev *hdev = data; 2014e2cb1decSSalil Mehta u32 clearval; 2015e2cb1decSSalil Mehta 2016e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 2017b90fcc5bSHuazhong Tan event_cause = hclgevf_check_evt_cause(hdev, &clearval); 2018e2cb1decSSalil Mehta 2019b90fcc5bSHuazhong Tan switch (event_cause) { 2020b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_RST: 2021b90fcc5bSHuazhong Tan hclgevf_reset_task_schedule(hdev); 2022b90fcc5bSHuazhong Tan break; 2023b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_MBX: 202407a0556aSSalil Mehta hclgevf_mbx_handler(hdev); 2025b90fcc5bSHuazhong Tan break; 2026b90fcc5bSHuazhong Tan default: 2027b90fcc5bSHuazhong Tan break; 2028b90fcc5bSHuazhong Tan } 2029e2cb1decSSalil Mehta 2030b90fcc5bSHuazhong Tan if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 2031e2cb1decSSalil Mehta hclgevf_clear_event_cause(hdev, clearval); 2032e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2033b90fcc5bSHuazhong Tan } 2034e2cb1decSSalil Mehta 2035e2cb1decSSalil Mehta return IRQ_HANDLED; 2036e2cb1decSSalil Mehta } 2037e2cb1decSSalil Mehta 2038e2cb1decSSalil Mehta static int hclgevf_configure(struct hclgevf_dev *hdev) 2039e2cb1decSSalil Mehta { 2040e2cb1decSSalil Mehta int ret; 2041e2cb1decSSalil Mehta 204292f11ea1SJian Shen /* get current port based vlan state from PF */ 204392f11ea1SJian Shen ret = hclgevf_get_port_base_vlan_filter_state(hdev); 204492f11ea1SJian Shen if (ret) 204592f11ea1SJian Shen return ret; 204692f11ea1SJian Shen 2047e2cb1decSSalil Mehta /* get queue configuration from PF */ 20486cee6fc3SJian Shen ret = hclgevf_get_queue_info(hdev); 2049e2cb1decSSalil Mehta if (ret) 2050e2cb1decSSalil Mehta return ret; 2051c0425944SPeng Li 2052c0425944SPeng Li /* get queue depth info from PF */ 2053c0425944SPeng Li ret = hclgevf_get_queue_depth(hdev); 2054c0425944SPeng Li if (ret) 2055c0425944SPeng Li return ret; 2056c0425944SPeng Li 20579c3e7130Sliuzhongzhu ret = hclgevf_get_pf_media_type(hdev); 20589c3e7130Sliuzhongzhu if (ret) 20599c3e7130Sliuzhongzhu return ret; 20609c3e7130Sliuzhongzhu 2061e2cb1decSSalil Mehta /* get tc configuration from PF */ 2062e2cb1decSSalil Mehta return hclgevf_get_tc_info(hdev); 2063e2cb1decSSalil Mehta } 2064e2cb1decSSalil Mehta 20657a01c897SSalil Mehta static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 20667a01c897SSalil Mehta { 20677a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 20681154bb26SPeng Li struct hclgevf_dev *hdev; 20697a01c897SSalil Mehta 20707a01c897SSalil Mehta hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 20717a01c897SSalil Mehta if (!hdev) 20727a01c897SSalil Mehta return -ENOMEM; 20737a01c897SSalil Mehta 20747a01c897SSalil Mehta hdev->pdev = pdev; 20757a01c897SSalil Mehta hdev->ae_dev = ae_dev; 20767a01c897SSalil Mehta ae_dev->priv = hdev; 20777a01c897SSalil Mehta 20787a01c897SSalil Mehta return 0; 20797a01c897SSalil Mehta } 20807a01c897SSalil Mehta 2081e2cb1decSSalil Mehta static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 2082e2cb1decSSalil Mehta { 2083e2cb1decSSalil Mehta struct hnae3_handle *roce = &hdev->roce; 2084e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 2085e2cb1decSSalil Mehta 208607acf909SJian Shen roce->rinfo.num_vectors = hdev->num_roce_msix; 2087e2cb1decSSalil Mehta 2088e2cb1decSSalil Mehta if (hdev->num_msi_left < roce->rinfo.num_vectors || 2089e2cb1decSSalil Mehta hdev->num_msi_left == 0) 2090e2cb1decSSalil Mehta return -EINVAL; 2091e2cb1decSSalil Mehta 209207acf909SJian Shen roce->rinfo.base_vector = hdev->roce_base_vector; 2093e2cb1decSSalil Mehta 2094e2cb1decSSalil Mehta roce->rinfo.netdev = nic->kinfo.netdev; 2095e2cb1decSSalil Mehta roce->rinfo.roce_io_base = hdev->hw.io_base; 2096e2cb1decSSalil Mehta 2097e2cb1decSSalil Mehta roce->pdev = nic->pdev; 2098e2cb1decSSalil Mehta roce->ae_algo = nic->ae_algo; 2099e2cb1decSSalil Mehta roce->numa_node_mask = nic->numa_node_mask; 2100e2cb1decSSalil Mehta 2101e2cb1decSSalil Mehta return 0; 2102e2cb1decSSalil Mehta } 2103e2cb1decSSalil Mehta 2104b26a6feaSPeng Li static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 2105b26a6feaSPeng Li { 2106b26a6feaSPeng Li struct hclgevf_cfg_gro_status_cmd *req; 2107b26a6feaSPeng Li struct hclgevf_desc desc; 2108b26a6feaSPeng Li int ret; 2109b26a6feaSPeng Li 2110b26a6feaSPeng Li if (!hnae3_dev_gro_supported(hdev)) 2111b26a6feaSPeng Li return 0; 2112b26a6feaSPeng Li 2113b26a6feaSPeng Li hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 2114b26a6feaSPeng Li false); 2115b26a6feaSPeng Li req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2116b26a6feaSPeng Li 2117b26a6feaSPeng Li req->gro_en = cpu_to_le16(en ? 1 : 0); 2118b26a6feaSPeng Li 2119b26a6feaSPeng Li ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2120b26a6feaSPeng Li if (ret) 2121b26a6feaSPeng Li dev_err(&hdev->pdev->dev, 2122b26a6feaSPeng Li "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2123b26a6feaSPeng Li 2124b26a6feaSPeng Li return ret; 2125b26a6feaSPeng Li } 2126b26a6feaSPeng Li 2127e2cb1decSSalil Mehta static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2128e2cb1decSSalil Mehta { 2129e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 21304093d1a2SGuangbin Huang int ret; 21314093d1a2SGuangbin Huang u32 i; 2132e2cb1decSSalil Mehta 21334093d1a2SGuangbin Huang rss_cfg->rss_size = hdev->nic.kinfo.rss_size; 2134e2cb1decSSalil Mehta 2135374ad291SJian Shen if (hdev->pdev->revision >= 0x21) { 2136472d7eceSJian Shen rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 2137472d7eceSJian Shen memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 2138374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 2139374ad291SJian Shen 2140374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 2141374ad291SJian Shen rss_cfg->rss_hash_key); 2142374ad291SJian Shen if (ret) 2143374ad291SJian Shen return ret; 2144d97b3072SJian Shen 2145d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = 2146d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2147d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = 2148d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2149d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = 2150d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2151d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = 2152d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2153d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = 2154d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2155d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = 2156d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2157d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = 2158d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2159d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = 2160d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2161d97b3072SJian Shen 2162d97b3072SJian Shen ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 2163d97b3072SJian Shen if (ret) 2164d97b3072SJian Shen return ret; 2165374ad291SJian Shen } 2166374ad291SJian Shen 21679b2f3477SWeihang Li /* Initialize RSS indirect table */ 2168e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 21694093d1a2SGuangbin Huang rss_cfg->rss_indirection_tbl[i] = i % rss_cfg->rss_size; 2170e2cb1decSSalil Mehta 2171e2cb1decSSalil Mehta ret = hclgevf_set_rss_indir_table(hdev); 2172e2cb1decSSalil Mehta if (ret) 2173e2cb1decSSalil Mehta return ret; 2174e2cb1decSSalil Mehta 21754093d1a2SGuangbin Huang return hclgevf_set_rss_tc_mode(hdev, rss_cfg->rss_size); 2176e2cb1decSSalil Mehta } 2177e2cb1decSSalil Mehta 2178e2cb1decSSalil Mehta static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2179e2cb1decSSalil Mehta { 2180e2cb1decSSalil Mehta return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2181e2cb1decSSalil Mehta false); 2182e2cb1decSSalil Mehta } 2183e2cb1decSSalil Mehta 2184ff200099SYunsheng Lin static void hclgevf_flush_link_update(struct hclgevf_dev *hdev) 2185ff200099SYunsheng Lin { 2186ff200099SYunsheng Lin #define HCLGEVF_FLUSH_LINK_TIMEOUT 100000 2187ff200099SYunsheng Lin 2188ff200099SYunsheng Lin unsigned long last = hdev->serv_processed_cnt; 2189ff200099SYunsheng Lin int i = 0; 2190ff200099SYunsheng Lin 2191ff200099SYunsheng Lin while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) && 2192ff200099SYunsheng Lin i++ < HCLGEVF_FLUSH_LINK_TIMEOUT && 2193ff200099SYunsheng Lin last == hdev->serv_processed_cnt) 2194ff200099SYunsheng Lin usleep_range(1, 1); 2195ff200099SYunsheng Lin } 2196ff200099SYunsheng Lin 21978cdb992fSJian Shen static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 21988cdb992fSJian Shen { 21998cdb992fSJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 22008cdb992fSJian Shen 22018cdb992fSJian Shen if (enable) { 2202ff200099SYunsheng Lin hclgevf_task_schedule(hdev, 0); 22038cdb992fSJian Shen } else { 2204b3c3fe8eSYunsheng Lin set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2205ff200099SYunsheng Lin 2206ff200099SYunsheng Lin /* flush memory to make sure DOWN is seen by service task */ 2207ff200099SYunsheng Lin smp_mb__before_atomic(); 2208ff200099SYunsheng Lin hclgevf_flush_link_update(hdev); 22098cdb992fSJian Shen } 22108cdb992fSJian Shen } 22118cdb992fSJian Shen 2212e2cb1decSSalil Mehta static int hclgevf_ae_start(struct hnae3_handle *handle) 2213e2cb1decSSalil Mehta { 2214e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2215e2cb1decSSalil Mehta 2216e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 2217e2cb1decSSalil Mehta 2218e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 2219e2cb1decSSalil Mehta 22209194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 22219194d18bSliuzhongzhu 2222e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2223e2cb1decSSalil Mehta 2224e2cb1decSSalil Mehta return 0; 2225e2cb1decSSalil Mehta } 2226e2cb1decSSalil Mehta 2227e2cb1decSSalil Mehta static void hclgevf_ae_stop(struct hnae3_handle *handle) 2228e2cb1decSSalil Mehta { 2229e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 223039cfbc9cSHuazhong Tan int i; 2231e2cb1decSSalil Mehta 22322f7e4896SFuyun Liang set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 22332f7e4896SFuyun Liang 2234146e92c1SHuazhong Tan if (hdev->reset_type != HNAE3_VF_RESET) 223539cfbc9cSHuazhong Tan for (i = 0; i < handle->kinfo.num_tqps; i++) 2236146e92c1SHuazhong Tan if (hclgevf_reset_tqp(handle, i)) 2237146e92c1SHuazhong Tan break; 223839cfbc9cSHuazhong Tan 2239e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 22408cc6c1f7SFuyun Liang hclgevf_update_link_status(hdev, 0); 2241e2cb1decSSalil Mehta } 2242e2cb1decSSalil Mehta 2243a6d818e3SYunsheng Lin static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2244a6d818e3SYunsheng Lin { 2245a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2246a6d818e3SYunsheng Lin u8 msg_data; 2247a6d818e3SYunsheng Lin 2248a6d818e3SYunsheng Lin msg_data = alive ? 1 : 0; 2249a6d818e3SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE, 2250a6d818e3SYunsheng Lin 0, &msg_data, 1, false, NULL, 0); 2251a6d818e3SYunsheng Lin } 2252a6d818e3SYunsheng Lin 2253a6d818e3SYunsheng Lin static int hclgevf_client_start(struct hnae3_handle *handle) 2254a6d818e3SYunsheng Lin { 2255e233516eSHuazhong Tan int ret; 2256e233516eSHuazhong Tan 2257e233516eSHuazhong Tan ret = hclgevf_set_alive(handle, true); 2258e233516eSHuazhong Tan if (ret) 2259e233516eSHuazhong Tan return ret; 2260a6d818e3SYunsheng Lin 2261e233516eSHuazhong Tan return 0; 2262a6d818e3SYunsheng Lin } 2263a6d818e3SYunsheng Lin 2264a6d818e3SYunsheng Lin static void hclgevf_client_stop(struct hnae3_handle *handle) 2265a6d818e3SYunsheng Lin { 2266a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2267a6d818e3SYunsheng Lin int ret; 2268a6d818e3SYunsheng Lin 2269a6d818e3SYunsheng Lin ret = hclgevf_set_alive(handle, false); 2270a6d818e3SYunsheng Lin if (ret) 2271a6d818e3SYunsheng Lin dev_warn(&hdev->pdev->dev, 2272a6d818e3SYunsheng Lin "%s failed %d\n", __func__, ret); 2273a6d818e3SYunsheng Lin } 2274a6d818e3SYunsheng Lin 2275e2cb1decSSalil Mehta static void hclgevf_state_init(struct hclgevf_dev *hdev) 2276e2cb1decSSalil Mehta { 2277e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2278e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2279d5432455SGuojia Liao clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 2280e2cb1decSSalil Mehta 2281b3c3fe8eSYunsheng Lin INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task); 228235a1e503SSalil Mehta 2283e2cb1decSSalil Mehta mutex_init(&hdev->mbx_resp.mbx_mutex); 2284f28368bbSHuazhong Tan sema_init(&hdev->reset_sem, 1); 2285e2cb1decSSalil Mehta 2286e2cb1decSSalil Mehta /* bring the device down */ 2287e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2288e2cb1decSSalil Mehta } 2289e2cb1decSSalil Mehta 2290e2cb1decSSalil Mehta static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2291e2cb1decSSalil Mehta { 2292e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2293acfc3d55SHuazhong Tan set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2294e2cb1decSSalil Mehta 2295b3c3fe8eSYunsheng Lin if (hdev->service_task.work.func) 2296b3c3fe8eSYunsheng Lin cancel_delayed_work_sync(&hdev->service_task); 2297e2cb1decSSalil Mehta 2298e2cb1decSSalil Mehta mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2299e2cb1decSSalil Mehta } 2300e2cb1decSSalil Mehta 2301e2cb1decSSalil Mehta static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2302e2cb1decSSalil Mehta { 2303e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2304e2cb1decSSalil Mehta int vectors; 2305e2cb1decSSalil Mehta int i; 2306e2cb1decSSalil Mehta 2307580a05f9SYonglong Liu if (hnae3_dev_roce_supported(hdev)) 230807acf909SJian Shen vectors = pci_alloc_irq_vectors(pdev, 230907acf909SJian Shen hdev->roce_base_msix_offset + 1, 231007acf909SJian Shen hdev->num_msi, 231107acf909SJian Shen PCI_IRQ_MSIX); 231207acf909SJian Shen else 2313580a05f9SYonglong Liu vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2314580a05f9SYonglong Liu hdev->num_msi, 2315e2cb1decSSalil Mehta PCI_IRQ_MSI | PCI_IRQ_MSIX); 231607acf909SJian Shen 2317e2cb1decSSalil Mehta if (vectors < 0) { 2318e2cb1decSSalil Mehta dev_err(&pdev->dev, 2319e2cb1decSSalil Mehta "failed(%d) to allocate MSI/MSI-X vectors\n", 2320e2cb1decSSalil Mehta vectors); 2321e2cb1decSSalil Mehta return vectors; 2322e2cb1decSSalil Mehta } 2323e2cb1decSSalil Mehta if (vectors < hdev->num_msi) 2324e2cb1decSSalil Mehta dev_warn(&hdev->pdev->dev, 2325adcf738bSGuojia Liao "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2326e2cb1decSSalil Mehta hdev->num_msi, vectors); 2327e2cb1decSSalil Mehta 2328e2cb1decSSalil Mehta hdev->num_msi = vectors; 2329e2cb1decSSalil Mehta hdev->num_msi_left = vectors; 2330580a05f9SYonglong Liu 2331e2cb1decSSalil Mehta hdev->base_msi_vector = pdev->irq; 233207acf909SJian Shen hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2333e2cb1decSSalil Mehta 2334e2cb1decSSalil Mehta hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2335e2cb1decSSalil Mehta sizeof(u16), GFP_KERNEL); 2336e2cb1decSSalil Mehta if (!hdev->vector_status) { 2337e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2338e2cb1decSSalil Mehta return -ENOMEM; 2339e2cb1decSSalil Mehta } 2340e2cb1decSSalil Mehta 2341e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 2342e2cb1decSSalil Mehta hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2343e2cb1decSSalil Mehta 2344e2cb1decSSalil Mehta hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2345e2cb1decSSalil Mehta sizeof(int), GFP_KERNEL); 2346e2cb1decSSalil Mehta if (!hdev->vector_irq) { 2347862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2348e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2349e2cb1decSSalil Mehta return -ENOMEM; 2350e2cb1decSSalil Mehta } 2351e2cb1decSSalil Mehta 2352e2cb1decSSalil Mehta return 0; 2353e2cb1decSSalil Mehta } 2354e2cb1decSSalil Mehta 2355e2cb1decSSalil Mehta static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2356e2cb1decSSalil Mehta { 2357e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2358e2cb1decSSalil Mehta 2359862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2360862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_irq); 2361e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2362e2cb1decSSalil Mehta } 2363e2cb1decSSalil Mehta 2364e2cb1decSSalil Mehta static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2365e2cb1decSSalil Mehta { 2366cdd332acSGuojia Liao int ret; 2367e2cb1decSSalil Mehta 2368e2cb1decSSalil Mehta hclgevf_get_misc_vector(hdev); 2369e2cb1decSSalil Mehta 2370f97c4d82SYonglong Liu snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 2371f97c4d82SYonglong Liu HCLGEVF_NAME, pci_name(hdev->pdev)); 2372e2cb1decSSalil Mehta ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2373f97c4d82SYonglong Liu 0, hdev->misc_vector.name, hdev); 2374e2cb1decSSalil Mehta if (ret) { 2375e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2376e2cb1decSSalil Mehta hdev->misc_vector.vector_irq); 2377e2cb1decSSalil Mehta return ret; 2378e2cb1decSSalil Mehta } 2379e2cb1decSSalil Mehta 23801819e409SXi Wang hclgevf_clear_event_cause(hdev, 0); 23811819e409SXi Wang 2382e2cb1decSSalil Mehta /* enable misc. vector(vector 0) */ 2383e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2384e2cb1decSSalil Mehta 2385e2cb1decSSalil Mehta return ret; 2386e2cb1decSSalil Mehta } 2387e2cb1decSSalil Mehta 2388e2cb1decSSalil Mehta static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2389e2cb1decSSalil Mehta { 2390e2cb1decSSalil Mehta /* disable misc vector(vector 0) */ 2391e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 23921819e409SXi Wang synchronize_irq(hdev->misc_vector.vector_irq); 2393e2cb1decSSalil Mehta free_irq(hdev->misc_vector.vector_irq, hdev); 2394e2cb1decSSalil Mehta hclgevf_free_vector(hdev, 0); 2395e2cb1decSSalil Mehta } 2396e2cb1decSSalil Mehta 2397bb87be87SYonglong Liu static void hclgevf_info_show(struct hclgevf_dev *hdev) 2398bb87be87SYonglong Liu { 2399bb87be87SYonglong Liu struct device *dev = &hdev->pdev->dev; 2400bb87be87SYonglong Liu 2401bb87be87SYonglong Liu dev_info(dev, "VF info begin:\n"); 2402bb87be87SYonglong Liu 2403adcf738bSGuojia Liao dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 2404adcf738bSGuojia Liao dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 2405adcf738bSGuojia Liao dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 2406adcf738bSGuojia Liao dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 2407adcf738bSGuojia Liao dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 2408adcf738bSGuojia Liao dev_info(dev, "PF media type of this VF: %u\n", 2409bb87be87SYonglong Liu hdev->hw.mac.media_type); 2410bb87be87SYonglong Liu 2411bb87be87SYonglong Liu dev_info(dev, "VF info end.\n"); 2412bb87be87SYonglong Liu } 2413bb87be87SYonglong Liu 24141db58f86SHuazhong Tan static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 24151db58f86SHuazhong Tan struct hnae3_client *client) 24161db58f86SHuazhong Tan { 24171db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 24181db58f86SHuazhong Tan int ret; 24191db58f86SHuazhong Tan 24201db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->nic); 24211db58f86SHuazhong Tan if (ret) 24221db58f86SHuazhong Tan return ret; 24231db58f86SHuazhong Tan 24241db58f86SHuazhong Tan set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 24251db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 24261db58f86SHuazhong Tan 24271db58f86SHuazhong Tan if (netif_msg_drv(&hdev->nic)) 24281db58f86SHuazhong Tan hclgevf_info_show(hdev); 24291db58f86SHuazhong Tan 24301db58f86SHuazhong Tan return 0; 24311db58f86SHuazhong Tan } 24321db58f86SHuazhong Tan 24331db58f86SHuazhong Tan static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 24341db58f86SHuazhong Tan struct hnae3_client *client) 24351db58f86SHuazhong Tan { 24361db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 24371db58f86SHuazhong Tan int ret; 24381db58f86SHuazhong Tan 24391db58f86SHuazhong Tan if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 24401db58f86SHuazhong Tan !hdev->nic_client) 24411db58f86SHuazhong Tan return 0; 24421db58f86SHuazhong Tan 24431db58f86SHuazhong Tan ret = hclgevf_init_roce_base_info(hdev); 24441db58f86SHuazhong Tan if (ret) 24451db58f86SHuazhong Tan return ret; 24461db58f86SHuazhong Tan 24471db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->roce); 24481db58f86SHuazhong Tan if (ret) 24491db58f86SHuazhong Tan return ret; 24501db58f86SHuazhong Tan 24511db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 24521db58f86SHuazhong Tan 24531db58f86SHuazhong Tan return 0; 24541db58f86SHuazhong Tan } 24551db58f86SHuazhong Tan 2456e718a93fSPeng Li static int hclgevf_init_client_instance(struct hnae3_client *client, 2457e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2458e2cb1decSSalil Mehta { 2459e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2460e2cb1decSSalil Mehta int ret; 2461e2cb1decSSalil Mehta 2462e2cb1decSSalil Mehta switch (client->type) { 2463e2cb1decSSalil Mehta case HNAE3_CLIENT_KNIC: 2464e2cb1decSSalil Mehta hdev->nic_client = client; 2465e2cb1decSSalil Mehta hdev->nic.client = client; 2466e2cb1decSSalil Mehta 24671db58f86SHuazhong Tan ret = hclgevf_init_nic_client_instance(ae_dev, client); 2468e2cb1decSSalil Mehta if (ret) 246949dd8054SJian Shen goto clear_nic; 2470e2cb1decSSalil Mehta 24711db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, 24721db58f86SHuazhong Tan hdev->roce_client); 2473e2cb1decSSalil Mehta if (ret) 247449dd8054SJian Shen goto clear_roce; 2475d9f28fc2SJian Shen 2476e2cb1decSSalil Mehta break; 2477e2cb1decSSalil Mehta case HNAE3_CLIENT_ROCE: 2478544a7bcdSLijun Ou if (hnae3_dev_roce_supported(hdev)) { 2479e2cb1decSSalil Mehta hdev->roce_client = client; 2480e2cb1decSSalil Mehta hdev->roce.client = client; 2481544a7bcdSLijun Ou } 2482e2cb1decSSalil Mehta 24831db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, client); 2484e2cb1decSSalil Mehta if (ret) 248549dd8054SJian Shen goto clear_roce; 2486e2cb1decSSalil Mehta 2487fa7a4bd5SJian Shen break; 2488fa7a4bd5SJian Shen default: 2489fa7a4bd5SJian Shen return -EINVAL; 2490e2cb1decSSalil Mehta } 2491e2cb1decSSalil Mehta 2492e2cb1decSSalil Mehta return 0; 249349dd8054SJian Shen 249449dd8054SJian Shen clear_nic: 249549dd8054SJian Shen hdev->nic_client = NULL; 249649dd8054SJian Shen hdev->nic.client = NULL; 249749dd8054SJian Shen return ret; 249849dd8054SJian Shen clear_roce: 249949dd8054SJian Shen hdev->roce_client = NULL; 250049dd8054SJian Shen hdev->roce.client = NULL; 250149dd8054SJian Shen return ret; 2502e2cb1decSSalil Mehta } 2503e2cb1decSSalil Mehta 2504e718a93fSPeng Li static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2505e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2506e2cb1decSSalil Mehta { 2507e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2508e718a93fSPeng Li 2509e2cb1decSSalil Mehta /* un-init roce, if it exists */ 251049dd8054SJian Shen if (hdev->roce_client) { 2511e2cb1decSSalil Mehta hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 251249dd8054SJian Shen hdev->roce_client = NULL; 251349dd8054SJian Shen hdev->roce.client = NULL; 251449dd8054SJian Shen } 2515e2cb1decSSalil Mehta 2516e2cb1decSSalil Mehta /* un-init nic/unic, if this was not called by roce client */ 251749dd8054SJian Shen if (client->ops->uninit_instance && hdev->nic_client && 251849dd8054SJian Shen client->type != HNAE3_CLIENT_ROCE) { 251925d1817cSHuazhong Tan clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 252025d1817cSHuazhong Tan 2521e2cb1decSSalil Mehta client->ops->uninit_instance(&hdev->nic, 0); 252249dd8054SJian Shen hdev->nic_client = NULL; 252349dd8054SJian Shen hdev->nic.client = NULL; 252449dd8054SJian Shen } 2525e2cb1decSSalil Mehta } 2526e2cb1decSSalil Mehta 2527e2cb1decSSalil Mehta static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2528e2cb1decSSalil Mehta { 2529e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2530e2cb1decSSalil Mehta struct hclgevf_hw *hw; 2531e2cb1decSSalil Mehta int ret; 2532e2cb1decSSalil Mehta 2533e2cb1decSSalil Mehta ret = pci_enable_device(pdev); 2534e2cb1decSSalil Mehta if (ret) { 2535e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed to enable PCI device\n"); 25363e249d3bSFuyun Liang return ret; 2537e2cb1decSSalil Mehta } 2538e2cb1decSSalil Mehta 2539e2cb1decSSalil Mehta ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2540e2cb1decSSalil Mehta if (ret) { 2541e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2542e2cb1decSSalil Mehta goto err_disable_device; 2543e2cb1decSSalil Mehta } 2544e2cb1decSSalil Mehta 2545e2cb1decSSalil Mehta ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2546e2cb1decSSalil Mehta if (ret) { 2547e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2548e2cb1decSSalil Mehta goto err_disable_device; 2549e2cb1decSSalil Mehta } 2550e2cb1decSSalil Mehta 2551e2cb1decSSalil Mehta pci_set_master(pdev); 2552e2cb1decSSalil Mehta hw = &hdev->hw; 2553e2cb1decSSalil Mehta hw->hdev = hdev; 25542e1ea493SPeng Li hw->io_base = pci_iomap(pdev, 2, 0); 2555e2cb1decSSalil Mehta if (!hw->io_base) { 2556e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't map configuration register space\n"); 2557e2cb1decSSalil Mehta ret = -ENOMEM; 2558e2cb1decSSalil Mehta goto err_clr_master; 2559e2cb1decSSalil Mehta } 2560e2cb1decSSalil Mehta 2561e2cb1decSSalil Mehta return 0; 2562e2cb1decSSalil Mehta 2563e2cb1decSSalil Mehta err_clr_master: 2564e2cb1decSSalil Mehta pci_clear_master(pdev); 2565e2cb1decSSalil Mehta pci_release_regions(pdev); 2566e2cb1decSSalil Mehta err_disable_device: 2567e2cb1decSSalil Mehta pci_disable_device(pdev); 25683e249d3bSFuyun Liang 2569e2cb1decSSalil Mehta return ret; 2570e2cb1decSSalil Mehta } 2571e2cb1decSSalil Mehta 2572e2cb1decSSalil Mehta static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2573e2cb1decSSalil Mehta { 2574e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2575e2cb1decSSalil Mehta 2576e2cb1decSSalil Mehta pci_iounmap(pdev, hdev->hw.io_base); 2577e2cb1decSSalil Mehta pci_clear_master(pdev); 2578e2cb1decSSalil Mehta pci_release_regions(pdev); 2579e2cb1decSSalil Mehta pci_disable_device(pdev); 2580e2cb1decSSalil Mehta } 2581e2cb1decSSalil Mehta 258207acf909SJian Shen static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 258307acf909SJian Shen { 258407acf909SJian Shen struct hclgevf_query_res_cmd *req; 258507acf909SJian Shen struct hclgevf_desc desc; 258607acf909SJian Shen int ret; 258707acf909SJian Shen 258807acf909SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 258907acf909SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 259007acf909SJian Shen if (ret) { 259107acf909SJian Shen dev_err(&hdev->pdev->dev, 259207acf909SJian Shen "query vf resource failed, ret = %d.\n", ret); 259307acf909SJian Shen return ret; 259407acf909SJian Shen } 259507acf909SJian Shen 259607acf909SJian Shen req = (struct hclgevf_query_res_cmd *)desc.data; 259707acf909SJian Shen 2598580a05f9SYonglong Liu if (hnae3_dev_roce_supported(hdev)) { 259907acf909SJian Shen hdev->roce_base_msix_offset = 260060df7e91SHuazhong Tan hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee), 260107acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_M, 260207acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_S); 260307acf909SJian Shen hdev->num_roce_msix = 260460df7e91SHuazhong Tan hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 260507acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 260607acf909SJian Shen 2607580a05f9SYonglong Liu /* nic's msix numbers is always equals to the roce's. */ 2608580a05f9SYonglong Liu hdev->num_nic_msix = hdev->num_roce_msix; 2609580a05f9SYonglong Liu 261007acf909SJian Shen /* VF should have NIC vectors and Roce vectors, NIC vectors 261107acf909SJian Shen * are queued before Roce vectors. The offset is fixed to 64. 261207acf909SJian Shen */ 261307acf909SJian Shen hdev->num_msi = hdev->num_roce_msix + 261407acf909SJian Shen hdev->roce_base_msix_offset; 261507acf909SJian Shen } else { 261607acf909SJian Shen hdev->num_msi = 261760df7e91SHuazhong Tan hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 261807acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2619580a05f9SYonglong Liu 2620580a05f9SYonglong Liu hdev->num_nic_msix = hdev->num_msi; 2621580a05f9SYonglong Liu } 2622580a05f9SYonglong Liu 2623580a05f9SYonglong Liu if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) { 2624580a05f9SYonglong Liu dev_err(&hdev->pdev->dev, 2625580a05f9SYonglong Liu "Just %u msi resources, not enough for vf(min:2).\n", 2626580a05f9SYonglong Liu hdev->num_nic_msix); 2627580a05f9SYonglong Liu return -EINVAL; 262807acf909SJian Shen } 262907acf909SJian Shen 263007acf909SJian Shen return 0; 263107acf909SJian Shen } 263207acf909SJian Shen 2633862d969aSHuazhong Tan static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2634862d969aSHuazhong Tan { 2635862d969aSHuazhong Tan struct pci_dev *pdev = hdev->pdev; 2636862d969aSHuazhong Tan int ret = 0; 2637862d969aSHuazhong Tan 2638862d969aSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2639862d969aSHuazhong Tan test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2640862d969aSHuazhong Tan hclgevf_misc_irq_uninit(hdev); 2641862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2642862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2643862d969aSHuazhong Tan } 2644862d969aSHuazhong Tan 2645862d969aSHuazhong Tan if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2646862d969aSHuazhong Tan pci_set_master(pdev); 2647862d969aSHuazhong Tan ret = hclgevf_init_msi(hdev); 2648862d969aSHuazhong Tan if (ret) { 2649862d969aSHuazhong Tan dev_err(&pdev->dev, 2650862d969aSHuazhong Tan "failed(%d) to init MSI/MSI-X\n", ret); 2651862d969aSHuazhong Tan return ret; 2652862d969aSHuazhong Tan } 2653862d969aSHuazhong Tan 2654862d969aSHuazhong Tan ret = hclgevf_misc_irq_init(hdev); 2655862d969aSHuazhong Tan if (ret) { 2656862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2657862d969aSHuazhong Tan dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2658862d969aSHuazhong Tan ret); 2659862d969aSHuazhong Tan return ret; 2660862d969aSHuazhong Tan } 2661862d969aSHuazhong Tan 2662862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2663862d969aSHuazhong Tan } 2664862d969aSHuazhong Tan 2665862d969aSHuazhong Tan return ret; 2666862d969aSHuazhong Tan } 2667862d969aSHuazhong Tan 26689c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2669e2cb1decSSalil Mehta { 26707a01c897SSalil Mehta struct pci_dev *pdev = hdev->pdev; 2671e2cb1decSSalil Mehta int ret; 2672e2cb1decSSalil Mehta 2673862d969aSHuazhong Tan ret = hclgevf_pci_reset(hdev); 2674862d969aSHuazhong Tan if (ret) { 2675862d969aSHuazhong Tan dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2676862d969aSHuazhong Tan return ret; 2677862d969aSHuazhong Tan } 2678862d969aSHuazhong Tan 26799c6f7085SHuazhong Tan ret = hclgevf_cmd_init(hdev); 26809c6f7085SHuazhong Tan if (ret) { 26819c6f7085SHuazhong Tan dev_err(&pdev->dev, "cmd failed %d\n", ret); 26829c6f7085SHuazhong Tan return ret; 26837a01c897SSalil Mehta } 2684e2cb1decSSalil Mehta 26859c6f7085SHuazhong Tan ret = hclgevf_rss_init_hw(hdev); 26869c6f7085SHuazhong Tan if (ret) { 26879c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 26889c6f7085SHuazhong Tan "failed(%d) to initialize RSS\n", ret); 26899c6f7085SHuazhong Tan return ret; 26909c6f7085SHuazhong Tan } 26919c6f7085SHuazhong Tan 2692b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2693b26a6feaSPeng Li if (ret) 2694b26a6feaSPeng Li return ret; 2695b26a6feaSPeng Li 26969c6f7085SHuazhong Tan ret = hclgevf_init_vlan_config(hdev); 26979c6f7085SHuazhong Tan if (ret) { 26989c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 26999c6f7085SHuazhong Tan "failed(%d) to initialize VLAN config\n", ret); 27009c6f7085SHuazhong Tan return ret; 27019c6f7085SHuazhong Tan } 27029c6f7085SHuazhong Tan 27039c6f7085SHuazhong Tan dev_info(&hdev->pdev->dev, "Reset done\n"); 27049c6f7085SHuazhong Tan 27059c6f7085SHuazhong Tan return 0; 27069c6f7085SHuazhong Tan } 27079c6f7085SHuazhong Tan 27089c6f7085SHuazhong Tan static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 27099c6f7085SHuazhong Tan { 27109c6f7085SHuazhong Tan struct pci_dev *pdev = hdev->pdev; 27119c6f7085SHuazhong Tan int ret; 27129c6f7085SHuazhong Tan 2713e2cb1decSSalil Mehta ret = hclgevf_pci_init(hdev); 271460df7e91SHuazhong Tan if (ret) 2715e2cb1decSSalil Mehta return ret; 2716e2cb1decSSalil Mehta 27178b0195a3SHuazhong Tan ret = hclgevf_cmd_queue_init(hdev); 271860df7e91SHuazhong Tan if (ret) 27198b0195a3SHuazhong Tan goto err_cmd_queue_init; 27208b0195a3SHuazhong Tan 2721eddf0462SYunsheng Lin ret = hclgevf_cmd_init(hdev); 2722eddf0462SYunsheng Lin if (ret) 2723eddf0462SYunsheng Lin goto err_cmd_init; 2724eddf0462SYunsheng Lin 272507acf909SJian Shen /* Get vf resource */ 272607acf909SJian Shen ret = hclgevf_query_vf_resource(hdev); 272760df7e91SHuazhong Tan if (ret) 27288b0195a3SHuazhong Tan goto err_cmd_init; 272907acf909SJian Shen 273007acf909SJian Shen ret = hclgevf_init_msi(hdev); 273107acf909SJian Shen if (ret) { 273207acf909SJian Shen dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 27338b0195a3SHuazhong Tan goto err_cmd_init; 273407acf909SJian Shen } 273507acf909SJian Shen 273607acf909SJian Shen hclgevf_state_init(hdev); 2737dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 2738afb6afdbSHuazhong Tan hdev->reset_type = HNAE3_NONE_RESET; 273907acf909SJian Shen 2740e2cb1decSSalil Mehta ret = hclgevf_misc_irq_init(hdev); 274160df7e91SHuazhong Tan if (ret) 2742e2cb1decSSalil Mehta goto err_misc_irq_init; 2743e2cb1decSSalil Mehta 2744862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2745862d969aSHuazhong Tan 2746e2cb1decSSalil Mehta ret = hclgevf_configure(hdev); 2747e2cb1decSSalil Mehta if (ret) { 2748e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2749e2cb1decSSalil Mehta goto err_config; 2750e2cb1decSSalil Mehta } 2751e2cb1decSSalil Mehta 2752e2cb1decSSalil Mehta ret = hclgevf_alloc_tqps(hdev); 2753e2cb1decSSalil Mehta if (ret) { 2754e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2755e2cb1decSSalil Mehta goto err_config; 2756e2cb1decSSalil Mehta } 2757e2cb1decSSalil Mehta 2758e2cb1decSSalil Mehta ret = hclgevf_set_handle_info(hdev); 275960df7e91SHuazhong Tan if (ret) 2760e2cb1decSSalil Mehta goto err_config; 2761e2cb1decSSalil Mehta 2762b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2763b26a6feaSPeng Li if (ret) 2764b26a6feaSPeng Li goto err_config; 2765b26a6feaSPeng Li 2766e2cb1decSSalil Mehta /* Initialize RSS for this VF */ 2767e2cb1decSSalil Mehta ret = hclgevf_rss_init_hw(hdev); 2768e2cb1decSSalil Mehta if (ret) { 2769e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2770e2cb1decSSalil Mehta "failed(%d) to initialize RSS\n", ret); 2771e2cb1decSSalil Mehta goto err_config; 2772e2cb1decSSalil Mehta } 2773e2cb1decSSalil Mehta 2774e2cb1decSSalil Mehta ret = hclgevf_init_vlan_config(hdev); 2775e2cb1decSSalil Mehta if (ret) { 2776e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2777e2cb1decSSalil Mehta "failed(%d) to initialize VLAN config\n", ret); 2778e2cb1decSSalil Mehta goto err_config; 2779e2cb1decSSalil Mehta } 2780e2cb1decSSalil Mehta 27810742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 278208d80a4cSHuazhong Tan dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 278308d80a4cSHuazhong Tan HCLGEVF_DRIVER_NAME); 2784e2cb1decSSalil Mehta 2785ff200099SYunsheng Lin hclgevf_task_schedule(hdev, round_jiffies_relative(HZ)); 2786ff200099SYunsheng Lin 2787e2cb1decSSalil Mehta return 0; 2788e2cb1decSSalil Mehta 2789e2cb1decSSalil Mehta err_config: 2790e2cb1decSSalil Mehta hclgevf_misc_irq_uninit(hdev); 2791e2cb1decSSalil Mehta err_misc_irq_init: 2792e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2793e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 279407acf909SJian Shen err_cmd_init: 27958b0195a3SHuazhong Tan hclgevf_cmd_uninit(hdev); 27968b0195a3SHuazhong Tan err_cmd_queue_init: 2797e2cb1decSSalil Mehta hclgevf_pci_uninit(hdev); 2798862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2799e2cb1decSSalil Mehta return ret; 2800e2cb1decSSalil Mehta } 2801e2cb1decSSalil Mehta 28027a01c897SSalil Mehta static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2803e2cb1decSSalil Mehta { 2804e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2805862d969aSHuazhong Tan 280623b4201dSJian Shen hclgevf_send_mbx_msg(hdev, HCLGE_MBX_VF_UNINIT, 0, NULL, 0, 280723b4201dSJian Shen false, NULL, 0); 280823b4201dSJian Shen 2809862d969aSHuazhong Tan if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2810eddf0462SYunsheng Lin hclgevf_misc_irq_uninit(hdev); 2811e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 28127a01c897SSalil Mehta } 28137a01c897SSalil Mehta 2814e3338205SHuazhong Tan hclgevf_pci_uninit(hdev); 2815862d969aSHuazhong Tan hclgevf_cmd_uninit(hdev); 2816862d969aSHuazhong Tan } 2817862d969aSHuazhong Tan 28187a01c897SSalil Mehta static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 28197a01c897SSalil Mehta { 28207a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 28217a01c897SSalil Mehta int ret; 28227a01c897SSalil Mehta 28237a01c897SSalil Mehta ret = hclgevf_alloc_hdev(ae_dev); 28247a01c897SSalil Mehta if (ret) { 28257a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device allocation failed\n"); 28267a01c897SSalil Mehta return ret; 28277a01c897SSalil Mehta } 28287a01c897SSalil Mehta 28297a01c897SSalil Mehta ret = hclgevf_init_hdev(ae_dev->priv); 2830a6d818e3SYunsheng Lin if (ret) { 28317a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device initialization failed\n"); 28327a01c897SSalil Mehta return ret; 28337a01c897SSalil Mehta } 28347a01c897SSalil Mehta 2835a6d818e3SYunsheng Lin return 0; 2836a6d818e3SYunsheng Lin } 2837a6d818e3SYunsheng Lin 28387a01c897SSalil Mehta static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 28397a01c897SSalil Mehta { 28407a01c897SSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 28417a01c897SSalil Mehta 28427a01c897SSalil Mehta hclgevf_uninit_hdev(hdev); 2843e2cb1decSSalil Mehta ae_dev->priv = NULL; 2844e2cb1decSSalil Mehta } 2845e2cb1decSSalil Mehta 2846849e4607SPeng Li static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2847849e4607SPeng Li { 2848849e4607SPeng Li struct hnae3_handle *nic = &hdev->nic; 2849849e4607SPeng Li struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2850849e4607SPeng Li 28518be73621SHuazhong Tan return min_t(u32, hdev->rss_size_max, 28528be73621SHuazhong Tan hdev->num_tqps / kinfo->num_tc); 2853849e4607SPeng Li } 2854849e4607SPeng Li 2855849e4607SPeng Li /** 2856849e4607SPeng Li * hclgevf_get_channels - Get the current channels enabled and max supported. 2857849e4607SPeng Li * @handle: hardware information for network interface 2858849e4607SPeng Li * @ch: ethtool channels structure 2859849e4607SPeng Li * 2860849e4607SPeng Li * We don't support separate tx and rx queues as channels. The other count 2861849e4607SPeng Li * represents how many queues are being used for control. max_combined counts 2862849e4607SPeng Li * how many queue pairs we can support. They may not be mapped 1 to 1 with 2863849e4607SPeng Li * q_vectors since we support a lot more queue pairs than q_vectors. 2864849e4607SPeng Li **/ 2865849e4607SPeng Li static void hclgevf_get_channels(struct hnae3_handle *handle, 2866849e4607SPeng Li struct ethtool_channels *ch) 2867849e4607SPeng Li { 2868849e4607SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2869849e4607SPeng Li 2870849e4607SPeng Li ch->max_combined = hclgevf_get_max_channels(hdev); 2871849e4607SPeng Li ch->other_count = 0; 2872849e4607SPeng Li ch->max_other = 0; 28738be73621SHuazhong Tan ch->combined_count = handle->kinfo.rss_size; 2874849e4607SPeng Li } 2875849e4607SPeng Li 2876cc719218SPeng Li static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 28770d43bf45SHuazhong Tan u16 *alloc_tqps, u16 *max_rss_size) 2878cc719218SPeng Li { 2879cc719218SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2880cc719218SPeng Li 28810d43bf45SHuazhong Tan *alloc_tqps = hdev->num_tqps; 2882cc719218SPeng Li *max_rss_size = hdev->rss_size_max; 2883cc719218SPeng Li } 2884cc719218SPeng Li 28854093d1a2SGuangbin Huang static void hclgevf_update_rss_size(struct hnae3_handle *handle, 28864093d1a2SGuangbin Huang u32 new_tqps_num) 28874093d1a2SGuangbin Huang { 28884093d1a2SGuangbin Huang struct hnae3_knic_private_info *kinfo = &handle->kinfo; 28894093d1a2SGuangbin Huang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 28904093d1a2SGuangbin Huang u16 max_rss_size; 28914093d1a2SGuangbin Huang 28924093d1a2SGuangbin Huang kinfo->req_rss_size = new_tqps_num; 28934093d1a2SGuangbin Huang 28944093d1a2SGuangbin Huang max_rss_size = min_t(u16, hdev->rss_size_max, 28954093d1a2SGuangbin Huang hdev->num_tqps / kinfo->num_tc); 28964093d1a2SGuangbin Huang 28974093d1a2SGuangbin Huang /* Use the user's configuration when it is not larger than 28984093d1a2SGuangbin Huang * max_rss_size, otherwise, use the maximum specification value. 28994093d1a2SGuangbin Huang */ 29004093d1a2SGuangbin Huang if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 29014093d1a2SGuangbin Huang kinfo->req_rss_size <= max_rss_size) 29024093d1a2SGuangbin Huang kinfo->rss_size = kinfo->req_rss_size; 29034093d1a2SGuangbin Huang else if (kinfo->rss_size > max_rss_size || 29044093d1a2SGuangbin Huang (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) 29054093d1a2SGuangbin Huang kinfo->rss_size = max_rss_size; 29064093d1a2SGuangbin Huang 29074093d1a2SGuangbin Huang kinfo->num_tqps = kinfo->num_tc * kinfo->rss_size; 29084093d1a2SGuangbin Huang } 29094093d1a2SGuangbin Huang 29104093d1a2SGuangbin Huang static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 29114093d1a2SGuangbin Huang bool rxfh_configured) 29124093d1a2SGuangbin Huang { 29134093d1a2SGuangbin Huang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 29144093d1a2SGuangbin Huang struct hnae3_knic_private_info *kinfo = &handle->kinfo; 29154093d1a2SGuangbin Huang u16 cur_rss_size = kinfo->rss_size; 29164093d1a2SGuangbin Huang u16 cur_tqps = kinfo->num_tqps; 29174093d1a2SGuangbin Huang u32 *rss_indir; 29184093d1a2SGuangbin Huang unsigned int i; 29194093d1a2SGuangbin Huang int ret; 29204093d1a2SGuangbin Huang 29214093d1a2SGuangbin Huang hclgevf_update_rss_size(handle, new_tqps_num); 29224093d1a2SGuangbin Huang 29234093d1a2SGuangbin Huang ret = hclgevf_set_rss_tc_mode(hdev, kinfo->rss_size); 29244093d1a2SGuangbin Huang if (ret) 29254093d1a2SGuangbin Huang return ret; 29264093d1a2SGuangbin Huang 29274093d1a2SGuangbin Huang /* RSS indirection table has been configuared by user */ 29284093d1a2SGuangbin Huang if (rxfh_configured) 29294093d1a2SGuangbin Huang goto out; 29304093d1a2SGuangbin Huang 29314093d1a2SGuangbin Huang /* Reinitializes the rss indirect table according to the new RSS size */ 29324093d1a2SGuangbin Huang rss_indir = kcalloc(HCLGEVF_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL); 29334093d1a2SGuangbin Huang if (!rss_indir) 29344093d1a2SGuangbin Huang return -ENOMEM; 29354093d1a2SGuangbin Huang 29364093d1a2SGuangbin Huang for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 29374093d1a2SGuangbin Huang rss_indir[i] = i % kinfo->rss_size; 29384093d1a2SGuangbin Huang 29394093d1a2SGuangbin Huang ret = hclgevf_set_rss(handle, rss_indir, NULL, 0); 29404093d1a2SGuangbin Huang if (ret) 29414093d1a2SGuangbin Huang dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 29424093d1a2SGuangbin Huang ret); 29434093d1a2SGuangbin Huang 29444093d1a2SGuangbin Huang kfree(rss_indir); 29454093d1a2SGuangbin Huang 29464093d1a2SGuangbin Huang out: 29474093d1a2SGuangbin Huang if (!ret) 29484093d1a2SGuangbin Huang dev_info(&hdev->pdev->dev, 29494093d1a2SGuangbin Huang "Channels changed, rss_size from %u to %u, tqps from %u to %u", 29504093d1a2SGuangbin Huang cur_rss_size, kinfo->rss_size, 29514093d1a2SGuangbin Huang cur_tqps, kinfo->rss_size * kinfo->num_tc); 29524093d1a2SGuangbin Huang 29534093d1a2SGuangbin Huang return ret; 29544093d1a2SGuangbin Huang } 29554093d1a2SGuangbin Huang 2956175ec96bSFuyun Liang static int hclgevf_get_status(struct hnae3_handle *handle) 2957175ec96bSFuyun Liang { 2958175ec96bSFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2959175ec96bSFuyun Liang 2960175ec96bSFuyun Liang return hdev->hw.mac.link; 2961175ec96bSFuyun Liang } 2962175ec96bSFuyun Liang 29634a152de9SFuyun Liang static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 29644a152de9SFuyun Liang u8 *auto_neg, u32 *speed, 29654a152de9SFuyun Liang u8 *duplex) 29664a152de9SFuyun Liang { 29674a152de9SFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 29684a152de9SFuyun Liang 29694a152de9SFuyun Liang if (speed) 29704a152de9SFuyun Liang *speed = hdev->hw.mac.speed; 29714a152de9SFuyun Liang if (duplex) 29724a152de9SFuyun Liang *duplex = hdev->hw.mac.duplex; 29734a152de9SFuyun Liang if (auto_neg) 29744a152de9SFuyun Liang *auto_neg = AUTONEG_DISABLE; 29754a152de9SFuyun Liang } 29764a152de9SFuyun Liang 29774a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 29784a152de9SFuyun Liang u8 duplex) 29794a152de9SFuyun Liang { 29804a152de9SFuyun Liang hdev->hw.mac.speed = speed; 29814a152de9SFuyun Liang hdev->hw.mac.duplex = duplex; 29824a152de9SFuyun Liang } 29834a152de9SFuyun Liang 29841731be4cSYonglong Liu static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 29855c9f6b39SPeng Li { 29865c9f6b39SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 29875c9f6b39SPeng Li 29885c9f6b39SPeng Li return hclgevf_config_gro(hdev, enable); 29895c9f6b39SPeng Li } 29905c9f6b39SPeng Li 299188d10bd6SJian Shen static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 299288d10bd6SJian Shen u8 *module_type) 2993c136b884SPeng Li { 2994c136b884SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 299588d10bd6SJian Shen 2996c136b884SPeng Li if (media_type) 2997c136b884SPeng Li *media_type = hdev->hw.mac.media_type; 299888d10bd6SJian Shen 299988d10bd6SJian Shen if (module_type) 300088d10bd6SJian Shen *module_type = hdev->hw.mac.module_type; 3001c136b884SPeng Li } 3002c136b884SPeng Li 30034d60291bSHuazhong Tan static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 30044d60291bSHuazhong Tan { 30054d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 30064d60291bSHuazhong Tan 3007aa5c4f17SHuazhong Tan return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 30084d60291bSHuazhong Tan } 30094d60291bSHuazhong Tan 30104d60291bSHuazhong Tan static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 30114d60291bSHuazhong Tan { 30124d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 30134d60291bSHuazhong Tan 30144d60291bSHuazhong Tan return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 30154d60291bSHuazhong Tan } 30164d60291bSHuazhong Tan 30174d60291bSHuazhong Tan static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 30184d60291bSHuazhong Tan { 30194d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 30204d60291bSHuazhong Tan 3021c88a6e7dSHuazhong Tan return hdev->rst_stats.hw_rst_done_cnt; 30224d60291bSHuazhong Tan } 30234d60291bSHuazhong Tan 30249194d18bSliuzhongzhu static void hclgevf_get_link_mode(struct hnae3_handle *handle, 30259194d18bSliuzhongzhu unsigned long *supported, 30269194d18bSliuzhongzhu unsigned long *advertising) 30279194d18bSliuzhongzhu { 30289194d18bSliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 30299194d18bSliuzhongzhu 30309194d18bSliuzhongzhu *supported = hdev->hw.mac.supported; 30319194d18bSliuzhongzhu *advertising = hdev->hw.mac.advertising; 30329194d18bSliuzhongzhu } 30339194d18bSliuzhongzhu 30341600c3e5SJian Shen #define MAX_SEPARATE_NUM 4 30351600c3e5SJian Shen #define SEPARATOR_VALUE 0xFFFFFFFF 30361600c3e5SJian Shen #define REG_NUM_PER_LINE 4 30371600c3e5SJian Shen #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 30381600c3e5SJian Shen 30391600c3e5SJian Shen static int hclgevf_get_regs_len(struct hnae3_handle *handle) 30401600c3e5SJian Shen { 30411600c3e5SJian Shen int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 30421600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 30431600c3e5SJian Shen 30441600c3e5SJian Shen cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 30451600c3e5SJian Shen common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 30461600c3e5SJian Shen ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 30471600c3e5SJian Shen tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 30481600c3e5SJian Shen 30491600c3e5SJian Shen return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 30501600c3e5SJian Shen tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 30511600c3e5SJian Shen } 30521600c3e5SJian Shen 30531600c3e5SJian Shen static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 30541600c3e5SJian Shen void *data) 30551600c3e5SJian Shen { 30561600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 30571600c3e5SJian Shen int i, j, reg_um, separator_num; 30581600c3e5SJian Shen u32 *reg = data; 30591600c3e5SJian Shen 30601600c3e5SJian Shen *version = hdev->fw_version; 30611600c3e5SJian Shen 30621600c3e5SJian Shen /* fetching per-VF registers values from VF PCIe register space */ 30631600c3e5SJian Shen reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 30641600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 30651600c3e5SJian Shen for (i = 0; i < reg_um; i++) 30661600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 30671600c3e5SJian Shen for (i = 0; i < separator_num; i++) 30681600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 30691600c3e5SJian Shen 30701600c3e5SJian Shen reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 30711600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 30721600c3e5SJian Shen for (i = 0; i < reg_um; i++) 30731600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 30741600c3e5SJian Shen for (i = 0; i < separator_num; i++) 30751600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 30761600c3e5SJian Shen 30771600c3e5SJian Shen reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 30781600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 30791600c3e5SJian Shen for (j = 0; j < hdev->num_tqps; j++) { 30801600c3e5SJian Shen for (i = 0; i < reg_um; i++) 30811600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 30821600c3e5SJian Shen ring_reg_addr_list[i] + 30831600c3e5SJian Shen 0x200 * j); 30841600c3e5SJian Shen for (i = 0; i < separator_num; i++) 30851600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 30861600c3e5SJian Shen } 30871600c3e5SJian Shen 30881600c3e5SJian Shen reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 30891600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 30901600c3e5SJian Shen for (j = 0; j < hdev->num_msi_used - 1; j++) { 30911600c3e5SJian Shen for (i = 0; i < reg_um; i++) 30921600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 30931600c3e5SJian Shen tqp_intr_reg_addr_list[i] + 30941600c3e5SJian Shen 4 * j); 30951600c3e5SJian Shen for (i = 0; i < separator_num; i++) 30961600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 30971600c3e5SJian Shen } 30981600c3e5SJian Shen } 30991600c3e5SJian Shen 310092f11ea1SJian Shen void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 310192f11ea1SJian Shen u8 *port_base_vlan_info, u8 data_size) 310292f11ea1SJian Shen { 310392f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 310492f11ea1SJian Shen 310592f11ea1SJian Shen rtnl_lock(); 310692f11ea1SJian Shen hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 310792f11ea1SJian Shen rtnl_unlock(); 310892f11ea1SJian Shen 310992f11ea1SJian Shen /* send msg to PF and wait update port based vlan info */ 311092f11ea1SJian Shen hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 311192f11ea1SJian Shen HCLGE_MBX_PORT_BASE_VLAN_CFG, 311292f11ea1SJian Shen port_base_vlan_info, data_size, 311392f11ea1SJian Shen false, NULL, 0); 311492f11ea1SJian Shen 311592f11ea1SJian Shen if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 311692f11ea1SJian Shen nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 311792f11ea1SJian Shen else 311892f11ea1SJian Shen nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 311992f11ea1SJian Shen 312092f11ea1SJian Shen rtnl_lock(); 312192f11ea1SJian Shen hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 312292f11ea1SJian Shen rtnl_unlock(); 312392f11ea1SJian Shen } 312492f11ea1SJian Shen 3125e2cb1decSSalil Mehta static const struct hnae3_ae_ops hclgevf_ops = { 3126e2cb1decSSalil Mehta .init_ae_dev = hclgevf_init_ae_dev, 3127e2cb1decSSalil Mehta .uninit_ae_dev = hclgevf_uninit_ae_dev, 31286ff3cf07SHuazhong Tan .flr_prepare = hclgevf_flr_prepare, 31296ff3cf07SHuazhong Tan .flr_done = hclgevf_flr_done, 3130e718a93fSPeng Li .init_client_instance = hclgevf_init_client_instance, 3131e718a93fSPeng Li .uninit_client_instance = hclgevf_uninit_client_instance, 3132e2cb1decSSalil Mehta .start = hclgevf_ae_start, 3133e2cb1decSSalil Mehta .stop = hclgevf_ae_stop, 3134a6d818e3SYunsheng Lin .client_start = hclgevf_client_start, 3135a6d818e3SYunsheng Lin .client_stop = hclgevf_client_stop, 3136e2cb1decSSalil Mehta .map_ring_to_vector = hclgevf_map_ring_to_vector, 3137e2cb1decSSalil Mehta .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 3138e2cb1decSSalil Mehta .get_vector = hclgevf_get_vector, 31390d3e6631SYunsheng Lin .put_vector = hclgevf_put_vector, 3140e2cb1decSSalil Mehta .reset_queue = hclgevf_reset_tqp, 3141e2cb1decSSalil Mehta .get_mac_addr = hclgevf_get_mac_addr, 3142e2cb1decSSalil Mehta .set_mac_addr = hclgevf_set_mac_addr, 3143e2cb1decSSalil Mehta .add_uc_addr = hclgevf_add_uc_addr, 3144e2cb1decSSalil Mehta .rm_uc_addr = hclgevf_rm_uc_addr, 3145e2cb1decSSalil Mehta .add_mc_addr = hclgevf_add_mc_addr, 3146e2cb1decSSalil Mehta .rm_mc_addr = hclgevf_rm_mc_addr, 3147e2cb1decSSalil Mehta .get_stats = hclgevf_get_stats, 3148e2cb1decSSalil Mehta .update_stats = hclgevf_update_stats, 3149e2cb1decSSalil Mehta .get_strings = hclgevf_get_strings, 3150e2cb1decSSalil Mehta .get_sset_count = hclgevf_get_sset_count, 3151e2cb1decSSalil Mehta .get_rss_key_size = hclgevf_get_rss_key_size, 3152e2cb1decSSalil Mehta .get_rss_indir_size = hclgevf_get_rss_indir_size, 3153e2cb1decSSalil Mehta .get_rss = hclgevf_get_rss, 3154e2cb1decSSalil Mehta .set_rss = hclgevf_set_rss, 3155d97b3072SJian Shen .get_rss_tuple = hclgevf_get_rss_tuple, 3156d97b3072SJian Shen .set_rss_tuple = hclgevf_set_rss_tuple, 3157e2cb1decSSalil Mehta .get_tc_size = hclgevf_get_tc_size, 3158e2cb1decSSalil Mehta .get_fw_version = hclgevf_get_fw_version, 3159e2cb1decSSalil Mehta .set_vlan_filter = hclgevf_set_vlan_filter, 3160b2641e2aSYunsheng Lin .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 31616d4c3981SSalil Mehta .reset_event = hclgevf_reset_event, 3162720bd583SHuazhong Tan .set_default_reset_request = hclgevf_set_def_reset_request, 31634093d1a2SGuangbin Huang .set_channels = hclgevf_set_channels, 3164849e4607SPeng Li .get_channels = hclgevf_get_channels, 3165cc719218SPeng Li .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 31661600c3e5SJian Shen .get_regs_len = hclgevf_get_regs_len, 31671600c3e5SJian Shen .get_regs = hclgevf_get_regs, 3168175ec96bSFuyun Liang .get_status = hclgevf_get_status, 31694a152de9SFuyun Liang .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3170c136b884SPeng Li .get_media_type = hclgevf_get_media_type, 31714d60291bSHuazhong Tan .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 31724d60291bSHuazhong Tan .ae_dev_resetting = hclgevf_ae_dev_resetting, 31734d60291bSHuazhong Tan .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 31745c9f6b39SPeng Li .set_gro_en = hclgevf_gro_en, 3175818f1675SYunsheng Lin .set_mtu = hclgevf_set_mtu, 31760c29d191Sliuzhongzhu .get_global_queue_id = hclgevf_get_qid_global, 31778cdb992fSJian Shen .set_timer_task = hclgevf_set_timer_task, 31789194d18bSliuzhongzhu .get_link_mode = hclgevf_get_link_mode, 3179e196ec75SJian Shen .set_promisc_mode = hclgevf_set_promisc_mode, 3180e2cb1decSSalil Mehta }; 3181e2cb1decSSalil Mehta 3182e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf = { 3183e2cb1decSSalil Mehta .ops = &hclgevf_ops, 3184e2cb1decSSalil Mehta .pdev_id_table = ae_algovf_pci_tbl, 3185e2cb1decSSalil Mehta }; 3186e2cb1decSSalil Mehta 3187e2cb1decSSalil Mehta static int hclgevf_init(void) 3188e2cb1decSSalil Mehta { 3189e2cb1decSSalil Mehta pr_info("%s is initializing\n", HCLGEVF_NAME); 3190e2cb1decSSalil Mehta 31910ea68902SYunsheng Lin hclgevf_wq = alloc_workqueue("%s", WQ_MEM_RECLAIM, 0, HCLGEVF_NAME); 31920ea68902SYunsheng Lin if (!hclgevf_wq) { 31930ea68902SYunsheng Lin pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME); 31940ea68902SYunsheng Lin return -ENOMEM; 31950ea68902SYunsheng Lin } 31960ea68902SYunsheng Lin 3197854cf33aSFuyun Liang hnae3_register_ae_algo(&ae_algovf); 3198854cf33aSFuyun Liang 3199854cf33aSFuyun Liang return 0; 3200e2cb1decSSalil Mehta } 3201e2cb1decSSalil Mehta 3202e2cb1decSSalil Mehta static void hclgevf_exit(void) 3203e2cb1decSSalil Mehta { 3204e2cb1decSSalil Mehta hnae3_unregister_ae_algo(&ae_algovf); 32050ea68902SYunsheng Lin destroy_workqueue(hclgevf_wq); 3206e2cb1decSSalil Mehta } 3207e2cb1decSSalil Mehta module_init(hclgevf_init); 3208e2cb1decSSalil Mehta module_exit(hclgevf_exit); 3209e2cb1decSSalil Mehta 3210e2cb1decSSalil Mehta MODULE_LICENSE("GPL"); 3211e2cb1decSSalil Mehta MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3212e2cb1decSSalil Mehta MODULE_DESCRIPTION("HCLGEVF Driver"); 3213e2cb1decSSalil Mehta MODULE_VERSION(HCLGEVF_MOD_VERSION); 3214