1e2cb1decSSalil Mehta // SPDX-License-Identifier: GPL-2.0+ 2e2cb1decSSalil Mehta // Copyright (c) 2016-2017 Hisilicon Limited. 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #include <linux/etherdevice.h> 5aa5c4f17SHuazhong Tan #include <linux/iopoll.h> 66988eb2aSSalil Mehta #include <net/rtnetlink.h> 7e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 8e2cb1decSSalil Mehta #include "hclgevf_main.h" 9e2cb1decSSalil Mehta #include "hclge_mbx.h" 10e2cb1decSSalil Mehta #include "hnae3.h" 11cd624299SYufeng Mo #include "hclgevf_devlink.h" 12027733b1SJie Wang #include "hclge_comm_rss.h" 13e2cb1decSSalil Mehta 14e2cb1decSSalil Mehta #define HCLGEVF_NAME "hclgevf" 15e2cb1decSSalil Mehta 16bbe6540eSHuazhong Tan #define HCLGEVF_RESET_MAX_FAIL_CNT 5 17bbe6540eSHuazhong Tan 189c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 195e7414cdSJian Shen static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 205e7414cdSJian Shen unsigned long delay); 215e7414cdSJian Shen 22e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf; 23e2cb1decSSalil Mehta 240ea68902SYunsheng Lin static struct workqueue_struct *hclgevf_wq; 250ea68902SYunsheng Lin 26e2cb1decSSalil Mehta static const struct pci_device_id ae_algovf_pci_tbl[] = { 27c155e22bSGuangbin Huang {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0}, 28c155e22bSGuangbin Huang {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 29c155e22bSGuangbin Huang HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 30e2cb1decSSalil Mehta /* required last entry */ 31e2cb1decSSalil Mehta {0, } 32e2cb1decSSalil Mehta }; 33e2cb1decSSalil Mehta 342f550a46SYunsheng Lin MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 352f550a46SYunsheng Lin 36cb413bfaSJie Wang static const u32 cmdq_reg_addr_list[] = {HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG, 37cb413bfaSJie Wang HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG, 38cb413bfaSJie Wang HCLGE_COMM_NIC_CSQ_DEPTH_REG, 39cb413bfaSJie Wang HCLGE_COMM_NIC_CSQ_TAIL_REG, 40cb413bfaSJie Wang HCLGE_COMM_NIC_CSQ_HEAD_REG, 41cb413bfaSJie Wang HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG, 42cb413bfaSJie Wang HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG, 43cb413bfaSJie Wang HCLGE_COMM_NIC_CRQ_DEPTH_REG, 44cb413bfaSJie Wang HCLGE_COMM_NIC_CRQ_TAIL_REG, 45cb413bfaSJie Wang HCLGE_COMM_NIC_CRQ_HEAD_REG, 46cb413bfaSJie Wang HCLGE_COMM_VECTOR0_CMDQ_SRC_REG, 47cb413bfaSJie Wang HCLGE_COMM_VECTOR0_CMDQ_STATE_REG, 48cb413bfaSJie Wang HCLGE_COMM_CMDQ_INTR_EN_REG, 49cb413bfaSJie Wang HCLGE_COMM_CMDQ_INTR_GEN_REG}; 501600c3e5SJian Shen 511600c3e5SJian Shen static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 521600c3e5SJian Shen HCLGEVF_RST_ING, 531600c3e5SJian Shen HCLGEVF_GRO_EN_REG}; 541600c3e5SJian Shen 551600c3e5SJian Shen static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 561600c3e5SJian Shen HCLGEVF_RING_RX_ADDR_H_REG, 571600c3e5SJian Shen HCLGEVF_RING_RX_BD_NUM_REG, 581600c3e5SJian Shen HCLGEVF_RING_RX_BD_LENGTH_REG, 591600c3e5SJian Shen HCLGEVF_RING_RX_MERGE_EN_REG, 601600c3e5SJian Shen HCLGEVF_RING_RX_TAIL_REG, 611600c3e5SJian Shen HCLGEVF_RING_RX_HEAD_REG, 621600c3e5SJian Shen HCLGEVF_RING_RX_FBD_NUM_REG, 631600c3e5SJian Shen HCLGEVF_RING_RX_OFFSET_REG, 641600c3e5SJian Shen HCLGEVF_RING_RX_FBD_OFFSET_REG, 651600c3e5SJian Shen HCLGEVF_RING_RX_STASH_REG, 661600c3e5SJian Shen HCLGEVF_RING_RX_BD_ERR_REG, 671600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_L_REG, 681600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_H_REG, 691600c3e5SJian Shen HCLGEVF_RING_TX_BD_NUM_REG, 701600c3e5SJian Shen HCLGEVF_RING_TX_PRIORITY_REG, 711600c3e5SJian Shen HCLGEVF_RING_TX_TC_REG, 721600c3e5SJian Shen HCLGEVF_RING_TX_MERGE_EN_REG, 731600c3e5SJian Shen HCLGEVF_RING_TX_TAIL_REG, 741600c3e5SJian Shen HCLGEVF_RING_TX_HEAD_REG, 751600c3e5SJian Shen HCLGEVF_RING_TX_FBD_NUM_REG, 761600c3e5SJian Shen HCLGEVF_RING_TX_OFFSET_REG, 771600c3e5SJian Shen HCLGEVF_RING_TX_EBD_NUM_REG, 781600c3e5SJian Shen HCLGEVF_RING_TX_EBD_OFFSET_REG, 791600c3e5SJian Shen HCLGEVF_RING_TX_BD_ERR_REG, 801600c3e5SJian Shen HCLGEVF_RING_EN_REG}; 811600c3e5SJian Shen 821600c3e5SJian Shen static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 831600c3e5SJian Shen HCLGEVF_TQP_INTR_GL0_REG, 841600c3e5SJian Shen HCLGEVF_TQP_INTR_GL1_REG, 851600c3e5SJian Shen HCLGEVF_TQP_INTR_GL2_REG, 861600c3e5SJian Shen HCLGEVF_TQP_INTR_RL_REG}; 871600c3e5SJian Shen 88aab8d1c6SJie Wang /* hclgevf_cmd_send - send command to command queue 89aab8d1c6SJie Wang * @hw: pointer to the hw struct 90aab8d1c6SJie Wang * @desc: prefilled descriptor for describing the command 91aab8d1c6SJie Wang * @num : the number of descriptors to be sent 92aab8d1c6SJie Wang * 93aab8d1c6SJie Wang * This is the main send command for command queue, it 94aab8d1c6SJie Wang * sends the queue, cleans the queue, etc 95aab8d1c6SJie Wang */ 96aab8d1c6SJie Wang int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclge_desc *desc, int num) 97aab8d1c6SJie Wang { 989970308fSJie Wang return hclge_comm_cmd_send(&hw->hw, desc, num); 99aab8d1c6SJie Wang } 100aab8d1c6SJie Wang 101aab8d1c6SJie Wang void hclgevf_arq_init(struct hclgevf_dev *hdev) 102aab8d1c6SJie Wang { 103aab8d1c6SJie Wang struct hclge_comm_cmq *cmdq = &hdev->hw.hw.cmq; 104aab8d1c6SJie Wang 105aab8d1c6SJie Wang spin_lock(&cmdq->crq.lock); 106aab8d1c6SJie Wang /* initialize the pointers of async rx queue of mailbox */ 107aab8d1c6SJie Wang hdev->arq.hdev = hdev; 108aab8d1c6SJie Wang hdev->arq.head = 0; 109aab8d1c6SJie Wang hdev->arq.tail = 0; 110aab8d1c6SJie Wang atomic_set(&hdev->arq.count, 0); 111aab8d1c6SJie Wang spin_unlock(&cmdq->crq.lock); 112aab8d1c6SJie Wang } 113aab8d1c6SJie Wang 1149b2f3477SWeihang Li static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 115e2cb1decSSalil Mehta { 116eed9535fSPeng Li if (!handle->client) 117eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, nic); 118eed9535fSPeng Li else if (handle->client->type == HNAE3_CLIENT_ROCE) 119eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, roce); 120eed9535fSPeng Li else 121e2cb1decSSalil Mehta return container_of(handle, struct hclgevf_dev, nic); 122e2cb1decSSalil Mehta } 123e2cb1decSSalil Mehta 124e2cb1decSSalil Mehta static void hclgevf_update_stats(struct hnae3_handle *handle, 125e2cb1decSSalil Mehta struct net_device_stats *net_stats) 126e2cb1decSSalil Mehta { 127e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 128e2cb1decSSalil Mehta int status; 129e2cb1decSSalil Mehta 1304afc310cSJie Wang status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 131e2cb1decSSalil Mehta if (status) 132e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 133e2cb1decSSalil Mehta "VF update of TQPS stats fail, status = %d.\n", 134e2cb1decSSalil Mehta status); 135e2cb1decSSalil Mehta } 136e2cb1decSSalil Mehta 137e2cb1decSSalil Mehta static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 138e2cb1decSSalil Mehta { 139e2cb1decSSalil Mehta if (strset == ETH_SS_TEST) 140e2cb1decSSalil Mehta return -EOPNOTSUPP; 141e2cb1decSSalil Mehta else if (strset == ETH_SS_STATS) 1424afc310cSJie Wang return hclge_comm_tqps_get_sset_count(handle); 143e2cb1decSSalil Mehta 144e2cb1decSSalil Mehta return 0; 145e2cb1decSSalil Mehta } 146e2cb1decSSalil Mehta 147e2cb1decSSalil Mehta static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 148e2cb1decSSalil Mehta u8 *data) 149e2cb1decSSalil Mehta { 150e2cb1decSSalil Mehta u8 *p = (char *)data; 151e2cb1decSSalil Mehta 152e2cb1decSSalil Mehta if (strset == ETH_SS_STATS) 1534afc310cSJie Wang p = hclge_comm_tqps_get_strings(handle, p); 154e2cb1decSSalil Mehta } 155e2cb1decSSalil Mehta 156e2cb1decSSalil Mehta static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 157e2cb1decSSalil Mehta { 1584afc310cSJie Wang hclge_comm_tqps_get_stats(handle, data); 159e2cb1decSSalil Mehta } 160e2cb1decSSalil Mehta 161d3410018SYufeng Mo static void hclgevf_build_send_msg(struct hclge_vf_to_pf_msg *msg, u8 code, 162d3410018SYufeng Mo u8 subcode) 163d3410018SYufeng Mo { 164d3410018SYufeng Mo if (msg) { 165d3410018SYufeng Mo memset(msg, 0, sizeof(struct hclge_vf_to_pf_msg)); 166d3410018SYufeng Mo msg->code = code; 167d3410018SYufeng Mo msg->subcode = subcode; 168d3410018SYufeng Mo } 169d3410018SYufeng Mo } 170d3410018SYufeng Mo 17132e6d104SJian Shen static int hclgevf_get_basic_info(struct hclgevf_dev *hdev) 172e2cb1decSSalil Mehta { 17332e6d104SJian Shen struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 17432e6d104SJian Shen u8 resp_msg[HCLGE_MBX_MAX_RESP_DATA_SIZE]; 17532e6d104SJian Shen struct hclge_basic_info *basic_info; 176d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 17732e6d104SJian Shen unsigned long caps; 178e2cb1decSSalil Mehta int status; 179e2cb1decSSalil Mehta 18032e6d104SJian Shen hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_BASIC_INFO, 0); 18132e6d104SJian Shen status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 182d3410018SYufeng Mo sizeof(resp_msg)); 183e2cb1decSSalil Mehta if (status) { 184e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 18532e6d104SJian Shen "failed to get basic info from pf, ret = %d", status); 186e2cb1decSSalil Mehta return status; 187e2cb1decSSalil Mehta } 188e2cb1decSSalil Mehta 18932e6d104SJian Shen basic_info = (struct hclge_basic_info *)resp_msg; 19032e6d104SJian Shen 19132e6d104SJian Shen hdev->hw_tc_map = basic_info->hw_tc_map; 19232e6d104SJian Shen hdev->mbx_api_version = basic_info->mbx_api_version; 19332e6d104SJian Shen caps = basic_info->pf_caps; 19432e6d104SJian Shen if (test_bit(HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B, &caps)) 19532e6d104SJian Shen set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps); 196e2cb1decSSalil Mehta 197e2cb1decSSalil Mehta return 0; 198e2cb1decSSalil Mehta } 199e2cb1decSSalil Mehta 20092f11ea1SJian Shen static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 20192f11ea1SJian Shen { 20292f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 203d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 20492f11ea1SJian Shen u8 resp_msg; 20592f11ea1SJian Shen int ret; 20692f11ea1SJian Shen 207d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 208d3410018SYufeng Mo HCLGE_MBX_GET_PORT_BASE_VLAN_STATE); 209d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg, 210d3410018SYufeng Mo sizeof(u8)); 21192f11ea1SJian Shen if (ret) { 21292f11ea1SJian Shen dev_err(&hdev->pdev->dev, 21392f11ea1SJian Shen "VF request to get port based vlan state failed %d", 21492f11ea1SJian Shen ret); 21592f11ea1SJian Shen return ret; 21692f11ea1SJian Shen } 21792f11ea1SJian Shen 21892f11ea1SJian Shen nic->port_base_vlan_state = resp_msg; 21992f11ea1SJian Shen 22092f11ea1SJian Shen return 0; 22192f11ea1SJian Shen } 22292f11ea1SJian Shen 2236cee6fc3SJian Shen static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 224e2cb1decSSalil Mehta { 225c0425944SPeng Li #define HCLGEVF_TQPS_RSS_INFO_LEN 6 226d3410018SYufeng Mo #define HCLGEVF_TQPS_ALLOC_OFFSET 0 227d3410018SYufeng Mo #define HCLGEVF_TQPS_RSS_SIZE_OFFSET 2 228d3410018SYufeng Mo #define HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET 4 229d3410018SYufeng Mo 230e2cb1decSSalil Mehta u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 231d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 232e2cb1decSSalil Mehta int status; 233e2cb1decSSalil Mehta 234d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QINFO, 0); 235d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 236e2cb1decSSalil Mehta HCLGEVF_TQPS_RSS_INFO_LEN); 237e2cb1decSSalil Mehta if (status) { 238e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 239e2cb1decSSalil Mehta "VF request to get tqp info from PF failed %d", 240e2cb1decSSalil Mehta status); 241e2cb1decSSalil Mehta return status; 242e2cb1decSSalil Mehta } 243e2cb1decSSalil Mehta 244d3410018SYufeng Mo memcpy(&hdev->num_tqps, &resp_msg[HCLGEVF_TQPS_ALLOC_OFFSET], 245d3410018SYufeng Mo sizeof(u16)); 246d3410018SYufeng Mo memcpy(&hdev->rss_size_max, &resp_msg[HCLGEVF_TQPS_RSS_SIZE_OFFSET], 247d3410018SYufeng Mo sizeof(u16)); 248d3410018SYufeng Mo memcpy(&hdev->rx_buf_len, &resp_msg[HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET], 249d3410018SYufeng Mo sizeof(u16)); 250c0425944SPeng Li 251c0425944SPeng Li return 0; 252c0425944SPeng Li } 253c0425944SPeng Li 254c0425944SPeng Li static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 255c0425944SPeng Li { 256c0425944SPeng Li #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 257d3410018SYufeng Mo #define HCLGEVF_TQPS_NUM_TX_DESC_OFFSET 0 258d3410018SYufeng Mo #define HCLGEVF_TQPS_NUM_RX_DESC_OFFSET 2 259d3410018SYufeng Mo 260c0425944SPeng Li u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 261d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 262c0425944SPeng Li int ret; 263c0425944SPeng Li 264d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QDEPTH, 0); 265d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 266c0425944SPeng Li HCLGEVF_TQPS_DEPTH_INFO_LEN); 267c0425944SPeng Li if (ret) { 268c0425944SPeng Li dev_err(&hdev->pdev->dev, 269c0425944SPeng Li "VF request to get tqp depth info from PF failed %d", 270c0425944SPeng Li ret); 271c0425944SPeng Li return ret; 272c0425944SPeng Li } 273c0425944SPeng Li 274d3410018SYufeng Mo memcpy(&hdev->num_tx_desc, &resp_msg[HCLGEVF_TQPS_NUM_TX_DESC_OFFSET], 275d3410018SYufeng Mo sizeof(u16)); 276d3410018SYufeng Mo memcpy(&hdev->num_rx_desc, &resp_msg[HCLGEVF_TQPS_NUM_RX_DESC_OFFSET], 277d3410018SYufeng Mo sizeof(u16)); 278e2cb1decSSalil Mehta 279e2cb1decSSalil Mehta return 0; 280e2cb1decSSalil Mehta } 281e2cb1decSSalil Mehta 2820c29d191Sliuzhongzhu static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 2830c29d191Sliuzhongzhu { 2840c29d191Sliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 285d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 2860c29d191Sliuzhongzhu u16 qid_in_pf = 0; 287d3410018SYufeng Mo u8 resp_data[2]; 2880c29d191Sliuzhongzhu int ret; 2890c29d191Sliuzhongzhu 290d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QID_IN_PF, 0); 291d3410018SYufeng Mo memcpy(send_msg.data, &queue_id, sizeof(queue_id)); 292d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_data, 29363cbf7a9SYufeng Mo sizeof(resp_data)); 2940c29d191Sliuzhongzhu if (!ret) 2950c29d191Sliuzhongzhu qid_in_pf = *(u16 *)resp_data; 2960c29d191Sliuzhongzhu 2970c29d191Sliuzhongzhu return qid_in_pf; 2980c29d191Sliuzhongzhu } 2990c29d191Sliuzhongzhu 3009c3e7130Sliuzhongzhu static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 3019c3e7130Sliuzhongzhu { 302d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 30388d10bd6SJian Shen u8 resp_msg[2]; 3049c3e7130Sliuzhongzhu int ret; 3059c3e7130Sliuzhongzhu 306d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MEDIA_TYPE, 0); 307d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 308d3410018SYufeng Mo sizeof(resp_msg)); 3099c3e7130Sliuzhongzhu if (ret) { 3109c3e7130Sliuzhongzhu dev_err(&hdev->pdev->dev, 3119c3e7130Sliuzhongzhu "VF request to get the pf port media type failed %d", 3129c3e7130Sliuzhongzhu ret); 3139c3e7130Sliuzhongzhu return ret; 3149c3e7130Sliuzhongzhu } 3159c3e7130Sliuzhongzhu 31688d10bd6SJian Shen hdev->hw.mac.media_type = resp_msg[0]; 31788d10bd6SJian Shen hdev->hw.mac.module_type = resp_msg[1]; 3189c3e7130Sliuzhongzhu 3199c3e7130Sliuzhongzhu return 0; 3209c3e7130Sliuzhongzhu } 3219c3e7130Sliuzhongzhu 322e2cb1decSSalil Mehta static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 323e2cb1decSSalil Mehta { 32487a9b2fdSYufeng Mo struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 3254afc310cSJie Wang struct hclge_comm_tqp *tqp; 326e2cb1decSSalil Mehta int i; 327e2cb1decSSalil Mehta 328e2cb1decSSalil Mehta hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 3294afc310cSJie Wang sizeof(struct hclge_comm_tqp), GFP_KERNEL); 330e2cb1decSSalil Mehta if (!hdev->htqp) 331e2cb1decSSalil Mehta return -ENOMEM; 332e2cb1decSSalil Mehta 333e2cb1decSSalil Mehta tqp = hdev->htqp; 334e2cb1decSSalil Mehta 335e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 336e2cb1decSSalil Mehta tqp->dev = &hdev->pdev->dev; 337e2cb1decSSalil Mehta tqp->index = i; 338e2cb1decSSalil Mehta 339e2cb1decSSalil Mehta tqp->q.ae_algo = &ae_algovf; 340e2cb1decSSalil Mehta tqp->q.buf_size = hdev->rx_buf_len; 341c0425944SPeng Li tqp->q.tx_desc_num = hdev->num_tx_desc; 342c0425944SPeng Li tqp->q.rx_desc_num = hdev->num_rx_desc; 3439a5ef4aaSYonglong Liu 3449a5ef4aaSYonglong Liu /* need an extended offset to configure queues >= 3459a5ef4aaSYonglong Liu * HCLGEVF_TQP_MAX_SIZE_DEV_V2. 3469a5ef4aaSYonglong Liu */ 3479a5ef4aaSYonglong Liu if (i < HCLGEVF_TQP_MAX_SIZE_DEV_V2) 348076bb537SJie Wang tqp->q.io_base = hdev->hw.hw.io_base + 3499a5ef4aaSYonglong Liu HCLGEVF_TQP_REG_OFFSET + 350e2cb1decSSalil Mehta i * HCLGEVF_TQP_REG_SIZE; 3519a5ef4aaSYonglong Liu else 352076bb537SJie Wang tqp->q.io_base = hdev->hw.hw.io_base + 3539a5ef4aaSYonglong Liu HCLGEVF_TQP_REG_OFFSET + 3549a5ef4aaSYonglong Liu HCLGEVF_TQP_EXT_REG_OFFSET + 3559a5ef4aaSYonglong Liu (i - HCLGEVF_TQP_MAX_SIZE_DEV_V2) * 3569a5ef4aaSYonglong Liu HCLGEVF_TQP_REG_SIZE; 357e2cb1decSSalil Mehta 35887a9b2fdSYufeng Mo /* when device supports tx push and has device memory, 35987a9b2fdSYufeng Mo * the queue can execute push mode or doorbell mode on 36087a9b2fdSYufeng Mo * device memory. 36187a9b2fdSYufeng Mo */ 36287a9b2fdSYufeng Mo if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps)) 36387a9b2fdSYufeng Mo tqp->q.mem_base = hdev->hw.hw.mem_base + 36487a9b2fdSYufeng Mo HCLGEVF_TQP_MEM_OFFSET(hdev, i); 36587a9b2fdSYufeng Mo 366e2cb1decSSalil Mehta tqp++; 367e2cb1decSSalil Mehta } 368e2cb1decSSalil Mehta 369e2cb1decSSalil Mehta return 0; 370e2cb1decSSalil Mehta } 371e2cb1decSSalil Mehta 372e2cb1decSSalil Mehta static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 373e2cb1decSSalil Mehta { 374e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 375e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo; 376e2cb1decSSalil Mehta u16 new_tqps = hdev->num_tqps; 377ebaf1908SWeihang Li unsigned int i; 37835244430SJian Shen u8 num_tc = 0; 379e2cb1decSSalil Mehta 380e2cb1decSSalil Mehta kinfo = &nic->kinfo; 381c0425944SPeng Li kinfo->num_tx_desc = hdev->num_tx_desc; 382c0425944SPeng Li kinfo->num_rx_desc = hdev->num_rx_desc; 383e2cb1decSSalil Mehta kinfo->rx_buf_len = hdev->rx_buf_len; 38493969dc1SJie Wang for (i = 0; i < HCLGE_COMM_MAX_TC_NUM; i++) 385e2cb1decSSalil Mehta if (hdev->hw_tc_map & BIT(i)) 38635244430SJian Shen num_tc++; 387e2cb1decSSalil Mehta 38835244430SJian Shen num_tc = num_tc ? num_tc : 1; 38935244430SJian Shen kinfo->tc_info.num_tc = num_tc; 39035244430SJian Shen kinfo->rss_size = min_t(u16, hdev->rss_size_max, new_tqps / num_tc); 39135244430SJian Shen new_tqps = kinfo->rss_size * num_tc; 392e2cb1decSSalil Mehta kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 393e2cb1decSSalil Mehta 394e2cb1decSSalil Mehta kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 395e2cb1decSSalil Mehta sizeof(struct hnae3_queue *), GFP_KERNEL); 396e2cb1decSSalil Mehta if (!kinfo->tqp) 397e2cb1decSSalil Mehta return -ENOMEM; 398e2cb1decSSalil Mehta 399e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 400e2cb1decSSalil Mehta hdev->htqp[i].q.handle = &hdev->nic; 401e2cb1decSSalil Mehta hdev->htqp[i].q.tqp_index = i; 402e2cb1decSSalil Mehta kinfo->tqp[i] = &hdev->htqp[i].q; 403e2cb1decSSalil Mehta } 404e2cb1decSSalil Mehta 405580a05f9SYonglong Liu /* after init the max rss_size and tqps, adjust the default tqp numbers 406580a05f9SYonglong Liu * and rss size with the actual vector numbers 407580a05f9SYonglong Liu */ 408580a05f9SYonglong Liu kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps); 40935244430SJian Shen kinfo->rss_size = min_t(u16, kinfo->num_tqps / num_tc, 410580a05f9SYonglong Liu kinfo->rss_size); 411580a05f9SYonglong Liu 412e2cb1decSSalil Mehta return 0; 413e2cb1decSSalil Mehta } 414e2cb1decSSalil Mehta 415e2cb1decSSalil Mehta static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 416e2cb1decSSalil Mehta { 417d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 418e2cb1decSSalil Mehta int status; 419e2cb1decSSalil Mehta 420d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_STATUS, 0); 421d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 422e2cb1decSSalil Mehta if (status) 423e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 424e2cb1decSSalil Mehta "VF failed to fetch link status(%d) from PF", status); 425e2cb1decSSalil Mehta } 426e2cb1decSSalil Mehta 427e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 428e2cb1decSSalil Mehta { 42945e92b7eSPeng Li struct hnae3_handle *rhandle = &hdev->roce; 430e2cb1decSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 43145e92b7eSPeng Li struct hnae3_client *rclient; 432e2cb1decSSalil Mehta struct hnae3_client *client; 433e2cb1decSSalil Mehta 434ff200099SYunsheng Lin if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state)) 435ff200099SYunsheng Lin return; 436ff200099SYunsheng Lin 437e2cb1decSSalil Mehta client = handle->client; 43845e92b7eSPeng Li rclient = hdev->roce_client; 439e2cb1decSSalil Mehta 440582d37bbSPeng Li link_state = 441582d37bbSPeng Li test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 442e2cb1decSSalil Mehta if (link_state != hdev->hw.mac.link) { 443b15c072aSYonglong Liu hdev->hw.mac.link = link_state; 444e2cb1decSSalil Mehta client->ops->link_status_change(handle, !!link_state); 44545e92b7eSPeng Li if (rclient && rclient->ops->link_status_change) 44645e92b7eSPeng Li rclient->ops->link_status_change(rhandle, !!link_state); 447e2cb1decSSalil Mehta } 448ff200099SYunsheng Lin 449ff200099SYunsheng Lin clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state); 450e2cb1decSSalil Mehta } 451e2cb1decSSalil Mehta 452538abaf3SYueHaibing static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 4539194d18bSliuzhongzhu { 4549194d18bSliuzhongzhu #define HCLGEVF_ADVERTISING 0 4559194d18bSliuzhongzhu #define HCLGEVF_SUPPORTED 1 4569194d18bSliuzhongzhu 457d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 458d3410018SYufeng Mo 459d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_MODE, 0); 460d3410018SYufeng Mo send_msg.data[0] = HCLGEVF_ADVERTISING; 461d3410018SYufeng Mo hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 462d3410018SYufeng Mo send_msg.data[0] = HCLGEVF_SUPPORTED; 463d3410018SYufeng Mo hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 4649194d18bSliuzhongzhu } 4659194d18bSliuzhongzhu 466e2cb1decSSalil Mehta static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 467e2cb1decSSalil Mehta { 468e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 469e2cb1decSSalil Mehta int ret; 470e2cb1decSSalil Mehta 471e2cb1decSSalil Mehta nic->ae_algo = &ae_algovf; 472e2cb1decSSalil Mehta nic->pdev = hdev->pdev; 473e2cb1decSSalil Mehta nic->numa_node_mask = hdev->numa_node_mask; 474424eb834SSalil Mehta nic->flags |= HNAE3_SUPPORT_VF; 475076bb537SJie Wang nic->kinfo.io_base = hdev->hw.hw.io_base; 476e2cb1decSSalil Mehta 477e2cb1decSSalil Mehta ret = hclgevf_knic_setup(hdev); 478e2cb1decSSalil Mehta if (ret) 479e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 480e2cb1decSSalil Mehta ret); 481e2cb1decSSalil Mehta return ret; 482e2cb1decSSalil Mehta } 483e2cb1decSSalil Mehta 484e2cb1decSSalil Mehta static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 485e2cb1decSSalil Mehta { 48636cbbdf6SPeng Li if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 48736cbbdf6SPeng Li dev_warn(&hdev->pdev->dev, 48836cbbdf6SPeng Li "vector(vector_id %d) has been freed.\n", vector_id); 48936cbbdf6SPeng Li return; 49036cbbdf6SPeng Li } 49136cbbdf6SPeng Li 492e2cb1decSSalil Mehta hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 493e2cb1decSSalil Mehta hdev->num_msi_left += 1; 494e2cb1decSSalil Mehta hdev->num_msi_used -= 1; 495e2cb1decSSalil Mehta } 496e2cb1decSSalil Mehta 497e2cb1decSSalil Mehta static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 498e2cb1decSSalil Mehta struct hnae3_vector_info *vector_info) 499e2cb1decSSalil Mehta { 500e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 501e2cb1decSSalil Mehta struct hnae3_vector_info *vector = vector_info; 502e2cb1decSSalil Mehta int alloc = 0; 503e2cb1decSSalil Mehta int i, j; 504e2cb1decSSalil Mehta 505580a05f9SYonglong Liu vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num); 506e2cb1decSSalil Mehta vector_num = min(hdev->num_msi_left, vector_num); 507e2cb1decSSalil Mehta 508e2cb1decSSalil Mehta for (j = 0; j < vector_num; j++) { 509e2cb1decSSalil Mehta for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 510e2cb1decSSalil Mehta if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 511e2cb1decSSalil Mehta vector->vector = pci_irq_vector(hdev->pdev, i); 512076bb537SJie Wang vector->io_addr = hdev->hw.hw.io_base + 513e2cb1decSSalil Mehta HCLGEVF_VECTOR_REG_BASE + 514e2cb1decSSalil Mehta (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 515e2cb1decSSalil Mehta hdev->vector_status[i] = 0; 516e2cb1decSSalil Mehta hdev->vector_irq[i] = vector->vector; 517e2cb1decSSalil Mehta 518e2cb1decSSalil Mehta vector++; 519e2cb1decSSalil Mehta alloc++; 520e2cb1decSSalil Mehta 521e2cb1decSSalil Mehta break; 522e2cb1decSSalil Mehta } 523e2cb1decSSalil Mehta } 524e2cb1decSSalil Mehta } 525e2cb1decSSalil Mehta hdev->num_msi_left -= alloc; 526e2cb1decSSalil Mehta hdev->num_msi_used += alloc; 527e2cb1decSSalil Mehta 528e2cb1decSSalil Mehta return alloc; 529e2cb1decSSalil Mehta } 530e2cb1decSSalil Mehta 531e2cb1decSSalil Mehta static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 532e2cb1decSSalil Mehta { 533e2cb1decSSalil Mehta int i; 534e2cb1decSSalil Mehta 535e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 536e2cb1decSSalil Mehta if (vector == hdev->vector_irq[i]) 537e2cb1decSSalil Mehta return i; 538e2cb1decSSalil Mehta 539e2cb1decSSalil Mehta return -EINVAL; 540e2cb1decSSalil Mehta } 541e2cb1decSSalil Mehta 542a638b1d8SJian Shen /* for revision 0x20, vf shared the same rss config with pf */ 543a638b1d8SJian Shen static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 544a638b1d8SJian Shen { 545a638b1d8SJian Shen #define HCLGEVF_RSS_MBX_RESP_LEN 8 546027733b1SJie Wang struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 547a638b1d8SJian Shen u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 548d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 549a638b1d8SJian Shen u16 msg_num, hash_key_index; 550a638b1d8SJian Shen u8 index; 551a638b1d8SJian Shen int ret; 552a638b1d8SJian Shen 553d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_RSS_KEY, 0); 5547428d6c9SJie Wang msg_num = (HCLGE_COMM_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 555a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN; 556a638b1d8SJian Shen for (index = 0; index < msg_num; index++) { 557d3410018SYufeng Mo send_msg.data[0] = index; 558d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 559a638b1d8SJian Shen HCLGEVF_RSS_MBX_RESP_LEN); 560a638b1d8SJian Shen if (ret) { 561a638b1d8SJian Shen dev_err(&hdev->pdev->dev, 562a638b1d8SJian Shen "VF get rss hash key from PF failed, ret=%d", 563a638b1d8SJian Shen ret); 564a638b1d8SJian Shen return ret; 565a638b1d8SJian Shen } 566a638b1d8SJian Shen 567a638b1d8SJian Shen hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 568a638b1d8SJian Shen if (index == msg_num - 1) 569a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 570a638b1d8SJian Shen &resp_msg[0], 5717428d6c9SJie Wang HCLGE_COMM_RSS_KEY_SIZE - hash_key_index); 572a638b1d8SJian Shen else 573a638b1d8SJian Shen memcpy(&rss_cfg->rss_hash_key[hash_key_index], 574a638b1d8SJian Shen &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 575a638b1d8SJian Shen } 576a638b1d8SJian Shen 577a638b1d8SJian Shen return 0; 578a638b1d8SJian Shen } 579a638b1d8SJian Shen 580e2cb1decSSalil Mehta static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 581e2cb1decSSalil Mehta u8 *hfunc) 582e2cb1decSSalil Mehta { 583e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 584027733b1SJie Wang struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 5857428d6c9SJie Wang int ret; 586e2cb1decSSalil Mehta 587295ba232SGuangbin Huang if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 5887428d6c9SJie Wang hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc); 589a638b1d8SJian Shen } else { 590a638b1d8SJian Shen if (hfunc) 591a638b1d8SJian Shen *hfunc = ETH_RSS_HASH_TOP; 592a638b1d8SJian Shen if (key) { 593a638b1d8SJian Shen ret = hclgevf_get_rss_hash_key(hdev); 594a638b1d8SJian Shen if (ret) 595a638b1d8SJian Shen return ret; 596a638b1d8SJian Shen memcpy(key, rss_cfg->rss_hash_key, 5977428d6c9SJie Wang HCLGE_COMM_RSS_KEY_SIZE); 598a638b1d8SJian Shen } 599374ad291SJian Shen } 600374ad291SJian Shen 6017428d6c9SJie Wang hclge_comm_get_rss_indir_tbl(rss_cfg, indir, 6027428d6c9SJie Wang hdev->ae_dev->dev_specs.rss_ind_tbl_size); 603e2cb1decSSalil Mehta 604374ad291SJian Shen return 0; 605e2cb1decSSalil Mehta } 606e2cb1decSSalil Mehta 607e2cb1decSSalil Mehta static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 608e2cb1decSSalil Mehta const u8 *key, const u8 hfunc) 609e2cb1decSSalil Mehta { 610e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 611027733b1SJie Wang struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 612374ad291SJian Shen int ret, i; 613374ad291SJian Shen 614295ba232SGuangbin Huang if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 61593969dc1SJie Wang ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, 61693969dc1SJie Wang hfunc); 617374ad291SJian Shen if (ret) 618374ad291SJian Shen return ret; 619374ad291SJian Shen } 620e2cb1decSSalil Mehta 621e2cb1decSSalil Mehta /* update the shadow RSS table with user specified qids */ 62287ce161eSGuangbin Huang for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 623e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = indir[i]; 624e2cb1decSSalil Mehta 625e2cb1decSSalil Mehta /* update the hardware */ 6267428d6c9SJie Wang return hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 6277428d6c9SJie Wang rss_cfg->rss_indirection_tbl); 6285fd0e7b4SHuazhong Tan } 6295fd0e7b4SHuazhong Tan 6305fd0e7b4SHuazhong Tan static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 6315fd0e7b4SHuazhong Tan struct ethtool_rxnfc *nfc) 6325fd0e7b4SHuazhong Tan { 6335fd0e7b4SHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 6345fd0e7b4SHuazhong Tan int ret; 6355fd0e7b4SHuazhong Tan 6365fd0e7b4SHuazhong Tan if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 6375fd0e7b4SHuazhong Tan return -EOPNOTSUPP; 6385fd0e7b4SHuazhong Tan 63993969dc1SJie Wang ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw, 64093969dc1SJie Wang &hdev->rss_cfg, nfc); 64193969dc1SJie Wang if (ret) 6425fd0e7b4SHuazhong Tan dev_err(&hdev->pdev->dev, 64393969dc1SJie Wang "failed to set rss tuple, ret = %d.\n", ret); 6445fd0e7b4SHuazhong Tan 645d97b3072SJian Shen return ret; 646d97b3072SJian Shen } 647d97b3072SJian Shen 648d97b3072SJian Shen static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 649d97b3072SJian Shen struct ethtool_rxnfc *nfc) 650d97b3072SJian Shen { 651d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 652d97b3072SJian Shen u8 tuple_sets; 65373f7767eSJian Shen int ret; 654d97b3072SJian Shen 655295ba232SGuangbin Huang if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 656d97b3072SJian Shen return -EOPNOTSUPP; 657d97b3072SJian Shen 658d97b3072SJian Shen nfc->data = 0; 659d97b3072SJian Shen 660027733b1SJie Wang ret = hclge_comm_get_rss_tuple(&hdev->rss_cfg, nfc->flow_type, 66173f7767eSJian Shen &tuple_sets); 66273f7767eSJian Shen if (ret || !tuple_sets) 66373f7767eSJian Shen return ret; 664d97b3072SJian Shen 6657428d6c9SJie Wang nfc->data = hclge_comm_convert_rss_tuple(tuple_sets); 666d97b3072SJian Shen 667d97b3072SJian Shen return 0; 668d97b3072SJian Shen } 669d97b3072SJian Shen 670e2cb1decSSalil Mehta static int hclgevf_get_tc_size(struct hnae3_handle *handle) 671e2cb1decSSalil Mehta { 672e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 673027733b1SJie Wang struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 674e2cb1decSSalil Mehta 675e2cb1decSSalil Mehta return rss_cfg->rss_size; 676e2cb1decSSalil Mehta } 677e2cb1decSSalil Mehta 678e2cb1decSSalil Mehta static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 679b204bc74SPeng Li int vector_id, 680e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 681e2cb1decSSalil Mehta { 682e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 683d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 684e2cb1decSSalil Mehta struct hnae3_ring_chain_node *node; 685e2cb1decSSalil Mehta int status; 686d3410018SYufeng Mo int i = 0; 687e2cb1decSSalil Mehta 688d3410018SYufeng Mo memset(&send_msg, 0, sizeof(send_msg)); 689d3410018SYufeng Mo send_msg.code = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 690c09ba484SPeng Li HCLGE_MBX_UNMAP_RING_TO_VECTOR; 691d3410018SYufeng Mo send_msg.vector_id = vector_id; 692e2cb1decSSalil Mehta 693e2cb1decSSalil Mehta for (node = ring_chain; node; node = node->next) { 694d3410018SYufeng Mo send_msg.param[i].ring_type = 695e4e87715SPeng Li hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 696d3410018SYufeng Mo 697d3410018SYufeng Mo send_msg.param[i].tqp_index = node->tqp_index; 698d3410018SYufeng Mo send_msg.param[i].int_gl_index = 699d3410018SYufeng Mo hnae3_get_field(node->int_gl_idx, 70079eee410SFuyun Liang HNAE3_RING_GL_IDX_M, 70179eee410SFuyun Liang HNAE3_RING_GL_IDX_S); 70279eee410SFuyun Liang 7035d02a58dSYunsheng Lin i++; 704d3410018SYufeng Mo if (i == HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM || !node->next) { 705d3410018SYufeng Mo send_msg.ring_num = i; 706e2cb1decSSalil Mehta 707d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, false, 708d3410018SYufeng Mo NULL, 0); 709e2cb1decSSalil Mehta if (status) { 710e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 711e2cb1decSSalil Mehta "Map TQP fail, status is %d.\n", 712e2cb1decSSalil Mehta status); 713e2cb1decSSalil Mehta return status; 714e2cb1decSSalil Mehta } 715e2cb1decSSalil Mehta i = 0; 716e2cb1decSSalil Mehta } 717e2cb1decSSalil Mehta } 718e2cb1decSSalil Mehta 719e2cb1decSSalil Mehta return 0; 720e2cb1decSSalil Mehta } 721e2cb1decSSalil Mehta 722e2cb1decSSalil Mehta static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 723e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 724e2cb1decSSalil Mehta { 725b204bc74SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 726b204bc74SPeng Li int vector_id; 727b204bc74SPeng Li 728b204bc74SPeng Li vector_id = hclgevf_get_vector_index(hdev, vector); 729b204bc74SPeng Li if (vector_id < 0) { 730b204bc74SPeng Li dev_err(&handle->pdev->dev, 731b204bc74SPeng Li "Get vector index fail. ret =%d\n", vector_id); 732b204bc74SPeng Li return vector_id; 733b204bc74SPeng Li } 734b204bc74SPeng Li 735b204bc74SPeng Li return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 736e2cb1decSSalil Mehta } 737e2cb1decSSalil Mehta 738e2cb1decSSalil Mehta static int hclgevf_unmap_ring_from_vector( 739e2cb1decSSalil Mehta struct hnae3_handle *handle, 740e2cb1decSSalil Mehta int vector, 741e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 742e2cb1decSSalil Mehta { 743e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 744e2cb1decSSalil Mehta int ret, vector_id; 745e2cb1decSSalil Mehta 746dea846e8SHuazhong Tan if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 747dea846e8SHuazhong Tan return 0; 748dea846e8SHuazhong Tan 749e2cb1decSSalil Mehta vector_id = hclgevf_get_vector_index(hdev, vector); 750e2cb1decSSalil Mehta if (vector_id < 0) { 751e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 752e2cb1decSSalil Mehta "Get vector index fail. ret =%d\n", vector_id); 753e2cb1decSSalil Mehta return vector_id; 754e2cb1decSSalil Mehta } 755e2cb1decSSalil Mehta 756b204bc74SPeng Li ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 7570d3e6631SYunsheng Lin if (ret) 758e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 759e2cb1decSSalil Mehta "Unmap ring from vector fail. vector=%d, ret =%d\n", 760e2cb1decSSalil Mehta vector_id, 761e2cb1decSSalil Mehta ret); 7620d3e6631SYunsheng Lin 763e2cb1decSSalil Mehta return ret; 764e2cb1decSSalil Mehta } 765e2cb1decSSalil Mehta 7660d3e6631SYunsheng Lin static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 7670d3e6631SYunsheng Lin { 7680d3e6631SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 76903718db9SYunsheng Lin int vector_id; 7700d3e6631SYunsheng Lin 77103718db9SYunsheng Lin vector_id = hclgevf_get_vector_index(hdev, vector); 77203718db9SYunsheng Lin if (vector_id < 0) { 77303718db9SYunsheng Lin dev_err(&handle->pdev->dev, 77403718db9SYunsheng Lin "hclgevf_put_vector get vector index fail. ret =%d\n", 77503718db9SYunsheng Lin vector_id); 77603718db9SYunsheng Lin return vector_id; 77703718db9SYunsheng Lin } 77803718db9SYunsheng Lin 77903718db9SYunsheng Lin hclgevf_free_vector(hdev, vector_id); 780e2cb1decSSalil Mehta 781e2cb1decSSalil Mehta return 0; 782e2cb1decSSalil Mehta } 783e2cb1decSSalil Mehta 7843b75c3dfSPeng Li static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 785e196ec75SJian Shen bool en_uc_pmc, bool en_mc_pmc, 786f01f5559SJian Shen bool en_bc_pmc) 787e2cb1decSSalil Mehta { 7885e7414cdSJian Shen struct hnae3_handle *handle = &hdev->nic; 789d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 790f01f5559SJian Shen int ret; 791e2cb1decSSalil Mehta 792d3410018SYufeng Mo memset(&send_msg, 0, sizeof(send_msg)); 793d3410018SYufeng Mo send_msg.code = HCLGE_MBX_SET_PROMISC_MODE; 794d3410018SYufeng Mo send_msg.en_bc = en_bc_pmc ? 1 : 0; 795d3410018SYufeng Mo send_msg.en_uc = en_uc_pmc ? 1 : 0; 796d3410018SYufeng Mo send_msg.en_mc = en_mc_pmc ? 1 : 0; 7975e7414cdSJian Shen send_msg.en_limit_promisc = test_bit(HNAE3_PFLAG_LIMIT_PROMISC, 7985e7414cdSJian Shen &handle->priv_flags) ? 1 : 0; 799e2cb1decSSalil Mehta 800d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 801f01f5559SJian Shen if (ret) 802e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 803f01f5559SJian Shen "Set promisc mode fail, status is %d.\n", ret); 804e2cb1decSSalil Mehta 805f01f5559SJian Shen return ret; 806e2cb1decSSalil Mehta } 807e2cb1decSSalil Mehta 808e196ec75SJian Shen static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 809e196ec75SJian Shen bool en_mc_pmc) 810e2cb1decSSalil Mehta { 811e196ec75SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 812e196ec75SJian Shen bool en_bc_pmc; 813e196ec75SJian Shen 814295ba232SGuangbin Huang en_bc_pmc = hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2; 815e196ec75SJian Shen 816e196ec75SJian Shen return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc, 817e196ec75SJian Shen en_bc_pmc); 818e2cb1decSSalil Mehta } 819e2cb1decSSalil Mehta 820c631c696SJian Shen static void hclgevf_request_update_promisc_mode(struct hnae3_handle *handle) 821c631c696SJian Shen { 822c631c696SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 823c631c696SJian Shen 824c631c696SJian Shen set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 8255e7414cdSJian Shen hclgevf_task_schedule(hdev, 0); 826c631c696SJian Shen } 827c631c696SJian Shen 828c631c696SJian Shen static void hclgevf_sync_promisc_mode(struct hclgevf_dev *hdev) 829c631c696SJian Shen { 830c631c696SJian Shen struct hnae3_handle *handle = &hdev->nic; 831c631c696SJian Shen bool en_uc_pmc = handle->netdev_flags & HNAE3_UPE; 832c631c696SJian Shen bool en_mc_pmc = handle->netdev_flags & HNAE3_MPE; 833c631c696SJian Shen int ret; 834c631c696SJian Shen 835c631c696SJian Shen if (test_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state)) { 836c631c696SJian Shen ret = hclgevf_set_promisc_mode(handle, en_uc_pmc, en_mc_pmc); 837c631c696SJian Shen if (!ret) 838c631c696SJian Shen clear_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 839c631c696SJian Shen } 840c631c696SJian Shen } 841c631c696SJian Shen 8428fa86551SYufeng Mo static int hclgevf_tqp_enable_cmd_send(struct hclgevf_dev *hdev, u16 tqp_id, 8438fa86551SYufeng Mo u16 stream_id, bool enable) 844e2cb1decSSalil Mehta { 845e2cb1decSSalil Mehta struct hclgevf_cfg_com_tqp_queue_cmd *req; 8466befad60SJie Wang struct hclge_desc desc; 847e2cb1decSSalil Mehta 848e2cb1decSSalil Mehta req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 849e2cb1decSSalil Mehta 85043710bfeSJie Wang hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); 851e2cb1decSSalil Mehta req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 852e2cb1decSSalil Mehta req->stream_id = cpu_to_le16(stream_id); 853ebaf1908SWeihang Li if (enable) 854ebaf1908SWeihang Li req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 855e2cb1decSSalil Mehta 8568fa86551SYufeng Mo return hclgevf_cmd_send(&hdev->hw, &desc, 1); 8578fa86551SYufeng Mo } 858e2cb1decSSalil Mehta 8598fa86551SYufeng Mo static int hclgevf_tqp_enable(struct hnae3_handle *handle, bool enable) 8608fa86551SYufeng Mo { 8618fa86551SYufeng Mo struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 8628fa86551SYufeng Mo int ret; 8638fa86551SYufeng Mo u16 i; 8648fa86551SYufeng Mo 8658fa86551SYufeng Mo for (i = 0; i < handle->kinfo.num_tqps; i++) { 8668fa86551SYufeng Mo ret = hclgevf_tqp_enable_cmd_send(hdev, i, 0, enable); 8678fa86551SYufeng Mo if (ret) 8688fa86551SYufeng Mo return ret; 8698fa86551SYufeng Mo } 8708fa86551SYufeng Mo 8718fa86551SYufeng Mo return 0; 872e2cb1decSSalil Mehta } 873e2cb1decSSalil Mehta 8748e6de441SHuazhong Tan static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p) 8758e6de441SHuazhong Tan { 876d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 8778e6de441SHuazhong Tan u8 host_mac[ETH_ALEN]; 8788e6de441SHuazhong Tan int status; 8798e6de441SHuazhong Tan 880d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MAC_ADDR, 0); 881d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, true, host_mac, 882d3410018SYufeng Mo ETH_ALEN); 8838e6de441SHuazhong Tan if (status) { 8848e6de441SHuazhong Tan dev_err(&hdev->pdev->dev, 8858e6de441SHuazhong Tan "fail to get VF MAC from host %d", status); 8868e6de441SHuazhong Tan return status; 8878e6de441SHuazhong Tan } 8888e6de441SHuazhong Tan 8898e6de441SHuazhong Tan ether_addr_copy(p, host_mac); 8908e6de441SHuazhong Tan 8918e6de441SHuazhong Tan return 0; 8928e6de441SHuazhong Tan } 8938e6de441SHuazhong Tan 894e2cb1decSSalil Mehta static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 895e2cb1decSSalil Mehta { 896e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 8978e6de441SHuazhong Tan u8 host_mac_addr[ETH_ALEN]; 898e2cb1decSSalil Mehta 8998e6de441SHuazhong Tan if (hclgevf_get_host_mac_addr(hdev, host_mac_addr)) 9008e6de441SHuazhong Tan return; 9018e6de441SHuazhong Tan 9028e6de441SHuazhong Tan hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr); 9038e6de441SHuazhong Tan if (hdev->has_pf_mac) 9048e6de441SHuazhong Tan ether_addr_copy(p, host_mac_addr); 9058e6de441SHuazhong Tan else 906e2cb1decSSalil Mehta ether_addr_copy(p, hdev->hw.mac.mac_addr); 907e2cb1decSSalil Mehta } 908e2cb1decSSalil Mehta 90976660757SJakub Kicinski static int hclgevf_set_mac_addr(struct hnae3_handle *handle, const void *p, 91059098055SFuyun Liang bool is_first) 911e2cb1decSSalil Mehta { 912e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 913e2cb1decSSalil Mehta u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 914d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 915e2cb1decSSalil Mehta u8 *new_mac_addr = (u8 *)p; 916e2cb1decSSalil Mehta int status; 917e2cb1decSSalil Mehta 918d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 0); 919ee4bcd3bSJian Shen send_msg.subcode = HCLGE_MBX_MAC_VLAN_UC_MODIFY; 920d3410018SYufeng Mo ether_addr_copy(send_msg.data, new_mac_addr); 921ee4bcd3bSJian Shen if (is_first && !hdev->has_pf_mac) 922ee4bcd3bSJian Shen eth_zero_addr(&send_msg.data[ETH_ALEN]); 923ee4bcd3bSJian Shen else 924d3410018SYufeng Mo ether_addr_copy(&send_msg.data[ETH_ALEN], old_mac_addr); 925d3410018SYufeng Mo status = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 926e2cb1decSSalil Mehta if (!status) 927e2cb1decSSalil Mehta ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 928e2cb1decSSalil Mehta 929e2cb1decSSalil Mehta return status; 930e2cb1decSSalil Mehta } 931e2cb1decSSalil Mehta 932ee4bcd3bSJian Shen static struct hclgevf_mac_addr_node * 933ee4bcd3bSJian Shen hclgevf_find_mac_node(struct list_head *list, const u8 *mac_addr) 934ee4bcd3bSJian Shen { 935ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp; 936ee4bcd3bSJian Shen 937ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, list, node) 938ee4bcd3bSJian Shen if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 939ee4bcd3bSJian Shen return mac_node; 940ee4bcd3bSJian Shen 941ee4bcd3bSJian Shen return NULL; 942ee4bcd3bSJian Shen } 943ee4bcd3bSJian Shen 944ee4bcd3bSJian Shen static void hclgevf_update_mac_node(struct hclgevf_mac_addr_node *mac_node, 945ee4bcd3bSJian Shen enum HCLGEVF_MAC_NODE_STATE state) 946ee4bcd3bSJian Shen { 947ee4bcd3bSJian Shen switch (state) { 948ee4bcd3bSJian Shen /* from set_rx_mode or tmp_add_list */ 949ee4bcd3bSJian Shen case HCLGEVF_MAC_TO_ADD: 950ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_DEL) 951ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_ACTIVE; 952ee4bcd3bSJian Shen break; 953ee4bcd3bSJian Shen /* only from set_rx_mode */ 954ee4bcd3bSJian Shen case HCLGEVF_MAC_TO_DEL: 955ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 956ee4bcd3bSJian Shen list_del(&mac_node->node); 957ee4bcd3bSJian Shen kfree(mac_node); 958ee4bcd3bSJian Shen } else { 959ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_TO_DEL; 960ee4bcd3bSJian Shen } 961ee4bcd3bSJian Shen break; 962ee4bcd3bSJian Shen /* only from tmp_add_list, the mac_node->state won't be 963ee4bcd3bSJian Shen * HCLGEVF_MAC_ACTIVE 964ee4bcd3bSJian Shen */ 965ee4bcd3bSJian Shen case HCLGEVF_MAC_ACTIVE: 966ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) 967ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_ACTIVE; 968ee4bcd3bSJian Shen break; 969ee4bcd3bSJian Shen } 970ee4bcd3bSJian Shen } 971ee4bcd3bSJian Shen 972ee4bcd3bSJian Shen static int hclgevf_update_mac_list(struct hnae3_handle *handle, 973ee4bcd3bSJian Shen enum HCLGEVF_MAC_NODE_STATE state, 974ee4bcd3bSJian Shen enum HCLGEVF_MAC_ADDR_TYPE mac_type, 975e2cb1decSSalil Mehta const unsigned char *addr) 976e2cb1decSSalil Mehta { 977e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 978ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node; 979ee4bcd3bSJian Shen struct list_head *list; 980e2cb1decSSalil Mehta 981ee4bcd3bSJian Shen list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 982ee4bcd3bSJian Shen &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 983ee4bcd3bSJian Shen 984ee4bcd3bSJian Shen spin_lock_bh(&hdev->mac_table.mac_list_lock); 985ee4bcd3bSJian Shen 986ee4bcd3bSJian Shen /* if the mac addr is already in the mac list, no need to add a new 987ee4bcd3bSJian Shen * one into it, just check the mac addr state, convert it to a new 988ee4bcd3bSJian Shen * new state, or just remove it, or do nothing. 989ee4bcd3bSJian Shen */ 990ee4bcd3bSJian Shen mac_node = hclgevf_find_mac_node(list, addr); 991ee4bcd3bSJian Shen if (mac_node) { 992ee4bcd3bSJian Shen hclgevf_update_mac_node(mac_node, state); 993ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 994ee4bcd3bSJian Shen return 0; 995ee4bcd3bSJian Shen } 996ee4bcd3bSJian Shen /* if this address is never added, unnecessary to delete */ 997ee4bcd3bSJian Shen if (state == HCLGEVF_MAC_TO_DEL) { 998ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 999ee4bcd3bSJian Shen return -ENOENT; 1000ee4bcd3bSJian Shen } 1001ee4bcd3bSJian Shen 1002ee4bcd3bSJian Shen mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 1003ee4bcd3bSJian Shen if (!mac_node) { 1004ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1005ee4bcd3bSJian Shen return -ENOMEM; 1006ee4bcd3bSJian Shen } 1007ee4bcd3bSJian Shen 1008ee4bcd3bSJian Shen mac_node->state = state; 1009ee4bcd3bSJian Shen ether_addr_copy(mac_node->mac_addr, addr); 1010ee4bcd3bSJian Shen list_add_tail(&mac_node->node, list); 1011ee4bcd3bSJian Shen 1012ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1013ee4bcd3bSJian Shen return 0; 1014ee4bcd3bSJian Shen } 1015ee4bcd3bSJian Shen 1016ee4bcd3bSJian Shen static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1017ee4bcd3bSJian Shen const unsigned char *addr) 1018ee4bcd3bSJian Shen { 1019ee4bcd3bSJian Shen return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1020ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_UC, addr); 1021e2cb1decSSalil Mehta } 1022e2cb1decSSalil Mehta 1023e2cb1decSSalil Mehta static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1024e2cb1decSSalil Mehta const unsigned char *addr) 1025e2cb1decSSalil Mehta { 1026ee4bcd3bSJian Shen return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1027ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_UC, addr); 1028e2cb1decSSalil Mehta } 1029e2cb1decSSalil Mehta 1030e2cb1decSSalil Mehta static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1031e2cb1decSSalil Mehta const unsigned char *addr) 1032e2cb1decSSalil Mehta { 1033ee4bcd3bSJian Shen return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1034ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_MC, addr); 1035e2cb1decSSalil Mehta } 1036e2cb1decSSalil Mehta 1037e2cb1decSSalil Mehta static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1038e2cb1decSSalil Mehta const unsigned char *addr) 1039e2cb1decSSalil Mehta { 1040ee4bcd3bSJian Shen return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1041ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_MC, addr); 1042ee4bcd3bSJian Shen } 1043e2cb1decSSalil Mehta 1044ee4bcd3bSJian Shen static int hclgevf_add_del_mac_addr(struct hclgevf_dev *hdev, 1045ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, 1046ee4bcd3bSJian Shen enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1047ee4bcd3bSJian Shen { 1048ee4bcd3bSJian Shen struct hclge_vf_to_pf_msg send_msg; 1049ee4bcd3bSJian Shen u8 code, subcode; 1050ee4bcd3bSJian Shen 1051ee4bcd3bSJian Shen if (mac_type == HCLGEVF_MAC_ADDR_UC) { 1052ee4bcd3bSJian Shen code = HCLGE_MBX_SET_UNICAST; 1053ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1054ee4bcd3bSJian Shen subcode = HCLGE_MBX_MAC_VLAN_UC_ADD; 1055ee4bcd3bSJian Shen else 1056ee4bcd3bSJian Shen subcode = HCLGE_MBX_MAC_VLAN_UC_REMOVE; 1057ee4bcd3bSJian Shen } else { 1058ee4bcd3bSJian Shen code = HCLGE_MBX_SET_MULTICAST; 1059ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1060ee4bcd3bSJian Shen subcode = HCLGE_MBX_MAC_VLAN_MC_ADD; 1061ee4bcd3bSJian Shen else 1062ee4bcd3bSJian Shen subcode = HCLGE_MBX_MAC_VLAN_MC_REMOVE; 1063ee4bcd3bSJian Shen } 1064ee4bcd3bSJian Shen 1065ee4bcd3bSJian Shen hclgevf_build_send_msg(&send_msg, code, subcode); 1066ee4bcd3bSJian Shen ether_addr_copy(send_msg.data, mac_node->mac_addr); 1067d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1068e2cb1decSSalil Mehta } 1069e2cb1decSSalil Mehta 1070ee4bcd3bSJian Shen static void hclgevf_config_mac_list(struct hclgevf_dev *hdev, 1071ee4bcd3bSJian Shen struct list_head *list, 1072ee4bcd3bSJian Shen enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1073ee4bcd3bSJian Shen { 10744f331fdaSYufeng Mo char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 1075ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp; 1076ee4bcd3bSJian Shen int ret; 1077ee4bcd3bSJian Shen 1078ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, list, node) { 1079ee4bcd3bSJian Shen ret = hclgevf_add_del_mac_addr(hdev, mac_node, mac_type); 1080ee4bcd3bSJian Shen if (ret) { 10814f331fdaSYufeng Mo hnae3_format_mac_addr(format_mac_addr, 10824f331fdaSYufeng Mo mac_node->mac_addr); 1083ee4bcd3bSJian Shen dev_err(&hdev->pdev->dev, 10844f331fdaSYufeng Mo "failed to configure mac %s, state = %d, ret = %d\n", 10854f331fdaSYufeng Mo format_mac_addr, mac_node->state, ret); 1086ee4bcd3bSJian Shen return; 1087ee4bcd3bSJian Shen } 1088ee4bcd3bSJian Shen if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1089ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_ACTIVE; 1090ee4bcd3bSJian Shen } else { 1091ee4bcd3bSJian Shen list_del(&mac_node->node); 1092ee4bcd3bSJian Shen kfree(mac_node); 1093ee4bcd3bSJian Shen } 1094ee4bcd3bSJian Shen } 1095ee4bcd3bSJian Shen } 1096ee4bcd3bSJian Shen 1097ee4bcd3bSJian Shen static void hclgevf_sync_from_add_list(struct list_head *add_list, 1098ee4bcd3bSJian Shen struct list_head *mac_list) 1099ee4bcd3bSJian Shen { 1100ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1101ee4bcd3bSJian Shen 1102ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, add_list, node) { 1103ee4bcd3bSJian Shen /* if the mac address from tmp_add_list is not in the 1104ee4bcd3bSJian Shen * uc/mc_mac_list, it means have received a TO_DEL request 1105ee4bcd3bSJian Shen * during the time window of sending mac config request to PF 1106ee4bcd3bSJian Shen * If mac_node state is ACTIVE, then change its state to TO_DEL, 1107ee4bcd3bSJian Shen * then it will be removed at next time. If is TO_ADD, it means 1108ee4bcd3bSJian Shen * send TO_ADD request failed, so just remove the mac node. 1109ee4bcd3bSJian Shen */ 1110ee4bcd3bSJian Shen new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1111ee4bcd3bSJian Shen if (new_node) { 1112ee4bcd3bSJian Shen hclgevf_update_mac_node(new_node, mac_node->state); 1113ee4bcd3bSJian Shen list_del(&mac_node->node); 1114ee4bcd3bSJian Shen kfree(mac_node); 1115ee4bcd3bSJian Shen } else if (mac_node->state == HCLGEVF_MAC_ACTIVE) { 1116ee4bcd3bSJian Shen mac_node->state = HCLGEVF_MAC_TO_DEL; 111749768ce9SBaokun Li list_move_tail(&mac_node->node, mac_list); 1118ee4bcd3bSJian Shen } else { 1119ee4bcd3bSJian Shen list_del(&mac_node->node); 1120ee4bcd3bSJian Shen kfree(mac_node); 1121ee4bcd3bSJian Shen } 1122ee4bcd3bSJian Shen } 1123ee4bcd3bSJian Shen } 1124ee4bcd3bSJian Shen 1125ee4bcd3bSJian Shen static void hclgevf_sync_from_del_list(struct list_head *del_list, 1126ee4bcd3bSJian Shen struct list_head *mac_list) 1127ee4bcd3bSJian Shen { 1128ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1129ee4bcd3bSJian Shen 1130ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, del_list, node) { 1131ee4bcd3bSJian Shen new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1132ee4bcd3bSJian Shen if (new_node) { 1133ee4bcd3bSJian Shen /* If the mac addr is exist in the mac list, it means 1134ee4bcd3bSJian Shen * received a new request TO_ADD during the time window 1135ee4bcd3bSJian Shen * of sending mac addr configurrequest to PF, so just 1136ee4bcd3bSJian Shen * change the mac state to ACTIVE. 1137ee4bcd3bSJian Shen */ 1138ee4bcd3bSJian Shen new_node->state = HCLGEVF_MAC_ACTIVE; 1139ee4bcd3bSJian Shen list_del(&mac_node->node); 1140ee4bcd3bSJian Shen kfree(mac_node); 1141ee4bcd3bSJian Shen } else { 114249768ce9SBaokun Li list_move_tail(&mac_node->node, mac_list); 1143ee4bcd3bSJian Shen } 1144ee4bcd3bSJian Shen } 1145ee4bcd3bSJian Shen } 1146ee4bcd3bSJian Shen 1147ee4bcd3bSJian Shen static void hclgevf_clear_list(struct list_head *list) 1148ee4bcd3bSJian Shen { 1149ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp; 1150ee4bcd3bSJian Shen 1151ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, list, node) { 1152ee4bcd3bSJian Shen list_del(&mac_node->node); 1153ee4bcd3bSJian Shen kfree(mac_node); 1154ee4bcd3bSJian Shen } 1155ee4bcd3bSJian Shen } 1156ee4bcd3bSJian Shen 1157ee4bcd3bSJian Shen static void hclgevf_sync_mac_list(struct hclgevf_dev *hdev, 1158ee4bcd3bSJian Shen enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1159ee4bcd3bSJian Shen { 1160ee4bcd3bSJian Shen struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1161ee4bcd3bSJian Shen struct list_head tmp_add_list, tmp_del_list; 1162ee4bcd3bSJian Shen struct list_head *list; 1163ee4bcd3bSJian Shen 1164ee4bcd3bSJian Shen INIT_LIST_HEAD(&tmp_add_list); 1165ee4bcd3bSJian Shen INIT_LIST_HEAD(&tmp_del_list); 1166ee4bcd3bSJian Shen 1167ee4bcd3bSJian Shen /* move the mac addr to the tmp_add_list and tmp_del_list, then 1168ee4bcd3bSJian Shen * we can add/delete these mac addr outside the spin lock 1169ee4bcd3bSJian Shen */ 1170ee4bcd3bSJian Shen list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1171ee4bcd3bSJian Shen &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1172ee4bcd3bSJian Shen 1173ee4bcd3bSJian Shen spin_lock_bh(&hdev->mac_table.mac_list_lock); 1174ee4bcd3bSJian Shen 1175ee4bcd3bSJian Shen list_for_each_entry_safe(mac_node, tmp, list, node) { 1176ee4bcd3bSJian Shen switch (mac_node->state) { 1177ee4bcd3bSJian Shen case HCLGEVF_MAC_TO_DEL: 117849768ce9SBaokun Li list_move_tail(&mac_node->node, &tmp_del_list); 1179ee4bcd3bSJian Shen break; 1180ee4bcd3bSJian Shen case HCLGEVF_MAC_TO_ADD: 1181ee4bcd3bSJian Shen new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 1182ee4bcd3bSJian Shen if (!new_node) 1183ee4bcd3bSJian Shen goto stop_traverse; 1184ee4bcd3bSJian Shen 1185ee4bcd3bSJian Shen ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 1186ee4bcd3bSJian Shen new_node->state = mac_node->state; 1187ee4bcd3bSJian Shen list_add_tail(&new_node->node, &tmp_add_list); 1188ee4bcd3bSJian Shen break; 1189ee4bcd3bSJian Shen default: 1190ee4bcd3bSJian Shen break; 1191ee4bcd3bSJian Shen } 1192ee4bcd3bSJian Shen } 1193ee4bcd3bSJian Shen 1194ee4bcd3bSJian Shen stop_traverse: 1195ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1196ee4bcd3bSJian Shen 1197ee4bcd3bSJian Shen /* delete first, in order to get max mac table space for adding */ 1198ee4bcd3bSJian Shen hclgevf_config_mac_list(hdev, &tmp_del_list, mac_type); 1199ee4bcd3bSJian Shen hclgevf_config_mac_list(hdev, &tmp_add_list, mac_type); 1200ee4bcd3bSJian Shen 1201ee4bcd3bSJian Shen /* if some mac addresses were added/deleted fail, move back to the 1202ee4bcd3bSJian Shen * mac_list, and retry at next time. 1203ee4bcd3bSJian Shen */ 1204ee4bcd3bSJian Shen spin_lock_bh(&hdev->mac_table.mac_list_lock); 1205ee4bcd3bSJian Shen 1206ee4bcd3bSJian Shen hclgevf_sync_from_del_list(&tmp_del_list, list); 1207ee4bcd3bSJian Shen hclgevf_sync_from_add_list(&tmp_add_list, list); 1208ee4bcd3bSJian Shen 1209ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1210ee4bcd3bSJian Shen } 1211ee4bcd3bSJian Shen 1212ee4bcd3bSJian Shen static void hclgevf_sync_mac_table(struct hclgevf_dev *hdev) 1213ee4bcd3bSJian Shen { 1214ee4bcd3bSJian Shen hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_UC); 1215ee4bcd3bSJian Shen hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_MC); 1216ee4bcd3bSJian Shen } 1217ee4bcd3bSJian Shen 1218ee4bcd3bSJian Shen static void hclgevf_uninit_mac_list(struct hclgevf_dev *hdev) 1219ee4bcd3bSJian Shen { 1220ee4bcd3bSJian Shen spin_lock_bh(&hdev->mac_table.mac_list_lock); 1221ee4bcd3bSJian Shen 1222ee4bcd3bSJian Shen hclgevf_clear_list(&hdev->mac_table.uc_mac_list); 1223ee4bcd3bSJian Shen hclgevf_clear_list(&hdev->mac_table.mc_mac_list); 1224ee4bcd3bSJian Shen 1225ee4bcd3bSJian Shen spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1226ee4bcd3bSJian Shen } 1227ee4bcd3bSJian Shen 1228fa6a262aSJian Shen static int hclgevf_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 1229fa6a262aSJian Shen { 1230fa6a262aSJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1231fa6a262aSJian Shen struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 1232fa6a262aSJian Shen struct hclge_vf_to_pf_msg send_msg; 1233fa6a262aSJian Shen 1234fa6a262aSJian Shen if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 1235fa6a262aSJian Shen return -EOPNOTSUPP; 1236fa6a262aSJian Shen 1237fa6a262aSJian Shen hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1238fa6a262aSJian Shen HCLGE_MBX_ENABLE_VLAN_FILTER); 1239fa6a262aSJian Shen send_msg.data[0] = enable ? 1 : 0; 1240fa6a262aSJian Shen 1241fa6a262aSJian Shen return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1242fa6a262aSJian Shen } 1243fa6a262aSJian Shen 1244e2cb1decSSalil Mehta static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1245e2cb1decSSalil Mehta __be16 proto, u16 vlan_id, 1246e2cb1decSSalil Mehta bool is_kill) 1247e2cb1decSSalil Mehta { 1248d3410018SYufeng Mo #define HCLGEVF_VLAN_MBX_IS_KILL_OFFSET 0 1249d3410018SYufeng Mo #define HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET 1 1250d3410018SYufeng Mo #define HCLGEVF_VLAN_MBX_PROTO_OFFSET 3 1251d3410018SYufeng Mo 1252e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1253d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1254fe4144d4SJian Shen int ret; 1255e2cb1decSSalil Mehta 1256b37ce587SYufeng Mo if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1257e2cb1decSSalil Mehta return -EINVAL; 1258e2cb1decSSalil Mehta 1259e2cb1decSSalil Mehta if (proto != htons(ETH_P_8021Q)) 1260e2cb1decSSalil Mehta return -EPROTONOSUPPORT; 1261e2cb1decSSalil Mehta 1262b7b5d25bSGuojia Liao /* When device is resetting or reset failed, firmware is unable to 1263b7b5d25bSGuojia Liao * handle mailbox. Just record the vlan id, and remove it after 1264fe4144d4SJian Shen * reset finished. 1265fe4144d4SJian Shen */ 1266b7b5d25bSGuojia Liao if ((test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 1267b7b5d25bSGuojia Liao test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) && is_kill) { 1268fe4144d4SJian Shen set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1269fe4144d4SJian Shen return -EBUSY; 1270fe4144d4SJian Shen } 1271fe4144d4SJian Shen 1272d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1273d3410018SYufeng Mo HCLGE_MBX_VLAN_FILTER); 1274d3410018SYufeng Mo send_msg.data[HCLGEVF_VLAN_MBX_IS_KILL_OFFSET] = is_kill; 1275d3410018SYufeng Mo memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET], &vlan_id, 1276d3410018SYufeng Mo sizeof(vlan_id)); 1277d3410018SYufeng Mo memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_PROTO_OFFSET], &proto, 1278d3410018SYufeng Mo sizeof(proto)); 127946ee7350SGuojia Liao /* when remove hw vlan filter failed, record the vlan id, 1280fe4144d4SJian Shen * and try to remove it from hw later, to be consistence 1281fe4144d4SJian Shen * with stack. 1282fe4144d4SJian Shen */ 1283d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1284fe4144d4SJian Shen if (is_kill && ret) 1285fe4144d4SJian Shen set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1286fe4144d4SJian Shen 1287fe4144d4SJian Shen return ret; 1288fe4144d4SJian Shen } 1289fe4144d4SJian Shen 1290fe4144d4SJian Shen static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1291fe4144d4SJian Shen { 1292fe4144d4SJian Shen #define HCLGEVF_MAX_SYNC_COUNT 60 1293fe4144d4SJian Shen struct hnae3_handle *handle = &hdev->nic; 1294fe4144d4SJian Shen int ret, sync_cnt = 0; 1295fe4144d4SJian Shen u16 vlan_id; 1296fe4144d4SJian Shen 1297fe4144d4SJian Shen vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1298fe4144d4SJian Shen while (vlan_id != VLAN_N_VID) { 1299fe4144d4SJian Shen ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1300fe4144d4SJian Shen vlan_id, true); 1301fe4144d4SJian Shen if (ret) 1302fe4144d4SJian Shen return; 1303fe4144d4SJian Shen 1304fe4144d4SJian Shen clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1305fe4144d4SJian Shen sync_cnt++; 1306fe4144d4SJian Shen if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1307fe4144d4SJian Shen return; 1308fe4144d4SJian Shen 1309fe4144d4SJian Shen vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1310fe4144d4SJian Shen } 1311e2cb1decSSalil Mehta } 1312e2cb1decSSalil Mehta 1313b2641e2aSYunsheng Lin static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1314b2641e2aSYunsheng Lin { 1315b2641e2aSYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1316d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1317b2641e2aSYunsheng Lin 1318d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1319d3410018SYufeng Mo HCLGE_MBX_VLAN_RX_OFF_CFG); 1320d3410018SYufeng Mo send_msg.data[0] = enable ? 1 : 0; 1321d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1322b2641e2aSYunsheng Lin } 1323b2641e2aSYunsheng Lin 13248fa86551SYufeng Mo static int hclgevf_reset_tqp(struct hnae3_handle *handle) 1325e2cb1decSSalil Mehta { 13268fa86551SYufeng Mo #define HCLGEVF_RESET_ALL_QUEUE_DONE 1U 1327e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1328d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 13298fa86551SYufeng Mo u8 return_status = 0; 13301a426f8bSPeng Li int ret; 13318fa86551SYufeng Mo u16 i; 1332e2cb1decSSalil Mehta 13331a426f8bSPeng Li /* disable vf queue before send queue reset msg to PF */ 13348fa86551SYufeng Mo ret = hclgevf_tqp_enable(handle, false); 13358fa86551SYufeng Mo if (ret) { 13368fa86551SYufeng Mo dev_err(&hdev->pdev->dev, "failed to disable tqp, ret = %d\n", 13378fa86551SYufeng Mo ret); 13387fa6be4fSHuazhong Tan return ret; 13398fa86551SYufeng Mo } 13401a426f8bSPeng Li 1341d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 13428fa86551SYufeng Mo 13438fa86551SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &return_status, 13448fa86551SYufeng Mo sizeof(return_status)); 13458fa86551SYufeng Mo if (ret || return_status == HCLGEVF_RESET_ALL_QUEUE_DONE) 13468fa86551SYufeng Mo return ret; 13478fa86551SYufeng Mo 13488fa86551SYufeng Mo for (i = 1; i < handle->kinfo.num_tqps; i++) { 13498fa86551SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 13508fa86551SYufeng Mo memcpy(send_msg.data, &i, sizeof(i)); 13518fa86551SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 13528fa86551SYufeng Mo if (ret) 13538fa86551SYufeng Mo return ret; 13548fa86551SYufeng Mo } 13558fa86551SYufeng Mo 13568fa86551SYufeng Mo return 0; 1357e2cb1decSSalil Mehta } 1358e2cb1decSSalil Mehta 1359818f1675SYunsheng Lin static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1360818f1675SYunsheng Lin { 1361818f1675SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1362d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1363818f1675SYunsheng Lin 1364d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MTU, 0); 1365d3410018SYufeng Mo memcpy(send_msg.data, &new_mtu, sizeof(new_mtu)); 1366d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1367818f1675SYunsheng Lin } 1368818f1675SYunsheng Lin 13696988eb2aSSalil Mehta static int hclgevf_notify_client(struct hclgevf_dev *hdev, 13706988eb2aSSalil Mehta enum hnae3_reset_notify_type type) 13716988eb2aSSalil Mehta { 13726988eb2aSSalil Mehta struct hnae3_client *client = hdev->nic_client; 13736988eb2aSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 13746a5f6fa3SHuazhong Tan int ret; 13756988eb2aSSalil Mehta 137625d1817cSHuazhong Tan if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 137725d1817cSHuazhong Tan !client) 137825d1817cSHuazhong Tan return 0; 137925d1817cSHuazhong Tan 13806988eb2aSSalil Mehta if (!client->ops->reset_notify) 13816988eb2aSSalil Mehta return -EOPNOTSUPP; 13826988eb2aSSalil Mehta 13836a5f6fa3SHuazhong Tan ret = client->ops->reset_notify(handle, type); 13846a5f6fa3SHuazhong Tan if (ret) 13856a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 13866a5f6fa3SHuazhong Tan type, ret); 13876a5f6fa3SHuazhong Tan 13886a5f6fa3SHuazhong Tan return ret; 13896988eb2aSSalil Mehta } 13906988eb2aSSalil Mehta 1391fe735c84SHuazhong Tan static int hclgevf_notify_roce_client(struct hclgevf_dev *hdev, 1392fe735c84SHuazhong Tan enum hnae3_reset_notify_type type) 1393fe735c84SHuazhong Tan { 1394fe735c84SHuazhong Tan struct hnae3_client *client = hdev->roce_client; 1395fe735c84SHuazhong Tan struct hnae3_handle *handle = &hdev->roce; 1396fe735c84SHuazhong Tan int ret; 1397fe735c84SHuazhong Tan 1398fe735c84SHuazhong Tan if (!test_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state) || !client) 1399fe735c84SHuazhong Tan return 0; 1400fe735c84SHuazhong Tan 1401fe735c84SHuazhong Tan if (!client->ops->reset_notify) 1402fe735c84SHuazhong Tan return -EOPNOTSUPP; 1403fe735c84SHuazhong Tan 1404fe735c84SHuazhong Tan ret = client->ops->reset_notify(handle, type); 1405fe735c84SHuazhong Tan if (ret) 1406fe735c84SHuazhong Tan dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 1407fe735c84SHuazhong Tan type, ret); 1408fe735c84SHuazhong Tan return ret; 1409fe735c84SHuazhong Tan } 1410fe735c84SHuazhong Tan 14116988eb2aSSalil Mehta static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 14126988eb2aSSalil Mehta { 1413aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_US 20000 1414aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_CNT 2000 1415aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1416aa5c4f17SHuazhong Tan (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1417aa5c4f17SHuazhong Tan 1418aa5c4f17SHuazhong Tan u32 val; 1419aa5c4f17SHuazhong Tan int ret; 14206988eb2aSSalil Mehta 1421f28368bbSHuazhong Tan if (hdev->reset_type == HNAE3_VF_RESET) 1422076bb537SJie Wang ret = readl_poll_timeout(hdev->hw.hw.io_base + 142372e2fb07SHuazhong Tan HCLGEVF_VF_RST_ING, val, 142472e2fb07SHuazhong Tan !(val & HCLGEVF_VF_RST_ING_BIT), 142572e2fb07SHuazhong Tan HCLGEVF_RESET_WAIT_US, 142672e2fb07SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 142772e2fb07SHuazhong Tan else 1428076bb537SJie Wang ret = readl_poll_timeout(hdev->hw.hw.io_base + 142972e2fb07SHuazhong Tan HCLGEVF_RST_ING, val, 1430aa5c4f17SHuazhong Tan !(val & HCLGEVF_RST_ING_BITS), 1431aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_US, 1432aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 14336988eb2aSSalil Mehta 14346988eb2aSSalil Mehta /* hardware completion status should be available by this time */ 1435aa5c4f17SHuazhong Tan if (ret) { 1436aa5c4f17SHuazhong Tan dev_err(&hdev->pdev->dev, 14378912fd6aSColin Ian King "couldn't get reset done status from h/w, timeout!\n"); 1438aa5c4f17SHuazhong Tan return ret; 14396988eb2aSSalil Mehta } 14406988eb2aSSalil Mehta 14416988eb2aSSalil Mehta /* we will wait a bit more to let reset of the stack to complete. This 14426988eb2aSSalil Mehta * might happen in case reset assertion was made by PF. Yes, this also 14436988eb2aSSalil Mehta * means we might end up waiting bit more even for VF reset. 14446988eb2aSSalil Mehta */ 14456988eb2aSSalil Mehta msleep(5000); 14466988eb2aSSalil Mehta 14476988eb2aSSalil Mehta return 0; 14486988eb2aSSalil Mehta } 14496988eb2aSSalil Mehta 14506b428b4fSHuazhong Tan static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable) 14516b428b4fSHuazhong Tan { 14526b428b4fSHuazhong Tan u32 reg_val; 14536b428b4fSHuazhong Tan 1454cb413bfaSJie Wang reg_val = hclgevf_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG); 14556b428b4fSHuazhong Tan if (enable) 14566b428b4fSHuazhong Tan reg_val |= HCLGEVF_NIC_SW_RST_RDY; 14576b428b4fSHuazhong Tan else 14586b428b4fSHuazhong Tan reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; 14596b428b4fSHuazhong Tan 1460cb413bfaSJie Wang hclgevf_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, 14616b428b4fSHuazhong Tan reg_val); 14626b428b4fSHuazhong Tan } 14636b428b4fSHuazhong Tan 14646988eb2aSSalil Mehta static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 14656988eb2aSSalil Mehta { 14667a01c897SSalil Mehta int ret; 14677a01c897SSalil Mehta 14686988eb2aSSalil Mehta /* uninitialize the nic client */ 14696a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 14706a5f6fa3SHuazhong Tan if (ret) 14716a5f6fa3SHuazhong Tan return ret; 14726988eb2aSSalil Mehta 14737a01c897SSalil Mehta /* re-initialize the hclge device */ 14749c6f7085SHuazhong Tan ret = hclgevf_reset_hdev(hdev); 14757a01c897SSalil Mehta if (ret) { 14767a01c897SSalil Mehta dev_err(&hdev->pdev->dev, 14777a01c897SSalil Mehta "hclge device re-init failed, VF is disabled!\n"); 14787a01c897SSalil Mehta return ret; 14797a01c897SSalil Mehta } 14806988eb2aSSalil Mehta 14816988eb2aSSalil Mehta /* bring up the nic client again */ 14826a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 14836a5f6fa3SHuazhong Tan if (ret) 14846a5f6fa3SHuazhong Tan return ret; 14856988eb2aSSalil Mehta 14866b428b4fSHuazhong Tan /* clear handshake status with IMP */ 14876b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, false); 14886b428b4fSHuazhong Tan 14891cc9bc6eSHuazhong Tan /* bring up the nic to enable TX/RX again */ 14901cc9bc6eSHuazhong Tan return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 14916988eb2aSSalil Mehta } 14926988eb2aSSalil Mehta 1493dea846e8SHuazhong Tan static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1494dea846e8SHuazhong Tan { 1495ada13ee3SHuazhong Tan #define HCLGEVF_RESET_SYNC_TIME 100 1496ada13ee3SHuazhong Tan 1497f28368bbSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FUNC_RESET) { 1498d41884eeSHuazhong Tan struct hclge_vf_to_pf_msg send_msg; 1499d41884eeSHuazhong Tan int ret; 1500d41884eeSHuazhong Tan 1501d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_RESET, 0); 1502d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1503cddd5648SHuazhong Tan if (ret) { 1504cddd5648SHuazhong Tan dev_err(&hdev->pdev->dev, 1505cddd5648SHuazhong Tan "failed to assert VF reset, ret = %d\n", ret); 1506cddd5648SHuazhong Tan return ret; 1507cddd5648SHuazhong Tan } 1508c88a6e7dSHuazhong Tan hdev->rst_stats.vf_func_rst_cnt++; 1509dea846e8SHuazhong Tan } 1510dea846e8SHuazhong Tan 1511076bb537SJie Wang set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 1512ada13ee3SHuazhong Tan /* inform hardware that preparatory work is done */ 1513ada13ee3SHuazhong Tan msleep(HCLGEVF_RESET_SYNC_TIME); 15146b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, true); 1515d41884eeSHuazhong Tan dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done\n", 1516d41884eeSHuazhong Tan hdev->reset_type); 1517dea846e8SHuazhong Tan 1518d41884eeSHuazhong Tan return 0; 1519dea846e8SHuazhong Tan } 1520dea846e8SHuazhong Tan 15213d77d0cbSHuazhong Tan static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev) 15223d77d0cbSHuazhong Tan { 15233d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "VF function reset count: %u\n", 15243d77d0cbSHuazhong Tan hdev->rst_stats.vf_func_rst_cnt); 15253d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "FLR reset count: %u\n", 15263d77d0cbSHuazhong Tan hdev->rst_stats.flr_rst_cnt); 15273d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "VF reset count: %u\n", 15283d77d0cbSHuazhong Tan hdev->rst_stats.vf_rst_cnt); 15293d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "reset done count: %u\n", 15303d77d0cbSHuazhong Tan hdev->rst_stats.rst_done_cnt); 15313d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "HW reset done count: %u\n", 15323d77d0cbSHuazhong Tan hdev->rst_stats.hw_rst_done_cnt); 15333d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "reset count: %u\n", 15343d77d0cbSHuazhong Tan hdev->rst_stats.rst_cnt); 15353d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "reset fail count: %u\n", 15363d77d0cbSHuazhong Tan hdev->rst_stats.rst_fail_cnt); 15373d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n", 15383d77d0cbSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE)); 15393d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n", 1540cb413bfaSJie Wang hclgevf_read_dev(&hdev->hw, HCLGE_COMM_VECTOR0_CMDQ_STATE_REG)); 15413d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n", 1542cb413bfaSJie Wang hclgevf_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG)); 15433d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n", 15443d77d0cbSHuazhong Tan hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING)); 15453d77d0cbSHuazhong Tan dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state); 15463d77d0cbSHuazhong Tan } 15473d77d0cbSHuazhong Tan 1548bbe6540eSHuazhong Tan static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1549bbe6540eSHuazhong Tan { 15506b428b4fSHuazhong Tan /* recover handshake status with IMP when reset fail */ 15516b428b4fSHuazhong Tan hclgevf_reset_handshake(hdev, true); 1552bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt++; 1553adcf738bSGuojia Liao dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n", 1554bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt); 1555bbe6540eSHuazhong Tan 1556bbe6540eSHuazhong Tan if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1557bbe6540eSHuazhong Tan set_bit(hdev->reset_type, &hdev->reset_pending); 1558bbe6540eSHuazhong Tan 1559bbe6540eSHuazhong Tan if (hclgevf_is_reset_pending(hdev)) { 1560bbe6540eSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1561bbe6540eSHuazhong Tan hclgevf_reset_task_schedule(hdev); 15623d77d0cbSHuazhong Tan } else { 1563d5432455SGuojia Liao set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 15643d77d0cbSHuazhong Tan hclgevf_dump_rst_info(hdev); 1565bbe6540eSHuazhong Tan } 1566bbe6540eSHuazhong Tan } 1567bbe6540eSHuazhong Tan 15681cc9bc6eSHuazhong Tan static int hclgevf_reset_prepare(struct hclgevf_dev *hdev) 15696988eb2aSSalil Mehta { 15706988eb2aSSalil Mehta int ret; 15716988eb2aSSalil Mehta 1572c88a6e7dSHuazhong Tan hdev->rst_stats.rst_cnt++; 15736988eb2aSSalil Mehta 1574fe735c84SHuazhong Tan /* perform reset of the stack & ae device for a client */ 1575fe735c84SHuazhong Tan ret = hclgevf_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 1576fe735c84SHuazhong Tan if (ret) 1577fe735c84SHuazhong Tan return ret; 1578fe735c84SHuazhong Tan 15791cc9bc6eSHuazhong Tan rtnl_lock(); 15806988eb2aSSalil Mehta /* bring down the nic to stop any ongoing TX/RX */ 15816a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 158229118ab9SHuazhong Tan rtnl_unlock(); 15836a5f6fa3SHuazhong Tan if (ret) 15841cc9bc6eSHuazhong Tan return ret; 1585dea846e8SHuazhong Tan 15861cc9bc6eSHuazhong Tan return hclgevf_reset_prepare_wait(hdev); 15876988eb2aSSalil Mehta } 15886988eb2aSSalil Mehta 15891cc9bc6eSHuazhong Tan static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev) 15901cc9bc6eSHuazhong Tan { 15911cc9bc6eSHuazhong Tan int ret; 15921cc9bc6eSHuazhong Tan 1593c88a6e7dSHuazhong Tan hdev->rst_stats.hw_rst_done_cnt++; 1594fe735c84SHuazhong Tan ret = hclgevf_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 1595fe735c84SHuazhong Tan if (ret) 1596fe735c84SHuazhong Tan return ret; 1597c88a6e7dSHuazhong Tan 159829118ab9SHuazhong Tan rtnl_lock(); 15996988eb2aSSalil Mehta /* now, re-initialize the nic client and ae device */ 16006988eb2aSSalil Mehta ret = hclgevf_reset_stack(hdev); 16011cc9bc6eSHuazhong Tan rtnl_unlock(); 16026a5f6fa3SHuazhong Tan if (ret) { 16036988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 16041cc9bc6eSHuazhong Tan return ret; 16056a5f6fa3SHuazhong Tan } 16066988eb2aSSalil Mehta 1607fe735c84SHuazhong Tan ret = hclgevf_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 1608fe735c84SHuazhong Tan /* ignore RoCE notify error if it fails HCLGEVF_RESET_MAX_FAIL_CNT - 1 1609fe735c84SHuazhong Tan * times 1610fe735c84SHuazhong Tan */ 1611fe735c84SHuazhong Tan if (ret && 1612fe735c84SHuazhong Tan hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT - 1) 1613fe735c84SHuazhong Tan return ret; 1614fe735c84SHuazhong Tan 1615fe735c84SHuazhong Tan ret = hclgevf_notify_roce_client(hdev, HNAE3_UP_CLIENT); 1616fe735c84SHuazhong Tan if (ret) 1617fe735c84SHuazhong Tan return ret; 1618fe735c84SHuazhong Tan 1619b644a8d4SHuazhong Tan hdev->last_reset_time = jiffies; 1620c88a6e7dSHuazhong Tan hdev->rst_stats.rst_done_cnt++; 1621bbe6540eSHuazhong Tan hdev->rst_stats.rst_fail_cnt = 0; 1622d5432455SGuojia Liao clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1623b644a8d4SHuazhong Tan 16241cc9bc6eSHuazhong Tan return 0; 16251cc9bc6eSHuazhong Tan } 16261cc9bc6eSHuazhong Tan 16271cc9bc6eSHuazhong Tan static void hclgevf_reset(struct hclgevf_dev *hdev) 16281cc9bc6eSHuazhong Tan { 16291cc9bc6eSHuazhong Tan if (hclgevf_reset_prepare(hdev)) 16301cc9bc6eSHuazhong Tan goto err_reset; 16311cc9bc6eSHuazhong Tan 16321cc9bc6eSHuazhong Tan /* check if VF could successfully fetch the hardware reset completion 16331cc9bc6eSHuazhong Tan * status from the hardware 16341cc9bc6eSHuazhong Tan */ 16351cc9bc6eSHuazhong Tan if (hclgevf_reset_wait(hdev)) { 16361cc9bc6eSHuazhong Tan /* can't do much in this situation, will disable VF */ 16371cc9bc6eSHuazhong Tan dev_err(&hdev->pdev->dev, 16381cc9bc6eSHuazhong Tan "failed to fetch H/W reset completion status\n"); 16391cc9bc6eSHuazhong Tan goto err_reset; 16401cc9bc6eSHuazhong Tan } 16411cc9bc6eSHuazhong Tan 16421cc9bc6eSHuazhong Tan if (hclgevf_reset_rebuild(hdev)) 16431cc9bc6eSHuazhong Tan goto err_reset; 16441cc9bc6eSHuazhong Tan 16451cc9bc6eSHuazhong Tan return; 16461cc9bc6eSHuazhong Tan 16476a5f6fa3SHuazhong Tan err_reset: 1648bbe6540eSHuazhong Tan hclgevf_reset_err_handle(hdev); 16496988eb2aSSalil Mehta } 16506988eb2aSSalil Mehta 1651720bd583SHuazhong Tan static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1652720bd583SHuazhong Tan unsigned long *addr) 1653720bd583SHuazhong Tan { 1654720bd583SHuazhong Tan enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1655720bd583SHuazhong Tan 1656dea846e8SHuazhong Tan /* return the highest priority reset level amongst all */ 1657b90fcc5bSHuazhong Tan if (test_bit(HNAE3_VF_RESET, addr)) { 1658b90fcc5bSHuazhong Tan rst_level = HNAE3_VF_RESET; 1659b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_RESET, addr); 1660b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1661b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1662b90fcc5bSHuazhong Tan } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1663dea846e8SHuazhong Tan rst_level = HNAE3_VF_FULL_RESET; 1664dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FULL_RESET, addr); 1665dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1666aa5c4f17SHuazhong Tan } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1667aa5c4f17SHuazhong Tan rst_level = HNAE3_VF_PF_FUNC_RESET; 1668aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1669aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1670dea846e8SHuazhong Tan } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1671dea846e8SHuazhong Tan rst_level = HNAE3_VF_FUNC_RESET; 1672dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 16736ff3cf07SHuazhong Tan } else if (test_bit(HNAE3_FLR_RESET, addr)) { 16746ff3cf07SHuazhong Tan rst_level = HNAE3_FLR_RESET; 16756ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_RESET, addr); 1676720bd583SHuazhong Tan } 1677720bd583SHuazhong Tan 1678720bd583SHuazhong Tan return rst_level; 1679720bd583SHuazhong Tan } 1680720bd583SHuazhong Tan 16816ae4e733SShiju Jose static void hclgevf_reset_event(struct pci_dev *pdev, 16826ae4e733SShiju Jose struct hnae3_handle *handle) 16836d4c3981SSalil Mehta { 16846ff3cf07SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 16856ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 16866d4c3981SSalil Mehta 16876d4c3981SSalil Mehta dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 16886d4c3981SSalil Mehta 16896ff3cf07SHuazhong Tan if (hdev->default_reset_request) 16900742ed7cSHuazhong Tan hdev->reset_level = 1691720bd583SHuazhong Tan hclgevf_get_reset_level(hdev, 1692720bd583SHuazhong Tan &hdev->default_reset_request); 1693720bd583SHuazhong Tan else 1694dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 16956d4c3981SSalil Mehta 1696436667d2SSalil Mehta /* reset of this VF requested */ 1697436667d2SSalil Mehta set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1698436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 16996d4c3981SSalil Mehta 17000742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 17016d4c3981SSalil Mehta } 17026d4c3981SSalil Mehta 1703720bd583SHuazhong Tan static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1704720bd583SHuazhong Tan enum hnae3_reset_type rst_type) 1705720bd583SHuazhong Tan { 1706720bd583SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1707720bd583SHuazhong Tan 1708720bd583SHuazhong Tan set_bit(rst_type, &hdev->default_reset_request); 1709720bd583SHuazhong Tan } 1710720bd583SHuazhong Tan 1711f28368bbSHuazhong Tan static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1712f28368bbSHuazhong Tan { 1713f28368bbSHuazhong Tan writel(en ? 1 : 0, vector->addr); 1714f28368bbSHuazhong Tan } 1715f28368bbSHuazhong Tan 1716bb1890d5SJiaran Zhang static void hclgevf_reset_prepare_general(struct hnae3_ae_dev *ae_dev, 1717bb1890d5SJiaran Zhang enum hnae3_reset_type rst_type) 17186ff3cf07SHuazhong Tan { 1719bb1890d5SJiaran Zhang #define HCLGEVF_RESET_RETRY_WAIT_MS 500 1720bb1890d5SJiaran Zhang #define HCLGEVF_RESET_RETRY_CNT 5 1721f28368bbSHuazhong Tan 17226ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1723f28368bbSHuazhong Tan int retry_cnt = 0; 1724f28368bbSHuazhong Tan int ret; 17256ff3cf07SHuazhong Tan 1726ed0e658cSJiaran Zhang while (retry_cnt++ < HCLGEVF_RESET_RETRY_CNT) { 1727f28368bbSHuazhong Tan down(&hdev->reset_sem); 1728f28368bbSHuazhong Tan set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1729bb1890d5SJiaran Zhang hdev->reset_type = rst_type; 1730f28368bbSHuazhong Tan ret = hclgevf_reset_prepare(hdev); 1731ed0e658cSJiaran Zhang if (!ret && !hdev->reset_pending) 1732ed0e658cSJiaran Zhang break; 1733ed0e658cSJiaran Zhang 17346ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 1735ed0e658cSJiaran Zhang "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n", 1736ed0e658cSJiaran Zhang ret, hdev->reset_pending, retry_cnt); 1737f28368bbSHuazhong Tan clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1738f28368bbSHuazhong Tan up(&hdev->reset_sem); 1739bb1890d5SJiaran Zhang msleep(HCLGEVF_RESET_RETRY_WAIT_MS); 1740f28368bbSHuazhong Tan } 1741f28368bbSHuazhong Tan 1742bb1890d5SJiaran Zhang /* disable misc vector before reset done */ 1743f28368bbSHuazhong Tan hclgevf_enable_vector(&hdev->misc_vector, false); 1744bb1890d5SJiaran Zhang 1745bb1890d5SJiaran Zhang if (hdev->reset_type == HNAE3_FLR_RESET) 1746f28368bbSHuazhong Tan hdev->rst_stats.flr_rst_cnt++; 1747f28368bbSHuazhong Tan } 1748f28368bbSHuazhong Tan 1749bb1890d5SJiaran Zhang static void hclgevf_reset_done(struct hnae3_ae_dev *ae_dev) 1750f28368bbSHuazhong Tan { 1751f28368bbSHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1752f28368bbSHuazhong Tan int ret; 1753f28368bbSHuazhong Tan 1754f28368bbSHuazhong Tan hclgevf_enable_vector(&hdev->misc_vector, true); 1755f28368bbSHuazhong Tan 1756f28368bbSHuazhong Tan ret = hclgevf_reset_rebuild(hdev); 1757f28368bbSHuazhong Tan if (ret) 1758f28368bbSHuazhong Tan dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", 1759f28368bbSHuazhong Tan ret); 1760f28368bbSHuazhong Tan 1761f28368bbSHuazhong Tan hdev->reset_type = HNAE3_NONE_RESET; 1762f28368bbSHuazhong Tan clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1763f28368bbSHuazhong Tan up(&hdev->reset_sem); 17646ff3cf07SHuazhong Tan } 17656ff3cf07SHuazhong Tan 1766e2cb1decSSalil Mehta static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1767e2cb1decSSalil Mehta { 1768e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1769e2cb1decSSalil Mehta 1770e2cb1decSSalil Mehta return hdev->fw_version; 1771e2cb1decSSalil Mehta } 1772e2cb1decSSalil Mehta 1773e2cb1decSSalil Mehta static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1774e2cb1decSSalil Mehta { 1775e2cb1decSSalil Mehta struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1776e2cb1decSSalil Mehta 1777e2cb1decSSalil Mehta vector->vector_irq = pci_irq_vector(hdev->pdev, 1778e2cb1decSSalil Mehta HCLGEVF_MISC_VECTOR_NUM); 1779076bb537SJie Wang vector->addr = hdev->hw.hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1780e2cb1decSSalil Mehta /* vector status always valid for Vector 0 */ 1781e2cb1decSSalil Mehta hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1782e2cb1decSSalil Mehta hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1783e2cb1decSSalil Mehta 1784e2cb1decSSalil Mehta hdev->num_msi_left -= 1; 1785e2cb1decSSalil Mehta hdev->num_msi_used += 1; 1786e2cb1decSSalil Mehta } 1787e2cb1decSSalil Mehta 178835a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 178935a1e503SSalil Mehta { 1790ff200099SYunsheng Lin if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 17910251d196SGuangbin Huang test_bit(HCLGEVF_STATE_SERVICE_INITED, &hdev->state) && 1792ff200099SYunsheng Lin !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, 1793ff200099SYunsheng Lin &hdev->state)) 17940ea68902SYunsheng Lin mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 179535a1e503SSalil Mehta } 179635a1e503SSalil Mehta 179707a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1798e2cb1decSSalil Mehta { 1799ff200099SYunsheng Lin if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1800ff200099SYunsheng Lin !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, 1801ff200099SYunsheng Lin &hdev->state)) 18020ea68902SYunsheng Lin mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 180307a0556aSSalil Mehta } 1804e2cb1decSSalil Mehta 1805ff200099SYunsheng Lin static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 1806ff200099SYunsheng Lin unsigned long delay) 1807e2cb1decSSalil Mehta { 1808d5432455SGuojia Liao if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1809d5432455SGuojia Liao !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 18100ea68902SYunsheng Lin mod_delayed_work(hclgevf_wq, &hdev->service_task, delay); 1811e2cb1decSSalil Mehta } 1812e2cb1decSSalil Mehta 1813ff200099SYunsheng Lin static void hclgevf_reset_service_task(struct hclgevf_dev *hdev) 181435a1e503SSalil Mehta { 1815d6ad7c53SGuojia Liao #define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3 1816d6ad7c53SGuojia Liao 1817ff200099SYunsheng Lin if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state)) 1818ff200099SYunsheng Lin return; 1819ff200099SYunsheng Lin 1820f28368bbSHuazhong Tan down(&hdev->reset_sem); 1821f28368bbSHuazhong Tan set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 182235a1e503SSalil Mehta 1823436667d2SSalil Mehta if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1824436667d2SSalil Mehta &hdev->reset_state)) { 1825cd7e963dSSalil Mehta /* PF has intimated that it is about to reset the hardware. 18269b2f3477SWeihang Li * We now have to poll & check if hardware has actually 18279b2f3477SWeihang Li * completed the reset sequence. On hardware reset completion, 18289b2f3477SWeihang Li * VF needs to reset the client and ae device. 182935a1e503SSalil Mehta */ 1830436667d2SSalil Mehta hdev->reset_attempts = 0; 1831436667d2SSalil Mehta 1832dea846e8SHuazhong Tan hdev->last_reset_time = jiffies; 18331385cc81SYufeng Mo hdev->reset_type = 18341385cc81SYufeng Mo hclgevf_get_reset_level(hdev, &hdev->reset_pending); 18351385cc81SYufeng Mo if (hdev->reset_type != HNAE3_NONE_RESET) 18361cc9bc6eSHuazhong Tan hclgevf_reset(hdev); 1837436667d2SSalil Mehta } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1838436667d2SSalil Mehta &hdev->reset_state)) { 1839436667d2SSalil Mehta /* we could be here when either of below happens: 18409b2f3477SWeihang Li * 1. reset was initiated due to watchdog timeout caused by 1841436667d2SSalil Mehta * a. IMP was earlier reset and our TX got choked down and 1842436667d2SSalil Mehta * which resulted in watchdog reacting and inducing VF 1843436667d2SSalil Mehta * reset. This also means our cmdq would be unreliable. 1844436667d2SSalil Mehta * b. problem in TX due to other lower layer(example link 1845436667d2SSalil Mehta * layer not functioning properly etc.) 1846436667d2SSalil Mehta * 2. VF reset might have been initiated due to some config 1847436667d2SSalil Mehta * change. 1848436667d2SSalil Mehta * 1849436667d2SSalil Mehta * NOTE: Theres no clear way to detect above cases than to react 1850436667d2SSalil Mehta * to the response of PF for this reset request. PF will ack the 1851436667d2SSalil Mehta * 1b and 2. cases but we will not get any intimation about 1a 1852436667d2SSalil Mehta * from PF as cmdq would be in unreliable state i.e. mailbox 1853436667d2SSalil Mehta * communication between PF and VF would be broken. 185446ee7350SGuojia Liao * 185546ee7350SGuojia Liao * if we are never geting into pending state it means either: 1856436667d2SSalil Mehta * 1. PF is not receiving our request which could be due to IMP 1857436667d2SSalil Mehta * reset 1858436667d2SSalil Mehta * 2. PF is screwed 1859436667d2SSalil Mehta * We cannot do much for 2. but to check first we can try reset 1860436667d2SSalil Mehta * our PCIe + stack and see if it alleviates the problem. 1861436667d2SSalil Mehta */ 1862d6ad7c53SGuojia Liao if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) { 1863436667d2SSalil Mehta /* prepare for full reset of stack + pcie interface */ 1864dea846e8SHuazhong Tan set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1865436667d2SSalil Mehta 1866436667d2SSalil Mehta /* "defer" schedule the reset task again */ 1867436667d2SSalil Mehta set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1868436667d2SSalil Mehta } else { 1869436667d2SSalil Mehta hdev->reset_attempts++; 1870436667d2SSalil Mehta 1871dea846e8SHuazhong Tan set_bit(hdev->reset_level, &hdev->reset_pending); 1872dea846e8SHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1873436667d2SSalil Mehta } 1874dea846e8SHuazhong Tan hclgevf_reset_task_schedule(hdev); 1875436667d2SSalil Mehta } 187635a1e503SSalil Mehta 1877afb6afdbSHuazhong Tan hdev->reset_type = HNAE3_NONE_RESET; 187835a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1879f28368bbSHuazhong Tan up(&hdev->reset_sem); 188035a1e503SSalil Mehta } 188135a1e503SSalil Mehta 1882ff200099SYunsheng Lin static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev) 1883e2cb1decSSalil Mehta { 1884ff200099SYunsheng Lin if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state)) 1885ff200099SYunsheng Lin return; 1886e2cb1decSSalil Mehta 1887e2cb1decSSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1888e2cb1decSSalil Mehta return; 1889e2cb1decSSalil Mehta 189007a0556aSSalil Mehta hclgevf_mbx_async_handler(hdev); 1891e2cb1decSSalil Mehta 1892e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1893e2cb1decSSalil Mehta } 1894e2cb1decSSalil Mehta 1895ff200099SYunsheng Lin static void hclgevf_keep_alive(struct hclgevf_dev *hdev) 1896a6d818e3SYunsheng Lin { 1897d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 1898a6d818e3SYunsheng Lin int ret; 1899a6d818e3SYunsheng Lin 1900076bb537SJie Wang if (test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state)) 1901c59a85c0SJian Shen return; 1902c59a85c0SJian Shen 1903d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_KEEP_ALIVE, 0); 1904d3410018SYufeng Mo ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1905a6d818e3SYunsheng Lin if (ret) 1906a6d818e3SYunsheng Lin dev_err(&hdev->pdev->dev, 1907a6d818e3SYunsheng Lin "VF sends keep alive cmd failed(=%d)\n", ret); 1908a6d818e3SYunsheng Lin } 1909a6d818e3SYunsheng Lin 1910ff200099SYunsheng Lin static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev) 1911e2cb1decSSalil Mehta { 1912ff200099SYunsheng Lin unsigned long delta = round_jiffies_relative(HZ); 1913ff200099SYunsheng Lin struct hnae3_handle *handle = &hdev->nic; 1914e2cb1decSSalil Mehta 1915e6394363SGuangbin Huang if (test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 1916e6394363SGuangbin Huang return; 1917e6394363SGuangbin Huang 1918ff200099SYunsheng Lin if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 1919ff200099SYunsheng Lin delta = jiffies - hdev->last_serv_processed; 1920db01afebSliuzhongzhu 1921ff200099SYunsheng Lin if (delta < round_jiffies_relative(HZ)) { 1922ff200099SYunsheng Lin delta = round_jiffies_relative(HZ) - delta; 1923ff200099SYunsheng Lin goto out; 1924db01afebSliuzhongzhu } 1925ff200099SYunsheng Lin } 1926ff200099SYunsheng Lin 1927ff200099SYunsheng Lin hdev->serv_processed_cnt++; 1928ff200099SYunsheng Lin if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL)) 1929ff200099SYunsheng Lin hclgevf_keep_alive(hdev); 1930ff200099SYunsheng Lin 1931ff200099SYunsheng Lin if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) { 1932ff200099SYunsheng Lin hdev->last_serv_processed = jiffies; 1933ff200099SYunsheng Lin goto out; 1934ff200099SYunsheng Lin } 1935ff200099SYunsheng Lin 1936ff200099SYunsheng Lin if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL)) 19374afc310cSJie Wang hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 1938e2cb1decSSalil Mehta 193901305e16SGuangbin Huang /* VF does not need to request link status when this bit is set, because 194001305e16SGuangbin Huang * PF will push its link status to VFs when link status changed. 1941e2cb1decSSalil Mehta */ 194201305e16SGuangbin Huang if (!test_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state)) 1943e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1944e2cb1decSSalil Mehta 19459194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 19469194d18bSliuzhongzhu 1947fe4144d4SJian Shen hclgevf_sync_vlan_filter(hdev); 1948fe4144d4SJian Shen 1949ee4bcd3bSJian Shen hclgevf_sync_mac_table(hdev); 1950ee4bcd3bSJian Shen 1951c631c696SJian Shen hclgevf_sync_promisc_mode(hdev); 1952c631c696SJian Shen 1953ff200099SYunsheng Lin hdev->last_serv_processed = jiffies; 1954436667d2SSalil Mehta 1955ff200099SYunsheng Lin out: 1956ff200099SYunsheng Lin hclgevf_task_schedule(hdev, delta); 1957ff200099SYunsheng Lin } 1958b3c3fe8eSYunsheng Lin 1959ff200099SYunsheng Lin static void hclgevf_service_task(struct work_struct *work) 1960ff200099SYunsheng Lin { 1961ff200099SYunsheng Lin struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev, 1962ff200099SYunsheng Lin service_task.work); 1963ff200099SYunsheng Lin 1964ff200099SYunsheng Lin hclgevf_reset_service_task(hdev); 1965ff200099SYunsheng Lin hclgevf_mailbox_service_task(hdev); 1966ff200099SYunsheng Lin hclgevf_periodic_service_task(hdev); 1967ff200099SYunsheng Lin 1968ff200099SYunsheng Lin /* Handle reset and mbx again in case periodical task delays the 1969ff200099SYunsheng Lin * handling by calling hclgevf_task_schedule() in 1970ff200099SYunsheng Lin * hclgevf_periodic_service_task() 1971ff200099SYunsheng Lin */ 1972ff200099SYunsheng Lin hclgevf_reset_service_task(hdev); 1973ff200099SYunsheng Lin hclgevf_mailbox_service_task(hdev); 1974e2cb1decSSalil Mehta } 1975e2cb1decSSalil Mehta 1976e2cb1decSSalil Mehta static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1977e2cb1decSSalil Mehta { 1978cb413bfaSJie Wang hclgevf_write_dev(&hdev->hw, HCLGE_COMM_VECTOR0_CMDQ_SRC_REG, regclr); 1979e2cb1decSSalil Mehta } 1980e2cb1decSSalil Mehta 1981b90fcc5bSHuazhong Tan static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1982b90fcc5bSHuazhong Tan u32 *clearval) 1983e2cb1decSSalil Mehta { 198413050921SHuazhong Tan u32 val, cmdq_stat_reg, rst_ing_reg; 1985e2cb1decSSalil Mehta 1986e2cb1decSSalil Mehta /* fetch the events from their corresponding regs */ 198713050921SHuazhong Tan cmdq_stat_reg = hclgevf_read_dev(&hdev->hw, 1988cb413bfaSJie Wang HCLGE_COMM_VECTOR0_CMDQ_STATE_REG); 198913050921SHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 1990b90fcc5bSHuazhong Tan rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1991b90fcc5bSHuazhong Tan dev_info(&hdev->pdev->dev, 1992b90fcc5bSHuazhong Tan "receive reset interrupt 0x%x!\n", rst_ing_reg); 1993b90fcc5bSHuazhong Tan set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1994b90fcc5bSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1995076bb537SJie Wang set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 199613050921SHuazhong Tan *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B); 1997c88a6e7dSHuazhong Tan hdev->rst_stats.vf_rst_cnt++; 199872e2fb07SHuazhong Tan /* set up VF hardware reset status, its PF will clear 199972e2fb07SHuazhong Tan * this status when PF has initialized done. 200072e2fb07SHuazhong Tan */ 200172e2fb07SHuazhong Tan val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING); 200272e2fb07SHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING, 200372e2fb07SHuazhong Tan val | HCLGEVF_VF_RST_ING_BIT); 2004b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_RST; 2005b90fcc5bSHuazhong Tan } 2006b90fcc5bSHuazhong Tan 2007e2cb1decSSalil Mehta /* check for vector0 mailbox(=CMDQ RX) event source */ 200813050921SHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 200913050921SHuazhong Tan /* for revision 0x21, clearing interrupt is writing bit 0 201013050921SHuazhong Tan * to the clear register, writing bit 1 means to keep the 201113050921SHuazhong Tan * old value. 201213050921SHuazhong Tan * for revision 0x20, the clear register is a read & write 201313050921SHuazhong Tan * register, so we should just write 0 to the bit we are 201413050921SHuazhong Tan * handling, and keep other bits as cmdq_stat_reg. 201513050921SHuazhong Tan */ 2016295ba232SGuangbin Huang if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) 201713050921SHuazhong Tan *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 201813050921SHuazhong Tan else 201913050921SHuazhong Tan *clearval = cmdq_stat_reg & 202013050921SHuazhong Tan ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 202113050921SHuazhong Tan 2022b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_MBX; 2023e2cb1decSSalil Mehta } 2024e2cb1decSSalil Mehta 2025e45afb39SHuazhong Tan /* print other vector0 event source */ 2026e45afb39SHuazhong Tan dev_info(&hdev->pdev->dev, 2027e45afb39SHuazhong Tan "vector 0 interrupt from unknown source, cmdq_src = %#x\n", 2028e45afb39SHuazhong Tan cmdq_stat_reg); 2029e2cb1decSSalil Mehta 2030b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_OTHER; 2031e2cb1decSSalil Mehta } 2032e2cb1decSSalil Mehta 2033e2cb1decSSalil Mehta static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 2034e2cb1decSSalil Mehta { 2035b90fcc5bSHuazhong Tan enum hclgevf_evt_cause event_cause; 2036e2cb1decSSalil Mehta struct hclgevf_dev *hdev = data; 2037e2cb1decSSalil Mehta u32 clearval; 2038e2cb1decSSalil Mehta 2039e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 2040b90fcc5bSHuazhong Tan event_cause = hclgevf_check_evt_cause(hdev, &clearval); 2041427900d2SJiaran Zhang if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) 2042427900d2SJiaran Zhang hclgevf_clear_event_cause(hdev, clearval); 2043e2cb1decSSalil Mehta 2044b90fcc5bSHuazhong Tan switch (event_cause) { 2045b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_RST: 2046b90fcc5bSHuazhong Tan hclgevf_reset_task_schedule(hdev); 2047b90fcc5bSHuazhong Tan break; 2048b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_MBX: 204907a0556aSSalil Mehta hclgevf_mbx_handler(hdev); 2050b90fcc5bSHuazhong Tan break; 2051b90fcc5bSHuazhong Tan default: 2052b90fcc5bSHuazhong Tan break; 2053b90fcc5bSHuazhong Tan } 2054e2cb1decSSalil Mehta 2055e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2056e2cb1decSSalil Mehta 2057e2cb1decSSalil Mehta return IRQ_HANDLED; 2058e2cb1decSSalil Mehta } 2059e2cb1decSSalil Mehta 2060e2cb1decSSalil Mehta static int hclgevf_configure(struct hclgevf_dev *hdev) 2061e2cb1decSSalil Mehta { 2062e2cb1decSSalil Mehta int ret; 2063e2cb1decSSalil Mehta 20643462207dSYufeng Mo hdev->gro_en = true; 20653462207dSYufeng Mo 206632e6d104SJian Shen ret = hclgevf_get_basic_info(hdev); 206732e6d104SJian Shen if (ret) 206832e6d104SJian Shen return ret; 206932e6d104SJian Shen 207092f11ea1SJian Shen /* get current port based vlan state from PF */ 207192f11ea1SJian Shen ret = hclgevf_get_port_base_vlan_filter_state(hdev); 207292f11ea1SJian Shen if (ret) 207392f11ea1SJian Shen return ret; 207492f11ea1SJian Shen 2075e2cb1decSSalil Mehta /* get queue configuration from PF */ 20766cee6fc3SJian Shen ret = hclgevf_get_queue_info(hdev); 2077e2cb1decSSalil Mehta if (ret) 2078e2cb1decSSalil Mehta return ret; 2079c0425944SPeng Li 2080c0425944SPeng Li /* get queue depth info from PF */ 2081c0425944SPeng Li ret = hclgevf_get_queue_depth(hdev); 2082c0425944SPeng Li if (ret) 2083c0425944SPeng Li return ret; 2084c0425944SPeng Li 208532e6d104SJian Shen return hclgevf_get_pf_media_type(hdev); 2086e2cb1decSSalil Mehta } 2087e2cb1decSSalil Mehta 20887a01c897SSalil Mehta static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 20897a01c897SSalil Mehta { 20907a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 20911154bb26SPeng Li struct hclgevf_dev *hdev; 20927a01c897SSalil Mehta 20937a01c897SSalil Mehta hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 20947a01c897SSalil Mehta if (!hdev) 20957a01c897SSalil Mehta return -ENOMEM; 20967a01c897SSalil Mehta 20977a01c897SSalil Mehta hdev->pdev = pdev; 20987a01c897SSalil Mehta hdev->ae_dev = ae_dev; 20997a01c897SSalil Mehta ae_dev->priv = hdev; 21007a01c897SSalil Mehta 21017a01c897SSalil Mehta return 0; 21027a01c897SSalil Mehta } 21037a01c897SSalil Mehta 2104e2cb1decSSalil Mehta static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 2105e2cb1decSSalil Mehta { 2106e2cb1decSSalil Mehta struct hnae3_handle *roce = &hdev->roce; 2107e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 2108e2cb1decSSalil Mehta 210907acf909SJian Shen roce->rinfo.num_vectors = hdev->num_roce_msix; 2110e2cb1decSSalil Mehta 2111e2cb1decSSalil Mehta if (hdev->num_msi_left < roce->rinfo.num_vectors || 2112e2cb1decSSalil Mehta hdev->num_msi_left == 0) 2113e2cb1decSSalil Mehta return -EINVAL; 2114e2cb1decSSalil Mehta 2115beb27ca4SJie Wang roce->rinfo.base_vector = hdev->roce_base_msix_offset; 2116e2cb1decSSalil Mehta 2117e2cb1decSSalil Mehta roce->rinfo.netdev = nic->kinfo.netdev; 2118076bb537SJie Wang roce->rinfo.roce_io_base = hdev->hw.hw.io_base; 2119076bb537SJie Wang roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base; 2120e2cb1decSSalil Mehta 2121e2cb1decSSalil Mehta roce->pdev = nic->pdev; 2122e2cb1decSSalil Mehta roce->ae_algo = nic->ae_algo; 2123e2cb1decSSalil Mehta roce->numa_node_mask = nic->numa_node_mask; 2124e2cb1decSSalil Mehta 2125e2cb1decSSalil Mehta return 0; 2126e2cb1decSSalil Mehta } 2127e2cb1decSSalil Mehta 21283462207dSYufeng Mo static int hclgevf_config_gro(struct hclgevf_dev *hdev) 2129b26a6feaSPeng Li { 2130b26a6feaSPeng Li struct hclgevf_cfg_gro_status_cmd *req; 21316befad60SJie Wang struct hclge_desc desc; 2132b26a6feaSPeng Li int ret; 2133b26a6feaSPeng Li 2134b26a6feaSPeng Li if (!hnae3_dev_gro_supported(hdev)) 2135b26a6feaSPeng Li return 0; 2136b26a6feaSPeng Li 213743710bfeSJie Wang hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, 2138b26a6feaSPeng Li false); 2139b26a6feaSPeng Li req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2140b26a6feaSPeng Li 21413462207dSYufeng Mo req->gro_en = hdev->gro_en ? 1 : 0; 2142b26a6feaSPeng Li 2143b26a6feaSPeng Li ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2144b26a6feaSPeng Li if (ret) 2145b26a6feaSPeng Li dev_err(&hdev->pdev->dev, 2146b26a6feaSPeng Li "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2147b26a6feaSPeng Li 2148b26a6feaSPeng Li return ret; 2149b26a6feaSPeng Li } 2150b26a6feaSPeng Li 2151944de484SGuojia Liao static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2152944de484SGuojia Liao { 2153027733b1SJie Wang struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 215493969dc1SJie Wang u16 tc_offset[HCLGE_COMM_MAX_TC_NUM]; 215593969dc1SJie Wang u16 tc_valid[HCLGE_COMM_MAX_TC_NUM]; 215693969dc1SJie Wang u16 tc_size[HCLGE_COMM_MAX_TC_NUM]; 2157944de484SGuojia Liao int ret; 2158944de484SGuojia Liao 2159295ba232SGuangbin Huang if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 21607428d6c9SJie Wang ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, 21617428d6c9SJie Wang rss_cfg->rss_algo, 2162944de484SGuojia Liao rss_cfg->rss_hash_key); 2163944de484SGuojia Liao if (ret) 2164944de484SGuojia Liao return ret; 2165944de484SGuojia Liao 21667428d6c9SJie Wang ret = hclge_comm_set_rss_input_tuple(&hdev->nic, &hdev->hw.hw, 21677428d6c9SJie Wang false, rss_cfg); 2168944de484SGuojia Liao if (ret) 2169944de484SGuojia Liao return ret; 2170944de484SGuojia Liao } 2171e2cb1decSSalil Mehta 21727428d6c9SJie Wang ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 21737428d6c9SJie Wang rss_cfg->rss_indirection_tbl); 2174e2cb1decSSalil Mehta if (ret) 2175e2cb1decSSalil Mehta return ret; 2176e2cb1decSSalil Mehta 217793969dc1SJie Wang hclge_comm_get_rss_tc_info(rss_cfg->rss_size, hdev->hw_tc_map, 217893969dc1SJie Wang tc_offset, tc_valid, tc_size); 217993969dc1SJie Wang 218093969dc1SJie Wang return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, 218193969dc1SJie Wang tc_valid, tc_size); 2182e2cb1decSSalil Mehta } 2183e2cb1decSSalil Mehta 2184e2cb1decSSalil Mehta static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2185e2cb1decSSalil Mehta { 2186bbfd4506SJian Shen struct hnae3_handle *nic = &hdev->nic; 2187bbfd4506SJian Shen int ret; 2188bbfd4506SJian Shen 2189bbfd4506SJian Shen ret = hclgevf_en_hw_strip_rxvtag(nic, true); 2190bbfd4506SJian Shen if (ret) { 2191bbfd4506SJian Shen dev_err(&hdev->pdev->dev, 2192bbfd4506SJian Shen "failed to enable rx vlan offload, ret = %d\n", ret); 2193bbfd4506SJian Shen return ret; 2194bbfd4506SJian Shen } 2195bbfd4506SJian Shen 2196e2cb1decSSalil Mehta return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2197e2cb1decSSalil Mehta false); 2198e2cb1decSSalil Mehta } 2199e2cb1decSSalil Mehta 2200ff200099SYunsheng Lin static void hclgevf_flush_link_update(struct hclgevf_dev *hdev) 2201ff200099SYunsheng Lin { 2202ff200099SYunsheng Lin #define HCLGEVF_FLUSH_LINK_TIMEOUT 100000 2203ff200099SYunsheng Lin 2204ff200099SYunsheng Lin unsigned long last = hdev->serv_processed_cnt; 2205ff200099SYunsheng Lin int i = 0; 2206ff200099SYunsheng Lin 2207ff200099SYunsheng Lin while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) && 2208ff200099SYunsheng Lin i++ < HCLGEVF_FLUSH_LINK_TIMEOUT && 2209ff200099SYunsheng Lin last == hdev->serv_processed_cnt) 2210ff200099SYunsheng Lin usleep_range(1, 1); 2211ff200099SYunsheng Lin } 2212ff200099SYunsheng Lin 22138cdb992fSJian Shen static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 22148cdb992fSJian Shen { 22158cdb992fSJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 22168cdb992fSJian Shen 22178cdb992fSJian Shen if (enable) { 2218ff200099SYunsheng Lin hclgevf_task_schedule(hdev, 0); 22198cdb992fSJian Shen } else { 2220b3c3fe8eSYunsheng Lin set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2221ff200099SYunsheng Lin 2222ff200099SYunsheng Lin /* flush memory to make sure DOWN is seen by service task */ 2223ff200099SYunsheng Lin smp_mb__before_atomic(); 2224ff200099SYunsheng Lin hclgevf_flush_link_update(hdev); 22258cdb992fSJian Shen } 22268cdb992fSJian Shen } 22278cdb992fSJian Shen 2228e2cb1decSSalil Mehta static int hclgevf_ae_start(struct hnae3_handle *handle) 2229e2cb1decSSalil Mehta { 2230e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2231e2cb1decSSalil Mehta 2232ed7bedd2SGuangbin Huang clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 223301305e16SGuangbin Huang clear_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state); 2234ed7bedd2SGuangbin Huang 22354afc310cSJie Wang hclge_comm_reset_tqp_stats(handle); 2236e2cb1decSSalil Mehta 2237e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 2238e2cb1decSSalil Mehta 22399194d18bSliuzhongzhu hclgevf_update_link_mode(hdev); 22409194d18bSliuzhongzhu 2241e2cb1decSSalil Mehta return 0; 2242e2cb1decSSalil Mehta } 2243e2cb1decSSalil Mehta 2244e2cb1decSSalil Mehta static void hclgevf_ae_stop(struct hnae3_handle *handle) 2245e2cb1decSSalil Mehta { 2246e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2247e2cb1decSSalil Mehta 22482f7e4896SFuyun Liang set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 22492f7e4896SFuyun Liang 2250146e92c1SHuazhong Tan if (hdev->reset_type != HNAE3_VF_RESET) 22518fa86551SYufeng Mo hclgevf_reset_tqp(handle); 225239cfbc9cSHuazhong Tan 22534afc310cSJie Wang hclge_comm_reset_tqp_stats(handle); 22548cc6c1f7SFuyun Liang hclgevf_update_link_status(hdev, 0); 2255e2cb1decSSalil Mehta } 2256e2cb1decSSalil Mehta 2257a6d818e3SYunsheng Lin static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2258a6d818e3SYunsheng Lin { 2259d3410018SYufeng Mo #define HCLGEVF_STATE_ALIVE 1 2260d3410018SYufeng Mo #define HCLGEVF_STATE_NOT_ALIVE 0 2261a6d818e3SYunsheng Lin 2262d3410018SYufeng Mo struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2263d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 2264d3410018SYufeng Mo 2265d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_ALIVE, 0); 2266d3410018SYufeng Mo send_msg.data[0] = alive ? HCLGEVF_STATE_ALIVE : 2267d3410018SYufeng Mo HCLGEVF_STATE_NOT_ALIVE; 2268d3410018SYufeng Mo return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2269a6d818e3SYunsheng Lin } 2270a6d818e3SYunsheng Lin 2271a6d818e3SYunsheng Lin static int hclgevf_client_start(struct hnae3_handle *handle) 2272a6d818e3SYunsheng Lin { 2273f621df96SQinglang Miao return hclgevf_set_alive(handle, true); 2274a6d818e3SYunsheng Lin } 2275a6d818e3SYunsheng Lin 2276a6d818e3SYunsheng Lin static void hclgevf_client_stop(struct hnae3_handle *handle) 2277a6d818e3SYunsheng Lin { 2278a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2279a6d818e3SYunsheng Lin int ret; 2280a6d818e3SYunsheng Lin 2281a6d818e3SYunsheng Lin ret = hclgevf_set_alive(handle, false); 2282a6d818e3SYunsheng Lin if (ret) 2283a6d818e3SYunsheng Lin dev_warn(&hdev->pdev->dev, 2284a6d818e3SYunsheng Lin "%s failed %d\n", __func__, ret); 2285a6d818e3SYunsheng Lin } 2286a6d818e3SYunsheng Lin 2287e2cb1decSSalil Mehta static void hclgevf_state_init(struct hclgevf_dev *hdev) 2288e2cb1decSSalil Mehta { 2289e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2290e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2291d5432455SGuojia Liao clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 2292e2cb1decSSalil Mehta 2293b3c3fe8eSYunsheng Lin INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task); 229435a1e503SSalil Mehta 2295e2cb1decSSalil Mehta mutex_init(&hdev->mbx_resp.mbx_mutex); 2296f28368bbSHuazhong Tan sema_init(&hdev->reset_sem, 1); 2297e2cb1decSSalil Mehta 2298ee4bcd3bSJian Shen spin_lock_init(&hdev->mac_table.mac_list_lock); 2299ee4bcd3bSJian Shen INIT_LIST_HEAD(&hdev->mac_table.uc_mac_list); 2300ee4bcd3bSJian Shen INIT_LIST_HEAD(&hdev->mac_table.mc_mac_list); 2301ee4bcd3bSJian Shen 2302e2cb1decSSalil Mehta /* bring the device down */ 2303e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2304e2cb1decSSalil Mehta } 2305e2cb1decSSalil Mehta 2306e2cb1decSSalil Mehta static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2307e2cb1decSSalil Mehta { 2308e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2309acfc3d55SHuazhong Tan set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2310e2cb1decSSalil Mehta 2311b3c3fe8eSYunsheng Lin if (hdev->service_task.work.func) 2312b3c3fe8eSYunsheng Lin cancel_delayed_work_sync(&hdev->service_task); 2313e2cb1decSSalil Mehta 2314e2cb1decSSalil Mehta mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2315e2cb1decSSalil Mehta } 2316e2cb1decSSalil Mehta 2317e2cb1decSSalil Mehta static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2318e2cb1decSSalil Mehta { 2319e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2320e2cb1decSSalil Mehta int vectors; 2321e2cb1decSSalil Mehta int i; 2322e2cb1decSSalil Mehta 2323580a05f9SYonglong Liu if (hnae3_dev_roce_supported(hdev)) 232407acf909SJian Shen vectors = pci_alloc_irq_vectors(pdev, 232507acf909SJian Shen hdev->roce_base_msix_offset + 1, 232607acf909SJian Shen hdev->num_msi, 232707acf909SJian Shen PCI_IRQ_MSIX); 232807acf909SJian Shen else 2329580a05f9SYonglong Liu vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2330580a05f9SYonglong Liu hdev->num_msi, 2331e2cb1decSSalil Mehta PCI_IRQ_MSI | PCI_IRQ_MSIX); 233207acf909SJian Shen 2333e2cb1decSSalil Mehta if (vectors < 0) { 2334e2cb1decSSalil Mehta dev_err(&pdev->dev, 2335e2cb1decSSalil Mehta "failed(%d) to allocate MSI/MSI-X vectors\n", 2336e2cb1decSSalil Mehta vectors); 2337e2cb1decSSalil Mehta return vectors; 2338e2cb1decSSalil Mehta } 2339e2cb1decSSalil Mehta if (vectors < hdev->num_msi) 2340e2cb1decSSalil Mehta dev_warn(&hdev->pdev->dev, 2341adcf738bSGuojia Liao "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2342e2cb1decSSalil Mehta hdev->num_msi, vectors); 2343e2cb1decSSalil Mehta 2344e2cb1decSSalil Mehta hdev->num_msi = vectors; 2345e2cb1decSSalil Mehta hdev->num_msi_left = vectors; 2346580a05f9SYonglong Liu 2347e2cb1decSSalil Mehta hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2348e2cb1decSSalil Mehta sizeof(u16), GFP_KERNEL); 2349e2cb1decSSalil Mehta if (!hdev->vector_status) { 2350e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2351e2cb1decSSalil Mehta return -ENOMEM; 2352e2cb1decSSalil Mehta } 2353e2cb1decSSalil Mehta 2354e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 2355e2cb1decSSalil Mehta hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2356e2cb1decSSalil Mehta 2357e2cb1decSSalil Mehta hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2358e2cb1decSSalil Mehta sizeof(int), GFP_KERNEL); 2359e2cb1decSSalil Mehta if (!hdev->vector_irq) { 2360862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2361e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2362e2cb1decSSalil Mehta return -ENOMEM; 2363e2cb1decSSalil Mehta } 2364e2cb1decSSalil Mehta 2365e2cb1decSSalil Mehta return 0; 2366e2cb1decSSalil Mehta } 2367e2cb1decSSalil Mehta 2368e2cb1decSSalil Mehta static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2369e2cb1decSSalil Mehta { 2370e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2371e2cb1decSSalil Mehta 2372862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2373862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_irq); 2374e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2375e2cb1decSSalil Mehta } 2376e2cb1decSSalil Mehta 2377e2cb1decSSalil Mehta static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2378e2cb1decSSalil Mehta { 2379cdd332acSGuojia Liao int ret; 2380e2cb1decSSalil Mehta 2381e2cb1decSSalil Mehta hclgevf_get_misc_vector(hdev); 2382e2cb1decSSalil Mehta 2383f97c4d82SYonglong Liu snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 2384f97c4d82SYonglong Liu HCLGEVF_NAME, pci_name(hdev->pdev)); 2385e2cb1decSSalil Mehta ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2386f97c4d82SYonglong Liu 0, hdev->misc_vector.name, hdev); 2387e2cb1decSSalil Mehta if (ret) { 2388e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2389e2cb1decSSalil Mehta hdev->misc_vector.vector_irq); 2390e2cb1decSSalil Mehta return ret; 2391e2cb1decSSalil Mehta } 2392e2cb1decSSalil Mehta 23931819e409SXi Wang hclgevf_clear_event_cause(hdev, 0); 23941819e409SXi Wang 2395e2cb1decSSalil Mehta /* enable misc. vector(vector 0) */ 2396e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2397e2cb1decSSalil Mehta 2398e2cb1decSSalil Mehta return ret; 2399e2cb1decSSalil Mehta } 2400e2cb1decSSalil Mehta 2401e2cb1decSSalil Mehta static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2402e2cb1decSSalil Mehta { 2403e2cb1decSSalil Mehta /* disable misc vector(vector 0) */ 2404e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 24051819e409SXi Wang synchronize_irq(hdev->misc_vector.vector_irq); 2406e2cb1decSSalil Mehta free_irq(hdev->misc_vector.vector_irq, hdev); 2407e2cb1decSSalil Mehta hclgevf_free_vector(hdev, 0); 2408e2cb1decSSalil Mehta } 2409e2cb1decSSalil Mehta 2410bb87be87SYonglong Liu static void hclgevf_info_show(struct hclgevf_dev *hdev) 2411bb87be87SYonglong Liu { 2412bb87be87SYonglong Liu struct device *dev = &hdev->pdev->dev; 2413bb87be87SYonglong Liu 2414bb87be87SYonglong Liu dev_info(dev, "VF info begin:\n"); 2415bb87be87SYonglong Liu 2416adcf738bSGuojia Liao dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 2417adcf738bSGuojia Liao dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 2418adcf738bSGuojia Liao dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 2419adcf738bSGuojia Liao dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 2420adcf738bSGuojia Liao dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 2421adcf738bSGuojia Liao dev_info(dev, "PF media type of this VF: %u\n", 2422bb87be87SYonglong Liu hdev->hw.mac.media_type); 2423bb87be87SYonglong Liu 2424bb87be87SYonglong Liu dev_info(dev, "VF info end.\n"); 2425bb87be87SYonglong Liu } 2426bb87be87SYonglong Liu 24271db58f86SHuazhong Tan static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 24281db58f86SHuazhong Tan struct hnae3_client *client) 24291db58f86SHuazhong Tan { 24301db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 24314cd5beaaSGuangbin Huang int rst_cnt = hdev->rst_stats.rst_cnt; 24321db58f86SHuazhong Tan int ret; 24331db58f86SHuazhong Tan 24341db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->nic); 24351db58f86SHuazhong Tan if (ret) 24361db58f86SHuazhong Tan return ret; 24371db58f86SHuazhong Tan 24381db58f86SHuazhong Tan set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 24394cd5beaaSGuangbin Huang if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 24404cd5beaaSGuangbin Huang rst_cnt != hdev->rst_stats.rst_cnt) { 24414cd5beaaSGuangbin Huang clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 24424cd5beaaSGuangbin Huang 24434cd5beaaSGuangbin Huang client->ops->uninit_instance(&hdev->nic, 0); 24444cd5beaaSGuangbin Huang return -EBUSY; 24454cd5beaaSGuangbin Huang } 24464cd5beaaSGuangbin Huang 24471db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 24481db58f86SHuazhong Tan 24491db58f86SHuazhong Tan if (netif_msg_drv(&hdev->nic)) 24501db58f86SHuazhong Tan hclgevf_info_show(hdev); 24511db58f86SHuazhong Tan 24521db58f86SHuazhong Tan return 0; 24531db58f86SHuazhong Tan } 24541db58f86SHuazhong Tan 24551db58f86SHuazhong Tan static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 24561db58f86SHuazhong Tan struct hnae3_client *client) 24571db58f86SHuazhong Tan { 24581db58f86SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 24591db58f86SHuazhong Tan int ret; 24601db58f86SHuazhong Tan 24611db58f86SHuazhong Tan if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 24621db58f86SHuazhong Tan !hdev->nic_client) 24631db58f86SHuazhong Tan return 0; 24641db58f86SHuazhong Tan 24651db58f86SHuazhong Tan ret = hclgevf_init_roce_base_info(hdev); 24661db58f86SHuazhong Tan if (ret) 24671db58f86SHuazhong Tan return ret; 24681db58f86SHuazhong Tan 24691db58f86SHuazhong Tan ret = client->ops->init_instance(&hdev->roce); 24701db58f86SHuazhong Tan if (ret) 24711db58f86SHuazhong Tan return ret; 24721db58f86SHuazhong Tan 2473fe735c84SHuazhong Tan set_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 24741db58f86SHuazhong Tan hnae3_set_client_init_flag(client, ae_dev, 1); 24751db58f86SHuazhong Tan 24761db58f86SHuazhong Tan return 0; 24771db58f86SHuazhong Tan } 24781db58f86SHuazhong Tan 2479e718a93fSPeng Li static int hclgevf_init_client_instance(struct hnae3_client *client, 2480e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2481e2cb1decSSalil Mehta { 2482e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2483e2cb1decSSalil Mehta int ret; 2484e2cb1decSSalil Mehta 2485e2cb1decSSalil Mehta switch (client->type) { 2486e2cb1decSSalil Mehta case HNAE3_CLIENT_KNIC: 2487e2cb1decSSalil Mehta hdev->nic_client = client; 2488e2cb1decSSalil Mehta hdev->nic.client = client; 2489e2cb1decSSalil Mehta 24901db58f86SHuazhong Tan ret = hclgevf_init_nic_client_instance(ae_dev, client); 2491e2cb1decSSalil Mehta if (ret) 249249dd8054SJian Shen goto clear_nic; 2493e2cb1decSSalil Mehta 24941db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, 24951db58f86SHuazhong Tan hdev->roce_client); 2496e2cb1decSSalil Mehta if (ret) 249749dd8054SJian Shen goto clear_roce; 2498d9f28fc2SJian Shen 2499e2cb1decSSalil Mehta break; 2500e2cb1decSSalil Mehta case HNAE3_CLIENT_ROCE: 2501544a7bcdSLijun Ou if (hnae3_dev_roce_supported(hdev)) { 2502e2cb1decSSalil Mehta hdev->roce_client = client; 2503e2cb1decSSalil Mehta hdev->roce.client = client; 2504544a7bcdSLijun Ou } 2505e2cb1decSSalil Mehta 25061db58f86SHuazhong Tan ret = hclgevf_init_roce_client_instance(ae_dev, client); 2507e2cb1decSSalil Mehta if (ret) 250849dd8054SJian Shen goto clear_roce; 2509e2cb1decSSalil Mehta 2510fa7a4bd5SJian Shen break; 2511fa7a4bd5SJian Shen default: 2512fa7a4bd5SJian Shen return -EINVAL; 2513e2cb1decSSalil Mehta } 2514e2cb1decSSalil Mehta 2515e2cb1decSSalil Mehta return 0; 251649dd8054SJian Shen 251749dd8054SJian Shen clear_nic: 251849dd8054SJian Shen hdev->nic_client = NULL; 251949dd8054SJian Shen hdev->nic.client = NULL; 252049dd8054SJian Shen return ret; 252149dd8054SJian Shen clear_roce: 252249dd8054SJian Shen hdev->roce_client = NULL; 252349dd8054SJian Shen hdev->roce.client = NULL; 252449dd8054SJian Shen return ret; 2525e2cb1decSSalil Mehta } 2526e2cb1decSSalil Mehta 2527e718a93fSPeng Li static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2528e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2529e2cb1decSSalil Mehta { 2530e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2531e718a93fSPeng Li 2532e2cb1decSSalil Mehta /* un-init roce, if it exists */ 253349dd8054SJian Shen if (hdev->roce_client) { 2534e140c798SYufeng Mo while (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 2535e140c798SYufeng Mo msleep(HCLGEVF_WAIT_RESET_DONE); 2536fe735c84SHuazhong Tan clear_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 2537e140c798SYufeng Mo 2538e2cb1decSSalil Mehta hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 253949dd8054SJian Shen hdev->roce_client = NULL; 254049dd8054SJian Shen hdev->roce.client = NULL; 254149dd8054SJian Shen } 2542e2cb1decSSalil Mehta 2543e2cb1decSSalil Mehta /* un-init nic/unic, if this was not called by roce client */ 254449dd8054SJian Shen if (client->ops->uninit_instance && hdev->nic_client && 254549dd8054SJian Shen client->type != HNAE3_CLIENT_ROCE) { 2546e140c798SYufeng Mo while (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 2547e140c798SYufeng Mo msleep(HCLGEVF_WAIT_RESET_DONE); 254825d1817cSHuazhong Tan clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 254925d1817cSHuazhong Tan 2550e2cb1decSSalil Mehta client->ops->uninit_instance(&hdev->nic, 0); 255149dd8054SJian Shen hdev->nic_client = NULL; 255249dd8054SJian Shen hdev->nic.client = NULL; 255349dd8054SJian Shen } 2554e2cb1decSSalil Mehta } 2555e2cb1decSSalil Mehta 255630ae7f8aSHuazhong Tan static int hclgevf_dev_mem_map(struct hclgevf_dev *hdev) 255730ae7f8aSHuazhong Tan { 255830ae7f8aSHuazhong Tan struct pci_dev *pdev = hdev->pdev; 255930ae7f8aSHuazhong Tan struct hclgevf_hw *hw = &hdev->hw; 256030ae7f8aSHuazhong Tan 256130ae7f8aSHuazhong Tan /* for device does not have device memory, return directly */ 256230ae7f8aSHuazhong Tan if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGEVF_MEM_BAR))) 256330ae7f8aSHuazhong Tan return 0; 256430ae7f8aSHuazhong Tan 2565076bb537SJie Wang hw->hw.mem_base = 2566076bb537SJie Wang devm_ioremap_wc(&pdev->dev, 2567076bb537SJie Wang pci_resource_start(pdev, HCLGEVF_MEM_BAR), 256830ae7f8aSHuazhong Tan pci_resource_len(pdev, HCLGEVF_MEM_BAR)); 2569076bb537SJie Wang if (!hw->hw.mem_base) { 2570be419fcaSColin Ian King dev_err(&pdev->dev, "failed to map device memory\n"); 257130ae7f8aSHuazhong Tan return -EFAULT; 257230ae7f8aSHuazhong Tan } 257330ae7f8aSHuazhong Tan 257430ae7f8aSHuazhong Tan return 0; 257530ae7f8aSHuazhong Tan } 257630ae7f8aSHuazhong Tan 2577e2cb1decSSalil Mehta static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2578e2cb1decSSalil Mehta { 2579e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2580e2cb1decSSalil Mehta struct hclgevf_hw *hw; 2581e2cb1decSSalil Mehta int ret; 2582e2cb1decSSalil Mehta 2583e2cb1decSSalil Mehta ret = pci_enable_device(pdev); 2584e2cb1decSSalil Mehta if (ret) { 2585e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed to enable PCI device\n"); 25863e249d3bSFuyun Liang return ret; 2587e2cb1decSSalil Mehta } 2588e2cb1decSSalil Mehta 2589e2cb1decSSalil Mehta ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2590e2cb1decSSalil Mehta if (ret) { 2591e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2592e2cb1decSSalil Mehta goto err_disable_device; 2593e2cb1decSSalil Mehta } 2594e2cb1decSSalil Mehta 2595e2cb1decSSalil Mehta ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2596e2cb1decSSalil Mehta if (ret) { 2597e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2598e2cb1decSSalil Mehta goto err_disable_device; 2599e2cb1decSSalil Mehta } 2600e2cb1decSSalil Mehta 2601e2cb1decSSalil Mehta pci_set_master(pdev); 2602e2cb1decSSalil Mehta hw = &hdev->hw; 2603076bb537SJie Wang hw->hw.io_base = pci_iomap(pdev, 2, 0); 2604076bb537SJie Wang if (!hw->hw.io_base) { 2605e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't map configuration register space\n"); 2606e2cb1decSSalil Mehta ret = -ENOMEM; 2607e2cb1decSSalil Mehta goto err_clr_master; 2608e2cb1decSSalil Mehta } 2609e2cb1decSSalil Mehta 261030ae7f8aSHuazhong Tan ret = hclgevf_dev_mem_map(hdev); 261130ae7f8aSHuazhong Tan if (ret) 261230ae7f8aSHuazhong Tan goto err_unmap_io_base; 261330ae7f8aSHuazhong Tan 2614e2cb1decSSalil Mehta return 0; 2615e2cb1decSSalil Mehta 261630ae7f8aSHuazhong Tan err_unmap_io_base: 2617076bb537SJie Wang pci_iounmap(pdev, hdev->hw.hw.io_base); 2618e2cb1decSSalil Mehta err_clr_master: 2619e2cb1decSSalil Mehta pci_clear_master(pdev); 2620e2cb1decSSalil Mehta pci_release_regions(pdev); 2621e2cb1decSSalil Mehta err_disable_device: 2622e2cb1decSSalil Mehta pci_disable_device(pdev); 26233e249d3bSFuyun Liang 2624e2cb1decSSalil Mehta return ret; 2625e2cb1decSSalil Mehta } 2626e2cb1decSSalil Mehta 2627e2cb1decSSalil Mehta static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2628e2cb1decSSalil Mehta { 2629e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2630e2cb1decSSalil Mehta 2631076bb537SJie Wang if (hdev->hw.hw.mem_base) 2632076bb537SJie Wang devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base); 263330ae7f8aSHuazhong Tan 2634076bb537SJie Wang pci_iounmap(pdev, hdev->hw.hw.io_base); 2635e2cb1decSSalil Mehta pci_clear_master(pdev); 2636e2cb1decSSalil Mehta pci_release_regions(pdev); 2637e2cb1decSSalil Mehta pci_disable_device(pdev); 2638e2cb1decSSalil Mehta } 2639e2cb1decSSalil Mehta 264007acf909SJian Shen static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 264107acf909SJian Shen { 264207acf909SJian Shen struct hclgevf_query_res_cmd *req; 26436befad60SJie Wang struct hclge_desc desc; 264407acf909SJian Shen int ret; 264507acf909SJian Shen 264643710bfeSJie Wang hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RSRC, true); 264707acf909SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 264807acf909SJian Shen if (ret) { 264907acf909SJian Shen dev_err(&hdev->pdev->dev, 265007acf909SJian Shen "query vf resource failed, ret = %d.\n", ret); 265107acf909SJian Shen return ret; 265207acf909SJian Shen } 265307acf909SJian Shen 265407acf909SJian Shen req = (struct hclgevf_query_res_cmd *)desc.data; 265507acf909SJian Shen 2656580a05f9SYonglong Liu if (hnae3_dev_roce_supported(hdev)) { 265707acf909SJian Shen hdev->roce_base_msix_offset = 265860df7e91SHuazhong Tan hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee), 265907acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_M, 266007acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_S); 266107acf909SJian Shen hdev->num_roce_msix = 266260df7e91SHuazhong Tan hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 266307acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 266407acf909SJian Shen 2665580a05f9SYonglong Liu /* nic's msix numbers is always equals to the roce's. */ 2666580a05f9SYonglong Liu hdev->num_nic_msix = hdev->num_roce_msix; 2667580a05f9SYonglong Liu 266807acf909SJian Shen /* VF should have NIC vectors and Roce vectors, NIC vectors 266907acf909SJian Shen * are queued before Roce vectors. The offset is fixed to 64. 267007acf909SJian Shen */ 267107acf909SJian Shen hdev->num_msi = hdev->num_roce_msix + 267207acf909SJian Shen hdev->roce_base_msix_offset; 267307acf909SJian Shen } else { 267407acf909SJian Shen hdev->num_msi = 267560df7e91SHuazhong Tan hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 267607acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2677580a05f9SYonglong Liu 2678580a05f9SYonglong Liu hdev->num_nic_msix = hdev->num_msi; 2679580a05f9SYonglong Liu } 2680580a05f9SYonglong Liu 2681580a05f9SYonglong Liu if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) { 2682580a05f9SYonglong Liu dev_err(&hdev->pdev->dev, 2683580a05f9SYonglong Liu "Just %u msi resources, not enough for vf(min:2).\n", 2684580a05f9SYonglong Liu hdev->num_nic_msix); 2685580a05f9SYonglong Liu return -EINVAL; 268607acf909SJian Shen } 268707acf909SJian Shen 268807acf909SJian Shen return 0; 268907acf909SJian Shen } 269007acf909SJian Shen 2691af2aedc5SGuangbin Huang static void hclgevf_set_default_dev_specs(struct hclgevf_dev *hdev) 2692af2aedc5SGuangbin Huang { 2693af2aedc5SGuangbin Huang #define HCLGEVF_MAX_NON_TSO_BD_NUM 8U 2694af2aedc5SGuangbin Huang 2695af2aedc5SGuangbin Huang struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2696af2aedc5SGuangbin Huang 2697af2aedc5SGuangbin Huang ae_dev->dev_specs.max_non_tso_bd_num = 2698af2aedc5SGuangbin Huang HCLGEVF_MAX_NON_TSO_BD_NUM; 2699af2aedc5SGuangbin Huang ae_dev->dev_specs.rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 27007428d6c9SJie Wang ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 2701ab16b49cSHuazhong Tan ae_dev->dev_specs.max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 2702e070c8b9SYufeng Mo ae_dev->dev_specs.max_frm_size = HCLGEVF_MAC_MAX_FRAME; 2703af2aedc5SGuangbin Huang } 2704af2aedc5SGuangbin Huang 2705af2aedc5SGuangbin Huang static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev, 27066befad60SJie Wang struct hclge_desc *desc) 2707af2aedc5SGuangbin Huang { 2708af2aedc5SGuangbin Huang struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2709af2aedc5SGuangbin Huang struct hclgevf_dev_specs_0_cmd *req0; 2710ab16b49cSHuazhong Tan struct hclgevf_dev_specs_1_cmd *req1; 2711af2aedc5SGuangbin Huang 2712af2aedc5SGuangbin Huang req0 = (struct hclgevf_dev_specs_0_cmd *)desc[0].data; 2713ab16b49cSHuazhong Tan req1 = (struct hclgevf_dev_specs_1_cmd *)desc[1].data; 2714af2aedc5SGuangbin Huang 2715af2aedc5SGuangbin Huang ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 2716af2aedc5SGuangbin Huang ae_dev->dev_specs.rss_ind_tbl_size = 2717af2aedc5SGuangbin Huang le16_to_cpu(req0->rss_ind_tbl_size); 271891bfae25SHuazhong Tan ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 2719af2aedc5SGuangbin Huang ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 2720ab16b49cSHuazhong Tan ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 2721e070c8b9SYufeng Mo ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 2722af2aedc5SGuangbin Huang } 2723af2aedc5SGuangbin Huang 272413297028SGuangbin Huang static void hclgevf_check_dev_specs(struct hclgevf_dev *hdev) 272513297028SGuangbin Huang { 272613297028SGuangbin Huang struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 272713297028SGuangbin Huang 272813297028SGuangbin Huang if (!dev_specs->max_non_tso_bd_num) 272913297028SGuangbin Huang dev_specs->max_non_tso_bd_num = HCLGEVF_MAX_NON_TSO_BD_NUM; 273013297028SGuangbin Huang if (!dev_specs->rss_ind_tbl_size) 273113297028SGuangbin Huang dev_specs->rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 273213297028SGuangbin Huang if (!dev_specs->rss_key_size) 27337428d6c9SJie Wang dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 2734ab16b49cSHuazhong Tan if (!dev_specs->max_int_gl) 2735ab16b49cSHuazhong Tan dev_specs->max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 2736e070c8b9SYufeng Mo if (!dev_specs->max_frm_size) 2737e070c8b9SYufeng Mo dev_specs->max_frm_size = HCLGEVF_MAC_MAX_FRAME; 273813297028SGuangbin Huang } 273913297028SGuangbin Huang 2740af2aedc5SGuangbin Huang static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev) 2741af2aedc5SGuangbin Huang { 27426befad60SJie Wang struct hclge_desc desc[HCLGEVF_QUERY_DEV_SPECS_BD_NUM]; 2743af2aedc5SGuangbin Huang int ret; 2744af2aedc5SGuangbin Huang int i; 2745af2aedc5SGuangbin Huang 2746af2aedc5SGuangbin Huang /* set default specifications as devices lower than version V3 do not 2747af2aedc5SGuangbin Huang * support querying specifications from firmware. 2748af2aedc5SGuangbin Huang */ 2749af2aedc5SGuangbin Huang if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 2750af2aedc5SGuangbin Huang hclgevf_set_default_dev_specs(hdev); 2751af2aedc5SGuangbin Huang return 0; 2752af2aedc5SGuangbin Huang } 2753af2aedc5SGuangbin Huang 2754af2aedc5SGuangbin Huang for (i = 0; i < HCLGEVF_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 2755af2aedc5SGuangbin Huang hclgevf_cmd_setup_basic_desc(&desc[i], 275643710bfeSJie Wang HCLGE_OPC_QUERY_DEV_SPECS, true); 2757cb413bfaSJie Wang desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2758af2aedc5SGuangbin Huang } 275943710bfeSJie Wang hclgevf_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true); 2760af2aedc5SGuangbin Huang 2761af2aedc5SGuangbin Huang ret = hclgevf_cmd_send(&hdev->hw, desc, HCLGEVF_QUERY_DEV_SPECS_BD_NUM); 2762af2aedc5SGuangbin Huang if (ret) 2763af2aedc5SGuangbin Huang return ret; 2764af2aedc5SGuangbin Huang 2765af2aedc5SGuangbin Huang hclgevf_parse_dev_specs(hdev, desc); 276613297028SGuangbin Huang hclgevf_check_dev_specs(hdev); 2767af2aedc5SGuangbin Huang 2768af2aedc5SGuangbin Huang return 0; 2769af2aedc5SGuangbin Huang } 2770af2aedc5SGuangbin Huang 2771862d969aSHuazhong Tan static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2772862d969aSHuazhong Tan { 2773862d969aSHuazhong Tan struct pci_dev *pdev = hdev->pdev; 2774862d969aSHuazhong Tan int ret = 0; 2775862d969aSHuazhong Tan 2776862d969aSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2777862d969aSHuazhong Tan test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2778862d969aSHuazhong Tan hclgevf_misc_irq_uninit(hdev); 2779862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2780862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2781862d969aSHuazhong Tan } 2782862d969aSHuazhong Tan 2783862d969aSHuazhong Tan if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2784862d969aSHuazhong Tan pci_set_master(pdev); 2785862d969aSHuazhong Tan ret = hclgevf_init_msi(hdev); 2786862d969aSHuazhong Tan if (ret) { 2787862d969aSHuazhong Tan dev_err(&pdev->dev, 2788862d969aSHuazhong Tan "failed(%d) to init MSI/MSI-X\n", ret); 2789862d969aSHuazhong Tan return ret; 2790862d969aSHuazhong Tan } 2791862d969aSHuazhong Tan 2792862d969aSHuazhong Tan ret = hclgevf_misc_irq_init(hdev); 2793862d969aSHuazhong Tan if (ret) { 2794862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2795862d969aSHuazhong Tan dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2796862d969aSHuazhong Tan ret); 2797862d969aSHuazhong Tan return ret; 2798862d969aSHuazhong Tan } 2799862d969aSHuazhong Tan 2800862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2801862d969aSHuazhong Tan } 2802862d969aSHuazhong Tan 2803862d969aSHuazhong Tan return ret; 2804862d969aSHuazhong Tan } 2805862d969aSHuazhong Tan 2806039ba863SJian Shen static int hclgevf_clear_vport_list(struct hclgevf_dev *hdev) 2807039ba863SJian Shen { 2808039ba863SJian Shen struct hclge_vf_to_pf_msg send_msg; 2809039ba863SJian Shen 2810039ba863SJian Shen hclgevf_build_send_msg(&send_msg, HCLGE_MBX_HANDLE_VF_TBL, 2811039ba863SJian Shen HCLGE_MBX_VPORT_LIST_CLEAR); 2812039ba863SJian Shen return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2813039ba863SJian Shen } 2814039ba863SJian Shen 281579664077SHuazhong Tan static void hclgevf_init_rxd_adv_layout(struct hclgevf_dev *hdev) 281679664077SHuazhong Tan { 281779664077SHuazhong Tan if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 281879664077SHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 1); 281979664077SHuazhong Tan } 282079664077SHuazhong Tan 282179664077SHuazhong Tan static void hclgevf_uninit_rxd_adv_layout(struct hclgevf_dev *hdev) 282279664077SHuazhong Tan { 282379664077SHuazhong Tan if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 282479664077SHuazhong Tan hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 0); 282579664077SHuazhong Tan } 282679664077SHuazhong Tan 28279c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2828e2cb1decSSalil Mehta { 28297a01c897SSalil Mehta struct pci_dev *pdev = hdev->pdev; 2830e2cb1decSSalil Mehta int ret; 2831e2cb1decSSalil Mehta 2832862d969aSHuazhong Tan ret = hclgevf_pci_reset(hdev); 2833862d969aSHuazhong Tan if (ret) { 2834862d969aSHuazhong Tan dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2835862d969aSHuazhong Tan return ret; 2836862d969aSHuazhong Tan } 2837862d969aSHuazhong Tan 2838cb413bfaSJie Wang hclgevf_arq_init(hdev); 2839cb413bfaSJie Wang ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, 2840cb413bfaSJie Wang &hdev->fw_version, false, 2841cb413bfaSJie Wang hdev->reset_pending); 28429c6f7085SHuazhong Tan if (ret) { 28439c6f7085SHuazhong Tan dev_err(&pdev->dev, "cmd failed %d\n", ret); 28449c6f7085SHuazhong Tan return ret; 28457a01c897SSalil Mehta } 2846e2cb1decSSalil Mehta 28479c6f7085SHuazhong Tan ret = hclgevf_rss_init_hw(hdev); 28489c6f7085SHuazhong Tan if (ret) { 28499c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 28509c6f7085SHuazhong Tan "failed(%d) to initialize RSS\n", ret); 28519c6f7085SHuazhong Tan return ret; 28529c6f7085SHuazhong Tan } 28539c6f7085SHuazhong Tan 28543462207dSYufeng Mo ret = hclgevf_config_gro(hdev); 2855b26a6feaSPeng Li if (ret) 2856b26a6feaSPeng Li return ret; 2857b26a6feaSPeng Li 28589c6f7085SHuazhong Tan ret = hclgevf_init_vlan_config(hdev); 28599c6f7085SHuazhong Tan if (ret) { 28609c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 28619c6f7085SHuazhong Tan "failed(%d) to initialize VLAN config\n", ret); 28629c6f7085SHuazhong Tan return ret; 28639c6f7085SHuazhong Tan } 28649c6f7085SHuazhong Tan 2865*190cd8a7SJian Shen /* get current port based vlan state from PF */ 2866*190cd8a7SJian Shen ret = hclgevf_get_port_base_vlan_filter_state(hdev); 2867*190cd8a7SJian Shen if (ret) 2868*190cd8a7SJian Shen return ret; 2869*190cd8a7SJian Shen 2870c631c696SJian Shen set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 2871c631c696SJian Shen 287279664077SHuazhong Tan hclgevf_init_rxd_adv_layout(hdev); 287379664077SHuazhong Tan 28749c6f7085SHuazhong Tan dev_info(&hdev->pdev->dev, "Reset done\n"); 28759c6f7085SHuazhong Tan 28769c6f7085SHuazhong Tan return 0; 28779c6f7085SHuazhong Tan } 28789c6f7085SHuazhong Tan 28799c6f7085SHuazhong Tan static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 28809c6f7085SHuazhong Tan { 28819c6f7085SHuazhong Tan struct pci_dev *pdev = hdev->pdev; 28829c6f7085SHuazhong Tan int ret; 28839c6f7085SHuazhong Tan 2884e2cb1decSSalil Mehta ret = hclgevf_pci_init(hdev); 288560df7e91SHuazhong Tan if (ret) 2886e2cb1decSSalil Mehta return ret; 2887e2cb1decSSalil Mehta 2888cd624299SYufeng Mo ret = hclgevf_devlink_init(hdev); 2889cd624299SYufeng Mo if (ret) 2890cd624299SYufeng Mo goto err_devlink_init; 2891cd624299SYufeng Mo 2892cb413bfaSJie Wang ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw); 289360df7e91SHuazhong Tan if (ret) 28948b0195a3SHuazhong Tan goto err_cmd_queue_init; 28958b0195a3SHuazhong Tan 2896cb413bfaSJie Wang hclgevf_arq_init(hdev); 2897cb413bfaSJie Wang ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, 2898cb413bfaSJie Wang &hdev->fw_version, false, 2899cb413bfaSJie Wang hdev->reset_pending); 2900eddf0462SYunsheng Lin if (ret) 2901eddf0462SYunsheng Lin goto err_cmd_init; 2902eddf0462SYunsheng Lin 290307acf909SJian Shen /* Get vf resource */ 290407acf909SJian Shen ret = hclgevf_query_vf_resource(hdev); 290560df7e91SHuazhong Tan if (ret) 29068b0195a3SHuazhong Tan goto err_cmd_init; 290707acf909SJian Shen 2908af2aedc5SGuangbin Huang ret = hclgevf_query_dev_specs(hdev); 2909af2aedc5SGuangbin Huang if (ret) { 2910af2aedc5SGuangbin Huang dev_err(&pdev->dev, 2911af2aedc5SGuangbin Huang "failed to query dev specifications, ret = %d\n", ret); 2912af2aedc5SGuangbin Huang goto err_cmd_init; 2913af2aedc5SGuangbin Huang } 2914af2aedc5SGuangbin Huang 291507acf909SJian Shen ret = hclgevf_init_msi(hdev); 291607acf909SJian Shen if (ret) { 291707acf909SJian Shen dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 29188b0195a3SHuazhong Tan goto err_cmd_init; 291907acf909SJian Shen } 292007acf909SJian Shen 292107acf909SJian Shen hclgevf_state_init(hdev); 2922dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 2923afb6afdbSHuazhong Tan hdev->reset_type = HNAE3_NONE_RESET; 292407acf909SJian Shen 2925e2cb1decSSalil Mehta ret = hclgevf_misc_irq_init(hdev); 292660df7e91SHuazhong Tan if (ret) 2927e2cb1decSSalil Mehta goto err_misc_irq_init; 2928e2cb1decSSalil Mehta 2929862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2930862d969aSHuazhong Tan 2931e2cb1decSSalil Mehta ret = hclgevf_configure(hdev); 2932e2cb1decSSalil Mehta if (ret) { 2933e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2934e2cb1decSSalil Mehta goto err_config; 2935e2cb1decSSalil Mehta } 2936e2cb1decSSalil Mehta 2937e2cb1decSSalil Mehta ret = hclgevf_alloc_tqps(hdev); 2938e2cb1decSSalil Mehta if (ret) { 2939e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2940e2cb1decSSalil Mehta goto err_config; 2941e2cb1decSSalil Mehta } 2942e2cb1decSSalil Mehta 2943e2cb1decSSalil Mehta ret = hclgevf_set_handle_info(hdev); 294460df7e91SHuazhong Tan if (ret) 2945e2cb1decSSalil Mehta goto err_config; 2946e2cb1decSSalil Mehta 29473462207dSYufeng Mo ret = hclgevf_config_gro(hdev); 2948b26a6feaSPeng Li if (ret) 2949b26a6feaSPeng Li goto err_config; 2950b26a6feaSPeng Li 2951e2cb1decSSalil Mehta /* Initialize RSS for this VF */ 295293969dc1SJie Wang ret = hclge_comm_rss_init_cfg(&hdev->nic, hdev->ae_dev, 295393969dc1SJie Wang &hdev->rss_cfg); 295487ce161eSGuangbin Huang if (ret) { 295587ce161eSGuangbin Huang dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 295687ce161eSGuangbin Huang goto err_config; 295787ce161eSGuangbin Huang } 295887ce161eSGuangbin Huang 2959e2cb1decSSalil Mehta ret = hclgevf_rss_init_hw(hdev); 2960e2cb1decSSalil Mehta if (ret) { 2961e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2962e2cb1decSSalil Mehta "failed(%d) to initialize RSS\n", ret); 2963e2cb1decSSalil Mehta goto err_config; 2964e2cb1decSSalil Mehta } 2965e2cb1decSSalil Mehta 2966039ba863SJian Shen /* ensure vf tbl list as empty before init*/ 2967039ba863SJian Shen ret = hclgevf_clear_vport_list(hdev); 2968039ba863SJian Shen if (ret) { 2969039ba863SJian Shen dev_err(&pdev->dev, 2970039ba863SJian Shen "failed to clear tbl list configuration, ret = %d.\n", 2971039ba863SJian Shen ret); 2972039ba863SJian Shen goto err_config; 2973039ba863SJian Shen } 2974039ba863SJian Shen 2975e2cb1decSSalil Mehta ret = hclgevf_init_vlan_config(hdev); 2976e2cb1decSSalil Mehta if (ret) { 2977e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2978e2cb1decSSalil Mehta "failed(%d) to initialize VLAN config\n", ret); 2979e2cb1decSSalil Mehta goto err_config; 2980e2cb1decSSalil Mehta } 2981e2cb1decSSalil Mehta 298279664077SHuazhong Tan hclgevf_init_rxd_adv_layout(hdev); 298379664077SHuazhong Tan 29840251d196SGuangbin Huang set_bit(HCLGEVF_STATE_SERVICE_INITED, &hdev->state); 29850251d196SGuangbin Huang 29860742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 298708d80a4cSHuazhong Tan dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 298808d80a4cSHuazhong Tan HCLGEVF_DRIVER_NAME); 2989e2cb1decSSalil Mehta 2990ff200099SYunsheng Lin hclgevf_task_schedule(hdev, round_jiffies_relative(HZ)); 2991ff200099SYunsheng Lin 2992e2cb1decSSalil Mehta return 0; 2993e2cb1decSSalil Mehta 2994e2cb1decSSalil Mehta err_config: 2995e2cb1decSSalil Mehta hclgevf_misc_irq_uninit(hdev); 2996e2cb1decSSalil Mehta err_misc_irq_init: 2997e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2998e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 299907acf909SJian Shen err_cmd_init: 30009970308fSJie Wang hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 30018b0195a3SHuazhong Tan err_cmd_queue_init: 3002cd624299SYufeng Mo hclgevf_devlink_uninit(hdev); 3003cd624299SYufeng Mo err_devlink_init: 3004e2cb1decSSalil Mehta hclgevf_pci_uninit(hdev); 3005862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3006e2cb1decSSalil Mehta return ret; 3007e2cb1decSSalil Mehta } 3008e2cb1decSSalil Mehta 30097a01c897SSalil Mehta static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 3010e2cb1decSSalil Mehta { 3011d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 3012d3410018SYufeng Mo 3013e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 301479664077SHuazhong Tan hclgevf_uninit_rxd_adv_layout(hdev); 3015862d969aSHuazhong Tan 3016d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_VF_UNINIT, 0); 3017d3410018SYufeng Mo hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 301823b4201dSJian Shen 3019862d969aSHuazhong Tan if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3020eddf0462SYunsheng Lin hclgevf_misc_irq_uninit(hdev); 3021e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 30227a01c897SSalil Mehta } 30237a01c897SSalil Mehta 30249970308fSJie Wang hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 3025cd624299SYufeng Mo hclgevf_devlink_uninit(hdev); 3026e3364c5fSZenghui Yu hclgevf_pci_uninit(hdev); 3027ee4bcd3bSJian Shen hclgevf_uninit_mac_list(hdev); 3028862d969aSHuazhong Tan } 3029862d969aSHuazhong Tan 30307a01c897SSalil Mehta static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 30317a01c897SSalil Mehta { 30327a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 30337a01c897SSalil Mehta int ret; 30347a01c897SSalil Mehta 30357a01c897SSalil Mehta ret = hclgevf_alloc_hdev(ae_dev); 30367a01c897SSalil Mehta if (ret) { 30377a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device allocation failed\n"); 30387a01c897SSalil Mehta return ret; 30397a01c897SSalil Mehta } 30407a01c897SSalil Mehta 30417a01c897SSalil Mehta ret = hclgevf_init_hdev(ae_dev->priv); 3042a6d818e3SYunsheng Lin if (ret) { 30437a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device initialization failed\n"); 30447a01c897SSalil Mehta return ret; 30457a01c897SSalil Mehta } 30467a01c897SSalil Mehta 3047a6d818e3SYunsheng Lin return 0; 3048a6d818e3SYunsheng Lin } 3049a6d818e3SYunsheng Lin 30507a01c897SSalil Mehta static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 30517a01c897SSalil Mehta { 30527a01c897SSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 30537a01c897SSalil Mehta 30547a01c897SSalil Mehta hclgevf_uninit_hdev(hdev); 3055e2cb1decSSalil Mehta ae_dev->priv = NULL; 3056e2cb1decSSalil Mehta } 3057e2cb1decSSalil Mehta 3058849e4607SPeng Li static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 3059849e4607SPeng Li { 3060849e4607SPeng Li struct hnae3_handle *nic = &hdev->nic; 3061849e4607SPeng Li struct hnae3_knic_private_info *kinfo = &nic->kinfo; 3062849e4607SPeng Li 30638be73621SHuazhong Tan return min_t(u32, hdev->rss_size_max, 306435244430SJian Shen hdev->num_tqps / kinfo->tc_info.num_tc); 3065849e4607SPeng Li } 3066849e4607SPeng Li 3067849e4607SPeng Li /** 3068849e4607SPeng Li * hclgevf_get_channels - Get the current channels enabled and max supported. 3069849e4607SPeng Li * @handle: hardware information for network interface 3070849e4607SPeng Li * @ch: ethtool channels structure 3071849e4607SPeng Li * 3072849e4607SPeng Li * We don't support separate tx and rx queues as channels. The other count 3073849e4607SPeng Li * represents how many queues are being used for control. max_combined counts 3074849e4607SPeng Li * how many queue pairs we can support. They may not be mapped 1 to 1 with 3075849e4607SPeng Li * q_vectors since we support a lot more queue pairs than q_vectors. 3076849e4607SPeng Li **/ 3077849e4607SPeng Li static void hclgevf_get_channels(struct hnae3_handle *handle, 3078849e4607SPeng Li struct ethtool_channels *ch) 3079849e4607SPeng Li { 3080849e4607SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3081849e4607SPeng Li 3082849e4607SPeng Li ch->max_combined = hclgevf_get_max_channels(hdev); 3083849e4607SPeng Li ch->other_count = 0; 3084849e4607SPeng Li ch->max_other = 0; 30858be73621SHuazhong Tan ch->combined_count = handle->kinfo.rss_size; 3086849e4607SPeng Li } 3087849e4607SPeng Li 3088cc719218SPeng Li static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 30890d43bf45SHuazhong Tan u16 *alloc_tqps, u16 *max_rss_size) 3090cc719218SPeng Li { 3091cc719218SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3092cc719218SPeng Li 30930d43bf45SHuazhong Tan *alloc_tqps = hdev->num_tqps; 3094cc719218SPeng Li *max_rss_size = hdev->rss_size_max; 3095cc719218SPeng Li } 3096cc719218SPeng Li 30974093d1a2SGuangbin Huang static void hclgevf_update_rss_size(struct hnae3_handle *handle, 30984093d1a2SGuangbin Huang u32 new_tqps_num) 30994093d1a2SGuangbin Huang { 31004093d1a2SGuangbin Huang struct hnae3_knic_private_info *kinfo = &handle->kinfo; 31014093d1a2SGuangbin Huang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 31024093d1a2SGuangbin Huang u16 max_rss_size; 31034093d1a2SGuangbin Huang 31044093d1a2SGuangbin Huang kinfo->req_rss_size = new_tqps_num; 31054093d1a2SGuangbin Huang 31064093d1a2SGuangbin Huang max_rss_size = min_t(u16, hdev->rss_size_max, 310735244430SJian Shen hdev->num_tqps / kinfo->tc_info.num_tc); 31084093d1a2SGuangbin Huang 31094093d1a2SGuangbin Huang /* Use the user's configuration when it is not larger than 31104093d1a2SGuangbin Huang * max_rss_size, otherwise, use the maximum specification value. 31114093d1a2SGuangbin Huang */ 31124093d1a2SGuangbin Huang if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 31134093d1a2SGuangbin Huang kinfo->req_rss_size <= max_rss_size) 31144093d1a2SGuangbin Huang kinfo->rss_size = kinfo->req_rss_size; 31154093d1a2SGuangbin Huang else if (kinfo->rss_size > max_rss_size || 31164093d1a2SGuangbin Huang (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) 31174093d1a2SGuangbin Huang kinfo->rss_size = max_rss_size; 31184093d1a2SGuangbin Huang 311935244430SJian Shen kinfo->num_tqps = kinfo->tc_info.num_tc * kinfo->rss_size; 31204093d1a2SGuangbin Huang } 31214093d1a2SGuangbin Huang 31224093d1a2SGuangbin Huang static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 31234093d1a2SGuangbin Huang bool rxfh_configured) 31244093d1a2SGuangbin Huang { 31254093d1a2SGuangbin Huang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 31264093d1a2SGuangbin Huang struct hnae3_knic_private_info *kinfo = &handle->kinfo; 312793969dc1SJie Wang u16 tc_offset[HCLGE_COMM_MAX_TC_NUM]; 312893969dc1SJie Wang u16 tc_valid[HCLGE_COMM_MAX_TC_NUM]; 312993969dc1SJie Wang u16 tc_size[HCLGE_COMM_MAX_TC_NUM]; 31304093d1a2SGuangbin Huang u16 cur_rss_size = kinfo->rss_size; 31314093d1a2SGuangbin Huang u16 cur_tqps = kinfo->num_tqps; 31324093d1a2SGuangbin Huang u32 *rss_indir; 31334093d1a2SGuangbin Huang unsigned int i; 31344093d1a2SGuangbin Huang int ret; 31354093d1a2SGuangbin Huang 31364093d1a2SGuangbin Huang hclgevf_update_rss_size(handle, new_tqps_num); 31374093d1a2SGuangbin Huang 313893969dc1SJie Wang hclge_comm_get_rss_tc_info(cur_rss_size, hdev->hw_tc_map, 313993969dc1SJie Wang tc_offset, tc_valid, tc_size); 314093969dc1SJie Wang ret = hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, 314193969dc1SJie Wang tc_valid, tc_size); 31424093d1a2SGuangbin Huang if (ret) 31434093d1a2SGuangbin Huang return ret; 31444093d1a2SGuangbin Huang 3145cd7e963dSSalil Mehta /* RSS indirection table has been configured by user */ 31464093d1a2SGuangbin Huang if (rxfh_configured) 31474093d1a2SGuangbin Huang goto out; 31484093d1a2SGuangbin Huang 31494093d1a2SGuangbin Huang /* Reinitializes the rss indirect table according to the new RSS size */ 315087ce161eSGuangbin Huang rss_indir = kcalloc(hdev->ae_dev->dev_specs.rss_ind_tbl_size, 315187ce161eSGuangbin Huang sizeof(u32), GFP_KERNEL); 31524093d1a2SGuangbin Huang if (!rss_indir) 31534093d1a2SGuangbin Huang return -ENOMEM; 31544093d1a2SGuangbin Huang 315587ce161eSGuangbin Huang for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 31564093d1a2SGuangbin Huang rss_indir[i] = i % kinfo->rss_size; 31574093d1a2SGuangbin Huang 3158944de484SGuojia Liao hdev->rss_cfg.rss_size = kinfo->rss_size; 3159944de484SGuojia Liao 31604093d1a2SGuangbin Huang ret = hclgevf_set_rss(handle, rss_indir, NULL, 0); 31614093d1a2SGuangbin Huang if (ret) 31624093d1a2SGuangbin Huang dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 31634093d1a2SGuangbin Huang ret); 31644093d1a2SGuangbin Huang 31654093d1a2SGuangbin Huang kfree(rss_indir); 31664093d1a2SGuangbin Huang 31674093d1a2SGuangbin Huang out: 31684093d1a2SGuangbin Huang if (!ret) 31694093d1a2SGuangbin Huang dev_info(&hdev->pdev->dev, 31704093d1a2SGuangbin Huang "Channels changed, rss_size from %u to %u, tqps from %u to %u", 31714093d1a2SGuangbin Huang cur_rss_size, kinfo->rss_size, 317235244430SJian Shen cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 31734093d1a2SGuangbin Huang 31744093d1a2SGuangbin Huang return ret; 31754093d1a2SGuangbin Huang } 31764093d1a2SGuangbin Huang 3177175ec96bSFuyun Liang static int hclgevf_get_status(struct hnae3_handle *handle) 3178175ec96bSFuyun Liang { 3179175ec96bSFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3180175ec96bSFuyun Liang 3181175ec96bSFuyun Liang return hdev->hw.mac.link; 3182175ec96bSFuyun Liang } 3183175ec96bSFuyun Liang 31844a152de9SFuyun Liang static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 31854a152de9SFuyun Liang u8 *auto_neg, u32 *speed, 31864a152de9SFuyun Liang u8 *duplex) 31874a152de9SFuyun Liang { 31884a152de9SFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 31894a152de9SFuyun Liang 31904a152de9SFuyun Liang if (speed) 31914a152de9SFuyun Liang *speed = hdev->hw.mac.speed; 31924a152de9SFuyun Liang if (duplex) 31934a152de9SFuyun Liang *duplex = hdev->hw.mac.duplex; 31944a152de9SFuyun Liang if (auto_neg) 31954a152de9SFuyun Liang *auto_neg = AUTONEG_DISABLE; 31964a152de9SFuyun Liang } 31974a152de9SFuyun Liang 31984a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 31994a152de9SFuyun Liang u8 duplex) 32004a152de9SFuyun Liang { 32014a152de9SFuyun Liang hdev->hw.mac.speed = speed; 32024a152de9SFuyun Liang hdev->hw.mac.duplex = duplex; 32034a152de9SFuyun Liang } 32044a152de9SFuyun Liang 32051731be4cSYonglong Liu static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 32065c9f6b39SPeng Li { 32075c9f6b39SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 32083462207dSYufeng Mo bool gro_en_old = hdev->gro_en; 32093462207dSYufeng Mo int ret; 32105c9f6b39SPeng Li 32113462207dSYufeng Mo hdev->gro_en = enable; 32123462207dSYufeng Mo ret = hclgevf_config_gro(hdev); 32133462207dSYufeng Mo if (ret) 32143462207dSYufeng Mo hdev->gro_en = gro_en_old; 32153462207dSYufeng Mo 32163462207dSYufeng Mo return ret; 32175c9f6b39SPeng Li } 32185c9f6b39SPeng Li 321988d10bd6SJian Shen static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 322088d10bd6SJian Shen u8 *module_type) 3221c136b884SPeng Li { 3222c136b884SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 322388d10bd6SJian Shen 3224c136b884SPeng Li if (media_type) 3225c136b884SPeng Li *media_type = hdev->hw.mac.media_type; 322688d10bd6SJian Shen 322788d10bd6SJian Shen if (module_type) 322888d10bd6SJian Shen *module_type = hdev->hw.mac.module_type; 3229c136b884SPeng Li } 3230c136b884SPeng Li 32314d60291bSHuazhong Tan static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 32324d60291bSHuazhong Tan { 32334d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 32344d60291bSHuazhong Tan 3235aa5c4f17SHuazhong Tan return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 32364d60291bSHuazhong Tan } 32374d60291bSHuazhong Tan 3238fe735c84SHuazhong Tan static bool hclgevf_get_cmdq_stat(struct hnae3_handle *handle) 3239fe735c84SHuazhong Tan { 3240fe735c84SHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3241fe735c84SHuazhong Tan 3242076bb537SJie Wang return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3243fe735c84SHuazhong Tan } 3244fe735c84SHuazhong Tan 32454d60291bSHuazhong Tan static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 32464d60291bSHuazhong Tan { 32474d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 32484d60291bSHuazhong Tan 32494d60291bSHuazhong Tan return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 32504d60291bSHuazhong Tan } 32514d60291bSHuazhong Tan 32524d60291bSHuazhong Tan static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 32534d60291bSHuazhong Tan { 32544d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 32554d60291bSHuazhong Tan 3256c88a6e7dSHuazhong Tan return hdev->rst_stats.hw_rst_done_cnt; 32574d60291bSHuazhong Tan } 32584d60291bSHuazhong Tan 32599194d18bSliuzhongzhu static void hclgevf_get_link_mode(struct hnae3_handle *handle, 32609194d18bSliuzhongzhu unsigned long *supported, 32619194d18bSliuzhongzhu unsigned long *advertising) 32629194d18bSliuzhongzhu { 32639194d18bSliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 32649194d18bSliuzhongzhu 32659194d18bSliuzhongzhu *supported = hdev->hw.mac.supported; 32669194d18bSliuzhongzhu *advertising = hdev->hw.mac.advertising; 32679194d18bSliuzhongzhu } 32689194d18bSliuzhongzhu 32691600c3e5SJian Shen #define MAX_SEPARATE_NUM 4 3270e407efddSHuazhong Tan #define SEPARATOR_VALUE 0xFDFCFBFA 32711600c3e5SJian Shen #define REG_NUM_PER_LINE 4 32721600c3e5SJian Shen #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 32731600c3e5SJian Shen 32741600c3e5SJian Shen static int hclgevf_get_regs_len(struct hnae3_handle *handle) 32751600c3e5SJian Shen { 32761600c3e5SJian Shen int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 32771600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 32781600c3e5SJian Shen 32791600c3e5SJian Shen cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 32801600c3e5SJian Shen common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 32811600c3e5SJian Shen ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 32821600c3e5SJian Shen tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 32831600c3e5SJian Shen 32841600c3e5SJian Shen return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 32851600c3e5SJian Shen tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 32861600c3e5SJian Shen } 32871600c3e5SJian Shen 32881600c3e5SJian Shen static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 32891600c3e5SJian Shen void *data) 32901600c3e5SJian Shen { 32911600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 32921600c3e5SJian Shen int i, j, reg_um, separator_num; 32931600c3e5SJian Shen u32 *reg = data; 32941600c3e5SJian Shen 32951600c3e5SJian Shen *version = hdev->fw_version; 32961600c3e5SJian Shen 32971600c3e5SJian Shen /* fetching per-VF registers values from VF PCIe register space */ 32981600c3e5SJian Shen reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 32991600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 33001600c3e5SJian Shen for (i = 0; i < reg_um; i++) 33011600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 33021600c3e5SJian Shen for (i = 0; i < separator_num; i++) 33031600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 33041600c3e5SJian Shen 33051600c3e5SJian Shen reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 33061600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 33071600c3e5SJian Shen for (i = 0; i < reg_um; i++) 33081600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 33091600c3e5SJian Shen for (i = 0; i < separator_num; i++) 33101600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 33111600c3e5SJian Shen 33121600c3e5SJian Shen reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 33131600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 33141600c3e5SJian Shen for (j = 0; j < hdev->num_tqps; j++) { 33151600c3e5SJian Shen for (i = 0; i < reg_um; i++) 33161600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 33171600c3e5SJian Shen ring_reg_addr_list[i] + 33181600c3e5SJian Shen 0x200 * j); 33191600c3e5SJian Shen for (i = 0; i < separator_num; i++) 33201600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 33211600c3e5SJian Shen } 33221600c3e5SJian Shen 33231600c3e5SJian Shen reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 33241600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 33251600c3e5SJian Shen for (j = 0; j < hdev->num_msi_used - 1; j++) { 33261600c3e5SJian Shen for (i = 0; i < reg_um; i++) 33271600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 33281600c3e5SJian Shen tqp_intr_reg_addr_list[i] + 33291600c3e5SJian Shen 4 * j); 33301600c3e5SJian Shen for (i = 0; i < separator_num; i++) 33311600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 33321600c3e5SJian Shen } 33331600c3e5SJian Shen } 33341600c3e5SJian Shen 333592f11ea1SJian Shen void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 333692f11ea1SJian Shen u8 *port_base_vlan_info, u8 data_size) 333792f11ea1SJian Shen { 333892f11ea1SJian Shen struct hnae3_handle *nic = &hdev->nic; 3339d3410018SYufeng Mo struct hclge_vf_to_pf_msg send_msg; 3340a6f7bfdcSJian Shen int ret; 334192f11ea1SJian Shen 334292f11ea1SJian Shen rtnl_lock(); 3343a6f7bfdcSJian Shen 3344b7b5d25bSGuojia Liao if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 3345b7b5d25bSGuojia Liao test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) { 3346a6f7bfdcSJian Shen dev_warn(&hdev->pdev->dev, 3347a6f7bfdcSJian Shen "is resetting when updating port based vlan info\n"); 334892f11ea1SJian Shen rtnl_unlock(); 3349a6f7bfdcSJian Shen return; 3350a6f7bfdcSJian Shen } 3351a6f7bfdcSJian Shen 3352a6f7bfdcSJian Shen ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 3353a6f7bfdcSJian Shen if (ret) { 3354a6f7bfdcSJian Shen rtnl_unlock(); 3355a6f7bfdcSJian Shen return; 3356a6f7bfdcSJian Shen } 335792f11ea1SJian Shen 335892f11ea1SJian Shen /* send msg to PF and wait update port based vlan info */ 3359d3410018SYufeng Mo hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 3360d3410018SYufeng Mo HCLGE_MBX_PORT_BASE_VLAN_CFG); 3361d3410018SYufeng Mo memcpy(send_msg.data, port_base_vlan_info, data_size); 3362a6f7bfdcSJian Shen ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3363a6f7bfdcSJian Shen if (!ret) { 336492f11ea1SJian Shen if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 3365a6f7bfdcSJian Shen nic->port_base_vlan_state = state; 336692f11ea1SJian Shen else 336792f11ea1SJian Shen nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 3368a6f7bfdcSJian Shen } 336992f11ea1SJian Shen 337092f11ea1SJian Shen hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 337192f11ea1SJian Shen rtnl_unlock(); 337292f11ea1SJian Shen } 337392f11ea1SJian Shen 3374e2cb1decSSalil Mehta static const struct hnae3_ae_ops hclgevf_ops = { 3375e2cb1decSSalil Mehta .init_ae_dev = hclgevf_init_ae_dev, 3376e2cb1decSSalil Mehta .uninit_ae_dev = hclgevf_uninit_ae_dev, 3377bb1890d5SJiaran Zhang .reset_prepare = hclgevf_reset_prepare_general, 3378bb1890d5SJiaran Zhang .reset_done = hclgevf_reset_done, 3379e718a93fSPeng Li .init_client_instance = hclgevf_init_client_instance, 3380e718a93fSPeng Li .uninit_client_instance = hclgevf_uninit_client_instance, 3381e2cb1decSSalil Mehta .start = hclgevf_ae_start, 3382e2cb1decSSalil Mehta .stop = hclgevf_ae_stop, 3383a6d818e3SYunsheng Lin .client_start = hclgevf_client_start, 3384a6d818e3SYunsheng Lin .client_stop = hclgevf_client_stop, 3385e2cb1decSSalil Mehta .map_ring_to_vector = hclgevf_map_ring_to_vector, 3386e2cb1decSSalil Mehta .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 3387e2cb1decSSalil Mehta .get_vector = hclgevf_get_vector, 33880d3e6631SYunsheng Lin .put_vector = hclgevf_put_vector, 3389e2cb1decSSalil Mehta .reset_queue = hclgevf_reset_tqp, 3390e2cb1decSSalil Mehta .get_mac_addr = hclgevf_get_mac_addr, 3391e2cb1decSSalil Mehta .set_mac_addr = hclgevf_set_mac_addr, 3392e2cb1decSSalil Mehta .add_uc_addr = hclgevf_add_uc_addr, 3393e2cb1decSSalil Mehta .rm_uc_addr = hclgevf_rm_uc_addr, 3394e2cb1decSSalil Mehta .add_mc_addr = hclgevf_add_mc_addr, 3395e2cb1decSSalil Mehta .rm_mc_addr = hclgevf_rm_mc_addr, 3396e2cb1decSSalil Mehta .get_stats = hclgevf_get_stats, 3397e2cb1decSSalil Mehta .update_stats = hclgevf_update_stats, 3398e2cb1decSSalil Mehta .get_strings = hclgevf_get_strings, 3399e2cb1decSSalil Mehta .get_sset_count = hclgevf_get_sset_count, 3400027733b1SJie Wang .get_rss_key_size = hclge_comm_get_rss_key_size, 3401e2cb1decSSalil Mehta .get_rss = hclgevf_get_rss, 3402e2cb1decSSalil Mehta .set_rss = hclgevf_set_rss, 3403d97b3072SJian Shen .get_rss_tuple = hclgevf_get_rss_tuple, 3404d97b3072SJian Shen .set_rss_tuple = hclgevf_set_rss_tuple, 3405e2cb1decSSalil Mehta .get_tc_size = hclgevf_get_tc_size, 3406e2cb1decSSalil Mehta .get_fw_version = hclgevf_get_fw_version, 3407e2cb1decSSalil Mehta .set_vlan_filter = hclgevf_set_vlan_filter, 3408fa6a262aSJian Shen .enable_vlan_filter = hclgevf_enable_vlan_filter, 3409b2641e2aSYunsheng Lin .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 34106d4c3981SSalil Mehta .reset_event = hclgevf_reset_event, 3411720bd583SHuazhong Tan .set_default_reset_request = hclgevf_set_def_reset_request, 34124093d1a2SGuangbin Huang .set_channels = hclgevf_set_channels, 3413849e4607SPeng Li .get_channels = hclgevf_get_channels, 3414cc719218SPeng Li .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 34151600c3e5SJian Shen .get_regs_len = hclgevf_get_regs_len, 34161600c3e5SJian Shen .get_regs = hclgevf_get_regs, 3417175ec96bSFuyun Liang .get_status = hclgevf_get_status, 34184a152de9SFuyun Liang .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3419c136b884SPeng Li .get_media_type = hclgevf_get_media_type, 34204d60291bSHuazhong Tan .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 34214d60291bSHuazhong Tan .ae_dev_resetting = hclgevf_ae_dev_resetting, 34224d60291bSHuazhong Tan .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 34235c9f6b39SPeng Li .set_gro_en = hclgevf_gro_en, 3424818f1675SYunsheng Lin .set_mtu = hclgevf_set_mtu, 34250c29d191Sliuzhongzhu .get_global_queue_id = hclgevf_get_qid_global, 34268cdb992fSJian Shen .set_timer_task = hclgevf_set_timer_task, 34279194d18bSliuzhongzhu .get_link_mode = hclgevf_get_link_mode, 3428e196ec75SJian Shen .set_promisc_mode = hclgevf_set_promisc_mode, 3429c631c696SJian Shen .request_update_promisc_mode = hclgevf_request_update_promisc_mode, 3430fe735c84SHuazhong Tan .get_cmdq_stat = hclgevf_get_cmdq_stat, 3431e2cb1decSSalil Mehta }; 3432e2cb1decSSalil Mehta 3433e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf = { 3434e2cb1decSSalil Mehta .ops = &hclgevf_ops, 3435e2cb1decSSalil Mehta .pdev_id_table = ae_algovf_pci_tbl, 3436e2cb1decSSalil Mehta }; 3437e2cb1decSSalil Mehta 3438e2cb1decSSalil Mehta static int hclgevf_init(void) 3439e2cb1decSSalil Mehta { 3440e2cb1decSSalil Mehta pr_info("%s is initializing\n", HCLGEVF_NAME); 3441e2cb1decSSalil Mehta 3442f29da408SYufeng Mo hclgevf_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGEVF_NAME); 34430ea68902SYunsheng Lin if (!hclgevf_wq) { 34440ea68902SYunsheng Lin pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME); 34450ea68902SYunsheng Lin return -ENOMEM; 34460ea68902SYunsheng Lin } 34470ea68902SYunsheng Lin 3448854cf33aSFuyun Liang hnae3_register_ae_algo(&ae_algovf); 3449854cf33aSFuyun Liang 3450854cf33aSFuyun Liang return 0; 3451e2cb1decSSalil Mehta } 3452e2cb1decSSalil Mehta 3453e2cb1decSSalil Mehta static void hclgevf_exit(void) 3454e2cb1decSSalil Mehta { 3455e2cb1decSSalil Mehta hnae3_unregister_ae_algo(&ae_algovf); 34560ea68902SYunsheng Lin destroy_workqueue(hclgevf_wq); 3457e2cb1decSSalil Mehta } 3458e2cb1decSSalil Mehta module_init(hclgevf_init); 3459e2cb1decSSalil Mehta module_exit(hclgevf_exit); 3460e2cb1decSSalil Mehta 3461e2cb1decSSalil Mehta MODULE_LICENSE("GPL"); 3462e2cb1decSSalil Mehta MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3463e2cb1decSSalil Mehta MODULE_DESCRIPTION("HCLGEVF Driver"); 3464e2cb1decSSalil Mehta MODULE_VERSION(HCLGEVF_MOD_VERSION); 3465