1e2cb1decSSalil Mehta // SPDX-License-Identifier: GPL-2.0+ 2e2cb1decSSalil Mehta // Copyright (c) 2016-2017 Hisilicon Limited. 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #include <linux/etherdevice.h> 5aa5c4f17SHuazhong Tan #include <linux/iopoll.h> 66988eb2aSSalil Mehta #include <net/rtnetlink.h> 7e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 8e2cb1decSSalil Mehta #include "hclgevf_main.h" 9e2cb1decSSalil Mehta #include "hclge_mbx.h" 10e2cb1decSSalil Mehta #include "hnae3.h" 11e2cb1decSSalil Mehta 12e2cb1decSSalil Mehta #define HCLGEVF_NAME "hclgevf" 13e2cb1decSSalil Mehta 149c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 15e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf; 16e2cb1decSSalil Mehta 17e2cb1decSSalil Mehta static const struct pci_device_id ae_algovf_pci_tbl[] = { 18e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 19e2cb1decSSalil Mehta {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 20e2cb1decSSalil Mehta /* required last entry */ 21e2cb1decSSalil Mehta {0, } 22e2cb1decSSalil Mehta }; 23e2cb1decSSalil Mehta 24472d7eceSJian Shen static const u8 hclgevf_hash_key[] = { 25472d7eceSJian Shen 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 26472d7eceSJian Shen 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 27472d7eceSJian Shen 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 28472d7eceSJian Shen 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 29472d7eceSJian Shen 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 30472d7eceSJian Shen }; 31472d7eceSJian Shen 322f550a46SYunsheng Lin MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 332f550a46SYunsheng Lin 341600c3e5SJian Shen static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 351600c3e5SJian Shen HCLGEVF_CMDQ_TX_ADDR_H_REG, 361600c3e5SJian Shen HCLGEVF_CMDQ_TX_DEPTH_REG, 371600c3e5SJian Shen HCLGEVF_CMDQ_TX_TAIL_REG, 381600c3e5SJian Shen HCLGEVF_CMDQ_TX_HEAD_REG, 391600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_L_REG, 401600c3e5SJian Shen HCLGEVF_CMDQ_RX_ADDR_H_REG, 411600c3e5SJian Shen HCLGEVF_CMDQ_RX_DEPTH_REG, 421600c3e5SJian Shen HCLGEVF_CMDQ_RX_TAIL_REG, 431600c3e5SJian Shen HCLGEVF_CMDQ_RX_HEAD_REG, 441600c3e5SJian Shen HCLGEVF_VECTOR0_CMDQ_SRC_REG, 451600c3e5SJian Shen HCLGEVF_CMDQ_INTR_STS_REG, 461600c3e5SJian Shen HCLGEVF_CMDQ_INTR_EN_REG, 471600c3e5SJian Shen HCLGEVF_CMDQ_INTR_GEN_REG}; 481600c3e5SJian Shen 491600c3e5SJian Shen static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 501600c3e5SJian Shen HCLGEVF_RST_ING, 511600c3e5SJian Shen HCLGEVF_GRO_EN_REG}; 521600c3e5SJian Shen 531600c3e5SJian Shen static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 541600c3e5SJian Shen HCLGEVF_RING_RX_ADDR_H_REG, 551600c3e5SJian Shen HCLGEVF_RING_RX_BD_NUM_REG, 561600c3e5SJian Shen HCLGEVF_RING_RX_BD_LENGTH_REG, 571600c3e5SJian Shen HCLGEVF_RING_RX_MERGE_EN_REG, 581600c3e5SJian Shen HCLGEVF_RING_RX_TAIL_REG, 591600c3e5SJian Shen HCLGEVF_RING_RX_HEAD_REG, 601600c3e5SJian Shen HCLGEVF_RING_RX_FBD_NUM_REG, 611600c3e5SJian Shen HCLGEVF_RING_RX_OFFSET_REG, 621600c3e5SJian Shen HCLGEVF_RING_RX_FBD_OFFSET_REG, 631600c3e5SJian Shen HCLGEVF_RING_RX_STASH_REG, 641600c3e5SJian Shen HCLGEVF_RING_RX_BD_ERR_REG, 651600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_L_REG, 661600c3e5SJian Shen HCLGEVF_RING_TX_ADDR_H_REG, 671600c3e5SJian Shen HCLGEVF_RING_TX_BD_NUM_REG, 681600c3e5SJian Shen HCLGEVF_RING_TX_PRIORITY_REG, 691600c3e5SJian Shen HCLGEVF_RING_TX_TC_REG, 701600c3e5SJian Shen HCLGEVF_RING_TX_MERGE_EN_REG, 711600c3e5SJian Shen HCLGEVF_RING_TX_TAIL_REG, 721600c3e5SJian Shen HCLGEVF_RING_TX_HEAD_REG, 731600c3e5SJian Shen HCLGEVF_RING_TX_FBD_NUM_REG, 741600c3e5SJian Shen HCLGEVF_RING_TX_OFFSET_REG, 751600c3e5SJian Shen HCLGEVF_RING_TX_EBD_NUM_REG, 761600c3e5SJian Shen HCLGEVF_RING_TX_EBD_OFFSET_REG, 771600c3e5SJian Shen HCLGEVF_RING_TX_BD_ERR_REG, 781600c3e5SJian Shen HCLGEVF_RING_EN_REG}; 791600c3e5SJian Shen 801600c3e5SJian Shen static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 811600c3e5SJian Shen HCLGEVF_TQP_INTR_GL0_REG, 821600c3e5SJian Shen HCLGEVF_TQP_INTR_GL1_REG, 831600c3e5SJian Shen HCLGEVF_TQP_INTR_GL2_REG, 841600c3e5SJian Shen HCLGEVF_TQP_INTR_RL_REG}; 851600c3e5SJian Shen 86e2cb1decSSalil Mehta static inline struct hclgevf_dev *hclgevf_ae_get_hdev( 87e2cb1decSSalil Mehta struct hnae3_handle *handle) 88e2cb1decSSalil Mehta { 89eed9535fSPeng Li if (!handle->client) 90eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, nic); 91eed9535fSPeng Li else if (handle->client->type == HNAE3_CLIENT_ROCE) 92eed9535fSPeng Li return container_of(handle, struct hclgevf_dev, roce); 93eed9535fSPeng Li else 94e2cb1decSSalil Mehta return container_of(handle, struct hclgevf_dev, nic); 95e2cb1decSSalil Mehta } 96e2cb1decSSalil Mehta 97e2cb1decSSalil Mehta static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 98e2cb1decSSalil Mehta { 99b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 100e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 101e2cb1decSSalil Mehta struct hclgevf_desc desc; 102e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 103e2cb1decSSalil Mehta int status; 104e2cb1decSSalil Mehta int i; 105e2cb1decSSalil Mehta 106b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 107b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 108e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 109e2cb1decSSalil Mehta HCLGEVF_OPC_QUERY_RX_STATUS, 110e2cb1decSSalil Mehta true); 111e2cb1decSSalil Mehta 112e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 113e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 114e2cb1decSSalil Mehta if (status) { 115e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 116e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 117e2cb1decSSalil Mehta status, i); 118e2cb1decSSalil Mehta return status; 119e2cb1decSSalil Mehta } 120e2cb1decSSalil Mehta tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 121cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 122e2cb1decSSalil Mehta 123e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 124e2cb1decSSalil Mehta true); 125e2cb1decSSalil Mehta 126e2cb1decSSalil Mehta desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 127e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 128e2cb1decSSalil Mehta if (status) { 129e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 130e2cb1decSSalil Mehta "Query tqp stat fail, status = %d,queue = %d\n", 131e2cb1decSSalil Mehta status, i); 132e2cb1decSSalil Mehta return status; 133e2cb1decSSalil Mehta } 134e2cb1decSSalil Mehta tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 135cf72fa63SJian Shen le32_to_cpu(desc.data[1]); 136e2cb1decSSalil Mehta } 137e2cb1decSSalil Mehta 138e2cb1decSSalil Mehta return 0; 139e2cb1decSSalil Mehta } 140e2cb1decSSalil Mehta 141e2cb1decSSalil Mehta static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 142e2cb1decSSalil Mehta { 143e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo = &handle->kinfo; 144e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 145e2cb1decSSalil Mehta u64 *buff = data; 146e2cb1decSSalil Mehta int i; 147e2cb1decSSalil Mehta 148b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 149b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 150e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 151e2cb1decSSalil Mehta } 152e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 153b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 154e2cb1decSSalil Mehta *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 155e2cb1decSSalil Mehta } 156e2cb1decSSalil Mehta 157e2cb1decSSalil Mehta return buff; 158e2cb1decSSalil Mehta } 159e2cb1decSSalil Mehta 160e2cb1decSSalil Mehta static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 161e2cb1decSSalil Mehta { 162b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 163e2cb1decSSalil Mehta 164b4f1d303SJian Shen return kinfo->num_tqps * 2; 165e2cb1decSSalil Mehta } 166e2cb1decSSalil Mehta 167e2cb1decSSalil Mehta static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 168e2cb1decSSalil Mehta { 169b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 170e2cb1decSSalil Mehta u8 *buff = data; 171e2cb1decSSalil Mehta int i = 0; 172e2cb1decSSalil Mehta 173b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 174b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 175e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1760c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 177e2cb1decSSalil Mehta tqp->index); 178e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 179e2cb1decSSalil Mehta } 180e2cb1decSSalil Mehta 181b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 182b4f1d303SJian Shen struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 183e2cb1decSSalil Mehta struct hclgevf_tqp, q); 1840c218123SJian Shen snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 185e2cb1decSSalil Mehta tqp->index); 186e2cb1decSSalil Mehta buff += ETH_GSTRING_LEN; 187e2cb1decSSalil Mehta } 188e2cb1decSSalil Mehta 189e2cb1decSSalil Mehta return buff; 190e2cb1decSSalil Mehta } 191e2cb1decSSalil Mehta 192e2cb1decSSalil Mehta static void hclgevf_update_stats(struct hnae3_handle *handle, 193e2cb1decSSalil Mehta struct net_device_stats *net_stats) 194e2cb1decSSalil Mehta { 195e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 196e2cb1decSSalil Mehta int status; 197e2cb1decSSalil Mehta 198e2cb1decSSalil Mehta status = hclgevf_tqps_update_stats(handle); 199e2cb1decSSalil Mehta if (status) 200e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 201e2cb1decSSalil Mehta "VF update of TQPS stats fail, status = %d.\n", 202e2cb1decSSalil Mehta status); 203e2cb1decSSalil Mehta } 204e2cb1decSSalil Mehta 205e2cb1decSSalil Mehta static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 206e2cb1decSSalil Mehta { 207e2cb1decSSalil Mehta if (strset == ETH_SS_TEST) 208e2cb1decSSalil Mehta return -EOPNOTSUPP; 209e2cb1decSSalil Mehta else if (strset == ETH_SS_STATS) 210e2cb1decSSalil Mehta return hclgevf_tqps_get_sset_count(handle, strset); 211e2cb1decSSalil Mehta 212e2cb1decSSalil Mehta return 0; 213e2cb1decSSalil Mehta } 214e2cb1decSSalil Mehta 215e2cb1decSSalil Mehta static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 216e2cb1decSSalil Mehta u8 *data) 217e2cb1decSSalil Mehta { 218e2cb1decSSalil Mehta u8 *p = (char *)data; 219e2cb1decSSalil Mehta 220e2cb1decSSalil Mehta if (strset == ETH_SS_STATS) 221e2cb1decSSalil Mehta p = hclgevf_tqps_get_strings(handle, p); 222e2cb1decSSalil Mehta } 223e2cb1decSSalil Mehta 224e2cb1decSSalil Mehta static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 225e2cb1decSSalil Mehta { 226e2cb1decSSalil Mehta hclgevf_tqps_get_stats(handle, data); 227e2cb1decSSalil Mehta } 228e2cb1decSSalil Mehta 229e2cb1decSSalil Mehta static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 230e2cb1decSSalil Mehta { 231e2cb1decSSalil Mehta u8 resp_msg; 232e2cb1decSSalil Mehta int status; 233e2cb1decSSalil Mehta 234e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 235e2cb1decSSalil Mehta true, &resp_msg, sizeof(u8)); 236e2cb1decSSalil Mehta if (status) { 237e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 238e2cb1decSSalil Mehta "VF request to get TC info from PF failed %d", 239e2cb1decSSalil Mehta status); 240e2cb1decSSalil Mehta return status; 241e2cb1decSSalil Mehta } 242e2cb1decSSalil Mehta 243e2cb1decSSalil Mehta hdev->hw_tc_map = resp_msg; 244e2cb1decSSalil Mehta 245e2cb1decSSalil Mehta return 0; 246e2cb1decSSalil Mehta } 247e2cb1decSSalil Mehta 2486cee6fc3SJian Shen static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 249e2cb1decSSalil Mehta { 250e2cb1decSSalil Mehta #define HCLGEVF_TQPS_RSS_INFO_LEN 8 251e2cb1decSSalil Mehta u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 252e2cb1decSSalil Mehta int status; 253e2cb1decSSalil Mehta 254e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 255e2cb1decSSalil Mehta true, resp_msg, 256e2cb1decSSalil Mehta HCLGEVF_TQPS_RSS_INFO_LEN); 257e2cb1decSSalil Mehta if (status) { 258e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 259e2cb1decSSalil Mehta "VF request to get tqp info from PF failed %d", 260e2cb1decSSalil Mehta status); 261e2cb1decSSalil Mehta return status; 262e2cb1decSSalil Mehta } 263e2cb1decSSalil Mehta 264e2cb1decSSalil Mehta memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 265e2cb1decSSalil Mehta memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 266e2cb1decSSalil Mehta memcpy(&hdev->num_desc, &resp_msg[4], sizeof(u16)); 267e2cb1decSSalil Mehta memcpy(&hdev->rx_buf_len, &resp_msg[6], sizeof(u16)); 268e2cb1decSSalil Mehta 269e2cb1decSSalil Mehta return 0; 270e2cb1decSSalil Mehta } 271e2cb1decSSalil Mehta 2720c29d191Sliuzhongzhu static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 2730c29d191Sliuzhongzhu { 2740c29d191Sliuzhongzhu struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2750c29d191Sliuzhongzhu u8 msg_data[2], resp_data[2]; 2760c29d191Sliuzhongzhu u16 qid_in_pf = 0; 2770c29d191Sliuzhongzhu int ret; 2780c29d191Sliuzhongzhu 2790c29d191Sliuzhongzhu memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 2800c29d191Sliuzhongzhu 2810c29d191Sliuzhongzhu ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data, 2820c29d191Sliuzhongzhu 2, true, resp_data, 2); 2830c29d191Sliuzhongzhu if (!ret) 2840c29d191Sliuzhongzhu qid_in_pf = *(u16 *)resp_data; 2850c29d191Sliuzhongzhu 2860c29d191Sliuzhongzhu return qid_in_pf; 2870c29d191Sliuzhongzhu } 2880c29d191Sliuzhongzhu 289e2cb1decSSalil Mehta static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 290e2cb1decSSalil Mehta { 291e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 292e2cb1decSSalil Mehta int i; 293e2cb1decSSalil Mehta 294e2cb1decSSalil Mehta hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 295e2cb1decSSalil Mehta sizeof(struct hclgevf_tqp), GFP_KERNEL); 296e2cb1decSSalil Mehta if (!hdev->htqp) 297e2cb1decSSalil Mehta return -ENOMEM; 298e2cb1decSSalil Mehta 299e2cb1decSSalil Mehta tqp = hdev->htqp; 300e2cb1decSSalil Mehta 301e2cb1decSSalil Mehta for (i = 0; i < hdev->num_tqps; i++) { 302e2cb1decSSalil Mehta tqp->dev = &hdev->pdev->dev; 303e2cb1decSSalil Mehta tqp->index = i; 304e2cb1decSSalil Mehta 305e2cb1decSSalil Mehta tqp->q.ae_algo = &ae_algovf; 306e2cb1decSSalil Mehta tqp->q.buf_size = hdev->rx_buf_len; 307e2cb1decSSalil Mehta tqp->q.desc_num = hdev->num_desc; 308e2cb1decSSalil Mehta tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 309e2cb1decSSalil Mehta i * HCLGEVF_TQP_REG_SIZE; 310e2cb1decSSalil Mehta 311e2cb1decSSalil Mehta tqp++; 312e2cb1decSSalil Mehta } 313e2cb1decSSalil Mehta 314e2cb1decSSalil Mehta return 0; 315e2cb1decSSalil Mehta } 316e2cb1decSSalil Mehta 317e2cb1decSSalil Mehta static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 318e2cb1decSSalil Mehta { 319e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 320e2cb1decSSalil Mehta struct hnae3_knic_private_info *kinfo; 321e2cb1decSSalil Mehta u16 new_tqps = hdev->num_tqps; 322e2cb1decSSalil Mehta int i; 323e2cb1decSSalil Mehta 324e2cb1decSSalil Mehta kinfo = &nic->kinfo; 325e2cb1decSSalil Mehta kinfo->num_tc = 0; 326e2cb1decSSalil Mehta kinfo->num_desc = hdev->num_desc; 327e2cb1decSSalil Mehta kinfo->rx_buf_len = hdev->rx_buf_len; 328e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 329e2cb1decSSalil Mehta if (hdev->hw_tc_map & BIT(i)) 330e2cb1decSSalil Mehta kinfo->num_tc++; 331e2cb1decSSalil Mehta 332e2cb1decSSalil Mehta kinfo->rss_size 333e2cb1decSSalil Mehta = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 334e2cb1decSSalil Mehta new_tqps = kinfo->rss_size * kinfo->num_tc; 335e2cb1decSSalil Mehta kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 336e2cb1decSSalil Mehta 337e2cb1decSSalil Mehta kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 338e2cb1decSSalil Mehta sizeof(struct hnae3_queue *), GFP_KERNEL); 339e2cb1decSSalil Mehta if (!kinfo->tqp) 340e2cb1decSSalil Mehta return -ENOMEM; 341e2cb1decSSalil Mehta 342e2cb1decSSalil Mehta for (i = 0; i < kinfo->num_tqps; i++) { 343e2cb1decSSalil Mehta hdev->htqp[i].q.handle = &hdev->nic; 344e2cb1decSSalil Mehta hdev->htqp[i].q.tqp_index = i; 345e2cb1decSSalil Mehta kinfo->tqp[i] = &hdev->htqp[i].q; 346e2cb1decSSalil Mehta } 347e2cb1decSSalil Mehta 348e2cb1decSSalil Mehta return 0; 349e2cb1decSSalil Mehta } 350e2cb1decSSalil Mehta 351e2cb1decSSalil Mehta static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 352e2cb1decSSalil Mehta { 353e2cb1decSSalil Mehta int status; 354e2cb1decSSalil Mehta u8 resp_msg; 355e2cb1decSSalil Mehta 356e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 357e2cb1decSSalil Mehta 0, false, &resp_msg, sizeof(u8)); 358e2cb1decSSalil Mehta if (status) 359e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 360e2cb1decSSalil Mehta "VF failed to fetch link status(%d) from PF", status); 361e2cb1decSSalil Mehta } 362e2cb1decSSalil Mehta 363e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 364e2cb1decSSalil Mehta { 36545e92b7eSPeng Li struct hnae3_handle *rhandle = &hdev->roce; 366e2cb1decSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 36745e92b7eSPeng Li struct hnae3_client *rclient; 368e2cb1decSSalil Mehta struct hnae3_client *client; 369e2cb1decSSalil Mehta 370e2cb1decSSalil Mehta client = handle->client; 37145e92b7eSPeng Li rclient = hdev->roce_client; 372e2cb1decSSalil Mehta 373582d37bbSPeng Li link_state = 374582d37bbSPeng Li test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 375582d37bbSPeng Li 376e2cb1decSSalil Mehta if (link_state != hdev->hw.mac.link) { 377e2cb1decSSalil Mehta client->ops->link_status_change(handle, !!link_state); 37845e92b7eSPeng Li if (rclient && rclient->ops->link_status_change) 37945e92b7eSPeng Li rclient->ops->link_status_change(rhandle, !!link_state); 380e2cb1decSSalil Mehta hdev->hw.mac.link = link_state; 381e2cb1decSSalil Mehta } 382e2cb1decSSalil Mehta } 383e2cb1decSSalil Mehta 384e2cb1decSSalil Mehta static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 385e2cb1decSSalil Mehta { 386e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 387e2cb1decSSalil Mehta int ret; 388e2cb1decSSalil Mehta 389e2cb1decSSalil Mehta nic->ae_algo = &ae_algovf; 390e2cb1decSSalil Mehta nic->pdev = hdev->pdev; 391e2cb1decSSalil Mehta nic->numa_node_mask = hdev->numa_node_mask; 392424eb834SSalil Mehta nic->flags |= HNAE3_SUPPORT_VF; 393e2cb1decSSalil Mehta 394e2cb1decSSalil Mehta if (hdev->ae_dev->dev_type != HNAE3_DEV_KNIC) { 395e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "unsupported device type %d\n", 396e2cb1decSSalil Mehta hdev->ae_dev->dev_type); 397e2cb1decSSalil Mehta return -EINVAL; 398e2cb1decSSalil Mehta } 399e2cb1decSSalil Mehta 400e2cb1decSSalil Mehta ret = hclgevf_knic_setup(hdev); 401e2cb1decSSalil Mehta if (ret) 402e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 403e2cb1decSSalil Mehta ret); 404e2cb1decSSalil Mehta return ret; 405e2cb1decSSalil Mehta } 406e2cb1decSSalil Mehta 407e2cb1decSSalil Mehta static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 408e2cb1decSSalil Mehta { 40936cbbdf6SPeng Li if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 41036cbbdf6SPeng Li dev_warn(&hdev->pdev->dev, 41136cbbdf6SPeng Li "vector(vector_id %d) has been freed.\n", vector_id); 41236cbbdf6SPeng Li return; 41336cbbdf6SPeng Li } 41436cbbdf6SPeng Li 415e2cb1decSSalil Mehta hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 416e2cb1decSSalil Mehta hdev->num_msi_left += 1; 417e2cb1decSSalil Mehta hdev->num_msi_used -= 1; 418e2cb1decSSalil Mehta } 419e2cb1decSSalil Mehta 420e2cb1decSSalil Mehta static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 421e2cb1decSSalil Mehta struct hnae3_vector_info *vector_info) 422e2cb1decSSalil Mehta { 423e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 424e2cb1decSSalil Mehta struct hnae3_vector_info *vector = vector_info; 425e2cb1decSSalil Mehta int alloc = 0; 426e2cb1decSSalil Mehta int i, j; 427e2cb1decSSalil Mehta 428e2cb1decSSalil Mehta vector_num = min(hdev->num_msi_left, vector_num); 429e2cb1decSSalil Mehta 430e2cb1decSSalil Mehta for (j = 0; j < vector_num; j++) { 431e2cb1decSSalil Mehta for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 432e2cb1decSSalil Mehta if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 433e2cb1decSSalil Mehta vector->vector = pci_irq_vector(hdev->pdev, i); 434e2cb1decSSalil Mehta vector->io_addr = hdev->hw.io_base + 435e2cb1decSSalil Mehta HCLGEVF_VECTOR_REG_BASE + 436e2cb1decSSalil Mehta (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 437e2cb1decSSalil Mehta hdev->vector_status[i] = 0; 438e2cb1decSSalil Mehta hdev->vector_irq[i] = vector->vector; 439e2cb1decSSalil Mehta 440e2cb1decSSalil Mehta vector++; 441e2cb1decSSalil Mehta alloc++; 442e2cb1decSSalil Mehta 443e2cb1decSSalil Mehta break; 444e2cb1decSSalil Mehta } 445e2cb1decSSalil Mehta } 446e2cb1decSSalil Mehta } 447e2cb1decSSalil Mehta hdev->num_msi_left -= alloc; 448e2cb1decSSalil Mehta hdev->num_msi_used += alloc; 449e2cb1decSSalil Mehta 450e2cb1decSSalil Mehta return alloc; 451e2cb1decSSalil Mehta } 452e2cb1decSSalil Mehta 453e2cb1decSSalil Mehta static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 454e2cb1decSSalil Mehta { 455e2cb1decSSalil Mehta int i; 456e2cb1decSSalil Mehta 457e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 458e2cb1decSSalil Mehta if (vector == hdev->vector_irq[i]) 459e2cb1decSSalil Mehta return i; 460e2cb1decSSalil Mehta 461e2cb1decSSalil Mehta return -EINVAL; 462e2cb1decSSalil Mehta } 463e2cb1decSSalil Mehta 464374ad291SJian Shen static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 465374ad291SJian Shen const u8 hfunc, const u8 *key) 466374ad291SJian Shen { 467374ad291SJian Shen struct hclgevf_rss_config_cmd *req; 468374ad291SJian Shen struct hclgevf_desc desc; 469374ad291SJian Shen int key_offset; 470374ad291SJian Shen int key_size; 471374ad291SJian Shen int ret; 472374ad291SJian Shen 473374ad291SJian Shen req = (struct hclgevf_rss_config_cmd *)desc.data; 474374ad291SJian Shen 475374ad291SJian Shen for (key_offset = 0; key_offset < 3; key_offset++) { 476374ad291SJian Shen hclgevf_cmd_setup_basic_desc(&desc, 477374ad291SJian Shen HCLGEVF_OPC_RSS_GENERIC_CONFIG, 478374ad291SJian Shen false); 479374ad291SJian Shen 480374ad291SJian Shen req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 481374ad291SJian Shen req->hash_config |= 482374ad291SJian Shen (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 483374ad291SJian Shen 484374ad291SJian Shen if (key_offset == 2) 485374ad291SJian Shen key_size = 486374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE - HCLGEVF_RSS_HASH_KEY_NUM * 2; 487374ad291SJian Shen else 488374ad291SJian Shen key_size = HCLGEVF_RSS_HASH_KEY_NUM; 489374ad291SJian Shen 490374ad291SJian Shen memcpy(req->hash_key, 491374ad291SJian Shen key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 492374ad291SJian Shen 493374ad291SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 494374ad291SJian Shen if (ret) { 495374ad291SJian Shen dev_err(&hdev->pdev->dev, 496374ad291SJian Shen "Configure RSS config fail, status = %d\n", 497374ad291SJian Shen ret); 498374ad291SJian Shen return ret; 499374ad291SJian Shen } 500374ad291SJian Shen } 501374ad291SJian Shen 502374ad291SJian Shen return 0; 503374ad291SJian Shen } 504374ad291SJian Shen 505e2cb1decSSalil Mehta static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 506e2cb1decSSalil Mehta { 507e2cb1decSSalil Mehta return HCLGEVF_RSS_KEY_SIZE; 508e2cb1decSSalil Mehta } 509e2cb1decSSalil Mehta 510e2cb1decSSalil Mehta static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 511e2cb1decSSalil Mehta { 512e2cb1decSSalil Mehta return HCLGEVF_RSS_IND_TBL_SIZE; 513e2cb1decSSalil Mehta } 514e2cb1decSSalil Mehta 515e2cb1decSSalil Mehta static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 516e2cb1decSSalil Mehta { 517e2cb1decSSalil Mehta const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 518e2cb1decSSalil Mehta struct hclgevf_rss_indirection_table_cmd *req; 519e2cb1decSSalil Mehta struct hclgevf_desc desc; 520e2cb1decSSalil Mehta int status; 521e2cb1decSSalil Mehta int i, j; 522e2cb1decSSalil Mehta 523e2cb1decSSalil Mehta req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 524e2cb1decSSalil Mehta 525e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 526e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 527e2cb1decSSalil Mehta false); 528e2cb1decSSalil Mehta req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 529e2cb1decSSalil Mehta req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 530e2cb1decSSalil Mehta for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 531e2cb1decSSalil Mehta req->rss_result[j] = 532e2cb1decSSalil Mehta indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 533e2cb1decSSalil Mehta 534e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 535e2cb1decSSalil Mehta if (status) { 536e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 537e2cb1decSSalil Mehta "VF failed(=%d) to set RSS indirection table\n", 538e2cb1decSSalil Mehta status); 539e2cb1decSSalil Mehta return status; 540e2cb1decSSalil Mehta } 541e2cb1decSSalil Mehta } 542e2cb1decSSalil Mehta 543e2cb1decSSalil Mehta return 0; 544e2cb1decSSalil Mehta } 545e2cb1decSSalil Mehta 546e2cb1decSSalil Mehta static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 547e2cb1decSSalil Mehta { 548e2cb1decSSalil Mehta struct hclgevf_rss_tc_mode_cmd *req; 549e2cb1decSSalil Mehta u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 550e2cb1decSSalil Mehta u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 551e2cb1decSSalil Mehta u16 tc_size[HCLGEVF_MAX_TC_NUM]; 552e2cb1decSSalil Mehta struct hclgevf_desc desc; 553e2cb1decSSalil Mehta u16 roundup_size; 554e2cb1decSSalil Mehta int status; 555e2cb1decSSalil Mehta int i; 556e2cb1decSSalil Mehta 557e2cb1decSSalil Mehta req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 558e2cb1decSSalil Mehta 559e2cb1decSSalil Mehta roundup_size = roundup_pow_of_two(rss_size); 560e2cb1decSSalil Mehta roundup_size = ilog2(roundup_size); 561e2cb1decSSalil Mehta 562e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 563e2cb1decSSalil Mehta tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 564e2cb1decSSalil Mehta tc_size[i] = roundup_size; 565e2cb1decSSalil Mehta tc_offset[i] = rss_size * i; 566e2cb1decSSalil Mehta } 567e2cb1decSSalil Mehta 568e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 569e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 570e4e87715SPeng Li hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 571e2cb1decSSalil Mehta (tc_valid[i] & 0x1)); 572e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 573e2cb1decSSalil Mehta HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 574e4e87715SPeng Li hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 575e2cb1decSSalil Mehta HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 576e2cb1decSSalil Mehta } 577e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 578e2cb1decSSalil Mehta if (status) 579e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 580e2cb1decSSalil Mehta "VF failed(=%d) to set rss tc mode\n", status); 581e2cb1decSSalil Mehta 582e2cb1decSSalil Mehta return status; 583e2cb1decSSalil Mehta } 584e2cb1decSSalil Mehta 585e2cb1decSSalil Mehta static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 586e2cb1decSSalil Mehta u8 *hfunc) 587e2cb1decSSalil Mehta { 588e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 589e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 590e2cb1decSSalil Mehta int i; 591e2cb1decSSalil Mehta 592374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 593374ad291SJian Shen /* Get hash algorithm */ 594374ad291SJian Shen if (hfunc) { 595374ad291SJian Shen switch (rss_cfg->hash_algo) { 596374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 597374ad291SJian Shen *hfunc = ETH_RSS_HASH_TOP; 598374ad291SJian Shen break; 599374ad291SJian Shen case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 600374ad291SJian Shen *hfunc = ETH_RSS_HASH_XOR; 601374ad291SJian Shen break; 602374ad291SJian Shen default: 603374ad291SJian Shen *hfunc = ETH_RSS_HASH_UNKNOWN; 604374ad291SJian Shen break; 605374ad291SJian Shen } 606374ad291SJian Shen } 607374ad291SJian Shen 608374ad291SJian Shen /* Get the RSS Key required by the user */ 609374ad291SJian Shen if (key) 610374ad291SJian Shen memcpy(key, rss_cfg->rss_hash_key, 611374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 612374ad291SJian Shen } 613374ad291SJian Shen 614e2cb1decSSalil Mehta if (indir) 615e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 616e2cb1decSSalil Mehta indir[i] = rss_cfg->rss_indirection_tbl[i]; 617e2cb1decSSalil Mehta 618374ad291SJian Shen return 0; 619e2cb1decSSalil Mehta } 620e2cb1decSSalil Mehta 621e2cb1decSSalil Mehta static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 622e2cb1decSSalil Mehta const u8 *key, const u8 hfunc) 623e2cb1decSSalil Mehta { 624e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 625e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 626374ad291SJian Shen int ret, i; 627374ad291SJian Shen 628374ad291SJian Shen if (handle->pdev->revision >= 0x21) { 629374ad291SJian Shen /* Set the RSS Hash Key if specififed by the user */ 630374ad291SJian Shen if (key) { 631374ad291SJian Shen switch (hfunc) { 632374ad291SJian Shen case ETH_RSS_HASH_TOP: 633374ad291SJian Shen rss_cfg->hash_algo = 634374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 635374ad291SJian Shen break; 636374ad291SJian Shen case ETH_RSS_HASH_XOR: 637374ad291SJian Shen rss_cfg->hash_algo = 638374ad291SJian Shen HCLGEVF_RSS_HASH_ALGO_SIMPLE; 639374ad291SJian Shen break; 640374ad291SJian Shen case ETH_RSS_HASH_NO_CHANGE: 641374ad291SJian Shen break; 642374ad291SJian Shen default: 643374ad291SJian Shen return -EINVAL; 644374ad291SJian Shen } 645374ad291SJian Shen 646374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 647374ad291SJian Shen key); 648374ad291SJian Shen if (ret) 649374ad291SJian Shen return ret; 650374ad291SJian Shen 651374ad291SJian Shen /* Update the shadow RSS key with user specified qids */ 652374ad291SJian Shen memcpy(rss_cfg->rss_hash_key, key, 653374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 654374ad291SJian Shen } 655374ad291SJian Shen } 656e2cb1decSSalil Mehta 657e2cb1decSSalil Mehta /* update the shadow RSS table with user specified qids */ 658e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 659e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = indir[i]; 660e2cb1decSSalil Mehta 661e2cb1decSSalil Mehta /* update the hardware */ 662e2cb1decSSalil Mehta return hclgevf_set_rss_indir_table(hdev); 663e2cb1decSSalil Mehta } 664e2cb1decSSalil Mehta 665d97b3072SJian Shen static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 666d97b3072SJian Shen { 667d97b3072SJian Shen u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 668d97b3072SJian Shen 669d97b3072SJian Shen if (nfc->data & RXH_L4_B_2_3) 670d97b3072SJian Shen hash_sets |= HCLGEVF_D_PORT_BIT; 671d97b3072SJian Shen else 672d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_PORT_BIT; 673d97b3072SJian Shen 674d97b3072SJian Shen if (nfc->data & RXH_IP_SRC) 675d97b3072SJian Shen hash_sets |= HCLGEVF_S_IP_BIT; 676d97b3072SJian Shen else 677d97b3072SJian Shen hash_sets &= ~HCLGEVF_S_IP_BIT; 678d97b3072SJian Shen 679d97b3072SJian Shen if (nfc->data & RXH_IP_DST) 680d97b3072SJian Shen hash_sets |= HCLGEVF_D_IP_BIT; 681d97b3072SJian Shen else 682d97b3072SJian Shen hash_sets &= ~HCLGEVF_D_IP_BIT; 683d97b3072SJian Shen 684d97b3072SJian Shen if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 685d97b3072SJian Shen hash_sets |= HCLGEVF_V_TAG_BIT; 686d97b3072SJian Shen 687d97b3072SJian Shen return hash_sets; 688d97b3072SJian Shen } 689d97b3072SJian Shen 690d97b3072SJian Shen static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 691d97b3072SJian Shen struct ethtool_rxnfc *nfc) 692d97b3072SJian Shen { 693d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 694d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 695d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 696d97b3072SJian Shen struct hclgevf_desc desc; 697d97b3072SJian Shen u8 tuple_sets; 698d97b3072SJian Shen int ret; 699d97b3072SJian Shen 700d97b3072SJian Shen if (handle->pdev->revision == 0x20) 701d97b3072SJian Shen return -EOPNOTSUPP; 702d97b3072SJian Shen 703d97b3072SJian Shen if (nfc->data & 704d97b3072SJian Shen ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 705d97b3072SJian Shen return -EINVAL; 706d97b3072SJian Shen 707d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 708d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 709d97b3072SJian Shen 710d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 711d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 712d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 713d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 714d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 715d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 716d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 717d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 718d97b3072SJian Shen 719d97b3072SJian Shen tuple_sets = hclgevf_get_rss_hash_bits(nfc); 720d97b3072SJian Shen switch (nfc->flow_type) { 721d97b3072SJian Shen case TCP_V4_FLOW: 722d97b3072SJian Shen req->ipv4_tcp_en = tuple_sets; 723d97b3072SJian Shen break; 724d97b3072SJian Shen case TCP_V6_FLOW: 725d97b3072SJian Shen req->ipv6_tcp_en = tuple_sets; 726d97b3072SJian Shen break; 727d97b3072SJian Shen case UDP_V4_FLOW: 728d97b3072SJian Shen req->ipv4_udp_en = tuple_sets; 729d97b3072SJian Shen break; 730d97b3072SJian Shen case UDP_V6_FLOW: 731d97b3072SJian Shen req->ipv6_udp_en = tuple_sets; 732d97b3072SJian Shen break; 733d97b3072SJian Shen case SCTP_V4_FLOW: 734d97b3072SJian Shen req->ipv4_sctp_en = tuple_sets; 735d97b3072SJian Shen break; 736d97b3072SJian Shen case SCTP_V6_FLOW: 737d97b3072SJian Shen if ((nfc->data & RXH_L4_B_0_1) || 738d97b3072SJian Shen (nfc->data & RXH_L4_B_2_3)) 739d97b3072SJian Shen return -EINVAL; 740d97b3072SJian Shen 741d97b3072SJian Shen req->ipv6_sctp_en = tuple_sets; 742d97b3072SJian Shen break; 743d97b3072SJian Shen case IPV4_FLOW: 744d97b3072SJian Shen req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 745d97b3072SJian Shen break; 746d97b3072SJian Shen case IPV6_FLOW: 747d97b3072SJian Shen req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 748d97b3072SJian Shen break; 749d97b3072SJian Shen default: 750d97b3072SJian Shen return -EINVAL; 751d97b3072SJian Shen } 752d97b3072SJian Shen 753d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 754d97b3072SJian Shen if (ret) { 755d97b3072SJian Shen dev_err(&hdev->pdev->dev, 756d97b3072SJian Shen "Set rss tuple fail, status = %d\n", ret); 757d97b3072SJian Shen return ret; 758d97b3072SJian Shen } 759d97b3072SJian Shen 760d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 761d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 762d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 763d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 764d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 765d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 766d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 767d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 768d97b3072SJian Shen return 0; 769d97b3072SJian Shen } 770d97b3072SJian Shen 771d97b3072SJian Shen static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 772d97b3072SJian Shen struct ethtool_rxnfc *nfc) 773d97b3072SJian Shen { 774d97b3072SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 775d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 776d97b3072SJian Shen u8 tuple_sets; 777d97b3072SJian Shen 778d97b3072SJian Shen if (handle->pdev->revision == 0x20) 779d97b3072SJian Shen return -EOPNOTSUPP; 780d97b3072SJian Shen 781d97b3072SJian Shen nfc->data = 0; 782d97b3072SJian Shen 783d97b3072SJian Shen switch (nfc->flow_type) { 784d97b3072SJian Shen case TCP_V4_FLOW: 785d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 786d97b3072SJian Shen break; 787d97b3072SJian Shen case UDP_V4_FLOW: 788d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 789d97b3072SJian Shen break; 790d97b3072SJian Shen case TCP_V6_FLOW: 791d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 792d97b3072SJian Shen break; 793d97b3072SJian Shen case UDP_V6_FLOW: 794d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 795d97b3072SJian Shen break; 796d97b3072SJian Shen case SCTP_V4_FLOW: 797d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 798d97b3072SJian Shen break; 799d97b3072SJian Shen case SCTP_V6_FLOW: 800d97b3072SJian Shen tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 801d97b3072SJian Shen break; 802d97b3072SJian Shen case IPV4_FLOW: 803d97b3072SJian Shen case IPV6_FLOW: 804d97b3072SJian Shen tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 805d97b3072SJian Shen break; 806d97b3072SJian Shen default: 807d97b3072SJian Shen return -EINVAL; 808d97b3072SJian Shen } 809d97b3072SJian Shen 810d97b3072SJian Shen if (!tuple_sets) 811d97b3072SJian Shen return 0; 812d97b3072SJian Shen 813d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_PORT_BIT) 814d97b3072SJian Shen nfc->data |= RXH_L4_B_2_3; 815d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_PORT_BIT) 816d97b3072SJian Shen nfc->data |= RXH_L4_B_0_1; 817d97b3072SJian Shen if (tuple_sets & HCLGEVF_D_IP_BIT) 818d97b3072SJian Shen nfc->data |= RXH_IP_DST; 819d97b3072SJian Shen if (tuple_sets & HCLGEVF_S_IP_BIT) 820d97b3072SJian Shen nfc->data |= RXH_IP_SRC; 821d97b3072SJian Shen 822d97b3072SJian Shen return 0; 823d97b3072SJian Shen } 824d97b3072SJian Shen 825d97b3072SJian Shen static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 826d97b3072SJian Shen struct hclgevf_rss_cfg *rss_cfg) 827d97b3072SJian Shen { 828d97b3072SJian Shen struct hclgevf_rss_input_tuple_cmd *req; 829d97b3072SJian Shen struct hclgevf_desc desc; 830d97b3072SJian Shen int ret; 831d97b3072SJian Shen 832d97b3072SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 833d97b3072SJian Shen 834d97b3072SJian Shen req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 835d97b3072SJian Shen 836d97b3072SJian Shen req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 837d97b3072SJian Shen req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 838d97b3072SJian Shen req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 839d97b3072SJian Shen req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 840d97b3072SJian Shen req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 841d97b3072SJian Shen req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 842d97b3072SJian Shen req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 843d97b3072SJian Shen req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 844d97b3072SJian Shen 845d97b3072SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 846d97b3072SJian Shen if (ret) 847d97b3072SJian Shen dev_err(&hdev->pdev->dev, 848d97b3072SJian Shen "Configure rss input fail, status = %d\n", ret); 849d97b3072SJian Shen return ret; 850d97b3072SJian Shen } 851d97b3072SJian Shen 852e2cb1decSSalil Mehta static int hclgevf_get_tc_size(struct hnae3_handle *handle) 853e2cb1decSSalil Mehta { 854e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 855e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 856e2cb1decSSalil Mehta 857e2cb1decSSalil Mehta return rss_cfg->rss_size; 858e2cb1decSSalil Mehta } 859e2cb1decSSalil Mehta 860e2cb1decSSalil Mehta static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 861b204bc74SPeng Li int vector_id, 862e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 863e2cb1decSSalil Mehta { 864e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 865e2cb1decSSalil Mehta struct hnae3_ring_chain_node *node; 866e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 867e2cb1decSSalil Mehta struct hclgevf_desc desc; 868b204bc74SPeng Li int i = 0; 869e2cb1decSSalil Mehta int status; 870e2cb1decSSalil Mehta u8 type; 871e2cb1decSSalil Mehta 872e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 873e2cb1decSSalil Mehta 874e2cb1decSSalil Mehta for (node = ring_chain; node; node = node->next) { 8755d02a58dSYunsheng Lin int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 8765d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 8775d02a58dSYunsheng Lin 8785d02a58dSYunsheng Lin if (i == 0) { 8795d02a58dSYunsheng Lin hclgevf_cmd_setup_basic_desc(&desc, 8805d02a58dSYunsheng Lin HCLGEVF_OPC_MBX_VF_TO_PF, 8815d02a58dSYunsheng Lin false); 8825d02a58dSYunsheng Lin type = en ? 8835d02a58dSYunsheng Lin HCLGE_MBX_MAP_RING_TO_VECTOR : 8845d02a58dSYunsheng Lin HCLGE_MBX_UNMAP_RING_TO_VECTOR; 8855d02a58dSYunsheng Lin req->msg[0] = type; 8865d02a58dSYunsheng Lin req->msg[1] = vector_id; 8875d02a58dSYunsheng Lin } 8885d02a58dSYunsheng Lin 8895d02a58dSYunsheng Lin req->msg[idx_offset] = 890e4e87715SPeng Li hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 8915d02a58dSYunsheng Lin req->msg[idx_offset + 1] = node->tqp_index; 892e4e87715SPeng Li req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 89379eee410SFuyun Liang HNAE3_RING_GL_IDX_M, 89479eee410SFuyun Liang HNAE3_RING_GL_IDX_S); 89579eee410SFuyun Liang 8965d02a58dSYunsheng Lin i++; 8975d02a58dSYunsheng Lin if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 8985d02a58dSYunsheng Lin HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 8995d02a58dSYunsheng Lin HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 9005d02a58dSYunsheng Lin !node->next) { 901e2cb1decSSalil Mehta req->msg[2] = i; 902e2cb1decSSalil Mehta 903e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 904e2cb1decSSalil Mehta if (status) { 905e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 906e2cb1decSSalil Mehta "Map TQP fail, status is %d.\n", 907e2cb1decSSalil Mehta status); 908e2cb1decSSalil Mehta return status; 909e2cb1decSSalil Mehta } 910e2cb1decSSalil Mehta i = 0; 911e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, 912e2cb1decSSalil Mehta HCLGEVF_OPC_MBX_VF_TO_PF, 913e2cb1decSSalil Mehta false); 914e2cb1decSSalil Mehta req->msg[0] = type; 915e2cb1decSSalil Mehta req->msg[1] = vector_id; 916e2cb1decSSalil Mehta } 917e2cb1decSSalil Mehta } 918e2cb1decSSalil Mehta 919e2cb1decSSalil Mehta return 0; 920e2cb1decSSalil Mehta } 921e2cb1decSSalil Mehta 922e2cb1decSSalil Mehta static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 923e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 924e2cb1decSSalil Mehta { 925b204bc74SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 926b204bc74SPeng Li int vector_id; 927b204bc74SPeng Li 928b204bc74SPeng Li vector_id = hclgevf_get_vector_index(hdev, vector); 929b204bc74SPeng Li if (vector_id < 0) { 930b204bc74SPeng Li dev_err(&handle->pdev->dev, 931b204bc74SPeng Li "Get vector index fail. ret =%d\n", vector_id); 932b204bc74SPeng Li return vector_id; 933b204bc74SPeng Li } 934b204bc74SPeng Li 935b204bc74SPeng Li return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 936e2cb1decSSalil Mehta } 937e2cb1decSSalil Mehta 938e2cb1decSSalil Mehta static int hclgevf_unmap_ring_from_vector( 939e2cb1decSSalil Mehta struct hnae3_handle *handle, 940e2cb1decSSalil Mehta int vector, 941e2cb1decSSalil Mehta struct hnae3_ring_chain_node *ring_chain) 942e2cb1decSSalil Mehta { 943e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 944e2cb1decSSalil Mehta int ret, vector_id; 945e2cb1decSSalil Mehta 946dea846e8SHuazhong Tan if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 947dea846e8SHuazhong Tan return 0; 948dea846e8SHuazhong Tan 949e2cb1decSSalil Mehta vector_id = hclgevf_get_vector_index(hdev, vector); 950e2cb1decSSalil Mehta if (vector_id < 0) { 951e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 952e2cb1decSSalil Mehta "Get vector index fail. ret =%d\n", vector_id); 953e2cb1decSSalil Mehta return vector_id; 954e2cb1decSSalil Mehta } 955e2cb1decSSalil Mehta 956b204bc74SPeng Li ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 9570d3e6631SYunsheng Lin if (ret) 958e2cb1decSSalil Mehta dev_err(&handle->pdev->dev, 959e2cb1decSSalil Mehta "Unmap ring from vector fail. vector=%d, ret =%d\n", 960e2cb1decSSalil Mehta vector_id, 961e2cb1decSSalil Mehta ret); 9620d3e6631SYunsheng Lin 963e2cb1decSSalil Mehta return ret; 964e2cb1decSSalil Mehta } 965e2cb1decSSalil Mehta 9660d3e6631SYunsheng Lin static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 9670d3e6631SYunsheng Lin { 9680d3e6631SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 96903718db9SYunsheng Lin int vector_id; 9700d3e6631SYunsheng Lin 97103718db9SYunsheng Lin vector_id = hclgevf_get_vector_index(hdev, vector); 97203718db9SYunsheng Lin if (vector_id < 0) { 97303718db9SYunsheng Lin dev_err(&handle->pdev->dev, 97403718db9SYunsheng Lin "hclgevf_put_vector get vector index fail. ret =%d\n", 97503718db9SYunsheng Lin vector_id); 97603718db9SYunsheng Lin return vector_id; 97703718db9SYunsheng Lin } 97803718db9SYunsheng Lin 97903718db9SYunsheng Lin hclgevf_free_vector(hdev, vector_id); 980e2cb1decSSalil Mehta 981e2cb1decSSalil Mehta return 0; 982e2cb1decSSalil Mehta } 983e2cb1decSSalil Mehta 9843b75c3dfSPeng Li static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 985f01f5559SJian Shen bool en_bc_pmc) 986e2cb1decSSalil Mehta { 987e2cb1decSSalil Mehta struct hclge_mbx_vf_to_pf_cmd *req; 988e2cb1decSSalil Mehta struct hclgevf_desc desc; 989f01f5559SJian Shen int ret; 990e2cb1decSSalil Mehta 991e2cb1decSSalil Mehta req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 992e2cb1decSSalil Mehta 993e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 994e2cb1decSSalil Mehta req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 995f01f5559SJian Shen req->msg[1] = en_bc_pmc ? 1 : 0; 996e2cb1decSSalil Mehta 997f01f5559SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 998f01f5559SJian Shen if (ret) 999e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1000f01f5559SJian Shen "Set promisc mode fail, status is %d.\n", ret); 1001e2cb1decSSalil Mehta 1002f01f5559SJian Shen return ret; 1003e2cb1decSSalil Mehta } 1004e2cb1decSSalil Mehta 1005f01f5559SJian Shen static int hclgevf_set_promisc_mode(struct hclgevf_dev *hdev, bool en_bc_pmc) 1006e2cb1decSSalil Mehta { 1007f01f5559SJian Shen return hclgevf_cmd_set_promisc_mode(hdev, en_bc_pmc); 1008e2cb1decSSalil Mehta } 1009e2cb1decSSalil Mehta 1010e2cb1decSSalil Mehta static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, int tqp_id, 1011e2cb1decSSalil Mehta int stream_id, bool enable) 1012e2cb1decSSalil Mehta { 1013e2cb1decSSalil Mehta struct hclgevf_cfg_com_tqp_queue_cmd *req; 1014e2cb1decSSalil Mehta struct hclgevf_desc desc; 1015e2cb1decSSalil Mehta int status; 1016e2cb1decSSalil Mehta 1017e2cb1decSSalil Mehta req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1018e2cb1decSSalil Mehta 1019e2cb1decSSalil Mehta hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1020e2cb1decSSalil Mehta false); 1021e2cb1decSSalil Mehta req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1022e2cb1decSSalil Mehta req->stream_id = cpu_to_le16(stream_id); 1023e2cb1decSSalil Mehta req->enable |= enable << HCLGEVF_TQP_ENABLE_B; 1024e2cb1decSSalil Mehta 1025e2cb1decSSalil Mehta status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1026e2cb1decSSalil Mehta if (status) 1027e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 1028e2cb1decSSalil Mehta "TQP enable fail, status =%d.\n", status); 1029e2cb1decSSalil Mehta 1030e2cb1decSSalil Mehta return status; 1031e2cb1decSSalil Mehta } 1032e2cb1decSSalil Mehta 1033e2cb1decSSalil Mehta static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1034e2cb1decSSalil Mehta { 1035b4f1d303SJian Shen struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1036e2cb1decSSalil Mehta struct hclgevf_tqp *tqp; 1037e2cb1decSSalil Mehta int i; 1038e2cb1decSSalil Mehta 1039b4f1d303SJian Shen for (i = 0; i < kinfo->num_tqps; i++) { 1040b4f1d303SJian Shen tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1041e2cb1decSSalil Mehta memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1042e2cb1decSSalil Mehta } 1043e2cb1decSSalil Mehta } 1044e2cb1decSSalil Mehta 1045e2cb1decSSalil Mehta static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1046e2cb1decSSalil Mehta { 1047e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1048e2cb1decSSalil Mehta 1049e2cb1decSSalil Mehta ether_addr_copy(p, hdev->hw.mac.mac_addr); 1050e2cb1decSSalil Mehta } 1051e2cb1decSSalil Mehta 105259098055SFuyun Liang static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 105359098055SFuyun Liang bool is_first) 1054e2cb1decSSalil Mehta { 1055e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1056e2cb1decSSalil Mehta u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1057e2cb1decSSalil Mehta u8 *new_mac_addr = (u8 *)p; 1058e2cb1decSSalil Mehta u8 msg_data[ETH_ALEN * 2]; 105959098055SFuyun Liang u16 subcode; 1060e2cb1decSSalil Mehta int status; 1061e2cb1decSSalil Mehta 1062e2cb1decSSalil Mehta ether_addr_copy(msg_data, new_mac_addr); 1063e2cb1decSSalil Mehta ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 1064e2cb1decSSalil Mehta 106559098055SFuyun Liang subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 106659098055SFuyun Liang HCLGE_MBX_MAC_VLAN_UC_MODIFY; 106759098055SFuyun Liang 1068e2cb1decSSalil Mehta status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 106959098055SFuyun Liang subcode, msg_data, ETH_ALEN * 2, 10702097fdefSJian Shen true, NULL, 0); 1071e2cb1decSSalil Mehta if (!status) 1072e2cb1decSSalil Mehta ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1073e2cb1decSSalil Mehta 1074e2cb1decSSalil Mehta return status; 1075e2cb1decSSalil Mehta } 1076e2cb1decSSalil Mehta 1077e2cb1decSSalil Mehta static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1078e2cb1decSSalil Mehta const unsigned char *addr) 1079e2cb1decSSalil Mehta { 1080e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1081e2cb1decSSalil Mehta 1082e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1083e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_ADD, 1084e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1085e2cb1decSSalil Mehta } 1086e2cb1decSSalil Mehta 1087e2cb1decSSalil Mehta static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1088e2cb1decSSalil Mehta const unsigned char *addr) 1089e2cb1decSSalil Mehta { 1090e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1091e2cb1decSSalil Mehta 1092e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1093e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1094e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1095e2cb1decSSalil Mehta } 1096e2cb1decSSalil Mehta 1097e2cb1decSSalil Mehta static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1098e2cb1decSSalil Mehta const unsigned char *addr) 1099e2cb1decSSalil Mehta { 1100e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1101e2cb1decSSalil Mehta 1102e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1103e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_ADD, 1104e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1105e2cb1decSSalil Mehta } 1106e2cb1decSSalil Mehta 1107e2cb1decSSalil Mehta static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1108e2cb1decSSalil Mehta const unsigned char *addr) 1109e2cb1decSSalil Mehta { 1110e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1111e2cb1decSSalil Mehta 1112e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1113e2cb1decSSalil Mehta HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1114e2cb1decSSalil Mehta addr, ETH_ALEN, false, NULL, 0); 1115e2cb1decSSalil Mehta } 1116e2cb1decSSalil Mehta 1117e2cb1decSSalil Mehta static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1118e2cb1decSSalil Mehta __be16 proto, u16 vlan_id, 1119e2cb1decSSalil Mehta bool is_kill) 1120e2cb1decSSalil Mehta { 1121e2cb1decSSalil Mehta #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1122e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1123e2cb1decSSalil Mehta u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1124e2cb1decSSalil Mehta 1125e2cb1decSSalil Mehta if (vlan_id > 4095) 1126e2cb1decSSalil Mehta return -EINVAL; 1127e2cb1decSSalil Mehta 1128e2cb1decSSalil Mehta if (proto != htons(ETH_P_8021Q)) 1129e2cb1decSSalil Mehta return -EPROTONOSUPPORT; 1130e2cb1decSSalil Mehta 1131e2cb1decSSalil Mehta msg_data[0] = is_kill; 1132e2cb1decSSalil Mehta memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1133e2cb1decSSalil Mehta memcpy(&msg_data[3], &proto, sizeof(proto)); 1134e2cb1decSSalil Mehta return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1135e2cb1decSSalil Mehta HCLGE_MBX_VLAN_FILTER, msg_data, 1136e2cb1decSSalil Mehta HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 1137e2cb1decSSalil Mehta } 1138e2cb1decSSalil Mehta 1139b2641e2aSYunsheng Lin static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1140b2641e2aSYunsheng Lin { 1141b2641e2aSYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1142b2641e2aSYunsheng Lin u8 msg_data; 1143b2641e2aSYunsheng Lin 1144b2641e2aSYunsheng Lin msg_data = enable ? 1 : 0; 1145b2641e2aSYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1146b2641e2aSYunsheng Lin HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1147b2641e2aSYunsheng Lin 1, false, NULL, 0); 1148b2641e2aSYunsheng Lin } 1149b2641e2aSYunsheng Lin 11507fa6be4fSHuazhong Tan static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1151e2cb1decSSalil Mehta { 1152e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1153e2cb1decSSalil Mehta u8 msg_data[2]; 11541a426f8bSPeng Li int ret; 1155e2cb1decSSalil Mehta 1156e2cb1decSSalil Mehta memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 1157e2cb1decSSalil Mehta 11581a426f8bSPeng Li /* disable vf queue before send queue reset msg to PF */ 11591a426f8bSPeng Li ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 11601a426f8bSPeng Li if (ret) 11617fa6be4fSHuazhong Tan return ret; 11621a426f8bSPeng Li 11637fa6be4fSHuazhong Tan return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 11641a426f8bSPeng Li 2, true, NULL, 0); 1165e2cb1decSSalil Mehta } 1166e2cb1decSSalil Mehta 1167818f1675SYunsheng Lin static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1168818f1675SYunsheng Lin { 1169818f1675SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1170818f1675SYunsheng Lin 1171818f1675SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu, 1172818f1675SYunsheng Lin sizeof(new_mtu), true, NULL, 0); 1173818f1675SYunsheng Lin } 1174818f1675SYunsheng Lin 11756988eb2aSSalil Mehta static int hclgevf_notify_client(struct hclgevf_dev *hdev, 11766988eb2aSSalil Mehta enum hnae3_reset_notify_type type) 11776988eb2aSSalil Mehta { 11786988eb2aSSalil Mehta struct hnae3_client *client = hdev->nic_client; 11796988eb2aSSalil Mehta struct hnae3_handle *handle = &hdev->nic; 11806a5f6fa3SHuazhong Tan int ret; 11816988eb2aSSalil Mehta 11826988eb2aSSalil Mehta if (!client->ops->reset_notify) 11836988eb2aSSalil Mehta return -EOPNOTSUPP; 11846988eb2aSSalil Mehta 11856a5f6fa3SHuazhong Tan ret = client->ops->reset_notify(handle, type); 11866a5f6fa3SHuazhong Tan if (ret) 11876a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 11886a5f6fa3SHuazhong Tan type, ret); 11896a5f6fa3SHuazhong Tan 11906a5f6fa3SHuazhong Tan return ret; 11916988eb2aSSalil Mehta } 11926988eb2aSSalil Mehta 11936ff3cf07SHuazhong Tan static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 11946ff3cf07SHuazhong Tan { 11956ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 11966ff3cf07SHuazhong Tan 11976ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DONE, &hdev->flr_state); 11986ff3cf07SHuazhong Tan } 11996ff3cf07SHuazhong Tan 12006ff3cf07SHuazhong Tan static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev, 12016ff3cf07SHuazhong Tan unsigned long delay_us, 12026ff3cf07SHuazhong Tan unsigned long wait_cnt) 12036ff3cf07SHuazhong Tan { 12046ff3cf07SHuazhong Tan unsigned long cnt = 0; 12056ff3cf07SHuazhong Tan 12066ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) && 12076ff3cf07SHuazhong Tan cnt++ < wait_cnt) 12086ff3cf07SHuazhong Tan usleep_range(delay_us, delay_us * 2); 12096ff3cf07SHuazhong Tan 12106ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) { 12116ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 12126ff3cf07SHuazhong Tan "flr wait timeout\n"); 12136ff3cf07SHuazhong Tan return -ETIMEDOUT; 12146ff3cf07SHuazhong Tan } 12156ff3cf07SHuazhong Tan 12166ff3cf07SHuazhong Tan return 0; 12176ff3cf07SHuazhong Tan } 12186ff3cf07SHuazhong Tan 12196988eb2aSSalil Mehta static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 12206988eb2aSSalil Mehta { 1221aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_US 20000 1222aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_CNT 2000 1223aa5c4f17SHuazhong Tan #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1224aa5c4f17SHuazhong Tan (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1225aa5c4f17SHuazhong Tan 1226aa5c4f17SHuazhong Tan u32 val; 1227aa5c4f17SHuazhong Tan int ret; 12286988eb2aSSalil Mehta 12296988eb2aSSalil Mehta /* wait to check the hardware reset completion status */ 1230aa5c4f17SHuazhong Tan val = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1231aa5c4f17SHuazhong Tan dev_info(&hdev->pdev->dev, "checking vf resetting status: %x\n", val); 1232aa5c4f17SHuazhong Tan 12336ff3cf07SHuazhong Tan if (hdev->reset_type == HNAE3_FLR_RESET) 12346ff3cf07SHuazhong Tan return hclgevf_flr_poll_timeout(hdev, 12356ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_US, 12366ff3cf07SHuazhong Tan HCLGEVF_RESET_WAIT_CNT); 12376ff3cf07SHuazhong Tan 1238aa5c4f17SHuazhong Tan ret = readl_poll_timeout(hdev->hw.io_base + HCLGEVF_RST_ING, val, 1239aa5c4f17SHuazhong Tan !(val & HCLGEVF_RST_ING_BITS), 1240aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_US, 1241aa5c4f17SHuazhong Tan HCLGEVF_RESET_WAIT_TIMEOUT_US); 12426988eb2aSSalil Mehta 12436988eb2aSSalil Mehta /* hardware completion status should be available by this time */ 1244aa5c4f17SHuazhong Tan if (ret) { 1245aa5c4f17SHuazhong Tan dev_err(&hdev->pdev->dev, 12466988eb2aSSalil Mehta "could'nt get reset done status from h/w, timeout!\n"); 1247aa5c4f17SHuazhong Tan return ret; 12486988eb2aSSalil Mehta } 12496988eb2aSSalil Mehta 12506988eb2aSSalil Mehta /* we will wait a bit more to let reset of the stack to complete. This 12516988eb2aSSalil Mehta * might happen in case reset assertion was made by PF. Yes, this also 12526988eb2aSSalil Mehta * means we might end up waiting bit more even for VF reset. 12536988eb2aSSalil Mehta */ 12546988eb2aSSalil Mehta msleep(5000); 12556988eb2aSSalil Mehta 12566988eb2aSSalil Mehta return 0; 12576988eb2aSSalil Mehta } 12586988eb2aSSalil Mehta 12596988eb2aSSalil Mehta static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 12606988eb2aSSalil Mehta { 12617a01c897SSalil Mehta int ret; 12627a01c897SSalil Mehta 12636988eb2aSSalil Mehta /* uninitialize the nic client */ 12646a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 12656a5f6fa3SHuazhong Tan if (ret) 12666a5f6fa3SHuazhong Tan return ret; 12676988eb2aSSalil Mehta 12687a01c897SSalil Mehta /* re-initialize the hclge device */ 12699c6f7085SHuazhong Tan ret = hclgevf_reset_hdev(hdev); 12707a01c897SSalil Mehta if (ret) { 12717a01c897SSalil Mehta dev_err(&hdev->pdev->dev, 12727a01c897SSalil Mehta "hclge device re-init failed, VF is disabled!\n"); 12737a01c897SSalil Mehta return ret; 12747a01c897SSalil Mehta } 12756988eb2aSSalil Mehta 12766988eb2aSSalil Mehta /* bring up the nic client again */ 12776a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 12786a5f6fa3SHuazhong Tan if (ret) 12796a5f6fa3SHuazhong Tan return ret; 12806988eb2aSSalil Mehta 12811f609492SYunsheng Lin return hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT); 12826988eb2aSSalil Mehta } 12836988eb2aSSalil Mehta 1284dea846e8SHuazhong Tan static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1285dea846e8SHuazhong Tan { 1286dea846e8SHuazhong Tan int ret = 0; 1287dea846e8SHuazhong Tan 1288dea846e8SHuazhong Tan switch (hdev->reset_type) { 1289dea846e8SHuazhong Tan case HNAE3_VF_FUNC_RESET: 1290dea846e8SHuazhong Tan ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1291dea846e8SHuazhong Tan 0, true, NULL, sizeof(u8)); 1292dea846e8SHuazhong Tan break; 12936ff3cf07SHuazhong Tan case HNAE3_FLR_RESET: 12946ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 12956ff3cf07SHuazhong Tan break; 1296dea846e8SHuazhong Tan default: 1297dea846e8SHuazhong Tan break; 1298dea846e8SHuazhong Tan } 1299dea846e8SHuazhong Tan 1300ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1301ef5f8e50SHuazhong Tan 1302dea846e8SHuazhong Tan dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1303dea846e8SHuazhong Tan hdev->reset_type, ret); 1304dea846e8SHuazhong Tan 1305dea846e8SHuazhong Tan return ret; 1306dea846e8SHuazhong Tan } 1307dea846e8SHuazhong Tan 13086988eb2aSSalil Mehta static int hclgevf_reset(struct hclgevf_dev *hdev) 13096988eb2aSSalil Mehta { 1310dea846e8SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 13116988eb2aSSalil Mehta int ret; 13126988eb2aSSalil Mehta 1313dea846e8SHuazhong Tan /* Initialize ae_dev reset status as well, in case enet layer wants to 1314dea846e8SHuazhong Tan * know if device is undergoing reset 1315dea846e8SHuazhong Tan */ 1316dea846e8SHuazhong Tan ae_dev->reset_type = hdev->reset_type; 13174d60291bSHuazhong Tan hdev->reset_count++; 13186988eb2aSSalil Mehta rtnl_lock(); 13196988eb2aSSalil Mehta 13206988eb2aSSalil Mehta /* bring down the nic to stop any ongoing TX/RX */ 13216a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 13226a5f6fa3SHuazhong Tan if (ret) 13236a5f6fa3SHuazhong Tan goto err_reset_lock; 13246988eb2aSSalil Mehta 132529118ab9SHuazhong Tan rtnl_unlock(); 132629118ab9SHuazhong Tan 13276a5f6fa3SHuazhong Tan ret = hclgevf_reset_prepare_wait(hdev); 13286a5f6fa3SHuazhong Tan if (ret) 13296a5f6fa3SHuazhong Tan goto err_reset; 1330dea846e8SHuazhong Tan 13316988eb2aSSalil Mehta /* check if VF could successfully fetch the hardware reset completion 13326988eb2aSSalil Mehta * status from the hardware 13336988eb2aSSalil Mehta */ 13346988eb2aSSalil Mehta ret = hclgevf_reset_wait(hdev); 13356988eb2aSSalil Mehta if (ret) { 13366988eb2aSSalil Mehta /* can't do much in this situation, will disable VF */ 13376988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, 13386988eb2aSSalil Mehta "VF failed(=%d) to fetch H/W reset completion status\n", 13396988eb2aSSalil Mehta ret); 13406a5f6fa3SHuazhong Tan goto err_reset; 13416988eb2aSSalil Mehta } 13426988eb2aSSalil Mehta 134329118ab9SHuazhong Tan rtnl_lock(); 134429118ab9SHuazhong Tan 13456988eb2aSSalil Mehta /* now, re-initialize the nic client and ae device*/ 13466988eb2aSSalil Mehta ret = hclgevf_reset_stack(hdev); 13476a5f6fa3SHuazhong Tan if (ret) { 13486988eb2aSSalil Mehta dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 13496a5f6fa3SHuazhong Tan goto err_reset_lock; 13506a5f6fa3SHuazhong Tan } 13516988eb2aSSalil Mehta 13526988eb2aSSalil Mehta /* bring up the nic to enable TX/RX again */ 13536a5f6fa3SHuazhong Tan ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 13546a5f6fa3SHuazhong Tan if (ret) 13556a5f6fa3SHuazhong Tan goto err_reset_lock; 13566988eb2aSSalil Mehta 13576988eb2aSSalil Mehta rtnl_unlock(); 13586988eb2aSSalil Mehta 1359b644a8d4SHuazhong Tan hdev->last_reset_time = jiffies; 1360b644a8d4SHuazhong Tan ae_dev->reset_type = HNAE3_NONE_RESET; 1361b644a8d4SHuazhong Tan 13626988eb2aSSalil Mehta return ret; 13636a5f6fa3SHuazhong Tan err_reset_lock: 13646a5f6fa3SHuazhong Tan rtnl_unlock(); 13656a5f6fa3SHuazhong Tan err_reset: 13666a5f6fa3SHuazhong Tan /* When VF reset failed, only the higher level reset asserted by PF 13676a5f6fa3SHuazhong Tan * can restore it, so re-initialize the command queue to receive 13686a5f6fa3SHuazhong Tan * this higher reset event. 13696a5f6fa3SHuazhong Tan */ 13706a5f6fa3SHuazhong Tan hclgevf_cmd_init(hdev); 13716a5f6fa3SHuazhong Tan dev_err(&hdev->pdev->dev, "failed to reset VF\n"); 13726a5f6fa3SHuazhong Tan 13736a5f6fa3SHuazhong Tan return ret; 13746988eb2aSSalil Mehta } 13756988eb2aSSalil Mehta 1376720bd583SHuazhong Tan static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1377720bd583SHuazhong Tan unsigned long *addr) 1378720bd583SHuazhong Tan { 1379720bd583SHuazhong Tan enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1380720bd583SHuazhong Tan 1381dea846e8SHuazhong Tan /* return the highest priority reset level amongst all */ 1382b90fcc5bSHuazhong Tan if (test_bit(HNAE3_VF_RESET, addr)) { 1383b90fcc5bSHuazhong Tan rst_level = HNAE3_VF_RESET; 1384b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_RESET, addr); 1385b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1386b90fcc5bSHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1387b90fcc5bSHuazhong Tan } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1388dea846e8SHuazhong Tan rst_level = HNAE3_VF_FULL_RESET; 1389dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FULL_RESET, addr); 1390dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1391aa5c4f17SHuazhong Tan } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1392aa5c4f17SHuazhong Tan rst_level = HNAE3_VF_PF_FUNC_RESET; 1393aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1394aa5c4f17SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 1395dea846e8SHuazhong Tan } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1396dea846e8SHuazhong Tan rst_level = HNAE3_VF_FUNC_RESET; 1397dea846e8SHuazhong Tan clear_bit(HNAE3_VF_FUNC_RESET, addr); 13986ff3cf07SHuazhong Tan } else if (test_bit(HNAE3_FLR_RESET, addr)) { 13996ff3cf07SHuazhong Tan rst_level = HNAE3_FLR_RESET; 14006ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_RESET, addr); 1401720bd583SHuazhong Tan } 1402720bd583SHuazhong Tan 1403720bd583SHuazhong Tan return rst_level; 1404720bd583SHuazhong Tan } 1405720bd583SHuazhong Tan 14066ae4e733SShiju Jose static void hclgevf_reset_event(struct pci_dev *pdev, 14076ae4e733SShiju Jose struct hnae3_handle *handle) 14086d4c3981SSalil Mehta { 14096ff3cf07SHuazhong Tan struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 14106ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 14116d4c3981SSalil Mehta 14126d4c3981SSalil Mehta dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 14136d4c3981SSalil Mehta 14146ff3cf07SHuazhong Tan if (hdev->default_reset_request) 14150742ed7cSHuazhong Tan hdev->reset_level = 1416720bd583SHuazhong Tan hclgevf_get_reset_level(hdev, 1417720bd583SHuazhong Tan &hdev->default_reset_request); 1418720bd583SHuazhong Tan else 1419dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 14206d4c3981SSalil Mehta 1421436667d2SSalil Mehta /* reset of this VF requested */ 1422436667d2SSalil Mehta set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1423436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 14246d4c3981SSalil Mehta 14250742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 14266d4c3981SSalil Mehta } 14276d4c3981SSalil Mehta 1428720bd583SHuazhong Tan static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1429720bd583SHuazhong Tan enum hnae3_reset_type rst_type) 1430720bd583SHuazhong Tan { 1431720bd583SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 1432720bd583SHuazhong Tan 1433720bd583SHuazhong Tan set_bit(rst_type, &hdev->default_reset_request); 1434720bd583SHuazhong Tan } 1435720bd583SHuazhong Tan 14366ff3cf07SHuazhong Tan static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 14376ff3cf07SHuazhong Tan { 14386ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_MS 100 14396ff3cf07SHuazhong Tan #define HCLGEVF_FLR_WAIT_CNT 50 14406ff3cf07SHuazhong Tan struct hclgevf_dev *hdev = ae_dev->priv; 14416ff3cf07SHuazhong Tan int cnt = 0; 14426ff3cf07SHuazhong Tan 14436ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 14446ff3cf07SHuazhong Tan clear_bit(HNAE3_FLR_DONE, &hdev->flr_state); 14456ff3cf07SHuazhong Tan set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request); 14466ff3cf07SHuazhong Tan hclgevf_reset_event(hdev->pdev, NULL); 14476ff3cf07SHuazhong Tan 14486ff3cf07SHuazhong Tan while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) && 14496ff3cf07SHuazhong Tan cnt++ < HCLGEVF_FLR_WAIT_CNT) 14506ff3cf07SHuazhong Tan msleep(HCLGEVF_FLR_WAIT_MS); 14516ff3cf07SHuazhong Tan 14526ff3cf07SHuazhong Tan if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state)) 14536ff3cf07SHuazhong Tan dev_err(&hdev->pdev->dev, 14546ff3cf07SHuazhong Tan "flr wait down timeout: %d\n", cnt); 14556ff3cf07SHuazhong Tan } 14566ff3cf07SHuazhong Tan 1457e2cb1decSSalil Mehta static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1458e2cb1decSSalil Mehta { 1459e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1460e2cb1decSSalil Mehta 1461e2cb1decSSalil Mehta return hdev->fw_version; 1462e2cb1decSSalil Mehta } 1463e2cb1decSSalil Mehta 1464e2cb1decSSalil Mehta static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1465e2cb1decSSalil Mehta { 1466e2cb1decSSalil Mehta struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1467e2cb1decSSalil Mehta 1468e2cb1decSSalil Mehta vector->vector_irq = pci_irq_vector(hdev->pdev, 1469e2cb1decSSalil Mehta HCLGEVF_MISC_VECTOR_NUM); 1470e2cb1decSSalil Mehta vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1471e2cb1decSSalil Mehta /* vector status always valid for Vector 0 */ 1472e2cb1decSSalil Mehta hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1473e2cb1decSSalil Mehta hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1474e2cb1decSSalil Mehta 1475e2cb1decSSalil Mehta hdev->num_msi_left -= 1; 1476e2cb1decSSalil Mehta hdev->num_msi_used += 1; 1477e2cb1decSSalil Mehta } 1478e2cb1decSSalil Mehta 147935a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 148035a1e503SSalil Mehta { 148135a1e503SSalil Mehta if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) && 148235a1e503SSalil Mehta !test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) { 148335a1e503SSalil Mehta set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 148435a1e503SSalil Mehta schedule_work(&hdev->rst_service_task); 148535a1e503SSalil Mehta } 148635a1e503SSalil Mehta } 148735a1e503SSalil Mehta 148807a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1489e2cb1decSSalil Mehta { 149007a0556aSSalil Mehta if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) && 149107a0556aSSalil Mehta !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) { 149207a0556aSSalil Mehta set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1493e2cb1decSSalil Mehta schedule_work(&hdev->mbx_service_task); 1494e2cb1decSSalil Mehta } 149507a0556aSSalil Mehta } 1496e2cb1decSSalil Mehta 1497e2cb1decSSalil Mehta static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 1498e2cb1decSSalil Mehta { 1499e2cb1decSSalil Mehta if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 1500e2cb1decSSalil Mehta !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 1501e2cb1decSSalil Mehta schedule_work(&hdev->service_task); 1502e2cb1decSSalil Mehta } 1503e2cb1decSSalil Mehta 1504436667d2SSalil Mehta static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev) 1505436667d2SSalil Mehta { 150607a0556aSSalil Mehta /* if we have any pending mailbox event then schedule the mbx task */ 150707a0556aSSalil Mehta if (hdev->mbx_event_pending) 150807a0556aSSalil Mehta hclgevf_mbx_task_schedule(hdev); 150907a0556aSSalil Mehta 1510436667d2SSalil Mehta if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state)) 1511436667d2SSalil Mehta hclgevf_reset_task_schedule(hdev); 1512436667d2SSalil Mehta } 1513436667d2SSalil Mehta 1514e2cb1decSSalil Mehta static void hclgevf_service_timer(struct timer_list *t) 1515e2cb1decSSalil Mehta { 1516e2cb1decSSalil Mehta struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 1517e2cb1decSSalil Mehta 1518e2cb1decSSalil Mehta mod_timer(&hdev->service_timer, jiffies + 5 * HZ); 1519e2cb1decSSalil Mehta 1520e2cb1decSSalil Mehta hclgevf_task_schedule(hdev); 1521e2cb1decSSalil Mehta } 1522e2cb1decSSalil Mehta 152335a1e503SSalil Mehta static void hclgevf_reset_service_task(struct work_struct *work) 152435a1e503SSalil Mehta { 152535a1e503SSalil Mehta struct hclgevf_dev *hdev = 152635a1e503SSalil Mehta container_of(work, struct hclgevf_dev, rst_service_task); 1527a8dedb65SSalil Mehta int ret; 152835a1e503SSalil Mehta 152935a1e503SSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 153035a1e503SSalil Mehta return; 153135a1e503SSalil Mehta 153235a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 153335a1e503SSalil Mehta 1534436667d2SSalil Mehta if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1535436667d2SSalil Mehta &hdev->reset_state)) { 1536436667d2SSalil Mehta /* PF has initmated that it is about to reset the hardware. 1537436667d2SSalil Mehta * We now have to poll & check if harware has actually completed 1538436667d2SSalil Mehta * the reset sequence. On hardware reset completion, VF needs to 1539436667d2SSalil Mehta * reset the client and ae device. 154035a1e503SSalil Mehta */ 1541436667d2SSalil Mehta hdev->reset_attempts = 0; 1542436667d2SSalil Mehta 1543dea846e8SHuazhong Tan hdev->last_reset_time = jiffies; 1544dea846e8SHuazhong Tan while ((hdev->reset_type = 1545dea846e8SHuazhong Tan hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 1546dea846e8SHuazhong Tan != HNAE3_NONE_RESET) { 15476988eb2aSSalil Mehta ret = hclgevf_reset(hdev); 15486988eb2aSSalil Mehta if (ret) 1549dea846e8SHuazhong Tan dev_err(&hdev->pdev->dev, 1550dea846e8SHuazhong Tan "VF stack reset failed %d.\n", ret); 1551dea846e8SHuazhong Tan } 1552436667d2SSalil Mehta } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1553436667d2SSalil Mehta &hdev->reset_state)) { 1554436667d2SSalil Mehta /* we could be here when either of below happens: 1555436667d2SSalil Mehta * 1. reset was initiated due to watchdog timeout due to 1556436667d2SSalil Mehta * a. IMP was earlier reset and our TX got choked down and 1557436667d2SSalil Mehta * which resulted in watchdog reacting and inducing VF 1558436667d2SSalil Mehta * reset. This also means our cmdq would be unreliable. 1559436667d2SSalil Mehta * b. problem in TX due to other lower layer(example link 1560436667d2SSalil Mehta * layer not functioning properly etc.) 1561436667d2SSalil Mehta * 2. VF reset might have been initiated due to some config 1562436667d2SSalil Mehta * change. 1563436667d2SSalil Mehta * 1564436667d2SSalil Mehta * NOTE: Theres no clear way to detect above cases than to react 1565436667d2SSalil Mehta * to the response of PF for this reset request. PF will ack the 1566436667d2SSalil Mehta * 1b and 2. cases but we will not get any intimation about 1a 1567436667d2SSalil Mehta * from PF as cmdq would be in unreliable state i.e. mailbox 1568436667d2SSalil Mehta * communication between PF and VF would be broken. 1569436667d2SSalil Mehta */ 1570436667d2SSalil Mehta 1571436667d2SSalil Mehta /* if we are never geting into pending state it means either: 1572436667d2SSalil Mehta * 1. PF is not receiving our request which could be due to IMP 1573436667d2SSalil Mehta * reset 1574436667d2SSalil Mehta * 2. PF is screwed 1575436667d2SSalil Mehta * We cannot do much for 2. but to check first we can try reset 1576436667d2SSalil Mehta * our PCIe + stack and see if it alleviates the problem. 1577436667d2SSalil Mehta */ 1578436667d2SSalil Mehta if (hdev->reset_attempts > 3) { 1579436667d2SSalil Mehta /* prepare for full reset of stack + pcie interface */ 1580dea846e8SHuazhong Tan set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1581436667d2SSalil Mehta 1582436667d2SSalil Mehta /* "defer" schedule the reset task again */ 1583436667d2SSalil Mehta set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1584436667d2SSalil Mehta } else { 1585436667d2SSalil Mehta hdev->reset_attempts++; 1586436667d2SSalil Mehta 1587dea846e8SHuazhong Tan set_bit(hdev->reset_level, &hdev->reset_pending); 1588dea846e8SHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1589436667d2SSalil Mehta } 1590dea846e8SHuazhong Tan hclgevf_reset_task_schedule(hdev); 1591436667d2SSalil Mehta } 159235a1e503SSalil Mehta 159335a1e503SSalil Mehta clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 159435a1e503SSalil Mehta } 159535a1e503SSalil Mehta 1596e2cb1decSSalil Mehta static void hclgevf_mailbox_service_task(struct work_struct *work) 1597e2cb1decSSalil Mehta { 1598e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1599e2cb1decSSalil Mehta 1600e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 1601e2cb1decSSalil Mehta 1602e2cb1decSSalil Mehta if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1603e2cb1decSSalil Mehta return; 1604e2cb1decSSalil Mehta 1605e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1606e2cb1decSSalil Mehta 160707a0556aSSalil Mehta hclgevf_mbx_async_handler(hdev); 1608e2cb1decSSalil Mehta 1609e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1610e2cb1decSSalil Mehta } 1611e2cb1decSSalil Mehta 1612a6d818e3SYunsheng Lin static void hclgevf_keep_alive_timer(struct timer_list *t) 1613a6d818e3SYunsheng Lin { 1614a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = from_timer(hdev, t, keep_alive_timer); 1615a6d818e3SYunsheng Lin 1616a6d818e3SYunsheng Lin schedule_work(&hdev->keep_alive_task); 1617a6d818e3SYunsheng Lin mod_timer(&hdev->keep_alive_timer, jiffies + 2 * HZ); 1618a6d818e3SYunsheng Lin } 1619a6d818e3SYunsheng Lin 1620a6d818e3SYunsheng Lin static void hclgevf_keep_alive_task(struct work_struct *work) 1621a6d818e3SYunsheng Lin { 1622a6d818e3SYunsheng Lin struct hclgevf_dev *hdev; 1623a6d818e3SYunsheng Lin u8 respmsg; 1624a6d818e3SYunsheng Lin int ret; 1625a6d818e3SYunsheng Lin 1626a6d818e3SYunsheng Lin hdev = container_of(work, struct hclgevf_dev, keep_alive_task); 1627c59a85c0SJian Shen 1628c59a85c0SJian Shen if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1629c59a85c0SJian Shen return; 1630c59a85c0SJian Shen 1631a6d818e3SYunsheng Lin ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL, 1632a6d818e3SYunsheng Lin 0, false, &respmsg, sizeof(u8)); 1633a6d818e3SYunsheng Lin if (ret) 1634a6d818e3SYunsheng Lin dev_err(&hdev->pdev->dev, 1635a6d818e3SYunsheng Lin "VF sends keep alive cmd failed(=%d)\n", ret); 1636a6d818e3SYunsheng Lin } 1637a6d818e3SYunsheng Lin 1638e2cb1decSSalil Mehta static void hclgevf_service_task(struct work_struct *work) 1639e2cb1decSSalil Mehta { 1640e2cb1decSSalil Mehta struct hclgevf_dev *hdev; 1641e2cb1decSSalil Mehta 1642e2cb1decSSalil Mehta hdev = container_of(work, struct hclgevf_dev, service_task); 1643e2cb1decSSalil Mehta 1644e2cb1decSSalil Mehta /* request the link status from the PF. PF would be able to tell VF 1645e2cb1decSSalil Mehta * about such updates in future so we might remove this later 1646e2cb1decSSalil Mehta */ 1647e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1648e2cb1decSSalil Mehta 1649436667d2SSalil Mehta hclgevf_deferred_task_schedule(hdev); 1650436667d2SSalil Mehta 1651e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1652e2cb1decSSalil Mehta } 1653e2cb1decSSalil Mehta 1654e2cb1decSSalil Mehta static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1655e2cb1decSSalil Mehta { 1656e2cb1decSSalil Mehta hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1657e2cb1decSSalil Mehta } 1658e2cb1decSSalil Mehta 1659b90fcc5bSHuazhong Tan static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1660b90fcc5bSHuazhong Tan u32 *clearval) 1661e2cb1decSSalil Mehta { 1662b90fcc5bSHuazhong Tan u32 cmdq_src_reg, rst_ing_reg; 1663e2cb1decSSalil Mehta 1664e2cb1decSSalil Mehta /* fetch the events from their corresponding regs */ 1665e2cb1decSSalil Mehta cmdq_src_reg = hclgevf_read_dev(&hdev->hw, 1666e2cb1decSSalil Mehta HCLGEVF_VECTOR0_CMDQ_SRC_REG); 1667e2cb1decSSalil Mehta 1668b90fcc5bSHuazhong Tan if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_src_reg) { 1669b90fcc5bSHuazhong Tan rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1670b90fcc5bSHuazhong Tan dev_info(&hdev->pdev->dev, 1671b90fcc5bSHuazhong Tan "receive reset interrupt 0x%x!\n", rst_ing_reg); 1672b90fcc5bSHuazhong Tan set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1673b90fcc5bSHuazhong Tan set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1674ef5f8e50SHuazhong Tan set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1675b90fcc5bSHuazhong Tan cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RST_INT_B); 1676b90fcc5bSHuazhong Tan *clearval = cmdq_src_reg; 1677b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_RST; 1678b90fcc5bSHuazhong Tan } 1679b90fcc5bSHuazhong Tan 1680e2cb1decSSalil Mehta /* check for vector0 mailbox(=CMDQ RX) event source */ 1681e2cb1decSSalil Mehta if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 1682e2cb1decSSalil Mehta cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1683e2cb1decSSalil Mehta *clearval = cmdq_src_reg; 1684b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_MBX; 1685e2cb1decSSalil Mehta } 1686e2cb1decSSalil Mehta 1687e2cb1decSSalil Mehta dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 1688e2cb1decSSalil Mehta 1689b90fcc5bSHuazhong Tan return HCLGEVF_VECTOR0_EVENT_OTHER; 1690e2cb1decSSalil Mehta } 1691e2cb1decSSalil Mehta 1692e2cb1decSSalil Mehta static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1693e2cb1decSSalil Mehta { 1694e2cb1decSSalil Mehta writel(en ? 1 : 0, vector->addr); 1695e2cb1decSSalil Mehta } 1696e2cb1decSSalil Mehta 1697e2cb1decSSalil Mehta static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1698e2cb1decSSalil Mehta { 1699b90fcc5bSHuazhong Tan enum hclgevf_evt_cause event_cause; 1700e2cb1decSSalil Mehta struct hclgevf_dev *hdev = data; 1701e2cb1decSSalil Mehta u32 clearval; 1702e2cb1decSSalil Mehta 1703e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 1704b90fcc5bSHuazhong Tan event_cause = hclgevf_check_evt_cause(hdev, &clearval); 1705e2cb1decSSalil Mehta 1706b90fcc5bSHuazhong Tan switch (event_cause) { 1707b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_RST: 1708b90fcc5bSHuazhong Tan hclgevf_reset_task_schedule(hdev); 1709b90fcc5bSHuazhong Tan break; 1710b90fcc5bSHuazhong Tan case HCLGEVF_VECTOR0_EVENT_MBX: 171107a0556aSSalil Mehta hclgevf_mbx_handler(hdev); 1712b90fcc5bSHuazhong Tan break; 1713b90fcc5bSHuazhong Tan default: 1714b90fcc5bSHuazhong Tan break; 1715b90fcc5bSHuazhong Tan } 1716e2cb1decSSalil Mehta 1717b90fcc5bSHuazhong Tan if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 1718e2cb1decSSalil Mehta hclgevf_clear_event_cause(hdev, clearval); 1719e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 1720b90fcc5bSHuazhong Tan } 1721e2cb1decSSalil Mehta 1722e2cb1decSSalil Mehta return IRQ_HANDLED; 1723e2cb1decSSalil Mehta } 1724e2cb1decSSalil Mehta 1725e2cb1decSSalil Mehta static int hclgevf_configure(struct hclgevf_dev *hdev) 1726e2cb1decSSalil Mehta { 1727e2cb1decSSalil Mehta int ret; 1728e2cb1decSSalil Mehta 1729c136b884SPeng Li hdev->hw.mac.media_type = HNAE3_MEDIA_TYPE_NONE; 1730c136b884SPeng Li 1731e2cb1decSSalil Mehta /* get queue configuration from PF */ 17326cee6fc3SJian Shen ret = hclgevf_get_queue_info(hdev); 1733e2cb1decSSalil Mehta if (ret) 1734e2cb1decSSalil Mehta return ret; 1735e2cb1decSSalil Mehta /* get tc configuration from PF */ 1736e2cb1decSSalil Mehta return hclgevf_get_tc_info(hdev); 1737e2cb1decSSalil Mehta } 1738e2cb1decSSalil Mehta 17397a01c897SSalil Mehta static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 17407a01c897SSalil Mehta { 17417a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 17421154bb26SPeng Li struct hclgevf_dev *hdev; 17437a01c897SSalil Mehta 17447a01c897SSalil Mehta hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 17457a01c897SSalil Mehta if (!hdev) 17467a01c897SSalil Mehta return -ENOMEM; 17477a01c897SSalil Mehta 17487a01c897SSalil Mehta hdev->pdev = pdev; 17497a01c897SSalil Mehta hdev->ae_dev = ae_dev; 17507a01c897SSalil Mehta ae_dev->priv = hdev; 17517a01c897SSalil Mehta 17527a01c897SSalil Mehta return 0; 17537a01c897SSalil Mehta } 17547a01c897SSalil Mehta 1755e2cb1decSSalil Mehta static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 1756e2cb1decSSalil Mehta { 1757e2cb1decSSalil Mehta struct hnae3_handle *roce = &hdev->roce; 1758e2cb1decSSalil Mehta struct hnae3_handle *nic = &hdev->nic; 1759e2cb1decSSalil Mehta 176007acf909SJian Shen roce->rinfo.num_vectors = hdev->num_roce_msix; 1761e2cb1decSSalil Mehta 1762e2cb1decSSalil Mehta if (hdev->num_msi_left < roce->rinfo.num_vectors || 1763e2cb1decSSalil Mehta hdev->num_msi_left == 0) 1764e2cb1decSSalil Mehta return -EINVAL; 1765e2cb1decSSalil Mehta 176607acf909SJian Shen roce->rinfo.base_vector = hdev->roce_base_vector; 1767e2cb1decSSalil Mehta 1768e2cb1decSSalil Mehta roce->rinfo.netdev = nic->kinfo.netdev; 1769e2cb1decSSalil Mehta roce->rinfo.roce_io_base = hdev->hw.io_base; 1770e2cb1decSSalil Mehta 1771e2cb1decSSalil Mehta roce->pdev = nic->pdev; 1772e2cb1decSSalil Mehta roce->ae_algo = nic->ae_algo; 1773e2cb1decSSalil Mehta roce->numa_node_mask = nic->numa_node_mask; 1774e2cb1decSSalil Mehta 1775e2cb1decSSalil Mehta return 0; 1776e2cb1decSSalil Mehta } 1777e2cb1decSSalil Mehta 1778b26a6feaSPeng Li static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 1779b26a6feaSPeng Li { 1780b26a6feaSPeng Li struct hclgevf_cfg_gro_status_cmd *req; 1781b26a6feaSPeng Li struct hclgevf_desc desc; 1782b26a6feaSPeng Li int ret; 1783b26a6feaSPeng Li 1784b26a6feaSPeng Li if (!hnae3_dev_gro_supported(hdev)) 1785b26a6feaSPeng Li return 0; 1786b26a6feaSPeng Li 1787b26a6feaSPeng Li hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 1788b26a6feaSPeng Li false); 1789b26a6feaSPeng Li req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 1790b26a6feaSPeng Li 1791b26a6feaSPeng Li req->gro_en = cpu_to_le16(en ? 1 : 0); 1792b26a6feaSPeng Li 1793b26a6feaSPeng Li ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1794b26a6feaSPeng Li if (ret) 1795b26a6feaSPeng Li dev_err(&hdev->pdev->dev, 1796b26a6feaSPeng Li "VF GRO hardware config cmd failed, ret = %d.\n", ret); 1797b26a6feaSPeng Li 1798b26a6feaSPeng Li return ret; 1799b26a6feaSPeng Li } 1800b26a6feaSPeng Li 1801e2cb1decSSalil Mehta static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 1802e2cb1decSSalil Mehta { 1803e2cb1decSSalil Mehta struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1804e2cb1decSSalil Mehta int i, ret; 1805e2cb1decSSalil Mehta 1806e2cb1decSSalil Mehta rss_cfg->rss_size = hdev->rss_size_max; 1807e2cb1decSSalil Mehta 1808374ad291SJian Shen if (hdev->pdev->revision >= 0x21) { 1809472d7eceSJian Shen rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 1810472d7eceSJian Shen memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 1811374ad291SJian Shen HCLGEVF_RSS_KEY_SIZE); 1812374ad291SJian Shen 1813374ad291SJian Shen ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 1814374ad291SJian Shen rss_cfg->rss_hash_key); 1815374ad291SJian Shen if (ret) 1816374ad291SJian Shen return ret; 1817d97b3072SJian Shen 1818d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_tcp_en = 1819d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1820d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_udp_en = 1821d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1822d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_sctp_en = 1823d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1824d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv4_fragment_en = 1825d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1826d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_tcp_en = 1827d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1828d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_udp_en = 1829d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1830d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_sctp_en = 1831d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1832d97b3072SJian Shen rss_cfg->rss_tuple_sets.ipv6_fragment_en = 1833d97b3072SJian Shen HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1834d97b3072SJian Shen 1835d97b3072SJian Shen ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 1836d97b3072SJian Shen if (ret) 1837d97b3072SJian Shen return ret; 1838d97b3072SJian Shen 1839374ad291SJian Shen } 1840374ad291SJian Shen 1841e2cb1decSSalil Mehta /* Initialize RSS indirect table for each vport */ 1842e2cb1decSSalil Mehta for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 1843e2cb1decSSalil Mehta rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max; 1844e2cb1decSSalil Mehta 1845e2cb1decSSalil Mehta ret = hclgevf_set_rss_indir_table(hdev); 1846e2cb1decSSalil Mehta if (ret) 1847e2cb1decSSalil Mehta return ret; 1848e2cb1decSSalil Mehta 1849e2cb1decSSalil Mehta return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max); 1850e2cb1decSSalil Mehta } 1851e2cb1decSSalil Mehta 1852e2cb1decSSalil Mehta static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 1853e2cb1decSSalil Mehta { 1854e2cb1decSSalil Mehta /* other vlan config(like, VLAN TX/RX offload) would also be added 1855e2cb1decSSalil Mehta * here later 1856e2cb1decSSalil Mehta */ 1857e2cb1decSSalil Mehta return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 1858e2cb1decSSalil Mehta false); 1859e2cb1decSSalil Mehta } 1860e2cb1decSSalil Mehta 18618cdb992fSJian Shen static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 18628cdb992fSJian Shen { 18638cdb992fSJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 18648cdb992fSJian Shen 18658cdb992fSJian Shen if (enable) { 18668cdb992fSJian Shen mod_timer(&hdev->service_timer, jiffies + HZ); 18678cdb992fSJian Shen } else { 18688cdb992fSJian Shen del_timer_sync(&hdev->service_timer); 18698cdb992fSJian Shen cancel_work_sync(&hdev->service_task); 18708cdb992fSJian Shen clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 18718cdb992fSJian Shen } 18728cdb992fSJian Shen } 18738cdb992fSJian Shen 1874e2cb1decSSalil Mehta static int hclgevf_ae_start(struct hnae3_handle *handle) 1875e2cb1decSSalil Mehta { 1876e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1877e2cb1decSSalil Mehta 1878e2cb1decSSalil Mehta /* reset tqp stats */ 1879e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 1880e2cb1decSSalil Mehta 1881e2cb1decSSalil Mehta hclgevf_request_link_info(hdev); 1882e2cb1decSSalil Mehta 1883e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1884e2cb1decSSalil Mehta 1885e2cb1decSSalil Mehta return 0; 1886e2cb1decSSalil Mehta } 1887e2cb1decSSalil Mehta 1888e2cb1decSSalil Mehta static void hclgevf_ae_stop(struct hnae3_handle *handle) 1889e2cb1decSSalil Mehta { 1890e2cb1decSSalil Mehta struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 189139cfbc9cSHuazhong Tan int i; 1892e2cb1decSSalil Mehta 18932f7e4896SFuyun Liang set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 18942f7e4896SFuyun Liang 189539cfbc9cSHuazhong Tan for (i = 0; i < handle->kinfo.num_tqps; i++) 189639cfbc9cSHuazhong Tan hclgevf_reset_tqp(handle, i); 189739cfbc9cSHuazhong Tan 1898e2cb1decSSalil Mehta /* reset tqp stats */ 1899e2cb1decSSalil Mehta hclgevf_reset_tqp_stats(handle); 19008cc6c1f7SFuyun Liang hclgevf_update_link_status(hdev, 0); 1901e2cb1decSSalil Mehta } 1902e2cb1decSSalil Mehta 1903a6d818e3SYunsheng Lin static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 1904a6d818e3SYunsheng Lin { 1905a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1906a6d818e3SYunsheng Lin u8 msg_data; 1907a6d818e3SYunsheng Lin 1908a6d818e3SYunsheng Lin msg_data = alive ? 1 : 0; 1909a6d818e3SYunsheng Lin return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE, 1910a6d818e3SYunsheng Lin 0, &msg_data, 1, false, NULL, 0); 1911a6d818e3SYunsheng Lin } 1912a6d818e3SYunsheng Lin 1913a6d818e3SYunsheng Lin static int hclgevf_client_start(struct hnae3_handle *handle) 1914a6d818e3SYunsheng Lin { 1915a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1916a6d818e3SYunsheng Lin 1917a6d818e3SYunsheng Lin mod_timer(&hdev->keep_alive_timer, jiffies + 2 * HZ); 1918a6d818e3SYunsheng Lin return hclgevf_set_alive(handle, true); 1919a6d818e3SYunsheng Lin } 1920a6d818e3SYunsheng Lin 1921a6d818e3SYunsheng Lin static void hclgevf_client_stop(struct hnae3_handle *handle) 1922a6d818e3SYunsheng Lin { 1923a6d818e3SYunsheng Lin struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1924a6d818e3SYunsheng Lin int ret; 1925a6d818e3SYunsheng Lin 1926a6d818e3SYunsheng Lin ret = hclgevf_set_alive(handle, false); 1927a6d818e3SYunsheng Lin if (ret) 1928a6d818e3SYunsheng Lin dev_warn(&hdev->pdev->dev, 1929a6d818e3SYunsheng Lin "%s failed %d\n", __func__, ret); 1930a6d818e3SYunsheng Lin 1931a6d818e3SYunsheng Lin del_timer_sync(&hdev->keep_alive_timer); 1932a6d818e3SYunsheng Lin cancel_work_sync(&hdev->keep_alive_task); 1933a6d818e3SYunsheng Lin } 1934a6d818e3SYunsheng Lin 1935e2cb1decSSalil Mehta static void hclgevf_state_init(struct hclgevf_dev *hdev) 1936e2cb1decSSalil Mehta { 1937e2cb1decSSalil Mehta /* setup tasks for the MBX */ 1938e2cb1decSSalil Mehta INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 1939e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1940e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1941e2cb1decSSalil Mehta 1942e2cb1decSSalil Mehta /* setup tasks for service timer */ 1943e2cb1decSSalil Mehta timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 1944e2cb1decSSalil Mehta 1945e2cb1decSSalil Mehta INIT_WORK(&hdev->service_task, hclgevf_service_task); 1946e2cb1decSSalil Mehta clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1947e2cb1decSSalil Mehta 194835a1e503SSalil Mehta INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task); 194935a1e503SSalil Mehta 1950e2cb1decSSalil Mehta mutex_init(&hdev->mbx_resp.mbx_mutex); 1951e2cb1decSSalil Mehta 1952e2cb1decSSalil Mehta /* bring the device down */ 1953e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1954e2cb1decSSalil Mehta } 1955e2cb1decSSalil Mehta 1956e2cb1decSSalil Mehta static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 1957e2cb1decSSalil Mehta { 1958e2cb1decSSalil Mehta set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1959e2cb1decSSalil Mehta 1960e2cb1decSSalil Mehta if (hdev->service_timer.function) 1961e2cb1decSSalil Mehta del_timer_sync(&hdev->service_timer); 1962e2cb1decSSalil Mehta if (hdev->service_task.func) 1963e2cb1decSSalil Mehta cancel_work_sync(&hdev->service_task); 1964e2cb1decSSalil Mehta if (hdev->mbx_service_task.func) 1965e2cb1decSSalil Mehta cancel_work_sync(&hdev->mbx_service_task); 196635a1e503SSalil Mehta if (hdev->rst_service_task.func) 196735a1e503SSalil Mehta cancel_work_sync(&hdev->rst_service_task); 1968e2cb1decSSalil Mehta 1969e2cb1decSSalil Mehta mutex_destroy(&hdev->mbx_resp.mbx_mutex); 1970e2cb1decSSalil Mehta } 1971e2cb1decSSalil Mehta 1972e2cb1decSSalil Mehta static int hclgevf_init_msi(struct hclgevf_dev *hdev) 1973e2cb1decSSalil Mehta { 1974e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 1975e2cb1decSSalil Mehta int vectors; 1976e2cb1decSSalil Mehta int i; 1977e2cb1decSSalil Mehta 197807acf909SJian Shen if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) 197907acf909SJian Shen vectors = pci_alloc_irq_vectors(pdev, 198007acf909SJian Shen hdev->roce_base_msix_offset + 1, 198107acf909SJian Shen hdev->num_msi, 198207acf909SJian Shen PCI_IRQ_MSIX); 198307acf909SJian Shen else 1984e2cb1decSSalil Mehta vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 1985e2cb1decSSalil Mehta PCI_IRQ_MSI | PCI_IRQ_MSIX); 198607acf909SJian Shen 1987e2cb1decSSalil Mehta if (vectors < 0) { 1988e2cb1decSSalil Mehta dev_err(&pdev->dev, 1989e2cb1decSSalil Mehta "failed(%d) to allocate MSI/MSI-X vectors\n", 1990e2cb1decSSalil Mehta vectors); 1991e2cb1decSSalil Mehta return vectors; 1992e2cb1decSSalil Mehta } 1993e2cb1decSSalil Mehta if (vectors < hdev->num_msi) 1994e2cb1decSSalil Mehta dev_warn(&hdev->pdev->dev, 1995e2cb1decSSalil Mehta "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 1996e2cb1decSSalil Mehta hdev->num_msi, vectors); 1997e2cb1decSSalil Mehta 1998e2cb1decSSalil Mehta hdev->num_msi = vectors; 1999e2cb1decSSalil Mehta hdev->num_msi_left = vectors; 2000e2cb1decSSalil Mehta hdev->base_msi_vector = pdev->irq; 200107acf909SJian Shen hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2002e2cb1decSSalil Mehta 2003e2cb1decSSalil Mehta hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2004e2cb1decSSalil Mehta sizeof(u16), GFP_KERNEL); 2005e2cb1decSSalil Mehta if (!hdev->vector_status) { 2006e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2007e2cb1decSSalil Mehta return -ENOMEM; 2008e2cb1decSSalil Mehta } 2009e2cb1decSSalil Mehta 2010e2cb1decSSalil Mehta for (i = 0; i < hdev->num_msi; i++) 2011e2cb1decSSalil Mehta hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2012e2cb1decSSalil Mehta 2013e2cb1decSSalil Mehta hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2014e2cb1decSSalil Mehta sizeof(int), GFP_KERNEL); 2015e2cb1decSSalil Mehta if (!hdev->vector_irq) { 2016862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2017e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2018e2cb1decSSalil Mehta return -ENOMEM; 2019e2cb1decSSalil Mehta } 2020e2cb1decSSalil Mehta 2021e2cb1decSSalil Mehta return 0; 2022e2cb1decSSalil Mehta } 2023e2cb1decSSalil Mehta 2024e2cb1decSSalil Mehta static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2025e2cb1decSSalil Mehta { 2026e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2027e2cb1decSSalil Mehta 2028862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_status); 2029862d969aSHuazhong Tan devm_kfree(&pdev->dev, hdev->vector_irq); 2030e2cb1decSSalil Mehta pci_free_irq_vectors(pdev); 2031e2cb1decSSalil Mehta } 2032e2cb1decSSalil Mehta 2033e2cb1decSSalil Mehta static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2034e2cb1decSSalil Mehta { 2035e2cb1decSSalil Mehta int ret = 0; 2036e2cb1decSSalil Mehta 2037e2cb1decSSalil Mehta hclgevf_get_misc_vector(hdev); 2038e2cb1decSSalil Mehta 2039e2cb1decSSalil Mehta ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2040e2cb1decSSalil Mehta 0, "hclgevf_cmd", hdev); 2041e2cb1decSSalil Mehta if (ret) { 2042e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2043e2cb1decSSalil Mehta hdev->misc_vector.vector_irq); 2044e2cb1decSSalil Mehta return ret; 2045e2cb1decSSalil Mehta } 2046e2cb1decSSalil Mehta 20471819e409SXi Wang hclgevf_clear_event_cause(hdev, 0); 20481819e409SXi Wang 2049e2cb1decSSalil Mehta /* enable misc. vector(vector 0) */ 2050e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, true); 2051e2cb1decSSalil Mehta 2052e2cb1decSSalil Mehta return ret; 2053e2cb1decSSalil Mehta } 2054e2cb1decSSalil Mehta 2055e2cb1decSSalil Mehta static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2056e2cb1decSSalil Mehta { 2057e2cb1decSSalil Mehta /* disable misc vector(vector 0) */ 2058e2cb1decSSalil Mehta hclgevf_enable_vector(&hdev->misc_vector, false); 20591819e409SXi Wang synchronize_irq(hdev->misc_vector.vector_irq); 2060e2cb1decSSalil Mehta free_irq(hdev->misc_vector.vector_irq, hdev); 2061e2cb1decSSalil Mehta hclgevf_free_vector(hdev, 0); 2062e2cb1decSSalil Mehta } 2063e2cb1decSSalil Mehta 2064e718a93fSPeng Li static int hclgevf_init_client_instance(struct hnae3_client *client, 2065e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2066e2cb1decSSalil Mehta { 2067e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2068e2cb1decSSalil Mehta int ret; 2069e2cb1decSSalil Mehta 2070e2cb1decSSalil Mehta switch (client->type) { 2071e2cb1decSSalil Mehta case HNAE3_CLIENT_KNIC: 2072e2cb1decSSalil Mehta hdev->nic_client = client; 2073e2cb1decSSalil Mehta hdev->nic.client = client; 2074e2cb1decSSalil Mehta 2075e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->nic); 2076e2cb1decSSalil Mehta if (ret) 207749dd8054SJian Shen goto clear_nic; 2078e2cb1decSSalil Mehta 2079d9f28fc2SJian Shen hnae3_set_client_init_flag(client, ae_dev, 1); 2080d9f28fc2SJian Shen 2081e2cb1decSSalil Mehta if (hdev->roce_client && hnae3_dev_roce_supported(hdev)) { 2082e2cb1decSSalil Mehta struct hnae3_client *rc = hdev->roce_client; 2083e2cb1decSSalil Mehta 2084e2cb1decSSalil Mehta ret = hclgevf_init_roce_base_info(hdev); 2085e2cb1decSSalil Mehta if (ret) 208649dd8054SJian Shen goto clear_roce; 2087e2cb1decSSalil Mehta ret = rc->ops->init_instance(&hdev->roce); 2088e2cb1decSSalil Mehta if (ret) 208949dd8054SJian Shen goto clear_roce; 2090d9f28fc2SJian Shen 2091d9f28fc2SJian Shen hnae3_set_client_init_flag(hdev->roce_client, ae_dev, 2092d9f28fc2SJian Shen 1); 2093e2cb1decSSalil Mehta } 2094e2cb1decSSalil Mehta break; 2095e2cb1decSSalil Mehta case HNAE3_CLIENT_UNIC: 2096e2cb1decSSalil Mehta hdev->nic_client = client; 2097e2cb1decSSalil Mehta hdev->nic.client = client; 2098e2cb1decSSalil Mehta 2099e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->nic); 2100e2cb1decSSalil Mehta if (ret) 210149dd8054SJian Shen goto clear_nic; 2102d9f28fc2SJian Shen 2103d9f28fc2SJian Shen hnae3_set_client_init_flag(client, ae_dev, 1); 2104e2cb1decSSalil Mehta break; 2105e2cb1decSSalil Mehta case HNAE3_CLIENT_ROCE: 2106544a7bcdSLijun Ou if (hnae3_dev_roce_supported(hdev)) { 2107e2cb1decSSalil Mehta hdev->roce_client = client; 2108e2cb1decSSalil Mehta hdev->roce.client = client; 2109544a7bcdSLijun Ou } 2110e2cb1decSSalil Mehta 2111544a7bcdSLijun Ou if (hdev->roce_client && hdev->nic_client) { 2112e2cb1decSSalil Mehta ret = hclgevf_init_roce_base_info(hdev); 2113e2cb1decSSalil Mehta if (ret) 211449dd8054SJian Shen goto clear_roce; 2115e2cb1decSSalil Mehta 2116e2cb1decSSalil Mehta ret = client->ops->init_instance(&hdev->roce); 2117e2cb1decSSalil Mehta if (ret) 211849dd8054SJian Shen goto clear_roce; 2119e2cb1decSSalil Mehta } 2120d9f28fc2SJian Shen 2121d9f28fc2SJian Shen hnae3_set_client_init_flag(client, ae_dev, 1); 2122fa7a4bd5SJian Shen break; 2123fa7a4bd5SJian Shen default: 2124fa7a4bd5SJian Shen return -EINVAL; 2125e2cb1decSSalil Mehta } 2126e2cb1decSSalil Mehta 2127e2cb1decSSalil Mehta return 0; 212849dd8054SJian Shen 212949dd8054SJian Shen clear_nic: 213049dd8054SJian Shen hdev->nic_client = NULL; 213149dd8054SJian Shen hdev->nic.client = NULL; 213249dd8054SJian Shen return ret; 213349dd8054SJian Shen clear_roce: 213449dd8054SJian Shen hdev->roce_client = NULL; 213549dd8054SJian Shen hdev->roce.client = NULL; 213649dd8054SJian Shen return ret; 2137e2cb1decSSalil Mehta } 2138e2cb1decSSalil Mehta 2139e718a93fSPeng Li static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2140e718a93fSPeng Li struct hnae3_ae_dev *ae_dev) 2141e2cb1decSSalil Mehta { 2142e718a93fSPeng Li struct hclgevf_dev *hdev = ae_dev->priv; 2143e718a93fSPeng Li 2144e2cb1decSSalil Mehta /* un-init roce, if it exists */ 214549dd8054SJian Shen if (hdev->roce_client) { 2146e2cb1decSSalil Mehta hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 214749dd8054SJian Shen hdev->roce_client = NULL; 214849dd8054SJian Shen hdev->roce.client = NULL; 214949dd8054SJian Shen } 2150e2cb1decSSalil Mehta 2151e2cb1decSSalil Mehta /* un-init nic/unic, if this was not called by roce client */ 215249dd8054SJian Shen if (client->ops->uninit_instance && hdev->nic_client && 215349dd8054SJian Shen client->type != HNAE3_CLIENT_ROCE) { 2154e2cb1decSSalil Mehta client->ops->uninit_instance(&hdev->nic, 0); 215549dd8054SJian Shen hdev->nic_client = NULL; 215649dd8054SJian Shen hdev->nic.client = NULL; 215749dd8054SJian Shen } 2158e2cb1decSSalil Mehta } 2159e2cb1decSSalil Mehta 2160e2cb1decSSalil Mehta static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2161e2cb1decSSalil Mehta { 2162e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2163e2cb1decSSalil Mehta struct hclgevf_hw *hw; 2164e2cb1decSSalil Mehta int ret; 2165e2cb1decSSalil Mehta 2166e2cb1decSSalil Mehta ret = pci_enable_device(pdev); 2167e2cb1decSSalil Mehta if (ret) { 2168e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed to enable PCI device\n"); 21693e249d3bSFuyun Liang return ret; 2170e2cb1decSSalil Mehta } 2171e2cb1decSSalil Mehta 2172e2cb1decSSalil Mehta ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2173e2cb1decSSalil Mehta if (ret) { 2174e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2175e2cb1decSSalil Mehta goto err_disable_device; 2176e2cb1decSSalil Mehta } 2177e2cb1decSSalil Mehta 2178e2cb1decSSalil Mehta ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2179e2cb1decSSalil Mehta if (ret) { 2180e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2181e2cb1decSSalil Mehta goto err_disable_device; 2182e2cb1decSSalil Mehta } 2183e2cb1decSSalil Mehta 2184e2cb1decSSalil Mehta pci_set_master(pdev); 2185e2cb1decSSalil Mehta hw = &hdev->hw; 2186e2cb1decSSalil Mehta hw->hdev = hdev; 21872e1ea493SPeng Li hw->io_base = pci_iomap(pdev, 2, 0); 2188e2cb1decSSalil Mehta if (!hw->io_base) { 2189e2cb1decSSalil Mehta dev_err(&pdev->dev, "can't map configuration register space\n"); 2190e2cb1decSSalil Mehta ret = -ENOMEM; 2191e2cb1decSSalil Mehta goto err_clr_master; 2192e2cb1decSSalil Mehta } 2193e2cb1decSSalil Mehta 2194e2cb1decSSalil Mehta return 0; 2195e2cb1decSSalil Mehta 2196e2cb1decSSalil Mehta err_clr_master: 2197e2cb1decSSalil Mehta pci_clear_master(pdev); 2198e2cb1decSSalil Mehta pci_release_regions(pdev); 2199e2cb1decSSalil Mehta err_disable_device: 2200e2cb1decSSalil Mehta pci_disable_device(pdev); 22013e249d3bSFuyun Liang 2202e2cb1decSSalil Mehta return ret; 2203e2cb1decSSalil Mehta } 2204e2cb1decSSalil Mehta 2205e2cb1decSSalil Mehta static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2206e2cb1decSSalil Mehta { 2207e2cb1decSSalil Mehta struct pci_dev *pdev = hdev->pdev; 2208e2cb1decSSalil Mehta 2209e2cb1decSSalil Mehta pci_iounmap(pdev, hdev->hw.io_base); 2210e2cb1decSSalil Mehta pci_clear_master(pdev); 2211e2cb1decSSalil Mehta pci_release_regions(pdev); 2212e2cb1decSSalil Mehta pci_disable_device(pdev); 2213e2cb1decSSalil Mehta } 2214e2cb1decSSalil Mehta 221507acf909SJian Shen static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 221607acf909SJian Shen { 221707acf909SJian Shen struct hclgevf_query_res_cmd *req; 221807acf909SJian Shen struct hclgevf_desc desc; 221907acf909SJian Shen int ret; 222007acf909SJian Shen 222107acf909SJian Shen hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 222207acf909SJian Shen ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 222307acf909SJian Shen if (ret) { 222407acf909SJian Shen dev_err(&hdev->pdev->dev, 222507acf909SJian Shen "query vf resource failed, ret = %d.\n", ret); 222607acf909SJian Shen return ret; 222707acf909SJian Shen } 222807acf909SJian Shen 222907acf909SJian Shen req = (struct hclgevf_query_res_cmd *)desc.data; 223007acf909SJian Shen 223107acf909SJian Shen if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) { 223207acf909SJian Shen hdev->roce_base_msix_offset = 223307acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 223407acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_M, 223507acf909SJian Shen HCLGEVF_MSIX_OFT_ROCEE_S); 223607acf909SJian Shen hdev->num_roce_msix = 223707acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 223807acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 223907acf909SJian Shen 224007acf909SJian Shen /* VF should have NIC vectors and Roce vectors, NIC vectors 224107acf909SJian Shen * are queued before Roce vectors. The offset is fixed to 64. 224207acf909SJian Shen */ 224307acf909SJian Shen hdev->num_msi = hdev->num_roce_msix + 224407acf909SJian Shen hdev->roce_base_msix_offset; 224507acf909SJian Shen } else { 224607acf909SJian Shen hdev->num_msi = 224707acf909SJian Shen hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 224807acf909SJian Shen HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 224907acf909SJian Shen } 225007acf909SJian Shen 225107acf909SJian Shen return 0; 225207acf909SJian Shen } 225307acf909SJian Shen 2254862d969aSHuazhong Tan static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2255862d969aSHuazhong Tan { 2256862d969aSHuazhong Tan struct pci_dev *pdev = hdev->pdev; 2257862d969aSHuazhong Tan int ret = 0; 2258862d969aSHuazhong Tan 2259862d969aSHuazhong Tan if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2260862d969aSHuazhong Tan test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2261862d969aSHuazhong Tan hclgevf_misc_irq_uninit(hdev); 2262862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2263862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2264862d969aSHuazhong Tan } 2265862d969aSHuazhong Tan 2266862d969aSHuazhong Tan if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2267862d969aSHuazhong Tan pci_set_master(pdev); 2268862d969aSHuazhong Tan ret = hclgevf_init_msi(hdev); 2269862d969aSHuazhong Tan if (ret) { 2270862d969aSHuazhong Tan dev_err(&pdev->dev, 2271862d969aSHuazhong Tan "failed(%d) to init MSI/MSI-X\n", ret); 2272862d969aSHuazhong Tan return ret; 2273862d969aSHuazhong Tan } 2274862d969aSHuazhong Tan 2275862d969aSHuazhong Tan ret = hclgevf_misc_irq_init(hdev); 2276862d969aSHuazhong Tan if (ret) { 2277862d969aSHuazhong Tan hclgevf_uninit_msi(hdev); 2278862d969aSHuazhong Tan dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2279862d969aSHuazhong Tan ret); 2280862d969aSHuazhong Tan return ret; 2281862d969aSHuazhong Tan } 2282862d969aSHuazhong Tan 2283862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2284862d969aSHuazhong Tan } 2285862d969aSHuazhong Tan 2286862d969aSHuazhong Tan return ret; 2287862d969aSHuazhong Tan } 2288862d969aSHuazhong Tan 22899c6f7085SHuazhong Tan static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2290e2cb1decSSalil Mehta { 22917a01c897SSalil Mehta struct pci_dev *pdev = hdev->pdev; 2292e2cb1decSSalil Mehta int ret; 2293e2cb1decSSalil Mehta 2294862d969aSHuazhong Tan ret = hclgevf_pci_reset(hdev); 2295862d969aSHuazhong Tan if (ret) { 2296862d969aSHuazhong Tan dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2297862d969aSHuazhong Tan return ret; 2298862d969aSHuazhong Tan } 2299862d969aSHuazhong Tan 23009c6f7085SHuazhong Tan ret = hclgevf_cmd_init(hdev); 23019c6f7085SHuazhong Tan if (ret) { 23029c6f7085SHuazhong Tan dev_err(&pdev->dev, "cmd failed %d\n", ret); 23039c6f7085SHuazhong Tan return ret; 23047a01c897SSalil Mehta } 2305e2cb1decSSalil Mehta 23069c6f7085SHuazhong Tan ret = hclgevf_rss_init_hw(hdev); 23079c6f7085SHuazhong Tan if (ret) { 23089c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 23099c6f7085SHuazhong Tan "failed(%d) to initialize RSS\n", ret); 23109c6f7085SHuazhong Tan return ret; 23119c6f7085SHuazhong Tan } 23129c6f7085SHuazhong Tan 2313b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2314b26a6feaSPeng Li if (ret) 2315b26a6feaSPeng Li return ret; 2316b26a6feaSPeng Li 23179c6f7085SHuazhong Tan ret = hclgevf_init_vlan_config(hdev); 23189c6f7085SHuazhong Tan if (ret) { 23199c6f7085SHuazhong Tan dev_err(&hdev->pdev->dev, 23209c6f7085SHuazhong Tan "failed(%d) to initialize VLAN config\n", ret); 23219c6f7085SHuazhong Tan return ret; 23229c6f7085SHuazhong Tan } 23239c6f7085SHuazhong Tan 23249c6f7085SHuazhong Tan dev_info(&hdev->pdev->dev, "Reset done\n"); 23259c6f7085SHuazhong Tan 23269c6f7085SHuazhong Tan return 0; 23279c6f7085SHuazhong Tan } 23289c6f7085SHuazhong Tan 23299c6f7085SHuazhong Tan static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 23309c6f7085SHuazhong Tan { 23319c6f7085SHuazhong Tan struct pci_dev *pdev = hdev->pdev; 23329c6f7085SHuazhong Tan int ret; 23339c6f7085SHuazhong Tan 2334e2cb1decSSalil Mehta ret = hclgevf_pci_init(hdev); 2335e2cb1decSSalil Mehta if (ret) { 2336e2cb1decSSalil Mehta dev_err(&pdev->dev, "PCI initialization failed\n"); 2337e2cb1decSSalil Mehta return ret; 2338e2cb1decSSalil Mehta } 2339e2cb1decSSalil Mehta 23408b0195a3SHuazhong Tan ret = hclgevf_cmd_queue_init(hdev); 23418b0195a3SHuazhong Tan if (ret) { 23428b0195a3SHuazhong Tan dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret); 23438b0195a3SHuazhong Tan goto err_cmd_queue_init; 23448b0195a3SHuazhong Tan } 23458b0195a3SHuazhong Tan 2346eddf0462SYunsheng Lin ret = hclgevf_cmd_init(hdev); 2347eddf0462SYunsheng Lin if (ret) 2348eddf0462SYunsheng Lin goto err_cmd_init; 2349eddf0462SYunsheng Lin 235007acf909SJian Shen /* Get vf resource */ 235107acf909SJian Shen ret = hclgevf_query_vf_resource(hdev); 235207acf909SJian Shen if (ret) { 235307acf909SJian Shen dev_err(&hdev->pdev->dev, 235407acf909SJian Shen "Query vf status error, ret = %d.\n", ret); 23558b0195a3SHuazhong Tan goto err_cmd_init; 235607acf909SJian Shen } 235707acf909SJian Shen 235807acf909SJian Shen ret = hclgevf_init_msi(hdev); 235907acf909SJian Shen if (ret) { 236007acf909SJian Shen dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 23618b0195a3SHuazhong Tan goto err_cmd_init; 236207acf909SJian Shen } 236307acf909SJian Shen 236407acf909SJian Shen hclgevf_state_init(hdev); 2365dea846e8SHuazhong Tan hdev->reset_level = HNAE3_VF_FUNC_RESET; 236607acf909SJian Shen 2367e2cb1decSSalil Mehta ret = hclgevf_misc_irq_init(hdev); 2368e2cb1decSSalil Mehta if (ret) { 2369e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2370e2cb1decSSalil Mehta ret); 2371e2cb1decSSalil Mehta goto err_misc_irq_init; 2372e2cb1decSSalil Mehta } 2373e2cb1decSSalil Mehta 2374862d969aSHuazhong Tan set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2375862d969aSHuazhong Tan 2376e2cb1decSSalil Mehta ret = hclgevf_configure(hdev); 2377e2cb1decSSalil Mehta if (ret) { 2378e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2379e2cb1decSSalil Mehta goto err_config; 2380e2cb1decSSalil Mehta } 2381e2cb1decSSalil Mehta 2382e2cb1decSSalil Mehta ret = hclgevf_alloc_tqps(hdev); 2383e2cb1decSSalil Mehta if (ret) { 2384e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2385e2cb1decSSalil Mehta goto err_config; 2386e2cb1decSSalil Mehta } 2387e2cb1decSSalil Mehta 2388e2cb1decSSalil Mehta ret = hclgevf_set_handle_info(hdev); 2389e2cb1decSSalil Mehta if (ret) { 2390e2cb1decSSalil Mehta dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 2391e2cb1decSSalil Mehta goto err_config; 2392e2cb1decSSalil Mehta } 2393e2cb1decSSalil Mehta 2394b26a6feaSPeng Li ret = hclgevf_config_gro(hdev, true); 2395b26a6feaSPeng Li if (ret) 2396b26a6feaSPeng Li goto err_config; 2397b26a6feaSPeng Li 2398f01f5559SJian Shen /* vf is not allowed to enable unicast/multicast promisc mode. 2399f01f5559SJian Shen * For revision 0x20, default to disable broadcast promisc mode, 2400f01f5559SJian Shen * firmware makes sure broadcast packets can be accepted. 2401f01f5559SJian Shen * For revision 0x21, default to enable broadcast promisc mode. 2402f01f5559SJian Shen */ 2403f01f5559SJian Shen ret = hclgevf_set_promisc_mode(hdev, true); 2404f01f5559SJian Shen if (ret) 2405f01f5559SJian Shen goto err_config; 2406f01f5559SJian Shen 2407e2cb1decSSalil Mehta /* Initialize RSS for this VF */ 2408e2cb1decSSalil Mehta ret = hclgevf_rss_init_hw(hdev); 2409e2cb1decSSalil Mehta if (ret) { 2410e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2411e2cb1decSSalil Mehta "failed(%d) to initialize RSS\n", ret); 2412e2cb1decSSalil Mehta goto err_config; 2413e2cb1decSSalil Mehta } 2414e2cb1decSSalil Mehta 2415e2cb1decSSalil Mehta ret = hclgevf_init_vlan_config(hdev); 2416e2cb1decSSalil Mehta if (ret) { 2417e2cb1decSSalil Mehta dev_err(&hdev->pdev->dev, 2418e2cb1decSSalil Mehta "failed(%d) to initialize VLAN config\n", ret); 2419e2cb1decSSalil Mehta goto err_config; 2420e2cb1decSSalil Mehta } 2421e2cb1decSSalil Mehta 24220742ed7cSHuazhong Tan hdev->last_reset_time = jiffies; 2423e2cb1decSSalil Mehta pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME); 2424e2cb1decSSalil Mehta 2425e2cb1decSSalil Mehta return 0; 2426e2cb1decSSalil Mehta 2427e2cb1decSSalil Mehta err_config: 2428e2cb1decSSalil Mehta hclgevf_misc_irq_uninit(hdev); 2429e2cb1decSSalil Mehta err_misc_irq_init: 2430e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2431e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 243207acf909SJian Shen err_cmd_init: 24338b0195a3SHuazhong Tan hclgevf_cmd_uninit(hdev); 24348b0195a3SHuazhong Tan err_cmd_queue_init: 2435e2cb1decSSalil Mehta hclgevf_pci_uninit(hdev); 2436862d969aSHuazhong Tan clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2437e2cb1decSSalil Mehta return ret; 2438e2cb1decSSalil Mehta } 2439e2cb1decSSalil Mehta 24407a01c897SSalil Mehta static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2441e2cb1decSSalil Mehta { 2442e2cb1decSSalil Mehta hclgevf_state_uninit(hdev); 2443862d969aSHuazhong Tan 2444862d969aSHuazhong Tan if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2445eddf0462SYunsheng Lin hclgevf_misc_irq_uninit(hdev); 2446e2cb1decSSalil Mehta hclgevf_uninit_msi(hdev); 24477a01c897SSalil Mehta } 24487a01c897SSalil Mehta 2449e3338205SHuazhong Tan hclgevf_pci_uninit(hdev); 2450862d969aSHuazhong Tan hclgevf_cmd_uninit(hdev); 2451862d969aSHuazhong Tan } 2452862d969aSHuazhong Tan 24537a01c897SSalil Mehta static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 24547a01c897SSalil Mehta { 24557a01c897SSalil Mehta struct pci_dev *pdev = ae_dev->pdev; 2456a6d818e3SYunsheng Lin struct hclgevf_dev *hdev; 24577a01c897SSalil Mehta int ret; 24587a01c897SSalil Mehta 24597a01c897SSalil Mehta ret = hclgevf_alloc_hdev(ae_dev); 24607a01c897SSalil Mehta if (ret) { 24617a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device allocation failed\n"); 24627a01c897SSalil Mehta return ret; 24637a01c897SSalil Mehta } 24647a01c897SSalil Mehta 24657a01c897SSalil Mehta ret = hclgevf_init_hdev(ae_dev->priv); 2466a6d818e3SYunsheng Lin if (ret) { 24677a01c897SSalil Mehta dev_err(&pdev->dev, "hclge device initialization failed\n"); 24687a01c897SSalil Mehta return ret; 24697a01c897SSalil Mehta } 24707a01c897SSalil Mehta 2471a6d818e3SYunsheng Lin hdev = ae_dev->priv; 2472a6d818e3SYunsheng Lin timer_setup(&hdev->keep_alive_timer, hclgevf_keep_alive_timer, 0); 2473a6d818e3SYunsheng Lin INIT_WORK(&hdev->keep_alive_task, hclgevf_keep_alive_task); 2474a6d818e3SYunsheng Lin 2475a6d818e3SYunsheng Lin return 0; 2476a6d818e3SYunsheng Lin } 2477a6d818e3SYunsheng Lin 24787a01c897SSalil Mehta static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 24797a01c897SSalil Mehta { 24807a01c897SSalil Mehta struct hclgevf_dev *hdev = ae_dev->priv; 24817a01c897SSalil Mehta 24827a01c897SSalil Mehta hclgevf_uninit_hdev(hdev); 2483e2cb1decSSalil Mehta ae_dev->priv = NULL; 2484e2cb1decSSalil Mehta } 2485e2cb1decSSalil Mehta 2486849e4607SPeng Li static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2487849e4607SPeng Li { 2488849e4607SPeng Li struct hnae3_handle *nic = &hdev->nic; 2489849e4607SPeng Li struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2490849e4607SPeng Li 24918be73621SHuazhong Tan return min_t(u32, hdev->rss_size_max, 24928be73621SHuazhong Tan hdev->num_tqps / kinfo->num_tc); 2493849e4607SPeng Li } 2494849e4607SPeng Li 2495849e4607SPeng Li /** 2496849e4607SPeng Li * hclgevf_get_channels - Get the current channels enabled and max supported. 2497849e4607SPeng Li * @handle: hardware information for network interface 2498849e4607SPeng Li * @ch: ethtool channels structure 2499849e4607SPeng Li * 2500849e4607SPeng Li * We don't support separate tx and rx queues as channels. The other count 2501849e4607SPeng Li * represents how many queues are being used for control. max_combined counts 2502849e4607SPeng Li * how many queue pairs we can support. They may not be mapped 1 to 1 with 2503849e4607SPeng Li * q_vectors since we support a lot more queue pairs than q_vectors. 2504849e4607SPeng Li **/ 2505849e4607SPeng Li static void hclgevf_get_channels(struct hnae3_handle *handle, 2506849e4607SPeng Li struct ethtool_channels *ch) 2507849e4607SPeng Li { 2508849e4607SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2509849e4607SPeng Li 2510849e4607SPeng Li ch->max_combined = hclgevf_get_max_channels(hdev); 2511849e4607SPeng Li ch->other_count = 0; 2512849e4607SPeng Li ch->max_other = 0; 25138be73621SHuazhong Tan ch->combined_count = handle->kinfo.rss_size; 2514849e4607SPeng Li } 2515849e4607SPeng Li 2516cc719218SPeng Li static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 25170d43bf45SHuazhong Tan u16 *alloc_tqps, u16 *max_rss_size) 2518cc719218SPeng Li { 2519cc719218SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2520cc719218SPeng Li 25210d43bf45SHuazhong Tan *alloc_tqps = hdev->num_tqps; 2522cc719218SPeng Li *max_rss_size = hdev->rss_size_max; 2523cc719218SPeng Li } 2524cc719218SPeng Li 2525175ec96bSFuyun Liang static int hclgevf_get_status(struct hnae3_handle *handle) 2526175ec96bSFuyun Liang { 2527175ec96bSFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2528175ec96bSFuyun Liang 2529175ec96bSFuyun Liang return hdev->hw.mac.link; 2530175ec96bSFuyun Liang } 2531175ec96bSFuyun Liang 25324a152de9SFuyun Liang static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 25334a152de9SFuyun Liang u8 *auto_neg, u32 *speed, 25344a152de9SFuyun Liang u8 *duplex) 25354a152de9SFuyun Liang { 25364a152de9SFuyun Liang struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 25374a152de9SFuyun Liang 25384a152de9SFuyun Liang if (speed) 25394a152de9SFuyun Liang *speed = hdev->hw.mac.speed; 25404a152de9SFuyun Liang if (duplex) 25414a152de9SFuyun Liang *duplex = hdev->hw.mac.duplex; 25424a152de9SFuyun Liang if (auto_neg) 25434a152de9SFuyun Liang *auto_neg = AUTONEG_DISABLE; 25444a152de9SFuyun Liang } 25454a152de9SFuyun Liang 25464a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 25474a152de9SFuyun Liang u8 duplex) 25484a152de9SFuyun Liang { 25494a152de9SFuyun Liang hdev->hw.mac.speed = speed; 25504a152de9SFuyun Liang hdev->hw.mac.duplex = duplex; 25514a152de9SFuyun Liang } 25524a152de9SFuyun Liang 25531731be4cSYonglong Liu static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 25545c9f6b39SPeng Li { 25555c9f6b39SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 25565c9f6b39SPeng Li 25575c9f6b39SPeng Li return hclgevf_config_gro(hdev, enable); 25585c9f6b39SPeng Li } 25595c9f6b39SPeng Li 2560c136b884SPeng Li static void hclgevf_get_media_type(struct hnae3_handle *handle, 2561c136b884SPeng Li u8 *media_type) 2562c136b884SPeng Li { 2563c136b884SPeng Li struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2564c136b884SPeng Li if (media_type) 2565c136b884SPeng Li *media_type = hdev->hw.mac.media_type; 2566c136b884SPeng Li } 2567c136b884SPeng Li 25684d60291bSHuazhong Tan static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 25694d60291bSHuazhong Tan { 25704d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 25714d60291bSHuazhong Tan 2572aa5c4f17SHuazhong Tan return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 25734d60291bSHuazhong Tan } 25744d60291bSHuazhong Tan 25754d60291bSHuazhong Tan static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 25764d60291bSHuazhong Tan { 25774d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 25784d60291bSHuazhong Tan 25794d60291bSHuazhong Tan return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 25804d60291bSHuazhong Tan } 25814d60291bSHuazhong Tan 25824d60291bSHuazhong Tan static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 25834d60291bSHuazhong Tan { 25844d60291bSHuazhong Tan struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 25854d60291bSHuazhong Tan 25864d60291bSHuazhong Tan return hdev->reset_count; 25874d60291bSHuazhong Tan } 25884d60291bSHuazhong Tan 25891600c3e5SJian Shen #define MAX_SEPARATE_NUM 4 25901600c3e5SJian Shen #define SEPARATOR_VALUE 0xFFFFFFFF 25911600c3e5SJian Shen #define REG_NUM_PER_LINE 4 25921600c3e5SJian Shen #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 25931600c3e5SJian Shen 25941600c3e5SJian Shen static int hclgevf_get_regs_len(struct hnae3_handle *handle) 25951600c3e5SJian Shen { 25961600c3e5SJian Shen int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 25971600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 25981600c3e5SJian Shen 25991600c3e5SJian Shen cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 26001600c3e5SJian Shen common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 26011600c3e5SJian Shen ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 26021600c3e5SJian Shen tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 26031600c3e5SJian Shen 26041600c3e5SJian Shen return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 26051600c3e5SJian Shen tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 26061600c3e5SJian Shen } 26071600c3e5SJian Shen 26081600c3e5SJian Shen static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 26091600c3e5SJian Shen void *data) 26101600c3e5SJian Shen { 26111600c3e5SJian Shen struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 26121600c3e5SJian Shen int i, j, reg_um, separator_num; 26131600c3e5SJian Shen u32 *reg = data; 26141600c3e5SJian Shen 26151600c3e5SJian Shen *version = hdev->fw_version; 26161600c3e5SJian Shen 26171600c3e5SJian Shen /* fetching per-VF registers values from VF PCIe register space */ 26181600c3e5SJian Shen reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 26191600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 26201600c3e5SJian Shen for (i = 0; i < reg_um; i++) 26211600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 26221600c3e5SJian Shen for (i = 0; i < separator_num; i++) 26231600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 26241600c3e5SJian Shen 26251600c3e5SJian Shen reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 26261600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 26271600c3e5SJian Shen for (i = 0; i < reg_um; i++) 26281600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 26291600c3e5SJian Shen for (i = 0; i < separator_num; i++) 26301600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 26311600c3e5SJian Shen 26321600c3e5SJian Shen reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 26331600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 26341600c3e5SJian Shen for (j = 0; j < hdev->num_tqps; j++) { 26351600c3e5SJian Shen for (i = 0; i < reg_um; i++) 26361600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 26371600c3e5SJian Shen ring_reg_addr_list[i] + 26381600c3e5SJian Shen 0x200 * j); 26391600c3e5SJian Shen for (i = 0; i < separator_num; i++) 26401600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 26411600c3e5SJian Shen } 26421600c3e5SJian Shen 26431600c3e5SJian Shen reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 26441600c3e5SJian Shen separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 26451600c3e5SJian Shen for (j = 0; j < hdev->num_msi_used - 1; j++) { 26461600c3e5SJian Shen for (i = 0; i < reg_um; i++) 26471600c3e5SJian Shen *reg++ = hclgevf_read_dev(&hdev->hw, 26481600c3e5SJian Shen tqp_intr_reg_addr_list[i] + 26491600c3e5SJian Shen 4 * j); 26501600c3e5SJian Shen for (i = 0; i < separator_num; i++) 26511600c3e5SJian Shen *reg++ = SEPARATOR_VALUE; 26521600c3e5SJian Shen } 26531600c3e5SJian Shen } 26541600c3e5SJian Shen 2655e2cb1decSSalil Mehta static const struct hnae3_ae_ops hclgevf_ops = { 2656e2cb1decSSalil Mehta .init_ae_dev = hclgevf_init_ae_dev, 2657e2cb1decSSalil Mehta .uninit_ae_dev = hclgevf_uninit_ae_dev, 26586ff3cf07SHuazhong Tan .flr_prepare = hclgevf_flr_prepare, 26596ff3cf07SHuazhong Tan .flr_done = hclgevf_flr_done, 2660e718a93fSPeng Li .init_client_instance = hclgevf_init_client_instance, 2661e718a93fSPeng Li .uninit_client_instance = hclgevf_uninit_client_instance, 2662e2cb1decSSalil Mehta .start = hclgevf_ae_start, 2663e2cb1decSSalil Mehta .stop = hclgevf_ae_stop, 2664a6d818e3SYunsheng Lin .client_start = hclgevf_client_start, 2665a6d818e3SYunsheng Lin .client_stop = hclgevf_client_stop, 2666e2cb1decSSalil Mehta .map_ring_to_vector = hclgevf_map_ring_to_vector, 2667e2cb1decSSalil Mehta .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 2668e2cb1decSSalil Mehta .get_vector = hclgevf_get_vector, 26690d3e6631SYunsheng Lin .put_vector = hclgevf_put_vector, 2670e2cb1decSSalil Mehta .reset_queue = hclgevf_reset_tqp, 2671e2cb1decSSalil Mehta .get_mac_addr = hclgevf_get_mac_addr, 2672e2cb1decSSalil Mehta .set_mac_addr = hclgevf_set_mac_addr, 2673e2cb1decSSalil Mehta .add_uc_addr = hclgevf_add_uc_addr, 2674e2cb1decSSalil Mehta .rm_uc_addr = hclgevf_rm_uc_addr, 2675e2cb1decSSalil Mehta .add_mc_addr = hclgevf_add_mc_addr, 2676e2cb1decSSalil Mehta .rm_mc_addr = hclgevf_rm_mc_addr, 2677e2cb1decSSalil Mehta .get_stats = hclgevf_get_stats, 2678e2cb1decSSalil Mehta .update_stats = hclgevf_update_stats, 2679e2cb1decSSalil Mehta .get_strings = hclgevf_get_strings, 2680e2cb1decSSalil Mehta .get_sset_count = hclgevf_get_sset_count, 2681e2cb1decSSalil Mehta .get_rss_key_size = hclgevf_get_rss_key_size, 2682e2cb1decSSalil Mehta .get_rss_indir_size = hclgevf_get_rss_indir_size, 2683e2cb1decSSalil Mehta .get_rss = hclgevf_get_rss, 2684e2cb1decSSalil Mehta .set_rss = hclgevf_set_rss, 2685d97b3072SJian Shen .get_rss_tuple = hclgevf_get_rss_tuple, 2686d97b3072SJian Shen .set_rss_tuple = hclgevf_set_rss_tuple, 2687e2cb1decSSalil Mehta .get_tc_size = hclgevf_get_tc_size, 2688e2cb1decSSalil Mehta .get_fw_version = hclgevf_get_fw_version, 2689e2cb1decSSalil Mehta .set_vlan_filter = hclgevf_set_vlan_filter, 2690b2641e2aSYunsheng Lin .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 26916d4c3981SSalil Mehta .reset_event = hclgevf_reset_event, 2692720bd583SHuazhong Tan .set_default_reset_request = hclgevf_set_def_reset_request, 2693849e4607SPeng Li .get_channels = hclgevf_get_channels, 2694cc719218SPeng Li .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 26951600c3e5SJian Shen .get_regs_len = hclgevf_get_regs_len, 26961600c3e5SJian Shen .get_regs = hclgevf_get_regs, 2697175ec96bSFuyun Liang .get_status = hclgevf_get_status, 26984a152de9SFuyun Liang .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 2699c136b884SPeng Li .get_media_type = hclgevf_get_media_type, 27004d60291bSHuazhong Tan .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 27014d60291bSHuazhong Tan .ae_dev_resetting = hclgevf_ae_dev_resetting, 27024d60291bSHuazhong Tan .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 27035c9f6b39SPeng Li .set_gro_en = hclgevf_gro_en, 2704818f1675SYunsheng Lin .set_mtu = hclgevf_set_mtu, 27050c29d191Sliuzhongzhu .get_global_queue_id = hclgevf_get_qid_global, 27068cdb992fSJian Shen .set_timer_task = hclgevf_set_timer_task, 2707e2cb1decSSalil Mehta }; 2708e2cb1decSSalil Mehta 2709e2cb1decSSalil Mehta static struct hnae3_ae_algo ae_algovf = { 2710e2cb1decSSalil Mehta .ops = &hclgevf_ops, 2711e2cb1decSSalil Mehta .pdev_id_table = ae_algovf_pci_tbl, 2712e2cb1decSSalil Mehta }; 2713e2cb1decSSalil Mehta 2714e2cb1decSSalil Mehta static int hclgevf_init(void) 2715e2cb1decSSalil Mehta { 2716e2cb1decSSalil Mehta pr_info("%s is initializing\n", HCLGEVF_NAME); 2717e2cb1decSSalil Mehta 2718854cf33aSFuyun Liang hnae3_register_ae_algo(&ae_algovf); 2719854cf33aSFuyun Liang 2720854cf33aSFuyun Liang return 0; 2721e2cb1decSSalil Mehta } 2722e2cb1decSSalil Mehta 2723e2cb1decSSalil Mehta static void hclgevf_exit(void) 2724e2cb1decSSalil Mehta { 2725e2cb1decSSalil Mehta hnae3_unregister_ae_algo(&ae_algovf); 2726e2cb1decSSalil Mehta } 2727e2cb1decSSalil Mehta module_init(hclgevf_init); 2728e2cb1decSSalil Mehta module_exit(hclgevf_exit); 2729e2cb1decSSalil Mehta 2730e2cb1decSSalil Mehta MODULE_LICENSE("GPL"); 2731e2cb1decSSalil Mehta MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 2732e2cb1decSSalil Mehta MODULE_DESCRIPTION("HCLGEVF Driver"); 2733e2cb1decSSalil Mehta MODULE_VERSION(HCLGEVF_MOD_VERSION); 2734