1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (c) 2016-2017 Hisilicon Limited. */ 3 4 #ifndef __HCLGEVF_CMD_H 5 #define __HCLGEVF_CMD_H 6 #include <linux/io.h> 7 #include <linux/types.h> 8 #include "hnae3.h" 9 10 #define HCLGEVF_CMDQ_TX_TIMEOUT 30000 11 #define HCLGEVF_CMDQ_RX_INVLD_B 0 12 #define HCLGEVF_CMDQ_RX_OUTVLD_B 1 13 14 struct hclgevf_hw; 15 struct hclgevf_dev; 16 17 struct hclgevf_desc { 18 __le16 opcode; 19 __le16 flag; 20 __le16 retval; 21 __le16 rsv; 22 __le32 data[6]; 23 }; 24 25 struct hclgevf_desc_cb { 26 dma_addr_t dma; 27 void *va; 28 u32 length; 29 }; 30 31 struct hclgevf_cmq_ring { 32 dma_addr_t desc_dma_addr; 33 struct hclgevf_desc *desc; 34 struct hclgevf_desc_cb *desc_cb; 35 struct hclgevf_dev *dev; 36 u32 head; 37 u32 tail; 38 39 u16 buf_size; 40 u16 desc_num; 41 int next_to_use; 42 int next_to_clean; 43 u8 flag; 44 spinlock_t lock; /* Command queue lock */ 45 }; 46 47 enum hclgevf_cmd_return_status { 48 HCLGEVF_CMD_EXEC_SUCCESS = 0, 49 HCLGEVF_CMD_NO_AUTH = 1, 50 HCLGEVF_CMD_NOT_EXEC = 2, 51 HCLGEVF_CMD_QUEUE_FULL = 3, 52 }; 53 54 enum hclgevf_cmd_status { 55 HCLGEVF_STATUS_SUCCESS = 0, 56 HCLGEVF_ERR_CSQ_FULL = -1, 57 HCLGEVF_ERR_CSQ_TIMEOUT = -2, 58 HCLGEVF_ERR_CSQ_ERROR = -3 59 }; 60 61 struct hclgevf_cmq { 62 struct hclgevf_cmq_ring csq; 63 struct hclgevf_cmq_ring crq; 64 u16 tx_timeout; /* Tx timeout */ 65 enum hclgevf_cmd_status last_status; 66 }; 67 68 #define HCLGEVF_CMD_FLAG_IN_VALID_SHIFT 0 69 #define HCLGEVF_CMD_FLAG_OUT_VALID_SHIFT 1 70 #define HCLGEVF_CMD_FLAG_NEXT_SHIFT 2 71 #define HCLGEVF_CMD_FLAG_WR_OR_RD_SHIFT 3 72 #define HCLGEVF_CMD_FLAG_NO_INTR_SHIFT 4 73 #define HCLGEVF_CMD_FLAG_ERR_INTR_SHIFT 5 74 75 #define HCLGEVF_CMD_FLAG_IN BIT(HCLGEVF_CMD_FLAG_IN_VALID_SHIFT) 76 #define HCLGEVF_CMD_FLAG_OUT BIT(HCLGEVF_CMD_FLAG_OUT_VALID_SHIFT) 77 #define HCLGEVF_CMD_FLAG_NEXT BIT(HCLGEVF_CMD_FLAG_NEXT_SHIFT) 78 #define HCLGEVF_CMD_FLAG_WR BIT(HCLGEVF_CMD_FLAG_WR_OR_RD_SHIFT) 79 #define HCLGEVF_CMD_FLAG_NO_INTR BIT(HCLGEVF_CMD_FLAG_NO_INTR_SHIFT) 80 #define HCLGEVF_CMD_FLAG_ERR_INTR BIT(HCLGEVF_CMD_FLAG_ERR_INTR_SHIFT) 81 82 enum hclgevf_opcode_type { 83 /* Generic command */ 84 HCLGEVF_OPC_QUERY_FW_VER = 0x0001, 85 HCLGEVF_OPC_QUERY_VF_RSRC = 0x0024, 86 /* TQP command */ 87 HCLGEVF_OPC_QUERY_TX_STATUS = 0x0B03, 88 HCLGEVF_OPC_QUERY_RX_STATUS = 0x0B13, 89 HCLGEVF_OPC_CFG_COM_TQP_QUEUE = 0x0B20, 90 /* GRO command */ 91 HCLGEVF_OPC_GRO_GENERIC_CONFIG = 0x0C10, 92 /* RSS cmd */ 93 HCLGEVF_OPC_RSS_GENERIC_CONFIG = 0x0D01, 94 HCLGEVF_OPC_RSS_INPUT_TUPLE = 0x0D02, 95 HCLGEVF_OPC_RSS_INDIR_TABLE = 0x0D07, 96 HCLGEVF_OPC_RSS_TC_MODE = 0x0D08, 97 /* Mailbox cmd */ 98 HCLGEVF_OPC_MBX_VF_TO_PF = 0x2001, 99 }; 100 101 #define HCLGEVF_TQP_REG_OFFSET 0x80000 102 #define HCLGEVF_TQP_REG_SIZE 0x200 103 104 struct hclgevf_tqp_map { 105 __le16 tqp_id; /* Absolute tqp id for in this pf */ 106 u8 tqp_vf; /* VF id */ 107 #define HCLGEVF_TQP_MAP_TYPE_PF 0 108 #define HCLGEVF_TQP_MAP_TYPE_VF 1 109 #define HCLGEVF_TQP_MAP_TYPE_B 0 110 #define HCLGEVF_TQP_MAP_EN_B 1 111 u8 tqp_flag; /* Indicate it's pf or vf tqp */ 112 __le16 tqp_vid; /* Virtual id in this pf/vf */ 113 u8 rsv[18]; 114 }; 115 116 #define HCLGEVF_VECTOR_ELEMENTS_PER_CMD 10 117 118 enum hclgevf_int_type { 119 HCLGEVF_INT_TX = 0, 120 HCLGEVF_INT_RX, 121 HCLGEVF_INT_EVENT, 122 }; 123 124 struct hclgevf_ctrl_vector_chain { 125 u8 int_vector_id; 126 u8 int_cause_num; 127 #define HCLGEVF_INT_TYPE_S 0 128 #define HCLGEVF_INT_TYPE_M 0x3 129 #define HCLGEVF_TQP_ID_S 2 130 #define HCLGEVF_TQP_ID_M (0x3fff << HCLGEVF_TQP_ID_S) 131 __le16 tqp_type_and_id[HCLGEVF_VECTOR_ELEMENTS_PER_CMD]; 132 u8 vfid; 133 u8 resv; 134 }; 135 136 struct hclgevf_query_version_cmd { 137 __le32 firmware; 138 __le32 firmware_rsv[5]; 139 }; 140 141 #define HCLGEVF_MSIX_OFT_ROCEE_S 0 142 #define HCLGEVF_MSIX_OFT_ROCEE_M (0xffff << HCLGEVF_MSIX_OFT_ROCEE_S) 143 #define HCLGEVF_VEC_NUM_S 0 144 #define HCLGEVF_VEC_NUM_M (0xff << HCLGEVF_VEC_NUM_S) 145 struct hclgevf_query_res_cmd { 146 __le16 tqp_num; 147 __le16 reserved; 148 __le16 msixcap_localid_ba_nic; 149 __le16 msixcap_localid_ba_rocee; 150 __le16 vf_intr_vector_number; 151 __le16 rsv[7]; 152 }; 153 154 #define HCLGEVF_GRO_EN_B 0 155 struct hclgevf_cfg_gro_status_cmd { 156 __le16 gro_en; 157 u8 rsv[22]; 158 }; 159 160 #define HCLGEVF_RSS_DEFAULT_OUTPORT_B 4 161 #define HCLGEVF_RSS_HASH_KEY_OFFSET_B 4 162 #define HCLGEVF_RSS_HASH_KEY_NUM 16 163 struct hclgevf_rss_config_cmd { 164 u8 hash_config; 165 u8 rsv[7]; 166 u8 hash_key[HCLGEVF_RSS_HASH_KEY_NUM]; 167 }; 168 169 struct hclgevf_rss_input_tuple_cmd { 170 u8 ipv4_tcp_en; 171 u8 ipv4_udp_en; 172 u8 ipv4_sctp_en; 173 u8 ipv4_fragment_en; 174 u8 ipv6_tcp_en; 175 u8 ipv6_udp_en; 176 u8 ipv6_sctp_en; 177 u8 ipv6_fragment_en; 178 u8 rsv[16]; 179 }; 180 181 #define HCLGEVF_RSS_CFG_TBL_SIZE 16 182 183 struct hclgevf_rss_indirection_table_cmd { 184 u16 start_table_index; 185 u16 rss_set_bitmap; 186 u8 rsv[4]; 187 u8 rss_result[HCLGEVF_RSS_CFG_TBL_SIZE]; 188 }; 189 190 #define HCLGEVF_RSS_TC_OFFSET_S 0 191 #define HCLGEVF_RSS_TC_OFFSET_M (0x3ff << HCLGEVF_RSS_TC_OFFSET_S) 192 #define HCLGEVF_RSS_TC_SIZE_S 12 193 #define HCLGEVF_RSS_TC_SIZE_M (0x7 << HCLGEVF_RSS_TC_SIZE_S) 194 #define HCLGEVF_RSS_TC_VALID_B 15 195 #define HCLGEVF_MAX_TC_NUM 8 196 struct hclgevf_rss_tc_mode_cmd { 197 u16 rss_tc_mode[HCLGEVF_MAX_TC_NUM]; 198 u8 rsv[8]; 199 }; 200 201 #define HCLGEVF_LINK_STS_B 0 202 #define HCLGEVF_LINK_STATUS BIT(HCLGEVF_LINK_STS_B) 203 struct hclgevf_link_status_cmd { 204 u8 status; 205 u8 rsv[23]; 206 }; 207 208 #define HCLGEVF_RING_ID_MASK 0x3ff 209 #define HCLGEVF_TQP_ENABLE_B 0 210 211 struct hclgevf_cfg_com_tqp_queue_cmd { 212 __le16 tqp_id; 213 __le16 stream_id; 214 u8 enable; 215 u8 rsv[19]; 216 }; 217 218 struct hclgevf_cfg_tx_queue_pointer_cmd { 219 __le16 tqp_id; 220 __le16 tx_tail; 221 __le16 tx_head; 222 __le16 fbd_num; 223 __le16 ring_offset; 224 u8 rsv[14]; 225 }; 226 227 #define HCLGEVF_TYPE_CRQ 0 228 #define HCLGEVF_TYPE_CSQ 1 229 #define HCLGEVF_NIC_CSQ_BASEADDR_L_REG 0x27000 230 #define HCLGEVF_NIC_CSQ_BASEADDR_H_REG 0x27004 231 #define HCLGEVF_NIC_CSQ_DEPTH_REG 0x27008 232 #define HCLGEVF_NIC_CSQ_TAIL_REG 0x27010 233 #define HCLGEVF_NIC_CSQ_HEAD_REG 0x27014 234 #define HCLGEVF_NIC_CRQ_BASEADDR_L_REG 0x27018 235 #define HCLGEVF_NIC_CRQ_BASEADDR_H_REG 0x2701c 236 #define HCLGEVF_NIC_CRQ_DEPTH_REG 0x27020 237 #define HCLGEVF_NIC_CRQ_TAIL_REG 0x27024 238 #define HCLGEVF_NIC_CRQ_HEAD_REG 0x27028 239 #define HCLGEVF_NIC_CMQ_EN_B 16 240 #define HCLGEVF_NIC_CMQ_ENABLE BIT(HCLGEVF_NIC_CMQ_EN_B) 241 #define HCLGEVF_NIC_CMQ_DESC_NUM 1024 242 #define HCLGEVF_NIC_CMQ_DESC_NUM_S 3 243 #define HCLGEVF_NIC_CMDQ_INT_SRC_REG 0x27100 244 245 static inline void hclgevf_write_reg(void __iomem *base, u32 reg, u32 value) 246 { 247 writel(value, base + reg); 248 } 249 250 static inline u32 hclgevf_read_reg(u8 __iomem *base, u32 reg) 251 { 252 u8 __iomem *reg_addr = READ_ONCE(base); 253 254 return readl(reg_addr + reg); 255 } 256 257 #define hclgevf_write_dev(a, reg, value) \ 258 hclgevf_write_reg((a)->io_base, (reg), (value)) 259 #define hclgevf_read_dev(a, reg) \ 260 hclgevf_read_reg((a)->io_base, (reg)) 261 262 #define HCLGEVF_SEND_SYNC(flag) \ 263 ((flag) & HCLGEVF_CMD_FLAG_NO_INTR) 264 265 int hclgevf_cmd_init(struct hclgevf_dev *hdev); 266 void hclgevf_cmd_uninit(struct hclgevf_dev *hdev); 267 int hclgevf_cmd_queue_init(struct hclgevf_dev *hdev); 268 269 int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclgevf_desc *desc, int num); 270 void hclgevf_cmd_setup_basic_desc(struct hclgevf_desc *desc, 271 enum hclgevf_opcode_type opcode, 272 bool is_read); 273 #endif 274