1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (c) 2016-2017 Hisilicon Limited. */ 3 4 #ifndef __HCLGEVF_CMD_H 5 #define __HCLGEVF_CMD_H 6 #include <linux/io.h> 7 #include <linux/types.h> 8 #include "hnae3.h" 9 10 #define HCLGEVF_CMDQ_TX_TIMEOUT 30000 11 #define HCLGEVF_CMDQ_RX_INVLD_B 0 12 #define HCLGEVF_CMDQ_RX_OUTVLD_B 1 13 14 struct hclgevf_hw; 15 struct hclgevf_dev; 16 17 struct hclgevf_desc { 18 __le16 opcode; 19 __le16 flag; 20 __le16 retval; 21 __le16 rsv; 22 __le32 data[6]; 23 }; 24 25 struct hclgevf_desc_cb { 26 dma_addr_t dma; 27 void *va; 28 u32 length; 29 }; 30 31 struct hclgevf_cmq_ring { 32 dma_addr_t desc_dma_addr; 33 struct hclgevf_desc *desc; 34 struct hclgevf_desc_cb *desc_cb; 35 struct hclgevf_dev *dev; 36 u32 head; 37 u32 tail; 38 39 u16 buf_size; 40 u16 desc_num; 41 int next_to_use; 42 int next_to_clean; 43 u8 flag; 44 spinlock_t lock; /* Command queue lock */ 45 }; 46 47 enum hclgevf_cmd_return_status { 48 HCLGEVF_CMD_EXEC_SUCCESS = 0, 49 HCLGEVF_CMD_NO_AUTH = 1, 50 HCLGEVF_CMD_NOT_EXEC = 2, 51 HCLGEVF_CMD_QUEUE_FULL = 3, 52 }; 53 54 enum hclgevf_cmd_status { 55 HCLGEVF_STATUS_SUCCESS = 0, 56 HCLGEVF_ERR_CSQ_FULL = -1, 57 HCLGEVF_ERR_CSQ_TIMEOUT = -2, 58 HCLGEVF_ERR_CSQ_ERROR = -3 59 }; 60 61 struct hclgevf_cmq { 62 struct hclgevf_cmq_ring csq; 63 struct hclgevf_cmq_ring crq; 64 u16 tx_timeout; /* Tx timeout */ 65 enum hclgevf_cmd_status last_status; 66 }; 67 68 #define HCLGEVF_CMD_FLAG_IN_VALID_SHIFT 0 69 #define HCLGEVF_CMD_FLAG_OUT_VALID_SHIFT 1 70 #define HCLGEVF_CMD_FLAG_NEXT_SHIFT 2 71 #define HCLGEVF_CMD_FLAG_WR_OR_RD_SHIFT 3 72 #define HCLGEVF_CMD_FLAG_NO_INTR_SHIFT 4 73 #define HCLGEVF_CMD_FLAG_ERR_INTR_SHIFT 5 74 75 #define HCLGEVF_CMD_FLAG_IN BIT(HCLGEVF_CMD_FLAG_IN_VALID_SHIFT) 76 #define HCLGEVF_CMD_FLAG_OUT BIT(HCLGEVF_CMD_FLAG_OUT_VALID_SHIFT) 77 #define HCLGEVF_CMD_FLAG_NEXT BIT(HCLGEVF_CMD_FLAG_NEXT_SHIFT) 78 #define HCLGEVF_CMD_FLAG_WR BIT(HCLGEVF_CMD_FLAG_WR_OR_RD_SHIFT) 79 #define HCLGEVF_CMD_FLAG_NO_INTR BIT(HCLGEVF_CMD_FLAG_NO_INTR_SHIFT) 80 #define HCLGEVF_CMD_FLAG_ERR_INTR BIT(HCLGEVF_CMD_FLAG_ERR_INTR_SHIFT) 81 82 enum hclgevf_opcode_type { 83 /* Generic command */ 84 HCLGEVF_OPC_QUERY_FW_VER = 0x0001, 85 HCLGEVF_OPC_QUERY_VF_RSRC = 0x0024, 86 /* TQP command */ 87 HCLGEVF_OPC_QUERY_TX_STATUS = 0x0B03, 88 HCLGEVF_OPC_QUERY_RX_STATUS = 0x0B13, 89 HCLGEVF_OPC_CFG_COM_TQP_QUEUE = 0x0B20, 90 /* RSS cmd */ 91 HCLGEVF_OPC_RSS_GENERIC_CONFIG = 0x0D01, 92 HCLGEVF_OPC_RSS_INPUT_TUPLE = 0x0D02, 93 HCLGEVF_OPC_RSS_INDIR_TABLE = 0x0D07, 94 HCLGEVF_OPC_RSS_TC_MODE = 0x0D08, 95 /* Mailbox cmd */ 96 HCLGEVF_OPC_MBX_VF_TO_PF = 0x2001, 97 }; 98 99 #define HCLGEVF_TQP_REG_OFFSET 0x80000 100 #define HCLGEVF_TQP_REG_SIZE 0x200 101 102 struct hclgevf_tqp_map { 103 __le16 tqp_id; /* Absolute tqp id for in this pf */ 104 u8 tqp_vf; /* VF id */ 105 #define HCLGEVF_TQP_MAP_TYPE_PF 0 106 #define HCLGEVF_TQP_MAP_TYPE_VF 1 107 #define HCLGEVF_TQP_MAP_TYPE_B 0 108 #define HCLGEVF_TQP_MAP_EN_B 1 109 u8 tqp_flag; /* Indicate it's pf or vf tqp */ 110 __le16 tqp_vid; /* Virtual id in this pf/vf */ 111 u8 rsv[18]; 112 }; 113 114 #define HCLGEVF_VECTOR_ELEMENTS_PER_CMD 10 115 116 enum hclgevf_int_type { 117 HCLGEVF_INT_TX = 0, 118 HCLGEVF_INT_RX, 119 HCLGEVF_INT_EVENT, 120 }; 121 122 struct hclgevf_ctrl_vector_chain { 123 u8 int_vector_id; 124 u8 int_cause_num; 125 #define HCLGEVF_INT_TYPE_S 0 126 #define HCLGEVF_INT_TYPE_M 0x3 127 #define HCLGEVF_TQP_ID_S 2 128 #define HCLGEVF_TQP_ID_M (0x3fff << HCLGEVF_TQP_ID_S) 129 __le16 tqp_type_and_id[HCLGEVF_VECTOR_ELEMENTS_PER_CMD]; 130 u8 vfid; 131 u8 resv; 132 }; 133 134 struct hclgevf_query_version_cmd { 135 __le32 firmware; 136 __le32 firmware_rsv[5]; 137 }; 138 139 #define HCLGEVF_MSIX_OFT_ROCEE_S 0 140 #define HCLGEVF_MSIX_OFT_ROCEE_M (0xffff << HCLGEVF_MSIX_OFT_ROCEE_S) 141 #define HCLGEVF_VEC_NUM_S 0 142 #define HCLGEVF_VEC_NUM_M (0xff << HCLGEVF_VEC_NUM_S) 143 struct hclgevf_query_res_cmd { 144 __le16 tqp_num; 145 __le16 reserved; 146 __le16 msixcap_localid_ba_nic; 147 __le16 msixcap_localid_ba_rocee; 148 __le16 vf_intr_vector_number; 149 __le16 rsv[7]; 150 }; 151 152 #define HCLGEVF_RSS_DEFAULT_OUTPORT_B 4 153 #define HCLGEVF_RSS_HASH_KEY_OFFSET_B 4 154 #define HCLGEVF_RSS_HASH_KEY_NUM 16 155 struct hclgevf_rss_config_cmd { 156 u8 hash_config; 157 u8 rsv[7]; 158 u8 hash_key[HCLGEVF_RSS_HASH_KEY_NUM]; 159 }; 160 161 struct hclgevf_rss_input_tuple_cmd { 162 u8 ipv4_tcp_en; 163 u8 ipv4_udp_en; 164 u8 ipv4_sctp_en; 165 u8 ipv4_fragment_en; 166 u8 ipv6_tcp_en; 167 u8 ipv6_udp_en; 168 u8 ipv6_sctp_en; 169 u8 ipv6_fragment_en; 170 u8 rsv[16]; 171 }; 172 173 #define HCLGEVF_RSS_CFG_TBL_SIZE 16 174 175 struct hclgevf_rss_indirection_table_cmd { 176 u16 start_table_index; 177 u16 rss_set_bitmap; 178 u8 rsv[4]; 179 u8 rss_result[HCLGEVF_RSS_CFG_TBL_SIZE]; 180 }; 181 182 #define HCLGEVF_RSS_TC_OFFSET_S 0 183 #define HCLGEVF_RSS_TC_OFFSET_M (0x3ff << HCLGEVF_RSS_TC_OFFSET_S) 184 #define HCLGEVF_RSS_TC_SIZE_S 12 185 #define HCLGEVF_RSS_TC_SIZE_M (0x7 << HCLGEVF_RSS_TC_SIZE_S) 186 #define HCLGEVF_RSS_TC_VALID_B 15 187 #define HCLGEVF_MAX_TC_NUM 8 188 struct hclgevf_rss_tc_mode_cmd { 189 u16 rss_tc_mode[HCLGEVF_MAX_TC_NUM]; 190 u8 rsv[8]; 191 }; 192 193 #define HCLGEVF_LINK_STS_B 0 194 #define HCLGEVF_LINK_STATUS BIT(HCLGEVF_LINK_STS_B) 195 struct hclgevf_link_status_cmd { 196 u8 status; 197 u8 rsv[23]; 198 }; 199 200 #define HCLGEVF_RING_ID_MASK 0x3ff 201 #define HCLGEVF_TQP_ENABLE_B 0 202 203 struct hclgevf_cfg_com_tqp_queue_cmd { 204 __le16 tqp_id; 205 __le16 stream_id; 206 u8 enable; 207 u8 rsv[19]; 208 }; 209 210 struct hclgevf_cfg_tx_queue_pointer_cmd { 211 __le16 tqp_id; 212 __le16 tx_tail; 213 __le16 tx_head; 214 __le16 fbd_num; 215 __le16 ring_offset; 216 u8 rsv[14]; 217 }; 218 219 #define HCLGEVF_TYPE_CRQ 0 220 #define HCLGEVF_TYPE_CSQ 1 221 #define HCLGEVF_NIC_CSQ_BASEADDR_L_REG 0x27000 222 #define HCLGEVF_NIC_CSQ_BASEADDR_H_REG 0x27004 223 #define HCLGEVF_NIC_CSQ_DEPTH_REG 0x27008 224 #define HCLGEVF_NIC_CSQ_TAIL_REG 0x27010 225 #define HCLGEVF_NIC_CSQ_HEAD_REG 0x27014 226 #define HCLGEVF_NIC_CRQ_BASEADDR_L_REG 0x27018 227 #define HCLGEVF_NIC_CRQ_BASEADDR_H_REG 0x2701c 228 #define HCLGEVF_NIC_CRQ_DEPTH_REG 0x27020 229 #define HCLGEVF_NIC_CRQ_TAIL_REG 0x27024 230 #define HCLGEVF_NIC_CRQ_HEAD_REG 0x27028 231 #define HCLGEVF_NIC_CMQ_EN_B 16 232 #define HCLGEVF_NIC_CMQ_ENABLE BIT(HCLGEVF_NIC_CMQ_EN_B) 233 #define HCLGEVF_NIC_CMQ_DESC_NUM 1024 234 #define HCLGEVF_NIC_CMQ_DESC_NUM_S 3 235 #define HCLGEVF_NIC_CMDQ_INT_SRC_REG 0x27100 236 237 static inline void hclgevf_write_reg(void __iomem *base, u32 reg, u32 value) 238 { 239 writel(value, base + reg); 240 } 241 242 static inline u32 hclgevf_read_reg(u8 __iomem *base, u32 reg) 243 { 244 u8 __iomem *reg_addr = READ_ONCE(base); 245 246 return readl(reg_addr + reg); 247 } 248 249 #define hclgevf_write_dev(a, reg, value) \ 250 hclgevf_write_reg((a)->io_base, (reg), (value)) 251 #define hclgevf_read_dev(a, reg) \ 252 hclgevf_read_reg((a)->io_base, (reg)) 253 254 #define HCLGEVF_SEND_SYNC(flag) \ 255 ((flag) & HCLGEVF_CMD_FLAG_NO_INTR) 256 257 int hclgevf_cmd_init(struct hclgevf_dev *hdev); 258 void hclgevf_cmd_uninit(struct hclgevf_dev *hdev); 259 260 int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclgevf_desc *desc, int num); 261 void hclgevf_cmd_setup_basic_desc(struct hclgevf_desc *desc, 262 enum hclgevf_opcode_type opcode, 263 bool is_read); 264 #endif 265