1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_TM_H 5 #define __HCLGE_TM_H 6 7 #include <linux/types.h> 8 9 #include "hnae3.h" 10 11 struct hclge_dev; 12 struct hclge_vport; 13 enum hclge_opcode_type; 14 15 /* MAC Pause */ 16 #define HCLGE_TX_MAC_PAUSE_EN_MSK BIT(0) 17 #define HCLGE_RX_MAC_PAUSE_EN_MSK BIT(1) 18 19 #define HCLGE_TM_PORT_BASE_MODE_MSK BIT(0) 20 21 #define HCLGE_DEFAULT_PAUSE_TRANS_GAP 0x7F 22 #define HCLGE_DEFAULT_PAUSE_TRANS_TIME 0xFFFF 23 24 /* SP or DWRR */ 25 #define HCLGE_TM_TX_SCHD_DWRR_MSK BIT(0) 26 #define HCLGE_TM_TX_SCHD_SP_MSK 0xFE 27 28 #define HCLGE_ETHER_MAX_RATE 100000 29 30 #define HCLGE_TM_PF_MAX_PRI_NUM 8 31 #define HCLGE_TM_PF_MAX_QSET_NUM 8 32 33 #define HCLGE_DSCP_MAP_TC_BD_NUM 2 34 #define HCLGE_DSCP_TC_SHIFT(n) (((n) & 1) * 4) 35 36 struct hclge_pg_to_pri_link_cmd { 37 u8 pg_id; 38 u8 rsvd1[3]; 39 u8 pri_bit_map; 40 }; 41 42 struct hclge_qs_to_pri_link_cmd { 43 __le16 qs_id; 44 __le16 rsvd; 45 u8 priority; 46 #define HCLGE_TM_QS_PRI_LINK_VLD_MSK BIT(0) 47 u8 link_vld; 48 }; 49 50 struct hclge_nq_to_qs_link_cmd { 51 __le16 nq_id; 52 __le16 rsvd; 53 #define HCLGE_TM_Q_QS_LINK_VLD_MSK BIT(10) 54 #define HCLGE_TM_QS_ID_L_MSK GENMASK(9, 0) 55 #define HCLGE_TM_QS_ID_L_S 0 56 #define HCLGE_TM_QS_ID_H_MSK GENMASK(14, 10) 57 #define HCLGE_TM_QS_ID_H_S 10 58 #define HCLGE_TM_QS_ID_H_EXT_S 11 59 #define HCLGE_TM_QS_ID_H_EXT_MSK GENMASK(15, 11) 60 __le16 qset_id; 61 }; 62 63 struct hclge_tqp_tx_queue_tc_cmd { 64 __le16 queue_id; 65 __le16 rsvd; 66 u8 tc_id; 67 u8 rev[3]; 68 }; 69 70 struct hclge_pg_weight_cmd { 71 u8 pg_id; 72 u8 dwrr; 73 }; 74 75 struct hclge_priority_weight_cmd { 76 u8 pri_id; 77 u8 dwrr; 78 }; 79 80 struct hclge_pri_sch_mode_cfg_cmd { 81 u8 pri_id; 82 u8 rsvd[3]; 83 u8 sch_mode; 84 }; 85 86 struct hclge_qs_sch_mode_cfg_cmd { 87 __le16 qs_id; 88 u8 rsvd[2]; 89 u8 sch_mode; 90 }; 91 92 struct hclge_qs_weight_cmd { 93 __le16 qs_id; 94 u8 dwrr; 95 }; 96 97 struct hclge_ets_tc_weight_cmd { 98 u8 tc_weight[HNAE3_MAX_TC]; 99 u8 weight_offset; 100 u8 rsvd[15]; 101 }; 102 103 #define HCLGE_TM_SHAP_IR_B_MSK GENMASK(7, 0) 104 #define HCLGE_TM_SHAP_IR_B_LSH 0 105 #define HCLGE_TM_SHAP_IR_U_MSK GENMASK(11, 8) 106 #define HCLGE_TM_SHAP_IR_U_LSH 8 107 #define HCLGE_TM_SHAP_IR_S_MSK GENMASK(15, 12) 108 #define HCLGE_TM_SHAP_IR_S_LSH 12 109 #define HCLGE_TM_SHAP_BS_B_MSK GENMASK(20, 16) 110 #define HCLGE_TM_SHAP_BS_B_LSH 16 111 #define HCLGE_TM_SHAP_BS_S_MSK GENMASK(25, 21) 112 #define HCLGE_TM_SHAP_BS_S_LSH 21 113 114 enum hclge_shap_bucket { 115 HCLGE_TM_SHAP_C_BUCKET = 0, 116 HCLGE_TM_SHAP_P_BUCKET, 117 }; 118 119 /* set bit HCLGE_TM_RATE_VLD to 1 means use 'rate' to config shaping */ 120 #define HCLGE_TM_RATE_VLD 0 121 122 struct hclge_pri_shapping_cmd { 123 u8 pri_id; 124 u8 rsvd[3]; 125 __le32 pri_shapping_para; 126 u8 flag; 127 u8 rsvd1[3]; 128 __le32 pri_rate; 129 }; 130 131 struct hclge_pg_shapping_cmd { 132 u8 pg_id; 133 u8 rsvd[3]; 134 __le32 pg_shapping_para; 135 u8 flag; 136 u8 rsvd1[3]; 137 __le32 pg_rate; 138 }; 139 140 struct hclge_qs_shapping_cmd { 141 __le16 qs_id; 142 u8 rsvd[2]; 143 __le32 qs_shapping_para; 144 u8 flag; 145 u8 rsvd1[3]; 146 __le32 qs_rate; 147 }; 148 149 #define HCLGE_BP_GRP_NUM 32 150 #define HCLGE_BP_SUB_GRP_ID_S 0 151 #define HCLGE_BP_SUB_GRP_ID_M GENMASK(4, 0) 152 #define HCLGE_BP_GRP_ID_S 5 153 #define HCLGE_BP_GRP_ID_M GENMASK(9, 5) 154 155 #define HCLGE_BP_EXT_GRP_NUM 40 156 #define HCLGE_BP_EXT_GRP_ID_S 5 157 #define HCLGE_BP_EXT_GRP_ID_M GENMASK(10, 5) 158 159 struct hclge_bp_to_qs_map_cmd { 160 u8 tc_id; 161 u8 rsvd[2]; 162 u8 qs_group_id; 163 __le32 qs_bit_map; 164 u32 rsvd1; 165 }; 166 167 #define HCLGE_PFC_DISABLE 0 168 #define HCLGE_PFC_TX_RX_DISABLE 0 169 170 struct hclge_pfc_en_cmd { 171 u8 tx_rx_en_bitmap; 172 u8 pri_en_bitmap; 173 }; 174 175 struct hclge_cfg_pause_param_cmd { 176 u8 mac_addr[ETH_ALEN]; 177 u8 pause_trans_gap; 178 u8 rsvd; 179 __le16 pause_trans_time; 180 u8 rsvd1[6]; 181 /* extra mac address to do double check for pause frame */ 182 u8 mac_addr_extra[ETH_ALEN]; 183 u16 rsvd2; 184 }; 185 186 struct hclge_pfc_stats_cmd { 187 __le64 pkt_num[3]; 188 }; 189 190 struct hclge_port_shapping_cmd { 191 __le32 port_shapping_para; 192 u8 flag; 193 u8 rsvd[3]; 194 __le32 port_rate; 195 }; 196 197 struct hclge_shaper_ir_para { 198 u8 ir_b; /* IR_B parameter of IR shaper */ 199 u8 ir_u; /* IR_U parameter of IR shaper */ 200 u8 ir_s; /* IR_S parameter of IR shaper */ 201 }; 202 203 struct hclge_tm_nodes_cmd { 204 u8 pg_base_id; 205 u8 pri_base_id; 206 __le16 qset_base_id; 207 __le16 queue_base_id; 208 u8 pg_num; 209 u8 pri_num; 210 __le16 qset_num; 211 __le16 queue_num; 212 }; 213 214 struct hclge_tm_shaper_para { 215 u32 rate; 216 u8 ir_b; 217 u8 ir_u; 218 u8 ir_s; 219 u8 bs_b; 220 u8 bs_s; 221 u8 flag; 222 }; 223 224 #define hclge_tm_set_field(dest, string, val) \ 225 hnae3_set_field((dest), \ 226 (HCLGE_TM_SHAP_##string##_MSK), \ 227 (HCLGE_TM_SHAP_##string##_LSH), val) 228 #define hclge_tm_get_field(src, string) \ 229 hnae3_get_field((src), HCLGE_TM_SHAP_##string##_MSK, \ 230 HCLGE_TM_SHAP_##string##_LSH) 231 232 int hclge_tm_schd_init(struct hclge_dev *hdev); 233 int hclge_tm_vport_map_update(struct hclge_dev *hdev); 234 int hclge_pause_setup_hw(struct hclge_dev *hdev, bool init); 235 int hclge_tm_schd_setup_hw(struct hclge_dev *hdev); 236 void hclge_tm_prio_tc_info_update(struct hclge_dev *hdev, u8 *prio_tc); 237 void hclge_tm_schd_info_update(struct hclge_dev *hdev, u8 num_tc); 238 void hclge_tm_pfc_info_update(struct hclge_dev *hdev); 239 int hclge_tm_dwrr_cfg(struct hclge_dev *hdev); 240 int hclge_tm_init_hw(struct hclge_dev *hdev, bool init); 241 int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap, 242 u8 pfc_bitmap); 243 int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx); 244 int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr); 245 void hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats); 246 void hclge_pfc_tx_stats_get(struct hclge_dev *hdev, u64 *stats); 247 int hclge_tm_qs_shaper_cfg(struct hclge_vport *vport, int max_tx_rate); 248 int hclge_tm_port_shaper_cfg(struct hclge_dev *hdev); 249 int hclge_tm_get_qset_num(struct hclge_dev *hdev, u16 *qset_num); 250 int hclge_tm_get_pri_num(struct hclge_dev *hdev, u8 *pri_num); 251 int hclge_tm_get_qset_map_pri(struct hclge_dev *hdev, u16 qset_id, u8 *priority, 252 u8 *link_vld); 253 int hclge_tm_get_qset_sch_mode(struct hclge_dev *hdev, u16 qset_id, u8 *mode); 254 int hclge_tm_get_qset_weight(struct hclge_dev *hdev, u16 qset_id, u8 *weight); 255 int hclge_tm_get_qset_shaper(struct hclge_dev *hdev, u16 qset_id, 256 struct hclge_tm_shaper_para *para); 257 int hclge_tm_get_pri_sch_mode(struct hclge_dev *hdev, u8 pri_id, u8 *mode); 258 int hclge_tm_get_pri_weight(struct hclge_dev *hdev, u8 pri_id, u8 *weight); 259 int hclge_tm_get_pri_shaper(struct hclge_dev *hdev, u8 pri_id, 260 enum hclge_opcode_type cmd, 261 struct hclge_tm_shaper_para *para); 262 int hclge_tm_get_q_to_qs_map(struct hclge_dev *hdev, u16 q_id, u16 *qset_id); 263 int hclge_tm_get_q_to_tc(struct hclge_dev *hdev, u16 q_id, u8 *tc_id); 264 int hclge_tm_get_pg_to_pri_map(struct hclge_dev *hdev, u8 pg_id, 265 u8 *pri_bit_map); 266 int hclge_tm_get_pg_weight(struct hclge_dev *hdev, u8 pg_id, u8 *weight); 267 int hclge_tm_get_pg_sch_mode(struct hclge_dev *hdev, u8 pg_id, u8 *mode); 268 int hclge_tm_get_pg_shaper(struct hclge_dev *hdev, u8 pg_id, 269 enum hclge_opcode_type cmd, 270 struct hclge_tm_shaper_para *para); 271 int hclge_tm_get_port_shaper(struct hclge_dev *hdev, 272 struct hclge_tm_shaper_para *para); 273 int hclge_up_to_tc_map(struct hclge_dev *hdev); 274 int hclge_dscp_to_tc_map(struct hclge_dev *hdev); 275 #endif 276