1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_TM_H 5 #define __HCLGE_TM_H 6 7 #include <linux/types.h> 8 9 /* MAC Pause */ 10 #define HCLGE_TX_MAC_PAUSE_EN_MSK BIT(0) 11 #define HCLGE_RX_MAC_PAUSE_EN_MSK BIT(1) 12 13 #define HCLGE_TM_PORT_BASE_MODE_MSK BIT(0) 14 15 #define HCLGE_DEFAULT_PAUSE_TRANS_GAP 0x7F 16 #define HCLGE_DEFAULT_PAUSE_TRANS_TIME 0xFFFF 17 18 /* SP or DWRR */ 19 #define HCLGE_TM_TX_SCHD_DWRR_MSK BIT(0) 20 #define HCLGE_TM_TX_SCHD_SP_MSK (0xFE) 21 22 struct hclge_pg_to_pri_link_cmd { 23 u8 pg_id; 24 u8 rsvd1[3]; 25 u8 pri_bit_map; 26 }; 27 28 struct hclge_qs_to_pri_link_cmd { 29 __le16 qs_id; 30 __le16 rsvd; 31 u8 priority; 32 #define HCLGE_TM_QS_PRI_LINK_VLD_MSK BIT(0) 33 u8 link_vld; 34 }; 35 36 struct hclge_nq_to_qs_link_cmd { 37 __le16 nq_id; 38 __le16 rsvd; 39 #define HCLGE_TM_Q_QS_LINK_VLD_MSK BIT(10) 40 __le16 qset_id; 41 }; 42 43 struct hclge_tqp_tx_queue_tc_cmd { 44 __le16 queue_id; 45 __le16 rsvd; 46 u8 tc_id; 47 u8 rev[3]; 48 }; 49 50 struct hclge_pg_weight_cmd { 51 u8 pg_id; 52 u8 dwrr; 53 }; 54 55 struct hclge_priority_weight_cmd { 56 u8 pri_id; 57 u8 dwrr; 58 }; 59 60 struct hclge_qs_weight_cmd { 61 __le16 qs_id; 62 u8 dwrr; 63 }; 64 65 struct hclge_ets_tc_weight_cmd { 66 u8 tc_weight[HNAE3_MAX_TC]; 67 u8 weight_offset; 68 u8 rsvd[15]; 69 }; 70 71 #define HCLGE_TM_SHAP_IR_B_MSK GENMASK(7, 0) 72 #define HCLGE_TM_SHAP_IR_B_LSH 0 73 #define HCLGE_TM_SHAP_IR_U_MSK GENMASK(11, 8) 74 #define HCLGE_TM_SHAP_IR_U_LSH 8 75 #define HCLGE_TM_SHAP_IR_S_MSK GENMASK(15, 12) 76 #define HCLGE_TM_SHAP_IR_S_LSH 12 77 #define HCLGE_TM_SHAP_BS_B_MSK GENMASK(20, 16) 78 #define HCLGE_TM_SHAP_BS_B_LSH 16 79 #define HCLGE_TM_SHAP_BS_S_MSK GENMASK(25, 21) 80 #define HCLGE_TM_SHAP_BS_S_LSH 21 81 82 enum hclge_shap_bucket { 83 HCLGE_TM_SHAP_C_BUCKET = 0, 84 HCLGE_TM_SHAP_P_BUCKET, 85 }; 86 87 struct hclge_pri_shapping_cmd { 88 u8 pri_id; 89 u8 rsvd[3]; 90 __le32 pri_shapping_para; 91 }; 92 93 struct hclge_pg_shapping_cmd { 94 u8 pg_id; 95 u8 rsvd[3]; 96 __le32 pg_shapping_para; 97 }; 98 99 struct hclge_qs_shapping_cmd { 100 __le16 qs_id; 101 u8 rsvd[2]; 102 __le32 qs_shapping_para; 103 }; 104 105 #define HCLGE_BP_GRP_NUM 32 106 #define HCLGE_BP_SUB_GRP_ID_S 0 107 #define HCLGE_BP_SUB_GRP_ID_M GENMASK(4, 0) 108 #define HCLGE_BP_GRP_ID_S 5 109 #define HCLGE_BP_GRP_ID_M GENMASK(9, 5) 110 struct hclge_bp_to_qs_map_cmd { 111 u8 tc_id; 112 u8 rsvd[2]; 113 u8 qs_group_id; 114 __le32 qs_bit_map; 115 u32 rsvd1; 116 }; 117 118 struct hclge_pfc_en_cmd { 119 u8 tx_rx_en_bitmap; 120 u8 pri_en_bitmap; 121 }; 122 123 struct hclge_cfg_pause_param_cmd { 124 u8 mac_addr[ETH_ALEN]; 125 u8 pause_trans_gap; 126 u8 rsvd; 127 __le16 pause_trans_time; 128 u8 rsvd1[6]; 129 /* extra mac address to do double check for pause frame */ 130 u8 mac_addr_extra[ETH_ALEN]; 131 u16 rsvd2; 132 }; 133 134 struct hclge_pfc_stats_cmd { 135 __le64 pkt_num[3]; 136 }; 137 138 struct hclge_port_shapping_cmd { 139 __le32 port_shapping_para; 140 }; 141 142 #define hclge_tm_set_field(dest, string, val) \ 143 hnae3_set_field((dest), \ 144 (HCLGE_TM_SHAP_##string##_MSK), \ 145 (HCLGE_TM_SHAP_##string##_LSH), val) 146 #define hclge_tm_get_field(src, string) \ 147 hnae3_get_field((src), (HCLGE_TM_SHAP_##string##_MSK), \ 148 (HCLGE_TM_SHAP_##string##_LSH)) 149 150 int hclge_tm_schd_init(struct hclge_dev *hdev); 151 int hclge_tm_vport_map_update(struct hclge_dev *hdev); 152 int hclge_pause_setup_hw(struct hclge_dev *hdev, bool init); 153 int hclge_tm_schd_setup_hw(struct hclge_dev *hdev); 154 void hclge_tm_prio_tc_info_update(struct hclge_dev *hdev, u8 *prio_tc); 155 void hclge_tm_schd_info_update(struct hclge_dev *hdev, u8 num_tc); 156 void hclge_tm_pfc_info_update(struct hclge_dev *hdev); 157 int hclge_tm_dwrr_cfg(struct hclge_dev *hdev); 158 int hclge_tm_init_hw(struct hclge_dev *hdev, bool init); 159 int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx); 160 int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr); 161 int hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats); 162 int hclge_pfc_tx_stats_get(struct hclge_dev *hdev, u64 *stats); 163 int hclge_tm_qs_shaper_cfg(struct hclge_vport *vport, int max_tx_rate); 164 165 #endif 166