1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3 
4 #ifndef __HCLGE_TM_H
5 #define __HCLGE_TM_H
6 
7 #include <linux/types.h>
8 
9 /* MAC Pause */
10 #define HCLGE_TX_MAC_PAUSE_EN_MSK	BIT(0)
11 #define HCLGE_RX_MAC_PAUSE_EN_MSK	BIT(1)
12 
13 #define HCLGE_TM_PORT_BASE_MODE_MSK	BIT(0)
14 
15 #define HCLGE_DEFAULT_PAUSE_TRANS_GAP	0xFF
16 #define HCLGE_DEFAULT_PAUSE_TRANS_TIME	0xFFFF
17 
18 /* SP or DWRR */
19 #define HCLGE_TM_TX_SCHD_DWRR_MSK	BIT(0)
20 #define HCLGE_TM_TX_SCHD_SP_MSK		(0xFE)
21 
22 struct hclge_pg_to_pri_link_cmd {
23 	u8 pg_id;
24 	u8 rsvd1[3];
25 	u8 pri_bit_map;
26 };
27 
28 struct hclge_qs_to_pri_link_cmd {
29 	__le16 qs_id;
30 	__le16 rsvd;
31 	u8 priority;
32 #define HCLGE_TM_QS_PRI_LINK_VLD_MSK	BIT(0)
33 	u8 link_vld;
34 };
35 
36 struct hclge_nq_to_qs_link_cmd {
37 	__le16 nq_id;
38 	__le16 rsvd;
39 #define HCLGE_TM_Q_QS_LINK_VLD_MSK	BIT(10)
40 	__le16 qset_id;
41 };
42 
43 struct hclge_pg_weight_cmd {
44 	u8 pg_id;
45 	u8 dwrr;
46 };
47 
48 struct hclge_priority_weight_cmd {
49 	u8 pri_id;
50 	u8 dwrr;
51 };
52 
53 struct hclge_qs_weight_cmd {
54 	__le16 qs_id;
55 	u8 dwrr;
56 };
57 
58 #define HCLGE_TM_SHAP_IR_B_MSK  GENMASK(7, 0)
59 #define HCLGE_TM_SHAP_IR_B_LSH	0
60 #define HCLGE_TM_SHAP_IR_U_MSK  GENMASK(11, 8)
61 #define HCLGE_TM_SHAP_IR_U_LSH	8
62 #define HCLGE_TM_SHAP_IR_S_MSK  GENMASK(15, 12)
63 #define HCLGE_TM_SHAP_IR_S_LSH	12
64 #define HCLGE_TM_SHAP_BS_B_MSK  GENMASK(20, 16)
65 #define HCLGE_TM_SHAP_BS_B_LSH	16
66 #define HCLGE_TM_SHAP_BS_S_MSK  GENMASK(25, 21)
67 #define HCLGE_TM_SHAP_BS_S_LSH	21
68 
69 enum hclge_shap_bucket {
70 	HCLGE_TM_SHAP_C_BUCKET = 0,
71 	HCLGE_TM_SHAP_P_BUCKET,
72 };
73 
74 struct hclge_pri_shapping_cmd {
75 	u8 pri_id;
76 	u8 rsvd[3];
77 	__le32 pri_shapping_para;
78 };
79 
80 struct hclge_pg_shapping_cmd {
81 	u8 pg_id;
82 	u8 rsvd[3];
83 	__le32 pg_shapping_para;
84 };
85 
86 #define HCLGE_BP_GRP_NUM		32
87 #define HCLGE_BP_SUB_GRP_ID_S		0
88 #define HCLGE_BP_SUB_GRP_ID_M		GENMASK(4, 0)
89 #define HCLGE_BP_GRP_ID_S		5
90 #define HCLGE_BP_GRP_ID_M		GENMASK(9, 5)
91 struct hclge_bp_to_qs_map_cmd {
92 	u8 tc_id;
93 	u8 rsvd[2];
94 	u8 qs_group_id;
95 	__le32 qs_bit_map;
96 	u32 rsvd1;
97 };
98 
99 struct hclge_pfc_en_cmd {
100 	u8 tx_rx_en_bitmap;
101 	u8 pri_en_bitmap;
102 };
103 
104 struct hclge_cfg_pause_param_cmd {
105 	u8 mac_addr[ETH_ALEN];
106 	u8 pause_trans_gap;
107 	u8 rsvd;
108 	__le16 pause_trans_time;
109 };
110 
111 struct hclge_pfc_stats_cmd {
112 	__le64 pkt_num[3];
113 };
114 
115 struct hclge_port_shapping_cmd {
116 	__le32 port_shapping_para;
117 };
118 
119 #define hclge_tm_set_field(dest, string, val) \
120 			   hnae3_set_field((dest), \
121 			   (HCLGE_TM_SHAP_##string##_MSK), \
122 			   (HCLGE_TM_SHAP_##string##_LSH), val)
123 #define hclge_tm_get_field(src, string) \
124 			hnae3_get_field((src), (HCLGE_TM_SHAP_##string##_MSK), \
125 				       (HCLGE_TM_SHAP_##string##_LSH))
126 
127 int hclge_tm_schd_init(struct hclge_dev *hdev);
128 int hclge_pause_setup_hw(struct hclge_dev *hdev);
129 int hclge_tm_schd_mode_hw(struct hclge_dev *hdev);
130 int hclge_tm_prio_tc_info_update(struct hclge_dev *hdev, u8 *prio_tc);
131 void hclge_tm_schd_info_update(struct hclge_dev *hdev, u8 num_tc);
132 int hclge_tm_dwrr_cfg(struct hclge_dev *hdev);
133 int hclge_tm_map_cfg(struct hclge_dev *hdev);
134 int hclge_tm_init_hw(struct hclge_dev *hdev);
135 int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx);
136 int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr);
137 int hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats);
138 int hclge_pfc_tx_stats_get(struct hclge_dev *hdev, u64 *stats);
139 #endif
140