1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3 
4 #include <linux/etherdevice.h>
5 
6 #include "hclge_cmd.h"
7 #include "hclge_main.h"
8 #include "hclge_tm.h"
9 
10 enum hclge_shaper_level {
11 	HCLGE_SHAPER_LVL_PRI	= 0,
12 	HCLGE_SHAPER_LVL_PG	= 1,
13 	HCLGE_SHAPER_LVL_PORT	= 2,
14 	HCLGE_SHAPER_LVL_QSET	= 3,
15 	HCLGE_SHAPER_LVL_CNT	= 4,
16 	HCLGE_SHAPER_LVL_VF	= 0,
17 	HCLGE_SHAPER_LVL_PF	= 1,
18 };
19 
20 #define HCLGE_TM_PFC_PKT_GET_CMD_NUM	3
21 #define HCLGE_TM_PFC_NUM_GET_PER_CMD	3
22 
23 #define HCLGE_SHAPER_BS_U_DEF	5
24 #define HCLGE_SHAPER_BS_S_DEF	20
25 
26 /* hclge_shaper_para_calc: calculate ir parameter for the shaper
27  * @ir: Rate to be config, its unit is Mbps
28  * @shaper_level: the shaper level. eg: port, pg, priority, queueset
29  * @ir_para: parameters of IR shaper
30  * @max_tm_rate: max tm rate is available to config
31  *
32  * the formula:
33  *
34  *		IR_b * (2 ^ IR_u) * 8
35  * IR(Mbps) = -------------------------  *  CLOCK(1000Mbps)
36  *		Tick * (2 ^ IR_s)
37  *
38  * @return: 0: calculate sucessful, negative: fail
39  */
40 static int hclge_shaper_para_calc(u32 ir, u8 shaper_level,
41 				  struct hclge_shaper_ir_para *ir_para,
42 				  u32 max_tm_rate)
43 {
44 #define DEFAULT_SHAPER_IR_B	126
45 #define DIVISOR_CLK		(1000 * 8)
46 #define DEFAULT_DIVISOR_IR_B	(DEFAULT_SHAPER_IR_B * DIVISOR_CLK)
47 
48 	static const u16 tick_array[HCLGE_SHAPER_LVL_CNT] = {
49 		6 * 256,        /* Prioriy level */
50 		6 * 32,         /* Prioriy group level */
51 		6 * 8,          /* Port level */
52 		6 * 256         /* Qset level */
53 	};
54 	u8 ir_u_calc = 0;
55 	u8 ir_s_calc = 0;
56 	u32 ir_calc;
57 	u32 tick;
58 
59 	/* Calc tick */
60 	if (shaper_level >= HCLGE_SHAPER_LVL_CNT ||
61 	    ir > max_tm_rate)
62 		return -EINVAL;
63 
64 	tick = tick_array[shaper_level];
65 
66 	/**
67 	 * Calc the speed if ir_b = 126, ir_u = 0 and ir_s = 0
68 	 * the formula is changed to:
69 	 *		126 * 1 * 8
70 	 * ir_calc = ---------------- * 1000
71 	 *		tick * 1
72 	 */
73 	ir_calc = (DEFAULT_DIVISOR_IR_B + (tick >> 1) - 1) / tick;
74 
75 	if (ir_calc == ir) {
76 		ir_para->ir_b = DEFAULT_SHAPER_IR_B;
77 		ir_para->ir_u = 0;
78 		ir_para->ir_s = 0;
79 
80 		return 0;
81 	} else if (ir_calc > ir) {
82 		/* Increasing the denominator to select ir_s value */
83 		while (ir_calc >= ir && ir) {
84 			ir_s_calc++;
85 			ir_calc = DEFAULT_DIVISOR_IR_B /
86 				  (tick * (1 << ir_s_calc));
87 		}
88 
89 		ir_para->ir_b = (ir * tick * (1 << ir_s_calc) +
90 				(DIVISOR_CLK >> 1)) / DIVISOR_CLK;
91 	} else {
92 		/* Increasing the numerator to select ir_u value */
93 		u32 numerator;
94 
95 		while (ir_calc < ir) {
96 			ir_u_calc++;
97 			numerator = DEFAULT_DIVISOR_IR_B * (1 << ir_u_calc);
98 			ir_calc = (numerator + (tick >> 1)) / tick;
99 		}
100 
101 		if (ir_calc == ir) {
102 			ir_para->ir_b = DEFAULT_SHAPER_IR_B;
103 		} else {
104 			u32 denominator = DIVISOR_CLK * (1 << --ir_u_calc);
105 			ir_para->ir_b = (ir * tick + (denominator >> 1)) /
106 					denominator;
107 		}
108 	}
109 
110 	ir_para->ir_u = ir_u_calc;
111 	ir_para->ir_s = ir_s_calc;
112 
113 	return 0;
114 }
115 
116 static int hclge_pfc_stats_get(struct hclge_dev *hdev,
117 			       enum hclge_opcode_type opcode, u64 *stats)
118 {
119 	struct hclge_desc desc[HCLGE_TM_PFC_PKT_GET_CMD_NUM];
120 	int ret, i, j;
121 
122 	if (!(opcode == HCLGE_OPC_QUERY_PFC_RX_PKT_CNT ||
123 	      opcode == HCLGE_OPC_QUERY_PFC_TX_PKT_CNT))
124 		return -EINVAL;
125 
126 	for (i = 0; i < HCLGE_TM_PFC_PKT_GET_CMD_NUM - 1; i++) {
127 		hclge_cmd_setup_basic_desc(&desc[i], opcode, true);
128 		desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
129 	}
130 
131 	hclge_cmd_setup_basic_desc(&desc[i], opcode, true);
132 
133 	ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_TM_PFC_PKT_GET_CMD_NUM);
134 	if (ret)
135 		return ret;
136 
137 	for (i = 0; i < HCLGE_TM_PFC_PKT_GET_CMD_NUM; i++) {
138 		struct hclge_pfc_stats_cmd *pfc_stats =
139 				(struct hclge_pfc_stats_cmd *)desc[i].data;
140 
141 		for (j = 0; j < HCLGE_TM_PFC_NUM_GET_PER_CMD; j++) {
142 			u32 index = i * HCLGE_TM_PFC_PKT_GET_CMD_NUM + j;
143 
144 			if (index < HCLGE_MAX_TC_NUM)
145 				stats[index] =
146 					le64_to_cpu(pfc_stats->pkt_num[j]);
147 		}
148 	}
149 	return 0;
150 }
151 
152 int hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats)
153 {
154 	return hclge_pfc_stats_get(hdev, HCLGE_OPC_QUERY_PFC_RX_PKT_CNT, stats);
155 }
156 
157 int hclge_pfc_tx_stats_get(struct hclge_dev *hdev, u64 *stats)
158 {
159 	return hclge_pfc_stats_get(hdev, HCLGE_OPC_QUERY_PFC_TX_PKT_CNT, stats);
160 }
161 
162 int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx)
163 {
164 	struct hclge_desc desc;
165 
166 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PAUSE_EN, false);
167 
168 	desc.data[0] = cpu_to_le32((tx ? HCLGE_TX_MAC_PAUSE_EN_MSK : 0) |
169 		(rx ? HCLGE_RX_MAC_PAUSE_EN_MSK : 0));
170 
171 	return hclge_cmd_send(&hdev->hw, &desc, 1);
172 }
173 
174 static int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap,
175 				  u8 pfc_bitmap)
176 {
177 	struct hclge_desc desc;
178 	struct hclge_pfc_en_cmd *pfc = (struct hclge_pfc_en_cmd *)desc.data;
179 
180 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PFC_PAUSE_EN, false);
181 
182 	pfc->tx_rx_en_bitmap = tx_rx_bitmap;
183 	pfc->pri_en_bitmap = pfc_bitmap;
184 
185 	return hclge_cmd_send(&hdev->hw, &desc, 1);
186 }
187 
188 static int hclge_pause_param_cfg(struct hclge_dev *hdev, const u8 *addr,
189 				 u8 pause_trans_gap, u16 pause_trans_time)
190 {
191 	struct hclge_cfg_pause_param_cmd *pause_param;
192 	struct hclge_desc desc;
193 
194 	pause_param = (struct hclge_cfg_pause_param_cmd *)desc.data;
195 
196 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, false);
197 
198 	ether_addr_copy(pause_param->mac_addr, addr);
199 	ether_addr_copy(pause_param->mac_addr_extra, addr);
200 	pause_param->pause_trans_gap = pause_trans_gap;
201 	pause_param->pause_trans_time = cpu_to_le16(pause_trans_time);
202 
203 	return hclge_cmd_send(&hdev->hw, &desc, 1);
204 }
205 
206 int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr)
207 {
208 	struct hclge_cfg_pause_param_cmd *pause_param;
209 	struct hclge_desc desc;
210 	u16 trans_time;
211 	u8 trans_gap;
212 	int ret;
213 
214 	pause_param = (struct hclge_cfg_pause_param_cmd *)desc.data;
215 
216 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, true);
217 
218 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
219 	if (ret)
220 		return ret;
221 
222 	trans_gap = pause_param->pause_trans_gap;
223 	trans_time = le16_to_cpu(pause_param->pause_trans_time);
224 
225 	return hclge_pause_param_cfg(hdev, mac_addr, trans_gap, trans_time);
226 }
227 
228 static int hclge_fill_pri_array(struct hclge_dev *hdev, u8 *pri, u8 pri_id)
229 {
230 	u8 tc;
231 
232 	tc = hdev->tm_info.prio_tc[pri_id];
233 
234 	if (tc >= hdev->tm_info.num_tc)
235 		return -EINVAL;
236 
237 	/**
238 	 * the register for priority has four bytes, the first bytes includes
239 	 *  priority0 and priority1, the higher 4bit stands for priority1
240 	 *  while the lower 4bit stands for priority0, as below:
241 	 * first byte:	| pri_1 | pri_0 |
242 	 * second byte:	| pri_3 | pri_2 |
243 	 * third byte:	| pri_5 | pri_4 |
244 	 * fourth byte:	| pri_7 | pri_6 |
245 	 */
246 	pri[pri_id >> 1] |= tc << ((pri_id & 1) * 4);
247 
248 	return 0;
249 }
250 
251 static int hclge_up_to_tc_map(struct hclge_dev *hdev)
252 {
253 	struct hclge_desc desc;
254 	u8 *pri = (u8 *)desc.data;
255 	u8 pri_id;
256 	int ret;
257 
258 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PRI_TO_TC_MAPPING, false);
259 
260 	for (pri_id = 0; pri_id < HNAE3_MAX_USER_PRIO; pri_id++) {
261 		ret = hclge_fill_pri_array(hdev, pri, pri_id);
262 		if (ret)
263 			return ret;
264 	}
265 
266 	return hclge_cmd_send(&hdev->hw, &desc, 1);
267 }
268 
269 static int hclge_tm_pg_to_pri_map_cfg(struct hclge_dev *hdev,
270 				      u8 pg_id, u8 pri_bit_map)
271 {
272 	struct hclge_pg_to_pri_link_cmd *map;
273 	struct hclge_desc desc;
274 
275 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_TO_PRI_LINK, false);
276 
277 	map = (struct hclge_pg_to_pri_link_cmd *)desc.data;
278 
279 	map->pg_id = pg_id;
280 	map->pri_bit_map = pri_bit_map;
281 
282 	return hclge_cmd_send(&hdev->hw, &desc, 1);
283 }
284 
285 static int hclge_tm_qs_to_pri_map_cfg(struct hclge_dev *hdev,
286 				      u16 qs_id, u8 pri)
287 {
288 	struct hclge_qs_to_pri_link_cmd *map;
289 	struct hclge_desc desc;
290 
291 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_TO_PRI_LINK, false);
292 
293 	map = (struct hclge_qs_to_pri_link_cmd *)desc.data;
294 
295 	map->qs_id = cpu_to_le16(qs_id);
296 	map->priority = pri;
297 	map->link_vld = HCLGE_TM_QS_PRI_LINK_VLD_MSK;
298 
299 	return hclge_cmd_send(&hdev->hw, &desc, 1);
300 }
301 
302 static int hclge_tm_q_to_qs_map_cfg(struct hclge_dev *hdev,
303 				    u16 q_id, u16 qs_id)
304 {
305 	struct hclge_nq_to_qs_link_cmd *map;
306 	struct hclge_desc desc;
307 	u16 qs_id_l;
308 	u16 qs_id_h;
309 
310 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_NQ_TO_QS_LINK, false);
311 
312 	map = (struct hclge_nq_to_qs_link_cmd *)desc.data;
313 
314 	map->nq_id = cpu_to_le16(q_id);
315 
316 	/* convert qs_id to the following format to support qset_id >= 1024
317 	 * qs_id: | 15 | 14 ~ 10 |  9 ~ 0   |
318 	 *            /         / \         \
319 	 *           /         /   \         \
320 	 * qset_id: | 15 ~ 11 |  10 |  9 ~ 0  |
321 	 *          | qs_id_h | vld | qs_id_l |
322 	 */
323 	qs_id_l = hnae3_get_field(qs_id, HCLGE_TM_QS_ID_L_MSK,
324 				  HCLGE_TM_QS_ID_L_S);
325 	qs_id_h = hnae3_get_field(qs_id, HCLGE_TM_QS_ID_H_MSK,
326 				  HCLGE_TM_QS_ID_H_S);
327 	hnae3_set_field(qs_id, HCLGE_TM_QS_ID_L_MSK, HCLGE_TM_QS_ID_L_S,
328 			qs_id_l);
329 	hnae3_set_field(qs_id, HCLGE_TM_QS_ID_H_EXT_MSK, HCLGE_TM_QS_ID_H_EXT_S,
330 			qs_id_h);
331 	map->qset_id = cpu_to_le16(qs_id | HCLGE_TM_Q_QS_LINK_VLD_MSK);
332 
333 	return hclge_cmd_send(&hdev->hw, &desc, 1);
334 }
335 
336 static int hclge_tm_pg_weight_cfg(struct hclge_dev *hdev, u8 pg_id,
337 				  u8 dwrr)
338 {
339 	struct hclge_pg_weight_cmd *weight;
340 	struct hclge_desc desc;
341 
342 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_WEIGHT, false);
343 
344 	weight = (struct hclge_pg_weight_cmd *)desc.data;
345 
346 	weight->pg_id = pg_id;
347 	weight->dwrr = dwrr;
348 
349 	return hclge_cmd_send(&hdev->hw, &desc, 1);
350 }
351 
352 static int hclge_tm_pri_weight_cfg(struct hclge_dev *hdev, u8 pri_id,
353 				   u8 dwrr)
354 {
355 	struct hclge_priority_weight_cmd *weight;
356 	struct hclge_desc desc;
357 
358 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_WEIGHT, false);
359 
360 	weight = (struct hclge_priority_weight_cmd *)desc.data;
361 
362 	weight->pri_id = pri_id;
363 	weight->dwrr = dwrr;
364 
365 	return hclge_cmd_send(&hdev->hw, &desc, 1);
366 }
367 
368 static int hclge_tm_qs_weight_cfg(struct hclge_dev *hdev, u16 qs_id,
369 				  u8 dwrr)
370 {
371 	struct hclge_qs_weight_cmd *weight;
372 	struct hclge_desc desc;
373 
374 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_WEIGHT, false);
375 
376 	weight = (struct hclge_qs_weight_cmd *)desc.data;
377 
378 	weight->qs_id = cpu_to_le16(qs_id);
379 	weight->dwrr = dwrr;
380 
381 	return hclge_cmd_send(&hdev->hw, &desc, 1);
382 }
383 
384 static u32 hclge_tm_get_shapping_para(u8 ir_b, u8 ir_u, u8 ir_s,
385 				      u8 bs_b, u8 bs_s)
386 {
387 	u32 shapping_para = 0;
388 
389 	hclge_tm_set_field(shapping_para, IR_B, ir_b);
390 	hclge_tm_set_field(shapping_para, IR_U, ir_u);
391 	hclge_tm_set_field(shapping_para, IR_S, ir_s);
392 	hclge_tm_set_field(shapping_para, BS_B, bs_b);
393 	hclge_tm_set_field(shapping_para, BS_S, bs_s);
394 
395 	return shapping_para;
396 }
397 
398 static int hclge_tm_pg_shapping_cfg(struct hclge_dev *hdev,
399 				    enum hclge_shap_bucket bucket, u8 pg_id,
400 				    u32 shapping_para, u32 rate)
401 {
402 	struct hclge_pg_shapping_cmd *shap_cfg_cmd;
403 	enum hclge_opcode_type opcode;
404 	struct hclge_desc desc;
405 
406 	opcode = bucket ? HCLGE_OPC_TM_PG_P_SHAPPING :
407 		 HCLGE_OPC_TM_PG_C_SHAPPING;
408 	hclge_cmd_setup_basic_desc(&desc, opcode, false);
409 
410 	shap_cfg_cmd = (struct hclge_pg_shapping_cmd *)desc.data;
411 
412 	shap_cfg_cmd->pg_id = pg_id;
413 
414 	shap_cfg_cmd->pg_shapping_para = cpu_to_le32(shapping_para);
415 
416 	hnae3_set_bit(shap_cfg_cmd->flag, HCLGE_TM_RATE_VLD, 1);
417 
418 	shap_cfg_cmd->pg_rate = cpu_to_le32(rate);
419 
420 	return hclge_cmd_send(&hdev->hw, &desc, 1);
421 }
422 
423 static int hclge_tm_port_shaper_cfg(struct hclge_dev *hdev)
424 {
425 	struct hclge_port_shapping_cmd *shap_cfg_cmd;
426 	struct hclge_shaper_ir_para ir_para;
427 	struct hclge_desc desc;
428 	u32 shapping_para;
429 	int ret;
430 
431 	ret = hclge_shaper_para_calc(hdev->hw.mac.speed, HCLGE_SHAPER_LVL_PORT,
432 				     &ir_para,
433 				     hdev->ae_dev->dev_specs.max_tm_rate);
434 	if (ret)
435 		return ret;
436 
437 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PORT_SHAPPING, false);
438 	shap_cfg_cmd = (struct hclge_port_shapping_cmd *)desc.data;
439 
440 	shapping_para = hclge_tm_get_shapping_para(ir_para.ir_b, ir_para.ir_u,
441 						   ir_para.ir_s,
442 						   HCLGE_SHAPER_BS_U_DEF,
443 						   HCLGE_SHAPER_BS_S_DEF);
444 
445 	shap_cfg_cmd->port_shapping_para = cpu_to_le32(shapping_para);
446 
447 	hnae3_set_bit(shap_cfg_cmd->flag, HCLGE_TM_RATE_VLD, 1);
448 
449 	shap_cfg_cmd->port_rate = cpu_to_le32(hdev->hw.mac.speed);
450 
451 	return hclge_cmd_send(&hdev->hw, &desc, 1);
452 }
453 
454 static int hclge_tm_pri_shapping_cfg(struct hclge_dev *hdev,
455 				     enum hclge_shap_bucket bucket, u8 pri_id,
456 				     u32 shapping_para, u32 rate)
457 {
458 	struct hclge_pri_shapping_cmd *shap_cfg_cmd;
459 	enum hclge_opcode_type opcode;
460 	struct hclge_desc desc;
461 
462 	opcode = bucket ? HCLGE_OPC_TM_PRI_P_SHAPPING :
463 		 HCLGE_OPC_TM_PRI_C_SHAPPING;
464 
465 	hclge_cmd_setup_basic_desc(&desc, opcode, false);
466 
467 	shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data;
468 
469 	shap_cfg_cmd->pri_id = pri_id;
470 
471 	shap_cfg_cmd->pri_shapping_para = cpu_to_le32(shapping_para);
472 
473 	hnae3_set_bit(shap_cfg_cmd->flag, HCLGE_TM_RATE_VLD, 1);
474 
475 	shap_cfg_cmd->pri_rate = cpu_to_le32(rate);
476 
477 	return hclge_cmd_send(&hdev->hw, &desc, 1);
478 }
479 
480 static int hclge_tm_pg_schd_mode_cfg(struct hclge_dev *hdev, u8 pg_id)
481 {
482 	struct hclge_desc desc;
483 
484 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_SCH_MODE_CFG, false);
485 
486 	if (hdev->tm_info.pg_info[pg_id].pg_sch_mode == HCLGE_SCH_MODE_DWRR)
487 		desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK);
488 	else
489 		desc.data[1] = 0;
490 
491 	desc.data[0] = cpu_to_le32(pg_id);
492 
493 	return hclge_cmd_send(&hdev->hw, &desc, 1);
494 }
495 
496 static int hclge_tm_pri_schd_mode_cfg(struct hclge_dev *hdev, u8 pri_id)
497 {
498 	struct hclge_desc desc;
499 
500 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_SCH_MODE_CFG, false);
501 
502 	if (hdev->tm_info.tc_info[pri_id].tc_sch_mode == HCLGE_SCH_MODE_DWRR)
503 		desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK);
504 	else
505 		desc.data[1] = 0;
506 
507 	desc.data[0] = cpu_to_le32(pri_id);
508 
509 	return hclge_cmd_send(&hdev->hw, &desc, 1);
510 }
511 
512 static int hclge_tm_qs_schd_mode_cfg(struct hclge_dev *hdev, u16 qs_id, u8 mode)
513 {
514 	struct hclge_desc desc;
515 
516 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_SCH_MODE_CFG, false);
517 
518 	if (mode == HCLGE_SCH_MODE_DWRR)
519 		desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK);
520 	else
521 		desc.data[1] = 0;
522 
523 	desc.data[0] = cpu_to_le32(qs_id);
524 
525 	return hclge_cmd_send(&hdev->hw, &desc, 1);
526 }
527 
528 static int hclge_tm_qs_bp_cfg(struct hclge_dev *hdev, u8 tc, u8 grp_id,
529 			      u32 bit_map)
530 {
531 	struct hclge_bp_to_qs_map_cmd *bp_to_qs_map_cmd;
532 	struct hclge_desc desc;
533 
534 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_BP_TO_QSET_MAPPING,
535 				   false);
536 
537 	bp_to_qs_map_cmd = (struct hclge_bp_to_qs_map_cmd *)desc.data;
538 
539 	bp_to_qs_map_cmd->tc_id = tc;
540 	bp_to_qs_map_cmd->qs_group_id = grp_id;
541 	bp_to_qs_map_cmd->qs_bit_map = cpu_to_le32(bit_map);
542 
543 	return hclge_cmd_send(&hdev->hw, &desc, 1);
544 }
545 
546 int hclge_tm_qs_shaper_cfg(struct hclge_vport *vport, int max_tx_rate)
547 {
548 	struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
549 	struct hclge_qs_shapping_cmd *shap_cfg_cmd;
550 	struct hclge_shaper_ir_para ir_para;
551 	struct hclge_dev *hdev = vport->back;
552 	struct hclge_desc desc;
553 	u32 shaper_para;
554 	int ret, i;
555 
556 	if (!max_tx_rate)
557 		max_tx_rate = hdev->ae_dev->dev_specs.max_tm_rate;
558 
559 	ret = hclge_shaper_para_calc(max_tx_rate, HCLGE_SHAPER_LVL_QSET,
560 				     &ir_para,
561 				     hdev->ae_dev->dev_specs.max_tm_rate);
562 	if (ret)
563 		return ret;
564 
565 	shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b, ir_para.ir_u,
566 						 ir_para.ir_s,
567 						 HCLGE_SHAPER_BS_U_DEF,
568 						 HCLGE_SHAPER_BS_S_DEF);
569 
570 	for (i = 0; i < kinfo->tc_info.num_tc; i++) {
571 		hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QCN_SHAPPING_CFG,
572 					   false);
573 
574 		shap_cfg_cmd = (struct hclge_qs_shapping_cmd *)desc.data;
575 		shap_cfg_cmd->qs_id = cpu_to_le16(vport->qs_offset + i);
576 		shap_cfg_cmd->qs_shapping_para = cpu_to_le32(shaper_para);
577 
578 		hnae3_set_bit(shap_cfg_cmd->flag, HCLGE_TM_RATE_VLD, 1);
579 		shap_cfg_cmd->qs_rate = cpu_to_le32(max_tx_rate);
580 
581 		ret = hclge_cmd_send(&hdev->hw, &desc, 1);
582 		if (ret) {
583 			dev_err(&hdev->pdev->dev,
584 				"vport%u, qs%u failed to set tx_rate:%d, ret=%d\n",
585 				vport->vport_id, shap_cfg_cmd->qs_id,
586 				max_tx_rate, ret);
587 			return ret;
588 		}
589 	}
590 
591 	return 0;
592 }
593 
594 static u16 hclge_vport_get_max_rss_size(struct hclge_vport *vport)
595 {
596 	struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
597 	struct hnae3_tc_info *tc_info = &kinfo->tc_info;
598 	struct hclge_dev *hdev = vport->back;
599 	u16 max_rss_size = 0;
600 	int i;
601 
602 	if (!tc_info->mqprio_active)
603 		return vport->alloc_tqps / tc_info->num_tc;
604 
605 	for (i = 0; i < HNAE3_MAX_TC; i++) {
606 		if (!(hdev->hw_tc_map & BIT(i)) || i >= tc_info->num_tc)
607 			continue;
608 		if (max_rss_size < tc_info->tqp_count[i])
609 			max_rss_size = tc_info->tqp_count[i];
610 	}
611 
612 	return max_rss_size;
613 }
614 
615 static u16 hclge_vport_get_tqp_num(struct hclge_vport *vport)
616 {
617 	struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
618 	struct hnae3_tc_info *tc_info = &kinfo->tc_info;
619 	struct hclge_dev *hdev = vport->back;
620 	int sum = 0;
621 	int i;
622 
623 	if (!tc_info->mqprio_active)
624 		return kinfo->rss_size * tc_info->num_tc;
625 
626 	for (i = 0; i < HNAE3_MAX_TC; i++) {
627 		if (hdev->hw_tc_map & BIT(i) && i < tc_info->num_tc)
628 			sum += tc_info->tqp_count[i];
629 	}
630 
631 	return sum;
632 }
633 
634 static void hclge_tm_update_kinfo_rss_size(struct hclge_vport *vport)
635 {
636 	struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
637 	struct hclge_dev *hdev = vport->back;
638 	u16 vport_max_rss_size;
639 	u16 max_rss_size;
640 
641 	/* TC configuration is shared by PF/VF in one port, only allow
642 	 * one tc for VF for simplicity. VF's vport_id is non zero.
643 	 */
644 	if (vport->vport_id) {
645 		kinfo->tc_info.num_tc = 1;
646 		vport->qs_offset = HNAE3_MAX_TC +
647 				   vport->vport_id - HCLGE_VF_VPORT_START_NUM;
648 		vport_max_rss_size = hdev->vf_rss_size_max;
649 	} else {
650 		kinfo->tc_info.num_tc =
651 			min_t(u16, vport->alloc_tqps, hdev->tm_info.num_tc);
652 		vport->qs_offset = 0;
653 		vport_max_rss_size = hdev->pf_rss_size_max;
654 	}
655 
656 	max_rss_size = min_t(u16, vport_max_rss_size,
657 			     hclge_vport_get_max_rss_size(vport));
658 
659 	/* Set to user value, no larger than max_rss_size. */
660 	if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size &&
661 	    kinfo->req_rss_size <= max_rss_size) {
662 		dev_info(&hdev->pdev->dev, "rss changes from %u to %u\n",
663 			 kinfo->rss_size, kinfo->req_rss_size);
664 		kinfo->rss_size = kinfo->req_rss_size;
665 	} else if (kinfo->rss_size > max_rss_size ||
666 		   (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) {
667 		/* Set to the maximum specification value (max_rss_size). */
668 		kinfo->rss_size = max_rss_size;
669 	}
670 }
671 
672 static void hclge_tm_vport_tc_info_update(struct hclge_vport *vport)
673 {
674 	struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
675 	struct hclge_dev *hdev = vport->back;
676 	u8 i;
677 
678 	hclge_tm_update_kinfo_rss_size(vport);
679 	kinfo->num_tqps = hclge_vport_get_tqp_num(vport);
680 	vport->dwrr = 100;  /* 100 percent as init */
681 	vport->alloc_rss_size = kinfo->rss_size;
682 	vport->bw_limit = hdev->tm_info.pg_info[0].bw_limit;
683 
684 	/* when enable mqprio, the tc_info has been updated. */
685 	if (kinfo->tc_info.mqprio_active)
686 		return;
687 
688 	for (i = 0; i < HNAE3_MAX_TC; i++) {
689 		if (hdev->hw_tc_map & BIT(i) && i < kinfo->tc_info.num_tc) {
690 			kinfo->tc_info.tqp_offset[i] = i * kinfo->rss_size;
691 			kinfo->tc_info.tqp_count[i] = kinfo->rss_size;
692 		} else {
693 			/* Set to default queue if TC is disable */
694 			kinfo->tc_info.tqp_offset[i] = 0;
695 			kinfo->tc_info.tqp_count[i] = 1;
696 		}
697 	}
698 
699 	memcpy(kinfo->tc_info.prio_tc, hdev->tm_info.prio_tc,
700 	       sizeof_field(struct hnae3_tc_info, prio_tc));
701 }
702 
703 static void hclge_tm_vport_info_update(struct hclge_dev *hdev)
704 {
705 	struct hclge_vport *vport = hdev->vport;
706 	u32 i;
707 
708 	for (i = 0; i < hdev->num_alloc_vport; i++) {
709 		hclge_tm_vport_tc_info_update(vport);
710 
711 		vport++;
712 	}
713 }
714 
715 static void hclge_tm_tc_info_init(struct hclge_dev *hdev)
716 {
717 	u8 i;
718 
719 	for (i = 0; i < hdev->tm_info.num_tc; i++) {
720 		hdev->tm_info.tc_info[i].tc_id = i;
721 		hdev->tm_info.tc_info[i].tc_sch_mode = HCLGE_SCH_MODE_DWRR;
722 		hdev->tm_info.tc_info[i].pgid = 0;
723 		hdev->tm_info.tc_info[i].bw_limit =
724 			hdev->tm_info.pg_info[0].bw_limit;
725 	}
726 
727 	for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
728 		hdev->tm_info.prio_tc[i] =
729 			(i >= hdev->tm_info.num_tc) ? 0 : i;
730 }
731 
732 static void hclge_tm_pg_info_init(struct hclge_dev *hdev)
733 {
734 #define BW_PERCENT	100
735 
736 	u8 i;
737 
738 	for (i = 0; i < hdev->tm_info.num_pg; i++) {
739 		int k;
740 
741 		hdev->tm_info.pg_dwrr[i] = i ? 0 : BW_PERCENT;
742 
743 		hdev->tm_info.pg_info[i].pg_id = i;
744 		hdev->tm_info.pg_info[i].pg_sch_mode = HCLGE_SCH_MODE_DWRR;
745 
746 		hdev->tm_info.pg_info[i].bw_limit =
747 					hdev->ae_dev->dev_specs.max_tm_rate;
748 
749 		if (i != 0)
750 			continue;
751 
752 		hdev->tm_info.pg_info[i].tc_bit_map = hdev->hw_tc_map;
753 		for (k = 0; k < hdev->tm_info.num_tc; k++)
754 			hdev->tm_info.pg_info[i].tc_dwrr[k] = BW_PERCENT;
755 	}
756 }
757 
758 static void hclge_update_fc_mode_by_dcb_flag(struct hclge_dev *hdev)
759 {
760 	if (hdev->tm_info.num_tc == 1 && !hdev->tm_info.pfc_en) {
761 		if (hdev->fc_mode_last_time == HCLGE_FC_PFC)
762 			dev_warn(&hdev->pdev->dev,
763 				 "Only 1 tc used, but last mode is FC_PFC\n");
764 
765 		hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
766 	} else if (hdev->tm_info.fc_mode != HCLGE_FC_PFC) {
767 		/* fc_mode_last_time record the last fc_mode when
768 		 * DCB is enabled, so that fc_mode can be set to
769 		 * the correct value when DCB is disabled.
770 		 */
771 		hdev->fc_mode_last_time = hdev->tm_info.fc_mode;
772 		hdev->tm_info.fc_mode = HCLGE_FC_PFC;
773 	}
774 }
775 
776 static void hclge_update_fc_mode(struct hclge_dev *hdev)
777 {
778 	if (!hdev->tm_info.pfc_en) {
779 		hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
780 		return;
781 	}
782 
783 	if (hdev->tm_info.fc_mode != HCLGE_FC_PFC) {
784 		hdev->fc_mode_last_time = hdev->tm_info.fc_mode;
785 		hdev->tm_info.fc_mode = HCLGE_FC_PFC;
786 	}
787 }
788 
789 void hclge_tm_pfc_info_update(struct hclge_dev *hdev)
790 {
791 	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
792 		hclge_update_fc_mode(hdev);
793 	else
794 		hclge_update_fc_mode_by_dcb_flag(hdev);
795 }
796 
797 static void hclge_tm_schd_info_init(struct hclge_dev *hdev)
798 {
799 	hclge_tm_pg_info_init(hdev);
800 
801 	hclge_tm_tc_info_init(hdev);
802 
803 	hclge_tm_vport_info_update(hdev);
804 
805 	hclge_tm_pfc_info_update(hdev);
806 }
807 
808 static int hclge_tm_pg_to_pri_map(struct hclge_dev *hdev)
809 {
810 	int ret;
811 	u32 i;
812 
813 	if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE)
814 		return 0;
815 
816 	for (i = 0; i < hdev->tm_info.num_pg; i++) {
817 		/* Cfg mapping */
818 		ret = hclge_tm_pg_to_pri_map_cfg(
819 			hdev, i, hdev->tm_info.pg_info[i].tc_bit_map);
820 		if (ret)
821 			return ret;
822 	}
823 
824 	return 0;
825 }
826 
827 static int hclge_tm_pg_shaper_cfg(struct hclge_dev *hdev)
828 {
829 	u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate;
830 	struct hclge_shaper_ir_para ir_para;
831 	u32 shaper_para;
832 	int ret;
833 	u32 i;
834 
835 	/* Cfg pg schd */
836 	if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE)
837 		return 0;
838 
839 	/* Pg to pri */
840 	for (i = 0; i < hdev->tm_info.num_pg; i++) {
841 		u32 rate = hdev->tm_info.pg_info[i].bw_limit;
842 
843 		/* Calc shaper para */
844 		ret = hclge_shaper_para_calc(rate, HCLGE_SHAPER_LVL_PG,
845 					     &ir_para, max_tm_rate);
846 		if (ret)
847 			return ret;
848 
849 		shaper_para = hclge_tm_get_shapping_para(0, 0, 0,
850 							 HCLGE_SHAPER_BS_U_DEF,
851 							 HCLGE_SHAPER_BS_S_DEF);
852 		ret = hclge_tm_pg_shapping_cfg(hdev,
853 					       HCLGE_TM_SHAP_C_BUCKET, i,
854 					       shaper_para, rate);
855 		if (ret)
856 			return ret;
857 
858 		shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b,
859 							 ir_para.ir_u,
860 							 ir_para.ir_s,
861 							 HCLGE_SHAPER_BS_U_DEF,
862 							 HCLGE_SHAPER_BS_S_DEF);
863 		ret = hclge_tm_pg_shapping_cfg(hdev,
864 					       HCLGE_TM_SHAP_P_BUCKET, i,
865 					       shaper_para, rate);
866 		if (ret)
867 			return ret;
868 	}
869 
870 	return 0;
871 }
872 
873 static int hclge_tm_pg_dwrr_cfg(struct hclge_dev *hdev)
874 {
875 	int ret;
876 	u32 i;
877 
878 	/* cfg pg schd */
879 	if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE)
880 		return 0;
881 
882 	/* pg to prio */
883 	for (i = 0; i < hdev->tm_info.num_pg; i++) {
884 		/* Cfg dwrr */
885 		ret = hclge_tm_pg_weight_cfg(hdev, i, hdev->tm_info.pg_dwrr[i]);
886 		if (ret)
887 			return ret;
888 	}
889 
890 	return 0;
891 }
892 
893 static int hclge_vport_q_to_qs_map(struct hclge_dev *hdev,
894 				   struct hclge_vport *vport)
895 {
896 	struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
897 	struct hnae3_tc_info *tc_info = &kinfo->tc_info;
898 	struct hnae3_queue **tqp = kinfo->tqp;
899 	u32 i, j;
900 	int ret;
901 
902 	for (i = 0; i < tc_info->num_tc; i++) {
903 		for (j = 0; j < tc_info->tqp_count[i]; j++) {
904 			struct hnae3_queue *q = tqp[tc_info->tqp_offset[i] + j];
905 
906 			ret = hclge_tm_q_to_qs_map_cfg(hdev,
907 						       hclge_get_queue_id(q),
908 						       vport->qs_offset + i);
909 			if (ret)
910 				return ret;
911 		}
912 	}
913 
914 	return 0;
915 }
916 
917 static int hclge_tm_pri_q_qs_cfg(struct hclge_dev *hdev)
918 {
919 	struct hclge_vport *vport = hdev->vport;
920 	int ret;
921 	u32 i, k;
922 
923 	if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {
924 		/* Cfg qs -> pri mapping, one by one mapping */
925 		for (k = 0; k < hdev->num_alloc_vport; k++) {
926 			struct hnae3_knic_private_info *kinfo =
927 				&vport[k].nic.kinfo;
928 
929 			for (i = 0; i < kinfo->tc_info.num_tc; i++) {
930 				ret = hclge_tm_qs_to_pri_map_cfg(
931 					hdev, vport[k].qs_offset + i, i);
932 				if (ret)
933 					return ret;
934 			}
935 		}
936 	} else if (hdev->tx_sch_mode == HCLGE_FLAG_VNET_BASE_SCH_MODE) {
937 		/* Cfg qs -> pri mapping,  qs = tc, pri = vf, 8 qs -> 1 pri */
938 		for (k = 0; k < hdev->num_alloc_vport; k++)
939 			for (i = 0; i < HNAE3_MAX_TC; i++) {
940 				ret = hclge_tm_qs_to_pri_map_cfg(
941 					hdev, vport[k].qs_offset + i, k);
942 				if (ret)
943 					return ret;
944 			}
945 	} else {
946 		return -EINVAL;
947 	}
948 
949 	/* Cfg q -> qs mapping */
950 	for (i = 0; i < hdev->num_alloc_vport; i++) {
951 		ret = hclge_vport_q_to_qs_map(hdev, vport);
952 		if (ret)
953 			return ret;
954 
955 		vport++;
956 	}
957 
958 	return 0;
959 }
960 
961 static int hclge_tm_pri_tc_base_shaper_cfg(struct hclge_dev *hdev)
962 {
963 	u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate;
964 	struct hclge_shaper_ir_para ir_para;
965 	u32 shaper_para;
966 	int ret;
967 	u32 i;
968 
969 	for (i = 0; i < hdev->tm_info.num_tc; i++) {
970 		u32 rate = hdev->tm_info.tc_info[i].bw_limit;
971 
972 		ret = hclge_shaper_para_calc(rate, HCLGE_SHAPER_LVL_PRI,
973 					     &ir_para, max_tm_rate);
974 		if (ret)
975 			return ret;
976 
977 		shaper_para = hclge_tm_get_shapping_para(0, 0, 0,
978 							 HCLGE_SHAPER_BS_U_DEF,
979 							 HCLGE_SHAPER_BS_S_DEF);
980 		ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_C_BUCKET, i,
981 						shaper_para, rate);
982 		if (ret)
983 			return ret;
984 
985 		shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b,
986 							 ir_para.ir_u,
987 							 ir_para.ir_s,
988 							 HCLGE_SHAPER_BS_U_DEF,
989 							 HCLGE_SHAPER_BS_S_DEF);
990 		ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_P_BUCKET, i,
991 						shaper_para, rate);
992 		if (ret)
993 			return ret;
994 	}
995 
996 	return 0;
997 }
998 
999 static int hclge_tm_pri_vnet_base_shaper_pri_cfg(struct hclge_vport *vport)
1000 {
1001 	struct hclge_dev *hdev = vport->back;
1002 	struct hclge_shaper_ir_para ir_para;
1003 	u32 shaper_para;
1004 	int ret;
1005 
1006 	ret = hclge_shaper_para_calc(vport->bw_limit, HCLGE_SHAPER_LVL_VF,
1007 				     &ir_para,
1008 				     hdev->ae_dev->dev_specs.max_tm_rate);
1009 	if (ret)
1010 		return ret;
1011 
1012 	shaper_para = hclge_tm_get_shapping_para(0, 0, 0,
1013 						 HCLGE_SHAPER_BS_U_DEF,
1014 						 HCLGE_SHAPER_BS_S_DEF);
1015 	ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_C_BUCKET,
1016 					vport->vport_id, shaper_para,
1017 					vport->bw_limit);
1018 	if (ret)
1019 		return ret;
1020 
1021 	shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b, ir_para.ir_u,
1022 						 ir_para.ir_s,
1023 						 HCLGE_SHAPER_BS_U_DEF,
1024 						 HCLGE_SHAPER_BS_S_DEF);
1025 	ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_P_BUCKET,
1026 					vport->vport_id, shaper_para,
1027 					vport->bw_limit);
1028 	if (ret)
1029 		return ret;
1030 
1031 	return 0;
1032 }
1033 
1034 static int hclge_tm_pri_vnet_base_shaper_qs_cfg(struct hclge_vport *vport)
1035 {
1036 	struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
1037 	struct hclge_dev *hdev = vport->back;
1038 	u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate;
1039 	struct hclge_shaper_ir_para ir_para;
1040 	u32 i;
1041 	int ret;
1042 
1043 	for (i = 0; i < kinfo->tc_info.num_tc; i++) {
1044 		ret = hclge_shaper_para_calc(hdev->tm_info.tc_info[i].bw_limit,
1045 					     HCLGE_SHAPER_LVL_QSET,
1046 					     &ir_para, max_tm_rate);
1047 		if (ret)
1048 			return ret;
1049 	}
1050 
1051 	return 0;
1052 }
1053 
1054 static int hclge_tm_pri_vnet_base_shaper_cfg(struct hclge_dev *hdev)
1055 {
1056 	struct hclge_vport *vport = hdev->vport;
1057 	int ret;
1058 	u32 i;
1059 
1060 	/* Need config vport shaper */
1061 	for (i = 0; i < hdev->num_alloc_vport; i++) {
1062 		ret = hclge_tm_pri_vnet_base_shaper_pri_cfg(vport);
1063 		if (ret)
1064 			return ret;
1065 
1066 		ret = hclge_tm_pri_vnet_base_shaper_qs_cfg(vport);
1067 		if (ret)
1068 			return ret;
1069 
1070 		vport++;
1071 	}
1072 
1073 	return 0;
1074 }
1075 
1076 static int hclge_tm_pri_shaper_cfg(struct hclge_dev *hdev)
1077 {
1078 	int ret;
1079 
1080 	if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {
1081 		ret = hclge_tm_pri_tc_base_shaper_cfg(hdev);
1082 		if (ret)
1083 			return ret;
1084 	} else {
1085 		ret = hclge_tm_pri_vnet_base_shaper_cfg(hdev);
1086 		if (ret)
1087 			return ret;
1088 	}
1089 
1090 	return 0;
1091 }
1092 
1093 static int hclge_tm_pri_tc_base_dwrr_cfg(struct hclge_dev *hdev)
1094 {
1095 	struct hclge_vport *vport = hdev->vport;
1096 	struct hclge_pg_info *pg_info;
1097 	u8 dwrr;
1098 	int ret;
1099 	u32 i, k;
1100 
1101 	for (i = 0; i < hdev->tm_info.num_tc; i++) {
1102 		pg_info =
1103 			&hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid];
1104 		dwrr = pg_info->tc_dwrr[i];
1105 
1106 		ret = hclge_tm_pri_weight_cfg(hdev, i, dwrr);
1107 		if (ret)
1108 			return ret;
1109 
1110 		for (k = 0; k < hdev->num_alloc_vport; k++) {
1111 			ret = hclge_tm_qs_weight_cfg(
1112 				hdev, vport[k].qs_offset + i,
1113 				vport[k].dwrr);
1114 			if (ret)
1115 				return ret;
1116 		}
1117 	}
1118 
1119 	return 0;
1120 }
1121 
1122 static int hclge_tm_ets_tc_dwrr_cfg(struct hclge_dev *hdev)
1123 {
1124 #define DEFAULT_TC_WEIGHT	1
1125 #define DEFAULT_TC_OFFSET	14
1126 
1127 	struct hclge_ets_tc_weight_cmd *ets_weight;
1128 	struct hclge_desc desc;
1129 	unsigned int i;
1130 
1131 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ETS_TC_WEIGHT, false);
1132 	ets_weight = (struct hclge_ets_tc_weight_cmd *)desc.data;
1133 
1134 	for (i = 0; i < HNAE3_MAX_TC; i++) {
1135 		struct hclge_pg_info *pg_info;
1136 
1137 		ets_weight->tc_weight[i] = DEFAULT_TC_WEIGHT;
1138 
1139 		if (!(hdev->hw_tc_map & BIT(i)))
1140 			continue;
1141 
1142 		pg_info =
1143 			&hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid];
1144 		ets_weight->tc_weight[i] = pg_info->tc_dwrr[i];
1145 	}
1146 
1147 	ets_weight->weight_offset = DEFAULT_TC_OFFSET;
1148 
1149 	return hclge_cmd_send(&hdev->hw, &desc, 1);
1150 }
1151 
1152 static int hclge_tm_pri_vnet_base_dwrr_pri_cfg(struct hclge_vport *vport)
1153 {
1154 	struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
1155 	struct hclge_dev *hdev = vport->back;
1156 	int ret;
1157 	u8 i;
1158 
1159 	/* Vf dwrr */
1160 	ret = hclge_tm_pri_weight_cfg(hdev, vport->vport_id, vport->dwrr);
1161 	if (ret)
1162 		return ret;
1163 
1164 	/* Qset dwrr */
1165 	for (i = 0; i < kinfo->tc_info.num_tc; i++) {
1166 		ret = hclge_tm_qs_weight_cfg(
1167 			hdev, vport->qs_offset + i,
1168 			hdev->tm_info.pg_info[0].tc_dwrr[i]);
1169 		if (ret)
1170 			return ret;
1171 	}
1172 
1173 	return 0;
1174 }
1175 
1176 static int hclge_tm_pri_vnet_base_dwrr_cfg(struct hclge_dev *hdev)
1177 {
1178 	struct hclge_vport *vport = hdev->vport;
1179 	int ret;
1180 	u32 i;
1181 
1182 	for (i = 0; i < hdev->num_alloc_vport; i++) {
1183 		ret = hclge_tm_pri_vnet_base_dwrr_pri_cfg(vport);
1184 		if (ret)
1185 			return ret;
1186 
1187 		vport++;
1188 	}
1189 
1190 	return 0;
1191 }
1192 
1193 static int hclge_tm_pri_dwrr_cfg(struct hclge_dev *hdev)
1194 {
1195 	int ret;
1196 
1197 	if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {
1198 		ret = hclge_tm_pri_tc_base_dwrr_cfg(hdev);
1199 		if (ret)
1200 			return ret;
1201 
1202 		if (!hnae3_dev_dcb_supported(hdev))
1203 			return 0;
1204 
1205 		ret = hclge_tm_ets_tc_dwrr_cfg(hdev);
1206 		if (ret == -EOPNOTSUPP) {
1207 			dev_warn(&hdev->pdev->dev,
1208 				 "fw %08x does't support ets tc weight cmd\n",
1209 				 hdev->fw_version);
1210 			ret = 0;
1211 		}
1212 
1213 		return ret;
1214 	} else {
1215 		ret = hclge_tm_pri_vnet_base_dwrr_cfg(hdev);
1216 		if (ret)
1217 			return ret;
1218 	}
1219 
1220 	return 0;
1221 }
1222 
1223 static int hclge_tm_map_cfg(struct hclge_dev *hdev)
1224 {
1225 	int ret;
1226 
1227 	ret = hclge_up_to_tc_map(hdev);
1228 	if (ret)
1229 		return ret;
1230 
1231 	ret = hclge_tm_pg_to_pri_map(hdev);
1232 	if (ret)
1233 		return ret;
1234 
1235 	return hclge_tm_pri_q_qs_cfg(hdev);
1236 }
1237 
1238 static int hclge_tm_shaper_cfg(struct hclge_dev *hdev)
1239 {
1240 	int ret;
1241 
1242 	ret = hclge_tm_port_shaper_cfg(hdev);
1243 	if (ret)
1244 		return ret;
1245 
1246 	ret = hclge_tm_pg_shaper_cfg(hdev);
1247 	if (ret)
1248 		return ret;
1249 
1250 	return hclge_tm_pri_shaper_cfg(hdev);
1251 }
1252 
1253 int hclge_tm_dwrr_cfg(struct hclge_dev *hdev)
1254 {
1255 	int ret;
1256 
1257 	ret = hclge_tm_pg_dwrr_cfg(hdev);
1258 	if (ret)
1259 		return ret;
1260 
1261 	return hclge_tm_pri_dwrr_cfg(hdev);
1262 }
1263 
1264 static int hclge_tm_lvl2_schd_mode_cfg(struct hclge_dev *hdev)
1265 {
1266 	int ret;
1267 	u8 i;
1268 
1269 	/* Only being config on TC-Based scheduler mode */
1270 	if (hdev->tx_sch_mode == HCLGE_FLAG_VNET_BASE_SCH_MODE)
1271 		return 0;
1272 
1273 	for (i = 0; i < hdev->tm_info.num_pg; i++) {
1274 		ret = hclge_tm_pg_schd_mode_cfg(hdev, i);
1275 		if (ret)
1276 			return ret;
1277 	}
1278 
1279 	return 0;
1280 }
1281 
1282 static int hclge_tm_schd_mode_vnet_base_cfg(struct hclge_vport *vport)
1283 {
1284 	struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
1285 	struct hclge_dev *hdev = vport->back;
1286 	int ret;
1287 	u8 i;
1288 
1289 	if (vport->vport_id >= HNAE3_MAX_TC)
1290 		return -EINVAL;
1291 
1292 	ret = hclge_tm_pri_schd_mode_cfg(hdev, vport->vport_id);
1293 	if (ret)
1294 		return ret;
1295 
1296 	for (i = 0; i < kinfo->tc_info.num_tc; i++) {
1297 		u8 sch_mode = hdev->tm_info.tc_info[i].tc_sch_mode;
1298 
1299 		ret = hclge_tm_qs_schd_mode_cfg(hdev, vport->qs_offset + i,
1300 						sch_mode);
1301 		if (ret)
1302 			return ret;
1303 	}
1304 
1305 	return 0;
1306 }
1307 
1308 static int hclge_tm_lvl34_schd_mode_cfg(struct hclge_dev *hdev)
1309 {
1310 	struct hclge_vport *vport = hdev->vport;
1311 	int ret;
1312 	u8 i, k;
1313 
1314 	if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {
1315 		for (i = 0; i < hdev->tm_info.num_tc; i++) {
1316 			ret = hclge_tm_pri_schd_mode_cfg(hdev, i);
1317 			if (ret)
1318 				return ret;
1319 
1320 			for (k = 0; k < hdev->num_alloc_vport; k++) {
1321 				ret = hclge_tm_qs_schd_mode_cfg(
1322 					hdev, vport[k].qs_offset + i,
1323 					HCLGE_SCH_MODE_DWRR);
1324 				if (ret)
1325 					return ret;
1326 			}
1327 		}
1328 	} else {
1329 		for (i = 0; i < hdev->num_alloc_vport; i++) {
1330 			ret = hclge_tm_schd_mode_vnet_base_cfg(vport);
1331 			if (ret)
1332 				return ret;
1333 
1334 			vport++;
1335 		}
1336 	}
1337 
1338 	return 0;
1339 }
1340 
1341 static int hclge_tm_schd_mode_hw(struct hclge_dev *hdev)
1342 {
1343 	int ret;
1344 
1345 	ret = hclge_tm_lvl2_schd_mode_cfg(hdev);
1346 	if (ret)
1347 		return ret;
1348 
1349 	return hclge_tm_lvl34_schd_mode_cfg(hdev);
1350 }
1351 
1352 int hclge_tm_schd_setup_hw(struct hclge_dev *hdev)
1353 {
1354 	int ret;
1355 
1356 	/* Cfg tm mapping  */
1357 	ret = hclge_tm_map_cfg(hdev);
1358 	if (ret)
1359 		return ret;
1360 
1361 	/* Cfg tm shaper */
1362 	ret = hclge_tm_shaper_cfg(hdev);
1363 	if (ret)
1364 		return ret;
1365 
1366 	/* Cfg dwrr */
1367 	ret = hclge_tm_dwrr_cfg(hdev);
1368 	if (ret)
1369 		return ret;
1370 
1371 	/* Cfg schd mode for each level schd */
1372 	return hclge_tm_schd_mode_hw(hdev);
1373 }
1374 
1375 static int hclge_pause_param_setup_hw(struct hclge_dev *hdev)
1376 {
1377 	struct hclge_mac *mac = &hdev->hw.mac;
1378 
1379 	return hclge_pause_param_cfg(hdev, mac->mac_addr,
1380 				     HCLGE_DEFAULT_PAUSE_TRANS_GAP,
1381 				     HCLGE_DEFAULT_PAUSE_TRANS_TIME);
1382 }
1383 
1384 static int hclge_pfc_setup_hw(struct hclge_dev *hdev)
1385 {
1386 	u8 enable_bitmap = 0;
1387 
1388 	if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
1389 		enable_bitmap = HCLGE_TX_MAC_PAUSE_EN_MSK |
1390 				HCLGE_RX_MAC_PAUSE_EN_MSK;
1391 
1392 	return hclge_pfc_pause_en_cfg(hdev, enable_bitmap,
1393 				      hdev->tm_info.pfc_en);
1394 }
1395 
1396 /* for the queues that use for backpress, divides to several groups,
1397  * each group contains 32 queue sets, which can be represented by u32 bitmap.
1398  */
1399 static int hclge_bp_setup_hw(struct hclge_dev *hdev, u8 tc)
1400 {
1401 	u16 grp_id_shift = HCLGE_BP_GRP_ID_S;
1402 	u16 grp_id_mask = HCLGE_BP_GRP_ID_M;
1403 	u8 grp_num = HCLGE_BP_GRP_NUM;
1404 	int i;
1405 
1406 	if (hdev->num_tqps > HCLGE_TQP_MAX_SIZE_DEV_V2) {
1407 		grp_num = HCLGE_BP_EXT_GRP_NUM;
1408 		grp_id_mask = HCLGE_BP_EXT_GRP_ID_M;
1409 		grp_id_shift = HCLGE_BP_EXT_GRP_ID_S;
1410 	}
1411 
1412 	for (i = 0; i < grp_num; i++) {
1413 		u32 qs_bitmap = 0;
1414 		int k, ret;
1415 
1416 		for (k = 0; k < hdev->num_alloc_vport; k++) {
1417 			struct hclge_vport *vport = &hdev->vport[k];
1418 			u16 qs_id = vport->qs_offset + tc;
1419 			u8 grp, sub_grp;
1420 
1421 			grp = hnae3_get_field(qs_id, grp_id_mask, grp_id_shift);
1422 			sub_grp = hnae3_get_field(qs_id, HCLGE_BP_SUB_GRP_ID_M,
1423 						  HCLGE_BP_SUB_GRP_ID_S);
1424 			if (i == grp)
1425 				qs_bitmap |= (1 << sub_grp);
1426 		}
1427 
1428 		ret = hclge_tm_qs_bp_cfg(hdev, tc, i, qs_bitmap);
1429 		if (ret)
1430 			return ret;
1431 	}
1432 
1433 	return 0;
1434 }
1435 
1436 static int hclge_mac_pause_setup_hw(struct hclge_dev *hdev)
1437 {
1438 	bool tx_en, rx_en;
1439 
1440 	switch (hdev->tm_info.fc_mode) {
1441 	case HCLGE_FC_NONE:
1442 		tx_en = false;
1443 		rx_en = false;
1444 		break;
1445 	case HCLGE_FC_RX_PAUSE:
1446 		tx_en = false;
1447 		rx_en = true;
1448 		break;
1449 	case HCLGE_FC_TX_PAUSE:
1450 		tx_en = true;
1451 		rx_en = false;
1452 		break;
1453 	case HCLGE_FC_FULL:
1454 		tx_en = true;
1455 		rx_en = true;
1456 		break;
1457 	case HCLGE_FC_PFC:
1458 		tx_en = false;
1459 		rx_en = false;
1460 		break;
1461 	default:
1462 		tx_en = true;
1463 		rx_en = true;
1464 	}
1465 
1466 	return hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
1467 }
1468 
1469 static int hclge_tm_bp_setup(struct hclge_dev *hdev)
1470 {
1471 	int ret;
1472 	int i;
1473 
1474 	for (i = 0; i < hdev->tm_info.num_tc; i++) {
1475 		ret = hclge_bp_setup_hw(hdev, i);
1476 		if (ret)
1477 			return ret;
1478 	}
1479 
1480 	return 0;
1481 }
1482 
1483 int hclge_pause_setup_hw(struct hclge_dev *hdev, bool init)
1484 {
1485 	int ret;
1486 
1487 	ret = hclge_pause_param_setup_hw(hdev);
1488 	if (ret)
1489 		return ret;
1490 
1491 	ret = hclge_mac_pause_setup_hw(hdev);
1492 	if (ret)
1493 		return ret;
1494 
1495 	/* Only DCB-supported dev supports qset back pressure and pfc cmd */
1496 	if (!hnae3_dev_dcb_supported(hdev))
1497 		return 0;
1498 
1499 	/* GE MAC does not support PFC, when driver is initializing and MAC
1500 	 * is in GE Mode, ignore the error here, otherwise initialization
1501 	 * will fail.
1502 	 */
1503 	ret = hclge_pfc_setup_hw(hdev);
1504 	if (init && ret == -EOPNOTSUPP)
1505 		dev_warn(&hdev->pdev->dev, "GE MAC does not support pfc\n");
1506 	else if (ret) {
1507 		dev_err(&hdev->pdev->dev, "config pfc failed! ret = %d\n",
1508 			ret);
1509 		return ret;
1510 	}
1511 
1512 	return hclge_tm_bp_setup(hdev);
1513 }
1514 
1515 void hclge_tm_prio_tc_info_update(struct hclge_dev *hdev, u8 *prio_tc)
1516 {
1517 	struct hclge_vport *vport = hdev->vport;
1518 	struct hnae3_knic_private_info *kinfo;
1519 	u32 i, k;
1520 
1521 	for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
1522 		hdev->tm_info.prio_tc[i] = prio_tc[i];
1523 
1524 		for (k = 0;  k < hdev->num_alloc_vport; k++) {
1525 			kinfo = &vport[k].nic.kinfo;
1526 			kinfo->tc_info.prio_tc[i] = prio_tc[i];
1527 		}
1528 	}
1529 }
1530 
1531 void hclge_tm_schd_info_update(struct hclge_dev *hdev, u8 num_tc)
1532 {
1533 	u8 bit_map = 0;
1534 	u8 i;
1535 
1536 	hdev->tm_info.num_tc = num_tc;
1537 
1538 	for (i = 0; i < hdev->tm_info.num_tc; i++)
1539 		bit_map |= BIT(i);
1540 
1541 	if (!bit_map) {
1542 		bit_map = 1;
1543 		hdev->tm_info.num_tc = 1;
1544 	}
1545 
1546 	hdev->hw_tc_map = bit_map;
1547 
1548 	hclge_tm_schd_info_init(hdev);
1549 }
1550 
1551 int hclge_tm_init_hw(struct hclge_dev *hdev, bool init)
1552 {
1553 	int ret;
1554 
1555 	if ((hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) &&
1556 	    (hdev->tx_sch_mode != HCLGE_FLAG_VNET_BASE_SCH_MODE))
1557 		return -ENOTSUPP;
1558 
1559 	ret = hclge_tm_schd_setup_hw(hdev);
1560 	if (ret)
1561 		return ret;
1562 
1563 	ret = hclge_pause_setup_hw(hdev, init);
1564 	if (ret)
1565 		return ret;
1566 
1567 	return 0;
1568 }
1569 
1570 int hclge_tm_schd_init(struct hclge_dev *hdev)
1571 {
1572 	/* fc_mode is HCLGE_FC_FULL on reset */
1573 	hdev->tm_info.fc_mode = HCLGE_FC_FULL;
1574 	hdev->fc_mode_last_time = hdev->tm_info.fc_mode;
1575 
1576 	if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE &&
1577 	    hdev->tm_info.num_pg != 1)
1578 		return -EINVAL;
1579 
1580 	hclge_tm_schd_info_init(hdev);
1581 
1582 	return hclge_tm_init_hw(hdev, true);
1583 }
1584 
1585 int hclge_tm_vport_map_update(struct hclge_dev *hdev)
1586 {
1587 	struct hclge_vport *vport = hdev->vport;
1588 	int ret;
1589 
1590 	hclge_tm_vport_tc_info_update(vport);
1591 
1592 	ret = hclge_vport_q_to_qs_map(hdev, vport);
1593 	if (ret)
1594 		return ret;
1595 
1596 	if (hdev->tm_info.num_tc == 1 && !hdev->tm_info.pfc_en)
1597 		return 0;
1598 
1599 	return hclge_tm_bp_setup(hdev);
1600 }
1601 
1602 int hclge_tm_get_qset_num(struct hclge_dev *hdev, u16 *qset_num)
1603 {
1604 	struct hclge_tm_nodes_cmd *nodes;
1605 	struct hclge_desc desc;
1606 	int ret;
1607 
1608 	if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) {
1609 		/* Each PF has 8 qsets and each VF has 1 qset */
1610 		*qset_num = HCLGE_TM_PF_MAX_QSET_NUM + pci_num_vf(hdev->pdev);
1611 		return 0;
1612 	}
1613 
1614 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_NODES, true);
1615 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1616 	if (ret) {
1617 		dev_err(&hdev->pdev->dev,
1618 			"failed to get qset num, ret = %d\n", ret);
1619 		return ret;
1620 	}
1621 
1622 	nodes = (struct hclge_tm_nodes_cmd *)desc.data;
1623 	*qset_num = le16_to_cpu(nodes->qset_num);
1624 	return 0;
1625 }
1626 
1627 int hclge_tm_get_pri_num(struct hclge_dev *hdev, u8 *pri_num)
1628 {
1629 	struct hclge_tm_nodes_cmd *nodes;
1630 	struct hclge_desc desc;
1631 	int ret;
1632 
1633 	if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) {
1634 		*pri_num = HCLGE_TM_PF_MAX_PRI_NUM;
1635 		return 0;
1636 	}
1637 
1638 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_NODES, true);
1639 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1640 	if (ret) {
1641 		dev_err(&hdev->pdev->dev,
1642 			"failed to get pri num, ret = %d\n", ret);
1643 		return ret;
1644 	}
1645 
1646 	nodes = (struct hclge_tm_nodes_cmd *)desc.data;
1647 	*pri_num = nodes->pri_num;
1648 	return 0;
1649 }
1650 
1651 int hclge_tm_get_qset_map_pri(struct hclge_dev *hdev, u16 qset_id, u8 *priority,
1652 			      u8 *link_vld)
1653 {
1654 	struct hclge_qs_to_pri_link_cmd *map;
1655 	struct hclge_desc desc;
1656 	int ret;
1657 
1658 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_TO_PRI_LINK, true);
1659 	map = (struct hclge_qs_to_pri_link_cmd *)desc.data;
1660 	map->qs_id = cpu_to_le16(qset_id);
1661 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1662 	if (ret) {
1663 		dev_err(&hdev->pdev->dev,
1664 			"failed to get qset map priority, ret = %d\n", ret);
1665 		return ret;
1666 	}
1667 
1668 	*priority = map->priority;
1669 	*link_vld = map->link_vld;
1670 	return 0;
1671 }
1672 
1673 int hclge_tm_get_qset_sch_mode(struct hclge_dev *hdev, u16 qset_id, u8 *mode)
1674 {
1675 	struct hclge_qs_sch_mode_cfg_cmd *qs_sch_mode;
1676 	struct hclge_desc desc;
1677 	int ret;
1678 
1679 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_SCH_MODE_CFG, true);
1680 	qs_sch_mode = (struct hclge_qs_sch_mode_cfg_cmd *)desc.data;
1681 	qs_sch_mode->qs_id = cpu_to_le16(qset_id);
1682 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1683 	if (ret) {
1684 		dev_err(&hdev->pdev->dev,
1685 			"failed to get qset sch mode, ret = %d\n", ret);
1686 		return ret;
1687 	}
1688 
1689 	*mode = qs_sch_mode->sch_mode;
1690 	return 0;
1691 }
1692 
1693 int hclge_tm_get_qset_weight(struct hclge_dev *hdev, u16 qset_id, u8 *weight)
1694 {
1695 	struct hclge_qs_weight_cmd *qs_weight;
1696 	struct hclge_desc desc;
1697 	int ret;
1698 
1699 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_WEIGHT, true);
1700 	qs_weight = (struct hclge_qs_weight_cmd *)desc.data;
1701 	qs_weight->qs_id = cpu_to_le16(qset_id);
1702 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1703 	if (ret) {
1704 		dev_err(&hdev->pdev->dev,
1705 			"failed to get qset weight, ret = %d\n", ret);
1706 		return ret;
1707 	}
1708 
1709 	*weight = qs_weight->dwrr;
1710 	return 0;
1711 }
1712 
1713 int hclge_tm_get_qset_shaper(struct hclge_dev *hdev, u16 qset_id,
1714 			     struct hclge_tm_shaper_para *para)
1715 {
1716 	struct hclge_qs_shapping_cmd *shap_cfg_cmd;
1717 	struct hclge_desc desc;
1718 	u32 shapping_para;
1719 	int ret;
1720 
1721 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QCN_SHAPPING_CFG, true);
1722 	shap_cfg_cmd = (struct hclge_qs_shapping_cmd *)desc.data;
1723 	shap_cfg_cmd->qs_id = cpu_to_le16(qset_id);
1724 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1725 	if (ret) {
1726 		dev_err(&hdev->pdev->dev,
1727 			"failed to get qset %u shaper, ret = %d\n", qset_id,
1728 			ret);
1729 		return ret;
1730 	}
1731 
1732 	shapping_para = le32_to_cpu(shap_cfg_cmd->qs_shapping_para);
1733 	para->ir_b = hclge_tm_get_field(shapping_para, IR_B);
1734 	para->ir_u = hclge_tm_get_field(shapping_para, IR_U);
1735 	para->ir_s = hclge_tm_get_field(shapping_para, IR_S);
1736 	para->bs_b = hclge_tm_get_field(shapping_para, BS_B);
1737 	para->bs_s = hclge_tm_get_field(shapping_para, BS_S);
1738 	para->flag = shap_cfg_cmd->flag;
1739 	para->rate = le32_to_cpu(shap_cfg_cmd->qs_rate);
1740 	return 0;
1741 }
1742 
1743 int hclge_tm_get_pri_sch_mode(struct hclge_dev *hdev, u8 pri_id, u8 *mode)
1744 {
1745 	struct hclge_pri_sch_mode_cfg_cmd *pri_sch_mode;
1746 	struct hclge_desc desc;
1747 	int ret;
1748 
1749 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_SCH_MODE_CFG, true);
1750 	pri_sch_mode = (struct hclge_pri_sch_mode_cfg_cmd *)desc.data;
1751 	pri_sch_mode->pri_id = pri_id;
1752 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1753 	if (ret) {
1754 		dev_err(&hdev->pdev->dev,
1755 			"failed to get priority sch mode, ret = %d\n", ret);
1756 		return ret;
1757 	}
1758 
1759 	*mode = pri_sch_mode->sch_mode;
1760 	return 0;
1761 }
1762 
1763 int hclge_tm_get_pri_weight(struct hclge_dev *hdev, u8 pri_id, u8 *weight)
1764 {
1765 	struct hclge_priority_weight_cmd *priority_weight;
1766 	struct hclge_desc desc;
1767 	int ret;
1768 
1769 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_WEIGHT, true);
1770 	priority_weight = (struct hclge_priority_weight_cmd *)desc.data;
1771 	priority_weight->pri_id = pri_id;
1772 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1773 	if (ret) {
1774 		dev_err(&hdev->pdev->dev,
1775 			"failed to get priority weight, ret = %d\n", ret);
1776 		return ret;
1777 	}
1778 
1779 	*weight = priority_weight->dwrr;
1780 	return 0;
1781 }
1782 
1783 int hclge_tm_get_pri_shaper(struct hclge_dev *hdev, u8 pri_id,
1784 			    enum hclge_opcode_type cmd,
1785 			    struct hclge_tm_shaper_para *para)
1786 {
1787 	struct hclge_pri_shapping_cmd *shap_cfg_cmd;
1788 	struct hclge_desc desc;
1789 	u32 shapping_para;
1790 	int ret;
1791 
1792 	if (cmd != HCLGE_OPC_TM_PRI_C_SHAPPING &&
1793 	    cmd != HCLGE_OPC_TM_PRI_P_SHAPPING)
1794 		return -EINVAL;
1795 
1796 	hclge_cmd_setup_basic_desc(&desc, cmd, true);
1797 	shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data;
1798 	shap_cfg_cmd->pri_id = pri_id;
1799 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1800 	if (ret) {
1801 		dev_err(&hdev->pdev->dev,
1802 			"failed to get priority shaper(%#x), ret = %d\n",
1803 			cmd, ret);
1804 		return ret;
1805 	}
1806 
1807 	shapping_para = le32_to_cpu(shap_cfg_cmd->pri_shapping_para);
1808 	para->ir_b = hclge_tm_get_field(shapping_para, IR_B);
1809 	para->ir_u = hclge_tm_get_field(shapping_para, IR_U);
1810 	para->ir_s = hclge_tm_get_field(shapping_para, IR_S);
1811 	para->bs_b = hclge_tm_get_field(shapping_para, BS_B);
1812 	para->bs_s = hclge_tm_get_field(shapping_para, BS_S);
1813 	para->flag = shap_cfg_cmd->flag;
1814 	para->rate = le32_to_cpu(shap_cfg_cmd->pri_rate);
1815 	return 0;
1816 }
1817 
1818 int hclge_tm_get_q_to_qs_map(struct hclge_dev *hdev, u16 q_id, u16 *qset_id)
1819 {
1820 	struct hclge_nq_to_qs_link_cmd *map;
1821 	struct hclge_desc desc;
1822 	u16 qs_id_l;
1823 	u16 qs_id_h;
1824 	int ret;
1825 
1826 	map = (struct hclge_nq_to_qs_link_cmd *)desc.data;
1827 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_NQ_TO_QS_LINK, true);
1828 	map->nq_id = cpu_to_le16(q_id);
1829 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1830 	if (ret) {
1831 		dev_err(&hdev->pdev->dev,
1832 			"failed to get queue to qset map, ret = %d\n", ret);
1833 		return ret;
1834 	}
1835 	*qset_id = le16_to_cpu(map->qset_id);
1836 
1837 	/* convert qset_id to the following format, drop the vld bit
1838 	 *            | qs_id_h | vld | qs_id_l |
1839 	 * qset_id:   | 15 ~ 11 |  10 |  9 ~ 0  |
1840 	 *             \         \   /         /
1841 	 *              \         \ /         /
1842 	 * qset_id: | 15 | 14 ~ 10 |  9 ~ 0  |
1843 	 */
1844 	qs_id_l = hnae3_get_field(*qset_id, HCLGE_TM_QS_ID_L_MSK,
1845 				  HCLGE_TM_QS_ID_L_S);
1846 	qs_id_h = hnae3_get_field(*qset_id, HCLGE_TM_QS_ID_H_EXT_MSK,
1847 				  HCLGE_TM_QS_ID_H_EXT_S);
1848 	*qset_id = 0;
1849 	hnae3_set_field(*qset_id, HCLGE_TM_QS_ID_L_MSK, HCLGE_TM_QS_ID_L_S,
1850 			qs_id_l);
1851 	hnae3_set_field(*qset_id, HCLGE_TM_QS_ID_H_MSK, HCLGE_TM_QS_ID_H_S,
1852 			qs_id_h);
1853 	return 0;
1854 }
1855 
1856 int hclge_tm_get_q_to_tc(struct hclge_dev *hdev, u16 q_id, u8 *tc_id)
1857 {
1858 #define HCLGE_TM_TC_MASK		0x7
1859 
1860 	struct hclge_tqp_tx_queue_tc_cmd *tc;
1861 	struct hclge_desc desc;
1862 	int ret;
1863 
1864 	tc = (struct hclge_tqp_tx_queue_tc_cmd *)desc.data;
1865 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TQP_TX_QUEUE_TC, true);
1866 	tc->queue_id = cpu_to_le16(q_id);
1867 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1868 	if (ret) {
1869 		dev_err(&hdev->pdev->dev,
1870 			"failed to get queue to tc map, ret = %d\n", ret);
1871 		return ret;
1872 	}
1873 
1874 	*tc_id = tc->tc_id & HCLGE_TM_TC_MASK;
1875 	return 0;
1876 }
1877 
1878 int hclge_tm_get_pg_to_pri_map(struct hclge_dev *hdev, u8 pg_id,
1879 			       u8 *pri_bit_map)
1880 {
1881 	struct hclge_pg_to_pri_link_cmd *map;
1882 	struct hclge_desc desc;
1883 	int ret;
1884 
1885 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_TO_PRI_LINK, true);
1886 	map = (struct hclge_pg_to_pri_link_cmd *)desc.data;
1887 	map->pg_id = pg_id;
1888 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1889 	if (ret) {
1890 		dev_err(&hdev->pdev->dev,
1891 			"failed to get pg to pri map, ret = %d\n", ret);
1892 		return ret;
1893 	}
1894 
1895 	*pri_bit_map = map->pri_bit_map;
1896 	return 0;
1897 }
1898 
1899 int hclge_tm_get_pg_weight(struct hclge_dev *hdev, u8 pg_id, u8 *weight)
1900 {
1901 	struct hclge_pg_weight_cmd *pg_weight_cmd;
1902 	struct hclge_desc desc;
1903 	int ret;
1904 
1905 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_WEIGHT, true);
1906 	pg_weight_cmd = (struct hclge_pg_weight_cmd *)desc.data;
1907 	pg_weight_cmd->pg_id = pg_id;
1908 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1909 	if (ret) {
1910 		dev_err(&hdev->pdev->dev,
1911 			"failed to get pg weight, ret = %d\n", ret);
1912 		return ret;
1913 	}
1914 
1915 	*weight = pg_weight_cmd->dwrr;
1916 	return 0;
1917 }
1918 
1919 int hclge_tm_get_pg_sch_mode(struct hclge_dev *hdev, u8 pg_id, u8 *mode)
1920 {
1921 	struct hclge_desc desc;
1922 	int ret;
1923 
1924 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_SCH_MODE_CFG, true);
1925 	desc.data[0] = cpu_to_le32(pg_id);
1926 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1927 	if (ret) {
1928 		dev_err(&hdev->pdev->dev,
1929 			"failed to get pg sch mode, ret = %d\n", ret);
1930 		return ret;
1931 	}
1932 
1933 	*mode = (u8)le32_to_cpu(desc.data[1]);
1934 	return 0;
1935 }
1936 
1937 int hclge_tm_get_pg_shaper(struct hclge_dev *hdev, u8 pg_id,
1938 			   enum hclge_opcode_type cmd,
1939 			   struct hclge_tm_shaper_para *para)
1940 {
1941 	struct hclge_pg_shapping_cmd *shap_cfg_cmd;
1942 	struct hclge_desc desc;
1943 	u32 shapping_para;
1944 	int ret;
1945 
1946 	if (cmd != HCLGE_OPC_TM_PG_C_SHAPPING &&
1947 	    cmd != HCLGE_OPC_TM_PG_P_SHAPPING)
1948 		return -EINVAL;
1949 
1950 	hclge_cmd_setup_basic_desc(&desc, cmd, true);
1951 	shap_cfg_cmd = (struct hclge_pg_shapping_cmd *)desc.data;
1952 	shap_cfg_cmd->pg_id = pg_id;
1953 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1954 	if (ret) {
1955 		dev_err(&hdev->pdev->dev,
1956 			"failed to get pg shaper(%#x), ret = %d\n",
1957 			cmd, ret);
1958 		return ret;
1959 	}
1960 
1961 	shapping_para = le32_to_cpu(shap_cfg_cmd->pg_shapping_para);
1962 	para->ir_b = hclge_tm_get_field(shapping_para, IR_B);
1963 	para->ir_u = hclge_tm_get_field(shapping_para, IR_U);
1964 	para->ir_s = hclge_tm_get_field(shapping_para, IR_S);
1965 	para->bs_b = hclge_tm_get_field(shapping_para, BS_B);
1966 	para->bs_s = hclge_tm_get_field(shapping_para, BS_S);
1967 	para->flag = shap_cfg_cmd->flag;
1968 	para->rate = le32_to_cpu(shap_cfg_cmd->pg_rate);
1969 	return 0;
1970 }
1971 
1972 int hclge_tm_get_port_shaper(struct hclge_dev *hdev,
1973 			     struct hclge_tm_shaper_para *para)
1974 {
1975 	struct hclge_port_shapping_cmd *port_shap_cfg_cmd;
1976 	struct hclge_desc desc;
1977 	u32 shapping_para;
1978 	int ret;
1979 
1980 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PORT_SHAPPING, true);
1981 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1982 	if (ret) {
1983 		dev_err(&hdev->pdev->dev,
1984 			"failed to get port shaper, ret = %d\n", ret);
1985 		return ret;
1986 	}
1987 
1988 	port_shap_cfg_cmd = (struct hclge_port_shapping_cmd *)desc.data;
1989 	shapping_para = le32_to_cpu(port_shap_cfg_cmd->port_shapping_para);
1990 	para->ir_b = hclge_tm_get_field(shapping_para, IR_B);
1991 	para->ir_u = hclge_tm_get_field(shapping_para, IR_U);
1992 	para->ir_s = hclge_tm_get_field(shapping_para, IR_S);
1993 	para->bs_b = hclge_tm_get_field(shapping_para, BS_B);
1994 	para->bs_s = hclge_tm_get_field(shapping_para, BS_S);
1995 	para->flag = port_shap_cfg_cmd->flag;
1996 	para->rate = le32_to_cpu(port_shap_cfg_cmd->port_rate);
1997 
1998 	return 0;
1999 }
2000