1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 6 #include "hclge_cmd.h" 7 #include "hclge_main.h" 8 #include "hclge_tm.h" 9 10 enum hclge_shaper_level { 11 HCLGE_SHAPER_LVL_PRI = 0, 12 HCLGE_SHAPER_LVL_PG = 1, 13 HCLGE_SHAPER_LVL_PORT = 2, 14 HCLGE_SHAPER_LVL_QSET = 3, 15 HCLGE_SHAPER_LVL_CNT = 4, 16 HCLGE_SHAPER_LVL_VF = 0, 17 HCLGE_SHAPER_LVL_PF = 1, 18 }; 19 20 #define HCLGE_TM_PFC_PKT_GET_CMD_NUM 3 21 #define HCLGE_TM_PFC_NUM_GET_PER_CMD 3 22 23 #define HCLGE_SHAPER_BS_U_DEF 5 24 #define HCLGE_SHAPER_BS_S_DEF 20 25 26 #define HCLGE_ETHER_MAX_RATE 100000 27 28 /* hclge_shaper_para_calc: calculate ir parameter for the shaper 29 * @ir: Rate to be config, its unit is Mbps 30 * @shaper_level: the shaper level. eg: port, pg, priority, queueset 31 * @ir_b: IR_B parameter of IR shaper 32 * @ir_u: IR_U parameter of IR shaper 33 * @ir_s: IR_S parameter of IR shaper 34 * 35 * the formula: 36 * 37 * IR_b * (2 ^ IR_u) * 8 38 * IR(Mbps) = ------------------------- * CLOCK(1000Mbps) 39 * Tick * (2 ^ IR_s) 40 * 41 * @return: 0: calculate sucessful, negative: fail 42 */ 43 static int hclge_shaper_para_calc(u32 ir, u8 shaper_level, 44 u8 *ir_b, u8 *ir_u, u8 *ir_s) 45 { 46 const u16 tick_array[HCLGE_SHAPER_LVL_CNT] = { 47 6 * 256, /* Prioriy level */ 48 6 * 32, /* Prioriy group level */ 49 6 * 8, /* Port level */ 50 6 * 256 /* Qset level */ 51 }; 52 u8 ir_u_calc = 0, ir_s_calc = 0; 53 u32 ir_calc; 54 u32 tick; 55 56 /* Calc tick */ 57 if (shaper_level >= HCLGE_SHAPER_LVL_CNT) 58 return -EINVAL; 59 60 tick = tick_array[shaper_level]; 61 62 /** 63 * Calc the speed if ir_b = 126, ir_u = 0 and ir_s = 0 64 * the formula is changed to: 65 * 126 * 1 * 8 66 * ir_calc = ---------------- * 1000 67 * tick * 1 68 */ 69 ir_calc = (1008000 + (tick >> 1) - 1) / tick; 70 71 if (ir_calc == ir) { 72 *ir_b = 126; 73 *ir_u = 0; 74 *ir_s = 0; 75 76 return 0; 77 } else if (ir_calc > ir) { 78 /* Increasing the denominator to select ir_s value */ 79 while (ir_calc > ir) { 80 ir_s_calc++; 81 ir_calc = 1008000 / (tick * (1 << ir_s_calc)); 82 } 83 84 if (ir_calc == ir) 85 *ir_b = 126; 86 else 87 *ir_b = (ir * tick * (1 << ir_s_calc) + 4000) / 8000; 88 } else { 89 /* Increasing the numerator to select ir_u value */ 90 u32 numerator; 91 92 while (ir_calc < ir) { 93 ir_u_calc++; 94 numerator = 1008000 * (1 << ir_u_calc); 95 ir_calc = (numerator + (tick >> 1)) / tick; 96 } 97 98 if (ir_calc == ir) { 99 *ir_b = 126; 100 } else { 101 u32 denominator = (8000 * (1 << --ir_u_calc)); 102 *ir_b = (ir * tick + (denominator >> 1)) / denominator; 103 } 104 } 105 106 *ir_u = ir_u_calc; 107 *ir_s = ir_s_calc; 108 109 return 0; 110 } 111 112 static int hclge_pfc_stats_get(struct hclge_dev *hdev, 113 enum hclge_opcode_type opcode, u64 *stats) 114 { 115 struct hclge_desc desc[HCLGE_TM_PFC_PKT_GET_CMD_NUM]; 116 int ret, i, j; 117 118 if (!(opcode == HCLGE_OPC_QUERY_PFC_RX_PKT_CNT || 119 opcode == HCLGE_OPC_QUERY_PFC_TX_PKT_CNT)) 120 return -EINVAL; 121 122 for (i = 0; i < HCLGE_TM_PFC_PKT_GET_CMD_NUM; i++) { 123 hclge_cmd_setup_basic_desc(&desc[i], opcode, true); 124 if (i != (HCLGE_TM_PFC_PKT_GET_CMD_NUM - 1)) 125 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 126 else 127 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 128 } 129 130 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_TM_PFC_PKT_GET_CMD_NUM); 131 if (ret) 132 return ret; 133 134 for (i = 0; i < HCLGE_TM_PFC_PKT_GET_CMD_NUM; i++) { 135 struct hclge_pfc_stats_cmd *pfc_stats = 136 (struct hclge_pfc_stats_cmd *)desc[i].data; 137 138 for (j = 0; j < HCLGE_TM_PFC_NUM_GET_PER_CMD; j++) { 139 u32 index = i * HCLGE_TM_PFC_PKT_GET_CMD_NUM + j; 140 141 if (index < HCLGE_MAX_TC_NUM) 142 stats[index] = 143 le64_to_cpu(pfc_stats->pkt_num[j]); 144 } 145 } 146 return 0; 147 } 148 149 int hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats) 150 { 151 return hclge_pfc_stats_get(hdev, HCLGE_OPC_QUERY_PFC_RX_PKT_CNT, stats); 152 } 153 154 int hclge_pfc_tx_stats_get(struct hclge_dev *hdev, u64 *stats) 155 { 156 return hclge_pfc_stats_get(hdev, HCLGE_OPC_QUERY_PFC_TX_PKT_CNT, stats); 157 } 158 159 int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx) 160 { 161 struct hclge_desc desc; 162 163 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PAUSE_EN, false); 164 165 desc.data[0] = cpu_to_le32((tx ? HCLGE_TX_MAC_PAUSE_EN_MSK : 0) | 166 (rx ? HCLGE_RX_MAC_PAUSE_EN_MSK : 0)); 167 168 return hclge_cmd_send(&hdev->hw, &desc, 1); 169 } 170 171 static int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap, 172 u8 pfc_bitmap) 173 { 174 struct hclge_desc desc; 175 struct hclge_pfc_en_cmd *pfc = (struct hclge_pfc_en_cmd *)&desc.data; 176 177 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PFC_PAUSE_EN, false); 178 179 pfc->tx_rx_en_bitmap = tx_rx_bitmap; 180 pfc->pri_en_bitmap = pfc_bitmap; 181 182 return hclge_cmd_send(&hdev->hw, &desc, 1); 183 } 184 185 static int hclge_pause_param_cfg(struct hclge_dev *hdev, const u8 *addr, 186 u8 pause_trans_gap, u16 pause_trans_time) 187 { 188 struct hclge_cfg_pause_param_cmd *pause_param; 189 struct hclge_desc desc; 190 191 pause_param = (struct hclge_cfg_pause_param_cmd *)&desc.data; 192 193 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, false); 194 195 ether_addr_copy(pause_param->mac_addr, addr); 196 pause_param->pause_trans_gap = pause_trans_gap; 197 pause_param->pause_trans_time = cpu_to_le16(pause_trans_time); 198 199 return hclge_cmd_send(&hdev->hw, &desc, 1); 200 } 201 202 int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr) 203 { 204 struct hclge_cfg_pause_param_cmd *pause_param; 205 struct hclge_desc desc; 206 u16 trans_time; 207 u8 trans_gap; 208 int ret; 209 210 pause_param = (struct hclge_cfg_pause_param_cmd *)&desc.data; 211 212 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, true); 213 214 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 215 if (ret) 216 return ret; 217 218 trans_gap = pause_param->pause_trans_gap; 219 trans_time = le16_to_cpu(pause_param->pause_trans_time); 220 221 return hclge_pause_param_cfg(hdev, mac_addr, trans_gap, 222 trans_time); 223 } 224 225 static int hclge_fill_pri_array(struct hclge_dev *hdev, u8 *pri, u8 pri_id) 226 { 227 u8 tc; 228 229 tc = hdev->tm_info.prio_tc[pri_id]; 230 231 if (tc >= hdev->tm_info.num_tc) 232 return -EINVAL; 233 234 /** 235 * the register for priority has four bytes, the first bytes includes 236 * priority0 and priority1, the higher 4bit stands for priority1 237 * while the lower 4bit stands for priority0, as below: 238 * first byte: | pri_1 | pri_0 | 239 * second byte: | pri_3 | pri_2 | 240 * third byte: | pri_5 | pri_4 | 241 * fourth byte: | pri_7 | pri_6 | 242 */ 243 pri[pri_id >> 1] |= tc << ((pri_id & 1) * 4); 244 245 return 0; 246 } 247 248 static int hclge_up_to_tc_map(struct hclge_dev *hdev) 249 { 250 struct hclge_desc desc; 251 u8 *pri = (u8 *)desc.data; 252 u8 pri_id; 253 int ret; 254 255 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PRI_TO_TC_MAPPING, false); 256 257 for (pri_id = 0; pri_id < HNAE3_MAX_USER_PRIO; pri_id++) { 258 ret = hclge_fill_pri_array(hdev, pri, pri_id); 259 if (ret) 260 return ret; 261 } 262 263 return hclge_cmd_send(&hdev->hw, &desc, 1); 264 } 265 266 static int hclge_tm_pg_to_pri_map_cfg(struct hclge_dev *hdev, 267 u8 pg_id, u8 pri_bit_map) 268 { 269 struct hclge_pg_to_pri_link_cmd *map; 270 struct hclge_desc desc; 271 272 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_TO_PRI_LINK, false); 273 274 map = (struct hclge_pg_to_pri_link_cmd *)desc.data; 275 276 map->pg_id = pg_id; 277 map->pri_bit_map = pri_bit_map; 278 279 return hclge_cmd_send(&hdev->hw, &desc, 1); 280 } 281 282 static int hclge_tm_qs_to_pri_map_cfg(struct hclge_dev *hdev, 283 u16 qs_id, u8 pri) 284 { 285 struct hclge_qs_to_pri_link_cmd *map; 286 struct hclge_desc desc; 287 288 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_TO_PRI_LINK, false); 289 290 map = (struct hclge_qs_to_pri_link_cmd *)desc.data; 291 292 map->qs_id = cpu_to_le16(qs_id); 293 map->priority = pri; 294 map->link_vld = HCLGE_TM_QS_PRI_LINK_VLD_MSK; 295 296 return hclge_cmd_send(&hdev->hw, &desc, 1); 297 } 298 299 static int hclge_tm_q_to_qs_map_cfg(struct hclge_dev *hdev, 300 u8 q_id, u16 qs_id) 301 { 302 struct hclge_nq_to_qs_link_cmd *map; 303 struct hclge_desc desc; 304 305 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_NQ_TO_QS_LINK, false); 306 307 map = (struct hclge_nq_to_qs_link_cmd *)desc.data; 308 309 map->nq_id = cpu_to_le16(q_id); 310 map->qset_id = cpu_to_le16(qs_id | HCLGE_TM_Q_QS_LINK_VLD_MSK); 311 312 return hclge_cmd_send(&hdev->hw, &desc, 1); 313 } 314 315 static int hclge_tm_pg_weight_cfg(struct hclge_dev *hdev, u8 pg_id, 316 u8 dwrr) 317 { 318 struct hclge_pg_weight_cmd *weight; 319 struct hclge_desc desc; 320 321 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_WEIGHT, false); 322 323 weight = (struct hclge_pg_weight_cmd *)desc.data; 324 325 weight->pg_id = pg_id; 326 weight->dwrr = dwrr; 327 328 return hclge_cmd_send(&hdev->hw, &desc, 1); 329 } 330 331 static int hclge_tm_pri_weight_cfg(struct hclge_dev *hdev, u8 pri_id, 332 u8 dwrr) 333 { 334 struct hclge_priority_weight_cmd *weight; 335 struct hclge_desc desc; 336 337 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_WEIGHT, false); 338 339 weight = (struct hclge_priority_weight_cmd *)desc.data; 340 341 weight->pri_id = pri_id; 342 weight->dwrr = dwrr; 343 344 return hclge_cmd_send(&hdev->hw, &desc, 1); 345 } 346 347 static int hclge_tm_qs_weight_cfg(struct hclge_dev *hdev, u16 qs_id, 348 u8 dwrr) 349 { 350 struct hclge_qs_weight_cmd *weight; 351 struct hclge_desc desc; 352 353 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_WEIGHT, false); 354 355 weight = (struct hclge_qs_weight_cmd *)desc.data; 356 357 weight->qs_id = cpu_to_le16(qs_id); 358 weight->dwrr = dwrr; 359 360 return hclge_cmd_send(&hdev->hw, &desc, 1); 361 } 362 363 static int hclge_tm_pg_shapping_cfg(struct hclge_dev *hdev, 364 enum hclge_shap_bucket bucket, u8 pg_id, 365 u8 ir_b, u8 ir_u, u8 ir_s, u8 bs_b, u8 bs_s) 366 { 367 struct hclge_pg_shapping_cmd *shap_cfg_cmd; 368 enum hclge_opcode_type opcode; 369 struct hclge_desc desc; 370 u32 shapping_para = 0; 371 372 opcode = bucket ? HCLGE_OPC_TM_PG_P_SHAPPING : 373 HCLGE_OPC_TM_PG_C_SHAPPING; 374 hclge_cmd_setup_basic_desc(&desc, opcode, false); 375 376 shap_cfg_cmd = (struct hclge_pg_shapping_cmd *)desc.data; 377 378 shap_cfg_cmd->pg_id = pg_id; 379 380 hclge_tm_set_field(shapping_para, IR_B, ir_b); 381 hclge_tm_set_field(shapping_para, IR_U, ir_u); 382 hclge_tm_set_field(shapping_para, IR_S, ir_s); 383 hclge_tm_set_field(shapping_para, BS_B, bs_b); 384 hclge_tm_set_field(shapping_para, BS_S, bs_s); 385 386 shap_cfg_cmd->pg_shapping_para = cpu_to_le32(shapping_para); 387 388 return hclge_cmd_send(&hdev->hw, &desc, 1); 389 } 390 391 static int hclge_tm_port_shaper_cfg(struct hclge_dev *hdev) 392 { 393 struct hclge_port_shapping_cmd *shap_cfg_cmd; 394 struct hclge_desc desc; 395 u32 shapping_para = 0; 396 u8 ir_u, ir_b, ir_s; 397 int ret; 398 399 ret = hclge_shaper_para_calc(HCLGE_ETHER_MAX_RATE, 400 HCLGE_SHAPER_LVL_PORT, 401 &ir_b, &ir_u, &ir_s); 402 if (ret) 403 return ret; 404 405 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PORT_SHAPPING, false); 406 shap_cfg_cmd = (struct hclge_port_shapping_cmd *)desc.data; 407 408 hclge_tm_set_field(shapping_para, IR_B, ir_b); 409 hclge_tm_set_field(shapping_para, IR_U, ir_u); 410 hclge_tm_set_field(shapping_para, IR_S, ir_s); 411 hclge_tm_set_field(shapping_para, BS_B, HCLGE_SHAPER_BS_U_DEF); 412 hclge_tm_set_field(shapping_para, BS_S, HCLGE_SHAPER_BS_S_DEF); 413 414 shap_cfg_cmd->port_shapping_para = cpu_to_le32(shapping_para); 415 416 return hclge_cmd_send(&hdev->hw, &desc, 1); 417 } 418 419 static int hclge_tm_pri_shapping_cfg(struct hclge_dev *hdev, 420 enum hclge_shap_bucket bucket, u8 pri_id, 421 u8 ir_b, u8 ir_u, u8 ir_s, 422 u8 bs_b, u8 bs_s) 423 { 424 struct hclge_pri_shapping_cmd *shap_cfg_cmd; 425 enum hclge_opcode_type opcode; 426 struct hclge_desc desc; 427 u32 shapping_para = 0; 428 429 opcode = bucket ? HCLGE_OPC_TM_PRI_P_SHAPPING : 430 HCLGE_OPC_TM_PRI_C_SHAPPING; 431 432 hclge_cmd_setup_basic_desc(&desc, opcode, false); 433 434 shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data; 435 436 shap_cfg_cmd->pri_id = pri_id; 437 438 hclge_tm_set_field(shapping_para, IR_B, ir_b); 439 hclge_tm_set_field(shapping_para, IR_U, ir_u); 440 hclge_tm_set_field(shapping_para, IR_S, ir_s); 441 hclge_tm_set_field(shapping_para, BS_B, bs_b); 442 hclge_tm_set_field(shapping_para, BS_S, bs_s); 443 444 shap_cfg_cmd->pri_shapping_para = cpu_to_le32(shapping_para); 445 446 return hclge_cmd_send(&hdev->hw, &desc, 1); 447 } 448 449 static int hclge_tm_pg_schd_mode_cfg(struct hclge_dev *hdev, u8 pg_id) 450 { 451 struct hclge_desc desc; 452 453 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_SCH_MODE_CFG, false); 454 455 if (hdev->tm_info.pg_info[pg_id].pg_sch_mode == HCLGE_SCH_MODE_DWRR) 456 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK); 457 else 458 desc.data[1] = 0; 459 460 desc.data[0] = cpu_to_le32(pg_id); 461 462 return hclge_cmd_send(&hdev->hw, &desc, 1); 463 } 464 465 static int hclge_tm_pri_schd_mode_cfg(struct hclge_dev *hdev, u8 pri_id) 466 { 467 struct hclge_desc desc; 468 469 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_SCH_MODE_CFG, false); 470 471 if (hdev->tm_info.tc_info[pri_id].tc_sch_mode == HCLGE_SCH_MODE_DWRR) 472 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK); 473 else 474 desc.data[1] = 0; 475 476 desc.data[0] = cpu_to_le32(pri_id); 477 478 return hclge_cmd_send(&hdev->hw, &desc, 1); 479 } 480 481 static int hclge_tm_qs_schd_mode_cfg(struct hclge_dev *hdev, u16 qs_id, u8 mode) 482 { 483 struct hclge_desc desc; 484 485 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_SCH_MODE_CFG, false); 486 487 if (mode == HCLGE_SCH_MODE_DWRR) 488 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK); 489 else 490 desc.data[1] = 0; 491 492 desc.data[0] = cpu_to_le32(qs_id); 493 494 return hclge_cmd_send(&hdev->hw, &desc, 1); 495 } 496 497 static int hclge_tm_qs_bp_cfg(struct hclge_dev *hdev, u8 tc, u8 grp_id, 498 u32 bit_map) 499 { 500 struct hclge_bp_to_qs_map_cmd *bp_to_qs_map_cmd; 501 struct hclge_desc desc; 502 503 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_BP_TO_QSET_MAPPING, 504 false); 505 506 bp_to_qs_map_cmd = (struct hclge_bp_to_qs_map_cmd *)desc.data; 507 508 bp_to_qs_map_cmd->tc_id = tc; 509 bp_to_qs_map_cmd->qs_group_id = grp_id; 510 bp_to_qs_map_cmd->qs_bit_map = cpu_to_le32(bit_map); 511 512 return hclge_cmd_send(&hdev->hw, &desc, 1); 513 } 514 515 static void hclge_tm_vport_tc_info_update(struct hclge_vport *vport) 516 { 517 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 518 struct hclge_dev *hdev = vport->back; 519 u8 i; 520 521 vport->bw_limit = hdev->tm_info.pg_info[0].bw_limit; 522 kinfo->num_tc = 523 min_t(u16, kinfo->num_tqps, hdev->tm_info.num_tc); 524 kinfo->rss_size 525 = min_t(u16, hdev->rss_size_max, 526 kinfo->num_tqps / kinfo->num_tc); 527 vport->qs_offset = hdev->tm_info.num_tc * vport->vport_id; 528 vport->dwrr = 100; /* 100 percent as init */ 529 vport->alloc_rss_size = kinfo->rss_size; 530 531 for (i = 0; i < kinfo->num_tc; i++) { 532 if (hdev->hw_tc_map & BIT(i)) { 533 kinfo->tc_info[i].enable = true; 534 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size; 535 kinfo->tc_info[i].tqp_count = kinfo->rss_size; 536 kinfo->tc_info[i].tc = i; 537 } else { 538 /* Set to default queue if TC is disable */ 539 kinfo->tc_info[i].enable = false; 540 kinfo->tc_info[i].tqp_offset = 0; 541 kinfo->tc_info[i].tqp_count = 1; 542 kinfo->tc_info[i].tc = 0; 543 } 544 } 545 546 memcpy(kinfo->prio_tc, hdev->tm_info.prio_tc, 547 FIELD_SIZEOF(struct hnae3_knic_private_info, prio_tc)); 548 } 549 550 static void hclge_tm_vport_info_update(struct hclge_dev *hdev) 551 { 552 struct hclge_vport *vport = hdev->vport; 553 u32 i; 554 555 for (i = 0; i < hdev->num_alloc_vport; i++) { 556 hclge_tm_vport_tc_info_update(vport); 557 558 vport++; 559 } 560 } 561 562 static void hclge_tm_tc_info_init(struct hclge_dev *hdev) 563 { 564 u8 i; 565 566 for (i = 0; i < hdev->tm_info.num_tc; i++) { 567 hdev->tm_info.tc_info[i].tc_id = i; 568 hdev->tm_info.tc_info[i].tc_sch_mode = HCLGE_SCH_MODE_DWRR; 569 hdev->tm_info.tc_info[i].pgid = 0; 570 hdev->tm_info.tc_info[i].bw_limit = 571 hdev->tm_info.pg_info[0].bw_limit; 572 } 573 574 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) 575 hdev->tm_info.prio_tc[i] = 576 (i >= hdev->tm_info.num_tc) ? 0 : i; 577 578 /* DCB is enabled if we have more than 1 TC */ 579 if (hdev->tm_info.num_tc > 1) 580 hdev->flag |= HCLGE_FLAG_DCB_ENABLE; 581 else 582 hdev->flag &= ~HCLGE_FLAG_DCB_ENABLE; 583 } 584 585 static void hclge_tm_pg_info_init(struct hclge_dev *hdev) 586 { 587 u8 i; 588 589 for (i = 0; i < hdev->tm_info.num_pg; i++) { 590 int k; 591 592 hdev->tm_info.pg_dwrr[i] = i ? 0 : 100; 593 594 hdev->tm_info.pg_info[i].pg_id = i; 595 hdev->tm_info.pg_info[i].pg_sch_mode = HCLGE_SCH_MODE_DWRR; 596 597 hdev->tm_info.pg_info[i].bw_limit = HCLGE_ETHER_MAX_RATE; 598 599 if (i != 0) 600 continue; 601 602 hdev->tm_info.pg_info[i].tc_bit_map = hdev->hw_tc_map; 603 for (k = 0; k < hdev->tm_info.num_tc; k++) 604 hdev->tm_info.pg_info[i].tc_dwrr[k] = 100; 605 } 606 } 607 608 static void hclge_pfc_info_init(struct hclge_dev *hdev) 609 { 610 if (!(hdev->flag & HCLGE_FLAG_DCB_ENABLE)) { 611 if (hdev->fc_mode_last_time == HCLGE_FC_PFC) 612 dev_warn(&hdev->pdev->dev, 613 "DCB is disable, but last mode is FC_PFC\n"); 614 615 hdev->tm_info.fc_mode = hdev->fc_mode_last_time; 616 } else if (hdev->tm_info.fc_mode != HCLGE_FC_PFC) { 617 /* fc_mode_last_time record the last fc_mode when 618 * DCB is enabled, so that fc_mode can be set to 619 * the correct value when DCB is disabled. 620 */ 621 hdev->fc_mode_last_time = hdev->tm_info.fc_mode; 622 hdev->tm_info.fc_mode = HCLGE_FC_PFC; 623 } 624 } 625 626 static int hclge_tm_schd_info_init(struct hclge_dev *hdev) 627 { 628 if ((hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) && 629 (hdev->tm_info.num_pg != 1)) 630 return -EINVAL; 631 632 hclge_tm_pg_info_init(hdev); 633 634 hclge_tm_tc_info_init(hdev); 635 636 hclge_tm_vport_info_update(hdev); 637 638 hclge_pfc_info_init(hdev); 639 640 return 0; 641 } 642 643 static int hclge_tm_pg_to_pri_map(struct hclge_dev *hdev) 644 { 645 int ret; 646 u32 i; 647 648 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) 649 return 0; 650 651 for (i = 0; i < hdev->tm_info.num_pg; i++) { 652 /* Cfg mapping */ 653 ret = hclge_tm_pg_to_pri_map_cfg( 654 hdev, i, hdev->tm_info.pg_info[i].tc_bit_map); 655 if (ret) 656 return ret; 657 } 658 659 return 0; 660 } 661 662 static int hclge_tm_pg_shaper_cfg(struct hclge_dev *hdev) 663 { 664 u8 ir_u, ir_b, ir_s; 665 int ret; 666 u32 i; 667 668 /* Cfg pg schd */ 669 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) 670 return 0; 671 672 /* Pg to pri */ 673 for (i = 0; i < hdev->tm_info.num_pg; i++) { 674 /* Calc shaper para */ 675 ret = hclge_shaper_para_calc( 676 hdev->tm_info.pg_info[i].bw_limit, 677 HCLGE_SHAPER_LVL_PG, 678 &ir_b, &ir_u, &ir_s); 679 if (ret) 680 return ret; 681 682 ret = hclge_tm_pg_shapping_cfg(hdev, 683 HCLGE_TM_SHAP_C_BUCKET, i, 684 0, 0, 0, HCLGE_SHAPER_BS_U_DEF, 685 HCLGE_SHAPER_BS_S_DEF); 686 if (ret) 687 return ret; 688 689 ret = hclge_tm_pg_shapping_cfg(hdev, 690 HCLGE_TM_SHAP_P_BUCKET, i, 691 ir_b, ir_u, ir_s, 692 HCLGE_SHAPER_BS_U_DEF, 693 HCLGE_SHAPER_BS_S_DEF); 694 if (ret) 695 return ret; 696 } 697 698 return 0; 699 } 700 701 static int hclge_tm_pg_dwrr_cfg(struct hclge_dev *hdev) 702 { 703 int ret; 704 u32 i; 705 706 /* cfg pg schd */ 707 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) 708 return 0; 709 710 /* pg to prio */ 711 for (i = 0; i < hdev->tm_info.num_pg; i++) { 712 /* Cfg dwrr */ 713 ret = hclge_tm_pg_weight_cfg(hdev, i, 714 hdev->tm_info.pg_dwrr[i]); 715 if (ret) 716 return ret; 717 } 718 719 return 0; 720 } 721 722 static int hclge_vport_q_to_qs_map(struct hclge_dev *hdev, 723 struct hclge_vport *vport) 724 { 725 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 726 struct hnae3_queue **tqp = kinfo->tqp; 727 struct hnae3_tc_info *v_tc_info; 728 u32 i, j; 729 int ret; 730 731 for (i = 0; i < kinfo->num_tc; i++) { 732 v_tc_info = &kinfo->tc_info[i]; 733 for (j = 0; j < v_tc_info->tqp_count; j++) { 734 struct hnae3_queue *q = tqp[v_tc_info->tqp_offset + j]; 735 736 ret = hclge_tm_q_to_qs_map_cfg(hdev, 737 hclge_get_queue_id(q), 738 vport->qs_offset + i); 739 if (ret) 740 return ret; 741 } 742 } 743 744 return 0; 745 } 746 747 static int hclge_tm_pri_q_qs_cfg(struct hclge_dev *hdev) 748 { 749 struct hclge_vport *vport = hdev->vport; 750 int ret; 751 u32 i, k; 752 753 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) { 754 /* Cfg qs -> pri mapping, one by one mapping */ 755 for (k = 0; k < hdev->num_alloc_vport; k++) 756 for (i = 0; i < hdev->tm_info.num_tc; i++) { 757 ret = hclge_tm_qs_to_pri_map_cfg( 758 hdev, vport[k].qs_offset + i, i); 759 if (ret) 760 return ret; 761 } 762 } else if (hdev->tx_sch_mode == HCLGE_FLAG_VNET_BASE_SCH_MODE) { 763 /* Cfg qs -> pri mapping, qs = tc, pri = vf, 8 qs -> 1 pri */ 764 for (k = 0; k < hdev->num_alloc_vport; k++) 765 for (i = 0; i < HNAE3_MAX_TC; i++) { 766 ret = hclge_tm_qs_to_pri_map_cfg( 767 hdev, vport[k].qs_offset + i, k); 768 if (ret) 769 return ret; 770 } 771 } else { 772 return -EINVAL; 773 } 774 775 /* Cfg q -> qs mapping */ 776 for (i = 0; i < hdev->num_alloc_vport; i++) { 777 ret = hclge_vport_q_to_qs_map(hdev, vport); 778 if (ret) 779 return ret; 780 781 vport++; 782 } 783 784 return 0; 785 } 786 787 static int hclge_tm_pri_tc_base_shaper_cfg(struct hclge_dev *hdev) 788 { 789 u8 ir_u, ir_b, ir_s; 790 int ret; 791 u32 i; 792 793 for (i = 0; i < hdev->tm_info.num_tc; i++) { 794 ret = hclge_shaper_para_calc( 795 hdev->tm_info.tc_info[i].bw_limit, 796 HCLGE_SHAPER_LVL_PRI, 797 &ir_b, &ir_u, &ir_s); 798 if (ret) 799 return ret; 800 801 ret = hclge_tm_pri_shapping_cfg( 802 hdev, HCLGE_TM_SHAP_C_BUCKET, i, 803 0, 0, 0, HCLGE_SHAPER_BS_U_DEF, 804 HCLGE_SHAPER_BS_S_DEF); 805 if (ret) 806 return ret; 807 808 ret = hclge_tm_pri_shapping_cfg( 809 hdev, HCLGE_TM_SHAP_P_BUCKET, i, 810 ir_b, ir_u, ir_s, HCLGE_SHAPER_BS_U_DEF, 811 HCLGE_SHAPER_BS_S_DEF); 812 if (ret) 813 return ret; 814 } 815 816 return 0; 817 } 818 819 static int hclge_tm_pri_vnet_base_shaper_pri_cfg(struct hclge_vport *vport) 820 { 821 struct hclge_dev *hdev = vport->back; 822 u8 ir_u, ir_b, ir_s; 823 int ret; 824 825 ret = hclge_shaper_para_calc(vport->bw_limit, HCLGE_SHAPER_LVL_VF, 826 &ir_b, &ir_u, &ir_s); 827 if (ret) 828 return ret; 829 830 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_C_BUCKET, 831 vport->vport_id, 832 0, 0, 0, HCLGE_SHAPER_BS_U_DEF, 833 HCLGE_SHAPER_BS_S_DEF); 834 if (ret) 835 return ret; 836 837 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_P_BUCKET, 838 vport->vport_id, 839 ir_b, ir_u, ir_s, 840 HCLGE_SHAPER_BS_U_DEF, 841 HCLGE_SHAPER_BS_S_DEF); 842 if (ret) 843 return ret; 844 845 return 0; 846 } 847 848 static int hclge_tm_pri_vnet_base_shaper_qs_cfg(struct hclge_vport *vport) 849 { 850 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 851 struct hclge_dev *hdev = vport->back; 852 u8 ir_u, ir_b, ir_s; 853 u32 i; 854 int ret; 855 856 for (i = 0; i < kinfo->num_tc; i++) { 857 ret = hclge_shaper_para_calc( 858 hdev->tm_info.tc_info[i].bw_limit, 859 HCLGE_SHAPER_LVL_QSET, 860 &ir_b, &ir_u, &ir_s); 861 if (ret) 862 return ret; 863 } 864 865 return 0; 866 } 867 868 static int hclge_tm_pri_vnet_base_shaper_cfg(struct hclge_dev *hdev) 869 { 870 struct hclge_vport *vport = hdev->vport; 871 int ret; 872 u32 i; 873 874 /* Need config vport shaper */ 875 for (i = 0; i < hdev->num_alloc_vport; i++) { 876 ret = hclge_tm_pri_vnet_base_shaper_pri_cfg(vport); 877 if (ret) 878 return ret; 879 880 ret = hclge_tm_pri_vnet_base_shaper_qs_cfg(vport); 881 if (ret) 882 return ret; 883 884 vport++; 885 } 886 887 return 0; 888 } 889 890 static int hclge_tm_pri_shaper_cfg(struct hclge_dev *hdev) 891 { 892 int ret; 893 894 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) { 895 ret = hclge_tm_pri_tc_base_shaper_cfg(hdev); 896 if (ret) 897 return ret; 898 } else { 899 ret = hclge_tm_pri_vnet_base_shaper_cfg(hdev); 900 if (ret) 901 return ret; 902 } 903 904 return 0; 905 } 906 907 static int hclge_tm_pri_tc_base_dwrr_cfg(struct hclge_dev *hdev) 908 { 909 struct hclge_vport *vport = hdev->vport; 910 struct hclge_pg_info *pg_info; 911 u8 dwrr; 912 int ret; 913 u32 i, k; 914 915 for (i = 0; i < hdev->tm_info.num_tc; i++) { 916 pg_info = 917 &hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid]; 918 dwrr = pg_info->tc_dwrr[i]; 919 920 ret = hclge_tm_pri_weight_cfg(hdev, i, dwrr); 921 if (ret) 922 return ret; 923 924 for (k = 0; k < hdev->num_alloc_vport; k++) { 925 ret = hclge_tm_qs_weight_cfg( 926 hdev, vport[k].qs_offset + i, 927 vport[k].dwrr); 928 if (ret) 929 return ret; 930 } 931 } 932 933 return 0; 934 } 935 936 static int hclge_tm_pri_vnet_base_dwrr_pri_cfg(struct hclge_vport *vport) 937 { 938 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 939 struct hclge_dev *hdev = vport->back; 940 int ret; 941 u8 i; 942 943 /* Vf dwrr */ 944 ret = hclge_tm_pri_weight_cfg(hdev, vport->vport_id, vport->dwrr); 945 if (ret) 946 return ret; 947 948 /* Qset dwrr */ 949 for (i = 0; i < kinfo->num_tc; i++) { 950 ret = hclge_tm_qs_weight_cfg( 951 hdev, vport->qs_offset + i, 952 hdev->tm_info.pg_info[0].tc_dwrr[i]); 953 if (ret) 954 return ret; 955 } 956 957 return 0; 958 } 959 960 static int hclge_tm_pri_vnet_base_dwrr_cfg(struct hclge_dev *hdev) 961 { 962 struct hclge_vport *vport = hdev->vport; 963 int ret; 964 u32 i; 965 966 for (i = 0; i < hdev->num_alloc_vport; i++) { 967 ret = hclge_tm_pri_vnet_base_dwrr_pri_cfg(vport); 968 if (ret) 969 return ret; 970 971 vport++; 972 } 973 974 return 0; 975 } 976 977 static int hclge_tm_pri_dwrr_cfg(struct hclge_dev *hdev) 978 { 979 int ret; 980 981 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) { 982 ret = hclge_tm_pri_tc_base_dwrr_cfg(hdev); 983 if (ret) 984 return ret; 985 } else { 986 ret = hclge_tm_pri_vnet_base_dwrr_cfg(hdev); 987 if (ret) 988 return ret; 989 } 990 991 return 0; 992 } 993 994 int hclge_tm_map_cfg(struct hclge_dev *hdev) 995 { 996 int ret; 997 998 ret = hclge_up_to_tc_map(hdev); 999 if (ret) 1000 return ret; 1001 1002 ret = hclge_tm_pg_to_pri_map(hdev); 1003 if (ret) 1004 return ret; 1005 1006 return hclge_tm_pri_q_qs_cfg(hdev); 1007 } 1008 1009 static int hclge_tm_shaper_cfg(struct hclge_dev *hdev) 1010 { 1011 int ret; 1012 1013 ret = hclge_tm_port_shaper_cfg(hdev); 1014 if (ret) 1015 return ret; 1016 1017 ret = hclge_tm_pg_shaper_cfg(hdev); 1018 if (ret) 1019 return ret; 1020 1021 return hclge_tm_pri_shaper_cfg(hdev); 1022 } 1023 1024 int hclge_tm_dwrr_cfg(struct hclge_dev *hdev) 1025 { 1026 int ret; 1027 1028 ret = hclge_tm_pg_dwrr_cfg(hdev); 1029 if (ret) 1030 return ret; 1031 1032 return hclge_tm_pri_dwrr_cfg(hdev); 1033 } 1034 1035 static int hclge_tm_lvl2_schd_mode_cfg(struct hclge_dev *hdev) 1036 { 1037 int ret; 1038 u8 i; 1039 1040 /* Only being config on TC-Based scheduler mode */ 1041 if (hdev->tx_sch_mode == HCLGE_FLAG_VNET_BASE_SCH_MODE) 1042 return 0; 1043 1044 for (i = 0; i < hdev->tm_info.num_pg; i++) { 1045 ret = hclge_tm_pg_schd_mode_cfg(hdev, i); 1046 if (ret) 1047 return ret; 1048 } 1049 1050 return 0; 1051 } 1052 1053 static int hclge_tm_schd_mode_vnet_base_cfg(struct hclge_vport *vport) 1054 { 1055 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 1056 struct hclge_dev *hdev = vport->back; 1057 int ret; 1058 u8 i; 1059 1060 ret = hclge_tm_pri_schd_mode_cfg(hdev, vport->vport_id); 1061 if (ret) 1062 return ret; 1063 1064 for (i = 0; i < kinfo->num_tc; i++) { 1065 u8 sch_mode = hdev->tm_info.tc_info[i].tc_sch_mode; 1066 1067 ret = hclge_tm_qs_schd_mode_cfg(hdev, vport->qs_offset + i, 1068 sch_mode); 1069 if (ret) 1070 return ret; 1071 } 1072 1073 return 0; 1074 } 1075 1076 static int hclge_tm_lvl34_schd_mode_cfg(struct hclge_dev *hdev) 1077 { 1078 struct hclge_vport *vport = hdev->vport; 1079 int ret; 1080 u8 i, k; 1081 1082 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) { 1083 for (i = 0; i < hdev->tm_info.num_tc; i++) { 1084 ret = hclge_tm_pri_schd_mode_cfg(hdev, i); 1085 if (ret) 1086 return ret; 1087 1088 for (k = 0; k < hdev->num_alloc_vport; k++) { 1089 ret = hclge_tm_qs_schd_mode_cfg( 1090 hdev, vport[k].qs_offset + i, 1091 HCLGE_SCH_MODE_DWRR); 1092 if (ret) 1093 return ret; 1094 } 1095 } 1096 } else { 1097 for (i = 0; i < hdev->num_alloc_vport; i++) { 1098 ret = hclge_tm_schd_mode_vnet_base_cfg(vport); 1099 if (ret) 1100 return ret; 1101 1102 vport++; 1103 } 1104 } 1105 1106 return 0; 1107 } 1108 1109 int hclge_tm_schd_mode_hw(struct hclge_dev *hdev) 1110 { 1111 int ret; 1112 1113 ret = hclge_tm_lvl2_schd_mode_cfg(hdev); 1114 if (ret) 1115 return ret; 1116 1117 return hclge_tm_lvl34_schd_mode_cfg(hdev); 1118 } 1119 1120 static int hclge_tm_schd_setup_hw(struct hclge_dev *hdev) 1121 { 1122 int ret; 1123 1124 /* Cfg tm mapping */ 1125 ret = hclge_tm_map_cfg(hdev); 1126 if (ret) 1127 return ret; 1128 1129 /* Cfg tm shaper */ 1130 ret = hclge_tm_shaper_cfg(hdev); 1131 if (ret) 1132 return ret; 1133 1134 /* Cfg dwrr */ 1135 ret = hclge_tm_dwrr_cfg(hdev); 1136 if (ret) 1137 return ret; 1138 1139 /* Cfg schd mode for each level schd */ 1140 return hclge_tm_schd_mode_hw(hdev); 1141 } 1142 1143 static int hclge_pause_param_setup_hw(struct hclge_dev *hdev) 1144 { 1145 struct hclge_mac *mac = &hdev->hw.mac; 1146 1147 return hclge_pause_param_cfg(hdev, mac->mac_addr, 1148 HCLGE_DEFAULT_PAUSE_TRANS_GAP, 1149 HCLGE_DEFAULT_PAUSE_TRANS_TIME); 1150 } 1151 1152 static int hclge_pfc_setup_hw(struct hclge_dev *hdev) 1153 { 1154 u8 enable_bitmap = 0; 1155 1156 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) 1157 enable_bitmap = HCLGE_TX_MAC_PAUSE_EN_MSK | 1158 HCLGE_RX_MAC_PAUSE_EN_MSK; 1159 1160 return hclge_pfc_pause_en_cfg(hdev, enable_bitmap, 1161 hdev->tm_info.hw_pfc_map); 1162 } 1163 1164 /* Each Tc has a 1024 queue sets to backpress, it divides to 1165 * 32 group, each group contains 32 queue sets, which can be 1166 * represented by u32 bitmap. 1167 */ 1168 static int hclge_bp_setup_hw(struct hclge_dev *hdev, u8 tc) 1169 { 1170 struct hclge_vport *vport = hdev->vport; 1171 u32 i, k, qs_bitmap; 1172 int ret; 1173 1174 for (i = 0; i < HCLGE_BP_GRP_NUM; i++) { 1175 qs_bitmap = 0; 1176 1177 for (k = 0; k < hdev->num_alloc_vport; k++) { 1178 u16 qs_id = vport->qs_offset + tc; 1179 u8 grp, sub_grp; 1180 1181 grp = hnae3_get_field(qs_id, HCLGE_BP_GRP_ID_M, 1182 HCLGE_BP_GRP_ID_S); 1183 sub_grp = hnae3_get_field(qs_id, HCLGE_BP_SUB_GRP_ID_M, 1184 HCLGE_BP_SUB_GRP_ID_S); 1185 if (i == grp) 1186 qs_bitmap |= (1 << sub_grp); 1187 1188 vport++; 1189 } 1190 1191 ret = hclge_tm_qs_bp_cfg(hdev, tc, i, qs_bitmap); 1192 if (ret) 1193 return ret; 1194 } 1195 1196 return 0; 1197 } 1198 1199 static int hclge_mac_pause_setup_hw(struct hclge_dev *hdev) 1200 { 1201 bool tx_en, rx_en; 1202 1203 switch (hdev->tm_info.fc_mode) { 1204 case HCLGE_FC_NONE: 1205 tx_en = false; 1206 rx_en = false; 1207 break; 1208 case HCLGE_FC_RX_PAUSE: 1209 tx_en = false; 1210 rx_en = true; 1211 break; 1212 case HCLGE_FC_TX_PAUSE: 1213 tx_en = true; 1214 rx_en = false; 1215 break; 1216 case HCLGE_FC_FULL: 1217 tx_en = true; 1218 rx_en = true; 1219 break; 1220 case HCLGE_FC_PFC: 1221 tx_en = false; 1222 rx_en = false; 1223 break; 1224 default: 1225 tx_en = true; 1226 rx_en = true; 1227 } 1228 1229 return hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); 1230 } 1231 1232 int hclge_pause_setup_hw(struct hclge_dev *hdev) 1233 { 1234 int ret; 1235 u8 i; 1236 1237 ret = hclge_pause_param_setup_hw(hdev); 1238 if (ret) 1239 return ret; 1240 1241 ret = hclge_mac_pause_setup_hw(hdev); 1242 if (ret) 1243 return ret; 1244 1245 /* Only DCB-supported dev supports qset back pressure and pfc cmd */ 1246 if (!hnae3_dev_dcb_supported(hdev)) 1247 return 0; 1248 1249 /* When MAC is GE Mode, hdev does not support pfc setting */ 1250 ret = hclge_pfc_setup_hw(hdev); 1251 if (ret) 1252 dev_warn(&hdev->pdev->dev, "set pfc pause failed:%d\n", ret); 1253 1254 for (i = 0; i < hdev->tm_info.num_tc; i++) { 1255 ret = hclge_bp_setup_hw(hdev, i); 1256 if (ret) 1257 return ret; 1258 } 1259 1260 return 0; 1261 } 1262 1263 int hclge_tm_prio_tc_info_update(struct hclge_dev *hdev, u8 *prio_tc) 1264 { 1265 struct hclge_vport *vport = hdev->vport; 1266 struct hnae3_knic_private_info *kinfo; 1267 u32 i, k; 1268 1269 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) { 1270 if (prio_tc[i] >= hdev->tm_info.num_tc) 1271 return -EINVAL; 1272 hdev->tm_info.prio_tc[i] = prio_tc[i]; 1273 1274 for (k = 0; k < hdev->num_alloc_vport; k++) { 1275 kinfo = &vport[k].nic.kinfo; 1276 kinfo->prio_tc[i] = prio_tc[i]; 1277 } 1278 } 1279 return 0; 1280 } 1281 1282 void hclge_tm_schd_info_update(struct hclge_dev *hdev, u8 num_tc) 1283 { 1284 u8 i, bit_map = 0; 1285 1286 hdev->tm_info.num_tc = num_tc; 1287 1288 for (i = 0; i < hdev->tm_info.num_tc; i++) 1289 bit_map |= BIT(i); 1290 1291 if (!bit_map) { 1292 bit_map = 1; 1293 hdev->tm_info.num_tc = 1; 1294 } 1295 1296 hdev->hw_tc_map = bit_map; 1297 1298 hclge_tm_schd_info_init(hdev); 1299 } 1300 1301 int hclge_tm_init_hw(struct hclge_dev *hdev) 1302 { 1303 int ret; 1304 1305 if ((hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) && 1306 (hdev->tx_sch_mode != HCLGE_FLAG_VNET_BASE_SCH_MODE)) 1307 return -ENOTSUPP; 1308 1309 ret = hclge_tm_schd_setup_hw(hdev); 1310 if (ret) 1311 return ret; 1312 1313 ret = hclge_pause_setup_hw(hdev); 1314 if (ret) 1315 return ret; 1316 1317 return 0; 1318 } 1319 1320 int hclge_tm_schd_init(struct hclge_dev *hdev) 1321 { 1322 int ret; 1323 1324 /* fc_mode is HCLGE_FC_FULL on reset */ 1325 hdev->tm_info.fc_mode = HCLGE_FC_FULL; 1326 hdev->fc_mode_last_time = hdev->tm_info.fc_mode; 1327 1328 ret = hclge_tm_schd_info_init(hdev); 1329 if (ret) 1330 return ret; 1331 1332 return hclge_tm_init_hw(hdev); 1333 } 1334