1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 6 #include "hclge_cmd.h" 7 #include "hclge_main.h" 8 #include "hclge_tm.h" 9 10 enum hclge_shaper_level { 11 HCLGE_SHAPER_LVL_PRI = 0, 12 HCLGE_SHAPER_LVL_PG = 1, 13 HCLGE_SHAPER_LVL_PORT = 2, 14 HCLGE_SHAPER_LVL_QSET = 3, 15 HCLGE_SHAPER_LVL_CNT = 4, 16 HCLGE_SHAPER_LVL_VF = 0, 17 HCLGE_SHAPER_LVL_PF = 1, 18 }; 19 20 #define HCLGE_TM_PFC_PKT_GET_CMD_NUM 3 21 #define HCLGE_TM_PFC_NUM_GET_PER_CMD 3 22 23 #define HCLGE_SHAPER_BS_U_DEF 5 24 #define HCLGE_SHAPER_BS_S_DEF 20 25 26 /* hclge_shaper_para_calc: calculate ir parameter for the shaper 27 * @ir: Rate to be config, its unit is Mbps 28 * @shaper_level: the shaper level. eg: port, pg, priority, queueset 29 * @ir_para: parameters of IR shaper 30 * @max_tm_rate: max tm rate is available to config 31 * 32 * the formula: 33 * 34 * IR_b * (2 ^ IR_u) * 8 35 * IR(Mbps) = ------------------------- * CLOCK(1000Mbps) 36 * Tick * (2 ^ IR_s) 37 * 38 * @return: 0: calculate sucessful, negative: fail 39 */ 40 static int hclge_shaper_para_calc(u32 ir, u8 shaper_level, 41 struct hclge_shaper_ir_para *ir_para, 42 u32 max_tm_rate) 43 { 44 #define DEFAULT_SHAPER_IR_B 126 45 #define DIVISOR_CLK (1000 * 8) 46 #define DEFAULT_DIVISOR_IR_B (DEFAULT_SHAPER_IR_B * DIVISOR_CLK) 47 48 static const u16 tick_array[HCLGE_SHAPER_LVL_CNT] = { 49 6 * 256, /* Prioriy level */ 50 6 * 32, /* Prioriy group level */ 51 6 * 8, /* Port level */ 52 6 * 256 /* Qset level */ 53 }; 54 u8 ir_u_calc = 0; 55 u8 ir_s_calc = 0; 56 u32 ir_calc; 57 u32 tick; 58 59 /* Calc tick */ 60 if (shaper_level >= HCLGE_SHAPER_LVL_CNT || 61 ir > max_tm_rate) 62 return -EINVAL; 63 64 tick = tick_array[shaper_level]; 65 66 /** 67 * Calc the speed if ir_b = 126, ir_u = 0 and ir_s = 0 68 * the formula is changed to: 69 * 126 * 1 * 8 70 * ir_calc = ---------------- * 1000 71 * tick * 1 72 */ 73 ir_calc = (DEFAULT_DIVISOR_IR_B + (tick >> 1) - 1) / tick; 74 75 if (ir_calc == ir) { 76 ir_para->ir_b = DEFAULT_SHAPER_IR_B; 77 ir_para->ir_u = 0; 78 ir_para->ir_s = 0; 79 80 return 0; 81 } else if (ir_calc > ir) { 82 /* Increasing the denominator to select ir_s value */ 83 while (ir_calc >= ir && ir) { 84 ir_s_calc++; 85 ir_calc = DEFAULT_DIVISOR_IR_B / 86 (tick * (1 << ir_s_calc)); 87 } 88 89 ir_para->ir_b = (ir * tick * (1 << ir_s_calc) + 90 (DIVISOR_CLK >> 1)) / DIVISOR_CLK; 91 } else { 92 /* Increasing the numerator to select ir_u value */ 93 u32 numerator; 94 95 while (ir_calc < ir) { 96 ir_u_calc++; 97 numerator = DEFAULT_DIVISOR_IR_B * (1 << ir_u_calc); 98 ir_calc = (numerator + (tick >> 1)) / tick; 99 } 100 101 if (ir_calc == ir) { 102 ir_para->ir_b = DEFAULT_SHAPER_IR_B; 103 } else { 104 u32 denominator = DIVISOR_CLK * (1 << --ir_u_calc); 105 ir_para->ir_b = (ir * tick + (denominator >> 1)) / 106 denominator; 107 } 108 } 109 110 ir_para->ir_u = ir_u_calc; 111 ir_para->ir_s = ir_s_calc; 112 113 return 0; 114 } 115 116 static int hclge_pfc_stats_get(struct hclge_dev *hdev, 117 enum hclge_opcode_type opcode, u64 *stats) 118 { 119 struct hclge_desc desc[HCLGE_TM_PFC_PKT_GET_CMD_NUM]; 120 int ret, i, j; 121 122 if (!(opcode == HCLGE_OPC_QUERY_PFC_RX_PKT_CNT || 123 opcode == HCLGE_OPC_QUERY_PFC_TX_PKT_CNT)) 124 return -EINVAL; 125 126 for (i = 0; i < HCLGE_TM_PFC_PKT_GET_CMD_NUM - 1; i++) { 127 hclge_cmd_setup_basic_desc(&desc[i], opcode, true); 128 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 129 } 130 131 hclge_cmd_setup_basic_desc(&desc[i], opcode, true); 132 133 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_TM_PFC_PKT_GET_CMD_NUM); 134 if (ret) 135 return ret; 136 137 for (i = 0; i < HCLGE_TM_PFC_PKT_GET_CMD_NUM; i++) { 138 struct hclge_pfc_stats_cmd *pfc_stats = 139 (struct hclge_pfc_stats_cmd *)desc[i].data; 140 141 for (j = 0; j < HCLGE_TM_PFC_NUM_GET_PER_CMD; j++) { 142 u32 index = i * HCLGE_TM_PFC_PKT_GET_CMD_NUM + j; 143 144 if (index < HCLGE_MAX_TC_NUM) 145 stats[index] = 146 le64_to_cpu(pfc_stats->pkt_num[j]); 147 } 148 } 149 return 0; 150 } 151 152 int hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats) 153 { 154 return hclge_pfc_stats_get(hdev, HCLGE_OPC_QUERY_PFC_RX_PKT_CNT, stats); 155 } 156 157 int hclge_pfc_tx_stats_get(struct hclge_dev *hdev, u64 *stats) 158 { 159 return hclge_pfc_stats_get(hdev, HCLGE_OPC_QUERY_PFC_TX_PKT_CNT, stats); 160 } 161 162 int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx) 163 { 164 struct hclge_desc desc; 165 166 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PAUSE_EN, false); 167 168 desc.data[0] = cpu_to_le32((tx ? HCLGE_TX_MAC_PAUSE_EN_MSK : 0) | 169 (rx ? HCLGE_RX_MAC_PAUSE_EN_MSK : 0)); 170 171 return hclge_cmd_send(&hdev->hw, &desc, 1); 172 } 173 174 static int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap, 175 u8 pfc_bitmap) 176 { 177 struct hclge_desc desc; 178 struct hclge_pfc_en_cmd *pfc = (struct hclge_pfc_en_cmd *)desc.data; 179 180 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PFC_PAUSE_EN, false); 181 182 pfc->tx_rx_en_bitmap = tx_rx_bitmap; 183 pfc->pri_en_bitmap = pfc_bitmap; 184 185 return hclge_cmd_send(&hdev->hw, &desc, 1); 186 } 187 188 static int hclge_pause_param_cfg(struct hclge_dev *hdev, const u8 *addr, 189 u8 pause_trans_gap, u16 pause_trans_time) 190 { 191 struct hclge_cfg_pause_param_cmd *pause_param; 192 struct hclge_desc desc; 193 194 pause_param = (struct hclge_cfg_pause_param_cmd *)desc.data; 195 196 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, false); 197 198 ether_addr_copy(pause_param->mac_addr, addr); 199 ether_addr_copy(pause_param->mac_addr_extra, addr); 200 pause_param->pause_trans_gap = pause_trans_gap; 201 pause_param->pause_trans_time = cpu_to_le16(pause_trans_time); 202 203 return hclge_cmd_send(&hdev->hw, &desc, 1); 204 } 205 206 int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr) 207 { 208 struct hclge_cfg_pause_param_cmd *pause_param; 209 struct hclge_desc desc; 210 u16 trans_time; 211 u8 trans_gap; 212 int ret; 213 214 pause_param = (struct hclge_cfg_pause_param_cmd *)desc.data; 215 216 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, true); 217 218 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 219 if (ret) 220 return ret; 221 222 trans_gap = pause_param->pause_trans_gap; 223 trans_time = le16_to_cpu(pause_param->pause_trans_time); 224 225 return hclge_pause_param_cfg(hdev, mac_addr, trans_gap, trans_time); 226 } 227 228 static int hclge_fill_pri_array(struct hclge_dev *hdev, u8 *pri, u8 pri_id) 229 { 230 u8 tc; 231 232 tc = hdev->tm_info.prio_tc[pri_id]; 233 234 if (tc >= hdev->tm_info.num_tc) 235 return -EINVAL; 236 237 /** 238 * the register for priority has four bytes, the first bytes includes 239 * priority0 and priority1, the higher 4bit stands for priority1 240 * while the lower 4bit stands for priority0, as below: 241 * first byte: | pri_1 | pri_0 | 242 * second byte: | pri_3 | pri_2 | 243 * third byte: | pri_5 | pri_4 | 244 * fourth byte: | pri_7 | pri_6 | 245 */ 246 pri[pri_id >> 1] |= tc << ((pri_id & 1) * 4); 247 248 return 0; 249 } 250 251 static int hclge_up_to_tc_map(struct hclge_dev *hdev) 252 { 253 struct hclge_desc desc; 254 u8 *pri = (u8 *)desc.data; 255 u8 pri_id; 256 int ret; 257 258 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PRI_TO_TC_MAPPING, false); 259 260 for (pri_id = 0; pri_id < HNAE3_MAX_USER_PRIO; pri_id++) { 261 ret = hclge_fill_pri_array(hdev, pri, pri_id); 262 if (ret) 263 return ret; 264 } 265 266 return hclge_cmd_send(&hdev->hw, &desc, 1); 267 } 268 269 static int hclge_tm_pg_to_pri_map_cfg(struct hclge_dev *hdev, 270 u8 pg_id, u8 pri_bit_map) 271 { 272 struct hclge_pg_to_pri_link_cmd *map; 273 struct hclge_desc desc; 274 275 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_TO_PRI_LINK, false); 276 277 map = (struct hclge_pg_to_pri_link_cmd *)desc.data; 278 279 map->pg_id = pg_id; 280 map->pri_bit_map = pri_bit_map; 281 282 return hclge_cmd_send(&hdev->hw, &desc, 1); 283 } 284 285 static int hclge_tm_qs_to_pri_map_cfg(struct hclge_dev *hdev, 286 u16 qs_id, u8 pri) 287 { 288 struct hclge_qs_to_pri_link_cmd *map; 289 struct hclge_desc desc; 290 291 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_TO_PRI_LINK, false); 292 293 map = (struct hclge_qs_to_pri_link_cmd *)desc.data; 294 295 map->qs_id = cpu_to_le16(qs_id); 296 map->priority = pri; 297 map->link_vld = HCLGE_TM_QS_PRI_LINK_VLD_MSK; 298 299 return hclge_cmd_send(&hdev->hw, &desc, 1); 300 } 301 302 static int hclge_tm_q_to_qs_map_cfg(struct hclge_dev *hdev, 303 u16 q_id, u16 qs_id) 304 { 305 struct hclge_nq_to_qs_link_cmd *map; 306 struct hclge_desc desc; 307 u16 qs_id_l; 308 u16 qs_id_h; 309 310 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_NQ_TO_QS_LINK, false); 311 312 map = (struct hclge_nq_to_qs_link_cmd *)desc.data; 313 314 map->nq_id = cpu_to_le16(q_id); 315 316 /* convert qs_id to the following format to support qset_id >= 1024 317 * qs_id: | 15 | 14 ~ 10 | 9 ~ 0 | 318 * / / \ \ 319 * / / \ \ 320 * qset_id: | 15 ~ 11 | 10 | 9 ~ 0 | 321 * | qs_id_h | vld | qs_id_l | 322 */ 323 qs_id_l = hnae3_get_field(qs_id, HCLGE_TM_QS_ID_L_MSK, 324 HCLGE_TM_QS_ID_L_S); 325 qs_id_h = hnae3_get_field(qs_id, HCLGE_TM_QS_ID_H_MSK, 326 HCLGE_TM_QS_ID_H_S); 327 hnae3_set_field(qs_id, HCLGE_TM_QS_ID_L_MSK, HCLGE_TM_QS_ID_L_S, 328 qs_id_l); 329 hnae3_set_field(qs_id, HCLGE_TM_QS_ID_H_EXT_MSK, HCLGE_TM_QS_ID_H_EXT_S, 330 qs_id_h); 331 map->qset_id = cpu_to_le16(qs_id | HCLGE_TM_Q_QS_LINK_VLD_MSK); 332 333 return hclge_cmd_send(&hdev->hw, &desc, 1); 334 } 335 336 static int hclge_tm_pg_weight_cfg(struct hclge_dev *hdev, u8 pg_id, 337 u8 dwrr) 338 { 339 struct hclge_pg_weight_cmd *weight; 340 struct hclge_desc desc; 341 342 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_WEIGHT, false); 343 344 weight = (struct hclge_pg_weight_cmd *)desc.data; 345 346 weight->pg_id = pg_id; 347 weight->dwrr = dwrr; 348 349 return hclge_cmd_send(&hdev->hw, &desc, 1); 350 } 351 352 static int hclge_tm_pri_weight_cfg(struct hclge_dev *hdev, u8 pri_id, 353 u8 dwrr) 354 { 355 struct hclge_priority_weight_cmd *weight; 356 struct hclge_desc desc; 357 358 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_WEIGHT, false); 359 360 weight = (struct hclge_priority_weight_cmd *)desc.data; 361 362 weight->pri_id = pri_id; 363 weight->dwrr = dwrr; 364 365 return hclge_cmd_send(&hdev->hw, &desc, 1); 366 } 367 368 static int hclge_tm_qs_weight_cfg(struct hclge_dev *hdev, u16 qs_id, 369 u8 dwrr) 370 { 371 struct hclge_qs_weight_cmd *weight; 372 struct hclge_desc desc; 373 374 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_WEIGHT, false); 375 376 weight = (struct hclge_qs_weight_cmd *)desc.data; 377 378 weight->qs_id = cpu_to_le16(qs_id); 379 weight->dwrr = dwrr; 380 381 return hclge_cmd_send(&hdev->hw, &desc, 1); 382 } 383 384 static u32 hclge_tm_get_shapping_para(u8 ir_b, u8 ir_u, u8 ir_s, 385 u8 bs_b, u8 bs_s) 386 { 387 u32 shapping_para = 0; 388 389 hclge_tm_set_field(shapping_para, IR_B, ir_b); 390 hclge_tm_set_field(shapping_para, IR_U, ir_u); 391 hclge_tm_set_field(shapping_para, IR_S, ir_s); 392 hclge_tm_set_field(shapping_para, BS_B, bs_b); 393 hclge_tm_set_field(shapping_para, BS_S, bs_s); 394 395 return shapping_para; 396 } 397 398 static int hclge_tm_pg_shapping_cfg(struct hclge_dev *hdev, 399 enum hclge_shap_bucket bucket, u8 pg_id, 400 u32 shapping_para, u32 rate) 401 { 402 struct hclge_pg_shapping_cmd *shap_cfg_cmd; 403 enum hclge_opcode_type opcode; 404 struct hclge_desc desc; 405 406 opcode = bucket ? HCLGE_OPC_TM_PG_P_SHAPPING : 407 HCLGE_OPC_TM_PG_C_SHAPPING; 408 hclge_cmd_setup_basic_desc(&desc, opcode, false); 409 410 shap_cfg_cmd = (struct hclge_pg_shapping_cmd *)desc.data; 411 412 shap_cfg_cmd->pg_id = pg_id; 413 414 shap_cfg_cmd->pg_shapping_para = cpu_to_le32(shapping_para); 415 416 hnae3_set_bit(shap_cfg_cmd->flag, HCLGE_TM_RATE_VLD, 1); 417 418 shap_cfg_cmd->pg_rate = cpu_to_le32(rate); 419 420 return hclge_cmd_send(&hdev->hw, &desc, 1); 421 } 422 423 static int hclge_tm_port_shaper_cfg(struct hclge_dev *hdev) 424 { 425 struct hclge_port_shapping_cmd *shap_cfg_cmd; 426 struct hclge_shaper_ir_para ir_para; 427 struct hclge_desc desc; 428 u32 shapping_para; 429 int ret; 430 431 ret = hclge_shaper_para_calc(hdev->hw.mac.speed, HCLGE_SHAPER_LVL_PORT, 432 &ir_para, 433 hdev->ae_dev->dev_specs.max_tm_rate); 434 if (ret) 435 return ret; 436 437 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PORT_SHAPPING, false); 438 shap_cfg_cmd = (struct hclge_port_shapping_cmd *)desc.data; 439 440 shapping_para = hclge_tm_get_shapping_para(ir_para.ir_b, ir_para.ir_u, 441 ir_para.ir_s, 442 HCLGE_SHAPER_BS_U_DEF, 443 HCLGE_SHAPER_BS_S_DEF); 444 445 shap_cfg_cmd->port_shapping_para = cpu_to_le32(shapping_para); 446 447 hnae3_set_bit(shap_cfg_cmd->flag, HCLGE_TM_RATE_VLD, 1); 448 449 shap_cfg_cmd->port_rate = cpu_to_le32(hdev->hw.mac.speed); 450 451 return hclge_cmd_send(&hdev->hw, &desc, 1); 452 } 453 454 static int hclge_tm_pri_shapping_cfg(struct hclge_dev *hdev, 455 enum hclge_shap_bucket bucket, u8 pri_id, 456 u32 shapping_para, u32 rate) 457 { 458 struct hclge_pri_shapping_cmd *shap_cfg_cmd; 459 enum hclge_opcode_type opcode; 460 struct hclge_desc desc; 461 462 opcode = bucket ? HCLGE_OPC_TM_PRI_P_SHAPPING : 463 HCLGE_OPC_TM_PRI_C_SHAPPING; 464 465 hclge_cmd_setup_basic_desc(&desc, opcode, false); 466 467 shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data; 468 469 shap_cfg_cmd->pri_id = pri_id; 470 471 shap_cfg_cmd->pri_shapping_para = cpu_to_le32(shapping_para); 472 473 hnae3_set_bit(shap_cfg_cmd->flag, HCLGE_TM_RATE_VLD, 1); 474 475 shap_cfg_cmd->pri_rate = cpu_to_le32(rate); 476 477 return hclge_cmd_send(&hdev->hw, &desc, 1); 478 } 479 480 static int hclge_tm_pg_schd_mode_cfg(struct hclge_dev *hdev, u8 pg_id) 481 { 482 struct hclge_desc desc; 483 484 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_SCH_MODE_CFG, false); 485 486 if (hdev->tm_info.pg_info[pg_id].pg_sch_mode == HCLGE_SCH_MODE_DWRR) 487 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK); 488 else 489 desc.data[1] = 0; 490 491 desc.data[0] = cpu_to_le32(pg_id); 492 493 return hclge_cmd_send(&hdev->hw, &desc, 1); 494 } 495 496 static int hclge_tm_pri_schd_mode_cfg(struct hclge_dev *hdev, u8 pri_id) 497 { 498 struct hclge_desc desc; 499 500 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_SCH_MODE_CFG, false); 501 502 if (hdev->tm_info.tc_info[pri_id].tc_sch_mode == HCLGE_SCH_MODE_DWRR) 503 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK); 504 else 505 desc.data[1] = 0; 506 507 desc.data[0] = cpu_to_le32(pri_id); 508 509 return hclge_cmd_send(&hdev->hw, &desc, 1); 510 } 511 512 static int hclge_tm_qs_schd_mode_cfg(struct hclge_dev *hdev, u16 qs_id, u8 mode) 513 { 514 struct hclge_desc desc; 515 516 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_SCH_MODE_CFG, false); 517 518 if (mode == HCLGE_SCH_MODE_DWRR) 519 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK); 520 else 521 desc.data[1] = 0; 522 523 desc.data[0] = cpu_to_le32(qs_id); 524 525 return hclge_cmd_send(&hdev->hw, &desc, 1); 526 } 527 528 static int hclge_tm_qs_bp_cfg(struct hclge_dev *hdev, u8 tc, u8 grp_id, 529 u32 bit_map) 530 { 531 struct hclge_bp_to_qs_map_cmd *bp_to_qs_map_cmd; 532 struct hclge_desc desc; 533 534 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_BP_TO_QSET_MAPPING, 535 false); 536 537 bp_to_qs_map_cmd = (struct hclge_bp_to_qs_map_cmd *)desc.data; 538 539 bp_to_qs_map_cmd->tc_id = tc; 540 bp_to_qs_map_cmd->qs_group_id = grp_id; 541 bp_to_qs_map_cmd->qs_bit_map = cpu_to_le32(bit_map); 542 543 return hclge_cmd_send(&hdev->hw, &desc, 1); 544 } 545 546 int hclge_tm_qs_shaper_cfg(struct hclge_vport *vport, int max_tx_rate) 547 { 548 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 549 struct hclge_qs_shapping_cmd *shap_cfg_cmd; 550 struct hclge_shaper_ir_para ir_para; 551 struct hclge_dev *hdev = vport->back; 552 struct hclge_desc desc; 553 u32 shaper_para; 554 int ret, i; 555 556 if (!max_tx_rate) 557 max_tx_rate = hdev->ae_dev->dev_specs.max_tm_rate; 558 559 ret = hclge_shaper_para_calc(max_tx_rate, HCLGE_SHAPER_LVL_QSET, 560 &ir_para, 561 hdev->ae_dev->dev_specs.max_tm_rate); 562 if (ret) 563 return ret; 564 565 shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b, ir_para.ir_u, 566 ir_para.ir_s, 567 HCLGE_SHAPER_BS_U_DEF, 568 HCLGE_SHAPER_BS_S_DEF); 569 570 for (i = 0; i < kinfo->tc_info.num_tc; i++) { 571 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QCN_SHAPPING_CFG, 572 false); 573 574 shap_cfg_cmd = (struct hclge_qs_shapping_cmd *)desc.data; 575 shap_cfg_cmd->qs_id = cpu_to_le16(vport->qs_offset + i); 576 shap_cfg_cmd->qs_shapping_para = cpu_to_le32(shaper_para); 577 578 hnae3_set_bit(shap_cfg_cmd->flag, HCLGE_TM_RATE_VLD, 1); 579 shap_cfg_cmd->qs_rate = cpu_to_le32(max_tx_rate); 580 581 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 582 if (ret) { 583 dev_err(&hdev->pdev->dev, 584 "vf%u, qs%u failed to set tx_rate:%d, ret=%d\n", 585 vport->vport_id, shap_cfg_cmd->qs_id, 586 max_tx_rate, ret); 587 return ret; 588 } 589 } 590 591 return 0; 592 } 593 594 static u16 hclge_vport_get_max_rss_size(struct hclge_vport *vport) 595 { 596 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 597 struct hnae3_tc_info *tc_info = &kinfo->tc_info; 598 struct hclge_dev *hdev = vport->back; 599 u16 max_rss_size = 0; 600 int i; 601 602 if (!tc_info->mqprio_active) 603 return vport->alloc_tqps / tc_info->num_tc; 604 605 for (i = 0; i < HNAE3_MAX_TC; i++) { 606 if (!(hdev->hw_tc_map & BIT(i)) || i >= tc_info->num_tc) 607 continue; 608 if (max_rss_size < tc_info->tqp_count[i]) 609 max_rss_size = tc_info->tqp_count[i]; 610 } 611 612 return max_rss_size; 613 } 614 615 static u16 hclge_vport_get_tqp_num(struct hclge_vport *vport) 616 { 617 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 618 struct hnae3_tc_info *tc_info = &kinfo->tc_info; 619 struct hclge_dev *hdev = vport->back; 620 int sum = 0; 621 int i; 622 623 if (!tc_info->mqprio_active) 624 return kinfo->rss_size * tc_info->num_tc; 625 626 for (i = 0; i < HNAE3_MAX_TC; i++) { 627 if (hdev->hw_tc_map & BIT(i) && i < tc_info->num_tc) 628 sum += tc_info->tqp_count[i]; 629 } 630 631 return sum; 632 } 633 634 static void hclge_tm_vport_tc_info_update(struct hclge_vport *vport) 635 { 636 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 637 struct hclge_dev *hdev = vport->back; 638 u16 vport_max_rss_size; 639 u16 max_rss_size; 640 u8 i; 641 642 /* TC configuration is shared by PF/VF in one port, only allow 643 * one tc for VF for simplicity. VF's vport_id is non zero. 644 */ 645 if (vport->vport_id) { 646 kinfo->tc_info.num_tc = 1; 647 vport->qs_offset = HNAE3_MAX_TC + 648 vport->vport_id - HCLGE_VF_VPORT_START_NUM; 649 vport_max_rss_size = hdev->vf_rss_size_max; 650 } else { 651 kinfo->tc_info.num_tc = 652 min_t(u16, vport->alloc_tqps, hdev->tm_info.num_tc); 653 vport->qs_offset = 0; 654 vport_max_rss_size = hdev->pf_rss_size_max; 655 } 656 657 max_rss_size = min_t(u16, vport_max_rss_size, 658 hclge_vport_get_max_rss_size(vport)); 659 660 /* Set to user value, no larger than max_rss_size. */ 661 if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 662 kinfo->req_rss_size <= max_rss_size) { 663 dev_info(&hdev->pdev->dev, "rss changes from %u to %u\n", 664 kinfo->rss_size, kinfo->req_rss_size); 665 kinfo->rss_size = kinfo->req_rss_size; 666 } else if (kinfo->rss_size > max_rss_size || 667 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) { 668 /* if user not set rss, the rss_size should compare with the 669 * valid msi numbers to ensure one to one map between tqp and 670 * irq as default. 671 */ 672 if (!kinfo->req_rss_size) 673 max_rss_size = min_t(u16, max_rss_size, 674 (hdev->num_nic_msi - 1) / 675 kinfo->tc_info.num_tc); 676 677 /* Set to the maximum specification value (max_rss_size). */ 678 kinfo->rss_size = max_rss_size; 679 } 680 681 kinfo->num_tqps = hclge_vport_get_tqp_num(vport); 682 vport->dwrr = 100; /* 100 percent as init */ 683 vport->alloc_rss_size = kinfo->rss_size; 684 vport->bw_limit = hdev->tm_info.pg_info[0].bw_limit; 685 686 /* when enable mqprio, the tc_info has been updated. */ 687 if (kinfo->tc_info.mqprio_active) 688 return; 689 690 for (i = 0; i < HNAE3_MAX_TC; i++) { 691 if (hdev->hw_tc_map & BIT(i) && i < kinfo->tc_info.num_tc) { 692 set_bit(i, &kinfo->tc_info.tc_en); 693 kinfo->tc_info.tqp_offset[i] = i * kinfo->rss_size; 694 kinfo->tc_info.tqp_count[i] = kinfo->rss_size; 695 } else { 696 /* Set to default queue if TC is disable */ 697 clear_bit(i, &kinfo->tc_info.tc_en); 698 kinfo->tc_info.tqp_offset[i] = 0; 699 kinfo->tc_info.tqp_count[i] = 1; 700 } 701 } 702 703 memcpy(kinfo->tc_info.prio_tc, hdev->tm_info.prio_tc, 704 sizeof_field(struct hnae3_tc_info, prio_tc)); 705 } 706 707 static void hclge_tm_vport_info_update(struct hclge_dev *hdev) 708 { 709 struct hclge_vport *vport = hdev->vport; 710 u32 i; 711 712 for (i = 0; i < hdev->num_alloc_vport; i++) { 713 hclge_tm_vport_tc_info_update(vport); 714 715 vport++; 716 } 717 } 718 719 static void hclge_tm_tc_info_init(struct hclge_dev *hdev) 720 { 721 u8 i; 722 723 for (i = 0; i < hdev->tm_info.num_tc; i++) { 724 hdev->tm_info.tc_info[i].tc_id = i; 725 hdev->tm_info.tc_info[i].tc_sch_mode = HCLGE_SCH_MODE_DWRR; 726 hdev->tm_info.tc_info[i].pgid = 0; 727 hdev->tm_info.tc_info[i].bw_limit = 728 hdev->tm_info.pg_info[0].bw_limit; 729 } 730 731 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) 732 hdev->tm_info.prio_tc[i] = 733 (i >= hdev->tm_info.num_tc) ? 0 : i; 734 735 /* DCB is enabled if we have more than 1 TC or pfc_en is 736 * non-zero. 737 */ 738 if (hdev->tm_info.num_tc > 1 || hdev->tm_info.pfc_en) 739 hdev->flag |= HCLGE_FLAG_DCB_ENABLE; 740 else 741 hdev->flag &= ~HCLGE_FLAG_DCB_ENABLE; 742 } 743 744 static void hclge_tm_pg_info_init(struct hclge_dev *hdev) 745 { 746 #define BW_PERCENT 100 747 748 u8 i; 749 750 for (i = 0; i < hdev->tm_info.num_pg; i++) { 751 int k; 752 753 hdev->tm_info.pg_dwrr[i] = i ? 0 : BW_PERCENT; 754 755 hdev->tm_info.pg_info[i].pg_id = i; 756 hdev->tm_info.pg_info[i].pg_sch_mode = HCLGE_SCH_MODE_DWRR; 757 758 hdev->tm_info.pg_info[i].bw_limit = 759 hdev->ae_dev->dev_specs.max_tm_rate; 760 761 if (i != 0) 762 continue; 763 764 hdev->tm_info.pg_info[i].tc_bit_map = hdev->hw_tc_map; 765 for (k = 0; k < hdev->tm_info.num_tc; k++) 766 hdev->tm_info.pg_info[i].tc_dwrr[k] = BW_PERCENT; 767 } 768 } 769 770 static void hclge_update_fc_mode_by_dcb_flag(struct hclge_dev *hdev) 771 { 772 if (!(hdev->flag & HCLGE_FLAG_DCB_ENABLE)) { 773 if (hdev->fc_mode_last_time == HCLGE_FC_PFC) 774 dev_warn(&hdev->pdev->dev, 775 "DCB is disable, but last mode is FC_PFC\n"); 776 777 hdev->tm_info.fc_mode = hdev->fc_mode_last_time; 778 } else if (hdev->tm_info.fc_mode != HCLGE_FC_PFC) { 779 /* fc_mode_last_time record the last fc_mode when 780 * DCB is enabled, so that fc_mode can be set to 781 * the correct value when DCB is disabled. 782 */ 783 hdev->fc_mode_last_time = hdev->tm_info.fc_mode; 784 hdev->tm_info.fc_mode = HCLGE_FC_PFC; 785 } 786 } 787 788 static void hclge_update_fc_mode(struct hclge_dev *hdev) 789 { 790 if (!hdev->tm_info.pfc_en) { 791 hdev->tm_info.fc_mode = hdev->fc_mode_last_time; 792 return; 793 } 794 795 if (hdev->tm_info.fc_mode != HCLGE_FC_PFC) { 796 hdev->fc_mode_last_time = hdev->tm_info.fc_mode; 797 hdev->tm_info.fc_mode = HCLGE_FC_PFC; 798 } 799 } 800 801 static void hclge_pfc_info_init(struct hclge_dev *hdev) 802 { 803 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 804 hclge_update_fc_mode(hdev); 805 else 806 hclge_update_fc_mode_by_dcb_flag(hdev); 807 } 808 809 static void hclge_tm_schd_info_init(struct hclge_dev *hdev) 810 { 811 hclge_tm_pg_info_init(hdev); 812 813 hclge_tm_tc_info_init(hdev); 814 815 hclge_tm_vport_info_update(hdev); 816 817 hclge_pfc_info_init(hdev); 818 } 819 820 static int hclge_tm_pg_to_pri_map(struct hclge_dev *hdev) 821 { 822 int ret; 823 u32 i; 824 825 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) 826 return 0; 827 828 for (i = 0; i < hdev->tm_info.num_pg; i++) { 829 /* Cfg mapping */ 830 ret = hclge_tm_pg_to_pri_map_cfg( 831 hdev, i, hdev->tm_info.pg_info[i].tc_bit_map); 832 if (ret) 833 return ret; 834 } 835 836 return 0; 837 } 838 839 static int hclge_tm_pg_shaper_cfg(struct hclge_dev *hdev) 840 { 841 u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate; 842 struct hclge_shaper_ir_para ir_para; 843 u32 shaper_para; 844 int ret; 845 u32 i; 846 847 /* Cfg pg schd */ 848 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) 849 return 0; 850 851 /* Pg to pri */ 852 for (i = 0; i < hdev->tm_info.num_pg; i++) { 853 u32 rate = hdev->tm_info.pg_info[i].bw_limit; 854 855 /* Calc shaper para */ 856 ret = hclge_shaper_para_calc(rate, HCLGE_SHAPER_LVL_PG, 857 &ir_para, max_tm_rate); 858 if (ret) 859 return ret; 860 861 shaper_para = hclge_tm_get_shapping_para(0, 0, 0, 862 HCLGE_SHAPER_BS_U_DEF, 863 HCLGE_SHAPER_BS_S_DEF); 864 ret = hclge_tm_pg_shapping_cfg(hdev, 865 HCLGE_TM_SHAP_C_BUCKET, i, 866 shaper_para, rate); 867 if (ret) 868 return ret; 869 870 shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b, 871 ir_para.ir_u, 872 ir_para.ir_s, 873 HCLGE_SHAPER_BS_U_DEF, 874 HCLGE_SHAPER_BS_S_DEF); 875 ret = hclge_tm_pg_shapping_cfg(hdev, 876 HCLGE_TM_SHAP_P_BUCKET, i, 877 shaper_para, rate); 878 if (ret) 879 return ret; 880 } 881 882 return 0; 883 } 884 885 static int hclge_tm_pg_dwrr_cfg(struct hclge_dev *hdev) 886 { 887 int ret; 888 u32 i; 889 890 /* cfg pg schd */ 891 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) 892 return 0; 893 894 /* pg to prio */ 895 for (i = 0; i < hdev->tm_info.num_pg; i++) { 896 /* Cfg dwrr */ 897 ret = hclge_tm_pg_weight_cfg(hdev, i, hdev->tm_info.pg_dwrr[i]); 898 if (ret) 899 return ret; 900 } 901 902 return 0; 903 } 904 905 static int hclge_vport_q_to_qs_map(struct hclge_dev *hdev, 906 struct hclge_vport *vport) 907 { 908 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 909 struct hnae3_tc_info *tc_info = &kinfo->tc_info; 910 struct hnae3_queue **tqp = kinfo->tqp; 911 u32 i, j; 912 int ret; 913 914 for (i = 0; i < tc_info->num_tc; i++) { 915 for (j = 0; j < tc_info->tqp_count[i]; j++) { 916 struct hnae3_queue *q = tqp[tc_info->tqp_offset[i] + j]; 917 918 ret = hclge_tm_q_to_qs_map_cfg(hdev, 919 hclge_get_queue_id(q), 920 vport->qs_offset + i); 921 if (ret) 922 return ret; 923 } 924 } 925 926 return 0; 927 } 928 929 static int hclge_tm_pri_q_qs_cfg(struct hclge_dev *hdev) 930 { 931 struct hclge_vport *vport = hdev->vport; 932 int ret; 933 u32 i, k; 934 935 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) { 936 /* Cfg qs -> pri mapping, one by one mapping */ 937 for (k = 0; k < hdev->num_alloc_vport; k++) { 938 struct hnae3_knic_private_info *kinfo = 939 &vport[k].nic.kinfo; 940 941 for (i = 0; i < kinfo->tc_info.num_tc; i++) { 942 ret = hclge_tm_qs_to_pri_map_cfg( 943 hdev, vport[k].qs_offset + i, i); 944 if (ret) 945 return ret; 946 } 947 } 948 } else if (hdev->tx_sch_mode == HCLGE_FLAG_VNET_BASE_SCH_MODE) { 949 /* Cfg qs -> pri mapping, qs = tc, pri = vf, 8 qs -> 1 pri */ 950 for (k = 0; k < hdev->num_alloc_vport; k++) 951 for (i = 0; i < HNAE3_MAX_TC; i++) { 952 ret = hclge_tm_qs_to_pri_map_cfg( 953 hdev, vport[k].qs_offset + i, k); 954 if (ret) 955 return ret; 956 } 957 } else { 958 return -EINVAL; 959 } 960 961 /* Cfg q -> qs mapping */ 962 for (i = 0; i < hdev->num_alloc_vport; i++) { 963 ret = hclge_vport_q_to_qs_map(hdev, vport); 964 if (ret) 965 return ret; 966 967 vport++; 968 } 969 970 return 0; 971 } 972 973 static int hclge_tm_pri_tc_base_shaper_cfg(struct hclge_dev *hdev) 974 { 975 u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate; 976 struct hclge_shaper_ir_para ir_para; 977 u32 shaper_para; 978 int ret; 979 u32 i; 980 981 for (i = 0; i < hdev->tm_info.num_tc; i++) { 982 u32 rate = hdev->tm_info.tc_info[i].bw_limit; 983 984 ret = hclge_shaper_para_calc(rate, HCLGE_SHAPER_LVL_PRI, 985 &ir_para, max_tm_rate); 986 if (ret) 987 return ret; 988 989 shaper_para = hclge_tm_get_shapping_para(0, 0, 0, 990 HCLGE_SHAPER_BS_U_DEF, 991 HCLGE_SHAPER_BS_S_DEF); 992 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_C_BUCKET, i, 993 shaper_para, rate); 994 if (ret) 995 return ret; 996 997 shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b, 998 ir_para.ir_u, 999 ir_para.ir_s, 1000 HCLGE_SHAPER_BS_U_DEF, 1001 HCLGE_SHAPER_BS_S_DEF); 1002 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_P_BUCKET, i, 1003 shaper_para, rate); 1004 if (ret) 1005 return ret; 1006 } 1007 1008 return 0; 1009 } 1010 1011 static int hclge_tm_pri_vnet_base_shaper_pri_cfg(struct hclge_vport *vport) 1012 { 1013 struct hclge_dev *hdev = vport->back; 1014 struct hclge_shaper_ir_para ir_para; 1015 u32 shaper_para; 1016 int ret; 1017 1018 ret = hclge_shaper_para_calc(vport->bw_limit, HCLGE_SHAPER_LVL_VF, 1019 &ir_para, 1020 hdev->ae_dev->dev_specs.max_tm_rate); 1021 if (ret) 1022 return ret; 1023 1024 shaper_para = hclge_tm_get_shapping_para(0, 0, 0, 1025 HCLGE_SHAPER_BS_U_DEF, 1026 HCLGE_SHAPER_BS_S_DEF); 1027 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_C_BUCKET, 1028 vport->vport_id, shaper_para, 1029 vport->bw_limit); 1030 if (ret) 1031 return ret; 1032 1033 shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b, ir_para.ir_u, 1034 ir_para.ir_s, 1035 HCLGE_SHAPER_BS_U_DEF, 1036 HCLGE_SHAPER_BS_S_DEF); 1037 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_P_BUCKET, 1038 vport->vport_id, shaper_para, 1039 vport->bw_limit); 1040 if (ret) 1041 return ret; 1042 1043 return 0; 1044 } 1045 1046 static int hclge_tm_pri_vnet_base_shaper_qs_cfg(struct hclge_vport *vport) 1047 { 1048 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 1049 struct hclge_dev *hdev = vport->back; 1050 u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate; 1051 struct hclge_shaper_ir_para ir_para; 1052 u32 i; 1053 int ret; 1054 1055 for (i = 0; i < kinfo->tc_info.num_tc; i++) { 1056 ret = hclge_shaper_para_calc(hdev->tm_info.tc_info[i].bw_limit, 1057 HCLGE_SHAPER_LVL_QSET, 1058 &ir_para, max_tm_rate); 1059 if (ret) 1060 return ret; 1061 } 1062 1063 return 0; 1064 } 1065 1066 static int hclge_tm_pri_vnet_base_shaper_cfg(struct hclge_dev *hdev) 1067 { 1068 struct hclge_vport *vport = hdev->vport; 1069 int ret; 1070 u32 i; 1071 1072 /* Need config vport shaper */ 1073 for (i = 0; i < hdev->num_alloc_vport; i++) { 1074 ret = hclge_tm_pri_vnet_base_shaper_pri_cfg(vport); 1075 if (ret) 1076 return ret; 1077 1078 ret = hclge_tm_pri_vnet_base_shaper_qs_cfg(vport); 1079 if (ret) 1080 return ret; 1081 1082 vport++; 1083 } 1084 1085 return 0; 1086 } 1087 1088 static int hclge_tm_pri_shaper_cfg(struct hclge_dev *hdev) 1089 { 1090 int ret; 1091 1092 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) { 1093 ret = hclge_tm_pri_tc_base_shaper_cfg(hdev); 1094 if (ret) 1095 return ret; 1096 } else { 1097 ret = hclge_tm_pri_vnet_base_shaper_cfg(hdev); 1098 if (ret) 1099 return ret; 1100 } 1101 1102 return 0; 1103 } 1104 1105 static int hclge_tm_pri_tc_base_dwrr_cfg(struct hclge_dev *hdev) 1106 { 1107 struct hclge_vport *vport = hdev->vport; 1108 struct hclge_pg_info *pg_info; 1109 u8 dwrr; 1110 int ret; 1111 u32 i, k; 1112 1113 for (i = 0; i < hdev->tm_info.num_tc; i++) { 1114 pg_info = 1115 &hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid]; 1116 dwrr = pg_info->tc_dwrr[i]; 1117 1118 ret = hclge_tm_pri_weight_cfg(hdev, i, dwrr); 1119 if (ret) 1120 return ret; 1121 1122 for (k = 0; k < hdev->num_alloc_vport; k++) { 1123 ret = hclge_tm_qs_weight_cfg( 1124 hdev, vport[k].qs_offset + i, 1125 vport[k].dwrr); 1126 if (ret) 1127 return ret; 1128 } 1129 } 1130 1131 return 0; 1132 } 1133 1134 static int hclge_tm_ets_tc_dwrr_cfg(struct hclge_dev *hdev) 1135 { 1136 #define DEFAULT_TC_WEIGHT 1 1137 #define DEFAULT_TC_OFFSET 14 1138 1139 struct hclge_ets_tc_weight_cmd *ets_weight; 1140 struct hclge_desc desc; 1141 unsigned int i; 1142 1143 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ETS_TC_WEIGHT, false); 1144 ets_weight = (struct hclge_ets_tc_weight_cmd *)desc.data; 1145 1146 for (i = 0; i < HNAE3_MAX_TC; i++) { 1147 struct hclge_pg_info *pg_info; 1148 1149 ets_weight->tc_weight[i] = DEFAULT_TC_WEIGHT; 1150 1151 if (!(hdev->hw_tc_map & BIT(i))) 1152 continue; 1153 1154 pg_info = 1155 &hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid]; 1156 ets_weight->tc_weight[i] = pg_info->tc_dwrr[i]; 1157 } 1158 1159 ets_weight->weight_offset = DEFAULT_TC_OFFSET; 1160 1161 return hclge_cmd_send(&hdev->hw, &desc, 1); 1162 } 1163 1164 static int hclge_tm_pri_vnet_base_dwrr_pri_cfg(struct hclge_vport *vport) 1165 { 1166 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 1167 struct hclge_dev *hdev = vport->back; 1168 int ret; 1169 u8 i; 1170 1171 /* Vf dwrr */ 1172 ret = hclge_tm_pri_weight_cfg(hdev, vport->vport_id, vport->dwrr); 1173 if (ret) 1174 return ret; 1175 1176 /* Qset dwrr */ 1177 for (i = 0; i < kinfo->tc_info.num_tc; i++) { 1178 ret = hclge_tm_qs_weight_cfg( 1179 hdev, vport->qs_offset + i, 1180 hdev->tm_info.pg_info[0].tc_dwrr[i]); 1181 if (ret) 1182 return ret; 1183 } 1184 1185 return 0; 1186 } 1187 1188 static int hclge_tm_pri_vnet_base_dwrr_cfg(struct hclge_dev *hdev) 1189 { 1190 struct hclge_vport *vport = hdev->vport; 1191 int ret; 1192 u32 i; 1193 1194 for (i = 0; i < hdev->num_alloc_vport; i++) { 1195 ret = hclge_tm_pri_vnet_base_dwrr_pri_cfg(vport); 1196 if (ret) 1197 return ret; 1198 1199 vport++; 1200 } 1201 1202 return 0; 1203 } 1204 1205 static int hclge_tm_pri_dwrr_cfg(struct hclge_dev *hdev) 1206 { 1207 int ret; 1208 1209 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) { 1210 ret = hclge_tm_pri_tc_base_dwrr_cfg(hdev); 1211 if (ret) 1212 return ret; 1213 1214 if (!hnae3_dev_dcb_supported(hdev)) 1215 return 0; 1216 1217 ret = hclge_tm_ets_tc_dwrr_cfg(hdev); 1218 if (ret == -EOPNOTSUPP) { 1219 dev_warn(&hdev->pdev->dev, 1220 "fw %08x does't support ets tc weight cmd\n", 1221 hdev->fw_version); 1222 ret = 0; 1223 } 1224 1225 return ret; 1226 } else { 1227 ret = hclge_tm_pri_vnet_base_dwrr_cfg(hdev); 1228 if (ret) 1229 return ret; 1230 } 1231 1232 return 0; 1233 } 1234 1235 static int hclge_tm_map_cfg(struct hclge_dev *hdev) 1236 { 1237 int ret; 1238 1239 ret = hclge_up_to_tc_map(hdev); 1240 if (ret) 1241 return ret; 1242 1243 ret = hclge_tm_pg_to_pri_map(hdev); 1244 if (ret) 1245 return ret; 1246 1247 return hclge_tm_pri_q_qs_cfg(hdev); 1248 } 1249 1250 static int hclge_tm_shaper_cfg(struct hclge_dev *hdev) 1251 { 1252 int ret; 1253 1254 ret = hclge_tm_port_shaper_cfg(hdev); 1255 if (ret) 1256 return ret; 1257 1258 ret = hclge_tm_pg_shaper_cfg(hdev); 1259 if (ret) 1260 return ret; 1261 1262 return hclge_tm_pri_shaper_cfg(hdev); 1263 } 1264 1265 int hclge_tm_dwrr_cfg(struct hclge_dev *hdev) 1266 { 1267 int ret; 1268 1269 ret = hclge_tm_pg_dwrr_cfg(hdev); 1270 if (ret) 1271 return ret; 1272 1273 return hclge_tm_pri_dwrr_cfg(hdev); 1274 } 1275 1276 static int hclge_tm_lvl2_schd_mode_cfg(struct hclge_dev *hdev) 1277 { 1278 int ret; 1279 u8 i; 1280 1281 /* Only being config on TC-Based scheduler mode */ 1282 if (hdev->tx_sch_mode == HCLGE_FLAG_VNET_BASE_SCH_MODE) 1283 return 0; 1284 1285 for (i = 0; i < hdev->tm_info.num_pg; i++) { 1286 ret = hclge_tm_pg_schd_mode_cfg(hdev, i); 1287 if (ret) 1288 return ret; 1289 } 1290 1291 return 0; 1292 } 1293 1294 static int hclge_tm_schd_mode_vnet_base_cfg(struct hclge_vport *vport) 1295 { 1296 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 1297 struct hclge_dev *hdev = vport->back; 1298 int ret; 1299 u8 i; 1300 1301 if (vport->vport_id >= HNAE3_MAX_TC) 1302 return -EINVAL; 1303 1304 ret = hclge_tm_pri_schd_mode_cfg(hdev, vport->vport_id); 1305 if (ret) 1306 return ret; 1307 1308 for (i = 0; i < kinfo->tc_info.num_tc; i++) { 1309 u8 sch_mode = hdev->tm_info.tc_info[i].tc_sch_mode; 1310 1311 ret = hclge_tm_qs_schd_mode_cfg(hdev, vport->qs_offset + i, 1312 sch_mode); 1313 if (ret) 1314 return ret; 1315 } 1316 1317 return 0; 1318 } 1319 1320 static int hclge_tm_lvl34_schd_mode_cfg(struct hclge_dev *hdev) 1321 { 1322 struct hclge_vport *vport = hdev->vport; 1323 int ret; 1324 u8 i, k; 1325 1326 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) { 1327 for (i = 0; i < hdev->tm_info.num_tc; i++) { 1328 ret = hclge_tm_pri_schd_mode_cfg(hdev, i); 1329 if (ret) 1330 return ret; 1331 1332 for (k = 0; k < hdev->num_alloc_vport; k++) { 1333 ret = hclge_tm_qs_schd_mode_cfg( 1334 hdev, vport[k].qs_offset + i, 1335 HCLGE_SCH_MODE_DWRR); 1336 if (ret) 1337 return ret; 1338 } 1339 } 1340 } else { 1341 for (i = 0; i < hdev->num_alloc_vport; i++) { 1342 ret = hclge_tm_schd_mode_vnet_base_cfg(vport); 1343 if (ret) 1344 return ret; 1345 1346 vport++; 1347 } 1348 } 1349 1350 return 0; 1351 } 1352 1353 static int hclge_tm_schd_mode_hw(struct hclge_dev *hdev) 1354 { 1355 int ret; 1356 1357 ret = hclge_tm_lvl2_schd_mode_cfg(hdev); 1358 if (ret) 1359 return ret; 1360 1361 return hclge_tm_lvl34_schd_mode_cfg(hdev); 1362 } 1363 1364 int hclge_tm_schd_setup_hw(struct hclge_dev *hdev) 1365 { 1366 int ret; 1367 1368 /* Cfg tm mapping */ 1369 ret = hclge_tm_map_cfg(hdev); 1370 if (ret) 1371 return ret; 1372 1373 /* Cfg tm shaper */ 1374 ret = hclge_tm_shaper_cfg(hdev); 1375 if (ret) 1376 return ret; 1377 1378 /* Cfg dwrr */ 1379 ret = hclge_tm_dwrr_cfg(hdev); 1380 if (ret) 1381 return ret; 1382 1383 /* Cfg schd mode for each level schd */ 1384 return hclge_tm_schd_mode_hw(hdev); 1385 } 1386 1387 static int hclge_pause_param_setup_hw(struct hclge_dev *hdev) 1388 { 1389 struct hclge_mac *mac = &hdev->hw.mac; 1390 1391 return hclge_pause_param_cfg(hdev, mac->mac_addr, 1392 HCLGE_DEFAULT_PAUSE_TRANS_GAP, 1393 HCLGE_DEFAULT_PAUSE_TRANS_TIME); 1394 } 1395 1396 static int hclge_pfc_setup_hw(struct hclge_dev *hdev) 1397 { 1398 u8 enable_bitmap = 0; 1399 1400 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) 1401 enable_bitmap = HCLGE_TX_MAC_PAUSE_EN_MSK | 1402 HCLGE_RX_MAC_PAUSE_EN_MSK; 1403 1404 return hclge_pfc_pause_en_cfg(hdev, enable_bitmap, 1405 hdev->tm_info.pfc_en); 1406 } 1407 1408 /* for the queues that use for backpress, divides to several groups, 1409 * each group contains 32 queue sets, which can be represented by u32 bitmap. 1410 */ 1411 static int hclge_bp_setup_hw(struct hclge_dev *hdev, u8 tc) 1412 { 1413 u16 grp_id_shift = HCLGE_BP_GRP_ID_S; 1414 u16 grp_id_mask = HCLGE_BP_GRP_ID_M; 1415 u8 grp_num = HCLGE_BP_GRP_NUM; 1416 int i; 1417 1418 if (hdev->num_tqps > HCLGE_TQP_MAX_SIZE_DEV_V2) { 1419 grp_num = HCLGE_BP_EXT_GRP_NUM; 1420 grp_id_mask = HCLGE_BP_EXT_GRP_ID_M; 1421 grp_id_shift = HCLGE_BP_EXT_GRP_ID_S; 1422 } 1423 1424 for (i = 0; i < grp_num; i++) { 1425 u32 qs_bitmap = 0; 1426 int k, ret; 1427 1428 for (k = 0; k < hdev->num_alloc_vport; k++) { 1429 struct hclge_vport *vport = &hdev->vport[k]; 1430 u16 qs_id = vport->qs_offset + tc; 1431 u8 grp, sub_grp; 1432 1433 grp = hnae3_get_field(qs_id, grp_id_mask, grp_id_shift); 1434 sub_grp = hnae3_get_field(qs_id, HCLGE_BP_SUB_GRP_ID_M, 1435 HCLGE_BP_SUB_GRP_ID_S); 1436 if (i == grp) 1437 qs_bitmap |= (1 << sub_grp); 1438 } 1439 1440 ret = hclge_tm_qs_bp_cfg(hdev, tc, i, qs_bitmap); 1441 if (ret) 1442 return ret; 1443 } 1444 1445 return 0; 1446 } 1447 1448 static int hclge_mac_pause_setup_hw(struct hclge_dev *hdev) 1449 { 1450 bool tx_en, rx_en; 1451 1452 switch (hdev->tm_info.fc_mode) { 1453 case HCLGE_FC_NONE: 1454 tx_en = false; 1455 rx_en = false; 1456 break; 1457 case HCLGE_FC_RX_PAUSE: 1458 tx_en = false; 1459 rx_en = true; 1460 break; 1461 case HCLGE_FC_TX_PAUSE: 1462 tx_en = true; 1463 rx_en = false; 1464 break; 1465 case HCLGE_FC_FULL: 1466 tx_en = true; 1467 rx_en = true; 1468 break; 1469 case HCLGE_FC_PFC: 1470 tx_en = false; 1471 rx_en = false; 1472 break; 1473 default: 1474 tx_en = true; 1475 rx_en = true; 1476 } 1477 1478 return hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); 1479 } 1480 1481 static int hclge_tm_bp_setup(struct hclge_dev *hdev) 1482 { 1483 int ret; 1484 int i; 1485 1486 for (i = 0; i < hdev->tm_info.num_tc; i++) { 1487 ret = hclge_bp_setup_hw(hdev, i); 1488 if (ret) 1489 return ret; 1490 } 1491 1492 return 0; 1493 } 1494 1495 int hclge_pause_setup_hw(struct hclge_dev *hdev, bool init) 1496 { 1497 int ret; 1498 1499 ret = hclge_pause_param_setup_hw(hdev); 1500 if (ret) 1501 return ret; 1502 1503 ret = hclge_mac_pause_setup_hw(hdev); 1504 if (ret) 1505 return ret; 1506 1507 /* Only DCB-supported dev supports qset back pressure and pfc cmd */ 1508 if (!hnae3_dev_dcb_supported(hdev)) 1509 return 0; 1510 1511 /* GE MAC does not support PFC, when driver is initializing and MAC 1512 * is in GE Mode, ignore the error here, otherwise initialization 1513 * will fail. 1514 */ 1515 ret = hclge_pfc_setup_hw(hdev); 1516 if (init && ret == -EOPNOTSUPP) 1517 dev_warn(&hdev->pdev->dev, "GE MAC does not support pfc\n"); 1518 else if (ret) { 1519 dev_err(&hdev->pdev->dev, "config pfc failed! ret = %d\n", 1520 ret); 1521 return ret; 1522 } 1523 1524 return hclge_tm_bp_setup(hdev); 1525 } 1526 1527 void hclge_tm_prio_tc_info_update(struct hclge_dev *hdev, u8 *prio_tc) 1528 { 1529 struct hclge_vport *vport = hdev->vport; 1530 struct hnae3_knic_private_info *kinfo; 1531 u32 i, k; 1532 1533 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) { 1534 hdev->tm_info.prio_tc[i] = prio_tc[i]; 1535 1536 for (k = 0; k < hdev->num_alloc_vport; k++) { 1537 kinfo = &vport[k].nic.kinfo; 1538 kinfo->tc_info.prio_tc[i] = prio_tc[i]; 1539 } 1540 } 1541 } 1542 1543 void hclge_tm_schd_info_update(struct hclge_dev *hdev, u8 num_tc) 1544 { 1545 u8 bit_map = 0; 1546 u8 i; 1547 1548 hdev->tm_info.num_tc = num_tc; 1549 1550 for (i = 0; i < hdev->tm_info.num_tc; i++) 1551 bit_map |= BIT(i); 1552 1553 if (!bit_map) { 1554 bit_map = 1; 1555 hdev->tm_info.num_tc = 1; 1556 } 1557 1558 hdev->hw_tc_map = bit_map; 1559 1560 hclge_tm_schd_info_init(hdev); 1561 } 1562 1563 void hclge_tm_pfc_info_update(struct hclge_dev *hdev) 1564 { 1565 /* DCB is enabled if we have more than 1 TC or pfc_en is 1566 * non-zero. 1567 */ 1568 if (hdev->tm_info.num_tc > 1 || hdev->tm_info.pfc_en) 1569 hdev->flag |= HCLGE_FLAG_DCB_ENABLE; 1570 else 1571 hdev->flag &= ~HCLGE_FLAG_DCB_ENABLE; 1572 1573 hclge_pfc_info_init(hdev); 1574 } 1575 1576 int hclge_tm_init_hw(struct hclge_dev *hdev, bool init) 1577 { 1578 int ret; 1579 1580 if ((hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) && 1581 (hdev->tx_sch_mode != HCLGE_FLAG_VNET_BASE_SCH_MODE)) 1582 return -ENOTSUPP; 1583 1584 ret = hclge_tm_schd_setup_hw(hdev); 1585 if (ret) 1586 return ret; 1587 1588 ret = hclge_pause_setup_hw(hdev, init); 1589 if (ret) 1590 return ret; 1591 1592 return 0; 1593 } 1594 1595 int hclge_tm_schd_init(struct hclge_dev *hdev) 1596 { 1597 /* fc_mode is HCLGE_FC_FULL on reset */ 1598 hdev->tm_info.fc_mode = HCLGE_FC_FULL; 1599 hdev->fc_mode_last_time = hdev->tm_info.fc_mode; 1600 1601 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE && 1602 hdev->tm_info.num_pg != 1) 1603 return -EINVAL; 1604 1605 hclge_tm_schd_info_init(hdev); 1606 1607 return hclge_tm_init_hw(hdev, true); 1608 } 1609 1610 int hclge_tm_vport_map_update(struct hclge_dev *hdev) 1611 { 1612 struct hclge_vport *vport = hdev->vport; 1613 int ret; 1614 1615 hclge_tm_vport_tc_info_update(vport); 1616 1617 ret = hclge_vport_q_to_qs_map(hdev, vport); 1618 if (ret) 1619 return ret; 1620 1621 if (!(hdev->flag & HCLGE_FLAG_DCB_ENABLE)) 1622 return 0; 1623 1624 return hclge_tm_bp_setup(hdev); 1625 } 1626 1627 int hclge_tm_get_qset_num(struct hclge_dev *hdev, u16 *qset_num) 1628 { 1629 struct hclge_tm_nodes_cmd *nodes; 1630 struct hclge_desc desc; 1631 int ret; 1632 1633 if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) { 1634 /* Each PF has 8 qsets and each VF has 1 qset */ 1635 *qset_num = HCLGE_TM_PF_MAX_QSET_NUM + pci_num_vf(hdev->pdev); 1636 return 0; 1637 } 1638 1639 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_NODES, true); 1640 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1641 if (ret) { 1642 dev_err(&hdev->pdev->dev, 1643 "failed to get qset num, ret = %d\n", ret); 1644 return ret; 1645 } 1646 1647 nodes = (struct hclge_tm_nodes_cmd *)desc.data; 1648 *qset_num = le16_to_cpu(nodes->qset_num); 1649 return 0; 1650 } 1651 1652 int hclge_tm_get_pri_num(struct hclge_dev *hdev, u8 *pri_num) 1653 { 1654 struct hclge_tm_nodes_cmd *nodes; 1655 struct hclge_desc desc; 1656 int ret; 1657 1658 if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) { 1659 *pri_num = HCLGE_TM_PF_MAX_PRI_NUM; 1660 return 0; 1661 } 1662 1663 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_NODES, true); 1664 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1665 if (ret) { 1666 dev_err(&hdev->pdev->dev, 1667 "failed to get pri num, ret = %d\n", ret); 1668 return ret; 1669 } 1670 1671 nodes = (struct hclge_tm_nodes_cmd *)desc.data; 1672 *pri_num = nodes->pri_num; 1673 return 0; 1674 } 1675 1676 int hclge_tm_get_qset_map_pri(struct hclge_dev *hdev, u16 qset_id, u8 *priority, 1677 u8 *link_vld) 1678 { 1679 struct hclge_qs_to_pri_link_cmd *map; 1680 struct hclge_desc desc; 1681 int ret; 1682 1683 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_TO_PRI_LINK, true); 1684 map = (struct hclge_qs_to_pri_link_cmd *)desc.data; 1685 map->qs_id = cpu_to_le16(qset_id); 1686 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1687 if (ret) { 1688 dev_err(&hdev->pdev->dev, 1689 "failed to get qset map priority, ret = %d\n", ret); 1690 return ret; 1691 } 1692 1693 *priority = map->priority; 1694 *link_vld = map->link_vld; 1695 return 0; 1696 } 1697 1698 int hclge_tm_get_qset_sch_mode(struct hclge_dev *hdev, u16 qset_id, u8 *mode) 1699 { 1700 struct hclge_qs_sch_mode_cfg_cmd *qs_sch_mode; 1701 struct hclge_desc desc; 1702 int ret; 1703 1704 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_SCH_MODE_CFG, true); 1705 qs_sch_mode = (struct hclge_qs_sch_mode_cfg_cmd *)desc.data; 1706 qs_sch_mode->qs_id = cpu_to_le16(qset_id); 1707 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1708 if (ret) { 1709 dev_err(&hdev->pdev->dev, 1710 "failed to get qset sch mode, ret = %d\n", ret); 1711 return ret; 1712 } 1713 1714 *mode = qs_sch_mode->sch_mode; 1715 return 0; 1716 } 1717 1718 int hclge_tm_get_qset_weight(struct hclge_dev *hdev, u16 qset_id, u8 *weight) 1719 { 1720 struct hclge_qs_weight_cmd *qs_weight; 1721 struct hclge_desc desc; 1722 int ret; 1723 1724 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_WEIGHT, true); 1725 qs_weight = (struct hclge_qs_weight_cmd *)desc.data; 1726 qs_weight->qs_id = cpu_to_le16(qset_id); 1727 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1728 if (ret) { 1729 dev_err(&hdev->pdev->dev, 1730 "failed to get qset weight, ret = %d\n", ret); 1731 return ret; 1732 } 1733 1734 *weight = qs_weight->dwrr; 1735 return 0; 1736 } 1737 1738 int hclge_tm_get_pri_sch_mode(struct hclge_dev *hdev, u8 pri_id, u8 *mode) 1739 { 1740 struct hclge_pri_sch_mode_cfg_cmd *pri_sch_mode; 1741 struct hclge_desc desc; 1742 int ret; 1743 1744 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_SCH_MODE_CFG, true); 1745 pri_sch_mode = (struct hclge_pri_sch_mode_cfg_cmd *)desc.data; 1746 pri_sch_mode->pri_id = pri_id; 1747 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1748 if (ret) { 1749 dev_err(&hdev->pdev->dev, 1750 "failed to get priority sch mode, ret = %d\n", ret); 1751 return ret; 1752 } 1753 1754 *mode = pri_sch_mode->sch_mode; 1755 return 0; 1756 } 1757 1758 int hclge_tm_get_pri_weight(struct hclge_dev *hdev, u8 pri_id, u8 *weight) 1759 { 1760 struct hclge_priority_weight_cmd *priority_weight; 1761 struct hclge_desc desc; 1762 int ret; 1763 1764 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_WEIGHT, true); 1765 priority_weight = (struct hclge_priority_weight_cmd *)desc.data; 1766 priority_weight->pri_id = pri_id; 1767 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1768 if (ret) { 1769 dev_err(&hdev->pdev->dev, 1770 "failed to get priority weight, ret = %d\n", ret); 1771 return ret; 1772 } 1773 1774 *weight = priority_weight->dwrr; 1775 return 0; 1776 } 1777 1778 int hclge_tm_get_pri_shaper(struct hclge_dev *hdev, u8 pri_id, 1779 enum hclge_opcode_type cmd, 1780 struct hclge_pri_shaper_para *para) 1781 { 1782 struct hclge_pri_shapping_cmd *shap_cfg_cmd; 1783 struct hclge_desc desc; 1784 u32 shapping_para; 1785 int ret; 1786 1787 if (cmd != HCLGE_OPC_TM_PRI_C_SHAPPING && 1788 cmd != HCLGE_OPC_TM_PRI_P_SHAPPING) 1789 return -EINVAL; 1790 1791 hclge_cmd_setup_basic_desc(&desc, cmd, true); 1792 shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data; 1793 shap_cfg_cmd->pri_id = pri_id; 1794 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1795 if (ret) { 1796 dev_err(&hdev->pdev->dev, 1797 "failed to get priority shaper(%#x), ret = %d\n", 1798 cmd, ret); 1799 return ret; 1800 } 1801 1802 shapping_para = le32_to_cpu(shap_cfg_cmd->pri_shapping_para); 1803 para->ir_b = hclge_tm_get_field(shapping_para, IR_B); 1804 para->ir_u = hclge_tm_get_field(shapping_para, IR_U); 1805 para->ir_s = hclge_tm_get_field(shapping_para, IR_S); 1806 para->bs_b = hclge_tm_get_field(shapping_para, BS_B); 1807 para->bs_s = hclge_tm_get_field(shapping_para, BS_S); 1808 para->flag = shap_cfg_cmd->flag; 1809 para->rate = le32_to_cpu(shap_cfg_cmd->pri_rate); 1810 return 0; 1811 } 1812