1 /* 2 * Copyright (c) 2016~2017 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #include <linux/etherdevice.h> 11 12 #include "hclge_cmd.h" 13 #include "hclge_main.h" 14 #include "hclge_tm.h" 15 16 enum hclge_shaper_level { 17 HCLGE_SHAPER_LVL_PRI = 0, 18 HCLGE_SHAPER_LVL_PG = 1, 19 HCLGE_SHAPER_LVL_PORT = 2, 20 HCLGE_SHAPER_LVL_QSET = 3, 21 HCLGE_SHAPER_LVL_CNT = 4, 22 HCLGE_SHAPER_LVL_VF = 0, 23 HCLGE_SHAPER_LVL_PF = 1, 24 }; 25 26 #define HCLGE_SHAPER_BS_U_DEF 1 27 #define HCLGE_SHAPER_BS_S_DEF 4 28 29 #define HCLGE_ETHER_MAX_RATE 100000 30 31 /* hclge_shaper_para_calc: calculate ir parameter for the shaper 32 * @ir: Rate to be config, its unit is Mbps 33 * @shaper_level: the shaper level. eg: port, pg, priority, queueset 34 * @ir_b: IR_B parameter of IR shaper 35 * @ir_u: IR_U parameter of IR shaper 36 * @ir_s: IR_S parameter of IR shaper 37 * 38 * the formula: 39 * 40 * IR_b * (2 ^ IR_u) * 8 41 * IR(Mbps) = ------------------------- * CLOCK(1000Mbps) 42 * Tick * (2 ^ IR_s) 43 * 44 * @return: 0: calculate sucessful, negative: fail 45 */ 46 static int hclge_shaper_para_calc(u32 ir, u8 shaper_level, 47 u8 *ir_b, u8 *ir_u, u8 *ir_s) 48 { 49 const u16 tick_array[HCLGE_SHAPER_LVL_CNT] = { 50 6 * 256, /* Prioriy level */ 51 6 * 32, /* Prioriy group level */ 52 6 * 8, /* Port level */ 53 6 * 256 /* Qset level */ 54 }; 55 u8 ir_u_calc = 0, ir_s_calc = 0; 56 u32 ir_calc; 57 u32 tick; 58 59 /* Calc tick */ 60 if (shaper_level >= HCLGE_SHAPER_LVL_CNT) 61 return -EINVAL; 62 63 tick = tick_array[shaper_level]; 64 65 /** 66 * Calc the speed if ir_b = 126, ir_u = 0 and ir_s = 0 67 * the formula is changed to: 68 * 126 * 1 * 8 69 * ir_calc = ---------------- * 1000 70 * tick * 1 71 */ 72 ir_calc = (1008000 + (tick >> 1) - 1) / tick; 73 74 if (ir_calc == ir) { 75 *ir_b = 126; 76 *ir_u = 0; 77 *ir_s = 0; 78 79 return 0; 80 } else if (ir_calc > ir) { 81 /* Increasing the denominator to select ir_s value */ 82 while (ir_calc > ir) { 83 ir_s_calc++; 84 ir_calc = 1008000 / (tick * (1 << ir_s_calc)); 85 } 86 87 if (ir_calc == ir) 88 *ir_b = 126; 89 else 90 *ir_b = (ir * tick * (1 << ir_s_calc) + 4000) / 8000; 91 } else { 92 /* Increasing the numerator to select ir_u value */ 93 u32 numerator; 94 95 while (ir_calc < ir) { 96 ir_u_calc++; 97 numerator = 1008000 * (1 << ir_u_calc); 98 ir_calc = (numerator + (tick >> 1)) / tick; 99 } 100 101 if (ir_calc == ir) { 102 *ir_b = 126; 103 } else { 104 u32 denominator = (8000 * (1 << --ir_u_calc)); 105 *ir_b = (ir * tick + (denominator >> 1)) / denominator; 106 } 107 } 108 109 *ir_u = ir_u_calc; 110 *ir_s = ir_s_calc; 111 112 return 0; 113 } 114 115 static int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx) 116 { 117 struct hclge_desc desc; 118 119 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PAUSE_EN, false); 120 121 desc.data[0] = cpu_to_le32((tx ? HCLGE_TX_MAC_PAUSE_EN_MSK : 0) | 122 (rx ? HCLGE_RX_MAC_PAUSE_EN_MSK : 0)); 123 124 return hclge_cmd_send(&hdev->hw, &desc, 1); 125 } 126 127 static int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap, 128 u8 pfc_bitmap) 129 { 130 struct hclge_desc desc; 131 struct hclge_pfc_en_cmd *pfc = (struct hclge_pfc_en_cmd *)&desc.data; 132 133 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PFC_PAUSE_EN, false); 134 135 pfc->tx_rx_en_bitmap = tx_rx_bitmap; 136 pfc->pri_en_bitmap = pfc_bitmap; 137 138 return hclge_cmd_send(&hdev->hw, &desc, 1); 139 } 140 141 static int hclge_fill_pri_array(struct hclge_dev *hdev, u8 *pri, u8 pri_id) 142 { 143 u8 tc; 144 145 tc = hdev->tm_info.prio_tc[pri_id]; 146 147 if (tc >= hdev->tm_info.num_tc) 148 return -EINVAL; 149 150 /** 151 * the register for priority has four bytes, the first bytes includes 152 * priority0 and priority1, the higher 4bit stands for priority1 153 * while the lower 4bit stands for priority0, as below: 154 * first byte: | pri_1 | pri_0 | 155 * second byte: | pri_3 | pri_2 | 156 * third byte: | pri_5 | pri_4 | 157 * fourth byte: | pri_7 | pri_6 | 158 */ 159 pri[pri_id >> 1] |= tc << ((pri_id & 1) * 4); 160 161 return 0; 162 } 163 164 static int hclge_up_to_tc_map(struct hclge_dev *hdev) 165 { 166 struct hclge_desc desc; 167 u8 *pri = (u8 *)desc.data; 168 u8 pri_id; 169 int ret; 170 171 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PRI_TO_TC_MAPPING, false); 172 173 for (pri_id = 0; pri_id < HNAE3_MAX_USER_PRIO; pri_id++) { 174 ret = hclge_fill_pri_array(hdev, pri, pri_id); 175 if (ret) 176 return ret; 177 } 178 179 return hclge_cmd_send(&hdev->hw, &desc, 1); 180 } 181 182 static int hclge_tm_pg_to_pri_map_cfg(struct hclge_dev *hdev, 183 u8 pg_id, u8 pri_bit_map) 184 { 185 struct hclge_pg_to_pri_link_cmd *map; 186 struct hclge_desc desc; 187 188 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_TO_PRI_LINK, false); 189 190 map = (struct hclge_pg_to_pri_link_cmd *)desc.data; 191 192 map->pg_id = pg_id; 193 map->pri_bit_map = pri_bit_map; 194 195 return hclge_cmd_send(&hdev->hw, &desc, 1); 196 } 197 198 static int hclge_tm_qs_to_pri_map_cfg(struct hclge_dev *hdev, 199 u16 qs_id, u8 pri) 200 { 201 struct hclge_qs_to_pri_link_cmd *map; 202 struct hclge_desc desc; 203 204 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_TO_PRI_LINK, false); 205 206 map = (struct hclge_qs_to_pri_link_cmd *)desc.data; 207 208 map->qs_id = cpu_to_le16(qs_id); 209 map->priority = pri; 210 map->link_vld = HCLGE_TM_QS_PRI_LINK_VLD_MSK; 211 212 return hclge_cmd_send(&hdev->hw, &desc, 1); 213 } 214 215 static int hclge_tm_q_to_qs_map_cfg(struct hclge_dev *hdev, 216 u8 q_id, u16 qs_id) 217 { 218 struct hclge_nq_to_qs_link_cmd *map; 219 struct hclge_desc desc; 220 221 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_NQ_TO_QS_LINK, false); 222 223 map = (struct hclge_nq_to_qs_link_cmd *)desc.data; 224 225 map->nq_id = cpu_to_le16(q_id); 226 map->qset_id = cpu_to_le16(qs_id | HCLGE_TM_Q_QS_LINK_VLD_MSK); 227 228 return hclge_cmd_send(&hdev->hw, &desc, 1); 229 } 230 231 static int hclge_tm_pg_weight_cfg(struct hclge_dev *hdev, u8 pg_id, 232 u8 dwrr) 233 { 234 struct hclge_pg_weight_cmd *weight; 235 struct hclge_desc desc; 236 237 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_WEIGHT, false); 238 239 weight = (struct hclge_pg_weight_cmd *)desc.data; 240 241 weight->pg_id = pg_id; 242 weight->dwrr = dwrr; 243 244 return hclge_cmd_send(&hdev->hw, &desc, 1); 245 } 246 247 static int hclge_tm_pri_weight_cfg(struct hclge_dev *hdev, u8 pri_id, 248 u8 dwrr) 249 { 250 struct hclge_priority_weight_cmd *weight; 251 struct hclge_desc desc; 252 253 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_WEIGHT, false); 254 255 weight = (struct hclge_priority_weight_cmd *)desc.data; 256 257 weight->pri_id = pri_id; 258 weight->dwrr = dwrr; 259 260 return hclge_cmd_send(&hdev->hw, &desc, 1); 261 } 262 263 static int hclge_tm_qs_weight_cfg(struct hclge_dev *hdev, u16 qs_id, 264 u8 dwrr) 265 { 266 struct hclge_qs_weight_cmd *weight; 267 struct hclge_desc desc; 268 269 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_WEIGHT, false); 270 271 weight = (struct hclge_qs_weight_cmd *)desc.data; 272 273 weight->qs_id = cpu_to_le16(qs_id); 274 weight->dwrr = dwrr; 275 276 return hclge_cmd_send(&hdev->hw, &desc, 1); 277 } 278 279 static int hclge_tm_pg_shapping_cfg(struct hclge_dev *hdev, 280 enum hclge_shap_bucket bucket, u8 pg_id, 281 u8 ir_b, u8 ir_u, u8 ir_s, u8 bs_b, u8 bs_s) 282 { 283 struct hclge_pg_shapping_cmd *shap_cfg_cmd; 284 enum hclge_opcode_type opcode; 285 struct hclge_desc desc; 286 287 opcode = bucket ? HCLGE_OPC_TM_PG_P_SHAPPING : 288 HCLGE_OPC_TM_PG_C_SHAPPING; 289 hclge_cmd_setup_basic_desc(&desc, opcode, false); 290 291 shap_cfg_cmd = (struct hclge_pg_shapping_cmd *)desc.data; 292 293 shap_cfg_cmd->pg_id = pg_id; 294 295 hclge_tm_set_field(shap_cfg_cmd->pg_shapping_para, IR_B, ir_b); 296 hclge_tm_set_field(shap_cfg_cmd->pg_shapping_para, IR_U, ir_u); 297 hclge_tm_set_field(shap_cfg_cmd->pg_shapping_para, IR_S, ir_s); 298 hclge_tm_set_field(shap_cfg_cmd->pg_shapping_para, BS_B, bs_b); 299 hclge_tm_set_field(shap_cfg_cmd->pg_shapping_para, BS_S, bs_s); 300 301 return hclge_cmd_send(&hdev->hw, &desc, 1); 302 } 303 304 static int hclge_tm_pri_shapping_cfg(struct hclge_dev *hdev, 305 enum hclge_shap_bucket bucket, u8 pri_id, 306 u8 ir_b, u8 ir_u, u8 ir_s, 307 u8 bs_b, u8 bs_s) 308 { 309 struct hclge_pri_shapping_cmd *shap_cfg_cmd; 310 enum hclge_opcode_type opcode; 311 struct hclge_desc desc; 312 313 opcode = bucket ? HCLGE_OPC_TM_PRI_P_SHAPPING : 314 HCLGE_OPC_TM_PRI_C_SHAPPING; 315 316 hclge_cmd_setup_basic_desc(&desc, opcode, false); 317 318 shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data; 319 320 shap_cfg_cmd->pri_id = pri_id; 321 322 hclge_tm_set_field(shap_cfg_cmd->pri_shapping_para, IR_B, ir_b); 323 hclge_tm_set_field(shap_cfg_cmd->pri_shapping_para, IR_U, ir_u); 324 hclge_tm_set_field(shap_cfg_cmd->pri_shapping_para, IR_S, ir_s); 325 hclge_tm_set_field(shap_cfg_cmd->pri_shapping_para, BS_B, bs_b); 326 hclge_tm_set_field(shap_cfg_cmd->pri_shapping_para, BS_S, bs_s); 327 328 return hclge_cmd_send(&hdev->hw, &desc, 1); 329 } 330 331 static int hclge_tm_pg_schd_mode_cfg(struct hclge_dev *hdev, u8 pg_id) 332 { 333 struct hclge_desc desc; 334 335 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_SCH_MODE_CFG, false); 336 337 if (hdev->tm_info.pg_info[pg_id].pg_sch_mode == HCLGE_SCH_MODE_DWRR) 338 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK); 339 else 340 desc.data[1] = 0; 341 342 desc.data[0] = cpu_to_le32(pg_id); 343 344 return hclge_cmd_send(&hdev->hw, &desc, 1); 345 } 346 347 static int hclge_tm_pri_schd_mode_cfg(struct hclge_dev *hdev, u8 pri_id) 348 { 349 struct hclge_desc desc; 350 351 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_SCH_MODE_CFG, false); 352 353 if (hdev->tm_info.tc_info[pri_id].tc_sch_mode == HCLGE_SCH_MODE_DWRR) 354 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK); 355 else 356 desc.data[1] = 0; 357 358 desc.data[0] = cpu_to_le32(pri_id); 359 360 return hclge_cmd_send(&hdev->hw, &desc, 1); 361 } 362 363 static int hclge_tm_qs_schd_mode_cfg(struct hclge_dev *hdev, u16 qs_id) 364 { 365 struct hclge_desc desc; 366 367 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_SCH_MODE_CFG, false); 368 369 if (hdev->tm_info.tc_info[qs_id].tc_sch_mode == HCLGE_SCH_MODE_DWRR) 370 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK); 371 else 372 desc.data[1] = 0; 373 374 desc.data[0] = cpu_to_le32(qs_id); 375 376 return hclge_cmd_send(&hdev->hw, &desc, 1); 377 } 378 379 static int hclge_tm_qs_bp_cfg(struct hclge_dev *hdev, u8 tc) 380 { 381 struct hclge_bp_to_qs_map_cmd *bp_to_qs_map_cmd; 382 struct hclge_desc desc; 383 384 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_BP_TO_QSET_MAPPING, 385 false); 386 387 bp_to_qs_map_cmd = (struct hclge_bp_to_qs_map_cmd *)desc.data; 388 389 bp_to_qs_map_cmd->tc_id = tc; 390 391 /* Qset and tc is one by one mapping */ 392 bp_to_qs_map_cmd->qs_bit_map = cpu_to_le32(1 << tc); 393 394 return hclge_cmd_send(&hdev->hw, &desc, 1); 395 } 396 397 static void hclge_tm_vport_tc_info_update(struct hclge_vport *vport) 398 { 399 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 400 struct hclge_dev *hdev = vport->back; 401 u8 i; 402 403 kinfo = &vport->nic.kinfo; 404 vport->bw_limit = hdev->tm_info.pg_info[0].bw_limit; 405 kinfo->num_tc = 406 min_t(u16, kinfo->num_tqps, hdev->tm_info.num_tc); 407 kinfo->rss_size 408 = min_t(u16, hdev->rss_size_max, 409 kinfo->num_tqps / kinfo->num_tc); 410 vport->qs_offset = hdev->tm_info.num_tc * vport->vport_id; 411 vport->dwrr = 100; /* 100 percent as init */ 412 vport->alloc_rss_size = kinfo->rss_size; 413 414 for (i = 0; i < kinfo->num_tc; i++) { 415 if (hdev->hw_tc_map & BIT(i)) { 416 kinfo->tc_info[i].enable = true; 417 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size; 418 kinfo->tc_info[i].tqp_count = kinfo->rss_size; 419 kinfo->tc_info[i].tc = i; 420 } else { 421 /* Set to default queue if TC is disable */ 422 kinfo->tc_info[i].enable = false; 423 kinfo->tc_info[i].tqp_offset = 0; 424 kinfo->tc_info[i].tqp_count = 1; 425 kinfo->tc_info[i].tc = 0; 426 } 427 } 428 429 memcpy(kinfo->prio_tc, hdev->tm_info.prio_tc, 430 FIELD_SIZEOF(struct hnae3_knic_private_info, prio_tc)); 431 } 432 433 static void hclge_tm_vport_info_update(struct hclge_dev *hdev) 434 { 435 struct hclge_vport *vport = hdev->vport; 436 u32 i; 437 438 for (i = 0; i < hdev->num_alloc_vport; i++) { 439 hclge_tm_vport_tc_info_update(vport); 440 441 vport++; 442 } 443 } 444 445 static void hclge_tm_tc_info_init(struct hclge_dev *hdev) 446 { 447 u8 i; 448 449 for (i = 0; i < hdev->tm_info.num_tc; i++) { 450 hdev->tm_info.tc_info[i].tc_id = i; 451 hdev->tm_info.tc_info[i].tc_sch_mode = HCLGE_SCH_MODE_DWRR; 452 hdev->tm_info.tc_info[i].pgid = 0; 453 hdev->tm_info.tc_info[i].bw_limit = 454 hdev->tm_info.pg_info[0].bw_limit; 455 } 456 457 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) 458 hdev->tm_info.prio_tc[i] = 459 (i >= hdev->tm_info.num_tc) ? 0 : i; 460 461 hdev->flag &= ~HCLGE_FLAG_DCB_ENABLE; 462 } 463 464 static void hclge_tm_pg_info_init(struct hclge_dev *hdev) 465 { 466 u8 i; 467 468 for (i = 0; i < hdev->tm_info.num_pg; i++) { 469 int k; 470 471 hdev->tm_info.pg_dwrr[i] = i ? 0 : 100; 472 473 hdev->tm_info.pg_info[i].pg_id = i; 474 hdev->tm_info.pg_info[i].pg_sch_mode = HCLGE_SCH_MODE_DWRR; 475 476 hdev->tm_info.pg_info[i].bw_limit = HCLGE_ETHER_MAX_RATE; 477 478 if (i != 0) 479 continue; 480 481 hdev->tm_info.pg_info[i].tc_bit_map = hdev->hw_tc_map; 482 for (k = 0; k < hdev->tm_info.num_tc; k++) 483 hdev->tm_info.pg_info[i].tc_dwrr[k] = 100; 484 } 485 } 486 487 static int hclge_tm_schd_info_init(struct hclge_dev *hdev) 488 { 489 if ((hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) && 490 (hdev->tm_info.num_pg != 1)) 491 return -EINVAL; 492 493 hclge_tm_pg_info_init(hdev); 494 495 hclge_tm_tc_info_init(hdev); 496 497 hclge_tm_vport_info_update(hdev); 498 499 hdev->tm_info.fc_mode = HCLGE_FC_NONE; 500 hdev->fc_mode_last_time = hdev->tm_info.fc_mode; 501 502 return 0; 503 } 504 505 static int hclge_tm_pg_to_pri_map(struct hclge_dev *hdev) 506 { 507 int ret; 508 u32 i; 509 510 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) 511 return 0; 512 513 for (i = 0; i < hdev->tm_info.num_pg; i++) { 514 /* Cfg mapping */ 515 ret = hclge_tm_pg_to_pri_map_cfg( 516 hdev, i, hdev->tm_info.pg_info[i].tc_bit_map); 517 if (ret) 518 return ret; 519 } 520 521 return 0; 522 } 523 524 static int hclge_tm_pg_shaper_cfg(struct hclge_dev *hdev) 525 { 526 u8 ir_u, ir_b, ir_s; 527 int ret; 528 u32 i; 529 530 /* Cfg pg schd */ 531 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) 532 return 0; 533 534 /* Pg to pri */ 535 for (i = 0; i < hdev->tm_info.num_pg; i++) { 536 /* Calc shaper para */ 537 ret = hclge_shaper_para_calc( 538 hdev->tm_info.pg_info[i].bw_limit, 539 HCLGE_SHAPER_LVL_PG, 540 &ir_b, &ir_u, &ir_s); 541 if (ret) 542 return ret; 543 544 ret = hclge_tm_pg_shapping_cfg(hdev, 545 HCLGE_TM_SHAP_C_BUCKET, i, 546 0, 0, 0, HCLGE_SHAPER_BS_U_DEF, 547 HCLGE_SHAPER_BS_S_DEF); 548 if (ret) 549 return ret; 550 551 ret = hclge_tm_pg_shapping_cfg(hdev, 552 HCLGE_TM_SHAP_P_BUCKET, i, 553 ir_b, ir_u, ir_s, 554 HCLGE_SHAPER_BS_U_DEF, 555 HCLGE_SHAPER_BS_S_DEF); 556 if (ret) 557 return ret; 558 } 559 560 return 0; 561 } 562 563 static int hclge_tm_pg_dwrr_cfg(struct hclge_dev *hdev) 564 { 565 int ret; 566 u32 i; 567 568 /* cfg pg schd */ 569 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) 570 return 0; 571 572 /* pg to prio */ 573 for (i = 0; i < hdev->tm_info.num_pg; i++) { 574 /* Cfg dwrr */ 575 ret = hclge_tm_pg_weight_cfg(hdev, i, 576 hdev->tm_info.pg_dwrr[i]); 577 if (ret) 578 return ret; 579 } 580 581 return 0; 582 } 583 584 static int hclge_vport_q_to_qs_map(struct hclge_dev *hdev, 585 struct hclge_vport *vport) 586 { 587 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 588 struct hnae3_queue **tqp = kinfo->tqp; 589 struct hnae3_tc_info *v_tc_info; 590 u32 i, j; 591 int ret; 592 593 for (i = 0; i < kinfo->num_tc; i++) { 594 v_tc_info = &kinfo->tc_info[i]; 595 for (j = 0; j < v_tc_info->tqp_count; j++) { 596 struct hnae3_queue *q = tqp[v_tc_info->tqp_offset + j]; 597 598 ret = hclge_tm_q_to_qs_map_cfg(hdev, 599 hclge_get_queue_id(q), 600 vport->qs_offset + i); 601 if (ret) 602 return ret; 603 } 604 } 605 606 return 0; 607 } 608 609 static int hclge_tm_pri_q_qs_cfg(struct hclge_dev *hdev) 610 { 611 struct hclge_vport *vport = hdev->vport; 612 int ret; 613 u32 i; 614 615 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) { 616 /* Cfg qs -> pri mapping, one by one mapping */ 617 for (i = 0; i < hdev->tm_info.num_tc; i++) { 618 ret = hclge_tm_qs_to_pri_map_cfg(hdev, i, i); 619 if (ret) 620 return ret; 621 } 622 } else if (hdev->tx_sch_mode == HCLGE_FLAG_VNET_BASE_SCH_MODE) { 623 int k; 624 /* Cfg qs -> pri mapping, qs = tc, pri = vf, 8 qs -> 1 pri */ 625 for (k = 0; k < hdev->num_alloc_vport; k++) 626 for (i = 0; i < HNAE3_MAX_TC; i++) { 627 ret = hclge_tm_qs_to_pri_map_cfg( 628 hdev, vport[k].qs_offset + i, k); 629 if (ret) 630 return ret; 631 } 632 } else { 633 return -EINVAL; 634 } 635 636 /* Cfg q -> qs mapping */ 637 for (i = 0; i < hdev->num_alloc_vport; i++) { 638 ret = hclge_vport_q_to_qs_map(hdev, vport); 639 if (ret) 640 return ret; 641 642 vport++; 643 } 644 645 return 0; 646 } 647 648 static int hclge_tm_pri_tc_base_shaper_cfg(struct hclge_dev *hdev) 649 { 650 u8 ir_u, ir_b, ir_s; 651 int ret; 652 u32 i; 653 654 for (i = 0; i < hdev->tm_info.num_tc; i++) { 655 ret = hclge_shaper_para_calc( 656 hdev->tm_info.tc_info[i].bw_limit, 657 HCLGE_SHAPER_LVL_PRI, 658 &ir_b, &ir_u, &ir_s); 659 if (ret) 660 return ret; 661 662 ret = hclge_tm_pri_shapping_cfg( 663 hdev, HCLGE_TM_SHAP_C_BUCKET, i, 664 0, 0, 0, HCLGE_SHAPER_BS_U_DEF, 665 HCLGE_SHAPER_BS_S_DEF); 666 if (ret) 667 return ret; 668 669 ret = hclge_tm_pri_shapping_cfg( 670 hdev, HCLGE_TM_SHAP_P_BUCKET, i, 671 ir_b, ir_u, ir_s, HCLGE_SHAPER_BS_U_DEF, 672 HCLGE_SHAPER_BS_S_DEF); 673 if (ret) 674 return ret; 675 } 676 677 return 0; 678 } 679 680 static int hclge_tm_pri_vnet_base_shaper_pri_cfg(struct hclge_vport *vport) 681 { 682 struct hclge_dev *hdev = vport->back; 683 u8 ir_u, ir_b, ir_s; 684 int ret; 685 686 ret = hclge_shaper_para_calc(vport->bw_limit, HCLGE_SHAPER_LVL_VF, 687 &ir_b, &ir_u, &ir_s); 688 if (ret) 689 return ret; 690 691 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_C_BUCKET, 692 vport->vport_id, 693 0, 0, 0, HCLGE_SHAPER_BS_U_DEF, 694 HCLGE_SHAPER_BS_S_DEF); 695 if (ret) 696 return ret; 697 698 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_P_BUCKET, 699 vport->vport_id, 700 ir_b, ir_u, ir_s, 701 HCLGE_SHAPER_BS_U_DEF, 702 HCLGE_SHAPER_BS_S_DEF); 703 if (ret) 704 return ret; 705 706 return 0; 707 } 708 709 static int hclge_tm_pri_vnet_base_shaper_qs_cfg(struct hclge_vport *vport) 710 { 711 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 712 struct hclge_dev *hdev = vport->back; 713 struct hnae3_tc_info *v_tc_info; 714 u8 ir_u, ir_b, ir_s; 715 u32 i; 716 int ret; 717 718 for (i = 0; i < kinfo->num_tc; i++) { 719 v_tc_info = &kinfo->tc_info[i]; 720 ret = hclge_shaper_para_calc( 721 hdev->tm_info.tc_info[i].bw_limit, 722 HCLGE_SHAPER_LVL_QSET, 723 &ir_b, &ir_u, &ir_s); 724 if (ret) 725 return ret; 726 } 727 728 return 0; 729 } 730 731 static int hclge_tm_pri_vnet_base_shaper_cfg(struct hclge_dev *hdev) 732 { 733 struct hclge_vport *vport = hdev->vport; 734 int ret; 735 u32 i; 736 737 /* Need config vport shaper */ 738 for (i = 0; i < hdev->num_alloc_vport; i++) { 739 ret = hclge_tm_pri_vnet_base_shaper_pri_cfg(vport); 740 if (ret) 741 return ret; 742 743 ret = hclge_tm_pri_vnet_base_shaper_qs_cfg(vport); 744 if (ret) 745 return ret; 746 747 vport++; 748 } 749 750 return 0; 751 } 752 753 static int hclge_tm_pri_shaper_cfg(struct hclge_dev *hdev) 754 { 755 int ret; 756 757 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) { 758 ret = hclge_tm_pri_tc_base_shaper_cfg(hdev); 759 if (ret) 760 return ret; 761 } else { 762 ret = hclge_tm_pri_vnet_base_shaper_cfg(hdev); 763 if (ret) 764 return ret; 765 } 766 767 return 0; 768 } 769 770 static int hclge_tm_pri_tc_base_dwrr_cfg(struct hclge_dev *hdev) 771 { 772 struct hclge_pg_info *pg_info; 773 u8 dwrr; 774 int ret; 775 u32 i; 776 777 for (i = 0; i < hdev->tm_info.num_tc; i++) { 778 pg_info = 779 &hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid]; 780 dwrr = pg_info->tc_dwrr[i]; 781 782 ret = hclge_tm_pri_weight_cfg(hdev, i, dwrr); 783 if (ret) 784 return ret; 785 786 ret = hclge_tm_qs_weight_cfg(hdev, i, dwrr); 787 if (ret) 788 return ret; 789 } 790 791 return 0; 792 } 793 794 static int hclge_tm_pri_vnet_base_dwrr_pri_cfg(struct hclge_vport *vport) 795 { 796 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 797 struct hclge_dev *hdev = vport->back; 798 int ret; 799 u8 i; 800 801 /* Vf dwrr */ 802 ret = hclge_tm_pri_weight_cfg(hdev, vport->vport_id, vport->dwrr); 803 if (ret) 804 return ret; 805 806 /* Qset dwrr */ 807 for (i = 0; i < kinfo->num_tc; i++) { 808 ret = hclge_tm_qs_weight_cfg( 809 hdev, vport->qs_offset + i, 810 hdev->tm_info.pg_info[0].tc_dwrr[i]); 811 if (ret) 812 return ret; 813 } 814 815 return 0; 816 } 817 818 static int hclge_tm_pri_vnet_base_dwrr_cfg(struct hclge_dev *hdev) 819 { 820 struct hclge_vport *vport = hdev->vport; 821 int ret; 822 u32 i; 823 824 for (i = 0; i < hdev->num_alloc_vport; i++) { 825 ret = hclge_tm_pri_vnet_base_dwrr_pri_cfg(vport); 826 if (ret) 827 return ret; 828 829 vport++; 830 } 831 832 return 0; 833 } 834 835 static int hclge_tm_pri_dwrr_cfg(struct hclge_dev *hdev) 836 { 837 int ret; 838 839 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) { 840 ret = hclge_tm_pri_tc_base_dwrr_cfg(hdev); 841 if (ret) 842 return ret; 843 } else { 844 ret = hclge_tm_pri_vnet_base_dwrr_cfg(hdev); 845 if (ret) 846 return ret; 847 } 848 849 return 0; 850 } 851 852 static int hclge_tm_map_cfg(struct hclge_dev *hdev) 853 { 854 int ret; 855 856 ret = hclge_tm_pg_to_pri_map(hdev); 857 if (ret) 858 return ret; 859 860 return hclge_tm_pri_q_qs_cfg(hdev); 861 } 862 863 static int hclge_tm_shaper_cfg(struct hclge_dev *hdev) 864 { 865 int ret; 866 867 ret = hclge_tm_pg_shaper_cfg(hdev); 868 if (ret) 869 return ret; 870 871 return hclge_tm_pri_shaper_cfg(hdev); 872 } 873 874 int hclge_tm_dwrr_cfg(struct hclge_dev *hdev) 875 { 876 int ret; 877 878 ret = hclge_tm_pg_dwrr_cfg(hdev); 879 if (ret) 880 return ret; 881 882 return hclge_tm_pri_dwrr_cfg(hdev); 883 } 884 885 static int hclge_tm_lvl2_schd_mode_cfg(struct hclge_dev *hdev) 886 { 887 int ret; 888 u8 i; 889 890 /* Only being config on TC-Based scheduler mode */ 891 if (hdev->tx_sch_mode == HCLGE_FLAG_VNET_BASE_SCH_MODE) 892 return 0; 893 894 for (i = 0; i < hdev->tm_info.num_pg; i++) { 895 ret = hclge_tm_pg_schd_mode_cfg(hdev, i); 896 if (ret) 897 return ret; 898 } 899 900 return 0; 901 } 902 903 static int hclge_tm_schd_mode_vnet_base_cfg(struct hclge_vport *vport) 904 { 905 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 906 struct hclge_dev *hdev = vport->back; 907 int ret; 908 u8 i; 909 910 ret = hclge_tm_pri_schd_mode_cfg(hdev, vport->vport_id); 911 if (ret) 912 return ret; 913 914 for (i = 0; i < kinfo->num_tc; i++) { 915 ret = hclge_tm_qs_schd_mode_cfg(hdev, vport->qs_offset + i); 916 if (ret) 917 return ret; 918 } 919 920 return 0; 921 } 922 923 static int hclge_tm_lvl34_schd_mode_cfg(struct hclge_dev *hdev) 924 { 925 struct hclge_vport *vport = hdev->vport; 926 int ret; 927 u8 i; 928 929 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) { 930 for (i = 0; i < hdev->tm_info.num_tc; i++) { 931 ret = hclge_tm_pri_schd_mode_cfg(hdev, i); 932 if (ret) 933 return ret; 934 935 ret = hclge_tm_qs_schd_mode_cfg(hdev, i); 936 if (ret) 937 return ret; 938 } 939 } else { 940 for (i = 0; i < hdev->num_alloc_vport; i++) { 941 ret = hclge_tm_schd_mode_vnet_base_cfg(vport); 942 if (ret) 943 return ret; 944 945 vport++; 946 } 947 } 948 949 return 0; 950 } 951 952 static int hclge_tm_schd_mode_hw(struct hclge_dev *hdev) 953 { 954 int ret; 955 956 ret = hclge_tm_lvl2_schd_mode_cfg(hdev); 957 if (ret) 958 return ret; 959 960 return hclge_tm_lvl34_schd_mode_cfg(hdev); 961 } 962 963 static int hclge_tm_schd_setup_hw(struct hclge_dev *hdev) 964 { 965 int ret; 966 967 /* Cfg tm mapping */ 968 ret = hclge_tm_map_cfg(hdev); 969 if (ret) 970 return ret; 971 972 /* Cfg tm shaper */ 973 ret = hclge_tm_shaper_cfg(hdev); 974 if (ret) 975 return ret; 976 977 /* Cfg dwrr */ 978 ret = hclge_tm_dwrr_cfg(hdev); 979 if (ret) 980 return ret; 981 982 /* Cfg schd mode for each level schd */ 983 return hclge_tm_schd_mode_hw(hdev); 984 } 985 986 static int hclge_pfc_setup_hw(struct hclge_dev *hdev) 987 { 988 u8 enable_bitmap = 0; 989 990 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) 991 enable_bitmap = HCLGE_TX_MAC_PAUSE_EN_MSK | 992 HCLGE_RX_MAC_PAUSE_EN_MSK; 993 994 return hclge_pfc_pause_en_cfg(hdev, enable_bitmap, 995 hdev->tm_info.hw_pfc_map); 996 } 997 998 static int hclge_mac_pause_setup_hw(struct hclge_dev *hdev) 999 { 1000 bool tx_en, rx_en; 1001 1002 switch (hdev->tm_info.fc_mode) { 1003 case HCLGE_FC_NONE: 1004 tx_en = false; 1005 rx_en = false; 1006 break; 1007 case HCLGE_FC_RX_PAUSE: 1008 tx_en = false; 1009 rx_en = true; 1010 break; 1011 case HCLGE_FC_TX_PAUSE: 1012 tx_en = true; 1013 rx_en = false; 1014 break; 1015 case HCLGE_FC_FULL: 1016 tx_en = true; 1017 rx_en = true; 1018 break; 1019 default: 1020 tx_en = true; 1021 rx_en = true; 1022 } 1023 1024 return hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); 1025 } 1026 1027 int hclge_pause_setup_hw(struct hclge_dev *hdev) 1028 { 1029 int ret; 1030 u8 i; 1031 1032 if (hdev->tm_info.fc_mode != HCLGE_FC_PFC) 1033 return hclge_mac_pause_setup_hw(hdev); 1034 1035 /* Only DCB-supported dev supports qset back pressure and pfc cmd */ 1036 if (!hnae3_dev_dcb_supported(hdev)) 1037 return 0; 1038 1039 /* When MAC is GE Mode, hdev does not support pfc setting */ 1040 ret = hclge_pfc_setup_hw(hdev); 1041 if (ret) 1042 dev_warn(&hdev->pdev->dev, "set pfc pause failed:%d\n", ret); 1043 1044 for (i = 0; i < hdev->tm_info.num_tc; i++) { 1045 ret = hclge_tm_qs_bp_cfg(hdev, i); 1046 if (ret) 1047 return ret; 1048 } 1049 1050 return hclge_up_to_tc_map(hdev); 1051 } 1052 1053 int hclge_tm_init_hw(struct hclge_dev *hdev) 1054 { 1055 int ret; 1056 1057 if ((hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) && 1058 (hdev->tx_sch_mode != HCLGE_FLAG_VNET_BASE_SCH_MODE)) 1059 return -ENOTSUPP; 1060 1061 ret = hclge_tm_schd_setup_hw(hdev); 1062 if (ret) 1063 return ret; 1064 1065 ret = hclge_pause_setup_hw(hdev); 1066 if (ret) 1067 return ret; 1068 1069 return 0; 1070 } 1071 1072 int hclge_tm_schd_init(struct hclge_dev *hdev) 1073 { 1074 int ret = hclge_tm_schd_info_init(hdev); 1075 1076 if (ret) 1077 return ret; 1078 1079 return hclge_tm_init_hw(hdev); 1080 } 1081