1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 6 #include "hclge_cmd.h" 7 #include "hclge_main.h" 8 #include "hclge_tm.h" 9 10 enum hclge_shaper_level { 11 HCLGE_SHAPER_LVL_PRI = 0, 12 HCLGE_SHAPER_LVL_PG = 1, 13 HCLGE_SHAPER_LVL_PORT = 2, 14 HCLGE_SHAPER_LVL_QSET = 3, 15 HCLGE_SHAPER_LVL_CNT = 4, 16 HCLGE_SHAPER_LVL_VF = 0, 17 HCLGE_SHAPER_LVL_PF = 1, 18 }; 19 20 #define HCLGE_TM_PFC_PKT_GET_CMD_NUM 3 21 #define HCLGE_TM_PFC_NUM_GET_PER_CMD 3 22 23 #define HCLGE_SHAPER_BS_U_DEF 5 24 #define HCLGE_SHAPER_BS_S_DEF 20 25 26 /* hclge_shaper_para_calc: calculate ir parameter for the shaper 27 * @ir: Rate to be config, its unit is Mbps 28 * @shaper_level: the shaper level. eg: port, pg, priority, queueset 29 * @ir_para: parameters of IR shaper 30 * @max_tm_rate: max tm rate is available to config 31 * 32 * the formula: 33 * 34 * IR_b * (2 ^ IR_u) * 8 35 * IR(Mbps) = ------------------------- * CLOCK(1000Mbps) 36 * Tick * (2 ^ IR_s) 37 * 38 * @return: 0: calculate sucessful, negative: fail 39 */ 40 static int hclge_shaper_para_calc(u32 ir, u8 shaper_level, 41 struct hclge_shaper_ir_para *ir_para, 42 u32 max_tm_rate) 43 { 44 #define DIVISOR_CLK (1000 * 8) 45 #define DIVISOR_IR_B_126 (126 * DIVISOR_CLK) 46 47 static const u16 tick_array[HCLGE_SHAPER_LVL_CNT] = { 48 6 * 256, /* Prioriy level */ 49 6 * 32, /* Prioriy group level */ 50 6 * 8, /* Port level */ 51 6 * 256 /* Qset level */ 52 }; 53 u8 ir_u_calc = 0; 54 u8 ir_s_calc = 0; 55 u32 ir_calc; 56 u32 tick; 57 58 /* Calc tick */ 59 if (shaper_level >= HCLGE_SHAPER_LVL_CNT || 60 ir > max_tm_rate) 61 return -EINVAL; 62 63 tick = tick_array[shaper_level]; 64 65 /** 66 * Calc the speed if ir_b = 126, ir_u = 0 and ir_s = 0 67 * the formula is changed to: 68 * 126 * 1 * 8 69 * ir_calc = ---------------- * 1000 70 * tick * 1 71 */ 72 ir_calc = (DIVISOR_IR_B_126 + (tick >> 1) - 1) / tick; 73 74 if (ir_calc == ir) { 75 ir_para->ir_b = 126; 76 ir_para->ir_u = 0; 77 ir_para->ir_s = 0; 78 79 return 0; 80 } else if (ir_calc > ir) { 81 /* Increasing the denominator to select ir_s value */ 82 while (ir_calc >= ir && ir) { 83 ir_s_calc++; 84 ir_calc = DIVISOR_IR_B_126 / (tick * (1 << ir_s_calc)); 85 } 86 87 ir_para->ir_b = (ir * tick * (1 << ir_s_calc) + 88 (DIVISOR_CLK >> 1)) / DIVISOR_CLK; 89 } else { 90 /* Increasing the numerator to select ir_u value */ 91 u32 numerator; 92 93 while (ir_calc < ir) { 94 ir_u_calc++; 95 numerator = DIVISOR_IR_B_126 * (1 << ir_u_calc); 96 ir_calc = (numerator + (tick >> 1)) / tick; 97 } 98 99 if (ir_calc == ir) { 100 ir_para->ir_b = 126; 101 } else { 102 u32 denominator = DIVISOR_CLK * (1 << --ir_u_calc); 103 ir_para->ir_b = (ir * tick + (denominator >> 1)) / 104 denominator; 105 } 106 } 107 108 ir_para->ir_u = ir_u_calc; 109 ir_para->ir_s = ir_s_calc; 110 111 return 0; 112 } 113 114 static int hclge_pfc_stats_get(struct hclge_dev *hdev, 115 enum hclge_opcode_type opcode, u64 *stats) 116 { 117 struct hclge_desc desc[HCLGE_TM_PFC_PKT_GET_CMD_NUM]; 118 int ret, i, j; 119 120 if (!(opcode == HCLGE_OPC_QUERY_PFC_RX_PKT_CNT || 121 opcode == HCLGE_OPC_QUERY_PFC_TX_PKT_CNT)) 122 return -EINVAL; 123 124 for (i = 0; i < HCLGE_TM_PFC_PKT_GET_CMD_NUM - 1; i++) { 125 hclge_cmd_setup_basic_desc(&desc[i], opcode, true); 126 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 127 } 128 129 hclge_cmd_setup_basic_desc(&desc[i], opcode, true); 130 131 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_TM_PFC_PKT_GET_CMD_NUM); 132 if (ret) 133 return ret; 134 135 for (i = 0; i < HCLGE_TM_PFC_PKT_GET_CMD_NUM; i++) { 136 struct hclge_pfc_stats_cmd *pfc_stats = 137 (struct hclge_pfc_stats_cmd *)desc[i].data; 138 139 for (j = 0; j < HCLGE_TM_PFC_NUM_GET_PER_CMD; j++) { 140 u32 index = i * HCLGE_TM_PFC_PKT_GET_CMD_NUM + j; 141 142 if (index < HCLGE_MAX_TC_NUM) 143 stats[index] = 144 le64_to_cpu(pfc_stats->pkt_num[j]); 145 } 146 } 147 return 0; 148 } 149 150 int hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats) 151 { 152 return hclge_pfc_stats_get(hdev, HCLGE_OPC_QUERY_PFC_RX_PKT_CNT, stats); 153 } 154 155 int hclge_pfc_tx_stats_get(struct hclge_dev *hdev, u64 *stats) 156 { 157 return hclge_pfc_stats_get(hdev, HCLGE_OPC_QUERY_PFC_TX_PKT_CNT, stats); 158 } 159 160 int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx) 161 { 162 struct hclge_desc desc; 163 164 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PAUSE_EN, false); 165 166 desc.data[0] = cpu_to_le32((tx ? HCLGE_TX_MAC_PAUSE_EN_MSK : 0) | 167 (rx ? HCLGE_RX_MAC_PAUSE_EN_MSK : 0)); 168 169 return hclge_cmd_send(&hdev->hw, &desc, 1); 170 } 171 172 static int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap, 173 u8 pfc_bitmap) 174 { 175 struct hclge_desc desc; 176 struct hclge_pfc_en_cmd *pfc = (struct hclge_pfc_en_cmd *)desc.data; 177 178 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PFC_PAUSE_EN, false); 179 180 pfc->tx_rx_en_bitmap = tx_rx_bitmap; 181 pfc->pri_en_bitmap = pfc_bitmap; 182 183 return hclge_cmd_send(&hdev->hw, &desc, 1); 184 } 185 186 static int hclge_pause_param_cfg(struct hclge_dev *hdev, const u8 *addr, 187 u8 pause_trans_gap, u16 pause_trans_time) 188 { 189 struct hclge_cfg_pause_param_cmd *pause_param; 190 struct hclge_desc desc; 191 192 pause_param = (struct hclge_cfg_pause_param_cmd *)desc.data; 193 194 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, false); 195 196 ether_addr_copy(pause_param->mac_addr, addr); 197 ether_addr_copy(pause_param->mac_addr_extra, addr); 198 pause_param->pause_trans_gap = pause_trans_gap; 199 pause_param->pause_trans_time = cpu_to_le16(pause_trans_time); 200 201 return hclge_cmd_send(&hdev->hw, &desc, 1); 202 } 203 204 int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr) 205 { 206 struct hclge_cfg_pause_param_cmd *pause_param; 207 struct hclge_desc desc; 208 u16 trans_time; 209 u8 trans_gap; 210 int ret; 211 212 pause_param = (struct hclge_cfg_pause_param_cmd *)desc.data; 213 214 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, true); 215 216 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 217 if (ret) 218 return ret; 219 220 trans_gap = pause_param->pause_trans_gap; 221 trans_time = le16_to_cpu(pause_param->pause_trans_time); 222 223 return hclge_pause_param_cfg(hdev, mac_addr, trans_gap, trans_time); 224 } 225 226 static int hclge_fill_pri_array(struct hclge_dev *hdev, u8 *pri, u8 pri_id) 227 { 228 u8 tc; 229 230 tc = hdev->tm_info.prio_tc[pri_id]; 231 232 if (tc >= hdev->tm_info.num_tc) 233 return -EINVAL; 234 235 /** 236 * the register for priority has four bytes, the first bytes includes 237 * priority0 and priority1, the higher 4bit stands for priority1 238 * while the lower 4bit stands for priority0, as below: 239 * first byte: | pri_1 | pri_0 | 240 * second byte: | pri_3 | pri_2 | 241 * third byte: | pri_5 | pri_4 | 242 * fourth byte: | pri_7 | pri_6 | 243 */ 244 pri[pri_id >> 1] |= tc << ((pri_id & 1) * 4); 245 246 return 0; 247 } 248 249 static int hclge_up_to_tc_map(struct hclge_dev *hdev) 250 { 251 struct hclge_desc desc; 252 u8 *pri = (u8 *)desc.data; 253 u8 pri_id; 254 int ret; 255 256 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PRI_TO_TC_MAPPING, false); 257 258 for (pri_id = 0; pri_id < HNAE3_MAX_USER_PRIO; pri_id++) { 259 ret = hclge_fill_pri_array(hdev, pri, pri_id); 260 if (ret) 261 return ret; 262 } 263 264 return hclge_cmd_send(&hdev->hw, &desc, 1); 265 } 266 267 static int hclge_tm_pg_to_pri_map_cfg(struct hclge_dev *hdev, 268 u8 pg_id, u8 pri_bit_map) 269 { 270 struct hclge_pg_to_pri_link_cmd *map; 271 struct hclge_desc desc; 272 273 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_TO_PRI_LINK, false); 274 275 map = (struct hclge_pg_to_pri_link_cmd *)desc.data; 276 277 map->pg_id = pg_id; 278 map->pri_bit_map = pri_bit_map; 279 280 return hclge_cmd_send(&hdev->hw, &desc, 1); 281 } 282 283 static int hclge_tm_qs_to_pri_map_cfg(struct hclge_dev *hdev, 284 u16 qs_id, u8 pri) 285 { 286 struct hclge_qs_to_pri_link_cmd *map; 287 struct hclge_desc desc; 288 289 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_TO_PRI_LINK, false); 290 291 map = (struct hclge_qs_to_pri_link_cmd *)desc.data; 292 293 map->qs_id = cpu_to_le16(qs_id); 294 map->priority = pri; 295 map->link_vld = HCLGE_TM_QS_PRI_LINK_VLD_MSK; 296 297 return hclge_cmd_send(&hdev->hw, &desc, 1); 298 } 299 300 static int hclge_tm_q_to_qs_map_cfg(struct hclge_dev *hdev, 301 u16 q_id, u16 qs_id) 302 { 303 struct hclge_nq_to_qs_link_cmd *map; 304 struct hclge_desc desc; 305 u16 qs_id_l; 306 u16 qs_id_h; 307 308 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_NQ_TO_QS_LINK, false); 309 310 map = (struct hclge_nq_to_qs_link_cmd *)desc.data; 311 312 map->nq_id = cpu_to_le16(q_id); 313 314 /* convert qs_id to the following format to support qset_id >= 1024 315 * qs_id: | 15 | 14 ~ 10 | 9 ~ 0 | 316 * / / \ \ 317 * / / \ \ 318 * qset_id: | 15 ~ 11 | 10 | 9 ~ 0 | 319 * | qs_id_h | vld | qs_id_l | 320 */ 321 qs_id_l = hnae3_get_field(qs_id, HCLGE_TM_QS_ID_L_MSK, 322 HCLGE_TM_QS_ID_L_S); 323 qs_id_h = hnae3_get_field(qs_id, HCLGE_TM_QS_ID_H_MSK, 324 HCLGE_TM_QS_ID_H_S); 325 hnae3_set_field(qs_id, HCLGE_TM_QS_ID_L_MSK, HCLGE_TM_QS_ID_L_S, 326 qs_id_l); 327 hnae3_set_field(qs_id, HCLGE_TM_QS_ID_H_EXT_MSK, HCLGE_TM_QS_ID_H_EXT_S, 328 qs_id_h); 329 map->qset_id = cpu_to_le16(qs_id | HCLGE_TM_Q_QS_LINK_VLD_MSK); 330 331 return hclge_cmd_send(&hdev->hw, &desc, 1); 332 } 333 334 static int hclge_tm_pg_weight_cfg(struct hclge_dev *hdev, u8 pg_id, 335 u8 dwrr) 336 { 337 struct hclge_pg_weight_cmd *weight; 338 struct hclge_desc desc; 339 340 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_WEIGHT, false); 341 342 weight = (struct hclge_pg_weight_cmd *)desc.data; 343 344 weight->pg_id = pg_id; 345 weight->dwrr = dwrr; 346 347 return hclge_cmd_send(&hdev->hw, &desc, 1); 348 } 349 350 static int hclge_tm_pri_weight_cfg(struct hclge_dev *hdev, u8 pri_id, 351 u8 dwrr) 352 { 353 struct hclge_priority_weight_cmd *weight; 354 struct hclge_desc desc; 355 356 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_WEIGHT, false); 357 358 weight = (struct hclge_priority_weight_cmd *)desc.data; 359 360 weight->pri_id = pri_id; 361 weight->dwrr = dwrr; 362 363 return hclge_cmd_send(&hdev->hw, &desc, 1); 364 } 365 366 static int hclge_tm_qs_weight_cfg(struct hclge_dev *hdev, u16 qs_id, 367 u8 dwrr) 368 { 369 struct hclge_qs_weight_cmd *weight; 370 struct hclge_desc desc; 371 372 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_WEIGHT, false); 373 374 weight = (struct hclge_qs_weight_cmd *)desc.data; 375 376 weight->qs_id = cpu_to_le16(qs_id); 377 weight->dwrr = dwrr; 378 379 return hclge_cmd_send(&hdev->hw, &desc, 1); 380 } 381 382 static u32 hclge_tm_get_shapping_para(u8 ir_b, u8 ir_u, u8 ir_s, 383 u8 bs_b, u8 bs_s) 384 { 385 u32 shapping_para = 0; 386 387 hclge_tm_set_field(shapping_para, IR_B, ir_b); 388 hclge_tm_set_field(shapping_para, IR_U, ir_u); 389 hclge_tm_set_field(shapping_para, IR_S, ir_s); 390 hclge_tm_set_field(shapping_para, BS_B, bs_b); 391 hclge_tm_set_field(shapping_para, BS_S, bs_s); 392 393 return shapping_para; 394 } 395 396 static int hclge_tm_pg_shapping_cfg(struct hclge_dev *hdev, 397 enum hclge_shap_bucket bucket, u8 pg_id, 398 u32 shapping_para, u32 rate) 399 { 400 struct hclge_pg_shapping_cmd *shap_cfg_cmd; 401 enum hclge_opcode_type opcode; 402 struct hclge_desc desc; 403 404 opcode = bucket ? HCLGE_OPC_TM_PG_P_SHAPPING : 405 HCLGE_OPC_TM_PG_C_SHAPPING; 406 hclge_cmd_setup_basic_desc(&desc, opcode, false); 407 408 shap_cfg_cmd = (struct hclge_pg_shapping_cmd *)desc.data; 409 410 shap_cfg_cmd->pg_id = pg_id; 411 412 shap_cfg_cmd->pg_shapping_para = cpu_to_le32(shapping_para); 413 414 hnae3_set_bit(shap_cfg_cmd->flag, HCLGE_TM_RATE_VLD, 1); 415 416 shap_cfg_cmd->pg_rate = cpu_to_le32(rate); 417 418 return hclge_cmd_send(&hdev->hw, &desc, 1); 419 } 420 421 static int hclge_tm_port_shaper_cfg(struct hclge_dev *hdev) 422 { 423 struct hclge_port_shapping_cmd *shap_cfg_cmd; 424 struct hclge_shaper_ir_para ir_para; 425 struct hclge_desc desc; 426 u32 shapping_para; 427 int ret; 428 429 ret = hclge_shaper_para_calc(hdev->hw.mac.speed, HCLGE_SHAPER_LVL_PORT, 430 &ir_para, 431 hdev->ae_dev->dev_specs.max_tm_rate); 432 if (ret) 433 return ret; 434 435 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PORT_SHAPPING, false); 436 shap_cfg_cmd = (struct hclge_port_shapping_cmd *)desc.data; 437 438 shapping_para = hclge_tm_get_shapping_para(ir_para.ir_b, ir_para.ir_u, 439 ir_para.ir_s, 440 HCLGE_SHAPER_BS_U_DEF, 441 HCLGE_SHAPER_BS_S_DEF); 442 443 shap_cfg_cmd->port_shapping_para = cpu_to_le32(shapping_para); 444 445 hnae3_set_bit(shap_cfg_cmd->flag, HCLGE_TM_RATE_VLD, 1); 446 447 shap_cfg_cmd->port_rate = cpu_to_le32(hdev->hw.mac.speed); 448 449 return hclge_cmd_send(&hdev->hw, &desc, 1); 450 } 451 452 static int hclge_tm_pri_shapping_cfg(struct hclge_dev *hdev, 453 enum hclge_shap_bucket bucket, u8 pri_id, 454 u32 shapping_para, u32 rate) 455 { 456 struct hclge_pri_shapping_cmd *shap_cfg_cmd; 457 enum hclge_opcode_type opcode; 458 struct hclge_desc desc; 459 460 opcode = bucket ? HCLGE_OPC_TM_PRI_P_SHAPPING : 461 HCLGE_OPC_TM_PRI_C_SHAPPING; 462 463 hclge_cmd_setup_basic_desc(&desc, opcode, false); 464 465 shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data; 466 467 shap_cfg_cmd->pri_id = pri_id; 468 469 shap_cfg_cmd->pri_shapping_para = cpu_to_le32(shapping_para); 470 471 hnae3_set_bit(shap_cfg_cmd->flag, HCLGE_TM_RATE_VLD, 1); 472 473 shap_cfg_cmd->pri_rate = cpu_to_le32(rate); 474 475 return hclge_cmd_send(&hdev->hw, &desc, 1); 476 } 477 478 static int hclge_tm_pg_schd_mode_cfg(struct hclge_dev *hdev, u8 pg_id) 479 { 480 struct hclge_desc desc; 481 482 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_SCH_MODE_CFG, false); 483 484 if (hdev->tm_info.pg_info[pg_id].pg_sch_mode == HCLGE_SCH_MODE_DWRR) 485 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK); 486 else 487 desc.data[1] = 0; 488 489 desc.data[0] = cpu_to_le32(pg_id); 490 491 return hclge_cmd_send(&hdev->hw, &desc, 1); 492 } 493 494 static int hclge_tm_pri_schd_mode_cfg(struct hclge_dev *hdev, u8 pri_id) 495 { 496 struct hclge_desc desc; 497 498 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_SCH_MODE_CFG, false); 499 500 if (hdev->tm_info.tc_info[pri_id].tc_sch_mode == HCLGE_SCH_MODE_DWRR) 501 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK); 502 else 503 desc.data[1] = 0; 504 505 desc.data[0] = cpu_to_le32(pri_id); 506 507 return hclge_cmd_send(&hdev->hw, &desc, 1); 508 } 509 510 static int hclge_tm_qs_schd_mode_cfg(struct hclge_dev *hdev, u16 qs_id, u8 mode) 511 { 512 struct hclge_desc desc; 513 514 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_SCH_MODE_CFG, false); 515 516 if (mode == HCLGE_SCH_MODE_DWRR) 517 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK); 518 else 519 desc.data[1] = 0; 520 521 desc.data[0] = cpu_to_le32(qs_id); 522 523 return hclge_cmd_send(&hdev->hw, &desc, 1); 524 } 525 526 static int hclge_tm_qs_bp_cfg(struct hclge_dev *hdev, u8 tc, u8 grp_id, 527 u32 bit_map) 528 { 529 struct hclge_bp_to_qs_map_cmd *bp_to_qs_map_cmd; 530 struct hclge_desc desc; 531 532 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_BP_TO_QSET_MAPPING, 533 false); 534 535 bp_to_qs_map_cmd = (struct hclge_bp_to_qs_map_cmd *)desc.data; 536 537 bp_to_qs_map_cmd->tc_id = tc; 538 bp_to_qs_map_cmd->qs_group_id = grp_id; 539 bp_to_qs_map_cmd->qs_bit_map = cpu_to_le32(bit_map); 540 541 return hclge_cmd_send(&hdev->hw, &desc, 1); 542 } 543 544 int hclge_tm_qs_shaper_cfg(struct hclge_vport *vport, int max_tx_rate) 545 { 546 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 547 struct hclge_qs_shapping_cmd *shap_cfg_cmd; 548 struct hclge_shaper_ir_para ir_para; 549 struct hclge_dev *hdev = vport->back; 550 struct hclge_desc desc; 551 u32 shaper_para; 552 int ret, i; 553 554 if (!max_tx_rate) 555 max_tx_rate = hdev->ae_dev->dev_specs.max_tm_rate; 556 557 ret = hclge_shaper_para_calc(max_tx_rate, HCLGE_SHAPER_LVL_QSET, 558 &ir_para, 559 hdev->ae_dev->dev_specs.max_tm_rate); 560 if (ret) 561 return ret; 562 563 shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b, ir_para.ir_u, 564 ir_para.ir_s, 565 HCLGE_SHAPER_BS_U_DEF, 566 HCLGE_SHAPER_BS_S_DEF); 567 568 for (i = 0; i < kinfo->tc_info.num_tc; i++) { 569 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QCN_SHAPPING_CFG, 570 false); 571 572 shap_cfg_cmd = (struct hclge_qs_shapping_cmd *)desc.data; 573 shap_cfg_cmd->qs_id = cpu_to_le16(vport->qs_offset + i); 574 shap_cfg_cmd->qs_shapping_para = cpu_to_le32(shaper_para); 575 576 hnae3_set_bit(shap_cfg_cmd->flag, HCLGE_TM_RATE_VLD, 1); 577 shap_cfg_cmd->qs_rate = cpu_to_le32(max_tx_rate); 578 579 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 580 if (ret) { 581 dev_err(&hdev->pdev->dev, 582 "vf%u, qs%u failed to set tx_rate:%d, ret=%d\n", 583 vport->vport_id, shap_cfg_cmd->qs_id, 584 max_tx_rate, ret); 585 return ret; 586 } 587 } 588 589 return 0; 590 } 591 592 static u16 hclge_vport_get_max_rss_size(struct hclge_vport *vport) 593 { 594 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 595 struct hnae3_tc_info *tc_info = &kinfo->tc_info; 596 struct hclge_dev *hdev = vport->back; 597 u16 max_rss_size = 0; 598 int i; 599 600 if (!tc_info->mqprio_active) 601 return vport->alloc_tqps / tc_info->num_tc; 602 603 for (i = 0; i < HNAE3_MAX_TC; i++) { 604 if (!(hdev->hw_tc_map & BIT(i)) || i >= tc_info->num_tc) 605 continue; 606 if (max_rss_size < tc_info->tqp_count[i]) 607 max_rss_size = tc_info->tqp_count[i]; 608 } 609 610 return max_rss_size; 611 } 612 613 static u16 hclge_vport_get_tqp_num(struct hclge_vport *vport) 614 { 615 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 616 struct hnae3_tc_info *tc_info = &kinfo->tc_info; 617 struct hclge_dev *hdev = vport->back; 618 int sum = 0; 619 int i; 620 621 if (!tc_info->mqprio_active) 622 return kinfo->rss_size * tc_info->num_tc; 623 624 for (i = 0; i < HNAE3_MAX_TC; i++) { 625 if (hdev->hw_tc_map & BIT(i) && i < tc_info->num_tc) 626 sum += tc_info->tqp_count[i]; 627 } 628 629 return sum; 630 } 631 632 static void hclge_tm_vport_tc_info_update(struct hclge_vport *vport) 633 { 634 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 635 struct hclge_dev *hdev = vport->back; 636 u16 vport_max_rss_size; 637 u16 max_rss_size; 638 u8 i; 639 640 /* TC configuration is shared by PF/VF in one port, only allow 641 * one tc for VF for simplicity. VF's vport_id is non zero. 642 */ 643 kinfo->tc_info.num_tc = vport->vport_id ? 1 : 644 min_t(u16, vport->alloc_tqps, hdev->tm_info.num_tc); 645 vport->qs_offset = (vport->vport_id ? HNAE3_MAX_TC : 0) + 646 (vport->vport_id ? (vport->vport_id - 1) : 0); 647 648 vport_max_rss_size = vport->vport_id ? hdev->vf_rss_size_max : 649 hdev->pf_rss_size_max; 650 max_rss_size = min_t(u16, vport_max_rss_size, 651 hclge_vport_get_max_rss_size(vport)); 652 653 /* Set to user value, no larger than max_rss_size. */ 654 if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 655 kinfo->req_rss_size <= max_rss_size) { 656 dev_info(&hdev->pdev->dev, "rss changes from %u to %u\n", 657 kinfo->rss_size, kinfo->req_rss_size); 658 kinfo->rss_size = kinfo->req_rss_size; 659 } else if (kinfo->rss_size > max_rss_size || 660 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) { 661 /* if user not set rss, the rss_size should compare with the 662 * valid msi numbers to ensure one to one map between tqp and 663 * irq as default. 664 */ 665 if (!kinfo->req_rss_size) 666 max_rss_size = min_t(u16, max_rss_size, 667 (hdev->num_nic_msi - 1) / 668 kinfo->tc_info.num_tc); 669 670 /* Set to the maximum specification value (max_rss_size). */ 671 kinfo->rss_size = max_rss_size; 672 } 673 674 kinfo->num_tqps = hclge_vport_get_tqp_num(vport); 675 vport->dwrr = 100; /* 100 percent as init */ 676 vport->alloc_rss_size = kinfo->rss_size; 677 vport->bw_limit = hdev->tm_info.pg_info[0].bw_limit; 678 679 /* when enable mqprio, the tc_info has been updated. */ 680 if (kinfo->tc_info.mqprio_active) 681 return; 682 683 for (i = 0; i < HNAE3_MAX_TC; i++) { 684 if (hdev->hw_tc_map & BIT(i) && i < kinfo->tc_info.num_tc) { 685 set_bit(i, &kinfo->tc_info.tc_en); 686 kinfo->tc_info.tqp_offset[i] = i * kinfo->rss_size; 687 kinfo->tc_info.tqp_count[i] = kinfo->rss_size; 688 } else { 689 /* Set to default queue if TC is disable */ 690 clear_bit(i, &kinfo->tc_info.tc_en); 691 kinfo->tc_info.tqp_offset[i] = 0; 692 kinfo->tc_info.tqp_count[i] = 1; 693 } 694 } 695 696 memcpy(kinfo->tc_info.prio_tc, hdev->tm_info.prio_tc, 697 sizeof_field(struct hnae3_tc_info, prio_tc)); 698 } 699 700 static void hclge_tm_vport_info_update(struct hclge_dev *hdev) 701 { 702 struct hclge_vport *vport = hdev->vport; 703 u32 i; 704 705 for (i = 0; i < hdev->num_alloc_vport; i++) { 706 hclge_tm_vport_tc_info_update(vport); 707 708 vport++; 709 } 710 } 711 712 static void hclge_tm_tc_info_init(struct hclge_dev *hdev) 713 { 714 u8 i; 715 716 for (i = 0; i < hdev->tm_info.num_tc; i++) { 717 hdev->tm_info.tc_info[i].tc_id = i; 718 hdev->tm_info.tc_info[i].tc_sch_mode = HCLGE_SCH_MODE_DWRR; 719 hdev->tm_info.tc_info[i].pgid = 0; 720 hdev->tm_info.tc_info[i].bw_limit = 721 hdev->tm_info.pg_info[0].bw_limit; 722 } 723 724 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) 725 hdev->tm_info.prio_tc[i] = 726 (i >= hdev->tm_info.num_tc) ? 0 : i; 727 728 /* DCB is enabled if we have more than 1 TC or pfc_en is 729 * non-zero. 730 */ 731 if (hdev->tm_info.num_tc > 1 || hdev->tm_info.pfc_en) 732 hdev->flag |= HCLGE_FLAG_DCB_ENABLE; 733 else 734 hdev->flag &= ~HCLGE_FLAG_DCB_ENABLE; 735 } 736 737 static void hclge_tm_pg_info_init(struct hclge_dev *hdev) 738 { 739 #define BW_PERCENT 100 740 741 u8 i; 742 743 for (i = 0; i < hdev->tm_info.num_pg; i++) { 744 int k; 745 746 hdev->tm_info.pg_dwrr[i] = i ? 0 : BW_PERCENT; 747 748 hdev->tm_info.pg_info[i].pg_id = i; 749 hdev->tm_info.pg_info[i].pg_sch_mode = HCLGE_SCH_MODE_DWRR; 750 751 hdev->tm_info.pg_info[i].bw_limit = 752 hdev->ae_dev->dev_specs.max_tm_rate; 753 754 if (i != 0) 755 continue; 756 757 hdev->tm_info.pg_info[i].tc_bit_map = hdev->hw_tc_map; 758 for (k = 0; k < hdev->tm_info.num_tc; k++) 759 hdev->tm_info.pg_info[i].tc_dwrr[k] = BW_PERCENT; 760 } 761 } 762 763 static void hclge_update_fc_mode_by_dcb_flag(struct hclge_dev *hdev) 764 { 765 if (!(hdev->flag & HCLGE_FLAG_DCB_ENABLE)) { 766 if (hdev->fc_mode_last_time == HCLGE_FC_PFC) 767 dev_warn(&hdev->pdev->dev, 768 "DCB is disable, but last mode is FC_PFC\n"); 769 770 hdev->tm_info.fc_mode = hdev->fc_mode_last_time; 771 } else if (hdev->tm_info.fc_mode != HCLGE_FC_PFC) { 772 /* fc_mode_last_time record the last fc_mode when 773 * DCB is enabled, so that fc_mode can be set to 774 * the correct value when DCB is disabled. 775 */ 776 hdev->fc_mode_last_time = hdev->tm_info.fc_mode; 777 hdev->tm_info.fc_mode = HCLGE_FC_PFC; 778 } 779 } 780 781 static void hclge_update_fc_mode(struct hclge_dev *hdev) 782 { 783 if (!hdev->tm_info.pfc_en) { 784 hdev->tm_info.fc_mode = hdev->fc_mode_last_time; 785 return; 786 } 787 788 if (hdev->tm_info.fc_mode != HCLGE_FC_PFC) { 789 hdev->fc_mode_last_time = hdev->tm_info.fc_mode; 790 hdev->tm_info.fc_mode = HCLGE_FC_PFC; 791 } 792 } 793 794 static void hclge_pfc_info_init(struct hclge_dev *hdev) 795 { 796 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 797 hclge_update_fc_mode(hdev); 798 else 799 hclge_update_fc_mode_by_dcb_flag(hdev); 800 } 801 802 static void hclge_tm_schd_info_init(struct hclge_dev *hdev) 803 { 804 hclge_tm_pg_info_init(hdev); 805 806 hclge_tm_tc_info_init(hdev); 807 808 hclge_tm_vport_info_update(hdev); 809 810 hclge_pfc_info_init(hdev); 811 } 812 813 static int hclge_tm_pg_to_pri_map(struct hclge_dev *hdev) 814 { 815 int ret; 816 u32 i; 817 818 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) 819 return 0; 820 821 for (i = 0; i < hdev->tm_info.num_pg; i++) { 822 /* Cfg mapping */ 823 ret = hclge_tm_pg_to_pri_map_cfg( 824 hdev, i, hdev->tm_info.pg_info[i].tc_bit_map); 825 if (ret) 826 return ret; 827 } 828 829 return 0; 830 } 831 832 static int hclge_tm_pg_shaper_cfg(struct hclge_dev *hdev) 833 { 834 u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate; 835 struct hclge_shaper_ir_para ir_para; 836 u32 shaper_para; 837 int ret; 838 u32 i; 839 840 /* Cfg pg schd */ 841 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) 842 return 0; 843 844 /* Pg to pri */ 845 for (i = 0; i < hdev->tm_info.num_pg; i++) { 846 u32 rate = hdev->tm_info.pg_info[i].bw_limit; 847 848 /* Calc shaper para */ 849 ret = hclge_shaper_para_calc(rate, HCLGE_SHAPER_LVL_PG, 850 &ir_para, max_tm_rate); 851 if (ret) 852 return ret; 853 854 shaper_para = hclge_tm_get_shapping_para(0, 0, 0, 855 HCLGE_SHAPER_BS_U_DEF, 856 HCLGE_SHAPER_BS_S_DEF); 857 ret = hclge_tm_pg_shapping_cfg(hdev, 858 HCLGE_TM_SHAP_C_BUCKET, i, 859 shaper_para, rate); 860 if (ret) 861 return ret; 862 863 shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b, 864 ir_para.ir_u, 865 ir_para.ir_s, 866 HCLGE_SHAPER_BS_U_DEF, 867 HCLGE_SHAPER_BS_S_DEF); 868 ret = hclge_tm_pg_shapping_cfg(hdev, 869 HCLGE_TM_SHAP_P_BUCKET, i, 870 shaper_para, rate); 871 if (ret) 872 return ret; 873 } 874 875 return 0; 876 } 877 878 static int hclge_tm_pg_dwrr_cfg(struct hclge_dev *hdev) 879 { 880 int ret; 881 u32 i; 882 883 /* cfg pg schd */ 884 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) 885 return 0; 886 887 /* pg to prio */ 888 for (i = 0; i < hdev->tm_info.num_pg; i++) { 889 /* Cfg dwrr */ 890 ret = hclge_tm_pg_weight_cfg(hdev, i, hdev->tm_info.pg_dwrr[i]); 891 if (ret) 892 return ret; 893 } 894 895 return 0; 896 } 897 898 static int hclge_vport_q_to_qs_map(struct hclge_dev *hdev, 899 struct hclge_vport *vport) 900 { 901 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 902 struct hnae3_tc_info *tc_info = &kinfo->tc_info; 903 struct hnae3_queue **tqp = kinfo->tqp; 904 u32 i, j; 905 int ret; 906 907 for (i = 0; i < tc_info->num_tc; i++) { 908 for (j = 0; j < tc_info->tqp_count[i]; j++) { 909 struct hnae3_queue *q = tqp[tc_info->tqp_offset[i] + j]; 910 911 ret = hclge_tm_q_to_qs_map_cfg(hdev, 912 hclge_get_queue_id(q), 913 vport->qs_offset + i); 914 if (ret) 915 return ret; 916 } 917 } 918 919 return 0; 920 } 921 922 static int hclge_tm_pri_q_qs_cfg(struct hclge_dev *hdev) 923 { 924 struct hclge_vport *vport = hdev->vport; 925 int ret; 926 u32 i, k; 927 928 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) { 929 /* Cfg qs -> pri mapping, one by one mapping */ 930 for (k = 0; k < hdev->num_alloc_vport; k++) { 931 struct hnae3_knic_private_info *kinfo = 932 &vport[k].nic.kinfo; 933 934 for (i = 0; i < kinfo->tc_info.num_tc; i++) { 935 ret = hclge_tm_qs_to_pri_map_cfg( 936 hdev, vport[k].qs_offset + i, i); 937 if (ret) 938 return ret; 939 } 940 } 941 } else if (hdev->tx_sch_mode == HCLGE_FLAG_VNET_BASE_SCH_MODE) { 942 /* Cfg qs -> pri mapping, qs = tc, pri = vf, 8 qs -> 1 pri */ 943 for (k = 0; k < hdev->num_alloc_vport; k++) 944 for (i = 0; i < HNAE3_MAX_TC; i++) { 945 ret = hclge_tm_qs_to_pri_map_cfg( 946 hdev, vport[k].qs_offset + i, k); 947 if (ret) 948 return ret; 949 } 950 } else { 951 return -EINVAL; 952 } 953 954 /* Cfg q -> qs mapping */ 955 for (i = 0; i < hdev->num_alloc_vport; i++) { 956 ret = hclge_vport_q_to_qs_map(hdev, vport); 957 if (ret) 958 return ret; 959 960 vport++; 961 } 962 963 return 0; 964 } 965 966 static int hclge_tm_pri_tc_base_shaper_cfg(struct hclge_dev *hdev) 967 { 968 u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate; 969 struct hclge_shaper_ir_para ir_para; 970 u32 shaper_para; 971 int ret; 972 u32 i; 973 974 for (i = 0; i < hdev->tm_info.num_tc; i++) { 975 u32 rate = hdev->tm_info.tc_info[i].bw_limit; 976 977 ret = hclge_shaper_para_calc(rate, HCLGE_SHAPER_LVL_PRI, 978 &ir_para, max_tm_rate); 979 if (ret) 980 return ret; 981 982 shaper_para = hclge_tm_get_shapping_para(0, 0, 0, 983 HCLGE_SHAPER_BS_U_DEF, 984 HCLGE_SHAPER_BS_S_DEF); 985 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_C_BUCKET, i, 986 shaper_para, rate); 987 if (ret) 988 return ret; 989 990 shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b, 991 ir_para.ir_u, 992 ir_para.ir_s, 993 HCLGE_SHAPER_BS_U_DEF, 994 HCLGE_SHAPER_BS_S_DEF); 995 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_P_BUCKET, i, 996 shaper_para, rate); 997 if (ret) 998 return ret; 999 } 1000 1001 return 0; 1002 } 1003 1004 static int hclge_tm_pri_vnet_base_shaper_pri_cfg(struct hclge_vport *vport) 1005 { 1006 struct hclge_dev *hdev = vport->back; 1007 struct hclge_shaper_ir_para ir_para; 1008 u32 shaper_para; 1009 int ret; 1010 1011 ret = hclge_shaper_para_calc(vport->bw_limit, HCLGE_SHAPER_LVL_VF, 1012 &ir_para, 1013 hdev->ae_dev->dev_specs.max_tm_rate); 1014 if (ret) 1015 return ret; 1016 1017 shaper_para = hclge_tm_get_shapping_para(0, 0, 0, 1018 HCLGE_SHAPER_BS_U_DEF, 1019 HCLGE_SHAPER_BS_S_DEF); 1020 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_C_BUCKET, 1021 vport->vport_id, shaper_para, 1022 vport->bw_limit); 1023 if (ret) 1024 return ret; 1025 1026 shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b, ir_para.ir_u, 1027 ir_para.ir_s, 1028 HCLGE_SHAPER_BS_U_DEF, 1029 HCLGE_SHAPER_BS_S_DEF); 1030 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_P_BUCKET, 1031 vport->vport_id, shaper_para, 1032 vport->bw_limit); 1033 if (ret) 1034 return ret; 1035 1036 return 0; 1037 } 1038 1039 static int hclge_tm_pri_vnet_base_shaper_qs_cfg(struct hclge_vport *vport) 1040 { 1041 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 1042 struct hclge_dev *hdev = vport->back; 1043 u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate; 1044 struct hclge_shaper_ir_para ir_para; 1045 u32 i; 1046 int ret; 1047 1048 for (i = 0; i < kinfo->tc_info.num_tc; i++) { 1049 ret = hclge_shaper_para_calc(hdev->tm_info.tc_info[i].bw_limit, 1050 HCLGE_SHAPER_LVL_QSET, 1051 &ir_para, max_tm_rate); 1052 if (ret) 1053 return ret; 1054 } 1055 1056 return 0; 1057 } 1058 1059 static int hclge_tm_pri_vnet_base_shaper_cfg(struct hclge_dev *hdev) 1060 { 1061 struct hclge_vport *vport = hdev->vport; 1062 int ret; 1063 u32 i; 1064 1065 /* Need config vport shaper */ 1066 for (i = 0; i < hdev->num_alloc_vport; i++) { 1067 ret = hclge_tm_pri_vnet_base_shaper_pri_cfg(vport); 1068 if (ret) 1069 return ret; 1070 1071 ret = hclge_tm_pri_vnet_base_shaper_qs_cfg(vport); 1072 if (ret) 1073 return ret; 1074 1075 vport++; 1076 } 1077 1078 return 0; 1079 } 1080 1081 static int hclge_tm_pri_shaper_cfg(struct hclge_dev *hdev) 1082 { 1083 int ret; 1084 1085 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) { 1086 ret = hclge_tm_pri_tc_base_shaper_cfg(hdev); 1087 if (ret) 1088 return ret; 1089 } else { 1090 ret = hclge_tm_pri_vnet_base_shaper_cfg(hdev); 1091 if (ret) 1092 return ret; 1093 } 1094 1095 return 0; 1096 } 1097 1098 static int hclge_tm_pri_tc_base_dwrr_cfg(struct hclge_dev *hdev) 1099 { 1100 struct hclge_vport *vport = hdev->vport; 1101 struct hclge_pg_info *pg_info; 1102 u8 dwrr; 1103 int ret; 1104 u32 i, k; 1105 1106 for (i = 0; i < hdev->tm_info.num_tc; i++) { 1107 pg_info = 1108 &hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid]; 1109 dwrr = pg_info->tc_dwrr[i]; 1110 1111 ret = hclge_tm_pri_weight_cfg(hdev, i, dwrr); 1112 if (ret) 1113 return ret; 1114 1115 for (k = 0; k < hdev->num_alloc_vport; k++) { 1116 ret = hclge_tm_qs_weight_cfg( 1117 hdev, vport[k].qs_offset + i, 1118 vport[k].dwrr); 1119 if (ret) 1120 return ret; 1121 } 1122 } 1123 1124 return 0; 1125 } 1126 1127 static int hclge_tm_ets_tc_dwrr_cfg(struct hclge_dev *hdev) 1128 { 1129 #define DEFAULT_TC_WEIGHT 1 1130 #define DEFAULT_TC_OFFSET 14 1131 1132 struct hclge_ets_tc_weight_cmd *ets_weight; 1133 struct hclge_desc desc; 1134 unsigned int i; 1135 1136 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ETS_TC_WEIGHT, false); 1137 ets_weight = (struct hclge_ets_tc_weight_cmd *)desc.data; 1138 1139 for (i = 0; i < HNAE3_MAX_TC; i++) { 1140 struct hclge_pg_info *pg_info; 1141 1142 ets_weight->tc_weight[i] = DEFAULT_TC_WEIGHT; 1143 1144 if (!(hdev->hw_tc_map & BIT(i))) 1145 continue; 1146 1147 pg_info = 1148 &hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid]; 1149 ets_weight->tc_weight[i] = pg_info->tc_dwrr[i]; 1150 } 1151 1152 ets_weight->weight_offset = DEFAULT_TC_OFFSET; 1153 1154 return hclge_cmd_send(&hdev->hw, &desc, 1); 1155 } 1156 1157 static int hclge_tm_pri_vnet_base_dwrr_pri_cfg(struct hclge_vport *vport) 1158 { 1159 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 1160 struct hclge_dev *hdev = vport->back; 1161 int ret; 1162 u8 i; 1163 1164 /* Vf dwrr */ 1165 ret = hclge_tm_pri_weight_cfg(hdev, vport->vport_id, vport->dwrr); 1166 if (ret) 1167 return ret; 1168 1169 /* Qset dwrr */ 1170 for (i = 0; i < kinfo->tc_info.num_tc; i++) { 1171 ret = hclge_tm_qs_weight_cfg( 1172 hdev, vport->qs_offset + i, 1173 hdev->tm_info.pg_info[0].tc_dwrr[i]); 1174 if (ret) 1175 return ret; 1176 } 1177 1178 return 0; 1179 } 1180 1181 static int hclge_tm_pri_vnet_base_dwrr_cfg(struct hclge_dev *hdev) 1182 { 1183 struct hclge_vport *vport = hdev->vport; 1184 int ret; 1185 u32 i; 1186 1187 for (i = 0; i < hdev->num_alloc_vport; i++) { 1188 ret = hclge_tm_pri_vnet_base_dwrr_pri_cfg(vport); 1189 if (ret) 1190 return ret; 1191 1192 vport++; 1193 } 1194 1195 return 0; 1196 } 1197 1198 static int hclge_tm_pri_dwrr_cfg(struct hclge_dev *hdev) 1199 { 1200 int ret; 1201 1202 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) { 1203 ret = hclge_tm_pri_tc_base_dwrr_cfg(hdev); 1204 if (ret) 1205 return ret; 1206 1207 if (!hnae3_dev_dcb_supported(hdev)) 1208 return 0; 1209 1210 ret = hclge_tm_ets_tc_dwrr_cfg(hdev); 1211 if (ret == -EOPNOTSUPP) { 1212 dev_warn(&hdev->pdev->dev, 1213 "fw %08x does't support ets tc weight cmd\n", 1214 hdev->fw_version); 1215 ret = 0; 1216 } 1217 1218 return ret; 1219 } else { 1220 ret = hclge_tm_pri_vnet_base_dwrr_cfg(hdev); 1221 if (ret) 1222 return ret; 1223 } 1224 1225 return 0; 1226 } 1227 1228 static int hclge_tm_map_cfg(struct hclge_dev *hdev) 1229 { 1230 int ret; 1231 1232 ret = hclge_up_to_tc_map(hdev); 1233 if (ret) 1234 return ret; 1235 1236 ret = hclge_tm_pg_to_pri_map(hdev); 1237 if (ret) 1238 return ret; 1239 1240 return hclge_tm_pri_q_qs_cfg(hdev); 1241 } 1242 1243 static int hclge_tm_shaper_cfg(struct hclge_dev *hdev) 1244 { 1245 int ret; 1246 1247 ret = hclge_tm_port_shaper_cfg(hdev); 1248 if (ret) 1249 return ret; 1250 1251 ret = hclge_tm_pg_shaper_cfg(hdev); 1252 if (ret) 1253 return ret; 1254 1255 return hclge_tm_pri_shaper_cfg(hdev); 1256 } 1257 1258 int hclge_tm_dwrr_cfg(struct hclge_dev *hdev) 1259 { 1260 int ret; 1261 1262 ret = hclge_tm_pg_dwrr_cfg(hdev); 1263 if (ret) 1264 return ret; 1265 1266 return hclge_tm_pri_dwrr_cfg(hdev); 1267 } 1268 1269 static int hclge_tm_lvl2_schd_mode_cfg(struct hclge_dev *hdev) 1270 { 1271 int ret; 1272 u8 i; 1273 1274 /* Only being config on TC-Based scheduler mode */ 1275 if (hdev->tx_sch_mode == HCLGE_FLAG_VNET_BASE_SCH_MODE) 1276 return 0; 1277 1278 for (i = 0; i < hdev->tm_info.num_pg; i++) { 1279 ret = hclge_tm_pg_schd_mode_cfg(hdev, i); 1280 if (ret) 1281 return ret; 1282 } 1283 1284 return 0; 1285 } 1286 1287 static int hclge_tm_schd_mode_vnet_base_cfg(struct hclge_vport *vport) 1288 { 1289 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 1290 struct hclge_dev *hdev = vport->back; 1291 int ret; 1292 u8 i; 1293 1294 if (vport->vport_id >= HNAE3_MAX_TC) 1295 return -EINVAL; 1296 1297 ret = hclge_tm_pri_schd_mode_cfg(hdev, vport->vport_id); 1298 if (ret) 1299 return ret; 1300 1301 for (i = 0; i < kinfo->tc_info.num_tc; i++) { 1302 u8 sch_mode = hdev->tm_info.tc_info[i].tc_sch_mode; 1303 1304 ret = hclge_tm_qs_schd_mode_cfg(hdev, vport->qs_offset + i, 1305 sch_mode); 1306 if (ret) 1307 return ret; 1308 } 1309 1310 return 0; 1311 } 1312 1313 static int hclge_tm_lvl34_schd_mode_cfg(struct hclge_dev *hdev) 1314 { 1315 struct hclge_vport *vport = hdev->vport; 1316 int ret; 1317 u8 i, k; 1318 1319 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) { 1320 for (i = 0; i < hdev->tm_info.num_tc; i++) { 1321 ret = hclge_tm_pri_schd_mode_cfg(hdev, i); 1322 if (ret) 1323 return ret; 1324 1325 for (k = 0; k < hdev->num_alloc_vport; k++) { 1326 ret = hclge_tm_qs_schd_mode_cfg( 1327 hdev, vport[k].qs_offset + i, 1328 HCLGE_SCH_MODE_DWRR); 1329 if (ret) 1330 return ret; 1331 } 1332 } 1333 } else { 1334 for (i = 0; i < hdev->num_alloc_vport; i++) { 1335 ret = hclge_tm_schd_mode_vnet_base_cfg(vport); 1336 if (ret) 1337 return ret; 1338 1339 vport++; 1340 } 1341 } 1342 1343 return 0; 1344 } 1345 1346 static int hclge_tm_schd_mode_hw(struct hclge_dev *hdev) 1347 { 1348 int ret; 1349 1350 ret = hclge_tm_lvl2_schd_mode_cfg(hdev); 1351 if (ret) 1352 return ret; 1353 1354 return hclge_tm_lvl34_schd_mode_cfg(hdev); 1355 } 1356 1357 int hclge_tm_schd_setup_hw(struct hclge_dev *hdev) 1358 { 1359 int ret; 1360 1361 /* Cfg tm mapping */ 1362 ret = hclge_tm_map_cfg(hdev); 1363 if (ret) 1364 return ret; 1365 1366 /* Cfg tm shaper */ 1367 ret = hclge_tm_shaper_cfg(hdev); 1368 if (ret) 1369 return ret; 1370 1371 /* Cfg dwrr */ 1372 ret = hclge_tm_dwrr_cfg(hdev); 1373 if (ret) 1374 return ret; 1375 1376 /* Cfg schd mode for each level schd */ 1377 return hclge_tm_schd_mode_hw(hdev); 1378 } 1379 1380 static int hclge_pause_param_setup_hw(struct hclge_dev *hdev) 1381 { 1382 struct hclge_mac *mac = &hdev->hw.mac; 1383 1384 return hclge_pause_param_cfg(hdev, mac->mac_addr, 1385 HCLGE_DEFAULT_PAUSE_TRANS_GAP, 1386 HCLGE_DEFAULT_PAUSE_TRANS_TIME); 1387 } 1388 1389 static int hclge_pfc_setup_hw(struct hclge_dev *hdev) 1390 { 1391 u8 enable_bitmap = 0; 1392 1393 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) 1394 enable_bitmap = HCLGE_TX_MAC_PAUSE_EN_MSK | 1395 HCLGE_RX_MAC_PAUSE_EN_MSK; 1396 1397 return hclge_pfc_pause_en_cfg(hdev, enable_bitmap, 1398 hdev->tm_info.pfc_en); 1399 } 1400 1401 /* for the queues that use for backpress, divides to several groups, 1402 * each group contains 32 queue sets, which can be represented by u32 bitmap. 1403 */ 1404 static int hclge_bp_setup_hw(struct hclge_dev *hdev, u8 tc) 1405 { 1406 u16 grp_id_shift = HCLGE_BP_GRP_ID_S; 1407 u16 grp_id_mask = HCLGE_BP_GRP_ID_M; 1408 u8 grp_num = HCLGE_BP_GRP_NUM; 1409 int i; 1410 1411 if (hdev->num_tqps > HCLGE_TQP_MAX_SIZE_DEV_V2) { 1412 grp_num = HCLGE_BP_EXT_GRP_NUM; 1413 grp_id_mask = HCLGE_BP_EXT_GRP_ID_M; 1414 grp_id_shift = HCLGE_BP_EXT_GRP_ID_S; 1415 } 1416 1417 for (i = 0; i < grp_num; i++) { 1418 u32 qs_bitmap = 0; 1419 int k, ret; 1420 1421 for (k = 0; k < hdev->num_alloc_vport; k++) { 1422 struct hclge_vport *vport = &hdev->vport[k]; 1423 u16 qs_id = vport->qs_offset + tc; 1424 u8 grp, sub_grp; 1425 1426 grp = hnae3_get_field(qs_id, grp_id_mask, grp_id_shift); 1427 sub_grp = hnae3_get_field(qs_id, HCLGE_BP_SUB_GRP_ID_M, 1428 HCLGE_BP_SUB_GRP_ID_S); 1429 if (i == grp) 1430 qs_bitmap |= (1 << sub_grp); 1431 } 1432 1433 ret = hclge_tm_qs_bp_cfg(hdev, tc, i, qs_bitmap); 1434 if (ret) 1435 return ret; 1436 } 1437 1438 return 0; 1439 } 1440 1441 static int hclge_mac_pause_setup_hw(struct hclge_dev *hdev) 1442 { 1443 bool tx_en, rx_en; 1444 1445 switch (hdev->tm_info.fc_mode) { 1446 case HCLGE_FC_NONE: 1447 tx_en = false; 1448 rx_en = false; 1449 break; 1450 case HCLGE_FC_RX_PAUSE: 1451 tx_en = false; 1452 rx_en = true; 1453 break; 1454 case HCLGE_FC_TX_PAUSE: 1455 tx_en = true; 1456 rx_en = false; 1457 break; 1458 case HCLGE_FC_FULL: 1459 tx_en = true; 1460 rx_en = true; 1461 break; 1462 case HCLGE_FC_PFC: 1463 tx_en = false; 1464 rx_en = false; 1465 break; 1466 default: 1467 tx_en = true; 1468 rx_en = true; 1469 } 1470 1471 return hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); 1472 } 1473 1474 static int hclge_tm_bp_setup(struct hclge_dev *hdev) 1475 { 1476 int ret; 1477 int i; 1478 1479 for (i = 0; i < hdev->tm_info.num_tc; i++) { 1480 ret = hclge_bp_setup_hw(hdev, i); 1481 if (ret) 1482 return ret; 1483 } 1484 1485 return 0; 1486 } 1487 1488 int hclge_pause_setup_hw(struct hclge_dev *hdev, bool init) 1489 { 1490 int ret; 1491 1492 ret = hclge_pause_param_setup_hw(hdev); 1493 if (ret) 1494 return ret; 1495 1496 ret = hclge_mac_pause_setup_hw(hdev); 1497 if (ret) 1498 return ret; 1499 1500 /* Only DCB-supported dev supports qset back pressure and pfc cmd */ 1501 if (!hnae3_dev_dcb_supported(hdev)) 1502 return 0; 1503 1504 /* GE MAC does not support PFC, when driver is initializing and MAC 1505 * is in GE Mode, ignore the error here, otherwise initialization 1506 * will fail. 1507 */ 1508 ret = hclge_pfc_setup_hw(hdev); 1509 if (init && ret == -EOPNOTSUPP) 1510 dev_warn(&hdev->pdev->dev, "GE MAC does not support pfc\n"); 1511 else if (ret) { 1512 dev_err(&hdev->pdev->dev, "config pfc failed! ret = %d\n", 1513 ret); 1514 return ret; 1515 } 1516 1517 return hclge_tm_bp_setup(hdev); 1518 } 1519 1520 void hclge_tm_prio_tc_info_update(struct hclge_dev *hdev, u8 *prio_tc) 1521 { 1522 struct hclge_vport *vport = hdev->vport; 1523 struct hnae3_knic_private_info *kinfo; 1524 u32 i, k; 1525 1526 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) { 1527 hdev->tm_info.prio_tc[i] = prio_tc[i]; 1528 1529 for (k = 0; k < hdev->num_alloc_vport; k++) { 1530 kinfo = &vport[k].nic.kinfo; 1531 kinfo->tc_info.prio_tc[i] = prio_tc[i]; 1532 } 1533 } 1534 } 1535 1536 void hclge_tm_schd_info_update(struct hclge_dev *hdev, u8 num_tc) 1537 { 1538 u8 bit_map = 0; 1539 u8 i; 1540 1541 hdev->tm_info.num_tc = num_tc; 1542 1543 for (i = 0; i < hdev->tm_info.num_tc; i++) 1544 bit_map |= BIT(i); 1545 1546 if (!bit_map) { 1547 bit_map = 1; 1548 hdev->tm_info.num_tc = 1; 1549 } 1550 1551 hdev->hw_tc_map = bit_map; 1552 1553 hclge_tm_schd_info_init(hdev); 1554 } 1555 1556 void hclge_tm_pfc_info_update(struct hclge_dev *hdev) 1557 { 1558 /* DCB is enabled if we have more than 1 TC or pfc_en is 1559 * non-zero. 1560 */ 1561 if (hdev->tm_info.num_tc > 1 || hdev->tm_info.pfc_en) 1562 hdev->flag |= HCLGE_FLAG_DCB_ENABLE; 1563 else 1564 hdev->flag &= ~HCLGE_FLAG_DCB_ENABLE; 1565 1566 hclge_pfc_info_init(hdev); 1567 } 1568 1569 int hclge_tm_init_hw(struct hclge_dev *hdev, bool init) 1570 { 1571 int ret; 1572 1573 if ((hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) && 1574 (hdev->tx_sch_mode != HCLGE_FLAG_VNET_BASE_SCH_MODE)) 1575 return -ENOTSUPP; 1576 1577 ret = hclge_tm_schd_setup_hw(hdev); 1578 if (ret) 1579 return ret; 1580 1581 ret = hclge_pause_setup_hw(hdev, init); 1582 if (ret) 1583 return ret; 1584 1585 return 0; 1586 } 1587 1588 int hclge_tm_schd_init(struct hclge_dev *hdev) 1589 { 1590 /* fc_mode is HCLGE_FC_FULL on reset */ 1591 hdev->tm_info.fc_mode = HCLGE_FC_FULL; 1592 hdev->fc_mode_last_time = hdev->tm_info.fc_mode; 1593 1594 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE && 1595 hdev->tm_info.num_pg != 1) 1596 return -EINVAL; 1597 1598 hclge_tm_schd_info_init(hdev); 1599 1600 return hclge_tm_init_hw(hdev, true); 1601 } 1602 1603 int hclge_tm_vport_map_update(struct hclge_dev *hdev) 1604 { 1605 struct hclge_vport *vport = hdev->vport; 1606 int ret; 1607 1608 hclge_tm_vport_tc_info_update(vport); 1609 1610 ret = hclge_vport_q_to_qs_map(hdev, vport); 1611 if (ret) 1612 return ret; 1613 1614 if (!(hdev->flag & HCLGE_FLAG_DCB_ENABLE)) 1615 return 0; 1616 1617 return hclge_tm_bp_setup(hdev); 1618 } 1619