1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2021 Hisilicon Limited. 3 4 #include <linux/skbuff.h> 5 #include "hclge_main.h" 6 #include "hnae3.h" 7 8 static int hclge_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) 9 { 10 struct hclge_dev *hdev = hclge_ptp_get_hdev(ptp); 11 u64 adj_val, adj_base, diff; 12 unsigned long flags; 13 bool is_neg = false; 14 u32 quo, numerator; 15 16 if (ppb < 0) { 17 ppb = -ppb; 18 is_neg = true; 19 } 20 21 adj_base = HCLGE_PTP_CYCLE_ADJ_BASE * HCLGE_PTP_CYCLE_ADJ_UNIT; 22 adj_val = adj_base * ppb; 23 diff = div_u64(adj_val, 1000000000ULL); 24 25 if (is_neg) 26 adj_val = adj_base - diff; 27 else 28 adj_val = adj_base + diff; 29 30 /* This clock cycle is defined by three part: quotient, numerator 31 * and denominator. For example, 2.5ns, the quotient is 2, 32 * denominator is fixed to HCLGE_PTP_CYCLE_ADJ_UNIT, and numerator 33 * is 0.5 * HCLGE_PTP_CYCLE_ADJ_UNIT. 34 */ 35 quo = div_u64_rem(adj_val, HCLGE_PTP_CYCLE_ADJ_UNIT, &numerator); 36 37 spin_lock_irqsave(&hdev->ptp->lock, flags); 38 writel(quo, hdev->ptp->io_base + HCLGE_PTP_CYCLE_QUO_REG); 39 writel(numerator, hdev->ptp->io_base + HCLGE_PTP_CYCLE_NUM_REG); 40 writel(HCLGE_PTP_CYCLE_ADJ_UNIT, 41 hdev->ptp->io_base + HCLGE_PTP_CYCLE_DEN_REG); 42 writel(HCLGE_PTP_CYCLE_ADJ_EN, 43 hdev->ptp->io_base + HCLGE_PTP_CYCLE_CFG_REG); 44 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 45 46 return 0; 47 } 48 49 bool hclge_ptp_set_tx_info(struct hnae3_handle *handle, struct sk_buff *skb) 50 { 51 struct hclge_vport *vport = hclge_get_vport(handle); 52 struct hclge_dev *hdev = vport->back; 53 struct hclge_ptp *ptp = hdev->ptp; 54 55 if (!test_bit(HCLGE_PTP_FLAG_TX_EN, &ptp->flags) || 56 test_and_set_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state)) { 57 ptp->tx_skipped++; 58 return false; 59 } 60 61 ptp->tx_start = jiffies; 62 ptp->tx_skb = skb_get(skb); 63 ptp->tx_cnt++; 64 65 return true; 66 } 67 68 void hclge_ptp_clean_tx_hwts(struct hclge_dev *hdev) 69 { 70 struct sk_buff *skb = hdev->ptp->tx_skb; 71 struct skb_shared_hwtstamps hwts; 72 u32 hi, lo; 73 u64 ns; 74 75 ns = readl(hdev->ptp->io_base + HCLGE_PTP_TX_TS_NSEC_REG) & 76 HCLGE_PTP_TX_TS_NSEC_MASK; 77 lo = readl(hdev->ptp->io_base + HCLGE_PTP_TX_TS_SEC_L_REG); 78 hi = readl(hdev->ptp->io_base + HCLGE_PTP_TX_TS_SEC_H_REG) & 79 HCLGE_PTP_TX_TS_SEC_H_MASK; 80 hdev->ptp->last_tx_seqid = readl(hdev->ptp->io_base + 81 HCLGE_PTP_TX_TS_SEQID_REG); 82 83 if (skb) { 84 hdev->ptp->tx_skb = NULL; 85 hdev->ptp->tx_cleaned++; 86 87 ns += (((u64)hi) << 32 | lo) * NSEC_PER_SEC; 88 hwts.hwtstamp = ns_to_ktime(ns); 89 skb_tstamp_tx(skb, &hwts); 90 dev_kfree_skb_any(skb); 91 } 92 93 clear_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state); 94 } 95 96 void hclge_ptp_get_rx_hwts(struct hnae3_handle *handle, struct sk_buff *skb, 97 u32 nsec, u32 sec) 98 { 99 struct hclge_vport *vport = hclge_get_vport(handle); 100 struct hclge_dev *hdev = vport->back; 101 unsigned long flags; 102 u64 ns = nsec; 103 u32 sec_h; 104 105 if (!test_bit(HCLGE_PTP_FLAG_RX_EN, &hdev->ptp->flags)) 106 return; 107 108 /* Since the BD does not have enough space for the higher 16 bits of 109 * second, and this part will not change frequently, so read it 110 * from register. 111 */ 112 spin_lock_irqsave(&hdev->ptp->lock, flags); 113 sec_h = readl(hdev->ptp->io_base + HCLGE_PTP_CUR_TIME_SEC_H_REG); 114 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 115 116 ns += (((u64)sec_h) << HCLGE_PTP_SEC_H_OFFSET | sec) * NSEC_PER_SEC; 117 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns); 118 hdev->ptp->last_rx = jiffies; 119 hdev->ptp->rx_cnt++; 120 } 121 122 static int hclge_ptp_gettimex(struct ptp_clock_info *ptp, struct timespec64 *ts, 123 struct ptp_system_timestamp *sts) 124 { 125 struct hclge_dev *hdev = hclge_ptp_get_hdev(ptp); 126 unsigned long flags; 127 u32 hi, lo; 128 u64 ns; 129 130 spin_lock_irqsave(&hdev->ptp->lock, flags); 131 ns = readl(hdev->ptp->io_base + HCLGE_PTP_CUR_TIME_NSEC_REG); 132 hi = readl(hdev->ptp->io_base + HCLGE_PTP_CUR_TIME_SEC_H_REG); 133 lo = readl(hdev->ptp->io_base + HCLGE_PTP_CUR_TIME_SEC_L_REG); 134 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 135 136 ns += (((u64)hi) << HCLGE_PTP_SEC_H_OFFSET | lo) * NSEC_PER_SEC; 137 *ts = ns_to_timespec64(ns); 138 139 return 0; 140 } 141 142 static int hclge_ptp_settime(struct ptp_clock_info *ptp, 143 const struct timespec64 *ts) 144 { 145 struct hclge_dev *hdev = hclge_ptp_get_hdev(ptp); 146 unsigned long flags; 147 148 spin_lock_irqsave(&hdev->ptp->lock, flags); 149 writel(ts->tv_nsec, hdev->ptp->io_base + HCLGE_PTP_TIME_NSEC_REG); 150 writel(ts->tv_sec >> HCLGE_PTP_SEC_H_OFFSET, 151 hdev->ptp->io_base + HCLGE_PTP_TIME_SEC_H_REG); 152 writel(ts->tv_sec & HCLGE_PTP_SEC_L_MASK, 153 hdev->ptp->io_base + HCLGE_PTP_TIME_SEC_L_REG); 154 /* synchronize the time of phc */ 155 writel(HCLGE_PTP_TIME_SYNC_EN, 156 hdev->ptp->io_base + HCLGE_PTP_TIME_SYNC_REG); 157 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 158 159 return 0; 160 } 161 162 static int hclge_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 163 { 164 struct hclge_dev *hdev = hclge_ptp_get_hdev(ptp); 165 unsigned long flags; 166 bool is_neg = false; 167 u32 adj_val = 0; 168 169 if (delta < 0) { 170 adj_val |= HCLGE_PTP_TIME_NSEC_NEG; 171 delta = -delta; 172 is_neg = true; 173 } 174 175 if (delta > HCLGE_PTP_TIME_NSEC_MASK) { 176 struct timespec64 ts; 177 s64 ns; 178 179 hclge_ptp_gettimex(ptp, &ts, NULL); 180 ns = timespec64_to_ns(&ts); 181 ns = is_neg ? ns - delta : ns + delta; 182 ts = ns_to_timespec64(ns); 183 return hclge_ptp_settime(ptp, &ts); 184 } 185 186 adj_val |= delta & HCLGE_PTP_TIME_NSEC_MASK; 187 188 spin_lock_irqsave(&hdev->ptp->lock, flags); 189 writel(adj_val, hdev->ptp->io_base + HCLGE_PTP_TIME_NSEC_REG); 190 writel(HCLGE_PTP_TIME_ADJ_EN, 191 hdev->ptp->io_base + HCLGE_PTP_TIME_ADJ_REG); 192 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 193 194 return 0; 195 } 196 197 int hclge_ptp_get_cfg(struct hclge_dev *hdev, struct ifreq *ifr) 198 { 199 if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state)) 200 return -EOPNOTSUPP; 201 202 return copy_to_user(ifr->ifr_data, &hdev->ptp->ts_cfg, 203 sizeof(struct hwtstamp_config)) ? -EFAULT : 0; 204 } 205 206 static int hclge_ptp_int_en(struct hclge_dev *hdev, bool en) 207 { 208 struct hclge_ptp_int_cmd *req; 209 struct hclge_desc desc; 210 int ret; 211 212 req = (struct hclge_ptp_int_cmd *)desc.data; 213 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PTP_INT_EN, false); 214 req->int_en = en ? 1 : 0; 215 216 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 217 if (ret) 218 dev_err(&hdev->pdev->dev, 219 "failed to %s ptp interrupt, ret = %d\n", 220 en ? "enable" : "disable", ret); 221 222 return ret; 223 } 224 225 int hclge_ptp_cfg_qry(struct hclge_dev *hdev, u32 *cfg) 226 { 227 struct hclge_ptp_cfg_cmd *req; 228 struct hclge_desc desc; 229 int ret; 230 231 req = (struct hclge_ptp_cfg_cmd *)desc.data; 232 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PTP_MODE_CFG, true); 233 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 234 if (ret) { 235 dev_err(&hdev->pdev->dev, 236 "failed to query ptp config, ret = %d\n", ret); 237 return ret; 238 } 239 240 *cfg = le32_to_cpu(req->cfg); 241 242 return 0; 243 } 244 245 static int hclge_ptp_cfg(struct hclge_dev *hdev, u32 cfg) 246 { 247 struct hclge_ptp_cfg_cmd *req; 248 struct hclge_desc desc; 249 int ret; 250 251 req = (struct hclge_ptp_cfg_cmd *)desc.data; 252 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PTP_MODE_CFG, false); 253 req->cfg = cpu_to_le32(cfg); 254 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 255 if (ret) 256 dev_err(&hdev->pdev->dev, 257 "failed to config ptp, ret = %d\n", ret); 258 259 return ret; 260 } 261 262 static int hclge_ptp_set_tx_mode(struct hwtstamp_config *cfg, 263 unsigned long *flags, u32 *ptp_cfg) 264 { 265 switch (cfg->tx_type) { 266 case HWTSTAMP_TX_OFF: 267 clear_bit(HCLGE_PTP_FLAG_TX_EN, flags); 268 break; 269 case HWTSTAMP_TX_ON: 270 set_bit(HCLGE_PTP_FLAG_TX_EN, flags); 271 *ptp_cfg |= HCLGE_PTP_TX_EN_B; 272 break; 273 default: 274 return -ERANGE; 275 } 276 277 return 0; 278 } 279 280 static int hclge_ptp_set_rx_mode(struct hwtstamp_config *cfg, 281 unsigned long *flags, u32 *ptp_cfg) 282 { 283 int rx_filter = cfg->rx_filter; 284 285 switch (cfg->rx_filter) { 286 case HWTSTAMP_FILTER_NONE: 287 clear_bit(HCLGE_PTP_FLAG_RX_EN, flags); 288 break; 289 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 290 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 291 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 292 set_bit(HCLGE_PTP_FLAG_RX_EN, flags); 293 *ptp_cfg |= HCLGE_PTP_RX_EN_B; 294 *ptp_cfg |= HCLGE_PTP_UDP_FULL_TYPE << HCLGE_PTP_UDP_EN_SHIFT; 295 rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 296 break; 297 case HWTSTAMP_FILTER_PTP_V2_EVENT: 298 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 299 case HWTSTAMP_FILTER_PTP_V2_SYNC: 300 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 301 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 302 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 303 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 304 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 305 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 306 set_bit(HCLGE_PTP_FLAG_RX_EN, flags); 307 *ptp_cfg |= HCLGE_PTP_RX_EN_B; 308 *ptp_cfg |= HCLGE_PTP_UDP_FULL_TYPE << HCLGE_PTP_UDP_EN_SHIFT; 309 *ptp_cfg |= HCLGE_PTP_MSG1_V2_DEFAULT << HCLGE_PTP_MSG1_SHIFT; 310 *ptp_cfg |= HCLGE_PTP_MSG0_V2_EVENT << HCLGE_PTP_MSG0_SHIFT; 311 *ptp_cfg |= HCLGE_PTP_MSG_TYPE_V2 << HCLGE_PTP_MSG_TYPE_SHIFT; 312 rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 313 break; 314 case HWTSTAMP_FILTER_ALL: 315 default: 316 return -ERANGE; 317 } 318 319 cfg->rx_filter = rx_filter; 320 321 return 0; 322 } 323 324 static int hclge_ptp_set_ts_mode(struct hclge_dev *hdev, 325 struct hwtstamp_config *cfg) 326 { 327 unsigned long flags = hdev->ptp->flags; 328 u32 ptp_cfg = 0; 329 int ret; 330 331 if (test_bit(HCLGE_PTP_FLAG_EN, &hdev->ptp->flags)) 332 ptp_cfg |= HCLGE_PTP_EN_B; 333 334 ret = hclge_ptp_set_tx_mode(cfg, &flags, &ptp_cfg); 335 if (ret) 336 return ret; 337 338 ret = hclge_ptp_set_rx_mode(cfg, &flags, &ptp_cfg); 339 if (ret) 340 return ret; 341 342 ret = hclge_ptp_cfg(hdev, ptp_cfg); 343 if (ret) 344 return ret; 345 346 hdev->ptp->flags = flags; 347 hdev->ptp->ptp_cfg = ptp_cfg; 348 349 return 0; 350 } 351 352 int hclge_ptp_set_cfg(struct hclge_dev *hdev, struct ifreq *ifr) 353 { 354 struct hwtstamp_config cfg; 355 int ret; 356 357 if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state)) { 358 dev_err(&hdev->pdev->dev, "phc is unsupported\n"); 359 return -EOPNOTSUPP; 360 } 361 362 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 363 return -EFAULT; 364 365 ret = hclge_ptp_set_ts_mode(hdev, &cfg); 366 if (ret) 367 return ret; 368 369 hdev->ptp->ts_cfg = cfg; 370 371 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 372 } 373 374 int hclge_ptp_get_ts_info(struct hnae3_handle *handle, 375 struct ethtool_ts_info *info) 376 { 377 struct hclge_vport *vport = hclge_get_vport(handle); 378 struct hclge_dev *hdev = vport->back; 379 380 if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state)) { 381 dev_err(&hdev->pdev->dev, "phc is unsupported\n"); 382 return -EOPNOTSUPP; 383 } 384 385 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 386 SOF_TIMESTAMPING_RX_SOFTWARE | 387 SOF_TIMESTAMPING_SOFTWARE | 388 SOF_TIMESTAMPING_TX_HARDWARE | 389 SOF_TIMESTAMPING_RX_HARDWARE | 390 SOF_TIMESTAMPING_RAW_HARDWARE; 391 392 if (hdev->ptp->clock) 393 info->phc_index = ptp_clock_index(hdev->ptp->clock); 394 else 395 info->phc_index = -1; 396 397 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON); 398 399 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | 400 BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 401 BIT(HWTSTAMP_FILTER_PTP_V2_L2_SYNC) | 402 BIT(HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ); 403 404 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 405 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 406 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT) | 407 BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 408 BIT(HWTSTAMP_FILTER_PTP_V2_SYNC) | 409 BIT(HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | 410 BIT(HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) | 411 BIT(HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ); 412 413 return 0; 414 } 415 416 static int hclge_ptp_create_clock(struct hclge_dev *hdev) 417 { 418 struct hclge_ptp *ptp; 419 420 ptp = devm_kzalloc(&hdev->pdev->dev, sizeof(*ptp), GFP_KERNEL); 421 if (!ptp) 422 return -ENOMEM; 423 424 ptp->hdev = hdev; 425 snprintf(ptp->info.name, sizeof(ptp->info.name), "%s", 426 HCLGE_DRIVER_NAME); 427 ptp->info.owner = THIS_MODULE; 428 ptp->info.max_adj = HCLGE_PTP_CYCLE_ADJ_MAX; 429 ptp->info.n_ext_ts = 0; 430 ptp->info.pps = 0; 431 ptp->info.adjfreq = hclge_ptp_adjfreq; 432 ptp->info.adjtime = hclge_ptp_adjtime; 433 ptp->info.gettimex64 = hclge_ptp_gettimex; 434 ptp->info.settime64 = hclge_ptp_settime; 435 436 ptp->info.n_alarm = 0; 437 ptp->clock = ptp_clock_register(&ptp->info, &hdev->pdev->dev); 438 if (IS_ERR(ptp->clock)) { 439 dev_err(&hdev->pdev->dev, 440 "%d failed to register ptp clock, ret = %ld\n", 441 ptp->info.n_alarm, PTR_ERR(ptp->clock)); 442 return -ENODEV; 443 } else if (!ptp->clock) { 444 dev_err(&hdev->pdev->dev, "failed to register ptp clock\n"); 445 return -ENODEV; 446 } 447 448 spin_lock_init(&ptp->lock); 449 ptp->io_base = hdev->hw.io_base + HCLGE_PTP_REG_OFFSET; 450 ptp->ts_cfg.rx_filter = HWTSTAMP_FILTER_NONE; 451 ptp->ts_cfg.tx_type = HWTSTAMP_TX_OFF; 452 hdev->ptp = ptp; 453 454 return 0; 455 } 456 457 static void hclge_ptp_destroy_clock(struct hclge_dev *hdev) 458 { 459 ptp_clock_unregister(hdev->ptp->clock); 460 hdev->ptp->clock = NULL; 461 devm_kfree(&hdev->pdev->dev, hdev->ptp); 462 hdev->ptp = NULL; 463 } 464 465 int hclge_ptp_init(struct hclge_dev *hdev) 466 { 467 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 468 struct timespec64 ts; 469 int ret; 470 471 if (!test_bit(HNAE3_DEV_SUPPORT_PTP_B, ae_dev->caps)) 472 return 0; 473 474 if (!hdev->ptp) { 475 ret = hclge_ptp_create_clock(hdev); 476 if (ret) 477 return ret; 478 } 479 480 ret = hclge_ptp_int_en(hdev, true); 481 if (ret) 482 goto out; 483 484 set_bit(HCLGE_PTP_FLAG_EN, &hdev->ptp->flags); 485 ret = hclge_ptp_adjfreq(&hdev->ptp->info, 0); 486 if (ret) { 487 dev_err(&hdev->pdev->dev, 488 "failed to init freq, ret = %d\n", ret); 489 goto out; 490 } 491 492 ret = hclge_ptp_set_ts_mode(hdev, &hdev->ptp->ts_cfg); 493 if (ret) { 494 dev_err(&hdev->pdev->dev, 495 "failed to init ts mode, ret = %d\n", ret); 496 goto out; 497 } 498 499 ktime_get_real_ts64(&ts); 500 ret = hclge_ptp_settime(&hdev->ptp->info, &ts); 501 if (ret) { 502 dev_err(&hdev->pdev->dev, 503 "failed to init ts time, ret = %d\n", ret); 504 goto out; 505 } 506 507 set_bit(HCLGE_STATE_PTP_EN, &hdev->state); 508 dev_info(&hdev->pdev->dev, "phc initializes ok!\n"); 509 510 return 0; 511 512 out: 513 hclge_ptp_destroy_clock(hdev); 514 515 return ret; 516 } 517 518 void hclge_ptp_uninit(struct hclge_dev *hdev) 519 { 520 struct hclge_ptp *ptp = hdev->ptp; 521 522 if (!ptp) 523 return; 524 525 hclge_ptp_int_en(hdev, false); 526 clear_bit(HCLGE_STATE_PTP_EN, &hdev->state); 527 clear_bit(HCLGE_PTP_FLAG_EN, &ptp->flags); 528 ptp->ts_cfg.rx_filter = HWTSTAMP_FILTER_NONE; 529 ptp->ts_cfg.tx_type = HWTSTAMP_TX_OFF; 530 531 if (hclge_ptp_set_ts_mode(hdev, &ptp->ts_cfg)) 532 dev_err(&hdev->pdev->dev, "failed to disable phc\n"); 533 534 if (ptp->tx_skb) { 535 struct sk_buff *skb = ptp->tx_skb; 536 537 ptp->tx_skb = NULL; 538 dev_kfree_skb_any(skb); 539 } 540 541 hclge_ptp_destroy_clock(hdev); 542 } 543