1 /* 2 * Copyright (c) 2016~2017 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 13 #include "hclge_cmd.h" 14 #include "hclge_main.h" 15 #include "hclge_mdio.h" 16 17 #define HCLGE_PHY_SUPPORTED_FEATURES (SUPPORTED_Autoneg | \ 18 SUPPORTED_TP | \ 19 SUPPORTED_Pause | \ 20 PHY_10BT_FEATURES | \ 21 PHY_100BT_FEATURES | \ 22 PHY_1000BT_FEATURES) 23 24 enum hclge_mdio_c22_op_seq { 25 HCLGE_MDIO_C22_WRITE = 1, 26 HCLGE_MDIO_C22_READ = 2 27 }; 28 29 #define HCLGE_MDIO_CTRL_START_B 0 30 #define HCLGE_MDIO_CTRL_ST_S 1 31 #define HCLGE_MDIO_CTRL_ST_M (0x3 << HCLGE_MDIO_CTRL_ST_S) 32 #define HCLGE_MDIO_CTRL_OP_S 3 33 #define HCLGE_MDIO_CTRL_OP_M (0x3 << HCLGE_MDIO_CTRL_OP_S) 34 35 #define HCLGE_MDIO_PHYID_S 0 36 #define HCLGE_MDIO_PHYID_M (0x1f << HCLGE_MDIO_PHYID_S) 37 38 #define HCLGE_MDIO_PHYREG_S 0 39 #define HCLGE_MDIO_PHYREG_M (0x1f << HCLGE_MDIO_PHYREG_S) 40 41 #define HCLGE_MDIO_STA_B 0 42 43 struct hclge_mdio_cfg_cmd { 44 u8 ctrl_bit; 45 u8 phyid; 46 u8 phyad; 47 u8 rsvd; 48 __le16 reserve; 49 __le16 data_wr; 50 __le16 data_rd; 51 __le16 sta; 52 }; 53 54 static int hclge_mdio_write(struct mii_bus *bus, int phyid, int regnum, 55 u16 data) 56 { 57 struct hclge_mdio_cfg_cmd *mdio_cmd; 58 struct hclge_dev *hdev = bus->priv; 59 struct hclge_desc desc; 60 int ret; 61 62 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MDIO_CONFIG, false); 63 64 mdio_cmd = (struct hclge_mdio_cfg_cmd *)desc.data; 65 66 hnae_set_field(mdio_cmd->phyid, HCLGE_MDIO_PHYID_M, 67 HCLGE_MDIO_PHYID_S, phyid); 68 hnae_set_field(mdio_cmd->phyad, HCLGE_MDIO_PHYREG_M, 69 HCLGE_MDIO_PHYREG_S, regnum); 70 71 hnae_set_bit(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_START_B, 1); 72 hnae_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_ST_M, 73 HCLGE_MDIO_CTRL_ST_S, 1); 74 hnae_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_OP_M, 75 HCLGE_MDIO_CTRL_OP_S, HCLGE_MDIO_C22_WRITE); 76 77 mdio_cmd->data_wr = cpu_to_le16(data); 78 79 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 80 if (ret) { 81 dev_err(&hdev->pdev->dev, 82 "mdio write fail when sending cmd, status is %d.\n", 83 ret); 84 return ret; 85 } 86 87 return 0; 88 } 89 90 static int hclge_mdio_read(struct mii_bus *bus, int phyid, int regnum) 91 { 92 struct hclge_mdio_cfg_cmd *mdio_cmd; 93 struct hclge_dev *hdev = bus->priv; 94 struct hclge_desc desc; 95 int ret; 96 97 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MDIO_CONFIG, true); 98 99 mdio_cmd = (struct hclge_mdio_cfg_cmd *)desc.data; 100 101 hnae_set_field(mdio_cmd->phyid, HCLGE_MDIO_PHYID_M, 102 HCLGE_MDIO_PHYID_S, phyid); 103 hnae_set_field(mdio_cmd->phyad, HCLGE_MDIO_PHYREG_M, 104 HCLGE_MDIO_PHYREG_S, regnum); 105 106 hnae_set_bit(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_START_B, 1); 107 hnae_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_ST_M, 108 HCLGE_MDIO_CTRL_ST_S, 1); 109 hnae_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_OP_M, 110 HCLGE_MDIO_CTRL_OP_S, HCLGE_MDIO_C22_READ); 111 112 /* Read out phy data */ 113 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 114 if (ret) { 115 dev_err(&hdev->pdev->dev, 116 "mdio read fail when get data, status is %d.\n", 117 ret); 118 return ret; 119 } 120 121 if (hnae_get_bit(le16_to_cpu(mdio_cmd->sta), HCLGE_MDIO_STA_B)) { 122 dev_err(&hdev->pdev->dev, "mdio read data error\n"); 123 return -EIO; 124 } 125 126 return le16_to_cpu(mdio_cmd->data_rd); 127 } 128 129 int hclge_mac_mdio_config(struct hclge_dev *hdev) 130 { 131 struct hclge_mac *mac = &hdev->hw.mac; 132 struct phy_device *phydev; 133 struct mii_bus *mdio_bus; 134 int ret; 135 136 if (hdev->hw.mac.phy_addr >= PHY_MAX_ADDR) 137 return 0; 138 139 mdio_bus = devm_mdiobus_alloc(&hdev->pdev->dev); 140 if (!mdio_bus) 141 return -ENOMEM; 142 143 mdio_bus->name = "hisilicon MII bus"; 144 mdio_bus->read = hclge_mdio_read; 145 mdio_bus->write = hclge_mdio_write; 146 snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%s-%s", "mii", 147 dev_name(&hdev->pdev->dev)); 148 149 mdio_bus->parent = &hdev->pdev->dev; 150 mdio_bus->priv = hdev; 151 mdio_bus->phy_mask = ~(1 << mac->phy_addr); 152 ret = mdiobus_register(mdio_bus); 153 if (ret) { 154 dev_err(mdio_bus->parent, 155 "Failed to register MDIO bus ret = %#x\n", ret); 156 return ret; 157 } 158 159 phydev = mdiobus_get_phy(mdio_bus, mac->phy_addr); 160 if (!phydev) { 161 dev_err(mdio_bus->parent, "Failed to get phy device\n"); 162 mdiobus_unregister(mdio_bus); 163 return -EIO; 164 } 165 166 mac->phydev = phydev; 167 mac->mdio_bus = mdio_bus; 168 169 return 0; 170 } 171 172 static void hclge_mac_adjust_link(struct net_device *netdev) 173 { 174 struct hnae3_handle *h = *((void **)netdev_priv(netdev)); 175 struct hclge_vport *vport = hclge_get_vport(h); 176 struct hclge_dev *hdev = vport->back; 177 int duplex, speed; 178 int ret; 179 180 speed = netdev->phydev->speed; 181 duplex = netdev->phydev->duplex; 182 183 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex); 184 if (ret) 185 netdev_err(netdev, "failed to adjust link.\n"); 186 } 187 188 int hclge_mac_start_phy(struct hclge_dev *hdev) 189 { 190 struct net_device *netdev = hdev->vport[0].nic.netdev; 191 struct phy_device *phydev = hdev->hw.mac.phydev; 192 int ret; 193 194 if (!phydev) 195 return 0; 196 197 ret = phy_connect_direct(netdev, phydev, 198 hclge_mac_adjust_link, 199 PHY_INTERFACE_MODE_SGMII); 200 if (ret) { 201 netdev_err(netdev, "phy_connect_direct err.\n"); 202 return ret; 203 } 204 205 phydev->supported &= HCLGE_PHY_SUPPORTED_FEATURES; 206 phydev->advertising = phydev->supported; 207 208 phy_start(phydev); 209 210 return 0; 211 } 212 213 void hclge_mac_stop_phy(struct hclge_dev *hdev) 214 { 215 struct net_device *netdev = hdev->vport[0].nic.netdev; 216 struct phy_device *phydev = netdev->phydev; 217 218 if (!phydev) 219 return; 220 221 phy_stop(phydev); 222 phy_disconnect(phydev); 223 } 224