1 /* 2 * Copyright (c) 2016~2017 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 13 #include "hclge_cmd.h" 14 #include "hclge_main.h" 15 #include "hclge_mdio.h" 16 17 #define HCLGE_PHY_SUPPORTED_FEATURES (SUPPORTED_Autoneg | \ 18 SUPPORTED_TP | \ 19 SUPPORTED_Pause | \ 20 SUPPORTED_Asym_Pause | \ 21 PHY_10BT_FEATURES | \ 22 PHY_100BT_FEATURES | \ 23 PHY_1000BT_FEATURES) 24 25 enum hclge_mdio_c22_op_seq { 26 HCLGE_MDIO_C22_WRITE = 1, 27 HCLGE_MDIO_C22_READ = 2 28 }; 29 30 #define HCLGE_MDIO_CTRL_START_B 0 31 #define HCLGE_MDIO_CTRL_ST_S 1 32 #define HCLGE_MDIO_CTRL_ST_M (0x3 << HCLGE_MDIO_CTRL_ST_S) 33 #define HCLGE_MDIO_CTRL_OP_S 3 34 #define HCLGE_MDIO_CTRL_OP_M (0x3 << HCLGE_MDIO_CTRL_OP_S) 35 36 #define HCLGE_MDIO_PHYID_S 0 37 #define HCLGE_MDIO_PHYID_M (0x1f << HCLGE_MDIO_PHYID_S) 38 39 #define HCLGE_MDIO_PHYREG_S 0 40 #define HCLGE_MDIO_PHYREG_M (0x1f << HCLGE_MDIO_PHYREG_S) 41 42 #define HCLGE_MDIO_STA_B 0 43 44 struct hclge_mdio_cfg_cmd { 45 u8 ctrl_bit; 46 u8 phyid; 47 u8 phyad; 48 u8 rsvd; 49 __le16 reserve; 50 __le16 data_wr; 51 __le16 data_rd; 52 __le16 sta; 53 }; 54 55 static int hclge_mdio_write(struct mii_bus *bus, int phyid, int regnum, 56 u16 data) 57 { 58 struct hclge_mdio_cfg_cmd *mdio_cmd; 59 struct hclge_dev *hdev = bus->priv; 60 struct hclge_desc desc; 61 int ret; 62 63 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 64 return 0; 65 66 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MDIO_CONFIG, false); 67 68 mdio_cmd = (struct hclge_mdio_cfg_cmd *)desc.data; 69 70 hnae_set_field(mdio_cmd->phyid, HCLGE_MDIO_PHYID_M, 71 HCLGE_MDIO_PHYID_S, phyid); 72 hnae_set_field(mdio_cmd->phyad, HCLGE_MDIO_PHYREG_M, 73 HCLGE_MDIO_PHYREG_S, regnum); 74 75 hnae_set_bit(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_START_B, 1); 76 hnae_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_ST_M, 77 HCLGE_MDIO_CTRL_ST_S, 1); 78 hnae_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_OP_M, 79 HCLGE_MDIO_CTRL_OP_S, HCLGE_MDIO_C22_WRITE); 80 81 mdio_cmd->data_wr = cpu_to_le16(data); 82 83 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 84 if (ret) { 85 dev_err(&hdev->pdev->dev, 86 "mdio write fail when sending cmd, status is %d.\n", 87 ret); 88 return ret; 89 } 90 91 return 0; 92 } 93 94 static int hclge_mdio_read(struct mii_bus *bus, int phyid, int regnum) 95 { 96 struct hclge_mdio_cfg_cmd *mdio_cmd; 97 struct hclge_dev *hdev = bus->priv; 98 struct hclge_desc desc; 99 int ret; 100 101 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 102 return 0; 103 104 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MDIO_CONFIG, true); 105 106 mdio_cmd = (struct hclge_mdio_cfg_cmd *)desc.data; 107 108 hnae_set_field(mdio_cmd->phyid, HCLGE_MDIO_PHYID_M, 109 HCLGE_MDIO_PHYID_S, phyid); 110 hnae_set_field(mdio_cmd->phyad, HCLGE_MDIO_PHYREG_M, 111 HCLGE_MDIO_PHYREG_S, regnum); 112 113 hnae_set_bit(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_START_B, 1); 114 hnae_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_ST_M, 115 HCLGE_MDIO_CTRL_ST_S, 1); 116 hnae_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_OP_M, 117 HCLGE_MDIO_CTRL_OP_S, HCLGE_MDIO_C22_READ); 118 119 /* Read out phy data */ 120 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 121 if (ret) { 122 dev_err(&hdev->pdev->dev, 123 "mdio read fail when get data, status is %d.\n", 124 ret); 125 return ret; 126 } 127 128 if (hnae_get_bit(le16_to_cpu(mdio_cmd->sta), HCLGE_MDIO_STA_B)) { 129 dev_err(&hdev->pdev->dev, "mdio read data error\n"); 130 return -EIO; 131 } 132 133 return le16_to_cpu(mdio_cmd->data_rd); 134 } 135 136 int hclge_mac_mdio_config(struct hclge_dev *hdev) 137 { 138 struct hclge_mac *mac = &hdev->hw.mac; 139 struct phy_device *phydev; 140 struct mii_bus *mdio_bus; 141 int ret; 142 143 if (hdev->hw.mac.phy_addr >= PHY_MAX_ADDR) { 144 dev_err(&hdev->pdev->dev, "phy_addr(%d) is too large.\n", 145 hdev->hw.mac.phy_addr); 146 return -EINVAL; 147 } 148 149 mdio_bus = devm_mdiobus_alloc(&hdev->pdev->dev); 150 if (!mdio_bus) 151 return -ENOMEM; 152 153 mdio_bus->name = "hisilicon MII bus"; 154 mdio_bus->read = hclge_mdio_read; 155 mdio_bus->write = hclge_mdio_write; 156 snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%s-%s", "mii", 157 dev_name(&hdev->pdev->dev)); 158 159 mdio_bus->parent = &hdev->pdev->dev; 160 mdio_bus->priv = hdev; 161 mdio_bus->phy_mask = ~(1 << mac->phy_addr); 162 ret = mdiobus_register(mdio_bus); 163 if (ret) { 164 dev_err(mdio_bus->parent, 165 "Failed to register MDIO bus ret = %#x\n", ret); 166 return ret; 167 } 168 169 phydev = mdiobus_get_phy(mdio_bus, mac->phy_addr); 170 if (!phydev) { 171 dev_err(mdio_bus->parent, "Failed to get phy device\n"); 172 mdiobus_unregister(mdio_bus); 173 return -EIO; 174 } 175 176 mac->phydev = phydev; 177 mac->mdio_bus = mdio_bus; 178 179 return 0; 180 } 181 182 static void hclge_mac_adjust_link(struct net_device *netdev) 183 { 184 struct hnae3_handle *h = *((void **)netdev_priv(netdev)); 185 struct hclge_vport *vport = hclge_get_vport(h); 186 struct hclge_dev *hdev = vport->back; 187 int duplex, speed; 188 int ret; 189 190 speed = netdev->phydev->speed; 191 duplex = netdev->phydev->duplex; 192 193 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex); 194 if (ret) 195 netdev_err(netdev, "failed to adjust link.\n"); 196 197 ret = hclge_cfg_flowctrl(hdev); 198 if (ret) 199 netdev_err(netdev, "failed to configure flow control.\n"); 200 } 201 202 int hclge_mac_start_phy(struct hclge_dev *hdev) 203 { 204 struct net_device *netdev = hdev->vport[0].nic.netdev; 205 struct phy_device *phydev = hdev->hw.mac.phydev; 206 int ret; 207 208 if (!phydev) 209 return 0; 210 211 ret = phy_connect_direct(netdev, phydev, 212 hclge_mac_adjust_link, 213 PHY_INTERFACE_MODE_SGMII); 214 if (ret) { 215 netdev_err(netdev, "phy_connect_direct err.\n"); 216 return ret; 217 } 218 219 phydev->supported &= HCLGE_PHY_SUPPORTED_FEATURES; 220 phydev->advertising = phydev->supported; 221 222 phy_start(phydev); 223 224 return 0; 225 } 226 227 void hclge_mac_stop_phy(struct hclge_dev *hdev) 228 { 229 struct net_device *netdev = hdev->vport[0].nic.netdev; 230 struct phy_device *phydev = netdev->phydev; 231 232 if (!phydev) 233 return; 234 235 phy_stop(phydev); 236 phy_disconnect(phydev); 237 } 238