1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include <linux/kernel.h> 6 7 #include "hclge_cmd.h" 8 #include "hclge_main.h" 9 #include "hclge_mdio.h" 10 11 enum hclge_mdio_c22_op_seq { 12 HCLGE_MDIO_C22_WRITE = 1, 13 HCLGE_MDIO_C22_READ = 2 14 }; 15 16 #define HCLGE_MDIO_CTRL_START_B 0 17 #define HCLGE_MDIO_CTRL_ST_S 1 18 #define HCLGE_MDIO_CTRL_ST_M (0x3 << HCLGE_MDIO_CTRL_ST_S) 19 #define HCLGE_MDIO_CTRL_OP_S 3 20 #define HCLGE_MDIO_CTRL_OP_M (0x3 << HCLGE_MDIO_CTRL_OP_S) 21 22 #define HCLGE_MDIO_PHYID_S 0 23 #define HCLGE_MDIO_PHYID_M (0x1f << HCLGE_MDIO_PHYID_S) 24 25 #define HCLGE_MDIO_PHYREG_S 0 26 #define HCLGE_MDIO_PHYREG_M (0x1f << HCLGE_MDIO_PHYREG_S) 27 28 #define HCLGE_MDIO_STA_B 0 29 30 struct hclge_mdio_cfg_cmd { 31 u8 ctrl_bit; 32 u8 phyid; 33 u8 phyad; 34 u8 rsvd; 35 __le16 reserve; 36 __le16 data_wr; 37 __le16 data_rd; 38 __le16 sta; 39 }; 40 41 static int hclge_mdio_write(struct mii_bus *bus, int phyid, int regnum, 42 u16 data) 43 { 44 struct hclge_mdio_cfg_cmd *mdio_cmd; 45 struct hclge_dev *hdev = bus->priv; 46 struct hclge_desc desc; 47 int ret; 48 49 if (test_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state)) 50 return 0; 51 52 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MDIO_CONFIG, false); 53 54 mdio_cmd = (struct hclge_mdio_cfg_cmd *)desc.data; 55 56 hnae3_set_field(mdio_cmd->phyid, HCLGE_MDIO_PHYID_M, 57 HCLGE_MDIO_PHYID_S, phyid); 58 hnae3_set_field(mdio_cmd->phyad, HCLGE_MDIO_PHYREG_M, 59 HCLGE_MDIO_PHYREG_S, regnum); 60 61 hnae3_set_bit(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_START_B, 1); 62 hnae3_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_ST_M, 63 HCLGE_MDIO_CTRL_ST_S, 1); 64 hnae3_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_OP_M, 65 HCLGE_MDIO_CTRL_OP_S, HCLGE_MDIO_C22_WRITE); 66 67 mdio_cmd->data_wr = cpu_to_le16(data); 68 69 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 70 if (ret) { 71 dev_err(&hdev->pdev->dev, 72 "mdio write fail when sending cmd, status is %d.\n", 73 ret); 74 return ret; 75 } 76 77 return 0; 78 } 79 80 static int hclge_mdio_read(struct mii_bus *bus, int phyid, int regnum) 81 { 82 struct hclge_mdio_cfg_cmd *mdio_cmd; 83 struct hclge_dev *hdev = bus->priv; 84 struct hclge_desc desc; 85 int ret; 86 87 if (test_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state)) 88 return 0; 89 90 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MDIO_CONFIG, true); 91 92 mdio_cmd = (struct hclge_mdio_cfg_cmd *)desc.data; 93 94 hnae3_set_field(mdio_cmd->phyid, HCLGE_MDIO_PHYID_M, 95 HCLGE_MDIO_PHYID_S, phyid); 96 hnae3_set_field(mdio_cmd->phyad, HCLGE_MDIO_PHYREG_M, 97 HCLGE_MDIO_PHYREG_S, regnum); 98 99 hnae3_set_bit(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_START_B, 1); 100 hnae3_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_ST_M, 101 HCLGE_MDIO_CTRL_ST_S, 1); 102 hnae3_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_OP_M, 103 HCLGE_MDIO_CTRL_OP_S, HCLGE_MDIO_C22_READ); 104 105 /* Read out phy data */ 106 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 107 if (ret) { 108 dev_err(&hdev->pdev->dev, 109 "mdio read fail when get data, status is %d.\n", 110 ret); 111 return ret; 112 } 113 114 if (hnae3_get_bit(le16_to_cpu(mdio_cmd->sta), HCLGE_MDIO_STA_B)) { 115 dev_err(&hdev->pdev->dev, "mdio read data error\n"); 116 return -EIO; 117 } 118 119 return le16_to_cpu(mdio_cmd->data_rd); 120 } 121 122 int hclge_mac_mdio_config(struct hclge_dev *hdev) 123 { 124 #define PHY_INEXISTENT 255 125 126 struct hclge_mac *mac = &hdev->hw.mac; 127 struct phy_device *phydev; 128 struct mii_bus *mdio_bus; 129 int ret; 130 131 if (hdev->hw.mac.phy_addr == PHY_INEXISTENT) { 132 dev_info(&hdev->pdev->dev, 133 "no phy device is connected to mdio bus\n"); 134 return 0; 135 } else if (hdev->hw.mac.phy_addr >= PHY_MAX_ADDR) { 136 dev_err(&hdev->pdev->dev, "phy_addr(%d) is too large.\n", 137 hdev->hw.mac.phy_addr); 138 return -EINVAL; 139 } 140 141 mdio_bus = devm_mdiobus_alloc(&hdev->pdev->dev); 142 if (!mdio_bus) 143 return -ENOMEM; 144 145 mdio_bus->name = "hisilicon MII bus"; 146 mdio_bus->read = hclge_mdio_read; 147 mdio_bus->write = hclge_mdio_write; 148 snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%s-%s", "mii", 149 dev_name(&hdev->pdev->dev)); 150 151 mdio_bus->parent = &hdev->pdev->dev; 152 mdio_bus->priv = hdev; 153 mdio_bus->phy_mask = ~(1 << mac->phy_addr); 154 ret = mdiobus_register(mdio_bus); 155 if (ret) { 156 dev_err(mdio_bus->parent, 157 "Failed to register MDIO bus ret = %#x\n", ret); 158 return ret; 159 } 160 161 phydev = mdiobus_get_phy(mdio_bus, mac->phy_addr); 162 if (!phydev) { 163 dev_err(mdio_bus->parent, "Failed to get phy device\n"); 164 mdiobus_unregister(mdio_bus); 165 return -EIO; 166 } 167 168 mac->phydev = phydev; 169 mac->mdio_bus = mdio_bus; 170 171 return 0; 172 } 173 174 static void hclge_mac_adjust_link(struct net_device *netdev) 175 { 176 struct hnae3_handle *h = *((void **)netdev_priv(netdev)); 177 struct hclge_vport *vport = hclge_get_vport(h); 178 struct hclge_dev *hdev = vport->back; 179 int duplex, speed; 180 int ret; 181 182 /* When phy link down, do nothing */ 183 if (netdev->phydev->link == 0) 184 return; 185 186 speed = netdev->phydev->speed; 187 duplex = netdev->phydev->duplex; 188 189 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex); 190 if (ret) 191 netdev_err(netdev, "failed to adjust link.\n"); 192 193 ret = hclge_cfg_flowctrl(hdev); 194 if (ret) 195 netdev_err(netdev, "failed to configure flow control.\n"); 196 } 197 198 int hclge_mac_connect_phy(struct hnae3_handle *handle) 199 { 200 struct hclge_vport *vport = hclge_get_vport(handle); 201 struct hclge_dev *hdev = vport->back; 202 struct net_device *netdev = hdev->vport[0].nic.netdev; 203 struct phy_device *phydev = hdev->hw.mac.phydev; 204 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 205 int ret; 206 207 if (!phydev) 208 return 0; 209 210 linkmode_clear_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported); 211 212 ret = phy_connect_direct(netdev, phydev, 213 hclge_mac_adjust_link, 214 PHY_INTERFACE_MODE_SGMII); 215 if (ret) { 216 netdev_err(netdev, "phy_connect_direct err.\n"); 217 return ret; 218 } 219 220 linkmode_copy(mask, hdev->hw.mac.supported); 221 linkmode_and(phydev->supported, phydev->supported, mask); 222 linkmode_copy(phydev->advertising, phydev->supported); 223 224 return 0; 225 } 226 227 void hclge_mac_disconnect_phy(struct hnae3_handle *handle) 228 { 229 struct hclge_vport *vport = hclge_get_vport(handle); 230 struct hclge_dev *hdev = vport->back; 231 struct phy_device *phydev = hdev->hw.mac.phydev; 232 233 if (!phydev) 234 return; 235 236 phy_disconnect(phydev); 237 } 238 239 void hclge_mac_start_phy(struct hclge_dev *hdev) 240 { 241 struct phy_device *phydev = hdev->hw.mac.phydev; 242 243 if (!phydev) 244 return; 245 246 phy_start(phydev); 247 } 248 249 void hclge_mac_stop_phy(struct hclge_dev *hdev) 250 { 251 struct net_device *netdev = hdev->vport[0].nic.netdev; 252 struct phy_device *phydev = netdev->phydev; 253 254 if (!phydev) 255 return; 256 257 phy_stop(phydev); 258 } 259