1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include "hclge_main.h" 5 #include "hclge_mbx.h" 6 #include "hnae3.h" 7 8 /* hclge_gen_resp_to_vf: used to generate a synchronous response to VF when PF 9 * receives a mailbox message from VF. 10 * @vport: pointer to struct hclge_vport 11 * @vf_to_pf_req: pointer to hclge_mbx_vf_to_pf_cmd of the original mailbox 12 * message 13 * @resp_status: indicate to VF whether its request success(0) or failed. 14 */ 15 static int hclge_gen_resp_to_vf(struct hclge_vport *vport, 16 struct hclge_mbx_vf_to_pf_cmd *vf_to_pf_req, 17 int resp_status, 18 u8 *resp_data, u16 resp_data_len) 19 { 20 struct hclge_mbx_pf_to_vf_cmd *resp_pf_to_vf; 21 struct hclge_dev *hdev = vport->back; 22 enum hclge_cmd_status status; 23 struct hclge_desc desc; 24 25 resp_pf_to_vf = (struct hclge_mbx_pf_to_vf_cmd *)desc.data; 26 27 if (resp_data_len > HCLGE_MBX_MAX_RESP_DATA_SIZE) { 28 dev_err(&hdev->pdev->dev, 29 "PF fail to gen resp to VF len %d exceeds max len %d\n", 30 resp_data_len, 31 HCLGE_MBX_MAX_RESP_DATA_SIZE); 32 } 33 34 hclge_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_PF_TO_VF, false); 35 36 resp_pf_to_vf->dest_vfid = vf_to_pf_req->mbx_src_vfid; 37 resp_pf_to_vf->msg_len = vf_to_pf_req->msg_len; 38 39 resp_pf_to_vf->msg[0] = HCLGE_MBX_PF_VF_RESP; 40 resp_pf_to_vf->msg[1] = vf_to_pf_req->msg[0]; 41 resp_pf_to_vf->msg[2] = vf_to_pf_req->msg[1]; 42 resp_pf_to_vf->msg[3] = (resp_status == 0) ? 0 : 1; 43 44 if (resp_data && resp_data_len > 0) 45 memcpy(&resp_pf_to_vf->msg[4], resp_data, resp_data_len); 46 47 status = hclge_cmd_send(&hdev->hw, &desc, 1); 48 if (status) 49 dev_err(&hdev->pdev->dev, 50 "PF failed(=%d) to send response to VF\n", status); 51 52 return status; 53 } 54 55 static int hclge_send_mbx_msg(struct hclge_vport *vport, u8 *msg, u16 msg_len, 56 u16 mbx_opcode, u8 dest_vfid) 57 { 58 struct hclge_mbx_pf_to_vf_cmd *resp_pf_to_vf; 59 struct hclge_dev *hdev = vport->back; 60 enum hclge_cmd_status status; 61 struct hclge_desc desc; 62 63 resp_pf_to_vf = (struct hclge_mbx_pf_to_vf_cmd *)desc.data; 64 65 hclge_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_PF_TO_VF, false); 66 67 resp_pf_to_vf->dest_vfid = dest_vfid; 68 resp_pf_to_vf->msg_len = msg_len; 69 resp_pf_to_vf->msg[0] = mbx_opcode; 70 71 memcpy(&resp_pf_to_vf->msg[1], msg, msg_len); 72 73 status = hclge_cmd_send(&hdev->hw, &desc, 1); 74 if (status) 75 dev_err(&hdev->pdev->dev, 76 "PF failed(=%d) to send mailbox message to VF\n", 77 status); 78 79 return status; 80 } 81 82 static int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport) 83 { 84 u8 msg_data[2]; 85 u8 dest_vfid; 86 87 dest_vfid = (u8)vport->vport_id; 88 89 /* send this requested info to VF */ 90 return hclge_send_mbx_msg(vport, msg_data, sizeof(u8), 91 HCLGE_MBX_ASSERTING_RESET, dest_vfid); 92 } 93 94 static void hclge_free_vector_ring_chain(struct hnae3_ring_chain_node *head) 95 { 96 struct hnae3_ring_chain_node *chain_tmp, *chain; 97 98 chain = head->next; 99 100 while (chain) { 101 chain_tmp = chain->next; 102 kzfree(chain); 103 chain = chain_tmp; 104 } 105 } 106 107 /* hclge_get_ring_chain_from_mbx: get ring type & tqp id & int_gl idx 108 * from mailbox message 109 * msg[0]: opcode 110 * msg[1]: <not relevant to this function> 111 * msg[2]: ring_num 112 * msg[3]: first ring type (TX|RX) 113 * msg[4]: first tqp id 114 * msg[5]: first int_gl idx 115 * msg[6] ~ msg[14]: other ring type, tqp id and int_gl idx 116 */ 117 static int hclge_get_ring_chain_from_mbx( 118 struct hclge_mbx_vf_to_pf_cmd *req, 119 struct hnae3_ring_chain_node *ring_chain, 120 struct hclge_vport *vport) 121 { 122 struct hnae3_ring_chain_node *cur_chain, *new_chain; 123 int ring_num; 124 int i; 125 126 ring_num = req->msg[2]; 127 128 if (ring_num > ((HCLGE_MBX_VF_MSG_DATA_NUM - 129 HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 130 HCLGE_MBX_RING_NODE_VARIABLE_NUM)) 131 return -ENOMEM; 132 133 hnae3_set_bit(ring_chain->flag, HNAE3_RING_TYPE_B, req->msg[3]); 134 ring_chain->tqp_index = 135 hclge_get_queue_id(vport->nic.kinfo.tqp[req->msg[4]]); 136 hnae3_set_field(ring_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 137 HNAE3_RING_GL_IDX_S, 138 req->msg[5]); 139 140 cur_chain = ring_chain; 141 142 for (i = 1; i < ring_num; i++) { 143 new_chain = kzalloc(sizeof(*new_chain), GFP_KERNEL); 144 if (!new_chain) 145 goto err; 146 147 hnae3_set_bit(new_chain->flag, HNAE3_RING_TYPE_B, 148 req->msg[HCLGE_MBX_RING_NODE_VARIABLE_NUM * i + 149 HCLGE_MBX_RING_MAP_BASIC_MSG_NUM]); 150 151 new_chain->tqp_index = 152 hclge_get_queue_id(vport->nic.kinfo.tqp 153 [req->msg[HCLGE_MBX_RING_NODE_VARIABLE_NUM * i + 154 HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 1]]); 155 156 hnae3_set_field(new_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 157 HNAE3_RING_GL_IDX_S, 158 req->msg[HCLGE_MBX_RING_NODE_VARIABLE_NUM * i + 159 HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 2]); 160 161 cur_chain->next = new_chain; 162 cur_chain = new_chain; 163 } 164 165 return 0; 166 err: 167 hclge_free_vector_ring_chain(ring_chain); 168 return -ENOMEM; 169 } 170 171 static int hclge_map_unmap_ring_to_vf_vector(struct hclge_vport *vport, bool en, 172 struct hclge_mbx_vf_to_pf_cmd *req) 173 { 174 struct hnae3_ring_chain_node ring_chain; 175 int vector_id = req->msg[1]; 176 int ret; 177 178 memset(&ring_chain, 0, sizeof(ring_chain)); 179 ret = hclge_get_ring_chain_from_mbx(req, &ring_chain, vport); 180 if (ret) 181 return ret; 182 183 ret = hclge_bind_ring_with_vector(vport, vector_id, en, &ring_chain); 184 if (ret) 185 return ret; 186 187 hclge_free_vector_ring_chain(&ring_chain); 188 189 return 0; 190 } 191 192 static int hclge_set_vf_promisc_mode(struct hclge_vport *vport, 193 struct hclge_mbx_vf_to_pf_cmd *req) 194 { 195 bool en_uc = req->msg[1] ? true : false; 196 bool en_mc = req->msg[2] ? true : false; 197 struct hclge_promisc_param param; 198 199 /* always enable broadcast promisc bit */ 200 hclge_promisc_param_init(¶m, en_uc, en_mc, true, vport->vport_id); 201 return hclge_cmd_set_promisc_mode(vport->back, ¶m); 202 } 203 204 static int hclge_set_vf_uc_mac_addr(struct hclge_vport *vport, 205 struct hclge_mbx_vf_to_pf_cmd *mbx_req, 206 bool gen_resp) 207 { 208 const u8 *mac_addr = (const u8 *)(&mbx_req->msg[2]); 209 struct hclge_dev *hdev = vport->back; 210 int status; 211 212 if (mbx_req->msg[1] == HCLGE_MBX_MAC_VLAN_UC_MODIFY) { 213 const u8 *old_addr = (const u8 *)(&mbx_req->msg[8]); 214 215 hclge_rm_uc_addr_common(vport, old_addr); 216 status = hclge_add_uc_addr_common(vport, mac_addr); 217 if (status) 218 hclge_add_uc_addr_common(vport, old_addr); 219 } else if (mbx_req->msg[1] == HCLGE_MBX_MAC_VLAN_UC_ADD) { 220 status = hclge_add_uc_addr_common(vport, mac_addr); 221 } else if (mbx_req->msg[1] == HCLGE_MBX_MAC_VLAN_UC_REMOVE) { 222 status = hclge_rm_uc_addr_common(vport, mac_addr); 223 } else { 224 dev_err(&hdev->pdev->dev, 225 "failed to set unicast mac addr, unknown subcode %d\n", 226 mbx_req->msg[1]); 227 return -EIO; 228 } 229 230 if (gen_resp) 231 hclge_gen_resp_to_vf(vport, mbx_req, status, NULL, 0); 232 233 return 0; 234 } 235 236 static int hclge_set_vf_mc_mta_status(struct hclge_vport *vport, 237 u8 *msg, u8 idx, bool is_end) 238 { 239 #define HCLGE_MTA_STATUS_MSG_SIZE 13 240 #define HCLGE_MTA_STATUS_MSG_BITS \ 241 (HCLGE_MTA_STATUS_MSG_SIZE * BITS_PER_BYTE) 242 #define HCLGE_MTA_STATUS_MSG_END_BITS \ 243 (HCLGE_MTA_TBL_SIZE % HCLGE_MTA_STATUS_MSG_BITS) 244 unsigned long status[BITS_TO_LONGS(HCLGE_MTA_STATUS_MSG_BITS)]; 245 u16 tbl_cnt; 246 u16 tbl_idx; 247 u8 msg_ofs; 248 u8 msg_bit; 249 250 tbl_cnt = is_end ? HCLGE_MTA_STATUS_MSG_END_BITS : 251 HCLGE_MTA_STATUS_MSG_BITS; 252 253 /* set msg field */ 254 msg_ofs = 0; 255 msg_bit = 0; 256 memset(status, 0, sizeof(status)); 257 for (tbl_idx = 0; tbl_idx < tbl_cnt; tbl_idx++) { 258 if (msg[msg_ofs] & BIT(msg_bit)) 259 set_bit(tbl_idx, status); 260 261 msg_bit++; 262 if (msg_bit == BITS_PER_BYTE) { 263 msg_bit = 0; 264 msg_ofs++; 265 } 266 } 267 268 return hclge_update_mta_status_common(vport, 269 status, idx * HCLGE_MTA_STATUS_MSG_BITS, 270 tbl_cnt, is_end); 271 } 272 273 static int hclge_set_vf_mc_mac_addr(struct hclge_vport *vport, 274 struct hclge_mbx_vf_to_pf_cmd *mbx_req, 275 bool gen_resp) 276 { 277 const u8 *mac_addr = (const u8 *)(&mbx_req->msg[2]); 278 struct hclge_dev *hdev = vport->back; 279 u8 resp_len = 0; 280 u8 resp_data; 281 int status; 282 283 if (mbx_req->msg[1] == HCLGE_MBX_MAC_VLAN_MC_ADD) { 284 status = hclge_add_mc_addr_common(vport, mac_addr); 285 } else if (mbx_req->msg[1] == HCLGE_MBX_MAC_VLAN_MC_REMOVE) { 286 status = hclge_rm_mc_addr_common(vport, mac_addr); 287 } else if (mbx_req->msg[1] == HCLGE_MBX_MAC_VLAN_MC_FUNC_MTA_ENABLE) { 288 u8 func_id = vport->vport_id; 289 bool enable = mbx_req->msg[2]; 290 291 status = hclge_cfg_func_mta_filter(hdev, func_id, enable); 292 } else if (mbx_req->msg[1] == HCLGE_MBX_MAC_VLAN_MTA_TYPE_READ) { 293 resp_data = hdev->mta_mac_sel_type; 294 resp_len = sizeof(u8); 295 gen_resp = true; 296 status = 0; 297 } else if (mbx_req->msg[1] == HCLGE_MBX_MAC_VLAN_MTA_STATUS_UPDATE) { 298 /* mta status update msg format 299 * msg[2.6 : 2.0] msg index 300 * msg[2.7] msg is end 301 * msg[15 : 3] mta status bits[103 : 0] 302 */ 303 bool is_end = (mbx_req->msg[2] & 0x80) ? true : false; 304 305 status = hclge_set_vf_mc_mta_status(vport, &mbx_req->msg[3], 306 mbx_req->msg[2] & 0x7F, 307 is_end); 308 } else { 309 dev_err(&hdev->pdev->dev, 310 "failed to set mcast mac addr, unknown subcode %d\n", 311 mbx_req->msg[1]); 312 return -EIO; 313 } 314 315 if (gen_resp) 316 hclge_gen_resp_to_vf(vport, mbx_req, status, 317 &resp_data, resp_len); 318 319 return 0; 320 } 321 322 static int hclge_set_vf_vlan_cfg(struct hclge_vport *vport, 323 struct hclge_mbx_vf_to_pf_cmd *mbx_req, 324 bool gen_resp) 325 { 326 int status = 0; 327 328 if (mbx_req->msg[1] == HCLGE_MBX_VLAN_FILTER) { 329 struct hnae3_handle *handle = &vport->nic; 330 u16 vlan, proto; 331 bool is_kill; 332 333 is_kill = !!mbx_req->msg[2]; 334 memcpy(&vlan, &mbx_req->msg[3], sizeof(vlan)); 335 memcpy(&proto, &mbx_req->msg[5], sizeof(proto)); 336 status = hclge_set_vlan_filter(handle, cpu_to_be16(proto), 337 vlan, is_kill); 338 } else if (mbx_req->msg[1] == HCLGE_MBX_VLAN_RX_OFF_CFG) { 339 struct hnae3_handle *handle = &vport->nic; 340 bool en = mbx_req->msg[2] ? true : false; 341 342 status = hclge_en_hw_strip_rxvtag(handle, en); 343 } 344 345 if (gen_resp) 346 status = hclge_gen_resp_to_vf(vport, mbx_req, status, NULL, 0); 347 348 return status; 349 } 350 351 static int hclge_get_vf_tcinfo(struct hclge_vport *vport, 352 struct hclge_mbx_vf_to_pf_cmd *mbx_req, 353 bool gen_resp) 354 { 355 struct hclge_dev *hdev = vport->back; 356 int ret; 357 358 ret = hclge_gen_resp_to_vf(vport, mbx_req, 0, &hdev->hw_tc_map, 359 sizeof(u8)); 360 361 return ret; 362 } 363 364 static int hclge_get_vf_queue_info(struct hclge_vport *vport, 365 struct hclge_mbx_vf_to_pf_cmd *mbx_req, 366 bool gen_resp) 367 { 368 #define HCLGE_TQPS_RSS_INFO_LEN 8 369 u8 resp_data[HCLGE_TQPS_RSS_INFO_LEN]; 370 struct hclge_dev *hdev = vport->back; 371 372 /* get the queue related info */ 373 memcpy(&resp_data[0], &vport->alloc_tqps, sizeof(u16)); 374 memcpy(&resp_data[2], &vport->nic.kinfo.rss_size, sizeof(u16)); 375 memcpy(&resp_data[4], &hdev->num_desc, sizeof(u16)); 376 memcpy(&resp_data[6], &hdev->rx_buf_len, sizeof(u16)); 377 378 return hclge_gen_resp_to_vf(vport, mbx_req, 0, resp_data, 379 HCLGE_TQPS_RSS_INFO_LEN); 380 } 381 382 static int hclge_get_link_info(struct hclge_vport *vport, 383 struct hclge_mbx_vf_to_pf_cmd *mbx_req) 384 { 385 struct hclge_dev *hdev = vport->back; 386 u16 link_status; 387 u8 msg_data[8]; 388 u8 dest_vfid; 389 u16 duplex; 390 391 /* mac.link can only be 0 or 1 */ 392 link_status = (u16)hdev->hw.mac.link; 393 duplex = hdev->hw.mac.duplex; 394 memcpy(&msg_data[0], &link_status, sizeof(u16)); 395 memcpy(&msg_data[2], &hdev->hw.mac.speed, sizeof(u32)); 396 memcpy(&msg_data[6], &duplex, sizeof(u16)); 397 dest_vfid = mbx_req->mbx_src_vfid; 398 399 /* send this requested info to VF */ 400 return hclge_send_mbx_msg(vport, msg_data, sizeof(msg_data), 401 HCLGE_MBX_LINK_STAT_CHANGE, dest_vfid); 402 } 403 404 static void hclge_mbx_reset_vf_queue(struct hclge_vport *vport, 405 struct hclge_mbx_vf_to_pf_cmd *mbx_req) 406 { 407 u16 queue_id; 408 409 memcpy(&queue_id, &mbx_req->msg[2], sizeof(queue_id)); 410 411 hclge_reset_vf_queue(vport, queue_id); 412 413 /* send response msg to VF after queue reset complete*/ 414 hclge_gen_resp_to_vf(vport, mbx_req, 0, NULL, 0); 415 } 416 417 static void hclge_reset_vf(struct hclge_vport *vport, 418 struct hclge_mbx_vf_to_pf_cmd *mbx_req) 419 { 420 struct hclge_dev *hdev = vport->back; 421 int ret; 422 423 dev_warn(&hdev->pdev->dev, "PF received VF reset request from VF %d!", 424 mbx_req->mbx_src_vfid); 425 426 /* Acknowledge VF that PF is now about to assert the reset for the VF. 427 * On receiving this message VF will get into pending state and will 428 * start polling for the hardware reset completion status. 429 */ 430 ret = hclge_inform_reset_assert_to_vf(vport); 431 if (ret) { 432 dev_err(&hdev->pdev->dev, 433 "PF fail(%d) to inform VF(%d)of reset, reset failed!\n", 434 ret, vport->vport_id); 435 return; 436 } 437 438 dev_warn(&hdev->pdev->dev, "PF is now resetting VF %d.\n", 439 mbx_req->mbx_src_vfid); 440 /* reset this virtual function */ 441 hclge_func_reset_cmd(hdev, mbx_req->mbx_src_vfid); 442 } 443 444 static bool hclge_cmd_crq_empty(struct hclge_hw *hw) 445 { 446 u32 tail = hclge_read_dev(hw, HCLGE_NIC_CRQ_TAIL_REG); 447 448 return tail == hw->cmq.crq.next_to_use; 449 } 450 451 void hclge_mbx_handler(struct hclge_dev *hdev) 452 { 453 struct hclge_cmq_ring *crq = &hdev->hw.cmq.crq; 454 struct hclge_mbx_vf_to_pf_cmd *req; 455 struct hclge_vport *vport; 456 struct hclge_desc *desc; 457 int ret, flag; 458 459 /* handle all the mailbox requests in the queue */ 460 while (!hclge_cmd_crq_empty(&hdev->hw)) { 461 desc = &crq->desc[crq->next_to_use]; 462 req = (struct hclge_mbx_vf_to_pf_cmd *)desc->data; 463 464 flag = le16_to_cpu(crq->desc[crq->next_to_use].flag); 465 if (unlikely(!hnae3_get_bit(flag, HCLGE_CMDQ_RX_OUTVLD_B))) { 466 dev_warn(&hdev->pdev->dev, 467 "dropped invalid mailbox message, code = %d\n", 468 req->msg[0]); 469 470 /* dropping/not processing this invalid message */ 471 crq->desc[crq->next_to_use].flag = 0; 472 hclge_mbx_ring_ptr_move_crq(crq); 473 continue; 474 } 475 476 vport = &hdev->vport[req->mbx_src_vfid]; 477 478 switch (req->msg[0]) { 479 case HCLGE_MBX_MAP_RING_TO_VECTOR: 480 ret = hclge_map_unmap_ring_to_vf_vector(vport, true, 481 req); 482 break; 483 case HCLGE_MBX_UNMAP_RING_TO_VECTOR: 484 ret = hclge_map_unmap_ring_to_vf_vector(vport, false, 485 req); 486 break; 487 case HCLGE_MBX_SET_PROMISC_MODE: 488 ret = hclge_set_vf_promisc_mode(vport, req); 489 if (ret) 490 dev_err(&hdev->pdev->dev, 491 "PF fail(%d) to set VF promisc mode\n", 492 ret); 493 break; 494 case HCLGE_MBX_SET_UNICAST: 495 ret = hclge_set_vf_uc_mac_addr(vport, req, true); 496 if (ret) 497 dev_err(&hdev->pdev->dev, 498 "PF fail(%d) to set VF UC MAC Addr\n", 499 ret); 500 break; 501 case HCLGE_MBX_SET_MULTICAST: 502 ret = hclge_set_vf_mc_mac_addr(vport, req, false); 503 if (ret) 504 dev_err(&hdev->pdev->dev, 505 "PF fail(%d) to set VF MC MAC Addr\n", 506 ret); 507 break; 508 case HCLGE_MBX_SET_VLAN: 509 ret = hclge_set_vf_vlan_cfg(vport, req, false); 510 if (ret) 511 dev_err(&hdev->pdev->dev, 512 "PF failed(%d) to config VF's VLAN\n", 513 ret); 514 break; 515 case HCLGE_MBX_GET_QINFO: 516 ret = hclge_get_vf_queue_info(vport, req, true); 517 if (ret) 518 dev_err(&hdev->pdev->dev, 519 "PF failed(%d) to get Q info for VF\n", 520 ret); 521 break; 522 case HCLGE_MBX_GET_TCINFO: 523 ret = hclge_get_vf_tcinfo(vport, req, true); 524 if (ret) 525 dev_err(&hdev->pdev->dev, 526 "PF failed(%d) to get TC info for VF\n", 527 ret); 528 break; 529 case HCLGE_MBX_GET_LINK_STATUS: 530 ret = hclge_get_link_info(vport, req); 531 if (ret) 532 dev_err(&hdev->pdev->dev, 533 "PF fail(%d) to get link stat for VF\n", 534 ret); 535 break; 536 case HCLGE_MBX_QUEUE_RESET: 537 hclge_mbx_reset_vf_queue(vport, req); 538 break; 539 case HCLGE_MBX_RESET: 540 hclge_reset_vf(vport, req); 541 break; 542 default: 543 dev_err(&hdev->pdev->dev, 544 "un-supported mailbox message, code = %d\n", 545 req->msg[0]); 546 break; 547 } 548 crq->desc[crq->next_to_use].flag = 0; 549 hclge_mbx_ring_ptr_move_crq(crq); 550 } 551 552 /* Write back CMDQ_RQ header pointer, M7 need this pointer */ 553 hclge_write_dev(&hdev->hw, HCLGE_NIC_CRQ_HEAD_REG, crq->next_to_use); 554 } 555