1 /* 2 * Copyright (c) 2016~2017 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #ifndef __HCLGE_MAIN_H 11 #define __HCLGE_MAIN_H 12 #include <linux/fs.h> 13 #include <linux/types.h> 14 #include <linux/phy.h> 15 #include <linux/if_vlan.h> 16 17 #include "hclge_cmd.h" 18 #include "hnae3.h" 19 20 #define HCLGE_MOD_VERSION "1.0" 21 #define HCLGE_DRIVER_NAME "hclge" 22 23 #define HCLGE_INVALID_VPORT 0xffff 24 25 #define HCLGE_ROCE_VECTOR_OFFSET 96 26 27 #define HCLGE_PF_CFG_BLOCK_SIZE 32 28 #define HCLGE_PF_CFG_DESC_NUM \ 29 (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES) 30 31 #define HCLGE_VECTOR_REG_BASE 0x20000 32 #define HCLGE_MISC_VECTOR_REG_BASE 0x20400 33 34 #define HCLGE_VECTOR_REG_OFFSET 0x4 35 #define HCLGE_VECTOR_VF_OFFSET 0x100000 36 37 #define HCLGE_RSS_IND_TBL_SIZE 512 38 #define HCLGE_RSS_SET_BITMAP_MSK GENMASK(15, 0) 39 #define HCLGE_RSS_KEY_SIZE 40 40 #define HCLGE_RSS_HASH_ALGO_TOEPLITZ 0 41 #define HCLGE_RSS_HASH_ALGO_SIMPLE 1 42 #define HCLGE_RSS_HASH_ALGO_SYMMETRIC 2 43 #define HCLGE_RSS_HASH_ALGO_MASK 0xf 44 #define HCLGE_RSS_CFG_TBL_NUM \ 45 (HCLGE_RSS_IND_TBL_SIZE / HCLGE_RSS_CFG_TBL_SIZE) 46 47 #define HCLGE_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0) 48 #define HCLGE_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0) 49 #define HCLGE_D_PORT_BIT BIT(0) 50 #define HCLGE_S_PORT_BIT BIT(1) 51 #define HCLGE_D_IP_BIT BIT(2) 52 #define HCLGE_S_IP_BIT BIT(3) 53 #define HCLGE_V_TAG_BIT BIT(4) 54 55 #define HCLGE_RSS_TC_SIZE_0 1 56 #define HCLGE_RSS_TC_SIZE_1 2 57 #define HCLGE_RSS_TC_SIZE_2 4 58 #define HCLGE_RSS_TC_SIZE_3 8 59 #define HCLGE_RSS_TC_SIZE_4 16 60 #define HCLGE_RSS_TC_SIZE_5 32 61 #define HCLGE_RSS_TC_SIZE_6 64 62 #define HCLGE_RSS_TC_SIZE_7 128 63 64 #define HCLGE_TQP_RESET_TRY_TIMES 10 65 66 #define HCLGE_PHY_PAGE_MDIX 0 67 #define HCLGE_PHY_PAGE_COPPER 0 68 69 /* Page Selection Reg. */ 70 #define HCLGE_PHY_PAGE_REG 22 71 72 /* Copper Specific Control Register */ 73 #define HCLGE_PHY_CSC_REG 16 74 75 /* Copper Specific Status Register */ 76 #define HCLGE_PHY_CSS_REG 17 77 78 #define HCLGE_PHY_MDIX_CTRL_S (5) 79 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5) 80 81 #define HCLGE_PHY_MDIX_STATUS_B (6) 82 #define HCLGE_PHY_SPEED_DUP_RESOLVE_B (11) 83 84 /* Factor used to calculate offset and bitmap of VF num */ 85 #define HCLGE_VF_NUM_PER_CMD 64 86 #define HCLGE_VF_NUM_PER_BYTE 8 87 88 /* Reset related Registers */ 89 #define HCLGE_MISC_RESET_STS_REG 0x20700 90 #define HCLGE_GLOBAL_RESET_REG 0x20A00 91 #define HCLGE_GLOBAL_RESET_BIT 0x0 92 #define HCLGE_CORE_RESET_BIT 0x1 93 #define HCLGE_FUN_RST_ING 0x20C00 94 #define HCLGE_FUN_RST_ING_B 0 95 96 /* Vector0 register bits define */ 97 #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5 98 #define HCLGE_VECTOR0_CORERESET_INT_B 6 99 #define HCLGE_VECTOR0_IMPRESET_INT_B 7 100 101 /* Vector0 interrupt CMDQ event source register(RW) */ 102 #define HCLGE_VECTOR0_CMDQ_SRC_REG 0x27100 103 /* CMDQ register bits for RX event(=MBX event) */ 104 #define HCLGE_VECTOR0_RX_CMDQ_INT_B 1 105 106 #define HCLGE_MAC_DEFAULT_FRAME \ 107 (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN + ETH_DATA_LEN) 108 #define HCLGE_MAC_MIN_FRAME 64 109 #define HCLGE_MAC_MAX_FRAME 9728 110 111 #define HCLGE_SUPPORT_1G_BIT BIT(0) 112 #define HCLGE_SUPPORT_10G_BIT BIT(1) 113 #define HCLGE_SUPPORT_25G_BIT BIT(2) 114 #define HCLGE_SUPPORT_50G_BIT BIT(3) 115 #define HCLGE_SUPPORT_100G_BIT BIT(4) 116 117 enum HCLGE_DEV_STATE { 118 HCLGE_STATE_REINITING, 119 HCLGE_STATE_DOWN, 120 HCLGE_STATE_DISABLED, 121 HCLGE_STATE_REMOVING, 122 HCLGE_STATE_SERVICE_INITED, 123 HCLGE_STATE_SERVICE_SCHED, 124 HCLGE_STATE_RST_SERVICE_SCHED, 125 HCLGE_STATE_RST_HANDLING, 126 HCLGE_STATE_MBX_SERVICE_SCHED, 127 HCLGE_STATE_MBX_HANDLING, 128 HCLGE_STATE_STATISTICS_UPDATING, 129 HCLGE_STATE_MAX 130 }; 131 132 enum hclge_evt_cause { 133 HCLGE_VECTOR0_EVENT_RST, 134 HCLGE_VECTOR0_EVENT_MBX, 135 HCLGE_VECTOR0_EVENT_OTHER, 136 }; 137 138 #define HCLGE_MPF_ENBALE 1 139 struct hclge_caps { 140 u16 num_tqp; 141 u16 num_buffer_cell; 142 u32 flag; 143 u16 vmdq; 144 }; 145 146 enum HCLGE_MAC_SPEED { 147 HCLGE_MAC_SPEED_10M = 10, /* 10 Mbps */ 148 HCLGE_MAC_SPEED_100M = 100, /* 100 Mbps */ 149 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */ 150 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */ 151 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */ 152 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */ 153 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */ 154 HCLGE_MAC_SPEED_100G = 100000 /* 100000 Mbps = 100 Gbps */ 155 }; 156 157 enum HCLGE_MAC_DUPLEX { 158 HCLGE_MAC_HALF, 159 HCLGE_MAC_FULL 160 }; 161 162 enum hclge_mta_dmac_sel_type { 163 HCLGE_MAC_ADDR_47_36, 164 HCLGE_MAC_ADDR_46_35, 165 HCLGE_MAC_ADDR_45_34, 166 HCLGE_MAC_ADDR_44_33, 167 }; 168 169 struct hclge_mac { 170 u8 phy_addr; 171 u8 flag; 172 u8 media_type; 173 u8 mac_addr[ETH_ALEN]; 174 u8 autoneg; 175 u8 duplex; 176 u32 speed; 177 int link; /* store the link status of mac & phy (if phy exit)*/ 178 struct phy_device *phydev; 179 struct mii_bus *mdio_bus; 180 phy_interface_t phy_if; 181 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); 182 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); 183 }; 184 185 struct hclge_hw { 186 void __iomem *io_base; 187 struct hclge_mac mac; 188 int num_vec; 189 struct hclge_cmq cmq; 190 struct hclge_caps caps; 191 void *back; 192 }; 193 194 /* TQP stats */ 195 struct hlcge_tqp_stats { 196 /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */ 197 u64 rcb_tx_ring_pktnum_rcd; /* 32bit */ 198 /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */ 199 u64 rcb_rx_ring_pktnum_rcd; /* 32bit */ 200 }; 201 202 struct hclge_tqp { 203 struct device *dev; /* Device for DMA mapping */ 204 struct hnae3_queue q; 205 struct hlcge_tqp_stats tqp_stats; 206 u16 index; /* Global index in a NIC controller */ 207 208 bool alloced; 209 }; 210 211 enum hclge_fc_mode { 212 HCLGE_FC_NONE, 213 HCLGE_FC_RX_PAUSE, 214 HCLGE_FC_TX_PAUSE, 215 HCLGE_FC_FULL, 216 HCLGE_FC_PFC, 217 HCLGE_FC_DEFAULT 218 }; 219 220 #define HCLGE_PG_NUM 4 221 #define HCLGE_SCH_MODE_SP 0 222 #define HCLGE_SCH_MODE_DWRR 1 223 struct hclge_pg_info { 224 u8 pg_id; 225 u8 pg_sch_mode; /* 0: sp; 1: dwrr */ 226 u8 tc_bit_map; 227 u32 bw_limit; 228 u8 tc_dwrr[HNAE3_MAX_TC]; 229 }; 230 231 struct hclge_tc_info { 232 u8 tc_id; 233 u8 tc_sch_mode; /* 0: sp; 1: dwrr */ 234 u8 pgid; 235 u32 bw_limit; 236 }; 237 238 struct hclge_cfg { 239 u8 vmdq_vport_num; 240 u8 tc_num; 241 u16 tqp_desc_num; 242 u16 rx_buf_len; 243 u16 rss_size_max; 244 u8 phy_addr; 245 u8 media_type; 246 u8 mac_addr[ETH_ALEN]; 247 u8 default_speed; 248 u32 numa_node_map; 249 u8 speed_ability; 250 }; 251 252 struct hclge_tm_info { 253 u8 num_tc; 254 u8 num_pg; /* It must be 1 if vNET-Base schd */ 255 u8 pg_dwrr[HCLGE_PG_NUM]; 256 u8 prio_tc[HNAE3_MAX_USER_PRIO]; 257 struct hclge_pg_info pg_info[HCLGE_PG_NUM]; 258 struct hclge_tc_info tc_info[HNAE3_MAX_TC]; 259 enum hclge_fc_mode fc_mode; 260 u8 hw_pfc_map; /* Allow for packet drop or not on this TC */ 261 }; 262 263 struct hclge_comm_stats_str { 264 char desc[ETH_GSTRING_LEN]; 265 unsigned long offset; 266 }; 267 268 /* all 64bit stats, opcode id: 0x0030 */ 269 struct hclge_64_bit_stats { 270 /* query_igu_stat */ 271 u64 igu_rx_oversize_pkt; 272 u64 igu_rx_undersize_pkt; 273 u64 igu_rx_out_all_pkt; 274 u64 igu_rx_uni_pkt; 275 u64 igu_rx_multi_pkt; 276 u64 igu_rx_broad_pkt; 277 u64 rsv0; 278 279 /* query_egu_stat */ 280 u64 egu_tx_out_all_pkt; 281 u64 egu_tx_uni_pkt; 282 u64 egu_tx_multi_pkt; 283 u64 egu_tx_broad_pkt; 284 285 /* ssu_ppp packet stats */ 286 u64 ssu_ppp_mac_key_num; 287 u64 ssu_ppp_host_key_num; 288 u64 ppp_ssu_mac_rlt_num; 289 u64 ppp_ssu_host_rlt_num; 290 291 /* ssu_tx_in_out_dfx_stats */ 292 u64 ssu_tx_in_num; 293 u64 ssu_tx_out_num; 294 /* ssu_rx_in_out_dfx_stats */ 295 u64 ssu_rx_in_num; 296 u64 ssu_rx_out_num; 297 }; 298 299 /* all 32bit stats, opcode id: 0x0031 */ 300 struct hclge_32_bit_stats { 301 u64 igu_rx_err_pkt; 302 u64 igu_rx_no_eof_pkt; 303 u64 igu_rx_no_sof_pkt; 304 u64 egu_tx_1588_pkt; 305 u64 egu_tx_err_pkt; 306 u64 ssu_full_drop_num; 307 u64 ssu_part_drop_num; 308 u64 ppp_key_drop_num; 309 u64 ppp_rlt_drop_num; 310 u64 ssu_key_drop_num; 311 u64 pkt_curr_buf_cnt; 312 u64 qcn_fb_rcv_cnt; 313 u64 qcn_fb_drop_cnt; 314 u64 qcn_fb_invaild_cnt; 315 u64 rsv0; 316 u64 rx_packet_tc0_in_cnt; 317 u64 rx_packet_tc1_in_cnt; 318 u64 rx_packet_tc2_in_cnt; 319 u64 rx_packet_tc3_in_cnt; 320 u64 rx_packet_tc4_in_cnt; 321 u64 rx_packet_tc5_in_cnt; 322 u64 rx_packet_tc6_in_cnt; 323 u64 rx_packet_tc7_in_cnt; 324 u64 rx_packet_tc0_out_cnt; 325 u64 rx_packet_tc1_out_cnt; 326 u64 rx_packet_tc2_out_cnt; 327 u64 rx_packet_tc3_out_cnt; 328 u64 rx_packet_tc4_out_cnt; 329 u64 rx_packet_tc5_out_cnt; 330 u64 rx_packet_tc6_out_cnt; 331 u64 rx_packet_tc7_out_cnt; 332 333 /* Tx packet level statistics */ 334 u64 tx_packet_tc0_in_cnt; 335 u64 tx_packet_tc1_in_cnt; 336 u64 tx_packet_tc2_in_cnt; 337 u64 tx_packet_tc3_in_cnt; 338 u64 tx_packet_tc4_in_cnt; 339 u64 tx_packet_tc5_in_cnt; 340 u64 tx_packet_tc6_in_cnt; 341 u64 tx_packet_tc7_in_cnt; 342 u64 tx_packet_tc0_out_cnt; 343 u64 tx_packet_tc1_out_cnt; 344 u64 tx_packet_tc2_out_cnt; 345 u64 tx_packet_tc3_out_cnt; 346 u64 tx_packet_tc4_out_cnt; 347 u64 tx_packet_tc5_out_cnt; 348 u64 tx_packet_tc6_out_cnt; 349 u64 tx_packet_tc7_out_cnt; 350 351 /* packet buffer statistics */ 352 u64 pkt_curr_buf_tc0_cnt; 353 u64 pkt_curr_buf_tc1_cnt; 354 u64 pkt_curr_buf_tc2_cnt; 355 u64 pkt_curr_buf_tc3_cnt; 356 u64 pkt_curr_buf_tc4_cnt; 357 u64 pkt_curr_buf_tc5_cnt; 358 u64 pkt_curr_buf_tc6_cnt; 359 u64 pkt_curr_buf_tc7_cnt; 360 361 u64 mb_uncopy_num; 362 u64 lo_pri_unicast_rlt_drop_num; 363 u64 hi_pri_multicast_rlt_drop_num; 364 u64 lo_pri_multicast_rlt_drop_num; 365 u64 rx_oq_drop_pkt_cnt; 366 u64 tx_oq_drop_pkt_cnt; 367 u64 nic_l2_err_drop_pkt_cnt; 368 u64 roc_l2_err_drop_pkt_cnt; 369 }; 370 371 /* mac stats ,opcode id: 0x0032 */ 372 struct hclge_mac_stats { 373 u64 mac_tx_mac_pause_num; 374 u64 mac_rx_mac_pause_num; 375 u64 mac_tx_pfc_pri0_pkt_num; 376 u64 mac_tx_pfc_pri1_pkt_num; 377 u64 mac_tx_pfc_pri2_pkt_num; 378 u64 mac_tx_pfc_pri3_pkt_num; 379 u64 mac_tx_pfc_pri4_pkt_num; 380 u64 mac_tx_pfc_pri5_pkt_num; 381 u64 mac_tx_pfc_pri6_pkt_num; 382 u64 mac_tx_pfc_pri7_pkt_num; 383 u64 mac_rx_pfc_pri0_pkt_num; 384 u64 mac_rx_pfc_pri1_pkt_num; 385 u64 mac_rx_pfc_pri2_pkt_num; 386 u64 mac_rx_pfc_pri3_pkt_num; 387 u64 mac_rx_pfc_pri4_pkt_num; 388 u64 mac_rx_pfc_pri5_pkt_num; 389 u64 mac_rx_pfc_pri6_pkt_num; 390 u64 mac_rx_pfc_pri7_pkt_num; 391 u64 mac_tx_total_pkt_num; 392 u64 mac_tx_total_oct_num; 393 u64 mac_tx_good_pkt_num; 394 u64 mac_tx_bad_pkt_num; 395 u64 mac_tx_good_oct_num; 396 u64 mac_tx_bad_oct_num; 397 u64 mac_tx_uni_pkt_num; 398 u64 mac_tx_multi_pkt_num; 399 u64 mac_tx_broad_pkt_num; 400 u64 mac_tx_undersize_pkt_num; 401 u64 mac_tx_oversize_pkt_num; 402 u64 mac_tx_64_oct_pkt_num; 403 u64 mac_tx_65_127_oct_pkt_num; 404 u64 mac_tx_128_255_oct_pkt_num; 405 u64 mac_tx_256_511_oct_pkt_num; 406 u64 mac_tx_512_1023_oct_pkt_num; 407 u64 mac_tx_1024_1518_oct_pkt_num; 408 u64 mac_tx_1519_2047_oct_pkt_num; 409 u64 mac_tx_2048_4095_oct_pkt_num; 410 u64 mac_tx_4096_8191_oct_pkt_num; 411 u64 rsv0; 412 u64 mac_tx_8192_9216_oct_pkt_num; 413 u64 mac_tx_9217_12287_oct_pkt_num; 414 u64 mac_tx_12288_16383_oct_pkt_num; 415 u64 mac_tx_1519_max_good_oct_pkt_num; 416 u64 mac_tx_1519_max_bad_oct_pkt_num; 417 418 u64 mac_rx_total_pkt_num; 419 u64 mac_rx_total_oct_num; 420 u64 mac_rx_good_pkt_num; 421 u64 mac_rx_bad_pkt_num; 422 u64 mac_rx_good_oct_num; 423 u64 mac_rx_bad_oct_num; 424 u64 mac_rx_uni_pkt_num; 425 u64 mac_rx_multi_pkt_num; 426 u64 mac_rx_broad_pkt_num; 427 u64 mac_rx_undersize_pkt_num; 428 u64 mac_rx_oversize_pkt_num; 429 u64 mac_rx_64_oct_pkt_num; 430 u64 mac_rx_65_127_oct_pkt_num; 431 u64 mac_rx_128_255_oct_pkt_num; 432 u64 mac_rx_256_511_oct_pkt_num; 433 u64 mac_rx_512_1023_oct_pkt_num; 434 u64 mac_rx_1024_1518_oct_pkt_num; 435 u64 mac_rx_1519_2047_oct_pkt_num; 436 u64 mac_rx_2048_4095_oct_pkt_num; 437 u64 mac_rx_4096_8191_oct_pkt_num; 438 u64 rsv1; 439 u64 mac_rx_8192_9216_oct_pkt_num; 440 u64 mac_rx_9217_12287_oct_pkt_num; 441 u64 mac_rx_12288_16383_oct_pkt_num; 442 u64 mac_rx_1519_max_good_oct_pkt_num; 443 u64 mac_rx_1519_max_bad_oct_pkt_num; 444 445 u64 mac_tx_fragment_pkt_num; 446 u64 mac_tx_undermin_pkt_num; 447 u64 mac_tx_jabber_pkt_num; 448 u64 mac_tx_err_all_pkt_num; 449 u64 mac_tx_from_app_good_pkt_num; 450 u64 mac_tx_from_app_bad_pkt_num; 451 u64 mac_rx_fragment_pkt_num; 452 u64 mac_rx_undermin_pkt_num; 453 u64 mac_rx_jabber_pkt_num; 454 u64 mac_rx_fcs_err_pkt_num; 455 u64 mac_rx_send_app_good_pkt_num; 456 u64 mac_rx_send_app_bad_pkt_num; 457 }; 458 459 #define HCLGE_STATS_TIMER_INTERVAL (60 * 5) 460 struct hclge_hw_stats { 461 struct hclge_mac_stats mac_stats; 462 struct hclge_64_bit_stats all_64_bit_stats; 463 struct hclge_32_bit_stats all_32_bit_stats; 464 u32 stats_timer; 465 }; 466 467 struct hclge_vlan_type_cfg { 468 u16 rx_ot_fst_vlan_type; 469 u16 rx_ot_sec_vlan_type; 470 u16 rx_in_fst_vlan_type; 471 u16 rx_in_sec_vlan_type; 472 u16 tx_ot_vlan_type; 473 u16 tx_in_vlan_type; 474 }; 475 476 #define HCLGE_VPORT_NUM 256 477 struct hclge_dev { 478 struct pci_dev *pdev; 479 struct hnae3_ae_dev *ae_dev; 480 struct hclge_hw hw; 481 struct hclge_misc_vector misc_vector; 482 struct hclge_hw_stats hw_stats; 483 unsigned long state; 484 485 enum hnae3_reset_type reset_type; 486 unsigned long reset_request; /* reset has been requested */ 487 unsigned long reset_pending; /* client rst is pending to be served */ 488 u32 fw_version; 489 u16 num_vmdq_vport; /* Num vmdq vport this PF has set up */ 490 u16 num_tqps; /* Num task queue pairs of this PF */ 491 u16 num_req_vfs; /* Num VFs requested for this PF */ 492 493 /* Base task tqp physical id of this PF */ 494 u16 base_tqp_pid; 495 u16 alloc_rss_size; /* Allocated RSS task queue */ 496 u16 rss_size_max; /* HW defined max RSS task queue */ 497 498 /* Num of guaranteed filters for this PF */ 499 u16 fdir_pf_filter_count; 500 u16 num_alloc_vport; /* Num vports this driver supports */ 501 u32 numa_node_mask; 502 u16 rx_buf_len; 503 u16 num_desc; 504 u8 hw_tc_map; 505 u8 tc_num_last_time; 506 enum hclge_fc_mode fc_mode_last_time; 507 508 #define HCLGE_FLAG_TC_BASE_SCH_MODE 1 509 #define HCLGE_FLAG_VNET_BASE_SCH_MODE 2 510 u8 tx_sch_mode; 511 u8 tc_max; 512 u8 pfc_max; 513 514 u8 default_up; 515 u8 dcbx_cap; 516 struct hclge_tm_info tm_info; 517 518 u16 num_msi; 519 u16 num_msi_left; 520 u16 num_msi_used; 521 u32 base_msi_vector; 522 u16 *vector_status; 523 int *vector_irq; 524 u16 num_roce_msi; /* Num of roce vectors for this PF */ 525 int roce_base_vector; 526 527 u16 pending_udp_bitmap; 528 529 u16 rx_itr_default; 530 u16 tx_itr_default; 531 532 u16 adminq_work_limit; /* Num of admin receive queue desc to process */ 533 unsigned long service_timer_period; 534 unsigned long service_timer_previous; 535 struct timer_list service_timer; 536 struct work_struct service_task; 537 struct work_struct rst_service_task; 538 struct work_struct mbx_service_task; 539 540 bool cur_promisc; 541 int num_alloc_vfs; /* Actual number of VFs allocated */ 542 543 struct hclge_tqp *htqp; 544 struct hclge_vport *vport; 545 546 struct dentry *hclge_dbgfs; 547 548 struct hnae3_client *nic_client; 549 struct hnae3_client *roce_client; 550 551 #define HCLGE_FLAG_MAIN BIT(0) 552 #define HCLGE_FLAG_DCB_CAPABLE BIT(1) 553 #define HCLGE_FLAG_DCB_ENABLE BIT(2) 554 #define HCLGE_FLAG_MQPRIO_ENABLE BIT(3) 555 u32 flag; 556 557 u32 pkt_buf_size; /* Total pf buf size for tx/rx */ 558 u32 mps; /* Max packet size */ 559 560 enum hclge_mta_dmac_sel_type mta_mac_sel_type; 561 bool enable_mta; /* Mutilcast filter enable */ 562 bool accept_mta_mc; /* Whether accept mta filter multicast */ 563 564 struct hclge_vlan_type_cfg vlan_type_cfg; 565 566 u64 rx_pkts_for_led; 567 u64 tx_pkts_for_led; 568 unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 569 }; 570 571 /* VPort level vlan tag configuration for TX direction */ 572 struct hclge_tx_vtag_cfg { 573 bool accept_tag; /* Whether accept tagged packet from host */ 574 bool accept_untag; /* Whether accept untagged packet from host */ 575 bool insert_tag1_en; /* Whether insert inner vlan tag */ 576 bool insert_tag2_en; /* Whether insert outer vlan tag */ 577 u16 default_tag1; /* The default inner vlan tag to insert */ 578 u16 default_tag2; /* The default outer vlan tag to insert */ 579 }; 580 581 /* VPort level vlan tag configuration for RX direction */ 582 struct hclge_rx_vtag_cfg { 583 bool strip_tag1_en; /* Whether strip inner vlan tag */ 584 bool strip_tag2_en; /* Whether strip outer vlan tag */ 585 bool vlan1_vlan_prionly;/* Inner VLAN Tag up to descriptor Enable */ 586 bool vlan2_vlan_prionly;/* Outer VLAN Tag up to descriptor Enable */ 587 }; 588 589 struct hclge_rss_tuple_cfg { 590 u8 ipv4_tcp_en; 591 u8 ipv4_udp_en; 592 u8 ipv4_sctp_en; 593 u8 ipv4_fragment_en; 594 u8 ipv6_tcp_en; 595 u8 ipv6_udp_en; 596 u8 ipv6_sctp_en; 597 u8 ipv6_fragment_en; 598 }; 599 600 struct hclge_vport { 601 u16 alloc_tqps; /* Allocated Tx/Rx queues */ 602 603 u8 rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */ 604 /* User configured lookup table entries */ 605 u8 rss_indirection_tbl[HCLGE_RSS_IND_TBL_SIZE]; 606 int rss_algo; /* User configured hash algorithm */ 607 /* User configured rss tuple sets */ 608 struct hclge_rss_tuple_cfg rss_tuple_sets; 609 610 u16 alloc_rss_size; 611 612 u16 qs_offset; 613 u16 bw_limit; /* VSI BW Limit (0 = disabled) */ 614 u8 dwrr; 615 616 struct hclge_tx_vtag_cfg txvlan_cfg; 617 struct hclge_rx_vtag_cfg rxvlan_cfg; 618 619 int vport_id; 620 struct hclge_dev *back; /* Back reference to associated dev */ 621 struct hnae3_handle nic; 622 struct hnae3_handle roce; 623 }; 624 625 void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc, 626 bool en_mc, bool en_bc, int vport_id); 627 628 int hclge_add_uc_addr_common(struct hclge_vport *vport, 629 const unsigned char *addr); 630 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 631 const unsigned char *addr); 632 int hclge_add_mc_addr_common(struct hclge_vport *vport, 633 const unsigned char *addr); 634 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 635 const unsigned char *addr); 636 637 int hclge_cfg_func_mta_filter(struct hclge_dev *hdev, 638 u8 func_id, 639 bool enable); 640 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle); 641 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 642 int vector_id, bool en, 643 struct hnae3_ring_chain_node *ring_chain); 644 645 static inline int hclge_get_queue_id(struct hnae3_queue *queue) 646 { 647 struct hclge_tqp *tqp = container_of(queue, struct hclge_tqp, q); 648 649 return tqp->index; 650 } 651 652 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex); 653 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 654 u16 vlan_id, bool is_kill); 655 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable); 656 657 int hclge_buffer_alloc(struct hclge_dev *hdev); 658 int hclge_rss_init_hw(struct hclge_dev *hdev); 659 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev); 660 661 void hclge_mbx_handler(struct hclge_dev *hdev); 662 void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id); 663 void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id); 664 int hclge_cfg_flowctrl(struct hclge_dev *hdev); 665 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id); 666 #endif 667